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cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/wasca_rst_controller.vhd | 1 | 9,055 | -- wasca_rst_controller.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller;
architecture rtl of wasca_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller
| gpl-2.0 | 408f6de320e55805998e3f88aac2b37f | 0.545997 | 2.731523 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/outpad.vhd | 2 | 4,148 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad
-- File: outpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end;
architecture rtl of outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i after 2 ns when slew = 0 else i;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
x0 : axcel_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
um : if (tech = umc) generate
x0 : umc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength) port map (padx, i, gnd, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of outpadv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad generic map (tech, level, slew, voltage, strength)
port map (pad(j), i(j));
end generate;
end;
| mit | a29a76b7d698b4fc2a0b407546a2b291 | 0.637898 | 3.629046 | false | false | false | false |
franz/pocl | examples/accel/rtl/vhdl/rf_1wr_1rd_always_1_guarded_0.vhd | 2 | 6,851 | -- Copyright (c) 2002-2009 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-- Title : File for TTA
-- Project : FlexDSP
-------------------------------------------------------------------------------
--
-- VHDL Entity of Guarded_RF.rf_1wr_1rd_always_1.symbol
--
-- Created: 13:42:41 02/14/06
-- by - tpitkane.tpitkane (elros)
-- at - 13:42:41 02/14/06
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2004.1 (Build 41)
---------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 02/14/06 1.0 tpitkane Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--LIBRARY work;
--USE work.util.all;
use work.util.all;
ENTITY rf_1wr_1rd_always_1_guarded_0 IS
GENERIC(
dataw : integer := 32;
rf_size : integer := 8
);
PORT(
clk : IN std_logic;
glock : IN std_logic;
r1load : IN std_logic;
r1opcode : IN std_logic_vector ( bit_width(rf_size)-1 DOWNTO 0 );
rstx : IN std_logic;
t1data : IN std_logic_vector (dataw-1 DOWNTO 0);
t1load : IN std_logic;
t1opcode : IN std_logic_vector ( bit_width(rf_size)-1 DOWNTO 0 );
r1data : OUT std_logic_vector (dataw-1 DOWNTO 0);
guard : OUT std_logic_vector (rf_size-1 DOWNTO 0)
);
-- Declarations
END rf_1wr_1rd_always_1_guarded_0 ;
---------------------------------------------------------------------------------
-- Title : File for TTA
-- Project : FlexDSP
-------------------------------------------------------------------------------
--
-- VHDL Architecture Guarded_RF.rf_1wr_1rd_always_1.rtl
--
-- Created: 13:42:41 02/14/06
-- by - tpitkane.tpitkane (elros)
-- at - 13:42:41 02/14/06
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2004.1 (Build 41)
---------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 02/14/06 1.0 tpitkane Created
---------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE rtl OF rf_1wr_1rd_always_1_guarded_0 IS
-- Architecture declarations
type reg_type is array (natural range <>) of std_logic_vector(dataw-1 downto 0 );
subtype rf_index is integer range 0 to rf_size-1;
signal reg : reg_type (rf_size-1 downto 0);
--signal temp : std_logic_vector(0 downto 0);
BEGIN
-----------------------------------------------------------------
input : PROCESS (clk, rstx)
-----------------------------------------------------------------
-- Process declarations
variable opc : integer;
variable idx : integer;
BEGIN
-- Asynchronous Reset
IF (rstx = '0') THEN
-- Reset Actions
idx := rf_size-1;
for idx in rf_size-1 downto 0 loop
reg(idx) <= (others => '0');
end loop; -- idx
ELSIF (clk'EVENT AND clk = '1') THEN
IF glock = '0' THEN
IF t1load = '1' THEN
opc := conv_integer(unsigned(t1opcode));
reg(opc) <= t1data;
END IF;
END IF;
END IF;
END PROCESS input;
-----------------------------------------------------------------
--output : PROCESS (glock, r1load, r1opcode, reg, rstx)
-----------------------------------------------------------------
r1data <= reg(conv_integer(unsigned(r1opcode)));
-----------------------------------------------------------------
guard_out : PROCESS (reg,t1load,t1opcode,t1data)
-----------------------------------------------------------------
-- Process declarations
variable guard_var : std_logic_vector(0 downto 0);
BEGIN
for i in rf_size-1 downto 0 loop
if dataw > 1 then
if t1load = '1' then
if i = conv_integer(unsigned(t1opcode)) then
guard_var :=
t1data(dataw-1 downto dataw-1)
or t1data(dataw-2 downto dataw-2);
for j in dataw-2 downto 0 loop
guard_var := t1data(j downto j)
or guard_var;
end loop;
else
guard_var :=
reg(i)(dataw-1 downto dataw-1)
or reg(i)(dataw-2 downto dataw-2);
for j in dataw-2 downto 0 loop
guard_var := reg(i)(j downto j)
or guard_var;
end loop;
end if;
else
guard_var :=
reg(i)(dataw-1 downto dataw-1)
or reg(i)(dataw-2 downto dataw-2);
for j in dataw-2 downto 0 loop
guard_var := reg(i)(j downto j)
or guard_var;
end loop;
end if;
-- temp <= reg(i)(1 downto 1)
-- or reg(i)(0 downto 0);
else
if t1load = '1' then
if i = conv_integer(unsigned(t1opcode)) then
guard_var(0 downto 0) := t1data(0 downto 0);
else
guard_var(0 downto 0) := reg(i)(0 downto 0);
end if;
else
guard_var(0 downto 0) := reg(i)(0 downto 0);
end if;
end if;
--temp <= reg(i)(1 downto 1)
-- or reg(i)(0 downto 0);
guard(i downto i) <= guard_var(0 downto 0);
end loop;
END PROCESS guard_out;
END rtl;
| mit | dcbada67402e1ff4f5c416de3625af70 | 0.488542 | 4.129596 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/Ascon_block_control.vhd | 1 | 6,626 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_control is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : out std_logic; -- biggest round is 12
sel1,sel2,sel3,sel4 : out std_logic_vector(1 downto 0);
sel0 : out std_logic_vector(2 downto 0);
selout : out std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : out std_logic;
ActivateGen : out std_logic;
GenSize : out std_logic_vector(2 downto 0);
-- External control signals
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(2 downto 0); -- only matters for last block decryption
Busy : out std_logic
);
end entity Ascon_StateUpdate_control;
architecture structural of Ascon_StateUpdate_control is
begin
-----------------------------------------
------ The Finite state machine --------
-----------------------------------------
-- Modes: initialization, associative data, encryption, decryption, tag generation, final encryption, final decryption, seperation constant
-- 0010 0000 0110 0100 0001 0111 0101, 0011
-- case1 1000, case2 1001
fsm: process(Clk, Reset) is
type state_type is (IDLE,LOADNEW,CRYPT,TAG);
variable CurrState : state_type := IDLE;
variable RoundNrVar : std_logic_vector(1 downto 0);
begin
if Clk'event and Clk = '1' then
-- default values
sel0 <= "000";
sel1 <= "00";
sel2 <= "00";
sel3 <= "00";
sel4 <= "00";
selout <= '0';
Reg0En <= '0';
Reg1En <= '0';
Reg2En <= '0';
Reg3En <= '0';
Reg4En <= '0';
RegOutEn <= '0';
ActivateGen <= '0';
GenSize <= "000";
Busy <= '0';
if Reset = '1' then -- synchronous reset active high
-- registers used by fsm:
RoundNrVar := "00";
CurrState := IDLE;
else
FSMlogic : case CurrState is
when IDLE =>
if Start = '1' then
Busy <= '1';
if Mode = "0000" then -- AD mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Xor with DataIn)
sel0 <= "010";
Reg0En <= '1';
CurrState := CRYPT;
elsif Mode = "0100" then -- Decryption mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0110" then -- Encryption
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0001" then -- Tag mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (XOR middle with key)
sel1 <= "10";
sel2 <= "11";
Reg1En <= '1';
Reg2En <= '1';
CurrState := TAG;
elsif Mode = "0111" then -- Last block encryption
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0101" then -- Last block decryption
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
GenSize <= Size;
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0011" then -- Seperation constant
sel4 <= "11";
Reg4En <= '1';
CurrState := IDLE;
elsif Mode = "0010" then -- Initialization mode
RoundNrVar := "11"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Load in key and IV)
sel0 <= "001";
sel1 <= "01";
sel2 <= "01";
sel3 <= "01";
sel4 <= "01";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
elsif Mode = "1000" then -- case1
sel0 <= "100";
Reg0En <= '1';
CurrState := IDLE;
else -- case2
sel0 <= "100";
Reg0En <= '1';
RoundNrVar := "11"; -- so starts at 0 next cycle
CurrState := CRYPT;
end if;
else
Busy <= '0';
CurrState := IDLE;
end if;
when LOADNEW =>
if RoundNrVar = "01" then -- first foesn't play a role, it's just to keep track in this if function
-- set Sel and Enables signal (Xor at the end)
sel3 <= "10";
sel4 <= "10";
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
Busy <= '1';
end if;
when CRYPT =>
RoundNrVar := "00";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
when TAG =>
if RoundNrVar = "01" then
-- set Sel and Enables signal (connect tag to output)
selout <= '1';
RegOutEn <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := TAG;
Busy <= '1';
end if;
end case FSMlogic;
RoundNr <= RoundNrVar(0);
end if;
end if;
end process fsm;
end architecture structural;
| gpl-3.0 | 2852a16eeca36f1ff4e06aefcf315902 | 0.539541 | 3.235352 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/axcelerator/buffer_axcelerator.vhd | 2 | 2,268 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkbuf_actel
-- File: clkbuf_actel.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock buffer generator for Actel devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library axcelerator;
use axcelerator.hclkint;
use axcelerator.clkint;
-- pragma translate_on
entity clkbuf_actel is
generic(
buftype : integer range 0 to 3 := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkbuf_actel is
signal o2, no2, nin : std_ulogic;
component hclkint port(a : in std_ulogic; y : out std_ulogic); end component;
component clkint port(a : in std_ulogic; y : out std_ulogic); end component;
attribute syn_maxfan : integer;
attribute syn_maxfan of o2 : signal is 10000;
begin
o <= o2;
buf0 : if buftype = 0 generate
o2 <= i;
end generate;
buf1 : if buftype = 1 generate
buf : hclkint port map(A => i, Y => o2);
end generate;
buf2 : if buftype = 2 generate
buf : clkint port map(A => i, Y => o2);
end generate;
buf3 : if buftype > 2 generate
nin <= not i;
buf : clkint port map(A => nin, Y => no2);
o2 <= not no2;
end generate;
end architecture;
| mit | afd5c79ebaf1894988831078b9b3785e | 0.616843 | 3.978947 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/libproc3.vhd | 1 | 6,153 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libproc3
-- File: libproc3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 proc3 component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libcache.all;
use gaisler.libiu.all;
--library fpu;
--use fpu.libfpu.all;
package libproc3 is
component proc3
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end component;
component grfpwx
generic (fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
mul : integer range 0 to 2 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component mfpwx
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component grlfpwx
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
end;
| mit | b5d88244fc2f4f810d461b08978e57c6 | 0.516171 | 3.673433 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_iterated/Kernel/FullDiffLayer.vhd | 1 | 2,094 | -------------------------------------------------------------------------------
--! @project Iterated hardware implementation of Asconv12864
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FullDiffusionLayer is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity FullDiffusionLayer;
architecture structural of FullDiffusionLayer is
begin
Diff0: entity work.DiffusionLayer
generic map(SHIFT1 => 19,SHIFT2 => 28)
port map(X0In,X0Out);
Diff1: entity work.DiffusionLayer
generic map(SHIFT1 => 61,SHIFT2 => 39)
port map(X1In,X1Out);
Diff2: entity work.DiffusionLayer
generic map(SHIFT1 => 1,SHIFT2 => 6)
port map(X2In,X2Out);
Diff3: entity work.DiffusionLayer
generic map(SHIFT1 => 10,SHIFT2 => 17)
port map(X3In,X3Out);
Diff4: entity work.DiffusionLayer
generic map(SHIFT1 => 7,SHIFT2 => 41)
port map(X4In,X4Out);
end architecture structural;
| gpl-3.0 | cd169c8371bd9fec4e59ade9ff98062a | 0.628462 | 3.3504 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcilib.vhd | 2 | 4,563 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcilib
-- File: pcilib.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Description: Package with type declarations for PCI registers & constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
package pcilib is
constant zero : std_logic_vector(31 downto 0) := (others => '0');
constant addzero : std_logic_vector(31 downto 0) := (others => '0');
subtype word4 is std_logic_vector(3 downto 0);
subtype word32 is std_logic_vector(31 downto 0);
-- Constants for PCI commands
constant pci_memory_read : word4 := "0110";
constant pci_memory_write : word4 := "0111";
constant pci_config_read : word4 := "1010";
constant pci_config_write : word4 := "1011";
constant INT_ACK : word4 := "0000";
constant SPEC_CYCLE : word4 := "0001";
constant IO_READ : word4 := "0010";
constant IO_WRITE : word4 := "0011";
constant MEM_READ : word4 := "0110";
constant MEM_WRITE : word4 := "0111";
constant CONF_READ : word4 := "1010";
constant CONF_WRITE : word4 := "1011";
constant MEM_R_MULT : word4 := "1100";
constant DAC : word4 := "1101";
constant MEM_R_LINE : word4 := "1110";
constant MEM_W_INV : word4 := "1111";
-- Constants for word size
constant W_SIZE_8_n : word4 := "1110"; -- word size active low
constant W_SIZE_16_n : word4 := "1100";
constant W_SIZE_32_n : word4 := "0000";
type pci_config_command_type is record
-- ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
-- spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
-- vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
-- wcc : std_logic; -- Address stepping enable
-- serre : std_logic; -- Enable SERR# driver
-- fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
-- c66mhz : std_logic; -- 66MHz capability
-- udf : std_logic; -- UDF supported
-- fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
-- dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
-- sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
--type pci_config_type is record
-- conf_en : std_logic;
-- bus : std_logic_vector(7 downto 0);
-- dev : std_logic_vector(4 downto 0);
-- func : std_logic_vector(2 downto 0);
-- reg : std_logic_vector(5 downto 0);
-- data : std_logic_vector(31 downto 0);
--end record;
type pci_sigs_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic; -- Master frame
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
perr : std_logic; -- Parity Error
oe_par : std_logic;
oe_ad : std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
oe_perr : std_logic;
end record;
end ;
| mit | 4a0206d066121aa97216e0b6b7aaef3c | 0.614508 | 3.499233 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/work/debug/grtestmod.vhd | 1 | 4,683 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
use std.textio.all;
entity grtestmod is
generic (halt : integer := 0);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : in std_ulogic;
address : in std_logic_vector(21 downto 2);
data : inout std_logic_vector(31 downto 0);
iosn : in std_ulogic;
oen : in std_ulogic;
writen : in std_ulogic;
brdyn : out std_ulogic := '1'
);
end;
architecture sim of grtestmod is
subtype msgtype is string(1 to 40);
constant ntests : integer := 2;
type msgarr is array (0 to ntests) of msgtype;
constant msg : msgarr := (
"*** Starting GRLIB system test *** ", -- 0
"Test completed OK, halting simulation ", -- 1
"Test FAILED " -- 2
);
signal ior, iow : std_ulogic;
begin
ior <= iosn or oen;
iow <= iosn or writen;
data <= (others => 'Z');
log : process(ior, iow, clk)
variable errno, errcnt, subtest, vendorid, deviceid : integer;
variable addr : std_logic_vector(21 downto 2);
variable ldata : std_logic_vector(31 downto 0);
begin
if rising_edge(clk) then
addr := to_X01(address);
ldata := to_X01(data);
end if;
if falling_edge (ior) then
brdyn <= '1', '0' after 100 ns;
elsif rising_edge (ior) then
brdyn <= '1';
elsif falling_edge(iow) then
brdyn <= '1', '0' after 100 ns;
elsif rising_edge(iow) then
brdyn <= '1';
-- addr := to_X01(address);
case addr(7 downto 2) is
when "000000" =>
vendorid := conv_integer(ldata(31 downto 24));
deviceid := conv_integer(ldata(23 downto 12));
print(iptable(vendorid).device_table(deviceid));
when "000001" =>
errno := conv_integer(ldata(15 downto 0));
if (halt = 0) then
assert false
report "test failed, error (" & tost(errno) & ")"
severity failure;
else
assert false
report "test failed, error (" & tost(errno) & ")"
severity warning;
end if;
when "000010" =>
subtest := conv_integer(ldata(7 downto 0));
if vendorid = VENDOR_GAISLER then
case deviceid is
when GAISLER_LEON3 => leon3_subtest(subtest);
when GAISLER_FTMCTRL => mctrl_subtest(subtest);
when GAISLER_GPTIMER => gptimer_subtest(subtest);
when GAISLER_LEON3DSU => dsu3_subtest(subtest);
when GAISLER_SPW => spw_subtest(subtest);
when GAISLER_SPICTRL => spictrl_subtest(subtest);
when GAISLER_I2CMST => i2cmst_subtest(subtest);
when GAISLER_UHCI => uhc_subtest(subtest);
when GAISLER_EHCI => ehc_subtest(subtest);
when others =>
print (" subtest " & tost(subtest));
end case;
elsif vendorid = VENDOR_ESA then
case deviceid is
when ESA_LEON2 => leon3_subtest(subtest);
when ESA_MCTRL => mctrl_subtest(subtest);
when ESA_TIMER => gptimer_subtest(subtest);
when others =>
print ("subtest " & tost(subtest));
end case;
else
print ("subtest " & tost(subtest));
end if;
when "000100" =>
print ("");
print ("**** GRLIB system test starting ****");
errcnt := 0;
when "000101" =>
if errcnt = 0 then
print ("Test passed, halting with IU error mode");
elsif errcnt = 1 then
print ("1 error detected, halting with IU error mode");
else
print (tost(errcnt) & " errors detected, halting with IU error mode");
end if;
print ("");
when others =>
end case;
end if;
end process;
end;
-- pragma translate_on
| mit | 25dbf1f490dcdd16939b84b66c5881ea | 0.604313 | 3.807317 | false | true | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Card_Buffer.vhd | 7 | 13,242 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a dual port memory block. It has a 16-bit port and a 1-bit port.
-- The 1-bit port is used to either send or receive data, while the 16-bit port is used
-- by Avalon interconnet to store and retrieve data.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Buffer is
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_Buffer is
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Card_Memory_Block
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_REQUEST, s_SEND_START_BIT, s_SEND_DATA, s_SEND_CRC, s_SEND_STOP, s_WAIT_BUSY, s_WAIT_BUSY_END,
s_WAIT_DATA_START, s_RECEIVING_LEADING_BITS, s_RECEIVING_DATA, s_RECEIVING_STOP_BIT, s_WAIT_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal crc_counter : std_logic_vector(3 downto 0);
signal local_mode : std_logic;
signal dataout_1bit : std_logic;
signal bit_counter : std_logic_vector(2 downto 0);
signal byte_counter : std_logic_vector(8 downto 0);
signal shift_register : std_logic_vector(16 downto 0);
signal timeout_register : std_logic_vector(15 downto 0);
signal data_in_reg : std_logic;
-- UNREGISTERED
signal crc_out : std_logic_vector(15 downto 0);
signal single_bit_conversion, single_bit_out : std_logic_vector( 0 downto 0);
signal packet_mem_addr_b : std_logic_vector(11 downto 0);
signal local_reset, to_crc_generator, from_crc_generator, from_mem_1_bit, shift_crc,
recv_data, crc_generator_enable : std_logic;
begin
-- State transitions
state_transitions: process( current_state, i_begin, i_sd_clock_pulse_trigger, i_transmit, byte_counter,
bit_counter, crc_counter, i_1bit_data_in, timeout_register, data_in_reg)
begin
case (current_state) is
when s_RESET =>
-- Reset local registers and begin waiting for user input.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for i_begin to be high
if ((i_begin = '1') and (i_sd_clock_pulse_trigger = '1')) then
if (i_transmit = '1') then
next_state <= s_SEND_START_BIT;
else
next_state <= s_WAIT_DATA_START;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_SEND_START_BIT =>
-- Send a 0 first, followed by 4096 bits of data, 16 CRC bits, and stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_SEND_DATA;
else
next_state <= s_SEND_START_BIT;
end if;
when s_SEND_DATA =>
-- Send 4096 data bits
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_SEND_CRC;
else
next_state <= s_SEND_DATA;
end if;
when s_SEND_CRC =>
-- Send 16 CRC bits
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_SEND_STOP;
else
next_state <= s_SEND_CRC;
end if;
when s_SEND_STOP =>
-- Send stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_SEND_STOP;
end if;
when s_WAIT_BUSY =>
-- After a write, wait for the busy signal. Do not return a done signal until you receive a busy signal.
-- If you do not and a long time expires, then the data must have been rejected (due to CRC error maybe).
-- In such a case return failure.
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0') and (timeout_register = "0000000000010000")) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_register = BUSY_WAIT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if (i_sd_clock_pulse_trigger = '1') then
if (data_in_reg = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_DATA_START =>
-- Wait for the start bit
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0')) then
next_state <= s_RECEIVING_LEADING_BITS;
else
if (timeout_register = TIMEOUT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_DATA_START;
end if;
end if;
when s_RECEIVING_LEADING_BITS =>
-- shift the start bit in as well as the next 16 bits. Once they are all in you can start putting data into memory.
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_RECEIVING_DATA;
else
next_state <= s_RECEIVING_LEADING_BITS;
end if;
when s_RECEIVING_DATA =>
-- Wait until all bits arrive.
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_RECEIVING_STOP_BIT;
else
next_state <= s_RECEIVING_DATA;
end if;
when s_RECEIVING_STOP_BIT =>
-- Wait until all bits arrive.
if (i_sd_clock_pulse_trigger = '1')then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_RECEIVING_STOP_BIT;
end if;
when s_WAIT_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_REQUEST;
end if;
when others =>
next_state <= s_RESET;
end case;
end process;
-- State registers
state_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- FSM outputs
to_crc_generator <= shift_register(16) when (current_state = s_RECEIVING_DATA) else
from_mem_1_bit when (current_state = s_SEND_DATA) else
'0';
shift_crc <= '1' when (current_state = s_SEND_CRC) else '0';
local_reset <= '1' when ((current_state = s_RESET) or (current_state = s_WAIT_REQUEST)) else '0';
recv_data <= '1' when (current_state = s_RECEIVING_DATA) else '0';
single_bit_conversion(0) <= shift_register(15);
crc_generator_enable <= '0' when (current_state = s_WAIT_DEASSERT) else i_sd_clock_pulse_trigger;
o_operation_complete <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_dat_direction <= '1' when ( (current_state = s_SEND_START_BIT) or
(current_state = s_SEND_DATA) or
(current_state = s_SEND_CRC) or
(current_state = s_SEND_STOP))
else '0';
o_1bit_data_out <= dataout_1bit;
o_crc_passed <= '1' when ((crc_out = shift_register(16 downto 1)) and (shift_register(0) = '1')) else '0';
o_timed_out <= '1' when (timeout_register = TIMEOUT) else '0';
-- Local components
local_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
-- counters and serial output
if (local_reset = '1') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
data_in_reg <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
if ((not (current_state = s_RECEIVING_LEADING_BITS)) and (not (current_state = s_SEND_CRC))) then
crc_counter <= (OTHERS => '0');
else
if (not (crc_counter = "1111")) then
crc_counter <= crc_counter + '1';
end if;
end if;
if ((current_state = s_RECEIVING_DATA) or (current_state = s_SEND_DATA)) then
if (not ((bit_counter = "000") and (byte_counter = "111111111"))) then
if (bit_counter = "000") then
byte_counter <= byte_counter + '1';
bit_counter <= "111";
else
bit_counter <= bit_counter - '1';
end if;
end if;
end if;
-- Output data bit.
if (current_state = s_SEND_START_BIT) then
dataout_1bit <= '0';
elsif (current_state = s_SEND_DATA) then
dataout_1bit <= from_mem_1_bit;
elsif (current_state = s_SEND_CRC) then
dataout_1bit <= from_crc_generator;
else
dataout_1bit <= '1'; -- Stop bit.
end if;
-- Shift register to store the CRC bits once the message is received.
if ((current_state = s_RECEIVING_DATA) or
(current_state = s_RECEIVING_LEADING_BITS) or
(current_state = s_RECEIVING_STOP_BIT)) then
shift_register(16 downto 1) <= shift_register(15 downto 0);
shift_register(0) <= data_in_reg;
end if;
data_in_reg <= i_1bit_data_in;
end if;
end if;
end process;
-- Register holding the timeout value for data transmission.
timeout_reg: process(i_clock, i_reset_n, current_state, i_sd_clock_pulse_trigger)
begin
if (i_reset_n = '0') then
timeout_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_SEND_STOP) or
(current_state = s_WAIT_REQUEST)) then
timeout_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
-- Increment the timeout counter
if (((current_state = s_WAIT_DATA_START) or
(current_state = s_WAIT_BUSY)) and (not (timeout_register = TIMEOUT))) then
timeout_register <= timeout_register + '1';
end if;
end if;
end if;
end process;
-- Instantiated components.
crc16_checker: Altera_UP_SD_CRC16_Generator
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_sync_reset => local_reset,
i_enable => crc_generator_enable,
i_shift => shift_crc,
i_datain => to_crc_generator,
o_dataout => from_crc_generator,
o_crcout => crc_out
);
packet_memory: Altera_UP_SD_Card_Memory_Block
PORT MAP
(
address_a => i_address_16bit_port,
address_b => packet_mem_addr_b,
clock_a => i_clock,
clock_b => i_clock,
data_a => i_16bit_data_in,
data_b => single_bit_conversion,
enable_a => i_enable_16bit_port,
enable_b => '1',
wren_a => i_write_16bit,
wren_b => recv_data,
q_a => o_16bit_data_out,
q_b => single_bit_out
);
from_mem_1_bit <= single_bit_out(0);
packet_mem_addr_b <= (byte_counter & bit_counter);
end rtl;
| gpl-2.0 | b5a56513d2e14308189c027fab544053 | 0.618336 | 2.879948 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/amba/dma2ahb_pkg.vhd | 2 | 6,002 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB_Package (package declaration)
--
-- File name : dma2ahb_pkg.vhd
--
-- Purpose : Interface package for AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : See DMA2AHB VHDL core
--
-- Library : gaisler
--
-- Authors : Mr Sandi Habinc
-- Gaisler Research AB
-- Forsta Langgantan 19
-- SE-413 27 Göteborg
-- Sweden
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
-- Support for record types
-- 1.5 SH 1 Sep 2005 New library gaisler
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.7 SH 6 Dec 2007 Added syncrst generic
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package DMA2AHB_Package is
-----------------------------------------------------------------------------
-- Direct Memory Access to AMBA AHB Master Interface Types
-----------------------------------------------------------------------------
type DMA_In_Type is record
Reset: Std_Logic;
Address: Std_Logic_Vector(32-1 downto 0);
Data: Std_Logic_Vector(32-1 downto 0);
Request: Std_Logic; -- access requested
Burst: Std_Logic; -- burst requested
Beat: Std_Logic_Vector(1 downto 0); -- incrementing beat
Size: Std_Logic_Vector(1 downto 0); -- size
Store: Std_Logic; -- data write requested
end record;
type DMA_Out_Type is record
Grant: Std_Logic; -- access accepted
OKAY: Std_Logic; -- write access ready
Ready: Std_Logic; -- read data ready
Retry: Std_Logic; -- retry
Fault: Std_Logic; -- error occured
Data: Std_Logic_Vector(32-1 downto 0);
end record;
-- constants for HBURST definition (used with dma_in_type.Beat)
constant HINCR: Std_Logic_Vector(1 downto 0) := "00";
constant HINCR4: Std_Logic_Vector(1 downto 0) := "01";
constant HINCR8: Std_Logic_Vector(1 downto 0) := "10";
constant HINCR16: Std_Logic_Vector(1 downto 0) := "11";
-- constants for HSIZE definition (used with dma_in_type.Size)
constant HSIZE8: Std_Logic_Vector(1 downto 0) := "00";
constant HSIZE16: Std_Logic_Vector(1 downto 0) := "01";
constant HSIZE32: Std_Logic_Vector(1 downto 0) := "10";
-----------------------------------------------------------------------------
-- Direct Memory Access to AMBA AHB Master Interface
-----------------------------------------------------------------------------
component DMA2AHB is
generic(
hindex: in Integer := 0;
vendorid: in Integer := 0;
deviceid: in Integer := 0;
version: in Integer := 0;
syncrst: in Integer := 1;
boundary: in Integer := 1);
port(
-- AMBA AHB system signals
HCLK: in Std_ULogic;
HRESETn: in Std_ULogic;
-- Direct Memory Access Interface
DMAIn: in DMA_In_Type;
DMAOut: out DMA_OUt_Type;
-- AMBA AHB Master Interface
AHBIn: in AHB_Mst_In_Type;
AHBOut: out AHB_Mst_Out_Type);
end component DMA2AHB;
end package DMA2AHB_Package; --===============================================--
| mit | 4d0bea32fccd5394aa4c695a54c8637d | 0.4995 | 4.678098 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/clkmux.vhd | 2 | 2,612 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkmux
-- File: clkmux.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Glitch-free clock multiplexer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkmux is
generic(tech : integer := 0;
rsel : integer range 0 to 1 := 0); -- registered sel
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic;
rst : in std_ulogic := '1'
);
end entity;
architecture rtl of clkmux is
signal seli, sel0, sel1, cg0, cg1 : std_ulogic;
begin
rs : if rsel = 1 generate
rsproc : process(i0)
begin
if rising_edge(i0) then seli <= sel; end if;
end process;
end generate;
cs : if rsel = 0 generate seli <= sel; end generate;
xil : if (tech = virtex2) or (tech = spartan3) or (tech = spartan3e)
or (tech = virtex4) or (tech = virtex5) generate
buf : clkmux_unisim port map(sel => seli, I0 => i0, I1 => i1, O => o);
end generate;
gen : if has_clkmux(tech) = 0 generate
p0 : process(i0, rst)
begin
if rst = '0' then
sel0 <= '1';
elsif falling_edge(i0) then
sel0 <= (not seli) and (not sel1);
end if;
end process;
p1 : process(i1, rst)
begin
if rst = '0' then
sel1 <= '0';
elsif falling_edge(i1) then
sel1 <= seli and (not sel0);
end if;
end process;
cg0 <= i0 and sel0;
cg1 <= i1 and sel1;
o <= cg0 or cg1;
end generate;
end architecture;
| mit | c232f9b302389d22f6072bd6236d708a | 0.569678 | 3.758273 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/inferred/mul_inferred.vhd | 2 | 2,183 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
| mit | 7595dbac7c35f88478547e480788b082 | 0.575813 | 3.84331 | false | false | false | false |
pcrost/gen-util | slv_util.vhd | 1 | 8,244 | -------------------------------------------------------------------------------
-- (C) P. Crosthwaite, University of Queensland (2011)
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library gen_util;
use gen_util.util.all;
package slv_util is
--find the minimum unsigned std_logic_vector length to represent the number A
function util_length_req (A : integer) return integer;
--zero extend a std_logic_vector to a specified width
function util_zero_ext_slv(a : std_logic_vector; width : integer) return std_logic_vector;
function util_zero_ext_slv(a : std_logic; width : integer) return std_logic_vector;
--sign extend a std_logic_vector to a specified width
function util_sign_ext_slv(a : std_logic_vector; width : integer) return std_logic_vector;
function util_sign_ext_slv(a : std_logic; width : integer) return std_logic_vector;
--return an std_logic_vector of all ones, all zeros or all don't-cares
function util_ones(w : integer) return std_logic_vector;
function util_zeros(w : integer) return std_logic_vector;
function util_dcs(w : integer) return std_logic_vector;
--determine if two std_logic vectors match subject to a set of don't cares
--The range of b must match or superset a.
--The range of dont_care must match or superset a.
function util_match_slv(
a : std_logic_vector;
b : std_logic_vector;
dont_care : std_logic_vector
) return boolean;
--count the number of ones in a std_logic vector
function count_ones (a : std_logic_vector) return integer;
--rebase a slv to be downto 0, rather than downto n where n is non-zero
function slv_dt0_slice (a : std_logic_vector) return std_logic_vector;
--do a don't care or function between two slvs
function util_dc_or_slv(a : std_logic_vector; b : std_logic_vector) return std_logic_vector;
--bit reverse a slv
function util_slv_reverse(a : std_logic_vector) return std_logic_vector;
--truncate a slv and assign it to another
procedure util_slv_trunc_assign(variable a : out std_logic_vector; constant b : in std_logic_vector);
procedure util_slv_trunc_assign(variable a : out std_logic; constant b : in std_logic_vector);
--conv_integer without simulation noise
function util_conv_integer_quiet(a : std_logic_vector) return integer;
--Signed Relational Adjustment. adjust a slv for use with relational operators when interpreting it as signed
function util_SRA(a : std_logic_vector) return std_logic_vector;
function util_signed_negative(a : std_logic_vector) return boolean;
function util_slv_ffs(a : std_logic_vector) return integer;
function util_slv_fls(a : std_logic_vector) return integer;
end slv_util;
package body slv_util is
function util_length_req (A : integer) return integer is
variable w : integer := A;
variable ret : integer := 0;
begin
while w /= 0 loop
ret := ret + 1;
w := w / 2;
end loop;
return ret;
end;
function util_zero_ext_slv(a : std_logic_vector; width : integer) return std_logic_vector is
begin
if (width = a'length) then
return a;
elsif (width > a'length) then
return conv_std_logic_vector(0, width - a'length) & a;
else
return a(width - 1 downto 0);
end if;
end;
function util_zero_ext_slv(a : std_logic; width : integer) return std_logic_vector is
variable aslv : std_logic_vector(0 downto 0) := (others => a);
begin
return util_zero_ext_slv(aslv, width);
end;
function util_sign_ext_slv(a : std_logic_vector; width : integer) return std_logic_vector is
variable ret : std_logic_vector(width-1 downto 0);
begin
if (width = a'length) then
return a;
else
ret(a'length-1 downto 0) := a;
ret(width-1 downto a'length) := (others => ret(a'length-1));
return ret;
end if;
end;
function util_sign_ext_slv(a : std_logic; width : integer) return std_logic_vector is
variable aslv : std_logic_vector(0 downto 0) := (others => a);
begin
return util_sign_ext_slv(aslv, width);
end;
function util_ones(w : integer) return std_logic_vector is
variable ret : std_logic_vector(w-1 downto 0);
begin
ret := (others => '1');
return ret;
end;
function util_zeros(w : integer) return std_logic_vector is
variable ret : std_logic_vector(w-1 downto 0);
begin
ret := (others => '0');
return ret;
end;
function util_dcs(w : integer) return std_logic_vector is
variable ret : std_logic_vector(w-1 downto 0);
begin
ret := (others => 'X');
return ret;
end;
function util_match_slv(
a : std_logic_vector;
b : std_logic_vector;
dont_care : std_logic_vector
) return boolean is
constant a0 : std_logic_vector(a'length-1 downto 0) := slv_dt0_slice(a);
constant b0 : std_logic_vector(a'length-1 downto 0) := slv_dt0_slice(b);
constant d0 : std_logic_vector(a'length-1 downto 0) := slv_dt0_slice(dont_care);
begin
for I in a'range loop
if (d0(I) = '0' and (a0(I) /= b0(I))) then
return false;
end if;
end loop;
return true;
end function;
function count_ones (a : std_logic_vector) return integer is
variable ret : integer range 0 to a'length := 0;
begin
for I in a'range loop
if (a(I) = '1') then ret := ret + 1; end if;
end loop;
return ret;
end function;
function slv_dt0_slice (a : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(a'length-1 downto 0);
begin
ret := a; return ret;
end;
function util_dc_or_slv(a : std_logic_vector; b : std_logic_vector) return std_logic_vector is
variable a_dt_0 : std_logic_vector(a'length-1 downto 0) := a;
variable b_dt_0 : std_logic_vector(b'length-1 downto 0) := b;
variable ret : std_logic_vector(a'length -1 downto 0);
begin
for I in a'range loop
ret(I) := util_dc_or(a_dt_0(I), b_dt_0(I));
end loop;
return ret;
end function;
function util_conv_integer_quiet(a : std_logic_vector) return integer is
variable bogus : boolean := false;
begin
for I in a'range loop
if (a(I) /= '1' and a(I) /= '0') then
bogus := true;
end if;
end loop;
if (bogus) then
return 0;
else
return conv_integer(a);
end if;
end function;
function util_slv_reverse(a : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(a'range);
begin
for i in a'range loop
ret(a'low + i) := a(a'high - i);
end loop;
return ret;
end;
procedure util_slv_trunc_assign(variable a : out std_logic_vector; constant b : in std_logic_vector) is
variable b_dt_0 : std_logic_vector (b'length-1 downto 0) := slv_dt0_slice(b);
begin
a := b_dt_0(a'length-1 downto 0);
end;
procedure util_slv_trunc_assign(variable a : out std_logic; constant b : in std_logic_vector) is
variable b_dt_0 : std_logic_vector (b'length-1 downto 0) := slv_dt0_slice(b);
begin
a := b_dt_0(0);
end;
function util_SRA(a : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(a'length-1 downto 0) := a;
begin
ret(ret'left) := not ret(ret'left);
return ret;
end;
function util_signed_negative(a : std_logic_vector) return boolean is begin
return (a(a'left) = '1');
end;
function util_slv_ffs(a: std_logic_vector) return integer is begin
for I in a'range loop
if (a(I) = '1') then
return I;
end if;
end loop;
return -1;
end;
function util_slv_fls(a: std_logic_vector) return integer is begin
for I in a'reverse_range loop
if (a(I) = '1') then
return I;
end if;
end loop;
return -1;
end;
end slv_util;
| lgpl-3.0 | de461aa7f9124ca14a6794a5c0eb1e54 | 0.671397 | 3.070391 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/unisim/ddr_unisim.vhd | 1 | 10,260 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: unisim_iddr_reg
-- File: unisim_iddr_reg.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: Xilinx DDR input register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.iddr;
--pragma translate_on
entity unisim_iddr_reg is
generic (tech : integer := virtex4);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of unisim_iddr_reg is
attribute BOX_TYPE : string;
-- attribute syn_useioff : boolean;
-- attribute syn_useioff of rtl : architecture is false;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
attribute BOX_TYPE of IDDR : component is "PRIMITIVE";
signal preQ2 : std_ulogic;
begin
-- SAME EDGE mode have when this is written an incorrect P&R
-- timing model, instead OPPOSITE_MODE with an extra register is used
-- V4 : if tech = virtex4 generate
-- U0 : IDDR
-- generic map(
-- DDR_CLK_EDGE => "SAME_EDGE",
-- INIT_Q1 => '0',
-- INIT_Q2 => '0',
-- SRTYPE => "ASYNC")
-- Port map(
-- Q1 => Q1,
-- Q2 => Q2,
-- C => C1,
-- CE => CE,
-- D => D,
-- R => R,
-- S => S);
-- end generate;
V4 : if (tech = virtex4) or (tech = virtex5) generate
U0 : IDDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE"
-- ,INIT_Q1 => '0',
-- INIT_Q2 => '0',
-- SRTYPE => "ASYNC"
)
Port map( Q1 => Q1, Q2 => preQ2, C => C1, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1, preQ2, R)
begin
if R='1' then --asynchronous reset, active high
Q2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
V2 : if tech = virtex2 or tech = spartan3 generate
-- CE and S inputs inactive for virtex 2
q1reg : process (C1, D, R)
begin
if R='1' then --asynchronous reset, active high
Q1 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q1 <= D;
end if;
end process;
q2reg : process (C1, D, R)
begin
if R='1' then --asynchronous reset, active high
preQ2 <= '0';
elsif C1'event and C1='0' then --Clock event - negedge
preQ2 <= D;
end if;
end process;
q3reg : process (C1, preQ2, R)
begin
if R='1' then --asynchronous reset, active high
Q2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
-- NOTE: You must include the following constraints in the .ucf
-- file when running back-end tools,
-- in order to ensure that IOB DDR registers are used:
-- -- INST "q2_reg" IOB=TRUE;
-- INST "q1_reg" IOB=TRUE;
-- -- Depending on the synthesis tools you use, it may be required to
-- check the edif file for modifications to
-- original net names...in this case, Synopsys changed the
-- names: q1 and q2 to q1_reg and q2_reg
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.oddr;
use unisim.FDDRRSE;
--pragma translate_on
entity unisim_oddr_reg is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of unisim_oddr_reg is
attribute BOX_TYPE : string;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
ODDR : component is "PRIMITIVE";
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
FDDRRSE : component is "PRIMITIVE";
signal preD2 : std_ulogic;
begin
-- SAME EDGE mode have when this is written an incorrect P&R
-- timing model, instead OPPOSITE_MODE with an extra register is used
-- V4 : if tech = virtex4 generate
-- U0 : ODDR
-- generic map(
-- DDR_CLK_EDGE => "SAME_EDGE",
-- INIT => '0',
-- SRTYPE => "ASYNC")
-- port map(
-- Q => Q,
-- C => C1,
-- CE => CE,
-- D1 => D1,
-- D2 => D2,
-- R => R,
-- S => S);
-- end generate;
V4 : if (tech = virtex4) or (tech = virtex5) generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
U0 : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE" -- ,INIT => '0'
, SRTYPE => "ASYNC")
port map(
Q => Q,
C => C1,
CE => CE,
D1 => D1,
D2 => preD2,
R => R,
S => S);
end generate;
V2 : if tech = virtex2 or tech = spartan3 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
c_dm : component FDDRRSE
-- generic map( INIT => '0')
port map(
Q => Q,
D0 => D1,
D1 => preD2,
C0 => C1,
C1 => C2,
CE => CE,
R => R,
S => S);
end generate;
end ;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
use unisim.FDDRRSE;
--pragma translate_on
entity oddrv2 is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of oddrv2 is
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component FDDRRSE
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preD2 : std_ulogic;
begin
rf : FD port map ( Q => preD2, C => C1, D => D2);
rr : FDDRRSE port map ( Q => Q, C0 => C1, C1 => C2,
CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
use unisim.oddr2;
--pragma translate_on
entity oddrc3e is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of oddrc3e is
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preD2 : std_ulogic;
begin
rf : FD port map ( Q => preD2, C => C1, D => D2);
rr : ODDR2 port map ( Q => Q, C0 => C1, C1 => C2,
CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
| mit | 870e18e13d42d14a3bbab5693503b914 | 0.527778 | 3.426854 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/resultPrivEscMux.vhd | 1 | 131,740 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY grlib;
USE grlib.sparc.all;
USE grlib.stdlib.all;
LIBRARY techmap;
USE techmap.gencomp.all;
LIBRARY gaisler;
USE gaisler.leon3.all;
USE gaisler.libiu.all;
USE gaisler.arith.all;
USE grlib.sparc_disas.all;
ENTITY iu3 IS
GENERIC (
nwin : integer RANGE 2 to 32 := 8;
isets : integer RANGE 1 to 4 := 2;
dsets : integer RANGE 1 to 4 := 2;
fpu : integer RANGE 0 to 15 := 0;
v8 : integer RANGE 0 to 63 := 2;
cp : integer RANGE 0 to 1 := 0;
mac : integer RANGE 0 to 1 := 0;
dsu : integer RANGE 0 to 1 := 1;
nwp : integer RANGE 0 to 4 := 2;
pclow : integer RANGE 0 to 2 := 2;
notag : integer RANGE 0 to 1 := 0;
index : integer RANGE 0 to 15 := 0;
lddel : integer RANGE 1 to 2 := 1;
irfwt : integer RANGE 0 to 1 := 1;
disas : integer RANGE 0 to 2 := 0;
tbuf : integer RANGE 0 to 64 := 2;
pwd : integer RANGE 0 to 2 := 0;
svt : integer RANGE 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer RANGE 0 to 15 := 0;
fabtech : integer RANGE 0 to NTECH := 2;
clk2x : integer := 0
);
PORT (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
END ENTITY;
ARCHITECTURE rtl OF iu3 IS
CONSTANT ISETMSB : integer := 0;
CONSTANT DSETMSB : integer := 0;
CONSTANT RFBITS : integer RANGE 6 to 10 := 4 + 4;
CONSTANT NWINLOG2 : integer RANGE 1 to 5 := 3;
CONSTANT CWPOPT : boolean := ( 8 = ( 2 ** 3 ) );
CONSTANT CWPMIN : std_logic_vector ( 3 - 1 downto 0 ) := ( OTHERS => '0' );
CONSTANT CWPMAX : std_logic_vector ( 3 - 1 downto 0 ) := conv_std_logic_vector ( 8 - 1 , 3 );
CONSTANT FPEN : boolean := ( 0 /= 0 );
CONSTANT CPEN : boolean := ( 0 = 1 );
CONSTANT MULEN : boolean := ( 2 /= 0 );
CONSTANT MULTYPE : integer := ( 2 / 16 );
CONSTANT DIVEN : boolean := ( 2 /= 0 );
CONSTANT MACEN : boolean := ( 0 = 1 );
CONSTANT MACPIPE : boolean := ( 0 = 1 ) and ( 2 / 2 = 1 );
CONSTANT IMPL : integer := 15;
CONSTANT VER : integer := 3;
CONSTANT DBGUNIT : boolean := ( 1 = 1 );
CONSTANT TRACEBUF : boolean := ( 2 /= 0 );
CONSTANT TBUFBITS : integer := 10 + 1 - 4;
CONSTANT PWRD1 : boolean := false;
CONSTANT PWRD2 : boolean := 0 /= 0;
CONSTANT RS1OPT : boolean := ( 1 /= 0 );
SUBTYPE word IS std_logic_vector ( 31 downto 0 );
SUBTYPE pctype IS std_logic_vector ( 31 downto 2 );
SUBTYPE rfatype IS std_logic_vector ( 7 downto 0 );
SUBTYPE cwptype IS std_logic_vector ( 3 - 1 downto 0 );
TYPE icdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dcdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dc_in_type IS RECORD
signed : std_ulogic;
enaddr : std_ulogic;
read : std_ulogic;
write : std_ulogic;
lock : std_ulogic;
dsuen : std_ulogic;
size : std_logic_vector ( 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE pipeline_ctrl_type IS RECORD
pc : pctype;
inst : word;
cnt : std_logic_vector ( 1 downto 0 );
rd : rfatype;
tt : std_logic_vector ( 5 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
END RECORD;
TYPE fetch_reg_type IS RECORD
pc : pctype;
branch : std_ulogic;
END RECORD;
TYPE decode_reg_type IS RECORD
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector ( 0 downto 0 );
mexc : std_ulogic;
cnt : std_logic_vector ( 1 downto 0 );
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
END RECORD;
TYPE regacc_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rsel1 : std_logic_vector ( 2 downto 0 );
rsel2 : std_logic_vector ( 2 downto 0 );
rfe1 : std_ulogic;
rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
END RECORD;
TYPE execute_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector ( 2 downto 0 );
alusel : std_logic_vector ( 1 downto 0 );
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1 : std_ulogic;
ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic;
shleft : std_ulogic;
ymsb : std_ulogic;
rd : std_logic_vector ( 4 downto 0 );
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
mulstep : std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
END RECORD;
TYPE memory_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
END RECORD;
TYPE exception_state IS ( run , trap , dsu1 , dsu2 );
TYPE exception_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector ( 0 downto 0 );
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector ( 1 downto 0 );
rstate : exception_state;
npc : std_logic_vector ( 2 downto 0 );
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
END RECORD;
TYPE dsu_registers IS RECORD
tt : std_logic_vector ( 7 downto 0 );
err : std_ulogic;
tbufcnt : std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
crdy : std_logic_vector ( 2 downto 1 );
END RECORD;
TYPE irestart_register IS RECORD
addr : pctype;
pwd : std_ulogic;
END RECORD;
TYPE pwd_register_type IS RECORD
pwd : std_ulogic;
error : std_ulogic;
END RECORD;
TYPE special_register_type IS RECORD
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
tt : std_logic_vector ( 7 downto 0 );
tba : std_logic_vector ( 19 downto 0 );
wim : std_logic_vector ( 8 - 1 downto 0 );
pil : std_logic_vector ( 3 downto 0 );
ec : std_ulogic;
ef : std_ulogic;
ps : std_ulogic;
s : std_ulogic;
et : std_ulogic;
y : word;
asr18 : word;
svt : std_ulogic;
dwt : std_ulogic;
END RECORD;
TYPE write_reg_type IS RECORD
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
END RECORD;
TYPE registers IS RECORD
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
END RECORD;
TYPE exception_type IS RECORD
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
END RECORD;
TYPE watchpoint_register IS RECORD
addr : std_logic_vector ( 31 downto 2 );
mask : std_logic_vector ( 31 downto 2 );
exec : std_ulogic;
load : std_ulogic;
store : std_ulogic;
END RECORD;
TYPE watchpoint_registers IS ARRAY ( 0 to 3 ) OF watchpoint_register;
CONSTANT wpr_none : watchpoint_register := ( "000000000000000000000000000000" , "000000000000000000000000000000" , '0' , '0' , '0' );
FUNCTION dbgexc (
r : registers;
dbgi : l3_debug_in_type;
trap : std_ulogic;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE dmode : std_ulogic;
BEGIN
dmode := '0';
IF ( not r.x.ctrl.annul and trap ) = '1' THEN
IF ( ( ( tt = "00" & TT_WATCH ) and ( dbgi.bwatch = '1' ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = "10000001" ) ) or ( dbgi.btrapa = '1' ) or ( ( dbgi.btrape = '1' ) and not ( ( tt ( 5 downto 0 ) = TT_PRIV ) or ( tt ( 5 downto 0 ) = TT_FPDIS ) or ( tt ( 5 downto 0 ) = TT_WINOF ) or ( tt ( 5 downto 0 ) = TT_WINUF ) or ( tt ( 5 downto 4 ) = "01" ) or ( tt ( 7 ) = '1' ) ) ) or ( ( ( not r.w.s.et ) and dbgi.berror ) = '1' ) ) THEN
dmode := '1';
END IF;
END IF;
RETURN ( dmode );
END;
FUNCTION dbgerr (
r : registers;
dbgi : l3_debug_in_type;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE err : std_ulogic;
BEGIN
err := not r.w.s.et;
IF ( ( ( dbgi.dbreak = '1' ) and ( tt = ( "00" & TT_WATCH ) ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = ( "10000001" ) ) ) ) THEN
err := '0';
END IF;
RETURN ( err );
END;
PROCEDURE diagwr (
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector ( 7 downto 0 );
pc : out pctype;
npc : out pctype;
tbufcnt : out std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
wr : out std_ulogic;
addr : out std_logic_vector ( 9 downto 0 );
data : out word;
fpcwr : out std_ulogic
) IS
VARIABLE i : integer RANGE 0 to 3;
BEGIN
s := r.w.s;
pc := r.f.pc;
npc := ir.addr;
wr := '0';
vwpr := wpr;
asi := dsur.asi;
addr := ( OTHERS => '0' );
data := dbg.ddata;
tbufcnt := dsur.tbufcnt;
fpcwr := '0';
IF ( dbg.dsuen and dbg.denable and dbg.dwrite ) = '1' THEN
CASE dbg.daddr ( 23 downto 20 ) IS
WHEN "0001" =>
IF dbg.daddr ( 16 ) = '1' THEN
tbufcnt := dbg.ddata ( 10 + 1 - 4 - 1 downto 0 );
END IF;
WHEN "0011" =>
IF dbg.daddr ( 12 ) = '0' THEN
wr := '1';
addr := ( OTHERS => '0' );
addr ( 7 downto 0 ) := dbg.daddr ( 9 downto 2 );
ELSE
fpcwr := '1';
END IF;
WHEN "0100" =>
CASE dbg.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
s.y := dbg.ddata;
WHEN "0001" =>
s.cwp := dbg.ddata ( 3 - 1 downto 0 );
s.icc := dbg.ddata ( 23 downto 20 );
s.ec := dbg.ddata ( 13 );
s.pil := dbg.ddata ( 11 downto 8 );
s.s := dbg.ddata ( 7 );
s.ps := dbg.ddata ( 6 );
s.et := dbg.ddata ( 5 );
WHEN "0010" =>
s.wim := dbg.ddata ( 8 - 1 downto 0 );
WHEN "0011" =>
s.tba := dbg.ddata ( 31 downto 12 );
s.tt := dbg.ddata ( 11 downto 4 );
WHEN "0100" =>
pc := dbg.ddata ( 31 downto 2 );
WHEN "0101" =>
npc := dbg.ddata ( 31 downto 2 );
WHEN "0110" =>
fpcwr := '1';
WHEN "0111" =>
NULL;
WHEN "1001" =>
asi := dbg.ddata ( 7 downto 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0001" =>
s.dwt := dbg.ddata ( 14 );
s.svt := dbg.ddata ( 13 );
WHEN "0010" =>
NULL;
WHEN "1000" =>
vwpr ( 0 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).exec := dbg.ddata ( 0 );
WHEN "1001" =>
vwpr ( 0 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).load := dbg.ddata ( 1 );
vwpr ( 0 ).store := dbg.ddata ( 0 );
WHEN "1010" =>
vwpr ( 1 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).exec := dbg.ddata ( 0 );
WHEN "1011" =>
vwpr ( 1 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).load := dbg.ddata ( 1 );
vwpr ( 1 ).store := dbg.ddata ( 0 );
WHEN "1100" =>
vwpr ( 2 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).exec := dbg.ddata ( 0 );
WHEN "1101" =>
vwpr ( 2 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).load := dbg.ddata ( 1 );
vwpr ( 2 ).store := dbg.ddata ( 0 );
WHEN "1110" =>
vwpr ( 3 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).exec := dbg.ddata ( 0 );
WHEN "1111" =>
vwpr ( 3 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).load := dbg.ddata ( 1 );
vwpr ( 3 ).store := dbg.ddata ( 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
FUNCTION asr17_gen (
r : in registers
) RETURN word IS
VARIABLE asr17 : word;
VARIABLE fpu2 : integer RANGE 0 to 3;
BEGIN
asr17 := "00000000000000000000000000000000";
asr17 ( 31 downto 28 ) := conv_std_logic_vector ( 0 , 4 );
asr17 ( 14 ) := r.w.s.dwt;
asr17 ( 13 ) := r.w.s.svt;
fpu2 := 0;
asr17 ( 11 downto 10 ) := conv_std_logic_vector ( fpu2 , 2 );
asr17 ( 8 ) := '1';
asr17 ( 7 downto 5 ) := conv_std_logic_vector ( 2 , 3 );
asr17 ( 4 downto 0 ) := conv_std_logic_vector ( 8 - 1 , 5 );
RETURN ( asr17 );
END;
PROCEDURE diagread (
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
rfdata : in std_logic_vector ( 31 downto 0 );
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word
) IS
VARIABLE cwp : std_logic_vector ( 4 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
data := ( OTHERS => '0' );
cwp := ( OTHERS => '0' );
cwp ( 3 - 1 downto 0 ) := r.w.s.cwp;
CASE dbgi.daddr ( 22 downto 20 ) IS
WHEN "001" =>
IF dbgi.daddr ( 16 ) = '1' THEN
data ( 10 + 1 - 4 - 1 downto 0 ) := dsur.tbufcnt;
ELSE
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
data := tbufo.data ( 127 downto 96 );
WHEN "01" =>
data := tbufo.data ( 95 downto 64 );
WHEN "10" =>
data := tbufo.data ( 63 downto 32 );
WHEN OTHERS =>
data := tbufo.data ( 31 downto 0 );
END CASE;
END IF;
WHEN "011" =>
IF dbgi.daddr ( 12 ) = '0' THEN
data := rfdata ( 31 downto 0 );
ELSE
data := fpo.dbg.data;
END IF;
WHEN "100" =>
CASE dbgi.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbgi.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
data := r.w.s.y;
WHEN "0001" =>
data := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
WHEN "0010" =>
data ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
WHEN "0100" =>
data ( 31 downto 2 ) := r.f.pc;
WHEN "0101" =>
data ( 31 downto 2 ) := ir.addr;
WHEN "0110" =>
data := fpo.dbg.data;
WHEN "0111" =>
NULL;
WHEN "1000" =>
data ( 12 downto 4 ) := dsur.err & dsur.tt;
WHEN "1001" =>
data ( 7 downto 0 ) := dsur.asi;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
IF dbgi.daddr ( 5 ) = '0' THEN
IF dbgi.daddr ( 4 downto 2 ) = "001" THEN
data := asr17_gen ( r );
END IF;
ELSE
i := conv_integer ( dbgi.daddr ( 4 downto 3 ) );
IF dbgi.daddr ( 2 ) = '0' THEN
data ( 31 downto 2 ) := wpr ( i ).addr;
data ( 0 ) := wpr ( i ).exec;
ELSE
data ( 31 downto 2 ) := wpr ( i ).mask;
data ( 1 ) := wpr ( i ).load;
data ( 0 ) := wpr ( i ).store;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "111" =>
data := r.x.data ( conv_integer ( r.x.set ) );
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE itrace (
r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
di : out tracebuf_in_type
) IS
VARIABLE meminst : std_ulogic;
BEGIN
di.addr := ( OTHERS => '0' );
di.data := ( OTHERS => '0' );
di.enable := '0';
di.write := ( OTHERS => '0' );
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst ( 31 ) and r.x.ctrl.inst ( 30 );
di.addr ( 10 + 1 - 4 - 1 downto 0 ) := dsur.tbufcnt;
di.data ( 127 ) := '0';
di.data ( 126 ) := not r.x.ctrl.pv;
di.data ( 125 downto 96 ) := dbgi.timer ( 29 downto 0 );
di.data ( 95 downto 64 ) := res;
di.data ( 63 downto 34 ) := r.x.ctrl.pc ( 31 downto 2 );
di.data ( 33 ) := trap;
di.data ( 32 ) := error;
di.data ( 31 downto 0 ) := r.x.ctrl.inst;
IF ( dbgi.tenable = '0' ) or ( r.x.rstate = dsu2 ) THEN
IF ( ( dbgi.dsuen and dbgi.denable ) = '1' ) and ( dbgi.daddr ( 23 downto 20 ) & dbgi.daddr ( 16 ) = "00010" ) THEN
di.enable := '1';
di.addr ( 10 + 1 - 4 - 1 downto 0 ) := dbgi.daddr ( 10 + 1 - 4 - 1 + 4 downto 4 );
IF dbgi.dwrite = '1' THEN
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
di.write ( 3 ) := '1';
WHEN "01" =>
di.write ( 2 ) := '1';
WHEN "10" =>
di.write ( 1 ) := '1';
WHEN OTHERS =>
di.write ( 0 ) := '1';
END CASE;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
END IF;
END IF;
ELSIF ( not r.x.ctrl.annul and ( r.x.ctrl.pv or meminst ) and not r.x.debug ) = '1' THEN
di.enable := '1';
di.write := ( OTHERS => '1' );
tbufcnt := dsur.tbufcnt + 1;
END IF;
di.diag := dco.testen & "000";
IF dco.scanen = '1' THEN
di.enable := '0';
END IF;
END;
PROCEDURE dbg_cache (
holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) IS
BEGIN
mresult2 := mresult;
dci2 := dci;
dci2.dsuen := '0';
IF r.x.rstate = dsu2 THEN
dci2.asi := dsur.asi;
IF ( dbgi.daddr ( 22 downto 20 ) = "111" ) and ( dbgi.dsuen = '1' ) THEN
dci2.dsuen := ( dbgi.denable or r.m.dci.dsuen ) and not dsur.crdy ( 2 );
dci2.enaddr := dbgi.denable;
dci2.size := "10";
dci2.read := '1';
dci2.write := '0';
IF ( dbgi.denable and not r.m.dci.enaddr ) = '1' THEN
mresult2 := ( OTHERS => '0' );
mresult2 ( 19 downto 2 ) := dbgi.daddr ( 19 downto 2 );
ELSE
mresult2 := dbgi.ddata;
END IF;
IF dbgi.dwrite = '1' THEN
dci2.read := '0';
dci2.write := '1';
END IF;
END IF;
END IF;
END;
PROCEDURE fpexack (
r : in registers;
fpexc : out std_ulogic
) IS
BEGIN
fpexc := '0';
END;
PROCEDURE diagrdy (
denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector ( 2 downto 1 )
) IS
BEGIN
crdy := dsur.crdy ( 1 ) & '0';
IF dci.dsuen = '1' THEN
CASE dsur.asi ( 4 downto 0 ) IS
WHEN ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy ( 2 ) := ico.diagrdy and not dsur.crdy ( 2 );
WHEN ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy ( 1 ) := not denable and dci.enaddr and not dsur.crdy ( 1 );
WHEN OTHERS =>
crdy ( 2 ) := dci.enaddr and denable;
END CASE;
END IF;
END;
SIGNAL r : registers;
SIGNAL rin : registers;
SIGNAL wpr : watchpoint_registers;
SIGNAL wprin : watchpoint_registers;
SIGNAL dsur : dsu_registers;
SIGNAL dsuin : dsu_registers;
SIGNAL ir : irestart_register;
SIGNAL irin : irestart_register;
SIGNAL rp : pwd_register_type;
SIGNAL rpin : pwd_register_type;
SIGNAL hackStateM1 : std_logic;
CONSTANT EXE_AND : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_XOR : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_OR : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_XNOR : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ANDN : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_ORN : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_DIV : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_PASS1 : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_PASS2 : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_STB : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_STH : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ONES : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_RDY : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_SPR : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_LINK : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT EXE_SLL : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_SRL : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_SRA : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_NOP : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_RES_ADD : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT EXE_RES_SHIFT : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT EXE_RES_LOGIC : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT EXE_RES_MISC : std_logic_vector ( 1 downto 0 ) := "11";
CONSTANT SZBYTE : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT SZHALF : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT SZWORD : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT SZDBL : std_logic_vector ( 1 downto 0 ) := "11";
PROCEDURE regaddr (
cwp : std_logic_vector;
reg : std_logic_vector ( 4 downto 0 );
rao : out rfatype
) IS
VARIABLE ra : rfatype;
CONSTANT globals : std_logic_vector ( 4 + 4 - 5 downto 0 ) := conv_std_logic_vector ( 8 , 4 + 4 - 4 );
BEGIN
ra := ( OTHERS => '0' );
ra ( 4 downto 0 ) := reg;
IF reg ( 4 downto 3 ) = "00" THEN
ra ( 7 downto 4 ) := CONV_STD_LOGIC_VECTOR ( 8 , 4 + 4 - 4 );
ELSE
ra ( 6 downto 4 ) := cwp + ra ( 4 );
END IF;
rao := ra;
END;
FUNCTION branch_address (
inst : word;
pc : pctype
) RETURN std_logic_vector IS
VARIABLE baddr : pctype;
VARIABLE caddr : pctype;
VARIABLE tmp : pctype;
BEGIN
caddr := ( OTHERS => '0' );
caddr ( 31 downto 2 ) := inst ( 29 downto 0 );
caddr ( 31 downto 2 ) := caddr ( 31 downto 2 ) + pc ( 31 downto 2 );
baddr := ( OTHERS => '0' );
baddr ( 31 downto 24 ) := ( OTHERS => inst ( 21 ) );
baddr ( 23 downto 2 ) := inst ( 21 downto 0 );
baddr ( 31 downto 2 ) := baddr ( 31 downto 2 ) + pc ( 31 downto 2 );
IF inst ( 30 ) = '1' THEN
tmp := caddr;
ELSE
tmp := baddr;
END IF;
RETURN ( tmp );
END;
FUNCTION branch_true (
icc : std_logic_vector ( 3 downto 0 );
inst : word
) RETURN std_ulogic IS
VARIABLE n : std_ulogic;
VARIABLE z : std_ulogic;
VARIABLE v : std_ulogic;
VARIABLE c : std_ulogic;
VARIABLE branch : std_ulogic;
BEGIN
n := icc ( 3 );
z := icc ( 2 );
v := icc ( 1 );
c := icc ( 0 );
CASE inst ( 27 downto 25 ) IS
WHEN "000" =>
branch := inst ( 28 ) xor '0';
WHEN "001" =>
branch := inst ( 28 ) xor z;
WHEN "010" =>
branch := inst ( 28 ) xor ( z or ( n xor v ) );
WHEN "011" =>
branch := inst ( 28 ) xor ( n xor v );
WHEN "100" =>
branch := inst ( 28 ) xor ( c or z );
WHEN "101" =>
branch := inst ( 28 ) xor c;
WHEN "110" =>
branch := inst ( 28 ) xor n;
WHEN OTHERS =>
branch := inst ( 28 ) xor v;
END CASE;
RETURN ( branch );
END;
PROCEDURE su_et_select (
r : in registers;
xc_ps : in std_ulogic;
xc_s : in std_ulogic;
xc_et : in std_ulogic;
su : out std_ulogic;
et : out std_ulogic
) IS
BEGIN
IF ( ( r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett ) = '1' ) and ( r.x.annul_all = '0' ) THEN
su := xc_ps;
et := '1';
ELSE
su := xc_s;
et := xc_et;
END IF;
END;
FUNCTION wphit (
r : registers;
wpr : watchpoint_registers;
debug : l3_debug_in_type
) RETURN std_ulogic IS
VARIABLE exc : std_ulogic;
BEGIN
exc := '0';
IF ( ( wpr ( 0 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 0 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = "000000000000000000000000000000" ) THEN
exc := '1';
END IF;
END IF;
IF ( ( wpr ( 1 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 1 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = "000000000000000000000000000000" ) THEN
exc := '1';
END IF;
END IF;
IF ( debug.dsuen and not r.a.ctrl.annul ) = '1' THEN
exc := exc or ( r.a.ctrl.pv and ( ( debug.dbreak and debug.bwatch ) or r.a.step ) );
END IF;
RETURN ( exc );
END;
FUNCTION shift3 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE shiftin : unsigned ( 63 downto 0 );
VARIABLE shiftout : unsigned ( 63 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
IF r.e.shleft = '1' THEN
shiftin ( 30 downto 0 ) := ( OTHERS => '0' );
shiftin ( 63 downto 31 ) := '0' & unsigned ( aluin1 );
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => r.e.sari );
shiftin ( 31 downto 0 ) := unsigned ( aluin1 );
END IF;
shiftout := SHIFT_RIGHT ( shiftin , cnt );
RETURN ( std_logic_vector ( shiftout ( 31 downto 0 ) ) );
END;
FUNCTION shift2 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE ushiftin : unsigned ( 31 downto 0 );
VARIABLE sshiftin : signed ( 32 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
ushiftin := unsigned ( aluin1 );
sshiftin := signed ( '0' & aluin1 );
IF r.e.shleft = '1' THEN
RETURN ( std_logic_vector ( SHIFT_LEFT ( ushiftin , cnt ) ) );
ELSE
IF r.e.sari = '1' THEN
sshiftin ( 32 ) := aluin1 ( 31 );
END IF;
sshiftin := SHIFT_RIGHT ( sshiftin , cnt );
RETURN ( std_logic_vector ( sshiftin ( 31 downto 0 ) ) );
END IF;
END;
FUNCTION shift (
r : registers;
aluin1 : word;
aluin2 : word;
shiftcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic
) RETURN word IS
VARIABLE shiftin : std_logic_vector ( 63 downto 0 );
BEGIN
shiftin := "00000000000000000000000000000000" & aluin1;
IF r.e.shleft = '1' THEN
shiftin ( 31 downto 0 ) := "00000000000000000000000000000000";
shiftin ( 63 downto 31 ) := '0' & aluin1;
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => sari );
END IF;
IF shiftcnt ( 4 ) = '1' THEN
shiftin ( 47 downto 0 ) := shiftin ( 63 downto 16 );
END IF;
IF shiftcnt ( 3 ) = '1' THEN
shiftin ( 39 downto 0 ) := shiftin ( 47 downto 8 );
END IF;
IF shiftcnt ( 2 ) = '1' THEN
shiftin ( 35 downto 0 ) := shiftin ( 39 downto 4 );
END IF;
IF shiftcnt ( 1 ) = '1' THEN
shiftin ( 33 downto 0 ) := shiftin ( 35 downto 2 );
END IF;
IF shiftcnt ( 0 ) = '1' THEN
shiftin ( 31 downto 0 ) := shiftin ( 32 downto 1 );
END IF;
RETURN ( shiftin ( 31 downto 0 ) );
END;
PROCEDURE exception_detect (
r : registers;
wpr : watchpoint_registers;
dbgi : l3_debug_in_type;
trapin : in std_ulogic;
ttin : in std_logic_vector ( 5 downto 0 );
trap : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE illegal_inst : std_ulogic;
VARIABLE privileged_inst : std_ulogic;
VARIABLE cp_disabled : std_ulogic;
VARIABLE fp_disabled : std_ulogic;
VARIABLE fpop : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE inst : word;
VARIABLE wph : std_ulogic;
BEGIN
inst := r.a.ctrl.inst;
trap := trapin;
tt := ttin;
IF r.a.ctrl.annul = '0' THEN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
rd := inst ( 29 downto 25 );
illegal_inst := '0';
privileged_inst := '0';
cp_disabled := '0';
fp_disabled := '0';
fpop := '0';
CASE op IS
WHEN CALL =>
NULL;
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI | BICC =>
NULL;
WHEN FBFCC =>
fp_disabled := '1';
WHEN CBCCC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR | XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX | ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC | SAVE | RESTORE | RDY =>
NULL;
WHEN TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
NULL;
WHEN UMAC | SMAC =>
illegal_inst := '1';
WHEN UMUL | SMUL | UMULCC | SMULCC =>
NULL;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
NULL;
WHEN RETT =>
illegal_inst := r.a.et;
privileged_inst := not r.a.su;
WHEN RDPSR | RDTBR | RDWIM =>
privileged_inst := not r.a.su;
WHEN WRY =>
NULL;
WHEN WRPSR =>
privileged_inst := not r.a.su;
WHEN WRWIM | WRTBR =>
privileged_inst := not r.a.su;
WHEN FPOP1 | FPOP2 =>
fp_disabled := '1';
fpop := '0';
WHEN CPOP1 | CPOP2 =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN OTHERS =>
CASE op3 IS
WHEN LDD | ISTD =>
illegal_inst := rd ( 0 );
WHEN LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
NULL;
WHEN LDDA | STDA =>
illegal_inst := inst ( 13 ) or rd ( 0 );
privileged_inst := not r.a.su;
WHEN LDA | LDUBA | LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA | SWAPA =>
illegal_inst := inst ( 13 );
privileged_inst := not r.a.su;
WHEN LDDF | STDF | LDF | LDFSR | STF | STFSR =>
fp_disabled := '1';
WHEN STDFQ =>
privileged_inst := not r.a.su;
fp_disabled := '1';
WHEN STDCQ =>
privileged_inst := not r.a.su;
cp_disabled := '1';
WHEN LDC | LDCSR | LDDC | STC | STCSR | STDC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
END CASE;
wph := wphit ( r , wpr , dbgi );
trap := '1';
IF r.a.ctrl.trap = '1' THEN
tt := TT_IAEX;
ELSIF privileged_inst = '1' THEN
tt := TT_PRIV;
ELSIF illegal_inst = '1' THEN
tt := TT_IINST;
ELSIF fp_disabled = '1' THEN
tt := TT_FPDIS;
ELSIF cp_disabled = '1' THEN
tt := TT_CPDIS;
ELSIF wph = '1' THEN
tt := TT_WATCH;
ELSIF r.a.wovf = '1' THEN
tt := TT_WINOF;
ELSIF r.a.wunf = '1' THEN
tt := TT_WINUF;
ELSIF r.a.ticc = '1' THEN
tt := TT_TICC;
ELSE
trap := '0';
tt := ( OTHERS => '0' );
END IF;
END IF;
END;
PROCEDURE wicc_y_gen (
inst : word;
wicc : out std_ulogic;
wy : out std_ulogic
) IS
BEGIN
wicc := '0';
wy := '0';
IF inst ( 31 downto 30 ) = FMT3 THEN
CASE inst ( 24 downto 19 ) IS
WHEN SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC | ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
WHEN WRY =>
IF r.d.inst ( conv_integer ( r.d.set ) ) ( 29 downto 25 ) = "00000" THEN
wy := '1';
END IF;
WHEN MULSCC =>
wicc := '1';
wy := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
wicc := '1';
wy := '1';
END IF;
WHEN UMUL | SMUL =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
wy := '1';
END IF;
WHEN UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wicc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
PROCEDURE cwp_gen (
r : registers;
v : registers;
annul : std_ulogic;
wcwp : std_ulogic;
ncwp : cwptype;
cwp : out cwptype
) IS
BEGIN
IF ( r.x.rstate = trap ) or ( r.x.rstate = dsu2 ) or ( rstn = '0' ) THEN
cwp := v.w.s.cwp;
ELSIF ( wcwp = '1' ) and ( annul = '0' ) THEN
cwp := ncwp;
ELSIF r.m.wcwp = '1' THEN
cwp := r.m.result ( 3 - 1 downto 0 );
ELSE
cwp := r.d.cwp;
END IF;
END;
PROCEDURE cwp_ex (
r : in registers;
wcwp : out std_ulogic
) IS
BEGIN
IF ( r.e.ctrl.inst ( 31 downto 30 ) = FMT3 ) and ( r.e.ctrl.inst ( 24 downto 19 ) = WRPSR ) THEN
wcwp := not r.e.ctrl.annul;
ELSE
wcwp := '0';
END IF;
END;
PROCEDURE cwp_ctrl (
r : in registers;
xc_wim : in std_logic_vector ( 8 - 1 downto 0 );
inst : word;
de_cwp : out cwptype;
wovf_exc : out std_ulogic;
wunf_exc : out std_ulogic;
wcwp : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE wim : word;
VARIABLE ncwp : cwptype;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
wovf_exc := '0';
wunf_exc := '0';
wim := ( OTHERS => '0' );
wim ( 8 - 1 downto 0 ) := xc_wim;
ncwp := r.d.cwp;
wcwp := '0';
IF ( op = FMT3 ) and ( ( op3 = RETT ) or ( op3 = RESTORE ) or ( op3 = SAVE ) ) THEN
wcwp := '1';
IF ( op3 = SAVE ) THEN
ncwp := r.d.cwp - 1;
ELSE
ncwp := r.d.cwp + 1;
END IF;
IF wim ( conv_integer ( ncwp ) ) = '1' THEN
IF op3 = SAVE THEN
wovf_exc := '1';
ELSE
wunf_exc := '1';
END IF;
END IF;
END IF;
de_cwp := ncwp;
END;
PROCEDURE rs1_gen (
r : registers;
inst : word;
rs1 : out std_logic_vector ( 4 downto 0 );
rs1mod : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
rs1 := inst ( 18 downto 14 );
rs1mod := '0';
IF ( op = LDST ) THEN
IF ( ( r.d.cnt = "01" ) and ( ( op3 ( 2 ) and not op3 ( 3 ) ) = '1' ) ) or ( r.d.cnt = "10" ) THEN
rs1mod := '1';
rs1 := inst ( 29 downto 25 );
END IF;
IF ( ( r.d.cnt = "10" ) and ( op3 ( 3 downto 0 ) = "0111" ) ) THEN
rs1 ( 0 ) := '1';
END IF;
END IF;
END;
PROCEDURE lock_gen (
r : registers;
rs2 : std_logic_vector ( 4 downto 0 );
rd : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rfrd : rfatype;
inst : word;
fpc_lock : std_ulogic;
mulinsn : std_ulogic;
divinsn : std_ulogic;
lldcheck1 : out std_ulogic;
lldcheck2 : out std_ulogic;
lldlock : out std_ulogic;
lldchkra : out std_ulogic;
lldchkex : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE rs1 : std_logic_vector ( 4 downto 0 );
VARIABLE i : std_ulogic;
VARIABLE ldcheck1 : std_ulogic;
VARIABLE ldcheck2 : std_ulogic;
VARIABLE ldchkra : std_ulogic;
VARIABLE ldchkex : std_ulogic;
VARIABLE ldcheck3 : std_ulogic;
VARIABLE ldlock : std_ulogic;
VARIABLE icc_check : std_ulogic;
VARIABLE bicc_hold : std_ulogic;
VARIABLE chkmul : std_ulogic;
VARIABLE y_check : std_ulogic;
VARIABLE lddlock : boolean;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
rs1 := inst ( 18 downto 14 );
lddlock := false;
i := inst ( 13 );
ldcheck1 := '0';
ldcheck2 := '0';
ldcheck3 := '0';
ldlock := '0';
ldchkra := '1';
ldchkex := '1';
icc_check := '0';
bicc_hold := '0';
y_check := '0';
IF ( r.d.annul = '0' ) THEN
CASE op IS
WHEN FMT2 =>
IF ( op2 = BICC ) and ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN FMT3 =>
ldcheck1 := '1';
ldcheck2 := not i;
CASE op3 IS
WHEN TICC =>
IF ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN RDY =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDWIM | RDTBR =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDPSR =>
ldcheck1 := '0';
ldcheck2 := '0';
icc_check := '1';
icc_check := '1';
WHEN SDIV | SDIVCC | UDIV | UDIVCC =>
y_check := '1';
WHEN FPOP1 | FPOP2 =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
ldcheck1 := '1';
ldchkra := '0';
CASE r.d.cnt IS
WHEN "00" =>
ldcheck2 := not i;
ldchkra := '1';
WHEN "01" =>
ldcheck2 := not i;
WHEN OTHERS =>
ldchkex := '0';
END CASE;
IF ( op3 ( 2 downto 0 ) = "011" ) THEN
lddlock := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
chkmul := mulinsn;
bicc_hold := bicc_hold or ( icc_check and r.m.ctrl.wicc and ( r.m.ctrl.cnt ( 0 ) or r.m.mul ) );
bicc_hold := bicc_hold or ( y_check and ( r.a.ctrl.wy or r.e.ctrl.wy ) );
chkmul := chkmul or divinsn;
bicc_hold := bicc_hold or ( icc_check and ( r.a.ctrl.wicc or r.e.ctrl.wicc ) );
IF ( ( ( r.a.ctrl.ld or chkmul ) and r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.a.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.a.ctrl.rd = rfa2 ) ) or ( ( ldcheck3 = '1' ) and ( r.a.ctrl.rd = rfrd ) ) ) THEN
ldlock := '1';
END IF;
IF ( ( ( r.e.ctrl.ld or r.e.mac ) and r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.e.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.e.ctrl.rd = rfa2 ) ) ) THEN
ldlock := '1';
END IF;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1;
lldcheck2 := ldcheck2;
lldlock := ldlock;
lldchkra := ldchkra;
lldchkex := ldchkex;
END;
PROCEDURE fpbranch (
inst : in word;
fcc : in std_logic_vector ( 1 downto 0 );
branch : out std_ulogic
) IS
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE fbres : std_ulogic;
BEGIN
cond := inst ( 28 downto 25 );
CASE cond ( 2 downto 0 ) IS
WHEN "000" =>
fbres := '0';
WHEN "001" =>
fbres := fcc ( 1 ) or fcc ( 0 );
WHEN "010" =>
fbres := fcc ( 1 ) xor fcc ( 0 );
WHEN "011" =>
fbres := fcc ( 0 );
WHEN "100" =>
fbres := ( not fcc ( 1 ) ) and fcc ( 0 );
WHEN "101" =>
fbres := fcc ( 1 );
WHEN "110" =>
fbres := fcc ( 1 ) and not fcc ( 0 );
WHEN OTHERS =>
fbres := fcc ( 1 ) and fcc ( 0 );
END CASE;
branch := cond ( 3 ) xor fbres;
END;
PROCEDURE ic_ctrl (
r : registers;
inst : word;
annul_all : in std_ulogic;
ldlock : in std_ulogic;
branch_true : in std_ulogic;
fbranch_true : in std_ulogic;
cbranch_true : in std_ulogic;
fccv : in std_ulogic;
cccv : in std_ulogic;
cnt : out std_logic_vector ( 1 downto 0 );
de_pc : out pctype;
de_branch : out std_ulogic;
ctrl_annul : out std_ulogic;
de_annul : out std_ulogic;
jmpl_inst : out std_ulogic;
inull : out std_ulogic;
de_pv : out std_ulogic;
ctrl_pv : out std_ulogic;
de_hold_pc : out std_ulogic;
ticc_exception : out std_ulogic;
rett_inst : out std_ulogic;
mulstart : out std_ulogic;
divstart : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE hold_pc : std_ulogic;
VARIABLE annul_current : std_ulogic;
VARIABLE annul_next : std_ulogic;
VARIABLE branch : std_ulogic;
VARIABLE annul : std_ulogic;
VARIABLE pv : std_ulogic;
VARIABLE de_jmpl : std_ulogic;
BEGIN
branch := '0';
annul_next := '0';
annul_current := '0';
pv := '1';
hold_pc := '0';
ticc_exception := '0';
rett_inst := '0';
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
annul := inst ( 29 );
de_jmpl := '0';
cnt := "00";
mulstart := '0';
divstart := '0';
IF r.d.annul = '0' THEN
CASE inst ( 31 downto 30 ) IS
WHEN CALL =>
branch := '1';
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
END IF;
WHEN FMT2 =>
IF ( op2 = BICC ) THEN
branch := branch_true;
IF hold_pc = '0' THEN
IF ( branch = '1' ) THEN
IF ( cond = BA ) and ( annul = '1' ) THEN
annul_next := '1';
END IF;
ELSE
annul_next := annul;
END IF;
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
annul_next := '0';
END IF;
END IF;
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
mulstart := '1';
WHEN "01" =>
IF mulo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
divstart := '1';
WHEN "01" =>
IF divo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN TICC =>
IF branch_true = '1' THEN
ticc_exception := '1';
END IF;
WHEN RETT =>
rett_inst := '1';
WHEN JMPL =>
de_jmpl := '1';
WHEN WRY =>
IF FALSE THEN
IF inst ( 29 downto 25 ) = "10011" THEN
CASE r.d.cnt IS
WHEN "00" =>
pv := '0';
cnt := "00";
hold_pc := '1';
IF r.x.ipend = '1' THEN
cnt := "01";
END IF;
WHEN "01" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.d.cnt IS
WHEN "00" =>
IF ( op3 ( 2 ) = '1' ) or ( op3 ( 1 downto 0 ) = "11" ) THEN
cnt := "01";
hold_pc := '1';
pv := '0';
END IF;
WHEN "01" =>
IF ( op3 ( 2 downto 0 ) = "111" ) or ( op3 ( 3 downto 0 ) = "1101" ) or ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( ( op3 ( 5 ) & op3 ( 2 downto 0 ) ) = "1110" ) ) THEN
cnt := "10";
pv := '0';
hold_pc := '1';
ELSE
cnt := "00";
END IF;
WHEN "10" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END IF;
IF ldlock = '1' THEN
cnt := r.d.cnt;
annul_next := '0';
pv := '1';
END IF;
hold_pc := ( hold_pc or ldlock ) and not annul_all;
IF hold_pc = '1' THEN
de_pc := r.d.pc;
ELSE
de_pc := r.f.pc;
END IF;
annul_current := ( annul_current or ldlock or annul_all );
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ( ( r.d.inull and not hold_pc ) or annul_all );
jmpl_inst := de_jmpl and not annul_current;
annul_next := ( r.d.inull and not hold_pc ) or annul_next or annul_all;
IF ( annul_next = '1' ) or ( rstn = '0' ) THEN
cnt := ( OTHERS => '0' );
END IF;
de_hold_pc := hold_pc;
de_branch := branch;
de_annul := annul_next;
de_pv := pv;
ctrl_pv := r.d.pv and not ( ( r.d.annul and not r.d.pv ) or annul_all or annul_current );
inull := ( not rstn ) or r.d.inull or hold_pc or annul_all;
END;
PROCEDURE rd_gen (
r : registers;
inst : word;
wreg : out std_ulogic;
ld : out std_ulogic;
rdo : out std_logic_vector ( 4 downto 0 )
) IS
VARIABLE write_reg : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
write_reg := '0';
rd := inst ( 29 downto 25 );
ld := '0';
CASE op IS
WHEN CALL =>
write_reg := '1';
rd := "01111";
WHEN FMT2 =>
IF ( op2 = SETHI ) THEN
write_reg := '1';
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
write_reg := '1';
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
write_reg := '1';
END IF;
WHEN RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH =>
NULL;
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
write_reg := '1';
END CASE;
WHEN OTHERS =>
ld := not op3 ( 2 );
IF ( op3 ( 2 ) = '0' ) and not ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( op3 ( 5 ) = '1' ) ) THEN
write_reg := '1';
END IF;
CASE op3 IS
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
IF r.d.cnt = "00" THEN
write_reg := '1';
ld := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF r.d.cnt = "01" THEN
CASE op3 IS
WHEN LDD | LDDA | LDDC | LDDF =>
rd ( 0 ) := '1';
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END CASE;
IF ( rd = "00000" ) THEN
write_reg := '0';
END IF;
wreg := write_reg;
rdo := rd;
END;
FUNCTION imm_data (
r : registers;
insn : word
) RETURN word IS
VARIABLE immediate_data : word;
VARIABLE inst : word;
BEGIN
immediate_data := ( OTHERS => '0' );
inst := insn;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
immediate_data := inst ( 21 downto 0 ) & "0000000000";
WHEN OTHERS =>
immediate_data ( 31 downto 13 ) := ( OTHERS => inst ( 12 ) );
immediate_data ( 12 downto 0 ) := inst ( 12 downto 0 );
END CASE;
RETURN ( immediate_data );
END;
FUNCTION get_spr (
r : registers
) RETURN word IS
VARIABLE spr : word;
BEGIN
spr := ( OTHERS => '0' );
CASE r.e.ctrl.inst ( 24 downto 19 ) IS
WHEN RDPSR =>
spr ( 31 downto 5 ) := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr ( 3 - 1 downto 0 ) := r.e.cwp;
WHEN RDTBR =>
spr ( 31 downto 4 ) := r.w.s.tba & r.w.s.tt;
WHEN RDWIM =>
spr ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( spr );
END;
FUNCTION imm_select (
inst : word
) RETURN boolean IS
VARIABLE imm : boolean;
BEGIN
imm := false;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
CASE inst ( 24 downto 22 ) IS
WHEN SETHI =>
imm := true;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE inst ( 24 downto 19 ) IS
WHEN RDWIM | RDPSR | RDTBR =>
imm := true;
WHEN OTHERS =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
END CASE;
WHEN LDST =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( imm );
END;
PROCEDURE alu_op (
r : in registers;
iop1 : in word;
iop2 : in word;
me_icc : std_logic_vector ( 3 downto 0 );
my : std_ulogic;
ldbp : std_ulogic;
aop1 : out word;
aop2 : out word;
aluop : out std_logic_vector ( 2 downto 0 );
alusel : out std_logic_vector ( 1 downto 0 );
aluadd : out std_ulogic;
shcnt : out std_logic_vector ( 4 downto 0 );
sari : out std_ulogic;
shleft : out std_ulogic;
ymsb : out std_ulogic;
mulins : out std_ulogic;
divins : out std_ulogic;
mulstep : out std_ulogic;
macins : out std_ulogic;
ldbp2 : out std_ulogic;
invop2 : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE y0 : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op2 := r.a.ctrl.inst ( 24 downto 22 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
aop1 := iop1;
aop2 := iop2;
ldbp2 := ldbp;
aluop := "000";
alusel := "11";
aluadd := '1';
shcnt := iop2 ( 4 downto 0 );
sari := '0';
shleft := '0';
invop2 := '0';
ymsb := iop1 ( 0 );
mulins := '0';
divins := '0';
mulstep := '0';
macins := '0';
IF r.e.ctrl.wy = '1' THEN
y0 := my;
ELSIF r.m.ctrl.wy = '1' THEN
y0 := r.m.y ( 0 );
ELSIF r.x.ctrl.wy = '1' THEN
y0 := r.x.y ( 0 );
ELSE
y0 := r.w.s.y ( 0 );
END IF;
IF r.e.ctrl.wicc = '1' THEN
icc := me_icc;
ELSIF r.m.ctrl.wicc = '1' THEN
icc := r.m.icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icc := r.x.icc;
ELSE
icc := r.w.s.icc;
END IF;
CASE op IS
WHEN CALL =>
aluop := "111";
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI =>
aluop := "001";
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE | TICC | JMPL | RETT =>
alusel := "00";
WHEN ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := "00";
aluadd := '0';
aop2 := not iop2;
invop2 := '1';
WHEN MULSCC =>
alusel := "00";
aop1 := ( icc ( 3 ) xor icc ( 1 ) ) & iop1 ( 31 downto 1 );
IF y0 = '0' THEN
aop2 := ( OTHERS => '0' );
ldbp2 := '0';
END IF;
mulstep := '1';
WHEN UMUL | UMULCC | SMUL | SMULCC =>
mulins := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | UDIVCC | SDIV | SDIVCC =>
aluop := "110";
alusel := "10";
divins := '1';
WHEN IAND | ANDCC =>
aluop := "000";
alusel := "10";
WHEN ANDN | ANDNCC =>
aluop := "100";
alusel := "10";
WHEN IOR | ORCC =>
aluop := "010";
alusel := "10";
WHEN ORN | ORNCC =>
aluop := "101";
alusel := "10";
WHEN IXNOR | XNORCC =>
aluop := "011";
alusel := "10";
WHEN XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := "001";
alusel := "10";
WHEN RDPSR | RDTBR | RDWIM =>
aluop := "110";
WHEN RDY =>
aluop := "101";
WHEN ISLL =>
aluop := "001";
alusel := "01";
shleft := '1';
shcnt := not iop2 ( 4 downto 0 );
invop2 := '1';
WHEN ISRL =>
aluop := "010";
alusel := "01";
WHEN ISRA =>
aluop := "100";
alusel := "01";
sari := iop1 ( 31 );
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.a.ctrl.cnt IS
WHEN "00" =>
alusel := "00";
WHEN "01" =>
CASE op3 IS
WHEN LDD | LDDA | LDDC =>
alusel := "00";
WHEN LDDF =>
alusel := "00";
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
alusel := "00";
WHEN STF | STDF =>
NULL;
WHEN OTHERS =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF op3 ( 1 downto 0 ) = "01" THEN
aluop := "010";
ELSIF op3 ( 1 downto 0 ) = "10" THEN
aluop := "011";
END IF;
END IF;
END CASE;
WHEN "10" =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF ( op3 ( 3 ) and not op3 ( 1 ) ) = '1' THEN
aluop := "100";
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END;
FUNCTION ra_inull_gen (
r : registers;
v : registers
) RETURN std_ulogic IS
VARIABLE de_inull : std_ulogic;
BEGIN
de_inull := '0';
IF ( ( v.e.jmpl or v.e.ctrl.rett ) and not v.e.ctrl.annul and not ( r.e.jmpl and not r.e.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
IF ( ( v.a.jmpl or v.a.ctrl.rett ) and not v.a.ctrl.annul and not ( r.a.jmpl and not r.a.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
RETURN ( de_inull );
END;
PROCEDURE op_mux (
r : in registers;
rfd : in word;
ed : in word;
md : in word;
xd : in word;
im : in word;
rsel : in std_logic_vector ( 2 downto 0 );
ldbp : out std_ulogic;
d : out word
) IS
BEGIN
ldbp := '0';
CASE rsel IS
WHEN "000" =>
d := rfd;
WHEN "001" =>
d := ed;
WHEN "010" =>
d := md;
ldbp := r.m.ctrl.ld;
WHEN "011" =>
d := xd;
WHEN "100" =>
d := im;
WHEN "101" =>
d := ( OTHERS => '0' );
WHEN "110" =>
d := r.w.result;
WHEN OTHERS =>
d := ( OTHERS => '-' );
END CASE;
END;
PROCEDURE op_find (
r : in registers;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
rs1 : std_logic_vector ( 4 downto 0 );
ra : rfatype;
im : boolean;
rfe : out std_ulogic;
osel : out std_logic_vector ( 2 downto 0 );
ldcheck : std_ulogic
) IS
BEGIN
rfe := '0';
IF im THEN
osel := "100";
ELSIF rs1 = "00000" THEN
osel := "101";
ELSIF ( ( r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ra = r.a.ctrl.rd ) THEN
osel := "001";
ELSIF ( ( r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ra = r.e.ctrl.rd ) THEN
osel := "010";
ELSIF r.m.ctrl.wreg = '1' and ( ra = r.m.ctrl.rd ) THEN
osel := "011";
ELSE
osel := "000";
rfe := ldcheck;
END IF;
END;
PROCEDURE cin_gen (
r : registers;
me_cin : in std_ulogic;
cin : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE ncin : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
IF r.e.ctrl.wicc = '1' THEN
ncin := me_cin;
ELSE
ncin := r.m.icc ( 0 );
END IF;
cin := '0';
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN ISUB | SUBCC | TSUBCC | TSUBCCTV =>
cin := '1';
WHEN ADDX | ADDXCC =>
cin := ncin;
WHEN SUBX | SUBXCC =>
cin := not ncin;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE logic_op (
r : registers;
aluin1 : word;
aluin2 : word;
mey : word;
ymsb : std_ulogic;
logicres : out word;
y : out word
) IS
VARIABLE logicout : word;
BEGIN
CASE r.e.aluop IS
WHEN "000" =>
logicout := aluin1 and aluin2;
WHEN "100" =>
logicout := aluin1 and not aluin2;
WHEN "010" =>
logicout := aluin1 or aluin2;
WHEN "101" =>
logicout := aluin1 or not aluin2;
WHEN "001" =>
logicout := aluin1 xor aluin2;
WHEN "011" =>
logicout := aluin1 xor not aluin2;
WHEN "110" =>
logicout := aluin2;
WHEN OTHERS =>
logicout := ( OTHERS => '-' );
END CASE;
IF ( r.e.ctrl.wy and r.e.mulstep ) = '1' THEN
y := ymsb & r.m.y ( 31 downto 1 );
ELSIF r.e.ctrl.wy = '1' THEN
y := logicout;
ELSIF r.m.ctrl.wy = '1' THEN
y := mey;
ELSIF r.x.ctrl.wy = '1' THEN
y := r.x.y;
ELSE
y := r.w.s.y;
END IF;
logicres := logicout;
END;
PROCEDURE misc_op (
r : registers;
wpr : watchpoint_registers;
aluin1 : word;
aluin2 : word;
ldata : word;
mey : word;
mout : out word;
edata : out word
) IS
VARIABLE miscout : word;
VARIABLE bpdata : word;
VARIABLE stdata : word;
VARIABLE wpi : integer;
BEGIN
wpi := 0;
miscout := r.e.ctrl.pc ( 31 downto 2 ) & "00";
edata := aluin1;
bpdata := aluin1;
IF ( ( r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul ) = '1' ) and ( r.x.ctrl.rd = r.e.ctrl.rd ) and ( r.e.ctrl.inst ( 31 downto 30 ) = LDST ) and ( r.e.ctrl.cnt /= "10" ) THEN
bpdata := ldata;
END IF;
CASE r.e.aluop IS
WHEN "010" =>
miscout := bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 );
edata := miscout;
WHEN "011" =>
miscout := bpdata ( 15 downto 0 ) & bpdata ( 15 downto 0 );
edata := miscout;
WHEN "000" =>
miscout := bpdata;
edata := miscout;
WHEN "001" =>
miscout := aluin2;
WHEN "100" =>
miscout := ( OTHERS => '1' );
edata := miscout;
WHEN "101" =>
IF ( r.m.ctrl.wy = '1' ) THEN
miscout := mey;
ELSE
miscout := r.m.y;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "11" ) THEN
wpi := conv_integer ( r.e.ctrl.inst ( 16 downto 15 ) );
IF r.e.ctrl.inst ( 14 ) = '0' THEN
miscout := wpr ( wpi ).addr & '0' & wpr ( wpi ).exec;
ELSE
miscout := wpr ( wpi ).mask & wpr ( wpi ).load & wpr ( wpi ).store;
END IF;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "10" ) and ( r.e.ctrl.inst ( 14 ) = '1' ) THEN
miscout := asr17_gen ( r );
END IF;
WHEN "110" =>
miscout := get_spr ( r );
WHEN OTHERS =>
NULL;
END CASE;
mout := miscout;
END;
PROCEDURE alu_select (
r : registers;
addout : std_logic_vector ( 32 downto 0 );
op1 : word;
op2 : word;
shiftout : word;
logicout : word;
miscout : word;
res : out word;
me_icc : std_logic_vector ( 3 downto 0 );
icco : out std_logic_vector ( 3 downto 0 );
divz : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE aluresult : word;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
icc := ( OTHERS => '0' );
CASE r.e.alusel IS
WHEN "00" =>
aluresult := addout ( 32 downto 1 );
IF r.e.aluadd = '0' THEN
icc ( 0 ) := ( ( not op1 ( 31 ) ) and not op2 ( 31 ) ) or ( addout ( 32 ) and ( ( not op1 ( 31 ) ) or not op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and ( op2 ( 31 ) ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and not op2 ( 31 ) );
ELSE
icc ( 0 ) := ( op1 ( 31 ) and op2 ( 31 ) ) or ( ( not addout ( 32 ) ) and ( op1 ( 31 ) or op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and op2 ( 31 ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and ( not op2 ( 31 ) ) );
END IF;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN TADDCC | TADDCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or op2 ( 0 ) or op2 ( 1 ) or icc ( 1 );
WHEN TSUBCC | TSUBCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or ( not op2 ( 0 ) ) or ( not op2 ( 1 ) ) or icc ( 1 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF aluresult = "00000000000000000000000000000000" THEN
icc ( 2 ) := '1';
END IF;
WHEN "01" =>
aluresult := shiftout;
WHEN "10" =>
aluresult := logicout;
IF aluresult = "00000000000000000000000000000000" THEN
icc ( 2 ) := '1';
END IF;
WHEN OTHERS =>
aluresult := miscout;
END CASE;
IF r.e.jmpl = '1' THEN
aluresult := r.e.ctrl.pc ( 31 downto 2 ) & "00";
END IF;
icc ( 3 ) := aluresult ( 31 );
divz := icc ( 2 );
IF r.e.ctrl.wicc = '1' THEN
IF ( op = FMT3 ) and ( op3 = WRPSR ) THEN
icco := logicout ( 23 downto 20 );
ELSE
icco := icc;
END IF;
ELSIF r.m.ctrl.wicc = '1' THEN
icco := me_icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icco := r.x.icc;
ELSE
icco := r.w.s.icc;
END IF;
res := aluresult;
END;
PROCEDURE dcache_gen (
r : registers;
v : registers;
dci : out dc_in_type;
link_pc : out std_ulogic;
jump : out std_ulogic;
force_a2 : out std_ulogic;
load : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE su : std_ulogic;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
dci.signed := '0';
dci.lock := '0';
dci.dsuen := '0';
dci.size := "10";
IF op = LDST THEN
CASE op3 IS
WHEN LDUB | LDUBA =>
dci.size := "00";
WHEN LDSTUB | LDSTUBA =>
dci.size := "00";
dci.lock := '1';
WHEN LDUH | LDUHA =>
dci.size := "01";
WHEN LDSB | LDSBA =>
dci.size := "00";
dci.signed := '1';
WHEN LDSH | LDSHA =>
dci.size := "01";
dci.signed := '1';
WHEN LD | LDA | LDF | LDC =>
dci.size := "10";
WHEN SWAP | SWAPA =>
dci.size := "10";
dci.lock := '1';
WHEN LDD | LDDA | LDDF | LDDC =>
dci.size := "11";
WHEN STB | STBA =>
dci.size := "00";
WHEN STH | STHA =>
dci.size := "01";
WHEN ST | STA | STF =>
dci.size := "10";
WHEN ISTD | STDA =>
dci.size := "11";
WHEN STDF | STDFQ =>
NULL;
WHEN STDC | STDCQ =>
NULL;
WHEN OTHERS =>
dci.size := "10";
dci.lock := '0';
dci.signed := '0';
END CASE;
END IF;
link_pc := '0';
jump := '0';
force_a2 := '0';
load := '0';
dci.write := '0';
dci.enaddr := '0';
dci.read := not op3 ( 2 );
IF ( r.e.ctrl.annul = '0' ) THEN
CASE op IS
WHEN CALL =>
link_pc := '1';
WHEN FMT3 =>
CASE op3 IS
WHEN JMPL =>
jump := '1';
link_pc := '1';
WHEN RETT =>
jump := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
CASE r.e.ctrl.cnt IS
WHEN "00" =>
dci.read := op3 ( 3 ) or not op3 ( 2 );
load := op3 ( 3 ) or not op3 ( 2 );
dci.enaddr := '1';
WHEN "01" =>
force_a2 := not op3 ( 2 );
load := not op3 ( 2 );
dci.enaddr := not op3 ( 2 );
IF op3 ( 3 downto 2 ) = "01" THEN
dci.write := '1';
END IF;
IF op3 ( 3 downto 2 ) = "11" THEN
dci.enaddr := '1';
END IF;
WHEN "10" =>
dci.write := '1';
WHEN OTHERS =>
NULL;
END CASE;
IF ( r.e.ctrl.trap or ( v.x.ctrl.trap and not v.x.ctrl.annul ) ) = '1' THEN
dci.enaddr := '0';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( ( r.x.ctrl.rett and not r.x.ctrl.annul ) = '1' ) THEN
su := r.w.s.ps;
ELSE
su := r.w.s.s;
END IF;
IF su = '1' THEN
dci.asi := "00001011";
ELSE
dci.asi := "00001010";
END IF;
IF ( op3 ( 4 ) = '1' ) and ( ( op3 ( 5 ) = '0' ) or not ( 0 = 1 ) ) THEN
dci.asi := r.e.ctrl.inst ( 12 downto 5 );
END IF;
END;
PROCEDURE fpstdata (
r : in registers;
edata : in word;
eres : in word;
fpstdata : in std_logic_vector ( 31 downto 0 );
edata2 : out word;
eres2 : out word
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
edata2 := edata;
eres2 := eres;
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
END;
FUNCTION ld_align (
data : dcdtype;
set : std_logic_vector ( 0 downto 0 );
size : std_logic_vector ( 1 downto 0 );
laddr : std_logic_vector ( 1 downto 0 );
signed : std_ulogic
) RETURN word IS
VARIABLE align_data : word;
VARIABLE rdata : word;
BEGIN
align_data := data ( conv_integer ( set ) );
rdata := ( OTHERS => '0' );
CASE size IS
WHEN "00" =>
CASE laddr IS
WHEN "00" =>
rdata ( 7 downto 0 ) := align_data ( 31 downto 24 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 31 ) );
END IF;
WHEN "01" =>
rdata ( 7 downto 0 ) := align_data ( 23 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 23 ) );
END IF;
WHEN "10" =>
rdata ( 7 downto 0 ) := align_data ( 15 downto 8 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 15 ) );
END IF;
WHEN OTHERS =>
rdata ( 7 downto 0 ) := align_data ( 7 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 7 ) );
END IF;
END CASE;
WHEN "01" =>
IF laddr ( 1 ) = '1' THEN
rdata ( 15 downto 0 ) := align_data ( 15 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 15 ) );
END IF;
ELSE
rdata ( 15 downto 0 ) := align_data ( 31 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 31 ) );
END IF;
END IF;
WHEN OTHERS =>
rdata := align_data;
END CASE;
RETURN ( rdata );
END;
PROCEDURE mem_trap (
r : registers;
wpr : watchpoint_registers;
annul : in std_ulogic;
holdn : in std_ulogic;
trapout : out std_ulogic;
iflush : out std_ulogic;
nullify : out std_ulogic;
werrout : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE cwp : std_logic_vector ( 3 - 1 downto 0 );
VARIABLE cwpx : std_logic_vector ( 5 downto 3 );
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE nalign_d : std_ulogic;
VARIABLE trap : std_ulogic;
VARIABLE werr : std_ulogic;
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op2 := r.m.ctrl.inst ( 24 downto 22 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
cwpx := r.m.result ( 5 downto 3 );
cwpx ( 5 ) := '0';
iflush := '0';
trap := r.m.ctrl.trap;
nullify := annul;
tt := r.m.ctrl.tt;
werr := ( dco.werr or r.m.werr ) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result ( 2 );
IF ( ( annul or trap ) /= '1' ) and ( r.m.ctrl.pv = '1' ) THEN
IF ( werr and holdn ) = '1' THEN
trap := '1';
tt := TT_DSEX;
werr := '0';
IF op = LDST THEN
nullify := '1';
END IF;
END IF;
END IF;
IF ( ( annul or trap ) /= '1' ) THEN
CASE op IS
WHEN FMT2 =>
CASE op2 IS
WHEN FBFCC =>
NULL;
WHEN CBCCC =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN WRPSR =>
IF ( orv ( cwpx ) = '1' ) THEN
trap := '1';
tt := TT_IINST;
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF r.m.divz = '1' THEN
trap := '1';
tt := TT_DIV;
END IF;
WHEN JMPL | RETT =>
IF r.m.nalign = '1' THEN
trap := '1';
tt := TT_UNALA;
END IF;
WHEN TADDCCTV | TSUBCCTV =>
IF ( r.m.icc ( 1 ) = '1' ) THEN
trap := '1';
tt := TT_TAG;
END IF;
WHEN FLUSH =>
iflush := '1';
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
IF r.m.ctrl.cnt = "00" THEN
CASE op3 IS
WHEN LDDF | STDF | STDFQ =>
NULL;
WHEN LDDC | STDC | STDCQ =>
NULL;
WHEN LDD | ISTD | LDDA | STDA =>
IF r.m.result ( 2 downto 0 ) /= "000" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDF | LDFSR | STFSR | STF =>
NULL;
WHEN LDC | LDCSR | STCSR | STC =>
NULL;
WHEN LD | LDA | ST | STA | SWAP | SWAPA =>
IF r.m.result ( 1 downto 0 ) /= "00" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
IF r.m.result ( 0 ) /= '0' THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF ( ( ( ( wpr ( 0 ).load and not op3 ( 2 ) ) or ( wpr ( 0 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 0 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = "000000000000000000000000000000" ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
IF ( ( ( ( wpr ( 1 ).load and not op3 ( 2 ) ) or ( wpr ( 1 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 1 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = "000000000000000000000000000000" ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( rstn = '0' ) or ( r.x.rstate = dsu2 ) THEN
werr := '0';
END IF;
trapout := trap;
werrout := werr;
END;
PROCEDURE irq_trap (
r : in registers;
ir : in irestart_register;
irl : in std_logic_vector ( 3 downto 0 );
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector ( 5 downto 0 );
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2 : out std_ulogic;
ipend : out std_ulogic;
tt2 : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE pend : std_ulogic;
BEGIN
nullify2 := nullify;
trap2 := trap;
tt2 := tt;
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
irqen := '1';
irqen2 := r.m.irqen;
IF ( annul or trap ) = '0' THEN
IF ( ( op = FMT3 ) and ( op3 = WRPSR ) ) THEN
irqen := '0';
END IF;
END IF;
IF ( irl = "1111" ) or ( irl > r.w.s.pil ) THEN
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
ELSE
pend := '0';
END IF;
ipend := pend;
IF ( ( not annul ) and pv and ( not trap ) and pend ) = '1' THEN
trap2 := '1';
tt2 := "01" & irl;
IF op = LDST THEN
nullify2 := '1';
END IF;
END IF;
END;
PROCEDURE irq_intack (
r : in registers;
holdn : in std_ulogic;
intack : out std_ulogic
) IS
BEGIN
intack := '0';
IF r.x.rstate = trap THEN
IF r.w.s.tt ( 7 downto 4 ) = "0001" THEN
intack := '1';
END IF;
END IF;
END;
PROCEDURE sp_write (
r : registers;
wpr : watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op2 := r.x.ctrl.inst ( 24 downto 22 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
s := r.w.s;
rd := r.x.ctrl.inst ( 29 downto 25 );
vwpr := wpr;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN WRY =>
IF rd = "00000" THEN
s.y := r.x.result;
ELSIF ( rd = "10001" ) THEN
s.dwt := r.x.result ( 14 );
s.svt := r.x.result ( 13 );
ELSIF rd ( 4 downto 3 ) = "11" THEN
CASE rd ( 2 downto 0 ) IS
WHEN "000" =>
vwpr ( 0 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 0 ).exec := r.x.result ( 0 );
WHEN "001" =>
vwpr ( 0 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 0 ).load := r.x.result ( 1 );
vwpr ( 0 ).store := r.x.result ( 0 );
WHEN "010" =>
vwpr ( 1 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 1 ).exec := r.x.result ( 0 );
WHEN "011" =>
vwpr ( 1 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 1 ).load := r.x.result ( 1 );
vwpr ( 1 ).store := r.x.result ( 0 );
WHEN "100" =>
vwpr ( 2 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 2 ).exec := r.x.result ( 0 );
WHEN "101" =>
vwpr ( 2 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 2 ).load := r.x.result ( 1 );
vwpr ( 2 ).store := r.x.result ( 0 );
WHEN "110" =>
vwpr ( 3 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 3 ).exec := r.x.result ( 0 );
WHEN OTHERS =>
vwpr ( 3 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 3 ).load := r.x.result ( 1 );
vwpr ( 3 ).store := r.x.result ( 0 );
END CASE;
END IF;
WHEN WRPSR =>
s.cwp := r.x.result ( 3 - 1 downto 0 );
s.icc := r.x.result ( 23 downto 20 );
s.ec := r.x.result ( 13 );
s.pil := r.x.result ( 11 downto 8 );
s.s := r.x.result ( 7 );
s.ps := r.x.result ( 6 );
s.et := r.x.result ( 5 );
WHEN WRWIM =>
s.wim := r.x.result ( 8 - 1 downto 0 );
WHEN WRTBR =>
s.tba := r.x.result ( 31 downto 12 );
WHEN SAVE =>
s.cwp := r.w.s.cwp - 1;
WHEN RESTORE =>
s.cwp := r.w.s.cwp + 1;
WHEN RETT =>
s.cwp := r.w.s.cwp + 1;
s.s := r.w.s.ps;
s.et := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF r.x.ctrl.wicc = '1' THEN
s.icc := r.x.icc;
END IF;
IF r.x.ctrl.wy = '1' THEN
s.y := r.x.y;
END IF;
END;
FUNCTION npc_find (
r : registers
) RETURN std_logic_vector IS
VARIABLE npc : std_logic_vector ( 2 downto 0 );
BEGIN
npc := "011";
IF r.m.ctrl.pv = '1' THEN
npc := "000";
ELSIF r.e.ctrl.pv = '1' THEN
npc := "001";
ELSIF r.a.ctrl.pv = '1' THEN
npc := "010";
ELSIF r.d.pv = '1' THEN
npc := "011";
ELSE
npc := "100";
END IF;
RETURN ( npc );
END;
FUNCTION npc_gen (
r : registers
) RETURN word IS
VARIABLE npc : std_logic_vector ( 31 downto 0 );
BEGIN
npc := r.a.ctrl.pc ( 31 downto 2 ) & "00";
CASE r.x.npc IS
WHEN "000" =>
npc ( 31 downto 2 ) := r.x.ctrl.pc ( 31 downto 2 );
WHEN "001" =>
npc ( 31 downto 2 ) := r.m.ctrl.pc ( 31 downto 2 );
WHEN "010" =>
npc ( 31 downto 2 ) := r.e.ctrl.pc ( 31 downto 2 );
WHEN "011" =>
npc ( 31 downto 2 ) := r.a.ctrl.pc ( 31 downto 2 );
WHEN OTHERS =>
npc ( 31 downto 2 ) := r.d.pc ( 31 downto 2 );
END CASE;
RETURN ( npc );
END;
PROCEDURE mul_res (
r : registers;
asr18in : word;
result : out word;
y : out word;
asr18 : out word;
icc : out std_logic_vector ( 3 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
result := r.m.result;
y := r.m.y;
icc := r.m.icc;
asr18 := asr18in;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL =>
result := mulo.result ( 31 downto 0 );
y := mulo.result ( 63 downto 32 );
WHEN UMULCC | SMULCC =>
result := mulo.result ( 31 downto 0 );
icc := mulo.icc;
y := mulo.result ( 63 downto 32 );
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | SDIV =>
result := divo.result ( 31 downto 0 );
WHEN UDIVCC | SDIVCC =>
result := divo.result ( 31 downto 0 );
icc := divo.icc;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
FUNCTION powerdwn (
r : registers;
trap : std_ulogic;
rp : pwd_register_type
) RETURN std_ulogic IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE pd : std_ulogic;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
rd := r.x.ctrl.inst ( 29 downto 25 );
pd := '0';
IF ( not ( r.x.ctrl.annul or trap ) and r.x.ctrl.pv ) = '1' THEN
IF ( ( op = FMT3 ) and ( op3 = WRY ) and ( rd = "10011" ) ) THEN
pd := '1';
END IF;
pd := pd or rp.pwd;
END IF;
RETURN ( pd );
END;
SIGNAL dummy : std_ulogic;
SIGNAL cpu_index : std_logic_vector ( 3 downto 0 );
SIGNAL disasen : std_ulogic;
BEGIN
comb : PROCESS ( ico , dco , rfo , r , wpr , ir , dsur , rstn , holdn , irqi , dbgi , fpo , cpo , tbo , mulo , divo , dummy , rp )
VARIABLE v : registers;
VARIABLE vp : pwd_register_type;
VARIABLE vwpr : watchpoint_registers;
VARIABLE vdsu : dsu_registers;
VARIABLE npc : std_logic_vector ( 31 downto 2 );
VARIABLE de_raddr1 : std_logic_vector ( 9 downto 0 );
VARIABLE de_raddr2 : std_logic_vector ( 9 downto 0 );
VARIABLE de_rs2 : std_logic_vector ( 4 downto 0 );
VARIABLE de_rd : std_logic_vector ( 4 downto 0 );
VARIABLE de_hold_pc : std_ulogic;
VARIABLE de_branch : std_ulogic;
VARIABLE de_fpop : std_ulogic;
VARIABLE de_ldlock : std_ulogic;
VARIABLE de_cwp : cwptype;
VARIABLE de_cwp2 : cwptype;
VARIABLE de_inull : std_ulogic;
VARIABLE de_ren1 : std_ulogic;
VARIABLE de_ren2 : std_ulogic;
VARIABLE de_wcwp : std_ulogic;
VARIABLE de_inst : word;
VARIABLE de_branch_address : pctype;
VARIABLE de_icc : std_logic_vector ( 3 downto 0 );
VARIABLE de_fbranch : std_ulogic;
VARIABLE de_cbranch : std_ulogic;
VARIABLE de_rs1mod : std_ulogic;
VARIABLE ra_op1 : word;
VARIABLE ra_op2 : word;
VARIABLE ra_div : std_ulogic;
VARIABLE ex_jump : std_ulogic;
VARIABLE ex_link_pc : std_ulogic;
VARIABLE ex_jump_address : pctype;
VARIABLE ex_add_res : std_logic_vector ( 32 downto 0 );
VARIABLE ex_shift_res : word;
VARIABLE ex_logic_res : word;
VARIABLE ex_misc_res : word;
VARIABLE ex_edata : word;
VARIABLE ex_edata2 : word;
VARIABLE ex_dci : dc_in_type;
VARIABLE ex_force_a2 : std_ulogic;
VARIABLE ex_load : std_ulogic;
VARIABLE ex_ymsb : std_ulogic;
VARIABLE ex_op1 : word;
VARIABLE ex_op2 : word;
VARIABLE ex_result : word;
VARIABLE ex_result2 : word;
VARIABLE mul_op2 : word;
VARIABLE ex_shcnt : std_logic_vector ( 4 downto 0 );
VARIABLE ex_dsuen : std_ulogic;
VARIABLE ex_ldbp2 : std_ulogic;
VARIABLE ex_sari : std_ulogic;
VARIABLE me_inull : std_ulogic;
VARIABLE me_nullify : std_ulogic;
VARIABLE me_nullify2 : std_ulogic;
VARIABLE me_iflush : std_ulogic;
VARIABLE me_newtt : std_logic_vector ( 5 downto 0 );
VARIABLE me_asr18 : word;
VARIABLE me_signed : std_ulogic;
VARIABLE me_size : std_logic_vector ( 1 downto 0 );
VARIABLE me_laddr : std_logic_vector ( 1 downto 0 );
VARIABLE me_icc : std_logic_vector ( 3 downto 0 );
VARIABLE xc_result : word;
VARIABLE xc_df_result : word;
VARIABLE xc_waddr : std_logic_vector ( 9 downto 0 );
VARIABLE xc_exception : std_ulogic;
VARIABLE xc_wreg : std_ulogic;
VARIABLE xc_trap_address : pctype;
VARIABLE xc_vectt : std_logic_vector ( 7 downto 0 );
VARIABLE xc_trap : std_ulogic;
VARIABLE xc_fpexack : std_ulogic;
VARIABLE xc_rstn : std_ulogic;
VARIABLE xc_halt : std_ulogic;
VARIABLE diagdata : word;
VARIABLE tbufi : tracebuf_in_type;
VARIABLE dbgm : std_ulogic;
VARIABLE fpcdbgwr : std_ulogic;
VARIABLE vfpi : fpc_in_type;
VARIABLE dsign : std_ulogic;
VARIABLE pwrd : std_ulogic;
VARIABLE sidle : std_ulogic;
VARIABLE vir : irestart_register;
VARIABLE icnt : std_ulogic;
VARIABLE tbufcntx : std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
BEGIN
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( 7 downto 0 ) := r.x.ctrl.rd ( 7 downto 0 );
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
IF r.x.mexc = '1' THEN
xc_vectt := "00" & TT_DAEX;
ELSIF r.x.ctrl.tt = TT_TICC THEN
xc_vectt := '1' & r.x.result ( 6 downto 0 );
ELSE
xc_vectt := "00" & r.x.ctrl.tt;
END IF;
IF r.w.s.svt = '0' THEN
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & xc_vectt;
ELSE
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & "00000000";
END IF;
xc_trap_address ( 3 downto 2 ) := ( OTHERS => '0' );
xc_wreg := '0';
v.x.annul_all := '0';
IF ( r.x.ctrl.ld = '1' ) THEN
xc_result := r.x.data ( 0 );
ELSE
xc_result := r.x.result;
END IF;
xc_df_result := xc_result;
dbgm := dbgexc ( r , dbgi , xc_trap , xc_vectt );
IF ( dbgi.dsuen and dbgi.dbreak ) = '0' THEN
v.x.debug := '0';
END IF;
pwrd := '0';
CASE r.x.rstate IS
WHEN run =>
IF ( not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug ) = '1' THEN
icnt := holdn;
END IF;
IF dbgm = '1' THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find ( r );
vdsu.tt := xc_vectt;
vdsu.err := dbgerr ( r , dbgi , xc_vectt );
ELSIF ( pwrd = '1' ) and ( ir.pwd = '0' ) THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find ( r );
vp.pwd := '1';
ELSIF ( r.x.ctrl.annul or xc_trap ) = '0' THEN
xc_wreg := r.x.ctrl.wreg;
sp_write ( r , wpr , v.w.s , vwpr );
vir.pwd := '0';
ELSIF ( ( not r.x.ctrl.annul ) and xc_trap ) = '1' THEN
xc_exception := '1';
xc_result := r.x.ctrl.pc ( 31 downto 2 ) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := ( OTHERS => '0' );
xc_waddr ( 6 downto 0 ) := r.w.s.cwp & "0001";
v.x.npc := npc_find ( r );
fpexack ( r , xc_fpexack );
IF r.w.s.et = '0' THEN
xc_wreg := '0';
END IF;
END IF;
WHEN trap =>
xc_result := npc_gen ( r );
xc_wreg := '1';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( 6 downto 0 ) := r.w.s.cwp & "0010";
IF ( r.w.s.et = '1' ) THEN
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
ELSE
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
END IF;
WHEN dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
xc_trap_address ( 31 downto 2 ) := ir.addr;
vir.addr := npc_gen ( r ) ( 31 downto 2 );
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
WHEN dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
sidle := ( rp.pwd or rp.error ) and ico.idle and dco.idle and not r.x.debug;
IF dbgi.reset = '1' THEN
vp.pwd := '0';
vp.error := '0';
END IF;
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.debug := '1';
END IF;
diagwr ( r , dsur , ir , dbgi , wpr , v.w.s , vwpr , vdsu.asi , xc_trap_address , vir.addr , vdsu.tbufcnt , xc_wreg , xc_waddr , xc_result , fpcdbgwr );
xc_halt := dbgi.halt;
IF r.x.ipend = '1' THEN
vp.pwd := '0';
END IF;
IF ( rp.error or rp.pwd or r.x.debug or xc_halt ) = '0' THEN
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address ( 31 downto 2 ) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
irq_intack ( r , holdn , v.x.intack );
itrace ( r , dsur , vdsu , xc_result , xc_exception , dbgi , rp.error , xc_trap , tbufcntx , tbufi );
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
IF ( r.x.rstate = dsu2 ) THEN
v.w.except := '0';
END IF;
v.w.wa := xc_waddr ( 7 downto 0 );
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= ( xc_wreg and holdn ) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt ( 3 downto 0 );
irqo.pwd <= rp.pwd;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
IF ( xc_rstn = '0' ) THEN
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
v.w.s.tt := ( OTHERS => '0' );
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.rstate := dsu1;
v.x.debug := '1';
END IF;
END IF;
v.w.s.ef := '0';
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result ( 1 downto 0 );
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res ( r , v.w.s.asr18 , v.x.result , v.x.y , me_asr18 , me_icc );
mem_trap ( r , wpr , v.x.ctrl.annul , holdn , v.x.ctrl.trap , me_iflush , me_nullify , v.m.werr , v.x.ctrl.tt );
me_newtt := v.x.ctrl.tt;
irq_trap ( r , ir , irqi.irl , v.x.ctrl.annul , v.x.ctrl.pv , v.x.ctrl.trap , me_newtt , me_nullify , v.m.irqen , v.m.irqen2 , me_nullify2 , v.x.ctrl.trap , v.x.ipend , v.x.ctrl.tt );
IF ( r.m.ctrl.ld or not dco.mds ) = '1' THEN
v.x.data ( 0 ) := dco.data ( 0 );
v.x.data ( 1 ) := dco.data ( 1 );
v.x.set := dco.set ( 0 downto 0 );
IF dco.mds = '0' THEN
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
ELSE
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
END IF;
v.x.data ( 0 ) := ld_align ( v.x.data , v.x.set , me_size , me_laddr , me_signed );
END IF;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
IF ( r.x.rstate = dsu2 ) THEN
me_nullify2 := '0';
v.x.set := dco.set ( 0 downto 0 );
END IF;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
IF r.e.ldbp1 = '1' THEN
ex_op1 := r.x.data ( 0 );
ex_sari := r.x.data ( 0 ) ( 31 ) and r.e.ctrl.inst ( 19 ) and r.e.ctrl.inst ( 20 );
END IF;
IF r.e.ldbp2 = '1' THEN
ex_op2 := r.x.data ( 0 );
ex_ymsb := r.x.data ( 0 ) ( 0 );
mul_op2 := ex_op2;
ex_shcnt := r.x.data ( 0 ) ( 4 downto 0 );
IF r.e.invop2 = '1' THEN
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
END IF;
END IF;
ex_add_res := ( ex_op1 & '1' ) + ( ex_op2 & r.e.alucin );
IF ex_add_res ( 2 downto 1 ) = "00" THEN
v.m.nalign := '0';
ELSE
v.m.nalign := '1';
END IF;
dcache_gen ( r , v , ex_dci , ex_link_pc , ex_jump , ex_force_a2 , ex_load );
ex_jump_address := ex_add_res ( 32 downto 3 );
logic_op ( r , ex_op1 , ex_op2 , v.x.y , ex_ymsb , ex_logic_res , v.m.y );
ex_shift_res := shift ( r , ex_op1 , ex_op2 , ex_shcnt , ex_sari );
misc_op ( r , wpr , ex_op1 , ex_op2 , xc_df_result , v.x.y , ex_misc_res , ex_edata );
ex_add_res ( 3 ) := ex_add_res ( 3 ) or ex_force_a2;
alu_select ( r , ex_add_res , ex_op1 , ex_op2 , ex_shift_res , ex_logic_res , ex_misc_res , ex_result , me_icc , v.m.icc , v.m.divz );
dbg_cache ( holdn , dbgi , r , dsur , ex_result , ex_dci , ex_result2 , v.m.dci );
fpstdata ( r , ex_edata , ex_result2 , fpo.data , ex_edata2 , v.m.result );
cwp_ex ( r , v.m.wcwp );
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
IF ( r.x.rstate = dsu2 ) THEN
v.m.ctrl.ld := '1';
END IF;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res ( 32 downto 1 );
dci.edata <= ex_edata2;
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect ( r , wpr , dbgi , r.a.ctrl.trap , r.a.ctrl.tt , v.e.ctrl.trap , v.e.ctrl.tt );
op_mux ( r , rfo.data1 , v.m.result , v.x.result , xc_df_result , "00000000000000000000000000000000" , r.a.rsel1 , v.e.ldbp1 , ra_op1 );
op_mux ( r , rfo.data2 , v.m.result , v.x.result , xc_df_result , r.a.imm , r.a.rsel2 , ex_ldbp2 , ra_op2 );
alu_op ( r , ra_op1 , ra_op2 , v.m.icc , v.m.y ( 0 ) , ex_ldbp2 , v.e.op1 , v.e.op2 , v.e.aluop , v.e.alusel , v.e.aluadd , v.e.shcnt , v.e.sari , v.e.shleft , v.e.ymsb , v.e.mul , ra_div , v.e.mulstep , v.e.mac , v.e.ldbp2 , v.e.invop2 );
cin_gen ( r , v.m.icc ( 0 ) , v.e.alucin );
de_inst := r.d.inst ( conv_integer ( r.d.set ) );
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select ( r , v.w.s.ps , v.w.s.s , v.w.s.et , v.a.su , v.a.et );
wicc_y_gen ( de_inst , v.a.ctrl.wicc , v.a.ctrl.wy );
cwp_ctrl ( r , v.w.s.wim , de_inst , de_cwp , v.a.wovf , v.a.wunf , de_wcwp );
rs1_gen ( r , de_inst , v.a.rs1 , de_rs1mod );
de_rs2 := de_inst ( 4 downto 0 );
de_raddr1 := ( OTHERS => '0' );
de_raddr2 := ( OTHERS => '0' );
IF de_rs1mod = '1' THEN
regaddr ( r.d.cwp , de_inst ( 29 downto 26 ) & v.a.rs1 ( 0 ) , de_raddr1 ( 7 downto 0 ) );
ELSE
regaddr ( r.d.cwp , de_inst ( 18 downto 15 ) & v.a.rs1 ( 0 ) , de_raddr1 ( 7 downto 0 ) );
END IF;
regaddr ( r.d.cwp , de_rs2 , de_raddr2 ( 7 downto 0 ) );
v.a.rfa1 := de_raddr1 ( 7 downto 0 );
v.a.rfa2 := de_raddr2 ( 7 downto 0 );
rd_gen ( r , de_inst , v.a.ctrl.wreg , v.a.ctrl.ld , de_rd );
regaddr ( de_cwp , de_rd , v.a.ctrl.rd );
fpbranch ( de_inst , fpo.cc , de_fbranch );
fpbranch ( de_inst , cpo.cc , de_cbranch );
v.a.imm := imm_data ( r , de_inst );
lock_gen ( r , de_rs2 , de_rd , v.a.rfa1 , v.a.rfa2 , v.a.ctrl.rd , de_inst , fpo.ldlock , v.e.mul , ra_div , v.a.ldcheck1 , v.a.ldcheck2 , de_ldlock , v.a.ldchkra , v.a.ldchkex );
ic_ctrl ( r , de_inst , v.x.annul_all , de_ldlock , branch_true ( de_icc , de_inst ) , de_fbranch , de_cbranch , fpo.ccv , cpo.ccv , v.d.cnt , v.d.pc , de_branch , v.a.ctrl.annul , v.d.annul , v.a.jmpl , de_inull , v.d.pv , v.a.ctrl.pv , de_hold_pc , v.a.ticc , v.a.ctrl.rett , v.a.mulstart , v.a.divstart );
cwp_gen ( r , v , v.a.ctrl.annul , de_wcwp , de_cwp , v.d.cwp );
v.d.inull := ra_inull_gen ( r , v );
op_find ( r , v.a.ldchkra , v.a.ldchkex , v.a.rs1 , v.a.rfa1 , false , v.a.rfe1 , v.a.rsel1 , v.a.ldcheck1 );
op_find ( r , v.a.ldchkra , v.a.ldchkex , de_rs2 , v.a.rfa2 , imm_select ( de_inst ) , v.a.rfe2 , v.a.rsel2 , v.a.ldcheck2 );
de_branch_address := branch_address ( de_inst , r.d.pc );
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
IF holdn = '0' THEN
de_raddr1 ( 7 downto 0 ) := r.a.rfa1;
de_raddr2 ( 7 downto 0 ) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
ELSE
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
END IF;
IF ( ( dbgi.denable and not dbgi.dwrite ) = '1' ) and ( r.x.rstate = dsu2 ) THEN
de_raddr1 ( 7 downto 0 ) := dbgi.daddr ( 9 downto 2 );
de_ren1 := '1';
END IF;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
IF ( xc_rstn = '0' ) THEN
v.d.cnt := ( OTHERS => '0' );
END IF;
npc := r.f.pc;
IF ( xc_rstn = '0' ) THEN
v.f.pc := ( OTHERS => '0' );
v.f.branch := '0';
v.f.pc ( 31 downto 12 ) := conv_std_logic_vector ( 16#00000# , 20 );
ELSIF xc_exception = '1' THEN
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
ELSIF de_hold_pc = '1' THEN
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
IF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
END IF;
ELSIF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
ELSIF de_branch = '1' THEN
v.f.pc := branch_address ( de_inst , r.d.pc );
v.f.branch := '1';
npc := v.f.pc;
ELSE
v.f.branch := '0';
v.f.pc ( 31 downto 2 ) := r.f.pc ( 31 downto 2 ) + 1;
npc := v.f.pc;
END IF;
ici.dpc <= r.d.pc ( 31 downto 2 ) & "00";
ici.fpc <= r.f.pc ( 31 downto 2 ) & "00";
ici.rpc <= npc ( 31 downto 2 ) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= ( OTHERS => '0' );
ici.flushl <= '0';
IF ( ico.mds and de_hold_pc ) = '0' THEN
v.d.inst ( 0 ) := ico.data ( 0 );
v.d.inst ( 1 ) := ico.data ( 1 );
v.d.set := ico.set ( 0 downto 0 );
v.d.mexc := ico.mexc;
END IF;
diagread ( dbgi , r , dsur , ir , wpr , rfo.data1 , dco , tbo , diagdata );
diagrdy ( dbgi.denable , dsur , r.m.dci , dco.mds , ico , vdsu.crdy );
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst ( 19 );
muli.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
muli.op2 <= ( mul_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & mul_op2;
muli.mac <= r.e.ctrl.inst ( 24 );
muli.acc ( 39 downto 32 ) <= r.x.y ( 7 downto 0 );
muli.acc ( 31 downto 0 ) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst ( 19 );
divi.flush <= r.x.annul_all;
divi.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
divi.op2 <= ( ex_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op2;
IF ( r.a.divstart and not r.a.ctrl.annul ) = '1' THEN
dsign := r.a.ctrl.inst ( 19 );
ELSE
dsign := r.e.ctrl.inst ( 19 );
END IF;
divi.y <= ( r.m.y ( 31 ) and dsign ) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy ( 2 );
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
END PROCESS;
preg : PROCESS ( sclk )
BEGIN
IF rising_edge ( sclk ) THEN
rp <= rpin;
IF rstn = '0' THEN
rp.error <= '0';
END IF;
END IF;
END PROCESS;
reg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF ( holdn = '1' ) THEN
r <= rin;
ELSE
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
IF ( holdn or ico.mds ) = '0' THEN
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
END IF;
IF ( holdn or dco.mds ) = '0' THEN
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
END IF;
END IF;
IF rstn = '0' THEN
r.w.s.s <= '1';
END IF;
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackStateM1 <= '1';
ELSE
hackStateM1 <= '0';
END IF;
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" ) THEN
r.w.s.s <= hackStateM1 OR rin.w.s.s;
ELSE
r.w.s.s <= rin.w.s.s;
END IF;
END IF;
END PROCESS;
dsureg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
dsur <= dsuin;
ELSE
dsur.crdy <= dsuin.crdy;
END IF;
END IF;
END PROCESS;
dsureg2 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
ir <= irin;
END IF;
END IF;
END PROCESS;
wpreg0 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 0 ) <= wprin ( 0 );
END IF;
IF rstn = '0' THEN
wpr ( 0 ).exec <= '0';
wpr ( 0 ).load <= '0';
wpr ( 0 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpreg1 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 1 ) <= wprin ( 1 );
END IF;
IF rstn = '0' THEN
wpr ( 1 ).exec <= '0';
wpr ( 1 ).load <= '0';
wpr ( 1 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpr ( 2 ) <= ( "000000000000000000000000000000" , "000000000000000000000000000000" , '0' , '0' , '0' );
wpr ( 3 ) <= ( "000000000000000000000000000000" , "000000000000000000000000000000" , '0' , '0' , '0' );
dummy <= '1';
END ARCHITECTURE;
| mit | 15117e6c72ab625470b513ed0665ac9b | 0.387286 | 4.096648 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddr2sp16a.vhd | 2 | 30,556 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2sp16a
-- File: ddr2sp16a.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: 16-bit DDR2 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddr2sp16a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddr2sp16a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant odtvalue : std_logic_vector(1 downto 0) := conv_std_logic_vector(odten, 2);
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDR2SP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr0, wr1, wr2, wr3, wr4a, wr4b, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode23, emode, lmode, emodeocd, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cal_rst : std_logic;
readdly : std_logic_vector(1 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
write : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
sync : std_logic_vector(2 downto 1);
startsd_ack : std_logic;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(4 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(3 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector(1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
waddr_d : std_logic_vector(abuf-1 downto 0); -- Same as waddr but delayed to compensate for pipelined output data
cfg : sdram_cfg_type;
readdly : std_logic_vector(1 downto 0); -- added read latency
newcom : std_logic; -- start sec. read/write
wdata : std_logic_vector(31 downto 0);
initnopdly : std_logic_vector(7 downto 0); -- 400 ns delay
sync : std_logic;
odt : std_logic_vector(1 downto 0);
end record;
signal vcc, rwrite : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rdata, wdata, rwdata, rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal waddr2 : std_logic_vector(abuf-1 downto 0);
signal ddr_rst : std_logic;
signal ddr_rst_gen : std_logic_vector(3 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst); -- Reset signal in DDR clock domain
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
variable ready : std_logic;
begin
v := ra; v.hrdata := rdata; v.hresp := HRESP_OKAY;
v.write := '0';
-- Sync ------------------------------------------------
v.sync(1) := r.startsdold; v.sync(2) := ra.sync(1);
ready := ra.startsd_ack xor ra.sync(2);
--------------------------------------------------------
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else v.state := dwrite; v.hready := '1'; v.write := '1'; end if;
end if;
v.raddr := ra.haddr(7 downto 2);
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ready = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
v.state := midle; v.hready := not (v.hsel and v.htrans(1));
if (v.hsel and v.htrans(1) and v.hwrite) = '1' then
v.state := dwrite; v.hready := '1'; v.write := '1';
end if;
v.startsd_ack := ra.startsd;
end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.write := '1'; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or ((ra.haddr(4 downto 2) = "111") and (ra.write = '1')) then
v.startsd := not ra.startsd; v.state := whold1;
v.write := '0'; v.hready := not (v.hsel and v.htrans(1));
end if;
when whold1 =>
v.state := whold2;
when whold2 =>
if ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
v.startsd_ack := ra.startsd;
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.startsd_ack := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(ddr_rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable dqm : std_logic_vector(3 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable readdata: std_logic_vector(31 downto 0); -- data from DDR
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
readdata := sdi.data(31 downto 0);
v.qdrive :='0';
v.cfg.cal_en := (others => '0'); v.cfg.cal_inc := (others => '0');
v.cfg.cal_rst := '0';
v.wdata := wdata; -- pipeline output data
regsd := (others => '0');
if ra.acc.haddr(3 downto 2) = "00" then
regsd(31 downto 15) := r.cfg.refon & r.cfg.ocd & r.cfg.emr & '0' & r.cfg.trcd &
r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd(11 downto 0) := r.cfg.refresh;
elsif ra.acc.haddr(3 downto 2) = "01" then
regsd(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd(14 downto 12) := conv_std_logic_vector(1, 3);
else
regsd(17 downto 16) := r.cfg.readdly;
regsd(22 downto 18) := r.cfg.trfc;
regsd(27 downto 23) := r.cfg.twr;
regsd(28) := r.cfg.trp;
end if;
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(1 downto 0) is
when "00" => dqm := "0111";
when "01" => dqm := "1011";
when "10" => dqm := "1101";
when others => dqm := "1110";
end case;
when "01" =>
if ra.acc.haddr(1) = '0' then dqm := "0011"; else dqm := "1100"; end if;
when others => dqm := "0000";
end case;
-- Sync ------------------------------------------
v.sync := ra.startsd; v.startsd := r.sync;
--------------------------------------------------
--v.startsd := ra.startsd;
---- main FSM
--
-- case r.mstate is
-- when midle =>
-- if r.startsd = '1' then
-- if (r.sdstate = sidle) and (r.cfg.command = "000")
-- and (r.cmstate = midle) then
-- startsd := '1'; v.mstate := active;
-- end if;
-- end if;
-- when others => null;
-- end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(23 downto 10);
when "01" => raddr := haddr(24 downto 11);
when "10" => raddr := haddr(25 downto 12);
when others => raddr := haddr(26 downto 13);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "00000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish) then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2;
else v.sdstate := act3;
end if;
--v.waddr := ra.acc.haddr(7 downto 2);
v.waddr := ra.acc.haddr(7 downto 3) & '0'; --& ra.acc.haddr(2);
v.waddr_d := ra.acc.haddr(7 downto 3) & '0'; --& ra.acc.haddr(2);
when act2 =>
v.sdstate := act3;
when act3 =>
v.casn := '0';
--v.address := ra.acc.haddr(13 downto 11) & '0' & ra.acc.haddr(10 downto 2) & '0';
v.address := ra.acc.haddr(13 downto 11) & '0' & ra.acc.haddr(10 downto 3) & "00";
v.hready := ra.acc.hwrite;
if ra.acc.hwrite = '1' then
v.sdstate := wr0;
v.sdwen := '0';
v.waddr := r.waddr + 1;
v.trfc := r.cfg.twr;
else v.sdstate := rd1; end if;
v.burst := '0';
when wr0 =>
v.casn := '1'; v.sdwen := '1'; v.bdrive := '0'; v.qdrive := '1';
if r.waddr_d = ra.acc.haddr(7 downto 2) then
v.dqm := dqm;
v.waddr_d := r.waddr_d + 1;
v.waddr := r.waddr + 1;
v.sdstate := wr1;
if (r.waddr_d /= ra.raddr) then v.hready := '1'; end if;
else
v.burst := '1';
v.waddr_d := r.waddr_d + 1;
v.waddr := r.waddr + 1;
v.dqm := (others => '1');
end if;
if r.burst = '1' and r.address(5 downto 4) < ra.raddr(2 downto 1) then
v.address(5 downto 4) := r.address(5 downto 4) + 1;
v.sdwen := '0'; v.casn := '0';
v.trfc := r.cfg.twr;
end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr_d := r.waddr_d + 1;
v.waddr := r.waddr + 1;
if (r.waddr_d <= ra.raddr) and (r.waddr_d /= "000000") and (r.hready = '1') then
v.hready := '1';
v.burst := '0';
if r.burst = '0' and r.address(5 downto 4) < ra.raddr(2 downto 1) then
v.address(5 downto 4) := r.address(5 downto 4) + 1;
v.sdwen := '0'; v.casn := '0';
v.trfc := r.cfg.twr;
v.burst := '1';
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1');
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1'; v.qdrive := '1';
if r.trfc = "00000" then -- wait to not violate TWR timing
v.sdstate := wr4b;
end if;
when wr4b =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
v.newcom := '1';
when rd7 =>
v.casn := '1'; v.sdstate := rd8;
v.readdly := r.cfg.readdly;
v.newcom := not r.newcom;
if r.address(5 downto 4) /= "11" then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd8 => -- (CL = 3)
v.casn := '1';
v.newcom := not r.newcom;
if r.readdly = "00" then -- add read delay
v.sdstate := rd2;
else
v.readdly := r.readdly - 1;
end if;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
v.newcom := not r.newcom;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
v.newcom := not r.newcom;
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
end if;
if v.hready = '1' then v.waddr := r.waddr + 1; end if;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
v.newcom := not r.newcom;
if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1') then
v.burst := '0';
elsif (r.sdcsn = "11") or (r.waddr(1 downto 0) = "11") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 1; end if;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
readdata := regsd; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
readdata := regsd; v.sdstate := sidle;
writecfg := ra.acc.hwrite; v.startsdold := r.startsd;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := r.cfg.emr; --v.ba := "01";
--v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
if r.cfg.emr = "01" then
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd
& odtvalue(1)&"000"&odtvalue(0)&"00";
else
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
end if;
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
v.address := "00010" & r.cfg.dllrst & "0" & "01" & "10010"; -- CAS = 3 WR = 3
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "00000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
v.ba := "00"; v.cfg.ocd := '0'; v.cfg.emr := "10"; -- EMR(2)
if r.cfg.cke = '1' then
if r.initnopdly = "00000000" then -- 400 ns of NOP and CKE
v.istate := pre; v.cfg.command := CMD_PRE;
else
v.initnopdly := r.initnopdly - 1;
end if;
end if;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode23; else v.istate := lmode; end if;
end if;
when emode23 =>
if r.cfg.command = "000" then
if r.cfg.emr = "11" then
v.cfg.emr := "01"; -- (EMR(1))
v.istate := emode; v.cfg.command := CMD_EMR;
else
v.cfg.emr := "11"; v.cfg.command := CMD_EMR; -- EMR(3)
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := emodeocd;
v.cfg.ocd := '1'; v.cfg.command := CMD_EMR;
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when emodeocd =>
if r.cfg.command = "000" then
if r.cfg.ocd = '0' then -- Exit OCD
v.istate := finish;
v.cfg.refon := '1'; v.cfg.renable := '0';
else -- Default OCD
v.cfg.ocd := '0';
v.cfg.command := CMD_EMR;
end if;
end if;
v.cfg.cal_rst := '1'; -- reset data bit delay
when others =>
if odten /= 0 then v.odt := (others => '1'); end if;
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
v.initnopdly := (others => '1');
v.odt := (others => '0');
end if;
end case;
---- second part of main fsm
--
-- case r.mstate is
-- when active =>
-- if v.hready = '1' then
-- v.mstate := midle;
-- end if;
-- when others => null;
-- end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or (r.cfg.dllrst = '1') then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
if r.waddr(1 downto 0) = "00" then
v.cfg.refresh := r.wdata(11 downto 0);
v.cfg.cke := r.wdata(15);
v.cfg.renable := r.wdata(16);
v.cfg.dllrst := r.wdata(17);
v.cfg.command := r.wdata(20 downto 18);
v.cfg.csize := r.wdata(22 downto 21);
v.cfg.bsize := r.wdata(25 downto 23);
v.cfg.trcd := r.wdata(26);
v.cfg.emr := r.wdata(29 downto 28);
v.cfg.ocd := r.wdata(30);
v.cfg.refon := r.wdata(31);
elsif r.waddr(1 downto 0) = "10" then
v.cfg.cal_en := r.wdata( 7 downto 0);
v.cfg.cal_inc := r.wdata(15 downto 8);
v.cfg.readdly := r.wdata(17 downto 16);
v.cfg.trfc := r.wdata(22 downto 18);
v.cfg.twr := r.wdata(27 downto 23);
v.cfg.trp := r.wdata(28);
v.cfg.cal_rst := r.wdata(31);
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if ddr_rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.cfg.twr := conv_std_logic_vector((15)*MHz/1000+3, 5);
v.refresh := (others => '0');
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
v.cfg.ocd := '0';
v.cfg.readdly := conv_std_logic_vector(readdly, 2);
v.initnopdly := (others => '1');
if MHz > 130 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
if MHz > 130 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.odt := (others => '0');
end if;
ri <= v;
ribdrive <= vbdrive;
rwdata <= readdata;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst, ddr_rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
end if;
if (rst = '0') then
ddr_rst_gen <= "0000";
end if;
if (ddr_rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= "111111111111" & r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
--sdo.data <= zero32 & zero32 & zero32 & wdata;
sdo.data <= zero32 & zero32 & zero32 & r.wdata;
sdo.cal_en <= r.cfg.cal_en;
sdo.cal_inc <= r.cfg.cal_inc;
sdo.cal_rst <= r.cfg.cal_rst;
sdo.odt <= r.odt;
read_buff : syncram_2p
generic map (tech => memtech, abits => 6, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr,
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr, datain => rwdata);
write_buff : syncram_2p
generic map (tech => memtech, abits => 6, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr,
dataout => wdata, wclk => clk_ahb, write => ra.write,
waddress => ra.haddr(7 downto 2), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2sp" & tost(hindex) & ": 16-bit DDR2 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| mit | 0c84deb2df31a711cfac780fdf47c781 | 0.494796 | 3.303351 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/virage/simprims/virage_simprims.vhd | 2 | 18,477 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: virage_simprims
-- File: virage_simprims.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple simulation models for VIRAGE RAMs
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
package virage_simprims is
component virage_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end component;
-- synchronous 2-port ram
component virage_2pram_sim
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end component;
component virage_dpram_sim
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end component;
end;
-- 1-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_syncram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end;
architecture behavioral of virage_syncram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clk, oe, me)
variable memarr : mem;-- := (others => (others => '0'));
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) and (me = '1') and not is_x(addr) then
if (we = '1') then memarr(to_integer(unsigned(addr))) := di; end if;
doint := memarr(to_integer(unsigned(addr)));
end if;
-- if (me and oe) = '1' then do <= doint;
if oe = '1' then do <= doint;
else do <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous 2-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_2pram_sim is
generic (
abits : integer := 10;
dbits : integer := 8;
words : integer := 1024
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end;
architecture behavioral of virage_2pram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (words-1)) of word;
begin
main : process(clka, clkb, oeb, mea, meb, wea)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra)) mod words) := dia; end if;
end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
doint := memarr(to_integer(unsigned(addrb)) mod words);
end if;
if oeb = '1' then dob <= doint;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous dual-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_dpram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end;
architecture behavioral of virage_dpram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clka, oea, mea, clkb, oeb, meb)
variable memarr : mem;
variable dointa, dointb : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra))) := dia; end if;
dointa := memarr(to_integer(unsigned(addra)));
end if;
if oea = '1' then doa <= dointa;
else doa <= (others => 'Z'); end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
if (web = '1') then memarr(to_integer(unsigned(addrb))) := dib; end if;
dointb := memarr(to_integer(unsigned(addrb)));
end if;
if oeb = '1' then dob <= dointb;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_128x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_128x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 7, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_256x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_256x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 8, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x38cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x38cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 38)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_1024x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_1024x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 10, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_2048x32cm8sw0ab is
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_2048x32cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 11, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_4096x36cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 12, dbits => 36)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end;
architecture behavioral of hdss1_16384x8cm16sw0 is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 14, dbits => 8)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
-- 2-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x40cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x40cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 40, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_168x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_168x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 168)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
-- dual-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_64x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_64x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 6, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_128x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_128x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 7, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_256x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_256x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 8, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x38cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x38cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 38)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_8192x8cm16sw0ab is
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_8192x8cm16sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 13, dbits => 8)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
-- pragma translate_on
| mit | c11840f7d7a878c54309c5c39a103d5b | 0.633977 | 3.166038 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/shadowMode/iu3.vhd | 1 | 111,419 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
signal dataToCache : std_logic_vector(31 downto 0);
signal triggerCPFault : std_ulogic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if(triggerCPFault = '1')then
xc_vectt := "00" & TT_CPDIS;
xc_trap := '1';
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif false and false and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if true then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if false then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not true) and (r.w.s.cwp = "000") then v.w.s.cwp := "111";
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
end if;
if true then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if true then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(7 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.w.s.ef := '0'; -- needed for AX
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := "000";
v.w.s.icc := "0000";
end if;
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := "00000000"; end if;
if true then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to 2-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if false and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if 0 = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000",
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if 2 > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000"; de_raddr2 := "0000000000";
if true then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if true then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2); de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := "000";
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000"; v.f.branch := '0';
if false then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to 2-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(0 downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if true then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if false then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if true then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if true then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then ir <= irin; end if;
end if;
end process;
dummy <= '1';
shadow_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
triggerCPFault <= '0';
IF(dci.write = '1')then
IF(dataToCache = X"6841_636B")THEN
triggerCPFault <= '1';
END IF;
END IF;
end if;
end process;
end;
| mit | 7240d50ae4817d9df56fd99931d57ec7 | 0.518215 | 3.1272 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/syncram.vhd | 2 | 6,173 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram
-- File: syncram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 1-port ram with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allmem.all;
entity syncram is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of syncram is
signal gnd4 : std_logic_vector(3 downto 0);
signal rena, wena : std_logic;
begin
inf : if tech = inferred generate
x0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, write);
end generate;
xcv : if tech = virtex generate
x0 : virtex_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
xc2v : if (tech = virtex2) or (tech = spartan3) or (tech = virtex4)
or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex2_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
vir : if tech = memvirage generate
x0 : virage_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
atrh : if tech = atc18rha generate
x0 : atc18rha_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write, testin);
end generate;
axc : if tech = axcel generate
x0 : axcel_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
proa : if tech = proasic generate
x0 : proasic_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
umc18 : if tech = umc generate
x0 : umc_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
rhu : if tech = rhumc generate
x0 : rhumc_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
proa3 : if tech = apa3 generate
x0 : proasic3_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
ihp : if tech = ihp25 generate
x0 : ihp25_syncram generic map(abits, dbits)
port map(clk, address, datain, dataout, enable, write);
end generate;
ihprh : if tech = ihp25rh generate
x0 : ihp25rh_syncram generic map(abits, dbits)
port map(clk, address, datain, dataout, enable, write);
end generate;
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = cyclone3) generate
x0 : altera_syncram generic map(abits, dbits)
port map(clk, address, datain, dataout, enable, write);
end generate;
rht : if tech = rhlib18t generate
x0 : rh_lib18t_syncram generic map(abits, dbits)
port map(clk, address, datain, dataout, enable, write, gnd4(1 downto 0));
end generate;
lat : if tech = lattice generate
x0 : ec_syncram generic map(abits, dbits)
port map(clk, address, datain, dataout, enable, write);
end generate;
ut025 : if tech = ut25 generate
x0 : ut025crh_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
pere : if tech = peregrine generate
x0 : peregrine_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
cust1 : if tech = custom1 generate
x0 : custom1_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
ecl : if tech = eclipse generate
rena <= enable and not write;
wena <= enable and write;
x0 : eclipse_syncram_2p generic map(abits, dbits)
port map(clk, rena, address, dataout, clk, address,
datain, wena);
end generate;
virage90 : if tech = memvirage90 generate
x0 : virage90_syncram generic map(abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
nex : if tech = easic90 generate
x0 : nextreme_syncram generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write);
end generate;
gnd4 <= "0000";
-- pragma translate_off
noram : if has_sram(tech) = 0 generate
x : process
begin
assert false report "synram: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| mit | a45c5b97bb1d3527d8cca4c7aa0724c9 | 0.638587 | 3.867794 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu3BaseDCE.vhd | 1 | 595,345 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(171 downto 0);
signal or_reduce_1 : std_logic;
signal dfp_delay_start : integer range 0 to 15;
signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right);
signal handlerTrap : std_ulogic;
signal dfp_bscan_cntrl1 : STD_LOGIC_VECTOR(35 downto 0);
signal dfp_bscan_value : STD_LOGIC_VECTOR(171 downto 0);
component scope
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
ASYNC_IN : IN STD_LOGIC_VECTOR(171 DOWNTO 0)
);
end component;
component iconScope
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0)
);
end component;
attribute syn_black_box : boolean;
attribute syn_noprune : integer;
attribute syn_black_box of iconScope: component is true;
attribute syn_black_box of scope: component is true;
attribute syn_noprune of iconScope: component is 1;
attribute syn_noprune of scope: component is 1;
-- Signals that serve as shadow signals for variables used in the pairs
signal V_A_ET_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow : STD_LOGIC_VECTOR(4 downto 3);
signal ICNT_shadow : STD_ULOGIC;
signal EX_OP1_shadow : WORD;
signal V_M_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal DE_REN1_shadow : STD_ULOGIC;
signal DE_INST_shadow : WORD;
signal V_A_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_W_S_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_RESULT6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_E_ALUCIN_shadow : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_A_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_RESULT1DOWNTO0_shadow : std_logic_vector(1 downto 0);
signal EX_SHCNT_shadow : ASI_TYPE;
signal V_M_DCI_SIZE_shadow : OP_TYPE;
signal V_X_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_MEXC_shadow : STD_ULOGIC;
signal TBUFCNTX_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_A_CTRL_WY_shadow : STD_ULOGIC;
signal NPC_shadow : PCTYPE;
signal V_M_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_MULSTART_shadow : STD_ULOGIC;
signal XC_VECTT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_TT_shadow : OP3_TYPE;
signal DSIGN_shadow : STD_ULOGIC;
signal V_E_CTRL_ANNUL_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow : PCTYPE;
signal V_A_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_RFE1_shadow : STD_ULOGIC;
signal V_W_WA_shadow : RFATYPE;
signal V_X_ANNUL_ALL_shadow : STD_ULOGIC;
signal EX_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES_shadow : STD_LOGIC_VECTOR(32 downto 0);
signal VIR_ADDR_shadow : PCTYPE;
signal EX_JUMP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_CWP_shadow : CWPTYPE;
signal V_D_INST0_shadow : std_logic_vector(31 downto 0);
signal V_A_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_DATA1_shadow : std_logic_vector(31 downto 0);
signal VP_PWD_shadow : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA00_shadow : STD_LOGIC;
signal V_M_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_PS_shadow : STD_ULOGIC;
signal V_X_CTRL_TT_shadow : OP3_TYPE;
signal V_D_STEP_shadow : STD_ULOGIC;
signal V_X_CTRL_WICC_shadow : STD_ULOGIC;
signal VIR_ADDR31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_X_RESULT_shadow : WORD;
signal V_D_CNT_shadow : OP_TYPE;
signal XC_VECTT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_W_S_EF_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow : std_logic_vector(4 downto 0);
signal V_X_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_M_NALIGN_shadow : STD_ULOGIC;
signal XC_WREG_shadow : STD_ULOGIC;
signal V_A_RFA2_shadow : RFATYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow : STD_LOGIC_VECTOR(32 downto 13);
signal EX_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_SU_shadow : STD_ULOGIC;
signal V_E_OP2_shadow : WORD;
signal EX_FORCE_A2_shadow : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_OP131_shadow : STD_LOGIC;
signal V_X_DCI_shadow : DC_IN_TYPE;
signal V_E_CTRL_WICC_shadow : STD_ULOGIC;
signal EX_OP13_shadow : STD_LOGIC;
signal V_F_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST_shadow : WORD;
signal V_E_CTRL_LD_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
signal V_E_SARI_shadow : STD_ULOGIC;
signal V_E_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_PV_shadow : STD_ULOGIC;
signal VDSU_CRDY2_shadow : STD_LOGIC;
signal MUL_OP2_shadow : WORD;
signal XC_EXCEPTION_shadow : STD_ULOGIC;
signal V_E_OP1_shadow : WORD;
signal VP_ERROR_shadow : STD_ULOGIC;
signal V_M_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal MUL_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_M_DCI_shadow : DC_IN_TYPE;
signal EX_OP23_shadow : STD_LOGIC;
signal V_X_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_A_DIVSTART_shadow : STD_ULOGIC;
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal VDSU_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_CTRL_CNT_shadow : OP_TYPE;
signal V_E_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_RFE2_shadow : STD_ULOGIC;
signal V_E_OP13_shadow : STD_LOGIC;
signal V_A_CWP_shadow : CWPTYPE;
signal ME_SIZE_shadow : OP_TYPE;
signal V_X_MAC_shadow : STD_ULOGIC;
signal V_M_CTRL_INST_shadow : WORD;
signal VIR_ADDR31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST20_shadow : STD_LOGIC;
signal DE_REN2_shadow : STD_ULOGIC;
signal V_E_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_MAC_shadow : STD_ULOGIC;
signal V_X_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal EX_ADD_RES3_shadow : STD_LOGIC;
signal V_X_CTRL_INST_shadow : WORD;
signal V_M_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow : OP_TYPE;
signal V_M_CTRL_ANNUL_shadow : STD_ULOGIC;
signal DE_INST19_shadow : STD_LOGIC;
signal XC_HALT_shadow : STD_ULOGIC;
signal V_E_OP231_shadow : STD_LOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_M_CTRL_WICC_shadow : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow : STD_ULOGIC;
signal V_W_S_S_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CWP_shadow : CWPTYPE;
signal V_A_STEP_shadow : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_CTRL_TRAP_shadow : STD_ULOGIC;
signal NPC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_INTACK_shadow : STD_ULOGIC;
signal SIDLE_shadow : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_DATA03_shadow : STD_LOGIC;
signal V_A_CTRL_INST19_shadow : STD_LOGIC;
signal V_W_S_SVT_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_LADDR_shadow : OP_TYPE;
signal V_W_S_DWT_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_TBA_shadow : STD_LOGIC_VECTOR(19 downto 0);
signal XC_WADDR6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_M_MUL_shadow : STD_ULOGIC;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_Y31_shadow : STD_LOGIC;
signal V_E_OP23_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal DE_RADDR17DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_X_DEBUG_shadow : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_CTRL_WREG_shadow : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow : STD_LOGIC;
signal V_D_MEXC_shadow : STD_ULOGIC;
signal V_W_RESULT_shadow : WORD;
signal VFPI_DBG_ENABLE_shadow : STD_ULOGIC;
signal EX_OP131_shadow : STD_LOGIC;
signal V_D_INST1_shadow : std_logic_vector(31 downto 0);
signal V_W_EXCEPT_shadow : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal ME_LADDR_shadow : OP_TYPE;
signal V_X_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_CTRL_RETT_shadow : STD_ULOGIC;
signal XC_WADDR7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_M_MAC_shadow : STD_ULOGIC;
signal V_D_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal VIR_ADDR3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_D_CWP_shadow : CWPTYPE;
signal DE_INST20_shadow : STD_LOGIC;
signal V_D_ANNUL_shadow : STD_ULOGIC;
signal EX_OP2_shadow : WORD;
signal EX_SARI_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DCI_SIZE_shadow : OP_TYPE;
signal V_M_Y_shadow : WORD;
signal V_X_CTRL_PC_shadow : PCTYPE;
signal V_X_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal V_A_CTRL_PC_shadow : PCTYPE;
signal V_A_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_INST20_shadow : STD_LOGIC;
signal V_E_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA0_shadow : std_logic_vector(31 downto 0);
signal V_E_CTRL_INST19_shadow : STD_LOGIC;
signal ME_SIGNED_shadow : STD_ULOGIC;
signal V_W_WREG_shadow : STD_ULOGIC;
signal V_D_PC_shadow : PCTYPE;
signal VFPI_D_ANNUL_shadow : STD_ULOGIC;
signal DE_RADDR27DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC_shadow : PCTYPE;
signal V_X_DATA031_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_X_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT_shadow : OP3_TYPE;
signal V_X_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_INST24_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_NERROR_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_W_S_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_F_BRANCH_shadow : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow : STD_ULOGIC;
signal V_A_CTRL_LD_shadow : STD_ULOGIC;
signal V_A_CTRL_TT_shadow : OP3_TYPE;
signal V_M_CTRL_LD_shadow : STD_ULOGIC;
signal V_E_SHCNT_shadow : ASI_TYPE;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST_shadow : WORD;
signal V_A_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal VIR_PWD_shadow : STD_ULOGIC;
signal XC_RESULT_shadow : WORD;
signal V_A_RFA1_shadow : RFATYPE;
signal V_E_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal ME_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal DE_INST24_shadow : STD_LOGIC;
signal XC_TRAP_shadow : STD_ULOGIC;
signal VDSU_TBUFCNT_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal XC_TRAP_ADDRESS_shadow : PCTYPE;
-- Intermediate value holding signal declarations
signal V_E_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal V_M_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_RFA1_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_4 : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_2 : STD_LOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal V_X_DATA00_shadow_intermed_3 : STD_LOGIC;
signal RIN_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WICC_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_3 : STD_ULOGIC;
signal RPIN_PWD_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal DE_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DBGI_DADDR9DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(9 downto 2);
signal R_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_STEP_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_7 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_1 : STD_LOGIC;
signal V_D_INST0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_YMSB_intermed_1 : STD_ULOGIC;
signal R_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_X_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_F_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_DATA04DOWNTO0_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal R_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal R_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal RIN_M_DCI_LOCK_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal R_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_ET_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal DBGI_STEP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_X_LADDR_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_WA_intermed_1 : std_logic_vector(7 downto 0);
signal V_D_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_2 : STD_LOGIC;
signal V_M_RESULT1DOWNTO0_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_DATA03_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_intermed_1 : DC_IN_TYPE;
signal DSUIN_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_D_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal ICO_MEXC_intermed_1 : STD_ULOGIC;
signal R_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_DCI_SIZE_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_W_S_S_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal R_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_S_ET_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal VIR_ADDR31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_8 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_X_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal DCO_DATA00_intermed_2 : STD_LOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal R_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_X_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_X_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal IR_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_X_DATA1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal ICO_MEXC_intermed_3 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal R_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_WICC_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_5 : STD_ULOGIC;
signal RIN_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal R_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_M_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_7 : std_logic_vector(31 downto 4);
signal RIN_E_OP13_intermed_1 : STD_LOGIC;
signal RIN_A_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_OP2_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal R_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_M_Y31_intermed_2 : STD_LOGIC;
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal XC_VECTT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_4 : STD_ULOGIC;
signal RIN_W_S_TBA_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal V_D_INST1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DATA031_intermed_1 : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 13);
signal R_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_X_DATA031_intermed_1 : STD_LOGIC;
signal R_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_SARI_intermed_1 : STD_ULOGIC;
signal R_M_Y31_intermed_1 : STD_LOGIC;
signal IR_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_W_S_S_shadow_intermed_2 : STD_ULOGIC;
signal DE_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal V_A_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow_intermed_2 : std_logic_vector(4 downto 0);
signal R_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal DCO_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_X_DATA0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_E_OP131_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST19_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal V_X_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_RFE2_shadow_intermed_1 : STD_ULOGIC;
signal V_M_Y_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal DE_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_MEXC_shadow_intermed_4 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_W_S_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal R_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal IR_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal R_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow_intermed_1 : STD_ULOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_X_DATA04DOWNTO0_intermed_3 : std_logic_vector(4 downto 0);
signal V_X_NERROR_shadow_intermed_1 : STD_ULOGIC;
signal V_A_RFE1_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal ICO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal VIR_ADDR_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_W_S_DWT_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_X_NERROR_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_5 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal IRIN_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal V_X_DATA00_shadow_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_M_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal R_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_DEBUG_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PV_intermed_4 : STD_ULOGIC;
signal R_E_MAC_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal IR_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_JMPL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal RIN_M_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_X_DATA04DOWNTO0_shadow_intermed_3 : std_logic_vector(4 downto 0);
signal RIN_W_S_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_DATA031_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_3 : STD_LOGIC;
signal DCO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_X_DATA0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 : std_logic_vector(3 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RPIN_ERROR_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_W_S_S_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal V_A_RFA1_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_CTRL_shadow_intermed_3 : PIPELINE_CTRL_TYPE;
signal R_D_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_1 : STD_LOGIC;
signal V_A_DIVSTART_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_4 : STD_ULOGIC;
signal RIN_W_S_PS_intermed_1 : STD_ULOGIC;
signal R_D_MEXC_intermed_3 : STD_ULOGIC;
signal RIN_A_RFA2_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_W_S_SVT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_4 : std_logic_vector(6 downto 0);
signal RIN_E_OP23_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_D_MEXC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_7 : std_logic_vector(31 downto 4);
signal R_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_8 : std_logic_vector(31 downto 12);
signal VP_PWD_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_NALIGN_intermed_1 : STD_ULOGIC;
signal RP_ERROR_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_W_S_TBA_shadow_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal R_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_JMPL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_RFE2_intermed_1 : STD_ULOGIC;
signal RIN_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_M_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_E_MAC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal IRIN_ADDR_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_CWP_shadow_intermed_2 : std_logic_vector(2 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_A_MULSTART_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_M_DCI_SIGNED_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal IRIN_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal V_M_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_DCI_SIGNED_shadow_intermed_2 : STD_ULOGIC;
signal R_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST19_intermed_3 : STD_LOGIC;
signal V_E_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_X_DATA1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_CWP_intermed_2 : std_logic_vector(2 downto 0);
signal R_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_A_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal DCO_DATA031_intermed_2 : STD_LOGIC;
signal R_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_E_YMSB_shadow_intermed_1 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_M_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DE_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal VIR_ADDR3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_3 : PIPELINE_CTRL_TYPE;
signal RIN_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_A_DIVSTART_intermed_1 : STD_ULOGIC;
signal VIR_ADDR31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_X_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal DSUR_CRDY2_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST_intermed_4 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal DE_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_MULSTART_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_M_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 3);
signal V_A_CTRL_PV_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_WREG_shadow_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_W_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal R_D_ANNUL_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_E_SARI_shadow_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal R_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_M_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal DSUIN_CRDY2_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_M_DCI_SIZE_intermed_2 : std_logic_vector(1 downto 0);
signal DE_INST19_shadow_intermed_3 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_ANNUL_shadow_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal IRIN_PWD_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_5 : STD_ULOGIC;
signal RIN_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TRAP_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal R_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_DATA03_intermed_1 : STD_LOGIC;
signal R_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal R_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_X_MAC_intermed_1 : STD_ULOGIC;
signal V_E_SHCNT_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_OP23_shadow_intermed_1 : STD_LOGIC;
signal V_D_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal R_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_W_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_LADDR_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_5 : std_logic_vector(31 downto 2);
signal XC_VECTT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal V_D_STEP_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal DE_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_5 : STD_ULOGIC;
signal RIN_X_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_F_BRANCH_intermed_1 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_DATA00_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_JMPL_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal DSUR_CRDY2_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA00_intermed_3 : STD_LOGIC;
signal R_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_OP131_intermed_1 : STD_LOGIC;
signal R_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal DE_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_ET_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST20_intermed_3 : STD_LOGIC;
signal RIN_W_EXCEPT_intermed_1 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_2 : STD_LOGIC;
signal R_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal R_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal VIR_ADDR31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_M_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal VIR_ADDR3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_ANNUL_shadow_intermed_3 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal R_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal R_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_E_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST24_intermed_3 : STD_LOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal DE_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PV_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal R_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_MAC_intermed_1 : STD_ULOGIC;
signal R_X_DATA00_intermed_2 : STD_LOGIC;
signal RIN_E_MAC_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_INTACK_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_ANNUL_intermed_5 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_X_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal DE_INST20_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal IR_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_ALUCIN_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_E_OP13_shadow_intermed_1 : STD_LOGIC;
signal V_A_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_6 : std_logic_vector(3 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_7 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal R_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal R_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_WREG_intermed_4 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal R_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal IRIN_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_OP1_intermed_1 : std_logic_vector(31 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal DE_INST20_shadow_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_E_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_M_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_INTACK_intermed_1 : STD_ULOGIC;
signal RIN_E_OP231_intermed_1 : STD_LOGIC;
signal RIN_X_DATA031_intermed_3 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_F_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_ET_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_3 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal ICO_MEXC_intermed_2 : STD_ULOGIC;
signal V_X_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_STEP_intermed_1 : STD_ULOGIC;
signal V_E_ALUCIN_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_M_MUL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal R_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_D_INST0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DCO_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO12_shadow_intermed_8 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WY_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal V_M_DCI_shadow_intermed_1 : DC_IN_TYPE;
signal V_M_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal RIN_D_MEXC_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DSUIN_TBUFCNT_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 : std_logic_vector(6 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal V_D_INST1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DEBUG_intermed_1 : STD_ULOGIC;
signal RIN_M_Y_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_SHCNT_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal RIN_D_ANNUL_intermed_2 : STD_ULOGIC;
signal ICO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_MEXC_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal DSUIN_CRDY2_intermed_2 : STD_LOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_DATA031_shadow_intermed_1 : STD_LOGIC;
signal RIN_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_D_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal DCO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_S_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_LD_shadow_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal V_E_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_F_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO2_shadow_intermed_8 : std_logic_vector(31 downto 2);
signal V_D_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal R_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_M_RESULT1DOWNTO0_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_5 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal V_X_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_5 : std_logic_vector(1 downto 0);
signal R_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_W_S_S_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_A_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal R_X_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_intermed_1 : DC_IN_TYPE;
signal R_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_EF_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_LD_intermed_3 : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal V_F_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 : STD_LOGIC_VECTOR(30 downto 11);
signal V_X_ANNUL_ALL_shadow_intermed_3 : STD_ULOGIC;
signal V_F_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal R_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RETT_intermed_3 : STD_ULOGIC;
signal R_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 3);
signal V_E_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_E_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal V_A_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_OP231_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RPIN_ERROR_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_D_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal DCO_DATA00_intermed_1 : STD_LOGIC;
signal V_M_Y31_shadow_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal DCO_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_DATA03_shadow_intermed_1 : STD_LOGIC;
signal V_E_OP1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal V_M_Y31_shadow_intermed_2 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal R_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_RFE1_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_M_MAC_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal R_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_DATA00_intermed_1 : STD_LOGIC;
signal V_X_ANNUL_ALL_shadow_intermed_1 : STD_ULOGIC;
signal R_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_F_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_W_S_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_W_S_PS_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal R_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_MAC_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_ICC_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_MAC_intermed_1 : STD_ULOGIC;
signal RIN_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal R_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 13);
signal RIN_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal IR_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_2 : STD_LOGIC;
signal RIN_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_E_OP2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap or handlerTrap;
v.x.nerror := rp.error;
if(handlerTrap = '1')then
xc_vectt := "00" & TT_WATCH;
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif false and false and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if true then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if false then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not true) and (r.w.s.cwp = "000") then v.w.s.cwp := "111";
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
end if;
if true then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if true then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(7 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.w.s.ef := '0'; -- needed for AX
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := "000";
v.w.s.icc := "0000";
end if;
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := "00000000"; end if;
if true then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to 2-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if false and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if 0 = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000",
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if 2 > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000"; de_raddr2 := "0000000000";
if true then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if true then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2); de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := "000";
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000"; v.f.branch := '0';
if false then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to 2-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(0 downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if true then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if false then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if true then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if true then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
V_A_ET_shadow <= V.A.ET;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 4 DOWNTO 3 );
ICNT_shadow <= ICNT;
EX_OP1_shadow <= EX_OP1;
V_M_CTRL_PC_shadow <= V.M.CTRL.PC;
V_E_CTRL_PC3DOWNTO2_shadow <= V.E.CTRL.PC( 3 DOWNTO 2 );
DE_REN1_shadow <= DE_REN1;
DE_INST_shadow <= DE_INST;
V_A_CTRL_CNT_shadow <= V.A.CTRL.CNT;
V_F_PC3DOWNTO2_shadow <= V.F.PC( 3 DOWNTO 2 );
V_W_S_TT_shadow <= V.W.S.TT;
V_X_RESULT6DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 );
EX_JUMP_ADDRESS3DOWNTO2_shadow <= EX_JUMP_ADDRESS( 3 DOWNTO 2 );
V_E_ALUCIN_shadow <= V.E.ALUCIN;
V_D_PC3DOWNTO2_shadow <= V.D.PC( 3 DOWNTO 2 );
V_A_CTRL_PV_shadow <= V.A.CTRL.PV;
V_E_CTRL_shadow <= V.E.CTRL;
V_M_CTRL_shadow <= V.M.CTRL;
V_M_RESULT1DOWNTO0_shadow <= V.M.RESULT ( 1 DOWNTO 0 );
EX_SHCNT_shadow <= EX_SHCNT;
V_M_DCI_SIZE_shadow <= V.M.DCI.SIZE;
V_X_CTRL_ANNUL_shadow <= V.X.CTRL.ANNUL;
V_X_MEXC_shadow <= V.X.MEXC;
TBUFCNTX_shadow <= TBUFCNTX;
V_A_CTRL_WY_shadow <= V.A.CTRL.WY;
NPC_shadow <= NPC;
V_M_CTRL_TT3DOWNTO0_shadow <= V.M.CTRL.TT( 3 DOWNTO 0 );
V_A_MULSTART_shadow <= V.A.MULSTART;
XC_VECTT3DOWNTO0_shadow <= XC_VECTT( 3 DOWNTO 0 );
V_E_CTRL_TT_shadow <= V.E.CTRL.TT;
DSIGN_shadow <= DSIGN;
V_E_CTRL_ANNUL_shadow <= V.E.CTRL.ANNUL;
EX_JUMP_ADDRESS_shadow <= EX_JUMP_ADDRESS;
V_A_CTRL_PC31DOWNTO12_shadow <= V.A.CTRL.PC( 31 DOWNTO 12 );
V_A_RFE1_shadow <= V.A.RFE1;
V_W_WA_shadow <= V.W.WA;
V_X_ANNUL_ALL_shadow <= V.X.ANNUL_ALL;
EX_YMSB_shadow <= EX_YMSB;
EX_ADD_RES_shadow <= EX_ADD_RES;
VIR_ADDR_shadow <= VIR.ADDR;
EX_JUMP_ADDRESS31DOWNTO12_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 12 );
V_W_S_CWP_shadow <= V.W.S.CWP;
V_D_INST0_shadow <= V.D.INST ( 0 );
V_A_CTRL_ANNUL_shadow <= V.A.CTRL.ANNUL;
V_X_DATA1_shadow <= V.X.DATA ( 1 );
VP_PWD_shadow <= VP.PWD;
V_M_CTRL_RD6DOWNTO0_shadow <= V.M.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA00_shadow <= V.X.DATA ( 0 )( 0 );
V_M_CTRL_RETT_shadow <= V.M.CTRL.RETT;
V_X_CTRL_RETT_shadow <= V.X.CTRL.RETT;
V_X_CTRL_PC31DOWNTO12_shadow <= V.X.CTRL.PC( 31 DOWNTO 12 );
V_W_S_PS_shadow <= V.W.S.PS;
V_X_CTRL_TT_shadow <= V.X.CTRL.TT;
V_D_STEP_shadow <= V.D.STEP;
V_X_CTRL_WICC_shadow <= V.X.CTRL.WICC;
VIR_ADDR31DOWNTO2_shadow <= VIR.ADDR( 31 DOWNTO 2 );
V_M_CTRL_RD7DOWNTO0_shadow <= V.M.CTRL.RD ( 7 DOWNTO 0 );
V_X_RESULT_shadow <= V.X.RESULT;
V_D_CNT_shadow <= V.D.CNT;
XC_VECTT_shadow <= XC_VECTT;
EX_ADD_RES32DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 );
V_W_S_EF_shadow <= V.W.S.EF;
V_A_CTRL_PC31DOWNTO2_shadow <= V.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA04DOWNTO0_shadow <= V.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DCI_SIGNED_shadow <= V.X.DCI.SIGNED;
V_M_NALIGN_shadow <= V.M.NALIGN;
XC_WREG_shadow <= XC_WREG;
V_A_RFA2_shadow <= V.A.RFA2;
V_E_CTRL_PC31DOWNTO12_shadow <= V.E.CTRL.PC( 31 DOWNTO 12 );
EX_ADD_RES32DOWNTO332DOWNTO13_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 13 );
EX_OP231_shadow <= EX_OP2( 31 );
XC_TRAP_ADDRESS31DOWNTO4_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 4 );
V_X_ICC_shadow <= V.X.ICC;
V_A_SU_shadow <= V.A.SU;
V_E_OP2_shadow <= V.E.OP2;
EX_FORCE_A2_shadow <= EX_FORCE_A2;
V_E_CTRL_PC31DOWNTO2_shadow <= V.E.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO4_shadow <= V.E.CTRL.PC( 31 DOWNTO 4 );
V_E_OP131_shadow <= V.E.OP1( 31 );
V_X_DCI_shadow <= V.X.DCI;
V_E_CTRL_WICC_shadow <= V.E.CTRL.WICC;
EX_OP13_shadow <= EX_OP1( 3 );
V_F_PC31DOWNTO12_shadow <= V.F.PC( 31 DOWNTO 12 );
V_E_CTRL_INST_shadow <= V.E.CTRL.INST;
V_E_CTRL_LD_shadow <= V.E.CTRL.LD;
V_M_SU_shadow <= V.M.SU;
V_E_SARI_shadow <= V.E.SARI;
V_E_ET_shadow <= V.E.ET;
V_M_CTRL_PV_shadow <= V.M.CTRL.PV;
VDSU_CRDY2_shadow <= VDSU.CRDY ( 2 );
MUL_OP2_shadow <= MUL_OP2;
XC_EXCEPTION_shadow <= XC_EXCEPTION;
V_E_OP1_shadow <= V.E.OP1;
VP_ERROR_shadow <= VP.ERROR;
V_M_DCI_SIGNED_shadow <= V.M.DCI.SIGNED;
V_D_PC31DOWNTO12_shadow <= V.D.PC( 31 DOWNTO 12 );
MUL_OP231_shadow <= MUL_OP2 ( 31 );
XC_TRAP_ADDRESS31DOWNTO2_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow <= V.M.CTRL.PC( 3 DOWNTO 2 );
V_M_DCI_shadow <= V.M.DCI;
EX_OP23_shadow <= EX_OP2( 3 );
V_X_CTRL_RD6DOWNTO0_shadow <= V.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_TRAP_shadow <= V.X.CTRL.TRAP;
V_A_DIVSTART_shadow <= V.A.DIVSTART;
V_X_RESULT6DOWNTO03DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
VDSU_TT_shadow <= VDSU.TT;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 5 );
V_X_CTRL_CNT_shadow <= V.X.CTRL.CNT;
V_E_YMSB_shadow <= V.E.YMSB;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 30 DOWNTO 11 );
V_A_RFE2_shadow <= V.A.RFE2;
V_E_OP13_shadow <= V.E.OP1( 3 );
V_A_CWP_shadow <= V.A.CWP;
ME_SIZE_shadow <= ME_SIZE;
V_X_MAC_shadow <= V.X.MAC;
V_M_CTRL_INST_shadow <= V.M.CTRL.INST;
VIR_ADDR31DOWNTO4_shadow <= VIR.ADDR( 31 DOWNTO 4 );
V_A_CTRL_INST20_shadow <= V.A.CTRL.INST( 20 );
DE_REN2_shadow <= DE_REN2;
V_E_CTRL_PV_shadow <= V.E.CTRL.PV;
V_E_MAC_shadow <= V.E.MAC;
V_X_CTRL_TT3DOWNTO0_shadow <= V.X.CTRL.TT( 3 DOWNTO 0 );
EX_ADD_RES3_shadow <= EX_ADD_RES ( 3 );
V_X_CTRL_INST_shadow <= V.X.CTRL.INST;
V_M_CTRL_PC31DOWNTO2_shadow <= V.M.CTRL.PC( 31 DOWNTO 2 );
V_W_S_ET_shadow <= V.W.S.ET;
V_M_CTRL_CNT_shadow <= V.M.CTRL.CNT;
V_M_CTRL_ANNUL_shadow <= V.M.CTRL.ANNUL;
DE_INST19_shadow <= DE_INST( 19 );
XC_HALT_shadow <= XC_HALT;
V_E_OP231_shadow <= V.E.OP2( 31 );
V_A_CTRL_PC3DOWNTO2_shadow <= V.A.CTRL.PC( 3 DOWNTO 2 );
VIR_ADDR31DOWNTO12_shadow <= VIR.ADDR( 31 DOWNTO 12 );
V_M_CTRL_WICC_shadow <= V.M.CTRL.WICC;
V_M_CTRL_WREG_shadow <= V.M.CTRL.WREG;
V_W_S_S_shadow <= V.W.S.S;
V_F_PC31DOWNTO2_shadow <= V.F.PC( 31 DOWNTO 2 );
V_E_CWP_shadow <= V.E.CWP;
V_A_STEP_shadow <= V.A.STEP;
V_A_CTRL_TT3DOWNTO0_shadow <= V.A.CTRL.TT( 3 DOWNTO 0 );
V_A_CTRL_TRAP_shadow <= V.A.CTRL.TRAP;
NPC31DOWNTO2_shadow <= NPC ( 31 DOWNTO 2 );
V_M_CTRL_TRAP_shadow <= V.M.CTRL.TRAP;
V_D_PC31DOWNTO4_shadow <= V.D.PC( 31 DOWNTO 4 );
V_X_INTACK_shadow <= V.X.INTACK;
SIDLE_shadow <= SIDLE;
V_A_CTRL_RETT_shadow <= V.A.CTRL.RETT;
V_X_DATA03_shadow <= V.X.DATA ( 0 )( 3 );
V_A_CTRL_INST19_shadow <= V.A.CTRL.INST( 19 );
V_W_S_SVT_shadow <= V.W.S.SVT;
V_A_CTRL_PC31DOWNTO4_shadow <= V.A.CTRL.PC( 31 DOWNTO 4 );
V_X_LADDR_shadow <= V.X.LADDR;
V_W_S_DWT_shadow <= V.W.S.DWT;
EX_JUMP_ADDRESS31DOWNTO2_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 2 );
V_W_S_TBA_shadow <= V.W.S.TBA;
XC_WADDR6DOWNTO0_shadow <= XC_WADDR ( 6 DOWNTO 0 );
V_M_MUL_shadow <= V.M.MUL;
V_E_SU_shadow <= V.E.SU;
V_M_Y31_shadow <= V.M.Y ( 31 );
V_E_OP23_shadow <= V.E.OP2( 3 );
V_M_CTRL_PC31DOWNTO4_shadow <= V.M.CTRL.PC( 31 DOWNTO 4 );
DE_RADDR17DOWNTO0_shadow <= DE_RADDR1 ( 7 DOWNTO 0 );
V_X_CTRL_PC31DOWNTO2_shadow <= V.X.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_TRAP_shadow <= V.E.CTRL.TRAP;
V_X_DEBUG_shadow <= V.X.DEBUG;
V_M_DCI_LOCK_shadow <= V.M.DCI.LOCK;
V_X_CTRL_PC3DOWNTO2_shadow <= V.X.CTRL.PC( 3 DOWNTO 2 );
V_X_CTRL_WREG_shadow <= V.X.CTRL.WREG;
V_E_CTRL_INST24_shadow <= V.E.CTRL.INST( 24 );
V_D_MEXC_shadow <= V.D.MEXC;
V_W_RESULT_shadow <= V.W.RESULT;
VFPI_DBG_ENABLE_shadow <= VFPI.DBG.ENABLE;
EX_OP131_shadow <= EX_OP1 ( 31 );
V_D_INST1_shadow <= V.D.INST ( 1 );
V_W_EXCEPT_shadow <= V.W.EXCEPT;
V_E_CTRL_TT3DOWNTO0_shadow <= V.E.CTRL.TT( 3 DOWNTO 0 );
ME_LADDR_shadow <= ME_LADDR;
V_X_CTRL_PC31DOWNTO4_shadow <= V.X.CTRL.PC( 31 DOWNTO 4 );
V_E_CTRL_RETT_shadow <= V.E.CTRL.RETT;
XC_WADDR7DOWNTO0_shadow <= XC_WADDR ( 7 DOWNTO 0 );
V_X_CTRL_PV_shadow <= V.X.CTRL.PV;
V_E_CTRL_RD6DOWNTO0_shadow <= V.E.CTRL.RD( 6 DOWNTO 0 );
V_M_MAC_shadow <= V.M.MAC;
V_D_SET_shadow <= V.D.SET;
VIR_ADDR3DOWNTO2_shadow <= VIR.ADDR( 3 DOWNTO 2 );
V_D_CWP_shadow <= V.D.CWP;
DE_INST20_shadow <= DE_INST( 20 );
V_D_ANNUL_shadow <= V.D.ANNUL;
EX_OP2_shadow <= EX_OP2;
EX_SARI_shadow <= EX_SARI;
V_D_PC31DOWNTO2_shadow <= V.D.PC( 31 DOWNTO 2 );
V_X_DCI_SIZE_shadow <= V.X.DCI.SIZE;
V_M_Y_shadow <= V.M.Y;
V_X_CTRL_PC_shadow <= V.X.CTRL.PC;
V_X_SET_shadow <= V.X.SET;
V_A_CTRL_PC_shadow <= V.A.CTRL.PC;
V_A_JMPL_shadow <= V.A.JMPL;
V_E_CTRL_PC_shadow <= V.E.CTRL.PC;
V_E_CTRL_INST20_shadow <= V.E.CTRL.INST( 20 );
V_E_CTRL_WREG_shadow <= V.E.CTRL.WREG;
V_A_CTRL_WREG_shadow <= V.A.CTRL.WREG;
V_A_CTRL_shadow <= V.A.CTRL;
V_A_CTRL_RD6DOWNTO0_shadow <= V.A.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA0_shadow <= V.X.DATA ( 0 );
V_E_CTRL_INST19_shadow <= V.E.CTRL.INST( 19 );
ME_SIGNED_shadow <= ME_SIGNED;
V_W_WREG_shadow <= V.W.WREG;
V_D_PC_shadow <= V.D.PC;
VFPI_D_ANNUL_shadow <= VFPI.D.ANNUL;
DE_RADDR27DOWNTO0_shadow <= DE_RADDR2 ( 7 DOWNTO 0 );
V_E_CTRL_CNT_shadow <= V.E.CTRL.CNT;
V_F_PC_shadow <= V.F.PC;
V_X_DATA031_shadow <= V.X.DATA ( 0 )( 31 );
V_M_CTRL_PC31DOWNTO12_shadow <= V.M.CTRL.PC( 31 DOWNTO 12 );
V_X_CTRL_RD7DOWNTO0_shadow <= V.X.CTRL.RD ( 7 DOWNTO 0 );
V_M_CTRL_TT_shadow <= V.M.CTRL.TT;
V_X_CTRL_shadow <= V.X.CTRL;
V_A_CTRL_INST24_shadow <= V.A.CTRL.INST( 24 );
XC_TRAP_ADDRESS3DOWNTO2_shadow <= XC_TRAP_ADDRESS( 3 DOWNTO 2 );
V_X_NERROR_shadow <= V.X.NERROR;
V_F_PC31DOWNTO4_shadow <= V.F.PC( 31 DOWNTO 4 );
V_W_S_TT3DOWNTO0_shadow <= V.W.S.TT( 3 DOWNTO 0 );
EX_JUMP_ADDRESS31DOWNTO4_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 4 );
EX_ADD_RES32DOWNTO332DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 3 );
V_F_BRANCH_shadow <= V.F.BRANCH;
V_A_CTRL_WICC_shadow <= V.A.CTRL.WICC;
V_A_CTRL_LD_shadow <= V.A.CTRL.LD;
V_A_CTRL_TT_shadow <= V.A.CTRL.TT;
V_M_CTRL_LD_shadow <= V.M.CTRL.LD;
V_E_SHCNT_shadow <= V.E.SHCNT;
XC_TRAP_ADDRESS31DOWNTO12_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 12 );
V_A_CTRL_INST_shadow <= V.A.CTRL.INST;
V_A_CTRL_RD7DOWNTO0_shadow <= V.A.CTRL.RD ( 7 DOWNTO 0 );
VIR_PWD_shadow <= VIR.PWD;
XC_RESULT_shadow <= XC_RESULT;
V_A_RFA1_shadow <= V.A.RFA1;
V_E_JMPL_shadow <= V.E.JMPL;
V_E_CTRL_RD7DOWNTO0_shadow <= V.E.CTRL.RD ( 7 DOWNTO 0 );
ME_ICC_shadow <= ME_ICC;
DE_INST24_shadow <= DE_INST( 24 );
XC_TRAP_shadow <= XC_TRAP;
VDSU_TBUFCNT_shadow <= VDSU.TBUFCNT;
XC_TRAP_ADDRESS_shadow <= XC_TRAP_ADDRESS;
end process;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
V_W_S_S_shadow_intermed_2 <= V_W_S_S_shadow_intermed_1;
V_W_S_PS_shadow_intermed_1 <= V_W_S_PS_shadow;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
R_W_S_S_intermed_1 <= R.W.S.S;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_S_intermed_2 <= RIN_W_S_S_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_X_RESULT6DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_X_DATA0_intermed_2 <= R_X_DATA0_intermed_1;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_3 <= R_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
R_A_CTRL_TT3DOWNTO0_intermed_5 <= R_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_6 <= RIN_A_CTRL_TT3DOWNTO0_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_W_S_TT3DOWNTO0_intermed_2 <= R_W_S_TT3DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_4 <= R_E_CTRL_TT3DOWNTO0_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_M_CTRL_TT3DOWNTO0_intermed_4 <= RIN_M_CTRL_TT3DOWNTO0_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_X_CTRL_TT3DOWNTO0_intermed_3 <= RIN_X_CTRL_TT3DOWNTO0_intermed_2;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
R_X_CTRL_TT3DOWNTO0_intermed_2 <= R_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
RIN_E_CTRL_TT3DOWNTO0_intermed_5 <= RIN_E_CTRL_TT3DOWNTO0_intermed_4;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_2 <= XC_VECTT3DOWNTO0_shadow_intermed_1;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_M_DCI_LOCK_intermed_1 <= RIN.M.DCI.LOCK;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_M_DCI_LOCK_shadow_intermed_1 <= V_M_DCI_LOCK_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
DCO_DATA031_intermed_2 <= DCO_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_3 <= DE_INST19_shadow_intermed_2;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_E_CTRL_INST19_intermed_2 <= R_E_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_E_CTRL_INST20_intermed_2 <= R_E_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_3 <= DE_INST20_shadow_intermed_2;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
DCO_DATA00_intermed_2 <= DCO_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_2 <= DCO_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_4 <= R_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_5 <= RIN_M_CTRL_PC31DOWNTO2_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_7 <= RIN_A_CTRL_PC31DOWNTO2_intermed_6;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_6 <= R_A_CTRL_PC31DOWNTO2_intermed_5;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_X_CTRL_PC31DOWNTO2_intermed_3 <= R_X_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_D_PC31DOWNTO2_shadow_intermed_8 <= V_D_PC31DOWNTO2_shadow_intermed_7;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
RIN_D_PC31DOWNTO2_intermed_8 <= RIN_D_PC31DOWNTO2_intermed_7;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_CTRL_PC31DOWNTO2_intermed_4 <= RIN_X_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_3 <= IRIN_ADDR31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_5 <= R_E_CTRL_PC31DOWNTO2_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_D_PC31DOWNTO2_intermed_7 <= R_D_PC31DOWNTO2_intermed_6;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_2 <= IR_ADDR31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_6 <= RIN_E_CTRL_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
R_F_PC31DOWNTO2_intermed_2 <= R_F_PC31DOWNTO2_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
VIR_ADDR31DOWNTO2_shadow_intermed_3 <= VIR_ADDR31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
V_A_MULSTART_shadow_intermed_1 <= V_A_MULSTART_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_MULSTART_intermed_1 <= RIN.A.MULSTART;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_3 <= DE_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_E_CTRL_INST24_intermed_2 <= R_E_CTRL_INST24_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_DIVSTART_intermed_1 <= RIN.A.DIVSTART;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_DIVSTART_shadow_intermed_1 <= V_A_DIVSTART_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
RIN_M_Y_intermed_1 <= RIN.M.Y;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y_shadow_intermed_1 <= V_M_Y_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_M_Y31_intermed_1 <= R.M.Y( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
R_M_Y31_intermed_2 <= R_M_Y31_intermed_1;
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
DSUR_CRDY2_intermed_2 <= DSUR_CRDY2_intermed_1;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
VP_ERROR_shadow_intermed_2 <= VP_ERROR_shadow_intermed_1;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RPIN_ERROR_intermed_2 <= RPIN_ERROR_intermed_1;
V_X_NERROR_shadow_intermed_1 <= V_X_NERROR_shadow;
RP_ERROR_intermed_1 <= RP.ERROR;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
DCO_DATA1_intermed_1 <= DCO.DATA ( 1 );
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
R_X_DATA1_intermed_2 <= R_X_DATA1_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_A_CTRL_PC31DOWNTO12_intermed_7 <= RIN_A_CTRL_PC31DOWNTO12_intermed_6;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_6 <= RIN_E_CTRL_PC31DOWNTO12_intermed_5;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_4 <= R_M_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_3 <= IRIN_ADDR31DOWNTO12_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
R_F_PC31DOWNTO12_intermed_2 <= R_F_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
RIN_M_CTRL_PC31DOWNTO12_intermed_5 <= RIN_M_CTRL_PC31DOWNTO12_intermed_4;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
IR_ADDR31DOWNTO12_intermed_2 <= IR_ADDR31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_3 <= R_X_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_D_PC31DOWNTO12_shadow_intermed_8 <= V_D_PC31DOWNTO12_shadow_intermed_7;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_D_PC31DOWNTO12_intermed_7 <= R_D_PC31DOWNTO12_intermed_6;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_A_CTRL_PC31DOWNTO12_intermed_6 <= R_A_CTRL_PC31DOWNTO12_intermed_5;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_5 <= R_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_X_CTRL_PC31DOWNTO12_intermed_4 <= RIN_X_CTRL_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
RIN_D_PC31DOWNTO12_intermed_8 <= RIN_D_PC31DOWNTO12_intermed_7;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
VIR_ADDR31DOWNTO12_shadow_intermed_3 <= VIR_ADDR31DOWNTO12_shadow_intermed_2;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4;
ICO_DATA0_intermed_1 <= ICO.DATA ( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
R_D_INST1_intermed_2 <= R_D_INST1_intermed_1;
ICO_DATA1_intermed_1 <= ICO.DATA ( 1 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
R_X_DATA03_intermed_2 <= R_X_DATA03_intermed_1;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_E_ALUCIN_shadow_intermed_1 <= V_E_ALUCIN_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_E_ALUCIN_intermed_1 <= RIN.E.ALUCIN;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_E_YMSB_shadow_intermed_1 <= V_E_YMSB_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_E_YMSB_intermed_1 <= RIN.E.YMSB;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_E_SHCNT_shadow_intermed_1 <= V_E_SHCNT_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_E_SHCNT_intermed_1 <= RIN.E.SHCNT;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
V_E_SARI_shadow_intermed_1 <= V_E_SARI_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_E_SARI_intermed_1 <= RIN.E.SARI;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
V_X_DCI_SIGNED_shadow_intermed_1 <= V_X_DCI_SIGNED_shadow;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
V_X_DCI_SIZE_shadow_intermed_1 <= V_X_DCI_SIZE_shadow;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_3 <= V_M_RESULT1DOWNTO0_shadow_intermed_2;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_3 <= RIN_M_RESULT1DOWNTO0_intermed_2;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_X_LADDR_shadow_intermed_1 <= V_X_LADDR_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_X_CTRL_TRAP_shadow_intermed_1 <= V_X_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
V_X_MEXC_shadow_intermed_1 <= V_X_MEXC_shadow;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
DCO_MEXC_intermed_1 <= DCO.MEXC;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RPIN_PWD_intermed_1 <= RPIN.PWD;
V_X_DEBUG_shadow_intermed_1 <= V_X_DEBUG_shadow;
VP_PWD_shadow_intermed_1 <= VP_PWD_shadow;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_W_S_TBA_shadow_intermed_1 <= V_W_S_TBA_shadow;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
RIN_W_S_TBA_intermed_1 <= RIN.W.S.TBA;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
DSUIN_TT_intermed_1 <= DSUIN.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RPIN_PWD_intermed_1 <= RPIN.PWD;
IRIN_PWD_intermed_1 <= IRIN.PWD;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_W_S_TT_intermed_1 <= RIN.W.S.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD6DOWNTO0_shadow;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_W_S_CWP_shadow_intermed_1 <= V_W_S_CWP_shadow;
RIN_W_S_ET_intermed_1 <= RIN.W.S.ET;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_D_PC_intermed_6 <= RIN_D_PC_intermed_5;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
VIR_ADDR_shadow_intermed_1 <= VIR_ADDR_shadow;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
RIN_A_CTRL_PC_intermed_5 <= RIN_A_CTRL_PC_intermed_4;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_4 <= R_A_CTRL_PC_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
V_E_CTRL_PC_shadow_intermed_4 <= V_E_CTRL_PC_shadow_intermed_3;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_M_CTRL_PC_intermed_2 <= R_M_CTRL_PC_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC_intermed_1 <= R.X.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
R_E_CTRL_PC_intermed_3 <= R_E_CTRL_PC_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_3 <= RIN_M_CTRL_PC_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_X_CTRL_PC_shadow_intermed_2 <= V_X_CTRL_PC_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_M_CTRL_PC_shadow_intermed_3 <= V_M_CTRL_PC_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_5 <= V_A_CTRL_PC_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
R_D_PC_intermed_5 <= R_D_PC_intermed_4;
RIN_F_PC_intermed_1 <= RIN.F.PC;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_E_CTRL_PC_intermed_4 <= RIN_E_CTRL_PC_intermed_3;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
RIN_X_CTRL_PC_intermed_2 <= RIN_X_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
V_D_PC_shadow_intermed_6 <= V_D_PC_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
DSUIN_TBUFCNT_intermed_1 <= DSUIN.TBUFCNT;
RIN_W_EXCEPT_intermed_1 <= RIN.W.EXCEPT;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
RIN_W_RESULT_intermed_1 <= RIN.W.RESULT;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_W_WA_intermed_1 <= RIN.W.WA;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_W_WREG_intermed_1 <= RIN.W.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_W_S_SVT_intermed_1 <= RIN.W.S.SVT;
RIN_W_S_DWT_intermed_1 <= RIN.W.S.DWT;
RIN_W_S_EF_intermed_1 <= RIN.W.S.EF;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_E_CTRL_intermed_2 <= RIN_E_CTRL_intermed_1;
R_E_CTRL_intermed_1 <= R.E.CTRL;
RIN_X_CTRL_intermed_1 <= RIN.X.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
V_E_CTRL_shadow_intermed_2 <= V_E_CTRL_shadow_intermed_1;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
RIN_A_CTRL_intermed_3 <= RIN_A_CTRL_intermed_2;
V_M_CTRL_shadow_intermed_1 <= V_M_CTRL_shadow;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
V_A_CTRL_shadow_intermed_3 <= V_A_CTRL_shadow_intermed_2;
R_A_CTRL_intermed_1 <= R.A.CTRL;
R_A_CTRL_intermed_2 <= R_A_CTRL_intermed_1;
V_M_DCI_shadow_intermed_1 <= V_M_DCI_shadow;
RIN_M_DCI_intermed_1 <= RIN.M.DCI;
RIN_X_DCI_intermed_1 <= RIN.X.DCI;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_E_CTRL_RETT_shadow_intermed_2 <= V_E_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_3 <= V_A_CTRL_RETT_shadow_intermed_2;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
RIN_A_CTRL_RETT_intermed_3 <= RIN_A_CTRL_RETT_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_E_CTRL_RETT_intermed_1 <= R.E.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
RIN_E_CTRL_RETT_intermed_2 <= RIN_E_CTRL_RETT_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_X_CTRL_RETT_intermed_1 <= RIN.X.CTRL.RETT;
V_M_CTRL_RETT_shadow_intermed_1 <= V_M_CTRL_RETT_shadow;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
R_A_CTRL_RETT_intermed_2 <= R_A_CTRL_RETT_intermed_1;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
V_E_MAC_shadow_intermed_2 <= V_E_MAC_shadow_intermed_1;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
RIN_E_MAC_intermed_2 <= RIN_E_MAC_intermed_1;
R_E_MAC_intermed_1 <= R.E.MAC;
V_M_MAC_shadow_intermed_1 <= V_M_MAC_shadow;
RIN_X_MAC_intermed_1 <= RIN.X.MAC;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_X_CTRL_ANNUL_intermed_1 <= RIN.X.CTRL.ANNUL;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
RIN_X_SET_intermed_1 <= RIN.X.SET;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_X_ICC_intermed_1 <= RIN.X.ICC;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
R_A_CTRL_WICC_intermed_2 <= R_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_E_CTRL_WICC_shadow_intermed_2 <= V_E_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_3 <= V_A_CTRL_WICC_shadow_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_X_CTRL_WICC_intermed_1 <= RIN.X.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_E_CTRL_WICC_intermed_2 <= RIN_E_CTRL_WICC_intermed_1;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
R_E_CTRL_WICC_intermed_1 <= R.E.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_M_CTRL_WICC_shadow_intermed_1 <= V_M_CTRL_WICC_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_WICC_intermed_3 <= RIN_A_CTRL_WICC_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
R_A_CTRL_intermed_1 <= R.A.CTRL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
RIN_E_CWP_intermed_1 <= RIN.E.CWP;
V_A_CWP_shadow_intermed_1 <= V_A_CWP_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_D_CWP_intermed_2 <= RIN_D_CWP_intermed_1;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
V_D_CWP_shadow_intermed_2 <= V_D_CWP_shadow_intermed_1;
R_D_CWP_intermed_1 <= R.D.CWP;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_M_MUL_intermed_1 <= RIN.M.MUL;
RIN_M_NALIGN_intermed_1 <= RIN.M.NALIGN;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
R_A_CTRL_LD_intermed_2 <= R_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_3 <= RIN_A_CTRL_LD_intermed_2;
V_E_CTRL_LD_shadow_intermed_1 <= V_E_CTRL_LD_shadow;
V_E_CTRL_LD_shadow_intermed_2 <= V_E_CTRL_LD_shadow_intermed_1;
R_E_CTRL_LD_intermed_1 <= R.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_2 <= RIN_E_CTRL_LD_intermed_1;
RIN_M_CTRL_LD_intermed_1 <= RIN.M.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
V_A_CTRL_LD_shadow_intermed_3 <= V_A_CTRL_LD_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
RIN_E_JMPL_intermed_1 <= RIN.E.JMPL;
RIN_A_JMPL_intermed_1 <= RIN.A.JMPL;
V_A_JMPL_shadow_intermed_1 <= V_A_JMPL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_A_SU_intermed_1 <= RIN.A.SU;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_ET_intermed_1 <= RIN.E.ET;
RIN_A_ET_intermed_1 <= RIN.A.ET;
V_A_ET_shadow_intermed_1 <= V_A_ET_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
V_A_RFA1_shadow_intermed_1 <= V_A_RFA1_shadow;
DBGI_DADDR9DOWNTO2_intermed_1 <= DBGI.DADDR ( 9 DOWNTO 2 );
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
RIN_A_RFA2_intermed_1 <= RIN.A.RFA2;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WY_intermed_1 <= RIN.A.CTRL.WY;
ICO_MEXC_intermed_1 <= ICO.MEXC;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
R_D_ANNUL_intermed_1 <= R.D.ANNUL;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
V_D_ANNUL_shadow_intermed_2 <= V_D_ANNUL_shadow_intermed_1;
DBGI_STEP_intermed_1 <= DBGI.STEP;
V_D_STEP_shadow_intermed_1 <= V_D_STEP_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_ANNUL_intermed_2 <= RIN_D_ANNUL_intermed_1;
RIN_A_STEP_intermed_1 <= RIN.A.STEP;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
RIN_F_BRANCH_intermed_1 <= RIN.F.BRANCH;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
R_D_INST0_intermed_1 <= R.D.INST( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
RIN_D_SET_intermed_1 <= RIN.D.SET;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
R_E_CTRL_INST_intermed_2 <= R_E_CTRL_INST_intermed_1;
R_M_CTRL_INST_intermed_1 <= R.M.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
DE_INST_shadow_intermed_4 <= DE_INST_shadow_intermed_3;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_4 <= V_A_CTRL_INST_shadow_intermed_3;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
V_E_CTRL_INST_shadow_intermed_3 <= V_E_CTRL_INST_shadow_intermed_2;
RIN_X_CTRL_INST_intermed_1 <= RIN.X.CTRL.INST;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_A_CTRL_INST_intermed_4 <= RIN_A_CTRL_INST_intermed_3;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_M_CTRL_INST_intermed_2 <= RIN_M_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_3 <= RIN_E_CTRL_INST_intermed_2;
V_M_CTRL_INST_shadow_intermed_1 <= V_M_CTRL_INST_shadow;
V_M_CTRL_INST_shadow_intermed_2 <= V_M_CTRL_INST_shadow_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_3 <= R_A_CTRL_INST_intermed_2;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_CNT_shadow_intermed_3 <= V_E_CTRL_CNT_shadow_intermed_2;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
RIN_D_CNT_intermed_5 <= RIN_D_CNT_intermed_4;
R_M_CTRL_CNT_intermed_1 <= R.M.CTRL.CNT;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
V_A_CTRL_CNT_shadow_intermed_4 <= V_A_CTRL_CNT_shadow_intermed_3;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
R_A_CTRL_CNT_intermed_3 <= R_A_CTRL_CNT_intermed_2;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
V_D_CNT_shadow_intermed_5 <= V_D_CNT_shadow_intermed_4;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_D_CNT_intermed_4 <= R_D_CNT_intermed_3;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
R_E_CTRL_CNT_intermed_2 <= R_E_CTRL_CNT_intermed_1;
RIN_X_CTRL_CNT_intermed_1 <= RIN.X.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_A_CTRL_CNT_intermed_4 <= RIN_A_CTRL_CNT_intermed_3;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_M_CTRL_CNT_intermed_2 <= RIN_M_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_3 <= RIN_E_CTRL_CNT_intermed_2;
V_M_CTRL_CNT_shadow_intermed_1 <= V_M_CTRL_CNT_shadow;
V_M_CTRL_CNT_shadow_intermed_2 <= V_M_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_3 <= V_E_CTRL_PV_shadow_intermed_2;
R_M_CTRL_PV_intermed_1 <= R.M.CTRL.PV;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_E_CTRL_PV_intermed_2 <= R_E_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_3 <= R_A_CTRL_PV_intermed_2;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_3 <= RIN_E_CTRL_PV_intermed_2;
RIN_X_CTRL_PV_intermed_1 <= RIN.X.CTRL.PV;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
RIN_M_CTRL_PV_intermed_2 <= RIN_M_CTRL_PV_intermed_1;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
V_A_CTRL_PV_shadow_intermed_4 <= V_A_CTRL_PV_shadow_intermed_3;
V_M_CTRL_PV_shadow_intermed_1 <= V_M_CTRL_PV_shadow;
V_M_CTRL_PV_shadow_intermed_2 <= V_M_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
RIN_A_CTRL_PV_intermed_4 <= RIN_A_CTRL_PV_intermed_3;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (RP.ERROR /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(1) <= '1' when (RP.ERROR /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(2) <= '1' when (RFI.REN1 /= DE_REN1_shadow) else '0';
dfp_trap_vector(3) <= '1' when (RFI.REN2 /= DE_REN2_shadow) else '0';
dfp_trap_vector(4) <= '1' when (RFI.DIAG(0) /= DCO.TESTEN) else '0';
dfp_trap_vector(5) <= '1' when (RFI.DIAG /= "0000") else '0';
dfp_trap_vector(6) <= '1' when (ICI.DPC(31 downto 2) /= R.D.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(7) <= '1' when (ICI.FPC(31 downto 2) /= R.F.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(8) <= '1' when (ICI.RPC(31 downto 2) /= NPC31DOWNTO2_shadow) else '0';
dfp_trap_vector(9) <= '1' when (ICI.FLUSHL /= '0') else '0';
dfp_trap_vector(10) <= '1' when (MULI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(11) <= '1' when (MULI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(12) <= '1' when (MULI.OP2(31 downto 0) /= MUL_OP2_shadow) else '0';
dfp_trap_vector(13) <= '1' when (MULI.OP2(31) /= MUL_OP231_shadow) else '0';
dfp_trap_vector(14) <= '1' when (DIVI.START /= R.A.DIVSTART) else '0';
dfp_trap_vector(15) <= '1' when (DIVI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(16) <= '1' when (DIVI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(17) <= '1' when (DIVI.OP2(31) /= EX_OP231_shadow) else '0';
dfp_trap_vector(18) <= '1' when (DIVI.OP2(31 downto 0) /= EX_OP2_shadow) else '0';
dfp_trap_vector(19) <= '1' when (DIVI.Y(31 downto 0) /= R.M.Y) else '0';
dfp_trap_vector(20) <= '1' when (DIVI.Y(31) /= R.M.Y ( 31 )) else '0';
dfp_trap_vector(21) <= '0' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_2) else '0';
dfp_trap_vector(22) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(23) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(24) <= '0' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_2) else '0';
dfp_trap_vector(25) <= '0' when (DSUR.CRDY ( 2 ) /= DSUR_CRDY2_intermed_2) else '0';
dfp_trap_vector(26) <= '0' when (DBGO.ERROR /= DUMMY) else '0';
dfp_trap_vector(27) <= '0' when (DBGO.ERROR /= '1') else '0';
dfp_trap_vector(28) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow) else '0';
dfp_trap_vector(29) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow) else '0';
dfp_trap_vector(30) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(31) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(32) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow) else '0';
dfp_trap_vector(33) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow) else '0';
dfp_trap_vector(34) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(35) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(36) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow) else '0';
dfp_trap_vector(37) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(38) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(39) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow) else '0';
dfp_trap_vector(40) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(41) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(42) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(43) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(44) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(45) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(46) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow) else '0';
dfp_trap_vector(47) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(48) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow) else '0';
dfp_trap_vector(49) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow) else '0';
dfp_trap_vector(50) <= '0' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(51) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow) else '0';
dfp_trap_vector(52) <= '0' when (DSUIN.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_2) else '0';
dfp_trap_vector(53) <= '0' when (DSUIN.CRDY ( 2 ) /= DSUR.CRDY ( 2 )) else '0';
dfp_trap_vector(54) <= '0' when (DSUIN.CRDY ( 2 ) /= DSUR_CRDY2_intermed_1) else '0';
dfp_trap_vector(55) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(56) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(57) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(58) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(59) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(60) <= '1' when (RIN.X.DATA ( 1 ) /= V_X_DATA1_shadow) else '0';
dfp_trap_vector(61) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow) else '0';
dfp_trap_vector(62) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow) else '0';
dfp_trap_vector(63) <= '1' when (RIN.D.INST ( 1 ) /= V_D_INST1_shadow) else '0';
dfp_trap_vector(64) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow) else '0';
dfp_trap_vector(65) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow) else '0';
dfp_trap_vector(66) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow) else '0';
dfp_trap_vector(67) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow) else '0';
dfp_trap_vector(68) <= '1' when (XC_HALT_shadow /= DBGI.HALT) else '0';
dfp_trap_vector(69) <= '1' when (XC_HALT_shadow /= '0') else '0';
dfp_trap_vector(70) <= '0' when (SIDLE_shadow /= RPIN_PWD_intermed_1) else '0';
dfp_trap_vector(71) <= '0' when (SIDLE_shadow /= V_X_DEBUG_shadow_intermed_1) else '0';
dfp_trap_vector(72) <= '0' when (SIDLE_shadow /= RP.PWD) else '0';
dfp_trap_vector(73) <= '0' when (SIDLE_shadow /= VP_PWD_shadow_intermed_1) else '0';
dfp_trap_vector(74) <= '0' when (SIDLE_shadow /= R.X.DEBUG) else '0';
dfp_trap_vector(75) <= '0' when (SIDLE_shadow /= '0') else '0';
dfp_trap_vector(76) <= '0' when (SIDLE_shadow /= RIN_X_DEBUG_intermed_1) else '0';
dfp_trap_vector(77) <= '1' when (V_X_NERROR_shadow /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(78) <= '1' when (V_X_NERROR_shadow /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(79) <= '1' when (V_X_NERROR_shadow /= RP.ERROR) else '0';
dfp_trap_vector(80) <= '0' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(11 downto 4) /= XC_VECTT_shadow) else '0';
dfp_trap_vector(81) <= '0' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(82) <= '0' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= "00") else '0';
dfp_trap_vector(83) <= '0' when (V_X_DEBUG_shadow /= R.X.DEBUG) else '0';
dfp_trap_vector(84) <= '0' when (V_X_DEBUG_shadow /= '0') else '0';
dfp_trap_vector(85) <= '0' when (V_X_DEBUG_shadow /= RIN_X_DEBUG_intermed_1) else '0';
dfp_trap_vector(86) <= '0' when (VIR_ADDR_shadow /= IR.ADDR) else '0';
dfp_trap_vector(87) <= '0' when (VIR_ADDR_shadow /= IRIN_ADDR_intermed_1) else '0';
dfp_trap_vector(88) <= '0' when (VDSU_TT_shadow /= DSUIN_TT_intermed_1) else '0';
dfp_trap_vector(89) <= '0' when (VDSU_TT_shadow /= DSUR.TT) else '0';
dfp_trap_vector(90) <= '1' when (VP_PWD_shadow /= RP.PWD) else '0';
dfp_trap_vector(91) <= '1' when (VP_PWD_shadow /= '0') else '0';
dfp_trap_vector(92) <= '1' when (VP_PWD_shadow /= RPIN_PWD_intermed_1) else '0';
dfp_trap_vector(93) <= '0' when (VIR_PWD_shadow /= '0') else '0';
dfp_trap_vector(94) <= '0' when (VIR_PWD_shadow /= IRIN_PWD_intermed_1) else '0';
dfp_trap_vector(95) <= '0' when (VIR_PWD_shadow /= IR.PWD) else '0';
dfp_trap_vector(96) <= '0' when (VDSU_TBUFCNT_shadow /= DSUR.TBUFCNT) else '0';
dfp_trap_vector(97) <= '1' when (VDSU_TBUFCNT_shadow /= TBUFCNTX_shadow) else '0';
dfp_trap_vector(98) <= '0' when (VDSU_TBUFCNT_shadow /= DSUIN_TBUFCNT_intermed_1) else '0';
dfp_trap_vector(99) <= '0' when (V_W_EXCEPT_shadow /= XC_EXCEPTION_shadow) else '0';
dfp_trap_vector(100) <= '1' when (V_W_RESULT_shadow /= XC_RESULT_shadow) else '0';
dfp_trap_vector(101) <= '1' when (V_W_WA_shadow /= XC_WADDR7DOWNTO0_shadow) else '0';
dfp_trap_vector(102) <= '1' when (V_W_S_SVT_shadow /= R.W.S.SVT) else '0';
dfp_trap_vector(103) <= '1' when (V_W_S_SVT_shadow /= '0') else '0';
dfp_trap_vector(104) <= '1' when (V_W_S_SVT_shadow /= RIN_W_S_SVT_intermed_1) else '0';
dfp_trap_vector(105) <= '1' when (V_W_S_DWT_shadow /= RIN_W_S_DWT_intermed_1) else '0';
dfp_trap_vector(106) <= '1' when (V_W_S_DWT_shadow /= R.W.S.DWT) else '0';
dfp_trap_vector(107) <= '1' when (V_W_S_DWT_shadow /= '0') else '0';
dfp_trap_vector(108) <= '0' when (V_W_S_EF_shadow /= '0') else '0';
dfp_trap_vector(109) <= '0' when (V_W_S_EF_shadow /= R.W.S.EF) else '0';
dfp_trap_vector(110) <= '0' when (V_W_S_EF_shadow /= RIN_W_S_EF_intermed_1) else '0';
dfp_trap_vector(111) <= '1' when (V_X_DCI_shadow /= R.M.DCI) else '0';
dfp_trap_vector(112) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0';
dfp_trap_vector(113) <= '1' when (V_X_MAC_shadow /= V_E_MAC_shadow_intermed_2) else '0';
dfp_trap_vector(114) <= '1' when (V_X_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(115) <= '1' when (V_X_MAC_shadow /= RIN_E_MAC_intermed_2) else '0';
dfp_trap_vector(116) <= '1' when (V_X_MAC_shadow /= R_E_MAC_intermed_1) else '0';
dfp_trap_vector(117) <= '1' when (V_X_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(118) <= '1' when (V_X_MAC_shadow /= V_M_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(119) <= '1' when (V_X_MAC_shadow /= RIN_X_MAC_intermed_1) else '0';
dfp_trap_vector(120) <= '1' when (V_X_MAC_shadow /= R.X.MAC) else '0';
dfp_trap_vector(121) <= '1' when (V_X_LADDR_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0';
dfp_trap_vector(122) <= '1' when (V_X_MEXC_shadow /= DCO.MEXC) else '0';
dfp_trap_vector(123) <= '1' when (V_X_ICC_shadow /= ME_ICC_shadow) else '0';
dfp_trap_vector(124) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0';
dfp_trap_vector(125) <= '1' when (V_E_CWP_shadow /= R.A.CWP) else '0';
dfp_trap_vector(126) <= '1' when (V_M_SU_shadow /= R.E.SU) else '0';
dfp_trap_vector(127) <= '1' when (V_M_MUL_shadow /= RIN_M_MUL_intermed_1) else '0';
dfp_trap_vector(128) <= '1' when (V_M_MUL_shadow /= '0') else '0';
dfp_trap_vector(129) <= '1' when (V_M_MUL_shadow /= R.M.MUL) else '0';
dfp_trap_vector(130) <= '1' when (V_M_MAC_shadow /= V_E_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(131) <= '1' when (V_M_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(132) <= '1' when (V_M_MAC_shadow /= RIN_E_MAC_intermed_1) else '0';
dfp_trap_vector(133) <= '1' when (V_M_MAC_shadow /= R.E.MAC) else '0';
dfp_trap_vector(134) <= '1' when (V_M_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(135) <= '1' when (V_E_JMPL_shadow /= R.A.JMPL) else '0';
dfp_trap_vector(136) <= '1' when (V_E_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0';
dfp_trap_vector(137) <= '1' when (V_E_SU_shadow /= R.A.SU) else '0';
dfp_trap_vector(138) <= '1' when (V_E_ET_shadow /= R.A.ET) else '0';
dfp_trap_vector(139) <= '1' when (V_A_CWP_shadow /= R.D.CWP) else '0';
dfp_trap_vector(140) <= '1' when (V_A_CTRL_TRAP_shadow /= R.D.MEXC) else '0';
dfp_trap_vector(141) <= '1' when (V_A_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_1) else '0';
dfp_trap_vector(142) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_1) else '0';
dfp_trap_vector(143) <= '1' when (V_A_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(144) <= '1' when (V_A_CTRL_TT_shadow /= R.A.CTRL.TT) else '0';
dfp_trap_vector(145) <= '1' when (V_A_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(146) <= '1' when (V_A_CTRL_INST_shadow /= DE_INST_shadow) else '0';
dfp_trap_vector(147) <= '1' when (V_A_CTRL_PC_shadow /= R.D.PC) else '0';
dfp_trap_vector(148) <= '1' when (V_A_CTRL_CNT_shadow /= R.D.CNT) else '0';
dfp_trap_vector(149) <= '1' when (V_A_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(150) <= '1' when (V_A_STEP_shadow /= R.A.STEP) else '0';
dfp_trap_vector(151) <= '1' when (V_A_STEP_shadow /= DBGI_STEP_intermed_1) else '0';
dfp_trap_vector(152) <= '1' when (V_A_STEP_shadow /= V_D_STEP_shadow_intermed_1) else '0';
dfp_trap_vector(153) <= '1' when (V_A_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(154) <= '1' when (V_A_STEP_shadow /= RIN_A_STEP_intermed_1) else '0';
dfp_trap_vector(155) <= '1' when (V_D_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(156) <= '1' when (V_D_STEP_shadow /= DBGI.STEP) else '0';
dfp_trap_vector(157) <= '1' when (V_D_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(158) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow) else '0';
dfp_trap_vector(159) <= '0' when (VDSU_CRDY2_shadow /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(160) <= '0' when (VDSU_CRDY2_shadow /= DSUR.CRDY ( 2 )) else '0';
dfp_trap_vector(161) <= '0' when (VDSU_CRDY2_shadow /= VDSU_CRDY2_shadow_intermed_2) else '0';
dfp_trap_vector(162) <= '0' when (VDSU_CRDY2_shadow /= DSUIN_CRDY2_intermed_2) else '0';
dfp_trap_vector(163) <= '0' when (VDSU_CRDY2_shadow /= DSUR_CRDY2_intermed_1) else '0';
dfp_trap_vector(164) <= '0' when (VIR_ADDR31DOWNTO4_shadow /= IR.ADDR( 31 DOWNTO 4 )) else '0';
dfp_trap_vector(165) <= '0' when (VIR_ADDR31DOWNTO4_shadow /= IRIN_ADDR31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(166) <= '0' when (VIR_ADDR3DOWNTO2_shadow /= IRIN_ADDR3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(167) <= '0' when (VIR_ADDR3DOWNTO2_shadow /= IR.ADDR( 3 DOWNTO 2 )) else '0';
dfp_trap_vector(168) <= '0' when (VIR_ADDR31DOWNTO12_shadow /= IRIN_ADDR31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(169) <= '0' when (VIR_ADDR31DOWNTO12_shadow /= IR.ADDR( 31 DOWNTO 12 )) else '0';
dfp_trap_vector(170) <= '0' when (VIR_ADDR31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(171) <= '0' when (VIR_ADDR31DOWNTO2_shadow /= IR.ADDR( 31 DOWNTO 2 )) else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_86 : std_logic_vector(85 downto 0);
variable or_reduce_43 : std_logic_vector(42 downto 0);
variable or_reduce_22 : std_logic_vector(21 downto 0);
variable or_reduce_11 : std_logic_vector(10 downto 0);
variable or_reduce_6 : std_logic_vector(5 downto 0);
variable or_reduce_3 : std_logic_vector(2 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_86 := dfp_trap_vector(171 downto 86) OR dfp_trap_vector(85 downto 0);
or_reduce_43 := or_reduce_86(85 downto 43) OR or_reduce_86(42 downto 0);
or_reduce_22 := or_reduce_43(42 downto 21) OR ("0" & or_reduce_43(20 downto 0));
or_reduce_11 := or_reduce_22(21 downto 11) OR or_reduce_22(10 downto 0);
or_reduce_6 := or_reduce_11(10 downto 5) OR ("0" & or_reduce_11(4 downto 0));
or_reduce_3 := or_reduce_6(5 downto 3) OR or_reduce_6(2 downto 0);
or_reduce_2 := or_reduce_3(2 downto 1) OR ("0" & or_reduce_3(0 downto 0));
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0';
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then ir <= irin; end if;
end if;
end process;
dummy <= '1';
-- Control module for ChipScope Pro
dfp_bscan_host: iconScope
port map (
CONTROL0 => dfp_bscan_cntrl1
);
-- Debugging probe for trap mask
dfp_bscan_value <= dfp_trap_mem;
dfp_probe_msk : scope
port map (
CONTROL => dfp_bscan_cntrl1,
ASYNC_IN => dfp_bscan_value
);
end;
| mit | cdc9aa16eeb1abb8b7358adb7d4925b8 | 0.686704 | 2.273541 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/sparc/sparc_disas.vhd | 2 | 27,297 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sparc_disas
-- File: sparc_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
package sparc_disas is
function tostf(v:std_logic_vector) return string;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr, rest : boolean);
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean);
function ins2st(pc, op : std_logic_vector(31 downto 0)) return string;
end;
package body sparc_disas is
type base_type is (hex, dec);
subtype nibble is std_logic_vector(3 downto 0);
type pc_op_type is record
pc, op : std_logic_vector(31 downto 0);
end record;
function tostd(v:std_logic_vector) return string;
function tosth(v:std_logic_vector) return string;
function tostrd(n:integer) return string;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
type carr is array (0 to 9) of character;
constant darr : carr := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
function tostd(v:std_logic_vector) return string is
variable s : string(1 to 2);
variable val : integer;
begin
val := conv_integer(v); s(1) := darr(val / 10); s(2) := darr(val mod 10);
return(s);
end;
function tosth(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return(s);
end;
function tostf(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return("0x" & s);
end;
function tostrd(n:integer) return string is
variable len : integer := 0;
variable tmp : string(10 downto 1);
variable v : integer := n;
begin
for i in 0 to 9 loop
tmp(i+1) := darr(v mod 10);
if tmp(i+1) /= '0' then
len := i;
end if;
v := v/10;
end loop;
return(tmp(len+1 downto 1));
end;
function ireg2st(v : std_logic_vector) return string is
variable ctmp : character;
variable reg : std_logic_vector(4 downto 0);
begin
reg := v;
case reg(4 downto 3) is
when "00" => ctmp := 'g'; when "01" => ctmp := 'o';
when "10" => ctmp := 'l'; when "11" => ctmp := 'i';
when others => ctmp := 'X';
end case;
if v(4 downto 0) = "11110" then return("%fp");
elsif v(4 downto 0) = "01110" then return("%sp");
else return('%' & ctmp & tost('0' & reg(2 downto 0))); end if;
end;
function simm13dec(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable simm : std_logic_vector(12 downto 0) := insn.op(12 downto 0);
variable rs1 : std_logic_vector(4 downto 0) := insn.op(18 downto 14);
variable i : std_ulogic := insn.op(13);
variable sig : character;
variable fill : std_logic_vector(31 downto 13) := (others => simm(12));
begin
if i = '0' then
return("");
else
if (simm(12) = '1') and (base = dec) then
sig := '-'; simm := (not simm) + 1;
else
sig := '+';
end if;
if base = dec then
if merge then
if rs1 = "00000" then
return(tost(simm));
else
return(sig & tost(simm));
end if;
else
if rs1 = "00000" then
return(tost(simm));
else
if sig = '-' then
return(", " & sig & tost(simm));
else
return(", " & tost(simm));
end if;
end if;
end if;
else
if rs1 = "00000" then
if simm(12) = '1' then return(tost(fill & simm));
else return(tost(simm)); end if;
else
if simm(12) = '1' then return(", " & tost(fill & simm));
else return(", " & tost(simm)); end if;
end if;
end if;
end if;
end;
function freg2(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs2) &
", %f" & tostd(rd));
end;
function creg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%c" & tostd(rs1) & ", %c" & tostd(rs2) & ", %c" & tostd(rd));
end;
function freg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2) & ", %f" & tostd(rd));
end;
function fregc(insn : pc_op_type) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2));
end;
function regimm(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
i := insn.op(13);
if i = '0' then
if (rs1 = "00000") then
if (rs2 = "00000") then return("0");
else return(ireg2st(rs2)); end if;
else
if (rs2 = "00000") then return(ireg2st(rs1));
elsif merge then return(ireg2st(rs1) & " + " & ireg2st(rs2));
else return(ireg2st(rs1) & ", " & ireg2st(rs2)); end if;
end if;
else
if (rs1 = "00000") then return(simm13dec(insn, base, merge));
elsif insn.op(12 downto 0) = "0000000000000" then return(ireg2st(rs1));
else return(ireg2st(rs1) & simm13dec(insn, base, merge)); end if;
end if;
end;
function regres(insn : pc_op_type; base : base_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rd := insn.op(29 downto 25);
return(regimm(insn, base,false) & ", " & ireg2st(rd ));
end;
function branchop(insn : pc_op_type) return string is
variable simm : std_logic_vector(31 downto 0);
begin
case insn.op(28 downto 25) is
when "0000" => return("n");
when "0001" => return("e");
when "0010" => return("le");
when "0011" => return("l");
when "0100" => return("leu");
when "0101" => return("cs");
when "0110" => return("neg");
when "0111" => return("vs");
when "1000" => return("a");
when "1001" => return("ne");
when "1010" => return("g");
when "1011" => return("ge");
when "1100" => return("gu");
when "1101" => return("cc");
when "1110" => return("pos");
when "1111" => return("vc");
when others => return("XXX");
end case;
end;
function fbranchop(insn : pc_op_type) return string is
variable simm : std_logic_vector(31 downto 0);
begin
case insn.op(28 downto 25) is
when "0000" => return("n");
when "0001" => return("ne");
when "0010" => return("lg");
when "0011" => return("ul");
when "0100" => return("l");
when "0101" => return("ug");
when "0110" => return("g");
when "0111" => return("u");
when "1000" => return("a");
when "1001" => return("e");
when "1010" => return("ue");
when "1011" => return("ge");
when "1100" => return("uge");
when "1101" => return("le");
when "1110" => return("ule");
when "1111" => return("o");
when others => return("XXX");
end case;
end;
function ldparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%c" & tost(rd));
end;
function ldparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%f" & tostd(rd));
end;
function ldpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & ireg2st(rd));
end;
function ldpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)) & ", " & ireg2st(rd));
end;
function stparc(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
if rd = "00000" then
return("[" & regimm(insn,dec,true) & "]");
else
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end if;
end;
function stparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%c" & tost(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%f" & tostd(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)));
end;
function ins2st(pc, op : std_logic_vector(31 downto 0)) return string is
constant STMAX : natural := 9;
constant bl2 : string(1 to 2) := (others => ' ');
constant bb : string(1 to 4) := (others => ' ');
variable op1 : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opf : std_logic_vector(8 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable addr : std_logic_vector(31 downto 0);
variable annul : std_ulogic;
variable i : std_ulogic;
variable simm : std_logic_vector(12 downto 0);
variable insn : pc_op_type;
begin
op1 := op(31 downto 30);
op2 := op(24 downto 22);
op3 := op(24 downto 19);
opf := op(13 downto 5);
cond := op(28 downto 25);
annul := op(29);
rs1 := op(18 downto 14);
rs2 := op(4 downto 0);
rd := op(29 downto 25);
i := op(13);
simm := op(12 downto 0);
insn.op := op;
insn.pc := pc;
case op1 is
when CALL =>
addr := pc + (op(29 downto 0) & "00");
return(tostf(pc) & bb & "call" & bl2 & tost(addr));
when FMT2 =>
case op2 is
when SETHI =>
if rd = "00000" then
return(tostf(pc) & bb & "nop");
else
return(tostf(pc) & bb & "sethi" & bl2 & "%hi(" &
tost(op(21 downto 0) & "0000000000") & "), " & ireg2st(rd));
end if;
when BICC | FBFCC =>
addr(31 downto 24) := (others => '0');
addr(1 downto 0) := (others => '0');
addr(23 downto 2) := op(21 downto 0);
if addr(23) = '1' then
addr(31 downto 24) := (others => '1');
else
addr(31 downto 24) := (others => '0');
end if;
addr := addr + pc;
if op2 = BICC then
if op(29) = '1' then
return(tostf(pc) & bb & 'b' & branchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bb & 'b' & branchop(insn) & bl2 &
tost(addr));
end if;
else
if op(29) = '1' then
return(tostf(pc) & bb & "fb" & fbranchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bb & "fb" & fbranchop(insn) & bl2 &
tost(addr));
end if;
end if;
-- when CBCCC => cptrap := '1';
when others => return(tostf(pc) & bb & "unimp");
end case;
when FMT3 =>
case op3 is
when IAND => return(tostf(pc) & bb & "and" & bl2 & regres(insn,hex));
when IADD => return(tostf(pc) & bb & "add" & bl2 & regres(insn,dec));
when IOR =>
if ((i = '0') and (rs1 = "00000") and (rs2 = "00000")) then
return(tostf(pc) & bb & "clr" & bl2 & ireg2st(rd));
elsif ((i = '1') and (simm = "0000000000000")) or (rs1 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regres(insn,hex));
else
return(tostf(pc) & bb & "or " & bl2 & regres(insn,hex));
end if;
when IXOR => return(tostf(pc) & bb & "xor" & bl2 & regres(insn,hex));
when ISUB => return(tostf(pc) & bb & "sub" & bl2 & regres(insn,dec));
when ANDN => return(tostf(pc) & bb & "andn" & bl2 & regres(insn,hex));
when ORN => return(tostf(pc) & bb & "orn" & bl2 & regres(insn,hex));
when IXNOR =>
if ((i = '0') and ((rs1 = rd) or (rs2 = "00000"))) then
return(tostf(pc) & bb & "not" & bl2 & ireg2st(rd));
else
return(tostf(pc) & bb & "xnor" & bl2 & ireg2st(rd));
end if;
when ADDX => return(tostf(pc) & bb & "addx" & bl2 & regres(insn,dec));
when SUBX => return(tostf(pc) & bb & "subx" & bl2 & regres(insn,dec));
when ADDCC => return(tostf(pc) & bb & "addcc" & bl2 & regres(insn,dec));
when ANDCC => return(tostf(pc) & bb & "andcc" & bl2 & regres(insn,hex));
when ORCC => return(tostf(pc) & bb & "orcc" & bl2 & regres(insn,hex));
when XORCC => return(tostf(pc) & bb & "xorcc" & bl2 & regres(insn,hex));
when SUBCC => return(tostf(pc) & bb & "subcc" & bl2 & regres(insn,dec));
when ANDNCC => return(tostf(pc) & bb & "andncc" & bl2 & regres(insn,hex));
when ORNCC => return(tostf(pc) & bb & "orncc" & bl2 & regres(insn,hex));
when XNORCC => return(tostf(pc) & bb & "xnorcc" & bl2 & regres(insn,hex));
when ADDXCC => return(tostf(pc) & bb & "addxcc" & bl2 & regres(insn,hex));
when UMAC => return(tostf(pc) & bb & "umac" & bl2 & regres(insn,dec));
when SMAC => return(tostf(pc) & bb & "smac" & bl2 & regres(insn,dec));
when UMUL => return(tostf(pc) & bb & "umul" & bl2 & regres(insn,dec));
when SMUL => return(tostf(pc) & bb & "smul" & bl2 & regres(insn,dec));
when UMULCC => return(tostf(pc) & bb & "umulcc" & bl2 & regres(insn,dec));
when SMULCC => return(tostf(pc) & bb & "smulcc" & bl2 & regres(insn,dec));
when SUBXCC => return(tostf(pc) & bb & "subxcc" & bl2 & regres(insn,dec));
when UDIV => return(tostf(pc) & bb & "udiv" & bl2 & regres(insn,dec));
when SDIV => return(tostf(pc) & bb & "sdiv" & bl2 & regres(insn,dec));
when UDIVCC => return(tostf(pc) & bb & "udivcc" & bl2 & regres(insn,dec));
when SDIVCC => return(tostf(pc) & bb & "sdivcc" & bl2 & regres(insn,dec));
when TADDCC => return(tostf(pc) & bb & "taddcc" & bl2 & regres(insn,dec));
when TSUBCC => return(tostf(pc) & bb & "tsubcc" & bl2 & regres(insn,dec));
when TADDCCTV => return(tostf(pc) & bb & "taddcctv" & bl2 & regres(insn,dec));
when TSUBCCTV => return(tostf(pc) & bb & "tsubcctv" & bl2 & regres(insn,dec));
when MULSCC => return(tostf(pc) & bb & "mulscc" & bl2 & regres(insn,dec));
when ISLL => return(tostf(pc) & bb & "sll" & bl2 & regres(insn,dec));
when ISRL => return(tostf(pc) & bb & "srl" & bl2 & regres(insn,dec));
when ISRA => return(tostf(pc) & bb & "sra" & bl2 & regres(insn,dec));
when RDY =>
if rs1 /= "00000" then
return(tostf(pc) & bb & "mov" & bl2 & "%asr" &
tostd(rs1) & ", " & ireg2st(rd));
else
return(tostf(pc) & bb & "mov" & bl2 & "%y, " & ireg2st(rd));
end if;
when RDPSR => return(tostf(pc) & bb & "mov" & bl2 & "%psr, " & ireg2st(rd));
when RDWIM => return(tostf(pc) & bb & "mov" & bl2 & "%wim, " & ireg2st(rd));
when RDTBR => return(tostf(pc) & bb & "mov" & bl2 & "%tbr, " & ireg2st(rd));
when WRY =>
if (rs1 = "00000") or (rs2 = "00000") then
if rd /= "00000" then
return(tostf(pc) & bb & "mov" & bl2
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %y");
end if;
else
if rd /= "00000" then
return(tostf(pc) & bb & "wr " & bl2 & "%asr"
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %y");
end if;
end if;
when WRPSR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %psr");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %psr");
end if;
when WRWIM =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %wim");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %wim");
end if;
when WRTBR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %tbr");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %tbr");
end if;
when JMPL =>
if (rd = "00000") then
if (i = '1') and (simm = "0000000001000") then
if (rs1 = "11111") then return(tostf(pc) & bb & "ret");
elsif (rs1 = "01111") then return(tostf(pc) & bb & "retl");
else return(tostf(pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bb & "jmpl" & bl2 & regres(insn,dec));
end if;
when TICC =>
return(tostf(pc) & bb & 't' & branchop(insn) & bl2 & regimm(insn,hex,false));
when FLUSH =>
return(tostf(pc) & bb & "flush" & bl2 & regimm(insn,hex,false));
when RETT =>
return(tostf(pc) & bb & "rett" & bl2 & regimm(insn,dec,true));
when RESTORE =>
if (rd = "00000") then
return(tostf(pc) & bb & "restore");
else
return(tostf(pc) & bb & "restore" & bl2 & regres(insn,hex));
end if;
when SAVE =>
if (rd = "00000") then return(tostf(pc) & bb & "save");
else return(tostf(pc) & bb & "save" & bl2 & regres(insn,dec)); end if;
when FPOP1 =>
case opf is
when FITOS => return(tostf(pc) & bb & "fitos" & bl2 & freg2(insn));
when FITOD => return(tostf(pc) & bb & "fitod" & bl2 & freg2(insn));
when FSTOI => return(tostf(pc) & bb & "fstoi" & bl2 & freg2(insn));
when FDTOI => return(tostf(pc) & bb & "fdtoi" & bl2 & freg2(insn));
when FSTOD => return(tostf(pc) & bb & "fstod" & bl2 & freg2(insn));
when FDTOS => return(tostf(pc) & bb & "fdtos" & bl2 & freg2(insn));
when FMOVS => return(tostf(pc) & bb & "fmovs" & bl2 & freg2(insn));
when FNEGS => return(tostf(pc) & bb & "fnegs" & bl2 & freg2(insn));
when FABSS => return(tostf(pc) & bb & "fabss" & bl2 & freg2(insn));
when FSQRTS => return(tostf(pc) & bb & "fsqrts" & bl2 & freg2(insn));
when FSQRTD => return(tostf(pc) & bb & "fsqrtd" & bl2 & freg2(insn));
when FADDS => return(tostf(pc) & bb & "fadds" & bl2 & freg3(insn));
when FADDD => return(tostf(pc) & bb & "faddd" & bl2 & freg3(insn));
when FSUBS => return(tostf(pc) & bb & "fsubs" & bl2 & freg3(insn));
when FSUBD => return(tostf(pc) & bb & "fsubd" & bl2 & freg3(insn));
when FMULS => return(tostf(pc) & bb & "fmuls" & bl2 & freg3(insn));
when FMULD => return(tostf(pc) & bb & "fmuld" & bl2 & freg3(insn));
when FSMULD => return(tostf(pc) & bb & "fsmuld" & bl2 & freg3(insn));
when FDIVS => return(tostf(pc) & bb & "fdivs" & bl2 & freg3(insn));
when FDIVD => return(tostf(pc) & bb & "fdivd" & bl2 & freg3(insn));
when others => return(tostf(pc) & bb & "unknown FOP1: " & tost(op));
end case;
when FPOP2 =>
case opf is
when FCMPS => return(tostf(pc) & bb & "fcmps" & bl2 & fregc(insn));
when FCMPD => return(tostf(pc) & bb & "fcmpd" & bl2 & fregc(insn));
when FCMPES => return(tostf(pc) & bb & "fcmpes" & bl2 & fregc(insn));
when FCMPED => return(tostf(pc) & bb & "fcmped" & bl2 & fregc(insn));
when others => return(tostf(pc) & bb & "unknown FOP2: " & tost(insn.op));
end case;
when CPOP1 =>
return(tostf(pc) & bb & "cpop1" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when CPOP2 =>
return(tostf(pc) & bb & "cpop2" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(insn.op));
end case;
when LDST =>
case op3 is
when STC =>
return(tostf(pc) & bb & "st" & bl2 & stparcp(insn, rd, dec));
when STF =>
return(tostf(pc) & bb & "st" & bl2 & stparf(insn, rd, dec));
when ST =>
if rd = "00000" then
return(tostf(pc) & bb & "clr" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "st" & bl2 & stpar(insn, rd, dec));
end if;
when STB =>
if rd = "00000" then
return(tostf(pc) & bb & "clrb" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "stb" & bl2 & stpar(insn, rd, dec));
end if;
when STH =>
if rd = "00000" then
return(tostf(pc) & bb & "clrh" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "sth" & bl2 & stpar(insn, rd, dec));
end if;
when STDC =>
return(tostf(pc) & bb & "std" & bl2 & stparcp(insn, rd, dec));
when STDF =>
return(tostf(pc) & bb & "std" & bl2 & stparf(insn, rd, dec));
when STCSR =>
return(tostf(pc) & bb & "st" & bl2 & "%csr, [" & regimm(insn,dec,true) & "]");
when STFSR =>
return(tostf(pc) & bb & "st" & bl2 & "%fsr, [" & regimm(insn,dec,true) & "]");
when STDCQ =>
return(tostf(pc) & bb & "std" & bl2 & "%cq, [" & regimm(insn,dec,true) & "]");
when STDFQ =>
return(tostf(pc) & bb & "std" & bl2 & "%fq, [" & regimm(insn,dec,true) & "]");
when ISTD =>
return(tostf(pc) & bb & "std" & bl2 & stpar(insn, rd, dec));
when STA =>
return(tostf(pc) & bb & "sta" & bl2 & stpara(insn, rd, dec));
when STBA =>
return(tostf(pc) & bb & "stba" & bl2 & stpara(insn, rd, dec));
when STHA =>
return(tostf(pc) & bb & "stha" & bl2 & stpara(insn, rd, dec));
when STDA =>
return(tostf(pc) & bb & "stda" & bl2 & stpara(insn, rd, dec));
when LDC =>
return(tostf(pc) & bb & "ld" & bl2 & ldparcp(insn, rd, dec));
when LDF =>
return(tostf(pc) & bb & "ld" & bl2 & ldparf(insn, rd, dec));
when LDCSR =>
return(tostf(pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %csr");
when LDFSR =>
return(tostf(pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %fsr");
when LD =>
return(tostf(pc) & bb & "ld" & bl2 & ldpar(insn, rd, dec));
when LDUB =>
return(tostf(pc) & bb & "ldub" & bl2 & ldpar(insn, rd, dec));
when LDUH =>
return(tostf(pc) & bb & "lduh" & bl2 & ldpar(insn, rd, dec));
when LDDC =>
return(tostf(pc) & bb & "ldd" & bl2 & ldparcp(insn, rd, dec));
when LDDF =>
return(tostf(pc) & bb & "ldd" & bl2 & ldparf(insn, rd, dec));
when LDD =>
return(tostf(pc) & bb & "ldd" & bl2 & ldpar(insn, rd, dec));
when LDSB =>
return(tostf(pc) & bb & "ldsb" & bl2 & ldpar(insn, rd, dec));
when LDSH =>
return(tostf(pc) & bb & "ldsh" & bl2 & ldpar(insn, rd, dec));
when LDSTUB =>
return(tostf(pc) & bb & "ldstub" & bl2 & ldpar(insn, rd, dec));
when SWAP =>
return(tostf(pc) & bb & "swap" & bl2 & ldpar(insn, rd, dec));
when LDA =>
return(tostf(pc) & bb & "lda" & bl2 & ldpara(insn, rd, dec));
when LDUBA =>
return(tostf(pc) & bb & "lduba" & bl2 & ldpara(insn, rd, dec));
when LDUHA =>
return(tostf(pc) & bb & "lduha" & bl2 & ldpara(insn, rd, dec));
when LDDA =>
return(tostf(pc) & bb & "ldda" & bl2 & ldpara(insn, rd, dec));
when LDSBA =>
return(tostf(pc) & bb & "ldsba" & bl2 & ldpara(insn, rd, dec));
when LDSHA =>
return(tostf(pc) & bb & "ldsha" & bl2 & ldpara(insn, rd, dec));
when LDSTUBA =>
return(tostf(pc) & bb & "ldstuba" & bl2 & ldpara(insn, rd, dec));
when SWAPA =>
return(tostf(pc) & bb & "swapa" & bl2 & ldpara(insn, rd, dec));
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(op));
end case;
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(op));
end case;
end;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr, rest : boolean) is
variable t : integer;
begin
if valid then
t := now / 1 ns;
if trap then print (tost(t) & " cpu" & tost(ndx) &": " & ins2st(pc, op) & " (trapped)");
elsif rest then print (tost(t) & " cpu" & tost(ndx) &": " & ins2st(pc, op) & " (restart)");
elsif wr then print (tost(t) & " cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res) & "]");
else print (tost(t) & " cpu" & tost(ndx) & ": " & ins2st(pc, op)); end if;
end if;
end;
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean) is
variable t : integer;
begin
if valid then
t := now / 1 ns;
if trap then print (tost(t) & " cpu" & tost(ndx) &": " & ins2st(pc, op) & " (trapped)");
elsif wr then
if dpres then print (tost(t) & " cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res) & "]");
else print (tost(t) & " cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res(63 downto 32)) & "]"); end if;
else print (tost(t) & " cpu" & tost(ndx) & ": " & ins2st(pc, op)); end if;
end if;
end;
end;
-- pragma translate_on
| mit | 4406b6ea660c7b5cdd39da2373971d84 | 0.56127 | 2.931064 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/i2c/i2c_master_bit_ctrl.vhd | 2 | 20,013 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]):
-- * Added two start states to fulfill Set-up time for
-- repeated START condition.
-- * Modified synchronization of SCL and SDA. START and STOP detection
-- is now performed after a two stage synchronizer and is also
-- filtered.
-- * Changed evaluation order of 'slave_wait', 'en' and 'cnt' in
-- generation of clk_en signal to prevent clk_en assertion when
-- slave_wait is asserted.
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e, start_f, start_g,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal disda_oen : std_logic; -- delayed isda_oen
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic_vector(1 downto 0); -- delayed scl_oen signals
-- synchronized SCL and SDA inputs
signal sSCL, sSDA : std_logic_vector(5 downto 0);
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
dscl_oen <= dscl_oen(0) & iscl_oen;
end if;
end process;
slave_wait <= dscl_oen(1) and not sSCL(1);
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif (ena = '0') then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
elsif (cnt = X"0000") then
cnt <= clk_cnt;
clk_en <= '1';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
--signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= (others => '1');
sSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= (others => '1');
sSDA <= (others => '1');
else
sSCL <= sSCL(4 downto 0) & scl_i;
sSDA <= sSDA(4 downto 0) & sda_i;
end if;
end if;
end process synch_SCL_SDA;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
if sSCL(5 downto 2) = "1111" and sSDA(5 downto 2) = "1100" then
sta_condition <= '1';
else
sta_condition <= '0';
end if;
if sSCL(5 downto 2) = "1111" and sSDA(5 downto 2) = "0011" then
sto_condition <= '1';
else
sto_condition <= '0';
end if;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
disda_oen <= '1';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA(1) and disda_oen);
else
ial <= (sda_chk and not sSDA(1) and disda_oen) or
(sto_condition and not cmd_stop);
end if;
disda_oen <= isda_oen;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if sSCL(3 downto 2) = "01" then
dout <= sSDA(2);
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= start_f;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_f =>
c_state <= start_g;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_g =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
| mit | fcb5aa3d9cd64aa087f417b3b258c4f4 | 0.448059 | 3.96297 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/Kernel/SboxRegisters.vhd | 1 | 5,940 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox_registers is
port(
Clk : in std_logic; -- Clock
Shift0In : in std_logic_vector(15 downto 0);
Shift1In : in std_logic_vector(15 downto 0);
Shift2In : in std_logic_vector(15 downto 0);
Shift3In : in std_logic_vector(15 downto 0);
Shift4In : in std_logic_vector(15 downto 0);
Shift0Out : out std_logic_vector(15 downto 0);
Shift1Out : out std_logic_vector(15 downto 0);
Shift2Out : out std_logic_vector(15 downto 0);
Shift3Out : out std_logic_vector(15 downto 0);
Shift4Out : out std_logic_vector(15 downto 0);
load0in : in std_logic_vector(63 downto 0);
load1in : in std_logic_vector(63 downto 0);
load2in : in std_logic_vector(63 downto 0);
load3in : in std_logic_vector(63 downto 0);
load4in : in std_logic_vector(63 downto 0);
load0out : out std_logic_vector(63 downto 0);
load1out : out std_logic_vector(63 downto 0);
load2out : out std_logic_vector(63 downto 0);
load3out : out std_logic_vector(63 downto 0);
load4out : out std_logic_vector(63 downto 0);
Sel : in std_logic_vector(1 downto 0);
ShiftEnable : in std_logic;
Reg0En : in std_logic;
Reg1En : in std_logic;
Reg2En : in std_logic;
Reg3En : in std_logic;
Reg4En : in std_logic
);
end entity Sbox_registers;
architecture structural of Sbox_registers is
signal Part0_0, Part0_1, Part0_2, Part0_3 : std_logic_vector(15 downto 0);
signal Part1_0, Part1_1, Part1_2, Part1_3 : std_logic_vector(15 downto 0);
signal Part2_0, Part2_1, Part2_2, Part2_3 : std_logic_vector(15 downto 0);
signal Part3_0, Part3_1, Part3_2, Part3_3 : std_logic_vector(15 downto 0);
signal Part4_0, Part4_1, Part4_2, Part4_3 : std_logic_vector(15 downto 0);
begin
----------------------------------
------ Combinatorial logic ------
----------------------------------
datapath: process(Part0_0, Part0_1, Part0_2, Part0_3, Part1_0, Part1_1, Part1_2, Part1_3, Part2_0, Part2_1, Part2_2, Part2_3,
Part3_0, Part3_1, Part3_2, Part3_3, Part4_0, Part4_1, Part4_2, Part4_3, Sel) is
begin
load0out <= Part0_0 & Part0_1 & Part0_2 & Part0_3;
load1out <= Part1_0 & Part1_1 & Part1_2 & Part1_3;
load2out <= Part2_0 & Part2_1 & Part2_2 & Part2_3;
load3out <= Part3_0 & Part3_1 & Part3_2 & Part3_3;
load4out <= Part4_0 & Part4_1 & Part4_2 & Part4_3;
if Sel = "00" then
Shift0Out <= Part0_0;
Shift1Out <= Part1_0;
Shift2Out <= Part2_0;
Shift3Out <= Part3_0;
Shift4Out <= Part4_0;
elsif Sel = "01" then
Shift0Out <= Part0_1;
Shift1Out <= Part1_1;
Shift2Out <= Part2_1;
Shift3Out <= Part3_1;
Shift4Out <= Part4_1;
elsif Sel = "10" then
Shift0Out <= Part0_2;
Shift1Out <= Part1_2;
Shift2Out <= Part2_2;
Shift3Out <= Part3_2;
Shift4Out <= Part4_2;
else
Shift0Out <= Part0_3;
Shift1Out <= Part1_3;
Shift2Out <= Part2_3;
Shift3Out <= Part3_3;
Shift4Out <= Part4_3;
end if;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk) is
begin
if(Clk = '1' and Clk'event) then
if ShiftEnable = '1' then
if Sel = "00" then
Part0_0 <= Shift0In;
Part1_0 <= Shift1In;
Part2_0 <= Shift2In;
Part3_0 <= Shift3In;
Part4_0 <= Shift4In;
elsif Sel = "01" then
Part0_1 <= Shift0In;
Part1_1 <= Shift1In;
Part2_1 <= Shift2In;
Part3_1 <= Shift3In;
Part4_1 <= Shift4In;
elsif Sel = "10" then
Part0_2 <= Shift0In;
Part1_2 <= Shift1In;
Part2_2 <= Shift2In;
Part3_2 <= Shift3In;
Part4_2 <= Shift4In;
elsif Sel = "11" then
Part0_3 <= Shift0In;
Part1_3 <= Shift1In;
Part2_3 <= Shift2In;
Part3_3 <= Shift3In;
Part4_3 <= Shift4In;
end if;
else
if Reg0En = '1' then
Part0_0 <= load0in(63 downto 48);
Part0_1 <= load0in(47 downto 32);
Part0_2 <= load0in(31 downto 16);
Part0_3 <= load0in(15 downto 0);
end if;
if Reg1En = '1' then
Part1_0 <= load1in(63 downto 48);
Part1_1 <= load1in(47 downto 32);
Part1_2 <= load1in(31 downto 16);
Part1_3 <= load1in(15 downto 0);
end if;
if Reg2En = '1' then
Part2_0 <= load2in(63 downto 48);
Part2_1 <= load2in(47 downto 32);
Part2_2 <= load2in(31 downto 16);
Part2_3 <= load2in(15 downto 0);
end if;
if Reg3En = '1' then
Part3_0 <= load3in(63 downto 48);
Part3_1 <= load3in(47 downto 32);
Part3_2 <= load3in(31 downto 16);
Part3_3 <= load3in(15 downto 0);
end if;
if Reg4En = '1' then
Part4_0 <= load4in(63 downto 48);
Part4_1 <= load4in(47 downto 32);
Part4_2 <= load4in(31 downto 16);
Part4_3 <= load4in(15 downto 0);
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 | 11e87a7fe6d224cc853ca97a8adabee5 | 0.579125 | 2.846191 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/unisim/pads_unisim.vhd | 2 | 28,969 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: pad_xilinx_gen
-- File: pad_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Xilinx pads wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUF;
-- pragma translate_on
entity virtex_inpad is
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex_inpad is
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage /= x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_I") port map (O => o, I => pad);
end generate;
sstl2y : if level = sstl2_ii generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos)
and (level /= sstl2_i)and (level /= sstl2_ii) generate
ip : IBUF port map (O => o, I => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUF;
-- pragma translate_on
entity virtex_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of virtex_iopad is
component IOBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_5")
port map (O => o, IO => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_3")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl2y : if level = sstl2_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18i : if level = sstl18_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18ii : if level = sstl18_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and (level /= sstl18_i) and (level /= sstl18_ii) generate
op : IOBUF port map (O => o, IO => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
-- pragma translate_on
entity virtex_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of virtex_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => i);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => i);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => i);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => i);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFT;
-- pragma translate_on
entity virtex_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i, en : in std_ulogic);
end ;
architecture rtl of virtex_toutpad is
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
op : OBUFT port map (O => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
entity virtex_skew_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end ;
architecture rtl of virtex_skew_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal reset, clk0, clk0b, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
reset <= not rst;
dll0 : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => skew)
port map ( CLKIN => i, CLKFB => clk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => reset, CLK0 => clk0);
bufg0 : BUFG port map (I => clk0, O => clk0b);
o <= clk0b; -- output before pad
--x0 : virtex_outpad generic map (level, slew, voltage, strength) port map (pad, clk0b);
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => clk0b);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => clk0b);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => clk0b);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => clk0b);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => clk0b);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => clk0b);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => clk0b);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFG;
use unisim.IBUF;
use unisim.BUFGMUX;
use unisim.BUFG;
use unisim.BUFGDLL;
-- pragma translate_on
entity virtex_clkpad is
generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1');
end;
architecture rtl of virtex_clkpad is
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
--component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
component CLKDLL port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLK270 : out std_ulogic;
CLK2X : out std_ulogic; CLK90 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic; RST : in std_ulogic);
end component;
signal gnd, ol, ol2, ol3 : std_ulogic;
signal rst : std_ulogic;
begin
gnd <= '0'; rst <= not rstn;
g0 : if arch = 0 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage /= x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
end generate;
sstl2 : if level = sstl2_ii generate
ip : IBUFG generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and (level /= sstl2_ii) generate
ip : IBUFG port map (O => o, I => pad);
end generate;
end generate;
g1 : if arch = 1 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
cmos0 : if level = cmos generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUF port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
end generate;
g2 : if arch = 2 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos0 : if level = cmos generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUFG port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
g3 : if arch = 3 generate
ip : IBUFG port map (O => ol, I => pad);
hf0 : if hf = 0 generate
dll: CLKDLL port map(
CLK0 => ol2,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK90 => open,
CLKDV => open,
LOCKED => open,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
hf1 : if hf = 1 generate
dll : CLKDLLHF
port map(
CLK0 => ol2,
CLK180 => open,
CLKDV => open,
LOCKED => open,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
bf : BUFG port map (O => ol3, I => ol2);
o <= ol3;
end generate g3;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFDS_LVDS_25;
use unisim.OBUFDS_LVDS_33;
-- pragma translate_on
entity virtex_outpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of virtex_outpad_ds is
component OBUFDS_LVDS_25
port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
component OBUFDS_LVDS_33
port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS_LVDS_33 port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS_LVDS_25 port map (O => padp, OB => padn, I => i);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS_LVDS_25;
use unisim.IBUFDS_LVDS_33;
-- pragma translate_on
entity virtex_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex_inpad_ds is
component IBUFDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS_LVDS_25;
use unisim.IBUFGDS_LVDS_33;
-- pragma translate_on
entity virtex_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex_clkpad_ds is
component IBUFGDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFGDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS;
-- pragma translate_on
entity virtex4_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_inpad_ds is
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS;
-- pragma translate_on
entity virtex4_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_clkpad_ds is
component IBUFGDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUFDS;
-- pragma translate_on
entity virtex5_iopad_ds is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of virtex5_iopad_ds is
component IOBUFDS generic (
CAPACITANCE : string := "DONT_CARE"; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT"; IFD_DELAY_VALUE : string := "AUTO");
port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic); end component;
begin
iop : IOBUFDS generic map (IOSTANDARD => "DEFAULT")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFDS;
-- pragma translate_on
entity virtex5_outpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of virtex5_outpad_ds is
component OBUFDS generic( IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_33")
port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_25")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
xsstl18_i : if level = sstl18_i generate
op : OBUFDS generic map(IOSTANDARD => "SSTL18_I")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_ii : if level = sstl18_ii generate
op : OBUFDS generic map(IOSTANDARD => "SSTL18_II")
port map (O => padp, OB => padn, I => i);
end generate;
end;
| mit | 3ddaf7d9b2a8b4b52692028a464187a1 | 0.597397 | 3.510968 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/unisim/clkgen_unisim.vhd | 2 | 29,179 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex2 clock generator ---------------------------------------
------------------------------------------------------------------
entity clkgen_virtex2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex2 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "20.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
bufg3 : BUFG port map (I => clk_x, O => clk_i2);
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex2" & ": virtex-2 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex2" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.CLKDLL;
use unisim.BUFGDLL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture rtl of clkgen_virtex is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, dll0rst, dll0lock, dll1lock : std_logic;
signal dll1rst : std_logic_vector(0 to 3);
signal clk0B, clkint, CLK2XL, CLKDV, CLK180, pciclkint : std_logic;
begin
gnd <= '0'; clk <= clk_i; clkn <= not clk_i;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0rst <= not cgi.pllrst;
dll0 : CLKDLL
port map (CLKIN => clkint, CLKFB => clk_k, CLK0 => clk_j, CLK180 => CLK180,
CLK2X => CLK2XL, CLKDV => CLKDV, LOCKED => dll0lock, RST => dll0rst);
clk0B <= CLK2XL when clk_mul/clk_div = 2
else CLKDV when clk_div/clk_mul = 2 else clk_j;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB = 0) generate
cgo.clklock <= dll1lock;
dll1 : CLKDLL
port map (CLKIN => clk_i, CLKFB => cgi.pllref, RST => dll1rst(0), CLK0 => sdclk,
CLK2X => clk2x, LOCKED => dll1lock);
rstdel : process (clk_i)
begin
if dll0lock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_i) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if not ((SDRAMEN /= 0) and (NOCLKFB = 0)) generate
sdclk <= clk_i; cgo.clklock <= dll0lock;
end generate;
cgo.pcilock <= '1';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkmul_virtex2 is
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end;
architecture struct of clkmul_virtex2 is
-- attribute CLKFX_MULTIPLY : string;
-- attribute CLKFX_DIVIDE : string;
attribute CLKIN_PERIOD : string;
--
-- attribute CLKFX_MULTIPLY of dll0: label is "5";
-- attribute CLKFX_DIVIDE of dll0: label is "4";
attribute CLKIN_PERIOD of dll0: label is "20";
--
-- attribute CLKFX_MULTIPLY of dll1: label is "4";
-- attribute CLKFX_DIVIDE of dll1: label is "4";
-- attribute CLKIN_PERIOD of dll1: label is "25";
--
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, clk_l : std_logic;
signal clk0B, clk_FB, dll0rst, lock : std_logic;
begin
gnd <= '0'; clk <= clk_i;
dll0rst <= not resetin;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkin, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
LOCKED => resetout, CLKFX => clk0B );
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_spartan3 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 50000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_spartan3 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "20.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= not clk_i when (CLK2XEN = 0) else not clk_p;
clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_j;
clk2xu <= clk_k;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_x, O => clk_k);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "2X")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_k;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_spartan3e" & ": spartan3/e sdram/pci clock generator, version " & tost(VERSION),
"clkgen_spartan3e" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
------------------------------------------------------------------
-- Virtex5 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex5 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex5 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "20.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, lsdclk : std_logic;
signal clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r: std_logic;
signal dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_x;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
bufgx : BUFG port map (I => lsdclk, O => sdclk);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex5" & ": virtex-5 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex5" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkand_unisim is
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand_unisim is
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end component;
begin
buf : bufgce port map(I => i, CE => en, O => o);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_unisim is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_unisim is
component bufgmux is
port(
i0, i1 : in std_ulogic;
s : in std_ulogic;
o : out std_ulogic);
end component;
signal sel0, sel1, cg0, cg1 : std_ulogic;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
| mit | 8b8536fed26f0a1d7b596d790c58ce5d | 0.584427 | 3.263505 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/gencomp/netcomp.vhd | 2 | 31,710 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: netcomp
-- File: netcomp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Delcation of netlists componnets
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use work.gencomp.all;
package netcomp is
---------------------------------------------------------------------------
-- netlists ---------------------------------------------------------------
---------------------------------------------------------------------------
component usbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
component grspwc_net
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grlfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component leon3ft_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic
);
end component;
component ftmctrl_net
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
memi_data: in Std_Logic_Vector(31 downto 0);
memi_brdyn: in Std_Logic;
memi_bexcn: in Std_Logic;
memi_writen: in Std_Logic;
memi_wrn: in Std_Logic_Vector(3 downto 0);
memi_bwidth: in Std_Logic_Vector(1 downto 0);
memi_sd: in Std_Logic_Vector(63 downto 0);
memi_cb: in Std_Logic_Vector(7 downto 0);
memi_scb: in Std_Logic_Vector(7 downto 0);
memi_edac: in Std_Logic;
memo_address: out Std_Logic_Vector(31 downto 0);
memo_data: out Std_Logic_Vector(31 downto 0);
memo_sddata: out Std_Logic_Vector(63 downto 0);
memo_ramsn: out Std_Logic_Vector(7 downto 0);
memo_ramoen: out Std_Logic_Vector(7 downto 0);
memo_ramn: out Std_ULogic;
memo_romn: out Std_ULogic;
memo_mben: out Std_Logic_Vector(3 downto 0);
memo_iosn: out Std_Logic;
memo_romsn: out Std_Logic_Vector(7 downto 0);
memo_oen: out Std_Logic;
memo_writen: out Std_Logic;
memo_wrn: out Std_Logic_Vector(3 downto 0);
memo_bdrive: out Std_Logic_Vector(3 downto 0);
memo_vbdrive: out Std_Logic_Vector(31 downto 0);
memo_svbdrive: out Std_Logic_Vector(63 downto 0);
memo_read: out Std_Logic;
memo_sa: out Std_Logic_Vector(14 downto 0);
memo_cb: out Std_Logic_Vector(7 downto 0);
memo_scb: out Std_Logic_Vector(7 downto 0);
memo_vcdrive: out Std_Logic_Vector(7 downto 0);
memo_svcdrive: out Std_Logic_Vector(7 downto 0);
memo_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0);
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0);
sdo_sdwen: out Std_ULogic;
sdo_rasn: out Std_ULogic;
sdo_casn: out Std_ULogic;
sdo_dqm: out Std_Logic_Vector( 7 downto 0);
wpo_wprothit: in Std_ULogic);
end component;
component ssrctrl_net
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
end;
| mit | 01ba6b4b13820e23b3d4bdc139dad54b | 0.559161 | 3.297286 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/Kernel/Ascon_block_datapath.vhd | 1 | 7,915 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic_vector(3 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
SelSbox : in std_logic_vector(1 downto 0);
SelDiff : in std_logic_vector(2 downto 0);
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
SboxEnable : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(2 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80400c0600000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal SboxReg0In,SboxReg1In,SboxReg2In,SboxReg3In,SboxReg4In : std_logic_vector(63 downto 0);
signal SboxReg0Out,SboxReg1Out,SboxReg2Out,SboxReg3Out,SboxReg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal Sbox0In,Sbox1In,Sbox2In,Sbox3In,Sbox4In : std_logic_vector(15 downto 0);
signal Sbox0Out,Sbox1Out,Sbox2Out,Sbox3Out,Sbox4Out : std_logic_vector(15 downto 0);
signal Diff1In, Diff2In, Diff3In, DiffOut : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg12,XorReg13,XorReg22 : std_logic_vector(63 downto 0);
signal XorReg31,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0 : std_logic_vector(63 downto 0);
signal OutSig1 : std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
sboxregisters: entity work.Sbox_registers port map(Clk ,Sbox0Out, Sbox1Out, Sbox2Out, Sbox3Out, Sbox4Out, Sbox0In, Sbox1In, Sbox2In, Sbox3In, Sbox4In,
SboxReg0In, SboxReg1In, SboxReg2In, SboxReg3In, SboxReg4In, SboxReg0Out, SboxReg1Out, SboxReg2Out, SboxReg3Out, SboxReg4Out,
SelSbox, SboxEnable, Reg0En, Reg1En, Reg2En, Reg3En, Reg4En);
sbox: entity work.Sbox port map(Sbox0In,Sbox1In,Sbox2In,Sbox3In,Sbox4In,RoundNr,Sbox0Out,Sbox1Out,Sbox2Out,Sbox3Out,Sbox4Out,SelSbox);
difflayer: entity work.FullDiffusionLayer port map(Diff1In,Diff2In,Diff3In,DiffOut);
outpgen: entity work.OutputGenerator port map(SboxReg0Out,DataIn,GenSize,ActivateGen,XorReg01,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(Diff1In, Diff2In, Diff3In, DiffOut, SboxReg0In, SboxReg1In, SboxReg2In, SboxReg3In, SboxReg4In,
XorReg01,XorReg02,XorReg12,XorReg13,XorReg22,XorReg31,XorReg4,OutSig0, OutSig1,
SboxReg0Out, SboxReg1Out, SboxReg2Out, SboxReg3Out, SboxReg4Out, Key, IV, RegOutIn, RegOutOut, sel0, sel1, sel2, sel3, sel4,
selout) is
begin
-- Set correct inputs in registers
if sel0 = "000" then
SboxReg0In <= DiffOut;
elsif sel0 = "001" then
SboxReg0In <= EXTRAIV;
elsif sel0 = "010" then
SboxReg0In <= XorReg01;
elsif sel0 = "011" then
SboxReg0In <= XorReg02;
else
SboxReg0In <= SboxReg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
SboxReg1In <= DiffOut;
elsif sel1 = "01" then
SboxReg1In <= Key(127 downto 64);
elsif sel1 = "10" then
SboxReg1In <= XorReg13;
else
SboxReg1In <= XorReg12;
end if;
if sel2 = "00" then
SboxReg2In <= DiffOut;
elsif sel2 = "01" then
SboxReg2In <= Key(63 downto 0);
else
SboxReg2In <= XorReg22;
end if;
if sel3 = "00" then
SboxReg3In <= DiffOut;
elsif sel3 = "01" then
SboxReg3In <= IV(127 downto 64);
else
SboxReg3In <= XorReg31;
end if;
if sel4 = "00" then
SboxReg4In <= DiffOut;
elsif sel4 = "01" then
SboxReg4In <= IV(63 downto 0);
elsif sel4 = "10" then
SboxReg4In <= XorReg4;
else
SboxReg4In <= SboxReg4Out xor SEPCONSTANT;
end if;
XorReg02 <= SboxReg0Out xor Key(127 downto 64);
XorReg12 <= SboxReg1Out xor Key(63 downto 0);
XorReg13 <= SboxReg1Out xor Key(127 downto 64);
XorReg22 <= SboxReg2Out xor Key(63 downto 0);
XorReg31 <= SboxReg3Out xor Key(127 downto 64);
XorReg4 <= SboxReg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn(127 downto 64) <= (others => '0');
RegOutIn(63 downto 0) <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
if SelDiff = "000" then
Diff1In(63 downto 64 - 19) <= SboxReg0Out(19 - 1 downto 0);
Diff1In(63 - 19 downto 0) <= SboxReg0Out(63 downto 19);
Diff2In(63 downto 64 - 28) <= SboxReg0Out(28 - 1 downto 0);
Diff2In(63 - 28 downto 0) <= SboxReg0Out(63 downto 28);
Diff3In <= SboxReg0Out;
elsif SelDiff = "001" then
Diff1In(63 downto 64 - 61) <= SboxReg1Out(61 - 1 downto 0);
Diff1In(63 - 61 downto 0) <= SboxReg1Out(63 downto 61);
Diff2In(63 downto 64 - 39) <= SboxReg1Out(39 - 1 downto 0);
Diff2In(63 - 39 downto 0) <= SboxReg1Out(63 downto 39);
Diff3In <= SboxReg1Out;
elsif SelDiff = "010" then
Diff1In(63 downto 64 - 1) <= SboxReg2Out(1 - 1 downto 0);
Diff1In(63 - 1 downto 0) <= SboxReg2Out(63 downto 1);
Diff2In(63 downto 64 - 6) <= SboxReg2Out(6 - 1 downto 0);
Diff2In(63 - 6 downto 0) <= SboxReg2Out(63 downto 6);
Diff3In <= SboxReg2Out;
elsif SelDiff = "011" then
Diff1In(63 downto 64 - 10) <= SboxReg3Out(10 - 1 downto 0);
Diff1In(63 - 10 downto 0) <= SboxReg3Out(63 downto 10);
Diff2In(63 downto 64 - 17) <= SboxReg3Out(17 - 1 downto 0);
Diff2In(63 - 17 downto 0) <= SboxReg3Out(63 downto 17);
Diff3In <= SboxReg3Out;
else
Diff1In(63 downto 64 - 7) <= SboxReg4Out(7 - 1 downto 0);
Diff1In(63 - 7 downto 0) <= SboxReg4Out(63 downto 7);
Diff2In(63 downto 64 - 41) <= SboxReg4Out(41 - 1 downto 0);
Diff2In(63 - 41 downto 0) <= SboxReg4Out(63 downto 41);
Diff3In <= SboxReg4Out;
end if;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
RegOutOut <= (others => '0');
else
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 | 2bf7fb803236b7a379c1545d8032a89b | 0.650032 | 2.939101 | false | false | false | false |
amerc/phimii | source/ethernet.vhd | 1 | 29,729 | --------------------------------------------------------------------------------
---
--- Ethernet MAC for Nexsys3 board
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
--- Revised by Amer Al-Canaan 2014
--- An ethernet MAC
---
--------------------------------------------------------------------------------
---
---10/100 Mbit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a MII interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
--MII IF
TXCLK : in std_logic; --
TXER : out std_logic; --
TXEN : out std_logic; --
TXD : out std_logic_vector(3 downto 0); --
RXCLK : in std_logic;--
RXER : in std_logic;--
RXDV : in std_logic; --
RXD : in std_logic_vector(3 downto 0);--
COL : in std_logic;-- *input Added
PhyCRS : in std_logic;-- *input Added
--RX STREAM
--fx2Clk_in : in std_logic;
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic;
GPIO_LEDS : out std_logic_vector(3 downto 0);
-- Btn
BtnL : in std_logic;
--7 seg
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anodes_out : out std_logic_vector(3 downto 0); -- seven-segment display anodes (one for each digit)
SW0 : in std_logic
);
end entity ethernet;
architecture RTL of ethernet is
--component RxTstFIFO2K
-- port (
-- rst : in STD_LOGIC;
-- wr_clk : in STD_LOGIC;
-- rd_clk : in STD_LOGIC;
-- din : in STD_LOGIC_VECTOR(7 DOWNTO 0);
-- wr_en : in STD_LOGIC;
-- rd_en : in STD_LOGIC;
-- dout : out STD_LOGIC_VECTOR(15 DOWNTO 0);
-- full : out STD_LOGIC;
-- empty : out STD_LOGIC
-- );
--end component;
COMPONENT OneHz25MHz
PORT(
Clk : IN std_logic;
op : OUT std_logic
);
END COMPONENT;
component seven_seg is
port(
clk_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
dots_in : in std_logic_vector(3 downto 0);
segs_out : out std_logic_vector(7 downto 0);
anodes_out : out std_logic_vector(3 downto 0)
);
end component;
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1023) of -- Modified :)
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE_0, PREAMBLE_1,
PREAMBLE_2, PREAMBLE_3, PREAMBLE_4, PREAMBLE_5, PREAMBLE_6, PREAMBLE_7,
PREAMBLE_8, PREAMBLE_9, PREAMBLE_10, PREAMBLE_11, PREAMBLE_12, PREAMBLE_13,
SFD_LOW, SFD_HIGH, SEND_DATA_HI_LO, SEND_DATA_LO_HI, SEND_DATA_HI_HI,
SEND_DATA_LO_LO, SEND_CRC_7, SEND_CRC_6, SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE, DATA_HIGH_HIGH,
DATA_HIGH_LOW, DATA_LOW_HIGH, DATA_LOW_LOW, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1513;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1513;
signal TX_READ_ADDRESS : integer range 0 to 1513;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1513;
signal TX_OUT_COUNT : integer range 0 to 1513;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(3 downto 0);
signal LOW_NIBBLE : std_logic_vector(3 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
--- 7 seg
signal Tosseg_dat : std_logic_vector(15 downto 0);
signal ssflags : std_logic_vector(3 downto 0);
signal ToFIFOdata : std_logic_vector(7 downto 0);
signal FIFO_we : std_logic;
signal FIFO_WR_EN : std_logic;
signal FIFO_Ren : std_logic;
signal FIFOout : std_logic_vector(15 downto 0);
signal FIFO_full : std_logic;
signal FIFO_empty : std_logic;
signal CLK1Hz : std_logic;
signal ToREN : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process reads data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(TXCLK);--CLK_25_MHZ
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_CLK_25 : process
begin
wait until rising_edge(TXCLK);--CLK_25_MHZ
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
CLK_25_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(TXCLK);--CLK_25_MHZ
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE_0;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
end if;
when PREAMBLE_0 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_1;
TXEN <= '1';
when PREAMBLE_1 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_2;
when PREAMBLE_2 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_3;
when PREAMBLE_3 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_4;
when PREAMBLE_4 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_5;
when PREAMBLE_5 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_6;
when PREAMBLE_6 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_7;
when PREAMBLE_7 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_8;
TXEN <= '1'; -- AMERR
when PREAMBLE_8 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_9;
when PREAMBLE_9 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_10;
when PREAMBLE_10 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_11;
when PREAMBLE_11 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_12;
when PREAMBLE_12 =>
TXD <= X"5";
TX_PHY_STATE <= PREAMBLE_13;
when PREAMBLE_13 =>
TXD <= X"5";
TX_PHY_STATE <= SFD_LOW;
when SFD_LOW =>
TXD <= X"5";
TX_PHY_STATE <= SFD_HIGH;
when SFD_HIGH =>
TXD <= X"D";
TX_PHY_STATE <= SEND_DATA_HI_LO;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_HI_LO =>
TXD <= TX_READ_DATA(11 downto 8);
TX_PHY_STATE <= SEND_DATA_HI_HI;
when SEND_DATA_HI_HI =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 12);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_7;
else
TX_PHY_STATE <= SEND_DATA_LO_LO;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_LO_LO =>
TXD <= TX_READ_DATA(3 downto 0);
TX_PHY_STATE <= SEND_DATA_LO_HI;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_LO_HI =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 4);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_7;
else
TX_PHY_STATE <= SEND_DATA_HI_LO;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 4);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 0);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 4);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 4);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 0);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 4);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(RXCLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = X"5" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = X"d" then
RX_PHY_STATE <= DATA_HIGH_LOW;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= X"5" or RXDV_D = '0' then
RX_PHY_STATE <= WAIT_START;
end if;
GPIO_LEDS(2 downto 0) <= b"000";
when DATA_HIGH_LOW =>
RX_WRITE_DATA(11 downto 8) <= RXD_D;
LOW_NIBBLE <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_HIGH_HIGH;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_HIGH_HIGH =>
RX_WRITE_DATA(15 downto 12) <= RXD_D;
ToFIFOdata <= RXD_D & LOW_NIBBLE;
if RXDV_D = '1' then
FIFO_WE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_LOW_LOW;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_LOW_LOW =>
RX_WRITE_DATA(3 downto 0) <= RXD_D;
LOW_NIBBLE <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_LOW_HIGH;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_LOW_HIGH =>
RX_WRITE_DATA(7 downto 4) <= RXD_D;
ToFIFOdata <= RXD_D & LOW_NIBBLE;
RX_WRITE_ENABLE <= '1';
if RXDV_D = '1' then
FIFO_WE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_HIGH_LOW;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
RX_PHY_STATE <= NOTIFY_NEW_PACKET; --AMER
GPIO_LEDS(2 downto 0) <= b"111";
elsif RX_PACKET_LENGTH < 64 then --AMER
RX_PHY_STATE <= NOTIFY_NEW_PACKET; --AMER
GPIO_LEDS(2 downto 0) <= b"001";
RX_PHY_STATE <= WAIT_START; --AMER
elsif RX_PACKET_LENGTH > 1518 then --AMER
RX_PHY_STATE <= NOTIFY_NEW_PACKET; --AMER
GPIO_LEDS(2 downto 0) <= b"011";
RX_PHY_STATE <= WAIT_START;--AMER
elsif RX_CRC /= X"C704dd7B" then
ToFIFOdata <= x"FF"; -- When a packed is discarded store FF in FIFO
FIFO_WE <= '1';
RX_PHY_STATE <= WAIT_START;--AMER
RX_PHY_STATE <= NOTIFY_NEW_PACKET; --AMER
GPIO_LEDS(2 downto 0) <= b"111"; --AMER
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
GPIO_LEDS(2 downto 0) <= b"100";
ToFIFOdata <= std_logic_vector(RX_PACKET_LENGTH(7 downto 0));
FIFO_WE <= '1';
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
GPIO_LEDS(2 downto 0) <= b"000";
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that it is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(RXCLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(RXCLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
-- A 1 Hz indicator on LED7 derived from the TXCLK
GPIO_LEDS(3) <= CLK1Hz;
-------
--This process displays some values on the 7-segment display
DISPLAY_FIFO: process
begin
wait until rising_edge(CLK);
-- Display the following when the 1 Hz clock is high
if CLK1Hz = '1' then
if FIFO_empty = '1' then
Tosseg_dat <= x"1111";
ssflags <= '1' & RST & FIFO_empty & S_TX_ACK;
else -- Display the following when the switch0 is on
if SW0 = '1' then
if BtnL = '1' then -- Display the following while pressing on the Left button
Tosseg_dat <= FIFOout;
ssflags <= RST & TX_WRITE & DONE & '1';
else
Tosseg_dat <= x"ABCD";
ssflags <= FIFO_empty & FIFO_full & FIFO_WE & FIFO_Ren;
end if;
else
if SW0 = '1' then
Tosseg_dat <= X"e" & '0' & std_logic_vector(TX_PACKET_LENGTH(10 downto 0));
ssflags <= RST & TX_WRITE & DONE & PhyCRS;
else
Tosseg_dat <= X"d" & '0' & std_logic_vector(RX_PACKET_LENGTH(10 downto 0));
ssflags <= RXER & RXDV & PhyCRS & COL;
end if;
end if;
end if;
else
-- Display the following when the 1 Hz clock is low
Tosseg_dat <= X"EEAA";
ssflags <= X"C"; -- for the 4 dots on the 7-segment display
end if;
end process DISPLAY_FIFO;
--- Takes care of 7-segment data
seven_seg_inst_1: seven_seg port map(
clk_in => CLK,
data_in => Tosseg_dat,
dots_in => ssflags,
segs_out => sseg_out,
anodes_out => anodes_out
);
--- To test received packet into a FIFO
-- ToREN <= not FIFO_empty;
--FIFO2Ko_RxTesting : RxTstFIFO2K
-- PORT MAP (
-- rst => RST,
-- wr_clk => RXCLK, -- Rx CLk
-- rd_clk => CLK1Hz,
-- din => ToFIFOdata, -- Received Bytes
-- wr_en => FIFO_WE,
-- rd_en => ToREN,
-- dout => FIFOout,
-- full => FIFO_full,
-- empty => FIFO_empty
-- );
--- Below is a 1 Hz generator .. was replaced by the external new OneHz25MHz.vhd
--process
--constant max_count : natural := 25000000;
--variable count : natural range 0 to max_count;
--begin
-- wait until rising_edge(TXCLK);
-- if RST = '0' then
-- count := 0;
-- CLK1Hz <= '0';
-- else
-- if count < max_count/2 then
-- CLK1Hz <='1';
-- count := count + 1;
-- elsif count < max_count then
-- CLK1Hz <='0';
-- count := count + 1;
-- else
-- count := 0;
-- CLK1Hz <='0';
-- end if;
-- end if;
--end process;
Inst_OneHz25MHz: OneHz25MHz PORT MAP(
Clk => TXCLK,
op => CLK1Hz
);
--
--process
--begin
--wait until rising_edge(CLK);
--FIFO_WR_EN <= FIFO_WR_EN and (not FIFO_full);
--end process;
--------------------------
end architecture RTL;
| mit | d8f698a0d82fe04a6c6e6e6380e73adc | 0.551044 | 3.183658 | false | false | false | false |
SteffenReith/J1Sc | vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/PLL.vhd | 2 | 6,178 | --------------------------------------------------------------------------------
--
-- Creation Date: Tue Jan 17 19:29:25 GMT+1 2017
-- Creator: Steffen Reith
-- Module Name: PLL - Structural
-- Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity PLL is
port (clkIn : in std_logic;
clkOut : out std_logic;
isLocked : out std_logic);
end PLL;
architecture Structural of PLL is
-- Control signals
signal locked : std_logic; -- The MMCM has achieved phase alignment
signal psDone_unused : std_logic; -- Dummy signal for phase shift done
signal clkinstopped_unused : std_logic; -- Input clock has stopped (not used)
signal clkfbstopped_unused : std_logic; -- Feedback clock has stopped (not used)
signal drdy_unused : std_logic; -- Reconfiguration ready signal
signal do_unused : std_logic_vector(15 downto 0); -- Reconfiguration data out
-- Internal clock signals
signal clkInI : std_logic; -- Internal buffered input clock
signal clkI1 : std_logic; -- Internal output clock 1
signal clkOutI1 : std_logic; -- Internal already buffered output clock 1
signal clkDI_unused : std_logic; -- Internal delayed output clock
-- Feedback clock signals
signal clkfbI : std_logic; -- Internal unbuffered feedback clock
signal clkfbIBuf : std_logic; -- Internal buffered feedback clock
-- Unused clock ports
signal clkfbb_unused : std_logic;
signal clk0b_unused : std_logic;
signal clk1b_unused : std_logic;
signal clk2_unused : std_logic;
signal clk2b_unused : std_logic;
signal clk3_unused : std_logic;
signal clk3b_unused : std_logic;
signal clk4_unused : std_logic;
signal clk5_unused : std_logic;
signal clk6_unused : std_logic;
begin
-- Instantiate a input clock buffer
clkInBuffer : IBUFG
port map (O => clkInI,
I => clkIn);
-- Instantiate a clock buffer for the internal feedback signal
feedbackBuffer : BUFG
port map (O => clkfbIBuf,
I => clkfbI);
-- Instantiate a clock manager
clkgen : MMCME2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- MMCM programming affecting jitter
CLKOUT4_CASCADE => false, -- don't divide output more than 128
COMPENSATION => "ZHOLD", -- Clk input compensation for feedback
STARTUP_WAIT => false, -- not supported yet (set to default)
DIVCLK_DIVIDE => 1, -- Division ratio for output clocks
CLKFBOUT_MULT_F => 10.000, -- set feedback base
CLKFBOUT_PHASE => 0.000, -- phase of feedback output
CLKFBOUT_USE_FINE_PS => false, -- Don't enable fine shift
--CLKOUT0_DIVIDE_F => 12.500, -- Scale clock to 80Mhz
CLKOUT0_DIVIDE_F => 10.000, -- Scale to 100Mhz
--CLKOUT0_DIVIDE_F => 8.333, -- Scale to 120Mhz
--CLKOUT0_DIVIDE_F => 8.000, -- Scale to 125Mhz
CLKOUT0_PHASE => 0.000, -- Phase of clock 0 (no shift)
CLKOUT0_DUTY_CYCLE => 0.500, -- Duty cycle of clock 0
CLKOUT0_USE_FINE_PS => false, -- No fine shift for clock 0
CLKOUT1_DIVIDE => 10, -- Scale clock 1 to 1.0
CLKOUT1_PHASE => 270.000, -- Phase of clock 1 (delayed)
CLKOUT1_DUTY_CYCLE => 0.500, -- Duty cycle of clock 1
CLKOUT1_USE_FINE_PS => false, -- No fine shift for clock 1
CLKIN1_PERIOD => 10.000, -- 10ns input clock period -> 100Mhz
REF_JITTER1 => 0.010) -- Set expected jitter to default
port map (
CLKFBOUT => clkfbI,
CLKFBOUTB => clkfbb_unused, -- Unused inverted feedback
-- Output clocks (delayed and non inverted)
CLKOUT0 => clkI1,
CLKOUT0B => clk0b_unused,
CLKOUT1 => clkDI_unused,
CLKOUT1B => clk1b_unused,
-- Unused clocks
CLKOUT2 => clk2_unused,
CLKOUT2B => clk2b_unused,
CLKOUT3 => clk3_unused,
CLKOUT3B => clk3b_unused,
CLKOUT4 => clk4_unused,
CLKOUT5 => clk5_unused,
CLKOUT6 => clk6_unused,
-- Input clock control
CLKFBIN => clkfbIBuf, -- Buffered feedback signal
CLKIN1 => clkInI, -- Input clock
CLKIN2 => '0', -- Second input clock is not used
CLKINSEL => '1', -- Select primary input clock
-- Disable dynamic reconfiguration
DADDR => (others => '0'), -- set all address bits to 0
DCLK => '0', -- No clock for the reconfig port
DEN => '0', -- Disable to reconfiguration port
DI => (others => '0'), -- set reconfiguration data to 0
DO => do_unused, -- Ignore MMCM reconfig data output
DRDY => drdy_unused, -- Ignore the ready signal
DWE => '0', -- Disable the write enable
-- Don't implement dynamic phase shift
PSCLK => '0', -- No phase shift clock
PSEN => '0', -- Disable phase shift
PSINCDEC => '0', -- No inc / dec of phase shift
PSDONE => psDone_unused, -- Dummy signal for phase shift done
-- Other control and status signals
LOCKED => locked, -- MMCE clock is stable
CLKINSTOPPED => clkinstopped_unused, -- Input clock has stopped (not used)
CLKFBSTOPPED => clkfbstopped_unused, -- Feedback clock has stopped (not used)
PWRDWN => '0', -- Don't power down MMCE
RST => '0'); -- No reset after startup
-- Scaled clock
clk1Buf : BUFGCE
port map (O => clkOutI1,
CE => locked,
I => clkI1);
clkOut <= clkOutI1;
-- Provide the locked signal to the outside world
isLocked <= locked;
end architecture;
| bsd-3-clause | c89feba72a1f1e1cda551a2fb8e85d2f | 0.562803 | 4.149093 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/proasic3/clkgen_proasic3.vhd | 2 | 6,738 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_proasic3.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Clock generators for Proasic3
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library proasic3;
use proasic3.PLL;
use proasic3.PLLINT;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Proasic3 clock generator --------------------------------------
------------------------------------------------------------------
entity clkgen_proasic3 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1;
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000); -- clock frequency in KHz
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture struct of clkgen_proasic3 is
constant VERSION : integer := 0;
component PLL
generic (VCOFREQUENCY:real := 0.0);
port(CLKA, EXTFB, POWERDOWN : in std_logic := 'U'; GLA,
LOCK, GLB, YB, GLC, YC : out std_logic; OADIV0, OADIV1,
OADIV2, OADIV3, OADIV4, OAMUX0, OAMUX1, OAMUX2, DLYGLA0,
DLYGLA1, DLYGLA2, DLYGLA3, DLYGLA4, OBDIV0, OBDIV1,
OBDIV2, OBDIV3, OBDIV4, OBMUX0, OBMUX1, OBMUX2, DLYYB0,
DLYYB1, DLYYB2, DLYYB3, DLYYB4, DLYGLB0, DLYGLB1, DLYGLB2,
DLYGLB3, DLYGLB4, OCDIV0, OCDIV1, OCDIV2, OCDIV3, OCDIV4,
OCMUX0, OCMUX1, OCMUX2, DLYYC0, DLYYC1, DLYYC2, DLYYC3,
DLYYC4, DLYGLC0, DLYGLC1, DLYGLC2, DLYGLC3, DLYGLC4,
FINDIV0, FINDIV1, FINDIV2, FINDIV3, FINDIV4, FINDIV5,
FINDIV6, FBDIV0, FBDIV1, FBDIV2, FBDIV3, FBDIV4, FBDIV5,
FBDIV6, FBDLY0, FBDLY1, FBDLY2, FBDLY3, FBDLY4, FBSEL0,
FBSEL1, XDLYSEL, VCOSEL0, VCOSEL1, VCOSEL2 : in std_logic :=
'U') ;
end component;
component PLLINT port( A : in std_logic; Y :out std_logic); end component;
signal VCC_1_net, GND_1_net, clkint : std_logic ;
signal M, N : std_logic_vector(6 downto 0) ;
signal O : std_logic_vector(4 downto 0) ;
signal vcosel : std_logic_vector(2 downto 0) ;
constant vcomhz : integer := (((freq * clk_mul)/clk_div)/1000);
constant glamhz : integer := vcomhz / clk_odiv;
constant vcofreq : real := real(vcomhz);
begin
VCC_1_net <= '1'; GND_1_net <= '0';
-- GLA = M / (N * U)
M <= conv_std_logic_vector((clk_mul)-1, 7);
N <= conv_std_logic_vector(clk_div-1, 7);
O <= conv_std_logic_vector(clk_odiv-1, 5);
vcosel <= "000" when vcomhz < 44 else
"010" when vcomhz < 88 else
"100" when vcomhz < 175 else "110";
c0: if (pcisysclk = 0) or (pcien = 0) generate
pllint0 : pllint port map (a => clkin, y => clkint);
end generate;
c1: if (pcien /= 0) generate
d0: if pcisysclk = 1 generate
pllint0 : pllint port map (a => pciclkin, y => clkint);
end generate d0;
pciclk <= pciclkin;
end generate;
c3 : if pcien = 0 generate
pciclk <= '0';
end generate;
cgo.pcilock <= '1';
Core : PLL
generic map(VCOFREQUENCY => vcofreq)
port map(CLKA => clkint, EXTFB => GND_1_net, POWERDOWN =>
VCC_1_net, GLA => clk, LOCK => cgo.clklock, GLB => OPEN , YB =>
OPEN , GLC => OPEN , YC => OPEN ,
OADIV0 => O(0),
OADIV1 => O(1),
OADIV2 => O(2),
OADIV3 => O(3),
OADIV4 => O(4),
OAMUX0 => GND_1_net,
OAMUX1 => GND_1_net,
OAMUX2 => VCC_1_net,
DLYGLA0 => GND_1_net,
DLYGLA1 => GND_1_net,
DLYGLA2 => GND_1_net,
DLYGLA3 => GND_1_net,
DLYGLA4 => GND_1_net,
OBDIV0 => GND_1_net,
OBDIV1 => GND_1_net,
OBDIV2 => GND_1_net,
OBDIV3 => GND_1_net,
OBDIV4 => GND_1_net,
OBMUX0 => GND_1_net,
OBMUX1 => GND_1_net,
OBMUX2 => GND_1_net,
DLYYB0 => GND_1_net,
DLYYB1 => GND_1_net,
DLYYB2 => GND_1_net,
DLYYB3 => GND_1_net,
DLYYB4 => GND_1_net,
DLYGLB0 => GND_1_net,
DLYGLB1 => GND_1_net,
DLYGLB2 => GND_1_net,
DLYGLB3 => GND_1_net,
DLYGLB4 => GND_1_net,
OCDIV0 => GND_1_net,
OCDIV1 => GND_1_net,
OCDIV2 => GND_1_net,
OCDIV3 => GND_1_net,
OCDIV4 => GND_1_net,
OCMUX0 => GND_1_net,
OCMUX1 => GND_1_net,
OCMUX2 => GND_1_net,
DLYYC0 => GND_1_net,
DLYYC1 => GND_1_net,
DLYYC2 => GND_1_net,
DLYYC3 => GND_1_net,
DLYYC4 => GND_1_net,
DLYGLC0 => GND_1_net,
DLYGLC1 => GND_1_net,
DLYGLC2 => GND_1_net,
DLYGLC3 => GND_1_net,
DLYGLC4 => GND_1_net,
FINDIV0 => N(0),
FINDIV1 => N(1),
FINDIV2 => N(2),
FINDIV3 => N(3),
FINDIV4 => N(4),
FINDIV5 => N(5),
FINDIV6 => N(6),
FBDIV0 => M(0),
FBDIV1 => M(1),
FBDIV2 => M(2),
FBDIV3 => M(3),
FBDIV4 => M(4),
FBDIV5 => M(5),
FBDIV6 => M(6),
FBDLY0 => GND_1_net,
FBDLY1 => GND_1_net,
FBDLY2 => GND_1_net,
FBDLY3 => GND_1_net,
FBDLY4 => GND_1_net,
FBSEL0 => VCC_1_net,
FBSEL1 => GND_1_net,
XDLYSEL => GND_1_net,
VCOSEL0 => vcosel(0),
VCOSEL1 => vcosel(1),
VCOSEL2 => vcosel(2));
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_proasic3" & ": proasic3 clock generator, input clock " & tost(freq/1000) & " MHz",
"clkgen_proasic3" & ": output clock " & tost(glamhz) & " MHz, mul/div/odiv " & tost(clk_mul)
& "/" & tost(clk_div) & "/" & tost(clk_odiv)
& ", VCO " & tost(vcomhz) & " MHz");
-- pragma translate_on
end ;
| mit | d31a5233d7a8b2ab1aeb9e574648a3d6 | 0.561146 | 3.036503 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_mul_opt.vhd | 1 | 4,213 | ---------------------------------------------------------------------
-- Optimized multiplier
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- This multiplier is designed for technologies that don't provide
-- fast 16x16 multipliers. One multiplication takes 6 cycles.
--
-- The multiplication algorithm is based on carry-save accumulation
-- of partial products.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_mul_opt is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
op1_i: in std_logic_vector(31 downto 0);
op2_i: in std_logic_vector(31 downto 0);
ce_o: out std_logic;
result_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_mul_opt is
function csa_sum(a: unsigned; b: unsigned; c: unsigned; n: integer) return unsigned is
variable r: unsigned(n-1 downto 0);
begin
for i in r'range loop
r(i):=a(i) xor b(i) xor c(i);
end loop;
return r;
end function;
function csa_carry(a: unsigned; b: unsigned; c: unsigned; n: integer) return unsigned is
variable r: unsigned(n-1 downto 0);
begin
for i in r'range loop
r(i):=(a(i) and b(i)) or (a(i) and c(i)) or (b(i) and c(i));
end loop;
return r&"0";
end function;
signal reg1: unsigned(op1_i'range);
signal reg2: unsigned(op2_i'range);
type pp_type is array (7 downto 0) of unsigned(31 downto 0);
signal pp: pp_type;
type pp_sum_type is array (7 downto 0) of unsigned(31 downto 0);
signal pp_sum: pp_sum_type;
type pp_carry_type is array (7 downto 0) of unsigned(32 downto 0);
signal pp_carry: pp_carry_type;
signal acc_sum: unsigned(31 downto 0);
signal acc_carry: unsigned(31 downto 0);
signal cnt: integer range 0 to 4:=0;
signal result: std_logic_vector(result_o'range);
signal ceo: std_logic:='0';
begin
-- Calculate 8 partial products in parallel
pp_gen: for i in pp'range generate
pp(i)<=shift_left(reg1,i) when reg2(i)='1' else (others=>'0');
end generate;
-- Add partial products to the accumulator using carry-save adder tree
pp_sum(0)<=csa_sum(pp(0),pp(1),pp(2),32);
pp_carry(0)<=csa_carry(pp(0),pp(1),pp(2),32);
pp_sum(1)<=csa_sum(pp(3),pp(4),pp(5),32);
pp_carry(1)<=csa_carry(pp(3),pp(4),pp(5),32);
pp_sum(2)<=csa_sum(pp(6),pp(7),acc_sum,32);
pp_carry(2)<=csa_carry(pp(6),pp(7),acc_sum,32);
pp_sum(3)<=csa_sum(pp_sum(0),pp_carry(0),pp_sum(1),32);
pp_carry(3)<=csa_carry(pp_sum(0),pp_carry(0),pp_sum(1),32);
pp_sum(4)<=csa_sum(pp_carry(1),pp_sum(2),pp_carry(2),32);
pp_carry(4)<=csa_carry(pp_carry(1),pp_sum(2),pp_carry(2),32);
pp_sum(5)<=csa_sum(pp_sum(3),pp_carry(3),pp_sum(4),32);
pp_carry(5)<=csa_carry(pp_sum(3),pp_carry(3),pp_sum(4),32);
pp_sum(6)<=csa_sum(pp_sum(5),pp_carry(5),pp_carry(4),32);
pp_carry(6)<=csa_carry(pp_sum(5),pp_carry(5),pp_carry(4),32);
pp_sum(7)<=csa_sum(pp_sum(6),pp_carry(6),acc_carry,32);
pp_carry(7)<=csa_carry(pp_sum(6),pp_carry(6),acc_carry,32);
-- Multiplier state machine
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
ceo<='0';
cnt<=0;
reg1<=(others=>'-');
reg2<=(others=>'-');
acc_sum<=(others=>'-');
acc_carry<=(others=>'-');
else
if cnt=1 then
ceo<='1';
else
ceo<='0';
end if;
if ce_i='1' then
cnt<=4;
reg1<=unsigned(op1_i);
reg2<=unsigned(op2_i);
acc_sum<=(others=>'0');
acc_carry<=(others=>'0');
else
acc_sum<=pp_sum(7);
acc_carry<=pp_carry(7)(acc_carry'range);
reg1<=reg1(reg1'high-8 downto 0)&X"00";
reg2<=X"00"®2(reg2'high downto 8);
if cnt>0 then
cnt<=cnt-1;
end if;
end if;
end if;
end if;
end process;
result<=std_logic_vector(acc_sum+acc_carry);
result_o<=result;
ce_o<=ceo;
-- A simulation-time multiplication check
-- synthesis translate_off
process (clk_i) is
variable p: unsigned(op1_i'length+op2_i'length-1 downto 0);
begin
if rising_edge(clk_i) then
if ce_i='1' then
p:=unsigned(op1_i)*unsigned(op2_i);
elsif ceo='1' then
assert result=std_logic_vector(p(result'range))
report "Incorrect multiplication result"
severity failure;
end if;
end if;
end process;
-- synthesis translate_on
end architecture;
| mit | 1a736c4b1e380ecd20c2ed079d5b74e4 | 0.634227 | 2.586249 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/iu3Version/iu3.vhd | 1 | 112,473 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
signal dataToCache : std_logic_vector(31 downto 0);
signal addressToCache : std_logic_vector(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif false and false and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if true then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if false then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not true) and (r.w.s.cwp = "000") then v.w.s.cwp := "111";
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
end if;
if true then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if true then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(7 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.w.s.ef := '0'; -- needed for AX
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := "000";
v.w.s.icc := "0000";
end if;
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := "00000000"; end if;
if true then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to 2-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if false and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(0 downto 0);
end if;
if(r.m.result = catchAddress)then
dci.maddress <= targetAddress;
dci.msu <= '1';
dci.esu <= '1';
else
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
end if;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if 0 = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000",
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if 2 > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000"; de_raddr2 := "0000000000";
if true then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if true then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2); de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := "000";
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000"; v.f.branch := '0';
if false then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to 2-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(0 downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if true then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if false then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if true then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if true then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then ir <= irin; end if;
end if;
end process;
dummy <= '1';
mem_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
addressToCache <= dci.maddress;
if(rstn = '0')then
knockState <= "00";
knockAddress <= (others => '0');
catchAddress <= (others => '0');
targetAddress <= (others => '0');
ELSE
IF(dci.write = '1')then
IF(dataToCache = X"AAAA_5555")THEN
knockState <= "01";
knockAddress <= addressToCache;
ELSIF(knockState = "01" and addressToCache = knockAddress and dataToCache = X"5555_AAAA")THEN
knockState <= "10";
ELSIF(knockState = "10" and addressToCache = knockAddress and dataToCache = X"CA5C_CA5C")THEN
knockState <= "11";
ELSIF(knockState = "11" and addressToCache = knockAddress)THEN
targetAddress <= dataToCache;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
end if;
end process;
end;
| mit | 64f5382ab4576fe8b459af7392a37675 | 0.518711 | 3.132516 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/greth/greth_gbit.vhd | 2 | 9,924 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gbit
-- File: greth_gbit.vhd
-- Author: Marko Isomaki
-- Description: Gigabit Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
use gaisler.misc.all;
library eth;
use eth.ethcomp.all;
entity greth_gbit is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth_gbit is
--host constants
constant fifosize : integer := 512;
constant fabits : integer := log2(fifosize);
constant fsize : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(fifosize, fabits+1);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, 0),
others => zero32);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufsize : integer := ebuf(log2(edclbufsz));
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(8 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(8 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(8 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(8 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
begin
gtxc0: greth_gbitc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => ahbmi.hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => ahbmo.hwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
gtx_clk => ethi.gtx_clk,
tx_clk => ethi.tx_clk,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd,
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
--ethernet output signals
reset => etho.reset,
txd => etho.txd,
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => etho.mdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen);
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclram : if (edcl = 1) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100/1000 Mbit Ethernet MAC rev " &
tost(REVISION) & tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz*edcl) & " kbyte " & tost(fifosize) & " txfifo, " &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| mit | e172adfdf92b6961549ee6f1bee0e0b9 | 0.52106 | 4.203304 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled2/Kernel/DiffusionLayer.vhd | 1 | 1,696 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DiffusionLayer is
generic( SHIFT1 : integer range 0 to 63;
SHIFT2 : integer range 0 to 63);
port( Input : in std_logic_vector(63 downto 0);
Output : out std_logic_vector(63 downto 0));
end entity DiffusionLayer;
architecture structural of DiffusionLayer is
begin
DiffLayer: process(Input) is
variable Temp0,Temp1 : std_logic_vector(63 downto 0);
begin
Temp0(63 downto 64-SHIFT1) := Input(SHIFT1-1 downto 0);
Temp0(63-SHIFT1 downto 0) := Input(63 downto SHIFT1);
Temp1(63 downto 64-SHIFT2) := Input(SHIFT2-1 downto 0);
Temp1(63-SHIFT2 downto 0) := Input(63 downto SHIFT2);
Output <= Temp0 xor Temp1 xor Input;
end process DiffLayer;
end architecture structural;
| gpl-3.0 | cdf68d3499451f0c85af0f9cf975e465 | 0.617925 | 3.743929 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu33AttacksDCE2.vhd | 1 | 118,538 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
signal dataToCache : std_logic_vector(31 downto 0);
signal triggerCPFault : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
signal addressToCache : std_logic_vector(31 downto 0);
SIGNAL hackStateM1 : std_logic;
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(9 downto 0);
signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right);
signal or_reduce_1 : std_logic;
signal dfp_delay_start : integer range 0 to 15;
signal handlerTrap : std_ulogic;
-- Signals that serve as shadow signals for variables used in the pairs
signal EX_EDATA2_shadow : WORD;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_RESULT_shadow : WORD;
signal V_A_SU_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
-- Intermediate value holding signal declarations
signal R_M_RESULT_intermed_3 : std_logic_vector(31 downto 0);
signal TARGETADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_M_RESULT_intermed_4 : std_logic_vector(31 downto 0);
signal R_M_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_RESULT_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_RESULT_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_M_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_M_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal DCI_EDATA_intermed_5 : STD_LOGIC_VECTOR(31 downto 0);
signal DCI_EDATA_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal ADDRESSTOCACHE_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_A_SU_intermed_2 : STD_ULOGIC;
signal DCI_EDATA_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal TARGETADDRESS_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal TARGETADDRESS_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_SU_shadow_intermed_2 : STD_ULOGIC;
signal DATATOCACHE_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_E_SU_intermed_1 : STD_ULOGIC;
signal DCI_MADDRESS_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal V_M_RESULT_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_3 : STD_ULOGIC;
signal DCI_EDATA_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal EX_EDATA2_shadow_intermed_5 : std_logic_vector(31 downto 0);
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal KNOCKADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal EX_EDATA2_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal DCI_MADDRESS_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal DATATOCACHE_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_E_SU_intermed_2 : STD_ULOGIC;
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal RIN_M_RESULT_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal DATATOCACHE_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal DCI_EDATA_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_SU_intermed_3 : STD_ULOGIC;
signal ADDRESSTOCACHE_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_M_RESULT_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal R_M_RESULT_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal DCI_MADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal V_M_SU_shadow_intermed_1 : STD_ULOGIC;
signal DATATOCACHE_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp, handlerTrap)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap or handlerTrap;
v.x.nerror := rp.error;
if(handlerTrap = '1')then
xc_vectt := "00" & TT_WATCH;
elsif(triggerCPFault = '1')then
xc_vectt := "00" & TT_CPDIS;
xc_trap := '1';
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
if(r.m.result = catchAddress)then
dci.maddress <= targetAddress;
dci.msu <= '1';
dci.esu <= '1';
else
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
end if;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
EX_EDATA2_shadow <= EX_EDATA2;
V_E_SU_shadow <= V.E.SU;
V_M_RESULT_shadow <= V.M.RESULT;
V_A_SU_shadow <= V.A.SU;
V_M_SU_shadow <= V.M.SU;
end process;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
ADDRESSTOCACHE_intermed_1 <= ADDRESSTOCACHE;
ADDRESSTOCACHE_intermed_2 <= ADDRESSTOCACHE_intermed_1;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
EX_EDATA2_shadow_intermed_3 <= EX_EDATA2_shadow_intermed_2;
EX_EDATA2_shadow_intermed_4 <= EX_EDATA2_shadow_intermed_3;
EX_EDATA2_shadow_intermed_5 <= EX_EDATA2_shadow_intermed_4;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
V_M_RESULT_shadow_intermed_2 <= V_M_RESULT_shadow_intermed_1;
V_M_RESULT_shadow_intermed_3 <= V_M_RESULT_shadow_intermed_2;
V_M_RESULT_shadow_intermed_4 <= V_M_RESULT_shadow_intermed_3;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DATATOCACHE_intermed_2 <= DATATOCACHE_intermed_1;
DATATOCACHE_intermed_3 <= DATATOCACHE_intermed_2;
DATATOCACHE_intermed_4 <= DATATOCACHE_intermed_3;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
DCI_EDATA_intermed_3 <= DCI_EDATA_intermed_2;
DCI_EDATA_intermed_4 <= DCI_EDATA_intermed_3;
DCI_EDATA_intermed_5 <= DCI_EDATA_intermed_4;
DCI_MADDRESS_intermed_1 <= DCI.MADDRESS;
DCI_MADDRESS_intermed_2 <= DCI_MADDRESS_intermed_1;
DCI_MADDRESS_intermed_3 <= DCI_MADDRESS_intermed_2;
KNOCKADDRESS_intermed_1 <= KNOCKADDRESS;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
RIN_M_RESULT_intermed_2 <= RIN_M_RESULT_intermed_1;
RIN_M_RESULT_intermed_3 <= RIN_M_RESULT_intermed_2;
RIN_M_RESULT_intermed_4 <= RIN_M_RESULT_intermed_3;
R_M_RESULT_intermed_1 <= R.M.RESULT;
R_M_RESULT_intermed_2 <= R_M_RESULT_intermed_1;
R_M_RESULT_intermed_3 <= R_M_RESULT_intermed_2;
TARGETADDRESS_intermed_1 <= TARGETADDRESS;
TARGETADDRESS_intermed_2 <= TARGETADDRESS_intermed_1;
TARGETADDRESS_intermed_3 <= TARGETADDRESS_intermed_2;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
RIN_E_SU_intermed_1 <= RIN.E.SU;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
V_A_SU_shadow_intermed_3 <= V_A_SU_shadow_intermed_2;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_E_SU_shadow_intermed_2 <= V_E_SU_shadow_intermed_1;
V_M_SU_shadow_intermed_1 <= V_M_SU_shadow;
R_A_SU_intermed_1 <= R.A.SU;
R_A_SU_intermed_2 <= R_A_SU_intermed_1;
R_E_SU_intermed_1 <= R.E.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
RIN_A_SU_intermed_3 <= RIN_A_SU_intermed_2;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_SU_intermed_2 <= RIN_E_SU_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
ADDRESSTOCACHE_intermed_1 <= ADDRESSTOCACHE;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
EX_EDATA2_shadow_intermed_3 <= EX_EDATA2_shadow_intermed_2;
EX_EDATA2_shadow_intermed_4 <= EX_EDATA2_shadow_intermed_3;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
V_M_RESULT_shadow_intermed_2 <= V_M_RESULT_shadow_intermed_1;
V_M_RESULT_shadow_intermed_3 <= V_M_RESULT_shadow_intermed_2;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DATATOCACHE_intermed_2 <= DATATOCACHE_intermed_1;
DATATOCACHE_intermed_3 <= DATATOCACHE_intermed_2;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
DCI_EDATA_intermed_3 <= DCI_EDATA_intermed_2;
DCI_EDATA_intermed_4 <= DCI_EDATA_intermed_3;
DCI_MADDRESS_intermed_1 <= DCI.MADDRESS;
DCI_MADDRESS_intermed_2 <= DCI_MADDRESS_intermed_1;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
RIN_M_RESULT_intermed_2 <= RIN_M_RESULT_intermed_1;
RIN_M_RESULT_intermed_3 <= RIN_M_RESULT_intermed_2;
R_M_RESULT_intermed_1 <= R.M.RESULT;
R_M_RESULT_intermed_2 <= R_M_RESULT_intermed_1;
TARGETADDRESS_intermed_1 <= TARGETADDRESS;
TARGETADDRESS_intermed_2 <= TARGETADDRESS_intermed_1;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (TRIGGERCPFAULT /= '0') else '0';
dfp_trap_vector(1) <= '1' when (HACKSTATEM1 /= '0') else '0';
dfp_trap_vector(2) <= '1' when (CATCHADDRESS /= X"00000000") else '0';
dfp_trap_vector(3) <= '1' when (CATCHADDRESS /= KNOCKADDRESS_intermed_1) else '0';
dfp_trap_vector(4) <= '1' when (CATCHADDRESS /= TARGETADDRESS_intermed_3) else '0';
dfp_trap_vector(5) <= '1' when (DCI.MADDRESS /= R.M.RESULT) else '0';
dfp_trap_vector(6) <= '1' when (KNOCKADDRESS /= X"00000000") else '0';
dfp_trap_vector(7) <= '1' when (KNOCKADDRESS /= TARGETADDRESS_intermed_2) else '0';
dfp_trap_vector(8) <= '1' when (KNOCKSTATE /= "00") else '0';
dfp_trap_vector(9) <= '1' when (TARGETADDRESS /= X"00000000") else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_5 : std_logic_vector(4 downto 0);
variable or_reduce_3 : std_logic_vector(2 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_5 := dfp_trap_vector(9 downto 5) OR dfp_trap_vector(4 downto 0);
or_reduce_3 := or_reduce_5(4 downto 2) OR ("0" & or_reduce_5(1 downto 0));
or_reduce_2 := or_reduce_3(2 downto 1) OR ("0" & or_reduce_3(0 downto 0));
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0';
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
hackStateM1 <= '0';
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
else
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackStateM1 <= '1';
END IF;
IF ( hackStateM1 = '1' and r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" ) THEN
r.w.s.s <= '1';
END IF;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
shadow_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
triggerCPFault <= '0';
IF(dci.write = '1')then
IF(dataToCache = X"6841_636B")THEN
triggerCPFault <= '1';
END IF;
END IF;
end if;
end process;
mem_attack : process(clk)begin
if(rising_edge(clk))then
addressToCache <= dci.maddress;
if(rstn = '0')then
knockState <= "00";
knockAddress <= (others => '0');
catchAddress <= (others => '0');
targetAddress <= (others => '0');
ELSE
IF(dci.write = '1')then
IF(dataToCache = X"AAAA_5555")THEN
knockState <= "01";
knockAddress <= addressToCache;
ELSIF(knockState = "01" and addressToCache = knockAddress and dataToCache = X"5555_AAAA")THEN
knockState <= "10";
ELSIF(knockState = "10" and addressToCache = knockAddress and dataToCache = X"CA5C_CA5C")THEN
knockState <= "11";
ELSIF(knockState = "11" and addressToCache = knockAddress)THEN
targetAddress <= dataToCache;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
end if;
end process;
end;
| mit | ba9bd9043f357c12314aad1efb7aa773 | 0.546399 | 3.010871 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32c_top.vhd | 1 | 3,182 | ---------------------------------------------------------------------
-- LXP32C CPU top-level module (C-series, with instruction cache)
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- This version uses Wishbone B3 interface for the instruction bus
-- (IBUS). It is designed for high-latency program memory, such as
-- external SDRAM chips.
--
-- Parameters:
-- DBUS_RMW: Use RMW cycle instead of SEL_O() signal
-- for byte-granular access to data bus
-- DIVIDER_EN: enable divider
-- IBUS_BURST_SIZE: size of the burst
-- IBUS_PREFETCH_SIZE: initiate read burst if number of words
-- left in the buffer is less than specified
-- MUL_ARCH: multiplier architecture ("dsp", "opt"
-- or "seq")
-- START_ADDR: address in program memory where execution
-- starts
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lxp32c_top is
generic(
DBUS_RMW: boolean:=false;
DIVIDER_EN: boolean:=true;
IBUS_BURST_SIZE: integer:=16;
IBUS_PREFETCH_SIZE: integer:=32;
MUL_ARCH: string:="dsp";
START_ADDR: std_logic_vector(31 downto 0):=(others=>'0')
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
ibus_cyc_o: out std_logic;
ibus_stb_o: out std_logic;
ibus_cti_o: out std_logic_vector(2 downto 0);
ibus_bte_o: out std_logic_vector(1 downto 0);
ibus_ack_i: in std_logic;
ibus_adr_o: out std_logic_vector(29 downto 0);
ibus_dat_i: in std_logic_vector(31 downto 0);
dbus_cyc_o: out std_logic;
dbus_stb_o: out std_logic;
dbus_we_o: out std_logic;
dbus_sel_o: out std_logic_vector(3 downto 0);
dbus_ack_i: in std_logic;
dbus_adr_o: out std_logic_vector(31 downto 2);
dbus_dat_o: out std_logic_vector(31 downto 0);
dbus_dat_i: in std_logic_vector(31 downto 0);
irq_i: in std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of lxp32c_top is
signal lli_re: std_logic;
signal lli_adr: std_logic_vector(29 downto 0);
signal lli_dat: std_logic_vector(31 downto 0);
signal lli_busy: std_logic;
begin
cpu_inst: entity work.lxp32_cpu(rtl)
generic map(
DBUS_RMW=>DBUS_RMW,
DIVIDER_EN=>DIVIDER_EN,
MUL_ARCH=>MUL_ARCH,
START_ADDR=>START_ADDR
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
lli_re_o=>lli_re,
lli_adr_o=>lli_adr,
lli_dat_i=>lli_dat,
lli_busy_i=>lli_busy,
dbus_cyc_o=>dbus_cyc_o,
dbus_stb_o=>dbus_stb_o,
dbus_we_o=>dbus_we_o,
dbus_sel_o=>dbus_sel_o,
dbus_ack_i=>dbus_ack_i,
dbus_adr_o=>dbus_adr_o,
dbus_dat_o=>dbus_dat_o,
dbus_dat_i=>dbus_dat_i,
irq_i=>irq_i
);
icache_inst: entity work.lxp32_icache(rtl)
generic map(
BURST_SIZE=>IBUS_BURST_SIZE,
PREFETCH_SIZE=>IBUS_PREFETCH_SIZE
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
lli_re_i=>lli_re,
lli_adr_i=>lli_adr,
lli_dat_o=>lli_dat,
lli_busy_o=>lli_busy,
wbm_cyc_o=>ibus_cyc_o,
wbm_stb_o=>ibus_stb_o,
wbm_cti_o=>ibus_cti_o,
wbm_bte_o=>ibus_bte_o,
wbm_ack_i=>ibus_ack_i,
wbm_adr_o=>ibus_adr_o,
wbm_dat_i=>ibus_dat_i
);
end architecture;
| mit | 2e164680ff2b09d4475dbd053ca0c0d3 | 0.604651 | 2.708085 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/amba/dma2ahb.vhd | 2 | 25,098 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB (Entity & architecture declarations)
--
-- File name : dma2ahb.vhd
--
-- Purpose : AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : The AMBA AHB interface has been reduced in function to support
-- only what is required. The following features are constrained:
-- Optionally generates HSIZE=BYTE, HWORD and WORD
-- Only generates HLOCK="0"
-- Only generates HPROT="0000"
-- Allways generates HBURST=HBURST_SINGLE, HBURST_INCR
-- Optionally generates HBURST_INCR4, HBURST_INCR8, HBURST_INCR16
--
-- Generates the following on reponses on DMA interface:
-- HRESP=HRESP_OKAY => DMAOut.Ready
-- HRESP=HRESP_ERROR => DMAOut.Fault
-- HRESP=HRESP_RETRY => DMAOut.Retry (normally not used)
-- HRESP=HRESP_SPLIT => DMAOut.Retry (normally not used)
--
-- Assumes pipelined data input (after OKAY asserted).
--
-- Only big-endianness is supported.
--
-- Supports Early Bus Termination with automatic restart.
-- Supports Retry/Split with automatic restart.
--
-- Library : gaisler
--
-- Authors : Mr Sandi Habinc
-- Gaisler Research AB
-- Forsta Langgatan 19
-- SE-413 27 Göteborg
-- Sweden
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.1 SH 1 Jul 2003 New version
-- 0.2 SH 21 Jul 2003 Combinatorial response introduced
-- 0.3 SH 25 Jan 2004 Support for interrupted bursts introduced
-- (early burst termination)
-- Optimised coding
-- Idle transfer initiated in 1st error phase
-- 1.3 SH 1 Oct 2004 Ported to GRLIB
-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
-- Support for record types
-- 1.5 SH 1 Sep 2005 New library gaisler
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.6 SH 1 Nov 2005 DMAOut.Grant asserted only while HREADY high
-- 1.8 SH 10 Nov 2005 Re-ported to GRLIB
-- 1.8.1 SH 12 Dec 2005 Ensured no HTRANS=seq occurs after idle
-- 1.9 SH 1 Jan 2006 Resolve retry/early burst termination
-- 1.9.2 SH 3 Jan 2006 DelDataPhase dealyed with HREADY signal
-- 1.9.3 SH 24 Feb 2006 Added syncrst generic
-- 1.9.4 MI 27 Mar 2007 Driving HSIZE with address
-- 1.9.5 SH 14 Dec 2007 Automatic 1kbyte boundary crossing (merged)
-- 1.9.6 JA 14 Dec 2007 Support for halfword and byte bursts
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.STDLIB.all;
use GRLIB.DMA2AHB_Package.all;
entity DMA2AHB is
generic(
hindex: in Integer := 0;
vendorid: in Integer := 0;
deviceid: in Integer := 0;
version: in Integer := 0;
syncrst: in Integer := 1;
boundary: in Integer := 1);
port(
-- AMBA AHB system signals
HCLK: in Std_ULogic; -- system clock
HRESETn: in Std_ULogic; -- asynchronous reset
-- Direct Memory Access Interface
DMAIn: in DMA_In_Type;
DMAOut: out DMA_OUt_Type;
-- AMBA AHB Master Interface
AHBIn: in AHB_Mst_In_Type;
AHBOut: out AHB_Mst_Out_Type);
end entity DMA2AHB;
--============================== Architecture ================================--
architecture RTL of DMA2AHB is
--=========================================================================--
-- Configuration GRLIB
-----------------------------------------------------------------------------
constant HConfig: AHB_Config_Type := (
0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
others => (others => '0'));
--=========================================================================--
-----------------------------------------------------------------------------
-- Local signals
-----------------------------------------------------------------------------
signal Address: Std_Logic_Vector(31 downto 0);
signal AddressSave: Std_Logic_Vector(31 downto 0);
signal ActivePhase: Std_ULogic; -- ongoing access
signal AddressPhase: Std_ULogic; -- address phase
signal DataPhase: Std_ULogic; -- data phase
signal ReDataPhase: Std_ULogic; -- restart first
signal ReAddrPhase: Std_ULogic; -- restart second
signal IdlePhase: Std_ULogic; -- idle phase
signal EarlyPhase: Std_ULogic; -- early termination
signal BoundaryPhase: Std_ULogic; -- boundary crossing
signal SingleAcc: Std_ULogic; -- single access
signal WriteAcc: Std_ULogic; -- write access
signal DelDataPhase: Std_ULogic; -- restart first
signal DelAddrPhase: Std_ULogic; -- restart second
signal AHBInHGRANTx: Std_ULogic; -- decoded grant
begin
--=========================================================================--
-- AMBA AHB master interface
-----------------------------------------------------------------------------
AHBOut.HIRQ <= (others => '0');
AHBOut.HCONFIG <= HConfig;
AHBOut.HINDEX <= hindex;
AHBInHGRANTx <= AHBIn.HGRANT(hindex);
--=========================================================================--
-----------------------------------------------------------------------------
-- AMBA AHB Master interface with fast issuing of accesses
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Fixed AMBA AHB signals
-----------------------------------------------------------------------------
AHBOut.HLOCK <= '0';
AHBOut.HPROT <= (others => '0');
-----------------------------------------------------------------------------
-- Combinatorial paths
-----------------------------------------------------------------------------
AHBOut.HADDR <= Address; -- internal to external
AHBOut.HWDATA <= DMAIn.Data; -- combinatorial path
DMAOut.OKAY <= '1' when AHBIn.HREADY='1' and
DataPhase ='1' and
AHBIN.HRESP=HRESP_OKAY else
'0';
DMAOut.Retry <= '1' when AHBIn.HREADY='0' and
DataPhase ='1' and
(AHBIN.HRESP=HRESP_RETRY or
AHBIN.HRESP=HRESP_SPLIT) else
'0';
DMAOut.Fault <= '1' when AHBIn.HREADY='0' and
DataPhase ='1' and
AHBIN.HRESP=HRESP_ERROR else
'0';
DMAOut.Grant <= '0' when DelDataPhase='1' or ReDataPhase='1' else
'1' when AHBIn.HREADY='1' and
AHBInHGRANTx='1' and
DMAIn.Request='1' else
'0';
AHBOut.HBUSREQ <= '0' when IdlePhase='1' else
'1' when DMAIn.Request='1' else
'1' when DMAIn.Burst='1' else
'1' when ReDataPhase='1' else
'1' when ReAddrPhase='1' else
'0';
-----------------------------------------------------------------------------
-- The AMBA AHB interfacing is done in this process
-----------------------------------------------------------------------------
AHBMaster: process(HCLK, HRESETn)
variable BoundaryCrossing: Std_ULogic;
variable AddressInc: Std_Logic_Vector(3 downto 0);
--------------------------------------------------------------------------
-- This procedure is used to define all reset values for the
-- asynchronous or synchronous reset statements in this process. This
-- is done to avoid source code duplication.
--------------------------------------------------------------------------
procedure Reset is
begin
ActivePhase <= '0';
EarlyPhase <= '0';
AddressPhase <= '0';
DataPhase <= '0';
ReDataPhase <= '0';
ReAddrPhase <= '0';
DelDataPhase <= '0';
DelAddrPhase <= '0';
BoundaryPhase <= '0';
IdlePhase <= '0';
EarlyPhase <= '0';
SingleAcc <= '0';
WriteAcc <= '0';
Address <= (others => '0');
AddressSave <= (others => '0');
DMAOut.Ready <= '0';
DMAOut.Data <= (others => '0');
AHBOut.HSIZE <= HSIZE_BYTE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HWRITE <= '0';
end Reset; ---------------------------------------------------------------
begin
if HRESETn='0' and syncrst=0 then -- asynchronous reset
Reset;
elsif Rising_Edge(HCLK) then
if DMAIn.Reset='1' or -- functional reset
(syncrst/=0 and HRESETn='0') then -- synchronous reset
Reset;
else -- no reset
--------------------------------------------------------------------
-- Temporary variables
--------------------------------------------------------------------
BoundaryCrossing := '0';
AddressInc := (others => '0');
--------------------------------------------------------------------
-- AMBA AHB interface - data phase handling
--------------------------------------------------------------------
-- indicate when no more activies are pending
if AddressPhase='0' and DataPhase='0' and
ReDataPhase='0' and ReAddrPhase='0' and
DMAIn.Burst='0' then
ActivePhase <= '0';
end if;
if AHBIn.HREADY='0' and DataPhase='1' then
-- error check
if AHBIN.HRESP=HRESP_ERROR then
DataPhase <= '0'; -- data phase aborted
end if;
-- split or retry check
if AHBIN.HRESP=HRESP_SPLIT or
AHBIN.HRESP=HRESP_RETRY then
ReDataPhase <= DataPhase; -- restart phases
ReAddrPhase <= AddressPhase or ReAddrPhase;
AddressPhase <= '0'; -- addr phase aborted
DataPhase <= '0'; -- data phase aborted
-- go back with address
if boundary=1 then
Address <= AddressSave;
else
Address(9 downto 0) <= AddressSave(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
end if;
end if;
if AHBIn.HREADY='1' and DataPhase='1' then
-- sample AHB input data at end of data phase
DMAOut.Data <= AHBIn.HRDATA;
DataPhase <= '0'; -- data phase ends
DMAOut.Ready <= '1';
else
-- remove acknowledgement after one cycle
DMAOut.Ready <= '0';
end if;
--------------------------------------------------------------------
-- AMBA AHB interface - address phase handling
--------------------------------------------------------------------
-- initialize data phase on AHB after previous address phase
if AddressPhase='1' and AHBIn.HREADY='1' then
DataPhase <= '1'; -- data phase start
end if;
-- address generation on AHB
if AHBIn.HREADY='1' then
if AddressPhase='1' then
-- burst continuation, sequential transfer
AddressInc(conv_integer(DMAIn.Size)) := '1';
if boundary=1 then -- automatic boundary
Address <= Address + AddressInc;
AddressSave <= Address;
if Address(9 downto 2)="11111111" then
BoundaryCrossing := '1';
BoundaryPhase <= '1';
end if;
else
Address(31 downto 10) <= DMAIn.Address(31 downto 10);
Address( 9 downto 0) <= Address(9 downto 0) + AddressInc;
AddressSave(9 downto 0) <= Address(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
elsif AHBInHGRANTx='1' and ActivePhase='0' and DMAIn.Request='1' then
-- start of burst, non-sequential transfer
-- start of single, non-sequential transfer
if boundary=1 then -- automatic boundary
Address <= DMAIn.Address;
AddressSave <= DMAIn.Address;
BoundaryCrossing := '0';
BoundaryPhase <= '0';
else
Address <= DMAIn.Address;
AddressSave(9 downto 0) <= DMAIn.Address(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
end if;
end if;
-- address generation on AHB
if AHBIn.HREADY='1' then
IdlePhase <= '0'; -- one clock cycle only
end if;
-- initialize address phase on AHB
if AHBIn.HREADY='1' then
-- granted the AHB bus
if AHBInHGRANTx='1' then
if ReDataPhase='1' then
ReDataPhase <= '0';
AddressPhase <= '1'; -- address phase start
EarlyPhase <= '0';
AHBOut.HTRANS <= HTRANS_NONSEQ;
if SingleAcc='1' then
AHBOut.HBURST <= HBURST_SINGLE;
else
AHBOut.HBURST <= HBURST_INCR;
end if;
AHBOut.HWRITE <= WriteAcc;
elsif ReAddrPhase='1' then
AddressPhase <= '1'; -- address phase start
ReAddrPhase <= '0';
if AddressPhase='1' then
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
-- new bursts, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
BoundaryPhase <= '0';
else
-- burst continuation, sequential transfer
AHBOut.HTRANS <= HTRANS_SEQ;
end if;
else
AHBOut.HTRANS <= HTRANS_NONSEQ;
end if;
EarlyPhase <= '0';
if SingleAcc='1' then
AHBOut.HBURST <= HBURST_SINGLE;
else
AHBOut.HBURST <= HBURST_INCR;
end if;
AHBOut.HWRITE <= WriteAcc;
elsif EarlyPhase='1' then
-- early terminated burst resumed
AddressPhase <= '1'; -- address phase start
EarlyPhase <= '0';
AHBOut.HTRANS <= HTRANS_NONSEQ;
AHBOut.HBURST <= HBURST_INCR;
AHBOut.HWRITE <= WriteAcc;
elsif DMAIn.Request='1' and DMAIn.Burst='1' then
AddressPhase <= '1'; -- address phase start
if ActivePhase='1' then
-- burst continuation, sequential transfer
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
-- new bursts, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
BoundaryPhase <= '0';
else
-- burst continuation, sequential transfer
AHBOut.HTRANS <= HTRANS_SEQ;
end if;
else
-- start of burst, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
if DMAIn.Beat ="00" then
AHBOut.HBURST <= HBURST_INCR;
elsif DMAIn.Beat ="01" then
AHBOut.HBURST <= HBURST_INCR4;
elsif DMAIn.Beat ="10" then
AHBOut.HBURST <= HBURST_INCR8;
else
AHBOut.HBURST <= HBURST_INCR16;
end if;
AHBOut.HWRITE <= DMAIn.Store;
ActivePhase <= '1';
SingleAcc <= '0';
WriteAcc <= DMAIn.Store;
end if;
elsif DMAIn.Request='0' and DMAIn.Burst='1' and ActivePhase='1' then
-- burst in wait state
AddressPhase <= '0'; -- no address phase
AHBOut.HTRANS <= HTRANS_BUSY;
elsif DMAIn.Request='1' and DMAIn.Burst='0' then
-- start of single, non-sequential transfer
AddressPhase <= '1'; -- address phase start
ActivePhase <= '1';
SingleAcc <= '1';
WriteAcc <= DMAIn.Store;
AHBOut.HTRANS <= HTRANS_NONSEQ;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= DMAIn.Store;
else
-- drive idle transfer as default master
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
-- not granted the AHB bus, but early burst termination
elsif (DMAIn.Request='1' or DMAIn.Burst='1') and ActivePhase='1'then
-- must restart a burst transfer since grant removed
AddressPhase <= '0'; -- no address phase
EarlyPhase <= '1';
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
-- not granted the AHB bus
else
-- drive idle transfer as default master
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
elsif AHBIn.HREADY='0' and DataPhase='1' then
if AHBIN.HRESP=HRESP_ERROR or
AHBIN.HRESP=HRESP_SPLIT or
AHBIN.HRESP=HRESP_RETRY then
-- drive idle transfer due to error, retry or split
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
IdlePhase <= '1';
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
end if;
end if;
if AHBIn.HREADY='1' then -- delay one phase
DelDataPhase <= ReDataPhase;
DelAddrPhase <= ReAddrPhase;
end if;
-- temporary variables cleared
BoundaryCrossing := '0';
AddressInc := (others => '0');
else
null;
end if;
end process AHBMaster;
end architecture RTL; --======================================================--
| mit | 010a59ee2677df0821c5a799b67f687b | 0.410869 | 5.701499 | false | false | false | false |
franz/pocl | examples/accel/rtl/platform/tta-axislave.vhdl | 2 | 18,196 | -- Copyright (c) 2016 Nokia Research Center
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : AXI lite interface to TTA debugger and stream IO
-- Project :
-------------------------------------------------------------------------------
-- File : tta-axislave.vhdl
-- Author : Tommi Zetterman <[email protected]>
-- Company : Nokia Research Center
-- Created : 2014-06-23
-- Last update: 2017-06-01
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Nokia Research Center
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-23 1.0 zetterma Created (as axi4dbgslave-rtl.vhdl
-- 2015-01-27 1.1 viitanet Modified into a processor wrapper
-- 2016-11-18 1.1 tervoa Added full AXI4 interface
-- 2017-03-27 1.2 tervoa Fixed burst transfer logic
-- 2017-04-25 1.3 tervoa Combined entiy and architecture files
-- 2017-06-01 1.4 tervoa Converted to memory buses with handshaking
-- 2017-06-01 1.5 tervoa Fix address increment logic
-- 2018-07-30 1.6 tervoa Support for optional sync reset
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tta_axislave is
generic (
-- Must be at least 2 + max(max(IMEMADDRWIDTH+IMEMWORDSEL,db_addr_width),
-- fu_LSU_addrw-2)
-- where IMEMWORDSEL = bit_width((IMEMDATAWIDTH+31)/32)
axi_addrw_g : integer := 17;
axi_dataw_g : integer := 32;
axi_idw_g : integer := 12;
sync_reset_g : integer := 0
);
port (
clk : in std_logic;
rstx : in std_logic;
-- Accelerator interface
avalid_out : out std_logic;
aready_in : in std_logic;
aaddr_out : out std_logic_vector(axi_addrw_g-2-1 downto 0);
awren_out : out std_logic;
astrb_out : out std_logic_vector(axi_dataw_g/8-1 downto 0);
adata_out : out std_logic_vector(axi_dataw_g-1 downto 0);
rvalid_in : in std_logic;
rready_out : out std_logic;
rdata_in : in std_logic_vector(axi_dataw_g-1 downto 0);
-- AXI slave port
s_axi_awid : in STD_LOGIC_VECTOR (axi_idw_g-1 downto 0);
s_axi_awaddr : in STD_LOGIC_VECTOR (axi_addrw_g-1 downto 0);
s_axi_awlen : in STD_LOGIC_VECTOR (8-1 downto 0);
s_axi_awsize : in STD_LOGIC_VECTOR (3-1 downto 0);
s_axi_awburst : in STD_LOGIC_VECTOR (2-1 downto 0);
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR (31 downto 0);
s_axi_wstrb : in STD_LOGIC_VECTOR (3 downto 0);
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR (axi_idw_g-1 downto 0);
s_axi_bresp : out STD_LOGIC_VECTOR (2-1 downto 0);
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR (axi_idw_g-1 downto 0);
s_axi_araddr : in STD_LOGIC_VECTOR (axi_addrw_g-1 downto 0);
s_axi_arlen : in STD_LOGIC_VECTOR (8-1 downto 0);
s_axi_arsize : in STD_LOGIC_VECTOR (3-1 downto 0);
s_axi_arburst : in STD_LOGIC_VECTOR (2-1 downto 0);
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR (axi_idw_g-1 downto 0);
s_axi_rdata : out STD_LOGIC_VECTOR (31 downto 0);
s_axi_rresp : out STD_LOGIC_VECTOR (2-1 downto 0);
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
end entity tta_axislave;
architecture rtl of tta_axislave is
constant sync_reset_c : boolean := sync_reset_g /= 0;
constant FIXED_BURST : std_logic_vector(1 downto 0) := "00";
constant INCR_BURST : std_logic_vector(1 downto 0) := "01";
constant WRAP_BURST : std_logic_vector(1 downto 0) := "10";
constant AXI_OKAY : std_logic_vector(1 downto 0) := "00";
constant AXI_SLVERR : std_logic_vector(1 downto 0) := "10";
type u8_array is array (natural range <>) of unsigned(7 downto 0);
constant burst_size_lut_c : u8_array(0 to 7) :=
("00000001", "00000010","00000100","00001000",
"00010000", "00100000","01000000","10000000");
type state_t is (S_READY, S_WRITE_DATA, S_FINISH_WRITE,
S_READ_DATA, S_FINISH_READ);
signal state : state_t;
-- Output registers
signal s_axi_awready_r : std_logic;
signal s_axi_wready_r : std_logic;
signal s_axi_bid_r : std_logic_vector(s_axi_bid'range);
signal s_axi_bresp_r : std_logic_vector(s_axi_bresp'range);
signal s_axi_bvalid_r : std_logic;
signal s_axi_arready_r : std_logic;
signal s_axi_rid_r : std_logic_vector(s_axi_rid'range);
signal s_axi_rdata_r : std_logic_vector(s_axi_rdata'range);
signal s_axi_rresp_r : std_logic_vector(s_axi_rresp'range);
signal s_axi_rlast_r : std_logic;
signal s_axi_rvalid_r : std_logic;
signal astrb_r, stall_strb_r : std_logic_vector(astrb_out'range);
signal adata_r, stall_data_r : std_logic_vector(adata_out'range);
signal aaddr_r, stall_addr_r : std_logic_vector(aaddr_out'range);
signal avalid_r, awren_r, stall_data_valid_r, rready_r : std_logic;
signal burst_cnt_r : unsigned(s_axi_arlen'range);
signal read_cnt_r : unsigned(s_axi_arlen'range);
signal transaction_r : std_logic_vector(s_axi_arid'range);
signal burst_type_r : std_logic_vector(s_axi_arburst'range);
signal burst_size_r : unsigned(7 downto 0);
signal wrap_mask_r : std_logic_vector(s_axi_araddr'range);
signal axi_addr_r : std_logic_vector(s_axi_araddr'range);
signal axi_stall_r : std_logic;
function increment_addr(burst_type : std_logic_vector(s_axi_arburst'range);
size : unsigned;
wrap_mask : std_logic_vector(axi_addrw_g-1 downto 0);
address : std_logic_vector(axi_addrw_g-1 downto 0))
return std_logic_vector is
variable address_tmp : std_logic_vector(axi_addrw_g-1 downto 0);
begin
case burst_type is
when FIXED_BURST =>
return address;
when INCR_BURST =>
return std_logic_vector(unsigned(address) + size);
when WRAP_BURST => -- UNTESTED
address_tmp := std_logic_vector(unsigned(address) + size);
for I in address'range loop
if wrap_mask(I) = '0' then
address_tmp(I) := address(I);
end if;
end loop;
return address_tmp;
when others =>
-- coverage off
-- pragma translate_off
assert false report "Unrecognized burst type" severity warning;
-- pragma translate_on
-- coverage on
return address;
end case;
end function increment_addr;
function wrap_mask(axsize : std_logic_vector(s_axi_arsize'range);
axlen : std_logic_vector(s_axi_arlen'range))
return std_logic_vector is
variable mask_temp : std_logic_vector(axi_addrw_g-1 downto 0);
variable axsize_int : integer range 0 to 7
:= to_integer(unsigned(axsize));
begin
for I in mask_temp'range loop
if I < axsize_int then
mask_temp(I) := '0';
elsif I < axsize_int + axlen'high then
mask_temp(I) := axlen(I - axsize_int);
else
mask_temp(I) := '0';
end if;
end loop;
return mask_temp;
end function wrap_mask;
begin
sync : process(clk, rstx)
variable axi_addr_v : std_logic_vector(axi_addr_r'range);
begin
if not sync_reset_c and rstx = '0' then
s_axi_awready_r <= '0';
s_axi_wready_r <= '0';
s_axi_bid_r <= (others => '0');
s_axi_bresp_r <= (others => '0');
s_axi_bvalid_r <= '0';
s_axi_arready_r <= '0';
s_axi_rid_r <= (others => '0');
s_axi_rdata_r <= (others => '0');
s_axi_rresp_r <= (others => '0');
s_axi_rlast_r <= '0';
s_axi_rvalid_r <= '0';
avalid_r <= '0';
aaddr_r <= (others => '0');
awren_r <= '0';
astrb_r <= (others => '0');
adata_r <= (others => '0');
rready_r <= '0';
axi_addr_r <= (others => '0');
state <= S_READY;
burst_cnt_r <= (others => '0');
transaction_r <= (others => '0');
stall_strb_r <= (others => '0');
stall_data_r <= (others => '0');
stall_addr_r <= (others => '0');
stall_data_valid_r <= '0';
elsif rising_edge(clk) then
if sync_reset_c and rstx = '0' then
s_axi_awready_r <= '0';
s_axi_wready_r <= '0';
s_axi_bid_r <= (others => '0');
s_axi_bresp_r <= (others => '0');
s_axi_bvalid_r <= '0';
s_axi_arready_r <= '0';
s_axi_rid_r <= (others => '0');
s_axi_rdata_r <= (others => '0');
s_axi_rresp_r <= (others => '0');
s_axi_rlast_r <= '0';
s_axi_rvalid_r <= '0';
avalid_r <= '0';
aaddr_r <= (others => '0');
awren_r <= '0';
astrb_r <= (others => '0');
adata_r <= (others => '0');
rready_r <= '0';
axi_addr_r <= (others => '0');
state <= S_READY;
burst_cnt_r <= (others => '0');
transaction_r <= (others => '0');
stall_strb_r <= (others => '0');
stall_data_r <= (others => '0');
stall_addr_r <= (others => '0');
stall_data_valid_r <= '0';
else
if s_axi_arready_r = '1' and s_axi_arvalid = '1' then
s_axi_arready_r <= '0';
end if;
if s_axi_awready_r = '1' and s_axi_awvalid = '1' then
s_axi_awready_r <= '0';
end if;
s_axi_wready_r <= '0';
rready_r <= '0';
s_axi_rlast_r <= '0';
-- valid_r(0) <= '0';
-- valid_r(2 downto 1) <= valid_r(1 downto 0);
axi_stall_r <= '0';
case state is
when S_READY =>
if s_axi_awvalid = '1' then
s_axi_awready_r <= '1';
axi_addr_r <= s_axi_awaddr;
transaction_r <= s_axi_awid;
wrap_mask_r <= wrap_mask(s_axi_awsize, s_axi_awlen);
burst_size_r <= burst_size_lut_c(to_integer(
unsigned(s_axi_awsize)));
burst_type_r <= s_axi_awburst;
burst_cnt_r <= unsigned(s_axi_awlen);
state <= S_WRITE_DATA;
elsif s_axi_arvalid = '1' then
s_axi_arready_r <= '1';
transaction_r <= s_axi_arid;
wrap_mask_r <= wrap_mask(s_axi_arsize, s_axi_arlen);
axi_addr_r <= s_axi_araddr;
aaddr_r <= s_axi_araddr(s_axi_araddr'high downto 2);
avalid_r <= '1';
awren_r <= '0';
rready_r <= '1';
burst_size_r <= burst_size_lut_c(to_integer(
unsigned(s_axi_arsize)));
burst_cnt_r <= unsigned(s_axi_arlen);
read_cnt_r <= unsigned(s_axi_arlen);
burst_type_r <= s_axi_arburst;
state <= S_READ_DATA;
end if;
when S_WRITE_DATA =>
if avalid_r = '0' or stall_data_valid_r = '0' then
s_axi_wready_r <= '1';
else
s_axi_wready_r <= '0';
end if;
if avalid_r = '1' and aready_in = '1' then
if stall_data_valid_r = '1' then
astrb_r <= stall_strb_r;
adata_r <= stall_data_r;
awren_r <= '1';
aaddr_r <= stall_addr_r;
stall_data_valid_r <= '0';
else
avalid_r <= '0';
end if;
end if;
if s_axi_wvalid = '1' and s_axi_wready_r = '1' then
if (aready_in = '1' and stall_data_valid_r = '0')
or avalid_r = '0' then
avalid_r <= '1';
awren_r <= '1';
astrb_r <= s_axi_wstrb;
adata_r <= s_axi_wdata;
aaddr_r <= axi_addr_r(axi_addr_r'high downto 2);
else
stall_data_valid_r <= '1';
stall_data_r <= s_axi_wdata;
stall_strb_r <= s_axi_wstrb;
stall_addr_r <= axi_addr_r(axi_addr_r'high downto 2);
end if;
if burst_cnt_r = 0 then
s_axi_wready_r <= '0';
s_axi_bresp_r <= AXI_OKAY;
s_axi_bvalid_r <= '1';
s_axi_bid_r <= transaction_r;
state <= S_FINISH_WRITE;
else
axi_addr_r <= increment_addr(burst_type_r, burst_size_r,
wrap_mask_r, axi_addr_r);
burst_cnt_r <= burst_cnt_r - 1;
end if;
end if;
when S_FINISH_WRITE =>
if s_axi_bready = '1' then
s_axi_bvalid_r <= '0';
end if;
if avalid_r = '1' and aready_in = '1' then
if stall_data_valid_r = '1' then
astrb_r <= stall_strb_r;
adata_r <= stall_data_r;
awren_r <= '1';
stall_data_valid_r <= '0';
else
avalid_r <= '0';
awren_r <= '0';
end if;
end if;
if avalid_r = '0' and s_axi_bvalid_r = '0' then
state <= S_READY;
end if;
when S_READ_DATA =>
if s_axi_rready = '1' and s_axi_rvalid_r = '1' then
if stall_data_valid_r = '1' then
s_axi_rdata_r <= stall_data_r;
stall_data_valid_r <= '0';
else
s_axi_rvalid_r <= '0';
end if;
end if;
if avalid_r = '1' and aready_in = '1' then
if read_cnt_r = 0 then
avalid_r <= '0';
else
axi_addr_v := increment_addr(burst_type_r, burst_size_r,
wrap_mask_r, axi_addr_r);
axi_addr_r <= axi_addr_v;
aaddr_r <= axi_addr_v(axi_addr_v'high downto 2);
read_cnt_r <= read_cnt_r - 1;
end if;
end if;
if s_axi_rvalid_r = '0' or stall_data_valid_r = '0' then
rready_r <= '1';
else
rready_r <= '0';
end if;
if rvalid_in = '1' and rready_r = '1' then
if (s_axi_rready = '1'and stall_data_valid_r = '0')
or s_axi_rvalid_r = '0' then
s_axi_rvalid_r <= '1';
s_axi_rdata_r <= rdata_in;
s_axi_rresp_r <= AXI_OKAY;
s_axi_rid_r <= transaction_r;
else
stall_data_valid_r <= '1';
stall_data_r <= rdata_in;
rready_r <= '0';
end if;
if burst_cnt_r = 0 then
if (s_axi_rready = '1'and stall_data_valid_r = '0')
or s_axi_rvalid_r = '0' then
s_axi_rlast_r <= '1';
end if;
rready_r <= '0';
state <= S_FINISH_READ;
else
burst_cnt_r <= burst_cnt_r - 1;
end if;
end if;
when S_FINISH_READ =>
if s_axi_rready = '1' and s_axi_rvalid_r = '1' then
if stall_data_valid_r = '1' then
s_axi_rlast_r <= '1';
s_axi_rdata_r <= stall_data_r;
stall_data_valid_r <= '0';
else
s_axi_rvalid_r <= '0';
s_axi_rlast_r <= '0';
state <= S_READY;
end if;
end if;
end case;
end if;
end if;
end process;
s_axi_awready <= s_axi_awready_r;
s_axi_wready <= s_axi_wready_r;
s_axi_bid <= s_axi_bid_r;
s_axi_bresp <= s_axi_bresp_r;
s_axi_bvalid <= s_axi_bvalid_r;
s_axi_arready <= s_axi_arready_r;
s_axi_rid <= s_axi_rid_r;
s_axi_rdata <= s_axi_rdata_r;
s_axi_rresp <= s_axi_rresp_r;
s_axi_rlast <= s_axi_rlast_r;
s_axi_rvalid <= s_axi_rvalid_r;
avalid_out <= avalid_r;
aaddr_out <= aaddr_r;
awren_out <= awren_r;
astrb_out <= astrb_r;
adata_out <= adata_r;
rready_out <= rready_r;
end architecture rtl;
| mit | ebdc66bd633427614686ee641fd40170 | 0.494065 | 3.333211 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/regfile_3p.vhd | 2 | 3,072 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: regfile_3p
-- File: regfile_3p.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: 3-port regfile implemented with two 2-port rams
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
entity regfile_3p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of regfile_3p is
constant rfinfer : boolean := (regfile_3p_infer(tech) = 1) or
(((tech = spartan3) or (tech = spartan3e) or (tech = virtex2) or (tech = virtex4) or (tech = virtex5)) and (abits <= 5));
begin
s0 : if rfinfer generate
rhu : generic_regfile_3p generic map (tech, abits, dbits, wrfst, numregs)
port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2);
end generate;
s1 : if not rfinfer generate
pere : if tech = peregrine generate
rfhard : peregrine_regfile_3p generic map (abits, dbits)
port map ( wclk, waddr, wdata, we, raddr1, re1, rdata1, raddr2, re2, rdata2);
end generate;
dp : if tech /= peregrine generate
x0 : syncram_2p generic map (tech, abits, dbits, 0, wrfst)
port map (rclk, re1, raddr1, rdata1, wclk, we, waddr, wdata, testin);
x1 : syncram_2p generic map (tech, abits, dbits, 0, wrfst)
port map (rclk, re2, raddr2, rdata2, wclk, we, waddr, wdata, testin);
end generate;
end generate;
end;
| mit | 6ac10de9464b7c3b3d6b843169372af4 | 0.616862 | 3.635503 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/buff_spi_ram.vhd | 3 | 9,944 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: buff_spi_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY buff_spi_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END buff_spi_ram;
ARCHITECTURE SYN OF buff_spi_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
intended_device_family => "MAX 10",
lpm_type => "altsyncram",
numwords_a => 512,
numwords_b => 512,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
read_during_write_mode_port_a => "NEW_DATA_WITH_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_WITH_NBE_READ",
widthad_a => 9,
widthad_b => 9,
width_a => 16,
width_b => 16,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
-- Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
-- Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
-- Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
-- Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
-- Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL buff_spi_ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL buff_spi_ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL buff_spi_ram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL buff_spi_ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL buff_spi_ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | fcd84b9dd82cca3d28fcf1dba4096a60 | 0.683126 | 3.383464 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/sim/jtag_ext.vhd | 2 | 2,054 | --------------------------------------------------------------------------------
-- Project: LEON-ARC
-- Entity: jtag_ext
-- Architecture(s): behav
-- Author: [email protected]
-- Company: Gleichmann Electronics
--
-- Description:
-- This file contains a simple module that listens to the JTAG signals TCK,
-- TMS, TDI and TDO.
-- If enabled, the logger prints the current value of the 4 pins mentioned
-- above into a log file whenever they change.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library work;
use work.txt_util.all;
entity jtag_ext is
generic (
logfile_name : string := "logfile_jtag";
t_delay : time := 5 ns);
port (
resetn : in std_logic;
-- logging enable signal
log_en : in std_logic := '1';
-- current cycle number
cycle_num : in integer;
tck : in std_logic;
tms : in std_logic;
tdi : in std_logic;
tdo : in std_logic);
end entity;
architecture behav of jtag_ext is
file logfile : text open write_mode is logfile_name;
shared variable logline : line;
shared variable logstring : string(1 to 80);
begin
log_start : process is
begin
if log_en = '1' then
print(logfile, "#");
print(logfile, "# CYCLE_NUMBER TCK TMS TDI TDO");
print(logfile, "#");
end if;
wait;
end process;
-- note: cycle number shall not be on sensitivity list
log_loop : process (log_en, tck, tdi, tdo, tms) is
begin
-- suspend process as soon as log enable is deasserted
if log_en = '0' then
-- wait;
elsif (log_en = '1') and (cycle_num >= 0) then
print(logfile,
str(cycle_num) & " " &
str(tck) & " " &
str(tms) & " " &
str(tdi) & " " &
str(tdo));
end if;
end process;
end architecture;
| mit | 71aaf973c583b34c0f0113efd95af18b | 0.508277 | 3.727768 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/sim/uart_ext.vhd | 2 | 2,239 | --------------------------------------------------------------------------------
-- Project: LEON-ARC
-- Entity: uart_ext
-- Architecture(s): behav
-- Author: [email protected]
-- Company: Gleichmann Electronics
--
-- Description:
-- This file contains a simple module that is connected to the 4 UART
-- signals CTS, RX, RTS and TX. It loops the signals RTS and TX back to the
-- outputs CTS and RX after a predefined time.
-- If enabled, the logger prints the current value of the 4 pins mentioned
-- above into a log file whenever they change.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library work;
use work.txt_util.all;
entity uart_ext is
generic (
logfile_name : string := "logfile_uart";
t_delay : time := 5 ns);
port (
resetn : in std_logic;
-- logging enable signal
log_en : in std_logic := '1';
-- current cycle number
cycle_num : in integer;
cts : out std_logic;
rxd : out std_logic;
txd : in std_logic;
rts : in std_logic);
end entity;
architecture behav of uart_ext is
file logfile : text open write_mode is logfile_name;
shared variable logline : line;
shared variable logstring : string(1 to 80);
begin
log_start : process is
begin
if log_en = '1' then
print(logfile, "#");
print(logfile, "# CYCLE_NUMBER CTS RX RTS TX");
print(logfile, "#");
end if;
wait;
end process;
-- note: cycle number shall not be on sensitivity list
log_loop : postponed process (log_en, rts, txd) is
variable rxd_int : std_logic;
variable cts_int : std_logic;
begin
rxd_int := txd;
cts_int := rts;
if (log_en = '1') and (cycle_num >= 0) then
print(logfile,
str(cycle_num) & " " &
str(cts_int) & " " &
str(rxd_int) & " " &
str(rts) & " " &
str(txd));
end if;
rxd <= rxd_int after t_delay;
cts <= cts_int after t_delay;
end process;
end architecture;
| mit | b578a62324497365e29508d2c7725f7c | 0.520322 | 3.688633 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/ringosc.vhd | 2 | 1,934 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ringosc
-- File: ringosc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Ring-oscillator with tech mapping
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ringosc is
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end ;
architecture rtl of ringosc is
component ringosc_dare
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
begin
dr : if tech = rhumc generate
drx : ringosc_dare port map (roen, roout);
end generate;
-- pragma translate_off
gen : if tech /= rhumc generate
signal tmp : std_ulogic := '0';
begin
tmp <= not tmp after 1 ns when roen = '1' else '0';
roout <= tmp;
end generate;
-- pragma translate_on
end architecture rtl; | mit | a05a5026eb118fadd549ff39553ebad7 | 0.596691 | 4.297778 | false | false | false | false |
Pinwino/sa | debugger_gw/wb_debugger.vhd | 1 | 14,095 | ----------------------------------------------------------------------------------
-- Company: FREE INDEPENDENT ALLIANCE OF MAKERS
-- Engineer: Jose Jimenez Montañez
--
-- Create Date: 21:56:34 06/08/2014
-- Design Name:
-- Module Name: wb_debugger - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.fine_delay_pkg.all;
--use work.etherbone_pkg.all;
use work.wr_xilinx_pkg.all;
use work.genram_pkg.all;
use work.wb_irq_pkg.all;
use work.debugger_pkg.all;
use work.synthesis_descriptor.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wb_debugger is
generic(
g_dbg_dpram_size : integer;
g_dbg_init_file : string;
g_reset_vector : t_wishbone_address := x"00000000"; -- if wb_irq_lm32 from general-cores::proposed-master
g_msi_queues : natural := 1;
g_profile : string := "medium_icache_debug";
g_internal_time_ref : boolean := true;
g_timers : integer := 1;
g_slave_interface_mode: t_wishbone_interface_mode := PIPELINED;
g_slave_granularity : t_wishbone_address_granularity := BYTE);
port(
clk_sys : in std_logic;
reset_n : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wrpc_uart_rxd_i : inout std_logic;
wrpc_uart_txd_o : inout std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
dbg_indicator : out std_logic;
dbg_control_select : in std_logic);
end wb_debugger;
architecture Behavioral of wb_debugger is
function f_check_if_lm32_firmware_necessary return boolean is
begin
if(g_dbg_init_file /= "") then
return true;
else
return false;
end if;
end function;
function f_generate_irq_timer return integer is
begin
if(g_timers /= 0) then
return 1;
else
return 0;
end if;
end function;
function f_generate_time_ref return integer is
begin
if(g_internal_time_ref) then
return 1;
else
return 0;
end if;
end function;
function f_choose_lm32_firmware_file return string is
begin
if(g_dbg_init_file = "debugger") then
report "[Dbg Core] Using debugging firmware." severity note;
return "../../dbg.ram";
elsif (g_dbg_init_file = "FD_node") then
report "[Dbg Core] Using FMC Delay stand alone node firmware." severity note;
return "../../fd_std.ram";
else
report "[Dbg Core] Using user provided firmware." severity note;
return g_dbg_init_file;
end if;
end function;
function f_select_dpram_size return integer is
begin
if(g_dbg_init_file = "debugger") then
report "[Dbg Core] Using a 40960 Bytes size RAM." severity note;
return 40960/4;
elsif (g_dbg_init_file = "FD_node") then
report "[Dbg Core] Using a 114740 Bytes RAM." severity note;
return 114740/4;
else
report "[Dbg Core] Using user specifie size RAM size." severity note;
return g_dbg_dpram_size;
end if;
end function;
-- constant c_NUM_WB_MASTERS : integer := 6 + f_generate_irq_timer + f_generate_time_ref;
constant c_NUM_WB_MASTERS : integer := 4 + f_generate_irq_timer + f_generate_time_ref;
constant c_NUM_WB_SLAVES : integer := 3;
constant c_MASTER_LM32 : integer := 0;
constant c_MASTER_ADAPT : integer := 2;
constant c_EXT_BRIDGE : integer := 0;
constant c_SLAVE_DPRAM : integer := 1;
constant c_SLAVE_UART : integer := 2;
constant c_SLAVE_IRQ_CTRL : integer := 3;
constant c_SLAVE_TICS : integer := c_SLAVE_IRQ_CTRL + f_generate_time_ref;
constant c_SLAVE_TIMER_IRQ: integer := c_SLAVE_TICS + f_generate_irq_timer;
constant c_EXT_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"000effff", x"00000000");
constant c_FREQ_DIVIDER : integer := 62500; -- LM32 clk = 62.5 Mhz
function f_generate_c_interconection_layout(
num_wb_masters : integer;
last_mandatory_slave : integer
)
return t_sdb_record_array is
variable interconnect_layout : t_sdb_record_array(NUM_WB_MASTERS-1 downto 0);
variable offset : integer range last_mandatory_slave to NUM_WB_MASTERS-1 := last_mandatory_slave;
variable adr_off: unsigned (c_wishbone_address_width-1 downto 0);
begin
-- Vader is Coming Look Busy
interconnect_layout (offset downto 0):=
(c_EXT_BRIDGE => f_sdb_embed_bridge(c_EXT_BRIDGE_SDB, x"00100000"),
c_SLAVE_DPRAM => f_sdb_embed_device(f_xwb_dbg_dpram(f_select_dpram_size), x"00000000"),
c_SLAVE_UART => f_sdb_embed_device(c_dbg_uart_sdb, x"00020100"),
c_SLAVE_IRQ_CTRL => f_sdb_embed_device(c_dbg_irq_ctrl_sdb, x"00020200"));
adr_off := x"00020300";
if (f_generate_time_ref /= 0) then
offset := offset + f_generate_time_ref;
interconnect_layout (offset) := f_sdb_embed_device(c_xwb_dbg_tics_sdb, t_wishbone_address(adr_off));
adr_off := adr_off + x"100";
end if;
if (f_generate_irq_timer /= 0) then
offset := offset + f_generate_irq_timer;
interconnect_layout (offset) := f_sdb_embed_device(c_dbg_irq_timer_sdb, t_wishbone_address(adr_off));
adr_off := adr_off + x"100";
end if;
--interconnect_layout (offset+1) := f_sdb_embed_synthesis(c_sdb_synthesis_info);
--interconnect_layout (offset+2) := f_sdb_embed_repo_url(c_sdb_repo_url);
return interconnect_layout;
end function;
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array := f_generate_c_interconection_layout (c_NUM_WB_MASTERS, c_SLAVE_IRQ_CTRL);
constant c_SDB_ADDRESS : t_wishbone_address := x"00020800";
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array (c_NUM_WB_SLAVES-1 downto 0);
signal dummy_debugger_ram_wbb_i : t_wishbone_slave_in;
signal forced_lm32_reset_n : std_logic := '1';
signal irq_slave_i : t_wishbone_slave_in_array(g_msi_queues-1 to 0);
signal irq_slave_o : t_wishbone_slave_out_array(g_msi_queues-1 to 0);
signal local_counter : unsigned (63 downto 0);
signal uart_dummy_i : std_logic;
signal uart_dummy_o : std_logic;
signal dbg_uart_rxd_i : std_logic;
signal dbg_uart_txd_o : std_logic;
signal use_dbg_uart : std_logic := '1';
signal state_control : unsigned (39 downto 0) := x"0000000000";
begin
dbg_indicator <= forced_lm32_reset_n;
master_o <= cnx_master_out(c_EXT_BRIDGE);
cnx_master_in(c_EXT_BRIDGE) <= master_i;
--------------------------------------
-- UART Selector & Reset controller
--------------------------------------
controller : process (clk_sys)
begin
if (rising_edge(clk_sys)) then
if (dbg_control_select = '0') then
if (state_control /= x"ffffffffff") then
state_control <= state_control + 1;
end if;
else
if ((state_control /= x"0000000000") and (state_control <= x"3B9ACA0")) then --0.5s
forced_lm32_reset_n <= not forced_lm32_reset_n;
elsif (state_control > x"3B9ACA0") then
use_dbg_uart <= not use_dbg_uart;
end if;
state_control <= x"0000000000";
end if;
end if;
end process;
--------------------------------------
-- UART
--------------------------------------
uart_txd_o <= dbg_uart_txd_o when use_dbg_uart ='1' else wrpc_uart_txd_o;
dbg_uart_rxd_i <= uart_rxd_i when use_dbg_uart ='1' else '1';
wrpc_uart_rxd_i <= uart_rxd_i when use_dbg_uart ='0' else '1';
DBG_UART : xwb_simple_uart
generic map(
g_with_virtual_uart => true,
g_with_physical_uart => true,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => reset_n,
slave_i => cnx_master_out(c_SLAVE_UART),
slave_o => cnx_master_in(c_SLAVE_UART),
desc_o => open,
uart_rxd_i => dbg_uart_rxd_i,
uart_txd_o => dbg_uart_txd_o
);
-----------------------------------------------------------------------------
-- LM32, with MSI interface
-----------------------------------------------------------------------------
DBG_IRQ_LM32_CORE : wb_irq_lm32
generic map(
g_msi_queues => g_msi_queues,
g_profile => g_profile
)
port map(
clk_sys_i => clk_sys,
rst_n_i => forced_lm32_reset_n,
dwb_o => cnx_slave_in(c_MASTER_LM32),
dwb_i => cnx_slave_out(c_MASTER_LM32),
iwb_o => cnx_slave_in(c_MASTER_LM32+1),
iwb_i => cnx_slave_out(c_MASTER_LM32+1),
irq_slave_o => irq_slave_o, -- wb msi interface
irq_slave_i => irq_slave_i,
ctrl_slave_o => cnx_master_in(c_SLAVE_IRQ_CTRL), -- ctrl interface for LM32 irq processing
ctrl_slave_i => cnx_master_out(c_SLAVE_IRQ_CTRL)
);
---------------------------------------------------------------------------
-- Dual-port RAM
-----------------------------------------------------------------------------
DBG_DPRAM : xwb_dpram
generic map(
g_size => f_select_dpram_size, --in 32-bit words
-- g_size => g_dbg_dpram_size, --in 32-bit words
g_init_file => f_choose_lm32_firmware_file,
g_must_have_init_file => f_check_if_lm32_firmware_necessary,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => WORD
)
port map(
clk_sys_i => clk_sys,
rst_n_i => reset_n,
slave1_i => cnx_master_out(c_SLAVE_DPRAM),
slave1_o => cnx_master_in(c_SLAVE_DPRAM),
slave2_i => dummy_debugger_ram_wbb_i,
slave2_o => open
);
---------------------------------------------------------------------------
-- TIMER
---------------------------------------------------------------------------
gen_time_ref : if (f_generate_time_ref /= 0) generate
begin
DBG_TIME_REF : xwb_tics
generic map(
g_period => c_FREQ_DIVIDER
)
port map(
clk_sys_i => clk_sys,
rst_n_i => reset_n,
-- Wishbone
slave_i => cnx_master_out(c_SLAVE_TICS),
slave_o => cnx_master_in(c_SLAVE_TICS),
desc_o => open
);
end generate gen_time_ref;
gen_timer : if (g_timers > 0) generate
begin
process(clk_sys)
begin
if (clk_sys'event and clk_sys = '1') then
if (reset_n = '0') then
local_counter <= (others => '0');
else
local_counter <= local_counter + 1;
end if;
end if;
end process;
DBG_IRQ_TIMER : wb_irq_timer
generic map(
g_timers => g_timers
)
port map(
clk_sys_i => clk_sys,
rst_sys_n_i => forced_lm32_reset_n,
tm_tai8ns_i => std_logic_vector(local_counter),
ctrl_slave_o => cnx_master_in(c_SLAVE_TIMER_IRQ), -- ctrl interface for LM32 irq processing
ctrl_slave_i => cnx_master_out(c_SLAVE_TIMER_IRQ),
irq_master_o => irq_slave_i(g_timers-1), -- wb msi interface
irq_master_i => irq_slave_o(g_timers-1)
);
end generate gen_timer;
---------------------------------------------------------------------------
-- Crossbar
---------------------------------------------------------------------------
DBG_MAIN_INTERCON : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS
)
port map (
clk_sys_i => clk_sys,
rst_n_i => reset_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out
);
---------------------------------------------------------------------------
-- Adatper
---------------------------------------------------------------------------
DBG_SALVE_ADAPTER : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => g_slave_interface_mode,
g_master_granularity => BYTE,
g_slave_use_struct => false,
g_slave_mode => g_slave_interface_mode,
g_slave_granularity => g_slave_granularity)
port map (
clk_sys_i => clk_sys,
rst_n_i => reset_n,
master_i => cnx_slave_out(c_MASTER_ADAPT),
master_o => cnx_slave_in(c_MASTER_ADAPT),
-- Slave interface 0x0 to 0x3ffff
sl_adr_i(c_wishbone_address_width-1 downto 18) => (others => '0'),
sl_adr_i(17 downto 0) => slave_i.adr(17 downto 0),
sl_dat_i => slave_i.dat,
sl_sel_i => slave_i.sel,
sl_cyc_i => slave_i.cyc,
sl_stb_i => slave_i.stb,
sl_we_i => slave_i.we,
sl_dat_o => slave_o.dat,
sl_ack_o => slave_o.ack,
sl_err_o => slave_o.err,
sl_rty_o => slave_o.rty,
sl_stall_o => slave_o.stall
);
end Behavioral;
| gpl-3.0 | dc12204b6e5382950262ab8f3edba02f | 0.554775 | 3.342979 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/dsu3x.vhd | 2 | 24,511 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
library techmap;
use techmap.gencomp.all;
entity dsu3x is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end;
architecture rtl of dsu3x is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant NBITS : integer := log2x(ncpu);
constant PROC_H : integer := 24+NBITS-1;
constant PROC_L : integer := 24;
constant AREA_H : integer := 23;
constant AREA_L : integer := 20;
constant HBITS : integer := 28;
constant DSU3_VERSION : integer := 1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3DSU, 0, DSU3_VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
type slv_reg_type is record
hsel : std_ulogic;
haddr : std_logic_vector(PROC_H downto 0);
hwrite : std_ulogic;
hwdata : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hready : std_ulogic;
hready2 : std_ulogic;
end record;
type reg_type is record
slv : slv_reg_type;
en : std_logic_vector(0 to NCPU-1);
te : std_logic_vector(0 to NCPU-1);
be : std_logic_vector(0 to NCPU-1);
bw : std_logic_vector(0 to NCPU-1);
bs : std_logic_vector(0 to NCPU-1);
bx : std_logic_vector(0 to NCPU-1);
bz : std_logic_vector(0 to NCPU-1);
halt : std_logic_vector(0 to NCPU-1);
reset : std_logic_vector(0 to NCPU-1);
bn : std_logic_vector(NCPU-1 downto 0);
ss : std_logic_vector(NCPU-1 downto 0);
bmsk : std_logic_vector(NCPU-1 downto 0);
dmsk : std_logic_vector(NCPU-1 downto 0);
cnt : std_logic_vector(2 downto 0);
dsubre : std_logic_vector(2 downto 0);
dsuen : std_logic_vector(2 downto 0);
act : std_ulogic;
timer : std_logic_vector(tbits-1 downto 0);
pwd : std_logic_vector(NCPU-1 downto 0);
tstop : std_ulogic;
end record;
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
type tregtype is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
hsel : std_logic;
ahbactive : std_logic;
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bphit : std_logic; -- AHB breakpoint hit
bphit2 : std_logic; -- delayed bphit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
tbwr : std_logic; -- trace buffer write enable
break : std_logic; -- break CPU when AHB tracing stops
end record;
type hclk_reg_type is record
irq : std_ulogic;
oen : std_ulogic;
end record;
constant TRACEN : boolean := (kbytes /= 0);
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal tr, trin : tregtype;
signal r, rin : reg_type;
signal rh, rhin : hclk_reg_type;
signal ahbsi2 : ahb_slv_in_type;
signal hrdata2x : std_logic_vector(31 downto 0);
begin
comb: process(rst, r, ahbsi, ahbsi2, dbgi, dsui, ahbmi, tr, tbo, hclken, rh, hrdata2x)
variable v : reg_type;
variable iuacc : std_ulogic;
variable dbgmode, tstop : std_ulogic;
variable rawindex : integer range 0 to (2**NBITS)-1;
variable index : natural range 0 to NCPU-1;
variable hasel1 : std_logic_vector(AREA_H-1 downto AREA_L);
variable hasel2 : std_logic_vector(6 downto 2);
variable tv : tregtype;
variable vabufi : tracebuf_in_type;
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable cpwd : std_logic_vector(15 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable bphit1, bphit2 : std_ulogic;
variable vh : hclk_reg_type;
begin
v := r;
iuacc := '0'; --v.slv.hready := '0';
dbgmode := '0'; tstop := '1';
v.dsubre := r.dsubre(1 downto 0) & dsui.break;
v.dsuen := r.dsuen(1 downto 0) & dsui.enable;
hrdata := r.slv.hrdata;
tv := tr; vabufi.enable := '0'; tv.bphit := '0'; tv.tbwr := '0';
if (clk2x /= 0) then tv.bphit2 := tr.bphit; else tv.bphit2 := '0'; end if;
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); aindex := (others => '0');
hirq := (others => '0'); v.reset := (others => '0');
if TRACEN then
aindex := tr.aindex + 1;
if (clk2x /= 0) then vh.irq := tr.bphit or tr.bphit2; hirq(irq) := rh.irq;
else hirq(irq) := tr.bphit; end if;
end if;
if hclken = '1' then
v.slv.hready := '0'; v.act := '0';
end if;
-- check for AHB watchpoints
bphit1 := '0'; bphit2 := '0';
if TRACEN and ((ahbsi2.hready and tr.ahbactive) = '1') then
if ((((tr.tbreg1.addr xor tr.haddr(31 downto 2)) and tr.tbreg1.mask) = zero32(29 downto 0)) and
(((tr.tbreg1.read and not tr.hwrite) or (tr.tbreg1.write and tr.hwrite)) = '1'))
then bphit1 := '1'; end if;
if ((((tr.tbreg2.addr xor tr.haddr(31 downto 2)) and tr.tbreg2.mask) = zero32(29 downto 0)) and
(((tr.tbreg2.read and not tr.hwrite) or (tr.tbreg2.write and tr.hwrite)) = '1'))
then bphit2 := '1'; end if;
if (bphit1 or bphit2) = '1' then
if ((tr.enable and not r.act) = '1') and (tr.dcnten = '0') and
(tr.delaycnt /= zero32(TBUFABITS-1 downto 0))
then tv.dcnten := '1';
else tv.enable := '0'; tv.bphit := tr.break; end if;
end if;
end if;
-- generate AHB buffer inputs
vabufi.write := "0000";
if TRACEN then
if (tr.enable = '1') and (r.act = '0') then
vabufi.addr(TBUFABITS-1 downto 0) := tr.aindex;
vabufi.data(127) := bphit1 or bphit2;
vabufi.data(96+tbits-1 downto 96) := r.timer;
vabufi.data(94 downto 80) := ahbmi.hirq(15 downto 1);
vabufi.data(79) := tr.hwrite;
vabufi.data(78 downto 77) := tr.htrans;
vabufi.data(76 downto 74) := tr.hsize;
vabufi.data(73 downto 71) := tr.hburst;
vabufi.data(70 downto 67) := tr.hmaster;
vabufi.data(66) := tr.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if tr.hwrite = '1' then
vabufi.data(63 downto 32) := ahbsi2.hwdata;
else
vabufi.data(63 downto 32) := ahbmi.hrdata;
end if;
vabufi.data(31 downto 0) := tr.haddr;
else
vabufi.addr(TBUFABITS-1 downto 0) := tr.haddr(TBUFABITS+3 downto 4);
vabufi.data := ahbsi2.hwdata & ahbsi2.hwdata & ahbsi2.hwdata & ahbsi2.hwdata;
end if;
-- write trace buffer
if (tr.enable and not r.act) = '1' then
if (tr.ahbactive and ahbsi2.hready) = '1' then
tv.aindex := aindex; tv.tbwr := '1';
vabufi.enable := '1'; vabufi.write := "1111";
end if;
end if;
-- trace buffer delay counter handling
if (tr.dcnten = '1') then
if (tr.delaycnt = zero32(TBUFABITS-1 downto 0)) then
tv.enable := '0'; tv.dcnten := '0'; tv.bphit := tr.break;
end if;
if tr.tbwr = '1' then tv.delaycnt := tr.delaycnt - 1; end if;
end if;
-- save AHB transfer parameters
if (ahbsi2.hready = '1' ) then
tv.haddr := ahbsi2.haddr; tv.hwrite := ahbsi2.hwrite; tv.htrans := ahbsi2.htrans;
tv.hsize := ahbsi2.hsize; tv.hburst := ahbsi2.hburst;
tv.hmaster := ahbsi2.hmaster; tv.hmastlock := ahbsi2.hmastlock;
end if;
if tr.hsel = '1' then tv.hwdata := ahbsi2.hwdata; end if;
if ahbsi2.hready = '1' then
tv.hsel := ahbsi2.hsel(hindex);
tv.ahbactive := ahbsi2.htrans(1);
end if;
end if;
if r.slv.hsel = '1' then
if (clk2x = 0) then
v.cnt := r.cnt - 1;
else
if (r.cnt /= "111") or (hclken = '1') then v.cnt := r.cnt - 1; end if;
end if;
end if;
if (r.slv.hready and hclken) = '1' then
v.slv.hsel := '0'; --v.slv.act := '0';
end if;
for i in 0 to NCPU-1 loop
if dbgi(i).dsumode = '1' then
if r.dmsk(i) = '0' then
dbgmode := '1';
if hclken = '1' then v.act := '1'; end if;
end if;
v.bn(i) := '1';
else
tstop := '0';
end if;
end loop;
if tstop = '0' then v.timer := r.timer + 1; end if;
if (clk2x /= 0) then
if hclken = '1' then v.tstop := tstop; end if;
tstop := r.tstop;
end if;
cpwd := (others => '0');
for i in 0 to NCPU-1 loop
v.bn(i) := v.bn(i) or (dbgmode and r.bmsk(i)) or (r.dsubre(1) and not r.dsubre(2));
if TRACEN then v.bn(i) := v.bn(i) or (tr.bphit and not r.ss(i) and not r.act); end if;
v.pwd(i) := dbgi(i).idle and (not dbgi(i).ipend) and not v.bn(i);
end loop;
cpwd(NCPU-1 downto 0) := r.pwd;
if (ahbsi2.hready and ahbsi2.hsel(hindex)) = '1' then
if (ahbsi2.htrans(1) = '1') then
v.slv.hsel := '1';
v.slv.haddr := ahbsi2.haddr(PROC_H downto 0);
v.slv.hwrite := ahbsi2.hwrite;
v.cnt := "111";
end if;
end if;
for i in 0 to NCPU-1 loop
v.en(i) := r.dsuen(2) and dbgi(i).dsu;
end loop;
rawindex := conv_integer(r.slv.haddr(PROC_H downto PROC_L));
if ncpu = 1 then index := 0; else
if rawindex > ncpu then index := ncpu-1; else index := rawindex; end if;
end if;
hasel1 := r.slv.haddr(AREA_H-1 downto AREA_L);
hasel2 := r.slv.haddr(6 downto 2);
if r.slv.hsel = '1' then
case hasel1 is
when "000" => -- DSU registers
if r.cnt(2 downto 0) = "110" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := (others => '0');
case hasel2 is
when "00000" =>
if (r.slv.hwrite and hclken) = '1' then
v.te(index) := ahbsi2.hwdata(0);
v.be(index) := ahbsi2.hwdata(1);
v.bw(index) := ahbsi2.hwdata(2);
v.bs(index) := ahbsi2.hwdata(3);
v.bx(index) := ahbsi2.hwdata(4);
v.bz(index) := ahbsi2.hwdata(5);
v.reset(index) := ahbsi2.hwdata(9);
v.halt(index) := ahbsi2.hwdata(10);
else
hrdata(0) := r.te(index);
hrdata(1) := r.be(index);
hrdata(2) := r.bw(index);
hrdata(3) := r.bs(index);
hrdata(4) := r.bx(index);
hrdata(5) := r.bz(index);
hrdata(6) := dbgi(index).dsumode;
hrdata(7) := r.dsuen(2);
hrdata(8) := r.dsubre(2);
hrdata(9) := not dbgi(index).error;
hrdata(10) := dbgi(index).halt;
hrdata(11) := dbgi(index).pwd;
end if;
when "00010" => -- timer
if (r.slv.hwrite and hclken) = '1' then
v.timer := ahbsi2.hwdata(tbits-1 downto 0);
else
hrdata(tbits-1 downto 0) := r.timer;
end if;
when "01000" =>
if (r.slv.hwrite and hclken) = '1' then
v.bn := ahbsi2.hwdata(NCPU-1 downto 0);
v.ss := ahbsi2.hwdata(16+NCPU-1 downto 16);
else
hrdata(NCPU-1 downto 0) := r.bn;
hrdata(16+NCPU-1 downto 16) := r.ss;
end if;
when "01001" =>
if (r.slv.hwrite and hclken) = '1' then
v.bmsk(NCPU-1 downto 0) := ahbsi2.hwdata(NCPU-1 downto 0);
v.dmsk(NCPU-1 downto 0) := ahbsi2.hwdata(NCPU-1+16 downto 16);
else
hrdata(NCPU-1 downto 0) := r.bmsk;
hrdata(NCPU-1+16 downto 16) := r.dmsk;
end if;
when "10000" =>
if TRACEN then
hrdata((TBUFABITS + 15) downto 16) := tr.delaycnt;
hrdata(2 downto 0) := tr.break & tr.dcnten & tr.enable;
if (r.slv.hwrite and hclken) = '1' then
tv.delaycnt := ahbsi2.hwdata((TBUFABITS+ 15) downto 16);
tv.break := ahbsi2.hwdata(2);
tv.dcnten := ahbsi2.hwdata(1);
tv.enable := ahbsi2.hwdata(0);
end if;
end if;
when "10001" =>
if TRACEN then
hrdata((TBUFABITS - 1 + 4) downto 4) := tr.aindex;
if (r.slv.hwrite and hclken) = '1' then
tv.aindex := ahbsi2.hwdata((TBUFABITS - 1 + 4) downto 4);
end if;
end if;
when "10100" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg1.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.addr := ahbsi2.hwdata(31 downto 2);
end if;
end if;
when "10101" =>
if TRACEN then
hrdata := tr.tbreg1.mask & tr.tbreg1.read & tr.tbreg1.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.mask := ahbsi2.hwdata(31 downto 2);
tv.tbreg1.read := ahbsi2.hwdata(1);
tv.tbreg1.write := ahbsi2.hwdata(0);
end if;
end if;
when "10110" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg2.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.addr := ahbsi2.hwdata(31 downto 2);
end if;
end if;
when "10111" =>
if TRACEN then
hrdata := tr.tbreg2.mask & tr.tbreg2.read & tr.tbreg2.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.mask := ahbsi2.hwdata(31 downto 2);
tv.tbreg2.read := ahbsi2.hwdata(1);
tv.tbreg2.write := ahbsi2.hwdata(0);
end if;
end if;
when others =>
end case;
when "010" => -- AHB tbuf
if TRACEN then
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
vabufi.enable := not (tr.enable and not r.act);
case tr.haddr(3 downto 2) is
when "00" =>
hrdata := tbo.data(127 downto 96);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(3) := vabufi.enable and v.slv.hready;
end if;
when "01" =>
hrdata := tbo.data(95 downto 64);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(2) := vabufi.enable and v.slv.hready;
end if;
when "10" =>
hrdata := tbo.data(63 downto 32);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(1) := vabufi.enable and v.slv.hready;
end if;
when others =>
hrdata := tbo.data(31 downto 0);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(0) := vabufi.enable and v.slv.hready;
end if;
end case;
end if;
when "011" | "001" => -- IU reg file, IU tbuf
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "100" => -- IU reg access
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(1 downto 0) = "11" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "111" => -- DSU ASI
if r.cnt(2 downto 1) = "11" then iuacc := '1'; else iuacc := '0'; end if;
if (dbgi(index).crdy = '1') or (r.cnt = "000") then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := dbgi(index).data;
when others =>
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end case;
if (r.slv.hready and hclken and not v.slv.hsel) = '1' then v.slv.hready := '0'; end if;
if (clk2x /= 0) and (r.slv.hready2 and hclken) = '1' then v.slv.hready := '1'; end if;
end if;
if r.slv.hsel = '1' then
if (r.slv.hwrite and hclken) = '1' then v.slv.hwdata := ahbsi2.hwdata; end if;
if (clk2x = 0) or ((r.slv.hready or r.slv.hready2) = '0') then
v.slv.hrdata := hrdata;
end if;
end if;
if ((ahbsi2.hready and ahbsi2.hsel(hindex)) = '1') and (ahbsi2.htrans(1) = '0') then
if (clk2x = 0) or (r.slv.hsel = '0') then
v.slv.hready := '1';
end if;
end if;
if (clk2x /= 0) and (r.slv.hready = '1') then v.slv.hready2 := '0'; end if;
if v.slv.hsel = '0' then v.slv.hready := '1'; end if;
vh.oen := '0';
if (clk2x /= 0) then
if (hclken and r.slv.hsel and (r.slv.hready2 or v.slv.hready)) = '1'
then vh.oen := '1'; end if;
if (r.slv.hsel = '1') and (r.cnt = "111") and (hclken = '0') then iuacc := '0'; end if;
end if;
if rst = '0' then
v.bn := (others => r.dsubre(2)); v.bmsk := (others => '0');
v.dmsk := (others => '0');
v.ss := (others => '0'); v.timer := (others => '0'); v.slv.hsel := '0';
for i in 0 to NCPU-1 loop
v.bw(i) := r.dsubre(2); v.be(i) := r.dsubre(2);
v.bx(i) := r.dsubre(2); v.bz(i) := r.dsubre(2);
v.bs(i) := '0'; v.te(i) := '0';
end loop;
tv.ahbactive := '0'; tv.enable := '0';
tv.hsel := '0'; tv.dcnten := '0';
tv.tbreg1.read := '0'; tv.tbreg1.write := '0';
tv.tbreg2.read := '0'; tv.tbreg2.write := '0';
v.slv.hready := '1'; v.halt := (others => '0');
end if;
vabufi.enable := vabufi.enable and not ahbsi.scanen;
vabufi.diag := ahbsi.testen & "000";
rin <= v; trin <= tv; tbi <= vabufi;
for i in 0 to NCPU-1 loop
dbgo(i).tenable <= r.te(i);
dbgo(i).dsuen <= r.en(i);
dbgo(i).dbreak <= r.bn(i); -- or (dbgmode and r.bmsk(i));
if conv_integer(r.slv.haddr(PROC_H downto PROC_L)) = i then
dbgo(i).denable <= iuacc;
else
dbgo(i).denable <= '0';
end if;
dbgo(i).step <= r.ss(i);
dbgo(i).berror <= r.be(i);
dbgo(i).bsoft <= r.bs(i);
dbgo(i).bwatch <= r.bw(i);
dbgo(i).btrapa <= r.bx(i);
dbgo(i).btrape <= r.bz(i);
dbgo(i).daddr <= r.slv.haddr(PROC_L-1 downto 2);
dbgo(i).ddata <= r.slv.hwdata;
dbgo(i).dwrite <= r.slv.hwrite;
dbgo(i).halt <= r.halt(i);
dbgo(i).reset <= r.reset(i);
dbgo(i).timer(tbits-1 downto 0) <= r.timer;
dbgo(i).timer(30 downto tbits) <= (others => '0');
end loop;
ahbso.hconfig <= hconfig;
ahbso.hresp <= HRESP_OKAY;
ahbso.hready <= r.slv.hready;
if (clk2x = 0) then
ahbso.hrdata <= r.slv.hrdata;
else
ahbso.hrdata <= hrdata2x;
end if;
ahbso.hsplit <= (others => '0');
ahbso.hcache <= '0';
ahbso.hirq <= hirq;
ahbso.hindex <= hindex;
dsuo.active <= r.act;
dsuo.tstop <= tstop;
dsuo.pwd <= cpwd;
rhin <= vh;
end process;
comb2gen0 : if (clk2x /= 0) generate
ag0 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hmastlock, hclken, ahbsi2.hmastlock);
ag1 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwrite, hclken, ahbsi2.hwrite);
ag2 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hready, hclken, ahbsi2.hready);
gen3 : for i in ahbsi.haddr'range generate
ag3 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.haddr(i), hclken, ahbsi2.haddr(i));
end generate;
gen4 : for i in ahbsi.htrans'range generate
ag4 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.htrans(i), hclken, ahbsi2.htrans(i));
end generate;
gen5 : for i in ahbsi.hwdata'range generate
ag5 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwdata(i), hclken, ahbsi2.hwdata(i));
end generate;
gen6 : for i in ahbsi.hsize'range generate
ag6 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsize(i), hclken, ahbsi2.hsize(i));
end generate;
gen7 : for i in ahbsi.hburst'range generate
ag7 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hburst(i), hclken, ahbsi2.hburst(i));
end generate;
gen8 : for i in ahbsi.hmaster'range generate
ag8 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hmaster(i), hclken, ahbsi2.hmaster(i));
end generate;
gen9 : for i in ahbsi.hsel'range generate
ag9 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsel(i), hclken, ahbsi2.hsel(i));
end generate;
gen10 : for i in hrdata2x'range generate
ag10 : clkand generic map (tech => 0, ren => 0) port map (r.slv.hrdata(i), rh.oen, hrdata2x(i));
end generate;
reg2 : process(hclk)
begin
if rising_edge(hclk) then rh <= rhin; end if;
end process;
end generate;
comb2gen1 : if (clk2x = 0) generate
ahbsi2 <= ahbsi; rh.irq <= '0'; rh.oen <= '0'; hrdata2x <= (others => '0');
end generate;
reg : process(cpuclk)
begin
if rising_edge(cpuclk) then r <= rin; end if;
end process;
tb0 : if TRACEN generate
treg : process(cpuclk)
begin if rising_edge(cpuclk) then tr <= trin; end if; end process;
mem0 : tbufmem
generic map (tech => tech, tbuf => kbytes) port map (cpuclk, tbi, tbo);
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit + AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end generate;
notb : if not TRACEN generate
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit");
-- pragma translate_on
end generate;
end;
| mit | 1956e33a2c5e64f96db41d53fc6c17c8 | 0.538615 | 3.295818 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/leon3mp.vhd | 1 | 21,368 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
signal stati : ahbstat_in_type;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-- gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
-- grgpio0: grgpio
-- generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
-- nbits => CFG_GRGPIO_WIDTH)
-- port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
--
-- pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
-- pio_pad : iopad generic map (tech => padtech)
-- port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-- end generate;
-- end generate;
-- ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
-- ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
-- nftslv => CFG_AHBSTATN)
-- port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_version
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| mit | be26f752875ed87d0e6a671fa47ac51c | 0.550824 | 3.540093 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/resultMemory2.vhd | 1 | 41,304 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY grlib;
USE grlib.amba.all;
USE grlib.stdlib.all;
LIBRARY gaisler;
USE grlib.devices.all;
USE gaisler.memctrl.all;
LIBRARY techmap;
USE techmap.gencomp.all;
ENTITY ddrsp64a IS
GENERIC (
memtech : integer := 0;
hindex : integer := 3;
haddr : integer := 1024;
hmask : integer := 3072;
ioaddr : integer := 1;
iomask : integer := 4095;
MHz : integer := 90;
col : integer := 9;
Mbyte : integer := 256;
fast : integer := 0;
pwron : integer := 1;
oepol : integer := 0
);
PORT (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
END ENTITY;
ARCHITECTURE rtl OF ddrsp64a IS
CONSTANT REVISION : integer := 0;
CONSTANT CMD_PRE : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT CMD_REF : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT CMD_LMR : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT CMD_EMR : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT abuf : integer := 6;
CONSTANT hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER , GAISLER_DDRSP , 0 , 0 , 0 ) , 4 => ahb_membar ( 1024 , '1' , '1' , 3072 ) , 5 => ahb_iobar ( 1 , 4095 ) , OTHERS => zero32 );
TYPE mcycletype IS ( midle , active , ext , leadout );
TYPE ahb_state_type IS ( midle , rhold , dread , dwrite , whold1 , whold2 );
TYPE sdcycletype IS ( act1 , act2 , act3 , rd1 , rd2 , rd3 , rd4 , rd5 , rd6 , rd7 , rd8 , wr1 , wr2 , wr3 , wr4a , wr4 , wr5 , sidle , ioreg1 , ioreg2 );
TYPE icycletype IS ( iidle , pre , ref1 , ref2 , emode , lmode , finish );
CONSTANT NAHBMST : integer := 16;
CONSTANT NAHBSLV : integer := 16;
CONSTANT NAPBSLV : integer := 16;
CONSTANT NAHBIRQ : integer := 32;
CONSTANT NAHBAMR : integer := 4;
CONSTANT NAHBIR : integer := 4;
CONSTANT NAHBCFG : integer := 4 + 4;
CONSTANT NAPBIR : integer := 1;
CONSTANT NAPBAMR : integer := 1;
CONSTANT NAPBCFG : integer := 1 + 1;
CONSTANT NBUS : integer := 4;
SUBTYPE amba_config_word IS std_logic_vector ( 31 downto 0 );
TYPE ahb_config_type IS ARRAY ( 0 to 4 + 4 - 1 ) OF amba_config_word;
TYPE apb_config_type IS ARRAY ( 0 to 1 + 1 - 1 ) OF amba_config_word;
TYPE ahb_mst_in_type IS RECORD
hgrant : std_logic_vector ( 0 to 16 - 1 );
hready : std_ulogic;
hresp : std_logic_vector ( 1 downto 0 );
hrdata : std_logic_vector ( 31 downto 0 );
hcache : std_ulogic;
hirq : std_logic_vector ( 32 - 1 downto 0 );
testen : std_ulogic;
testrst : std_ulogic;
scanen : std_ulogic;
testoen : std_ulogic;
END RECORD;
TYPE ahb_mst_out_type IS RECORD
hbusreq : std_ulogic;
hlock : std_ulogic;
htrans : std_logic_vector ( 1 downto 0 );
haddr : std_logic_vector ( 31 downto 0 );
hwrite : std_ulogic;
hsize : std_logic_vector ( 2 downto 0 );
hburst : std_logic_vector ( 2 downto 0 );
hprot : std_logic_vector ( 3 downto 0 );
hwdata : std_logic_vector ( 31 downto 0 );
hirq : std_logic_vector ( 32 - 1 downto 0 );
hconfig : ahb_config_type;
hindex : integer RANGE 0 to 16 - 1;
END RECORD;
TYPE ahb_slv_in_type IS RECORD
hsel : std_logic_vector ( 0 to 16 - 1 );
haddr : std_logic_vector ( 31 downto 0 );
hwrite : std_ulogic;
htrans : std_logic_vector ( 1 downto 0 );
hsize : std_logic_vector ( 2 downto 0 );
hburst : std_logic_vector ( 2 downto 0 );
hwdata : std_logic_vector ( 31 downto 0 );
hprot : std_logic_vector ( 3 downto 0 );
hready : std_ulogic;
hmaster : std_logic_vector ( 3 downto 0 );
hmastlock : std_ulogic;
hmbsel : std_logic_vector ( 0 to 4 - 1 );
hcache : std_ulogic;
hirq : std_logic_vector ( 32 - 1 downto 0 );
testen : std_ulogic;
testrst : std_ulogic;
scanen : std_ulogic;
testoen : std_ulogic;
END RECORD;
TYPE ahb_slv_out_type IS RECORD
hready : std_ulogic;
hresp : std_logic_vector ( 1 downto 0 );
hrdata : std_logic_vector ( 31 downto 0 );
hsplit : std_logic_vector ( 15 downto 0 );
hcache : std_ulogic;
hirq : std_logic_vector ( 32 - 1 downto 0 );
hconfig : ahb_config_type;
hindex : integer RANGE 0 to 16 - 1;
END RECORD;
TYPE ahb_mst_out_vector_type IS ARRAY ( natural RANGE <> ) OF ahb_mst_out_type;
TYPE ahb_slv_out_vector_type IS ARRAY ( natural RANGE <> ) OF ahb_slv_out_type;
SUBTYPE ahb_mst_out_vector IS ahb_mst_out_vector_type ( 16 - 1 downto 0 );
SUBTYPE ahb_slv_out_vector IS ahb_slv_out_vector_type ( 16 - 1 downto 0 );
TYPE ahb_mst_out_bus_vector IS ARRAY ( 0 to 4 - 1 ) OF ahb_mst_out_vector;
TYPE ahb_slv_out_bus_vector IS ARRAY ( 0 to 4 - 1 ) OF ahb_slv_out_vector;
CONSTANT HTRANS_IDLE : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT HTRANS_BUSY : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT HTRANS_NONSEQ : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT HTRANS_SEQ : std_logic_vector ( 1 downto 0 ) := "11";
CONSTANT HBURST_SINGLE : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT HBURST_INCR : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT HBURST_WRAP4 : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT HBURST_INCR4 : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT HBURST_WRAP8 : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT HBURST_INCR8 : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT HBURST_WRAP16 : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT HBURST_INCR16 : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT HSIZE_BYTE : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT HSIZE_HWORD : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT HSIZE_WORD : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT HSIZE_DWORD : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT HSIZE_4WORD : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT HSIZE_8WORD : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT HSIZE_16WORD : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT HSIZE_32WORD : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT HRESP_OKAY : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT HRESP_ERROR : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT HRESP_RETRY : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT HRESP_SPLIT : std_logic_vector ( 1 downto 0 ) := "11";
TYPE apb_slv_in_type IS RECORD
psel : std_logic_vector ( 0 to 16 - 1 );
penable : std_ulogic;
paddr : std_logic_vector ( 31 downto 0 );
pwrite : std_ulogic;
pwdata : std_logic_vector ( 31 downto 0 );
pirq : std_logic_vector ( 32 - 1 downto 0 );
testen : std_ulogic;
testrst : std_ulogic;
scanen : std_ulogic;
testoen : std_ulogic;
END RECORD;
TYPE apb_slv_out_type IS RECORD
prdata : std_logic_vector ( 31 downto 0 );
pirq : std_logic_vector ( 32 - 1 downto 0 );
pconfig : apb_config_type;
pindex : integer RANGE 0 to 16 - 1;
END RECORD;
TYPE apb_slv_out_vector IS ARRAY ( 0 to 16 - 1 ) OF apb_slv_out_type;
CONSTANT AMBA_CONFIG_VER0 : std_logic_vector ( 1 downto 0 ) := "00";
SUBTYPE amba_vendor_type IS integer RANGE 0 to 16#ff#;
SUBTYPE amba_device_type IS integer RANGE 0 to 16#3ff#;
SUBTYPE amba_version_type IS integer RANGE 0 to 16#3f#;
SUBTYPE amba_cfgver_type IS integer RANGE 0 to 3;
SUBTYPE amba_irq_type IS integer RANGE 0 to 32 - 1;
SUBTYPE ahb_addr_type IS integer RANGE 0 to 16#fff#;
CONSTANT zx : std_logic_vector ( 31 downto 0 ) := ( OTHERS => '0' );
CONSTANT zxirq : std_logic_vector ( 32 - 1 downto 0 ) := ( OTHERS => '0' );
CONSTANT zy : std_logic_vector ( 0 to 31 ) := ( OTHERS => '0' );
TYPE memory_in_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector ( 3 downto 0 );
bwidth : std_logic_vector ( 1 downto 0 );
sd : std_logic_vector ( 63 downto 0 );
cb : std_logic_vector ( 7 downto 0 );
scb : std_logic_vector ( 7 downto 0 );
edac : std_logic;
END RECORD;
TYPE memory_out_type IS RECORD
address : std_logic_vector ( 31 downto 0 );
data : std_logic_vector ( 31 downto 0 );
sddata : std_logic_vector ( 63 downto 0 );
ramsn : std_logic_vector ( 7 downto 0 );
ramoen : std_logic_vector ( 7 downto 0 );
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector ( 3 downto 0 );
iosn : std_logic;
romsn : std_logic_vector ( 7 downto 0 );
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector ( 3 downto 0 );
bdrive : std_logic_vector ( 3 downto 0 );
vbdrive : std_logic_vector ( 31 downto 0 );
svbdrive : std_logic_vector ( 63 downto 0 );
read : std_logic;
sa : std_logic_vector ( 14 downto 0 );
cb : std_logic_vector ( 7 downto 0 );
scb : std_logic_vector ( 7 downto 0 );
vcdrive : std_logic_vector ( 7 downto 0 );
svcdrive : std_logic_vector ( 7 downto 0 );
ce : std_ulogic;
END RECORD;
TYPE sdctrl_in_type IS RECORD
wprot : std_ulogic;
data : std_logic_vector ( 127 downto 0 );
cb : std_logic_vector ( 15 downto 0 );
END RECORD;
TYPE sdctrl_out_type IS RECORD
sdcke : std_logic_vector ( 1 downto 0 );
sdcsn : std_logic_vector ( 1 downto 0 );
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector ( 15 downto 0 );
bdrive : std_ulogic;
qdrive : std_ulogic;
vbdrive : std_logic_vector ( 31 downto 0 );
address : std_logic_vector ( 16 downto 2 );
data : std_logic_vector ( 127 downto 0 );
cb : std_logic_vector ( 15 downto 0 );
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0 );
cal_en : std_logic_vector ( 7 downto 0 );
cal_inc : std_logic_vector ( 7 downto 0 );
cal_rst : std_logic;
odt : std_logic_vector ( 1 downto 0 );
END RECORD;
TYPE sdram_out_type IS RECORD
sdcke : std_logic_vector ( 1 downto 0 );
sdcsn : std_logic_vector ( 1 downto 0 );
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE sdram_cfg_type IS RECORD
command : std_logic_vector ( 2 downto 0 );
csize : std_logic_vector ( 1 downto 0 );
bsize : std_logic_vector ( 2 downto 0 );
trcd : std_ulogic;
trfc : std_logic_vector ( 2 downto 0 );
trp : std_ulogic;
refresh : std_logic_vector ( 11 downto 0 );
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
END RECORD;
TYPE access_param IS RECORD
haddr : std_logic_vector ( 31 downto 0 );
size : std_logic_vector ( 1 downto 0 );
hwrite : std_ulogic;
hio : std_ulogic;
END RECORD;
TYPE ahb_reg_type IS RECORD
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_logic_vector ( 3 downto 0 );
state : ahb_state_type;
haddr : std_logic_vector ( 31 downto 0 );
hrdata : std_logic_vector ( 31 downto 0 );
hwdata : std_logic_vector ( 31 downto 0 );
hwrite : std_ulogic;
htrans : std_logic_vector ( 1 downto 0 );
hresp : std_logic_vector ( 1 downto 0 );
raddr : std_logic_vector ( 6 - 1 downto 0 );
size : std_logic_vector ( 1 downto 0 );
acc : access_param;
END RECORD;
TYPE ddr_reg_type IS RECORD
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector ( 2 downto 0 );
refresh : std_logic_vector ( 11 downto 0 );
sdcsn : std_logic_vector ( 1 downto 0 );
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector ( 15 downto 0 );
address : std_logic_vector ( 15 downto 2 );
ba : std_logic_vector ( 1 downto 0 );
waddr : std_logic_vector ( 6 - 1 downto 0 );
cfg : sdram_cfg_type;
hrdata : std_logic_vector ( 127 downto 0 );
END RECORD;
SIGNAL vcc : std_ulogic;
SIGNAL r : ddr_reg_type;
SIGNAL ri : ddr_reg_type;
SIGNAL ra : ahb_reg_type;
SIGNAL rai : ahb_reg_type;
SIGNAL rbdrive : std_logic_vector ( 31 downto 0 );
SIGNAL ribdrive : std_logic_vector ( 31 downto 0 );
SIGNAL rdata : std_logic_vector ( 127 downto 0 );
SIGNAL wdata : std_logic_vector ( 127 downto 0 );
ATTRIBUTE syn_preserve : boolean;
ATTRIBUTE syn_preserve OF rbdrive : signal IS true;
BEGIN
vcc <= '1';
ahb_ctrl : PROCESS ( rst , ahbsi , r , ra , rdata )
VARIABLE v : ahb_reg_type;
VARIABLE startsd : std_ulogic;
VARIABLE dout : std_logic_vector ( 31 downto 0 );
BEGIN
v := ra;
v.hresp := "00";
v.write := "0000";
CASE ra.raddr ( 1 downto 0 ) IS
WHEN "00" =>
v.hrdata := rdata ( 127 downto 96 );
WHEN "01" =>
v.hrdata := rdata ( 95 downto 64 );
WHEN "10" =>
v.hrdata := rdata ( 63 downto 32 );
WHEN OTHERS =>
v.hrdata := rdata ( 31 downto 0 );
END CASE;
v.ready := not ( ra.startsd xor r.startsdold );
v.ready2 := ra.ready;
IF ( ( ahbsi.hready and ahbsi.hsel ( 3 ) ) = '1' ) THEN
v.htrans := ahbsi.htrans;
v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize ( 1 downto 0 );
v.hwrite := ahbsi.hwrite;
IF ahbsi.htrans ( 1 ) = '1' THEN
v.hio := ahbsi.hmbsel ( 1 );
v.hsel := '1';
v.hready := '0';
END IF;
END IF;
IF ahbsi.hready = '1' THEN
v.hsel := ahbsi.hsel ( 3 );
END IF;
CASE ra.state IS
WHEN midle =>
IF ( ( v.hsel and v.htrans ( 1 ) ) = '1' ) THEN
IF v.hwrite = '0' THEN
v.state := rhold;
v.startsd := not ra.startsd;
ELSE
v.state := dwrite;
v.hready := '1';
v.write := decode ( v.haddr ( 3 downto 2 ) );
END IF;
END IF;
v.raddr := ra.haddr ( 7 downto 2 );
v.ready := '0';
v.ready2 := '0';
IF ahbsi.hready = '1' THEN
v.acc := ( v.haddr , v.size , v.hwrite , v.hio );
END IF;
WHEN rhold =>
v.raddr := ra.haddr ( 7 downto 2 );
IF ra.ready2 = '1' THEN
v.state := dread;
v.hready := '1';
v.raddr := ra.raddr + 1;
END IF;
WHEN dread =>
v.raddr := ra.raddr + 1;
v.hready := '1';
IF ( ( v.hsel and v.htrans ( 1 ) and v.htrans ( 0 ) ) = '0' ) or ( ra.raddr ( 2 downto 0 ) = "000" ) THEN
v.state := midle;
v.hready := '0';
END IF;
v.acc := ( v.haddr , v.size , v.hwrite , v.hio );
WHEN dwrite =>
v.raddr := ra.haddr ( 7 downto 2 );
v.hready := '1';
v.write := decode ( v.haddr ( 3 downto 2 ) );
IF ( ( v.hsel and v.htrans ( 1 ) and v.htrans ( 0 ) ) = '0' ) or ( ra.haddr ( 4 downto 2 ) = "111" ) THEN
v.startsd := not ra.startsd;
v.state := whold1;
v.write := "0000";
v.hready := '0';
END IF;
WHEN whold1 =>
v.state := whold2;
v.ready := '0';
WHEN whold2 =>
IF ra.ready = '1' THEN
v.state := midle;
v.acc := ( v.haddr , v.size , v.hwrite , v.hio );
END IF;
END CASE;
v.hwdata := ahbsi.hwdata;
IF ( ahbsi.hready and ahbsi.hsel ( 3 ) ) = '1' THEN
IF ahbsi.htrans ( 1 ) = '0' THEN
v.hready := '1';
END IF;
END IF;
dout := ra.hrdata ( 31 downto 0 );
IF rst = '0' THEN
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
END IF;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
END PROCESS;
ddr_ctrl : PROCESS ( rst , r , ra , sdi , rbdrive , wdata )
VARIABLE v : ddr_reg_type;
VARIABLE startsd : std_ulogic;
VARIABLE dqm : std_logic_vector ( 15 downto 0 );
VARIABLE raddr : std_logic_vector ( 13 downto 0 );
VARIABLE adec : std_ulogic;
VARIABLE rams : std_logic_vector ( 1 downto 0 );
VARIABLE ba : std_logic_vector ( 1 downto 0 );
VARIABLE haddr : std_logic_vector ( 31 downto 0 );
VARIABLE hsize : std_logic_vector ( 1 downto 0 );
VARIABLE hwrite : std_ulogic;
VARIABLE htrans : std_logic_vector ( 1 downto 0 );
VARIABLE hready : std_ulogic;
VARIABLE vbdrive : std_logic_vector ( 31 downto 0 );
VARIABLE bdrive : std_ulogic;
VARIABLE writecfg : std_ulogic;
VARIABLE regsd1 : std_logic_vector ( 31 downto 0 );
VARIABLE regsd2 : std_logic_vector ( 31 downto 0 );
BEGIN
v := r;
v.hready := '0';
writecfg := '0';
vbdrive := rbdrive;
v.hrdata := sdi.data;
v.qdrive := '0';
regsd1 := ( OTHERS => '0' );
regsd1 ( 31 downto 15 ) := r.cfg.refon & r.cfg.trp & r.cfg.trfc & r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command & r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1 ( 11 downto 0 ) := r.cfg.refresh;
regsd2 := ( OTHERS => '0' );
regsd2 ( 8 downto 0 ) := conv_std_logic_vector ( 90 , 9 );
regsd2 ( 14 downto 12 ) := conv_std_logic_vector ( 3 , 3 );
CASE ra.acc.size IS
WHEN "00" =>
CASE ra.acc.haddr ( 3 downto 0 ) IS
WHEN "0000" =>
dqm := "0111111111111111";
WHEN "0001" =>
dqm := "1011111111111111";
WHEN "0010" =>
dqm := "1101111111111111";
WHEN "0011" =>
dqm := "1110111111111111";
WHEN "0100" =>
dqm := "1111011111111111";
WHEN "0101" =>
dqm := "1111101111111111";
WHEN "0110" =>
dqm := "1111110111111111";
WHEN "0111" =>
dqm := "1111111011111111";
WHEN "1000" =>
dqm := "1111111101111111";
WHEN "1001" =>
dqm := "1111111110111111";
WHEN "1010" =>
dqm := "1111111111011111";
WHEN "1011" =>
dqm := "1111111111101111";
WHEN "1100" =>
dqm := "1111111111110111";
WHEN "1101" =>
dqm := "1111111111111011";
WHEN "1110" =>
dqm := "1111111111111101";
WHEN OTHERS =>
dqm := "1111111111111110";
END CASE;
WHEN "01" =>
CASE ra.acc.haddr ( 3 downto 1 ) IS
WHEN "000" =>
dqm := "0011111111111111";
WHEN "001" =>
dqm := "1100111111111111";
WHEN "010" =>
dqm := "1111001111111111";
WHEN "011" =>
dqm := "1111110011111111";
WHEN "100" =>
dqm := "1111111100111111";
WHEN "101" =>
dqm := "1111111111001111";
WHEN "110" =>
dqm := "1111111111110011";
WHEN OTHERS =>
dqm := "1111111111111100";
END CASE;
WHEN OTHERS =>
dqm := "0000000000000000";
END CASE;
v.startsd := ra.startsd;
CASE r.mstate IS
WHEN midle =>
IF r.startsd = '1' THEN
IF ( r.sdstate = sidle ) and ( r.cfg.command = "000" ) and ( r.cmstate = midle ) THEN
startsd := '1';
v.mstate := active;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
startsd := r.startsd xor r.startsdold;
haddr := ra.acc.haddr;
CASE r.cfg.csize IS
WHEN "00" =>
WHEN "01" =>
WHEN "10" =>
WHEN OTHERS =>
END CASE;
rams := adec & not adec;
IF r.trfc /= "000" THEN
v.trfc := r.trfc - 1;
END IF;
CASE r.sdstate IS
WHEN sidle =>
IF ( startsd = '1' ) and ( r.cfg.command = "000" ) and ( r.cmstate = midle ) and ( r.istate = finish ) THEN
v.address := raddr;
v.ba := ba;
IF ra.acc.hio = '0' THEN
v.sdcsn := not rams ( 1 downto 0 );
v.rasn := '0';
v.sdstate := act1;
ELSE
v.sdstate := ioreg1;
END IF;
END IF;
v.waddr := ra.acc.haddr ( 7 downto 2 );
WHEN act1 =>
v.rasn := '1';
v.trfc := r.cfg.trfc;
IF r.cfg.trcd = '1' THEN
v.sdstate := act2;
ELSE
v.sdstate := act3;
v.hready := ra.acc.hwrite;
END IF;
v.waddr := ra.acc.haddr ( 7 downto 2 );
WHEN act2 =>
v.sdstate := act3;
v.hready := ra.acc.hwrite;
WHEN act3 =>
v.casn := '0';
v.address := ra.acc.haddr ( 15 downto 13 ) & '0' & ra.acc.haddr ( 12 downto 4 ) & '0';
v.dqm := dqm;
IF ra.acc.hwrite = '1' THEN
v.waddr := r.waddr + 4;
v.waddr ( 1 downto 0 ) := "00";
v.sdstate := wr1;
v.sdwen := '0';
v.bdrive := '0';
v.qdrive := '1';
IF ( r.waddr /= ra.raddr ) THEN
v.hready := '1';
IF ( r.waddr ( 5 downto 2 ) = ra.raddr ( 5 downto 2 ) ) THEN
IF r.waddr ( 1 ) = '1' THEN
v.dqm ( 15 downto 8 ) := ( OTHERS => '1' );
ELSE
CASE ra.raddr ( 1 downto 0 ) IS
WHEN "01" =>
v.dqm ( 7 downto 0 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 3 downto 0 ) := ( OTHERS => '1' );
v.dqm ( 15 downto 12 ) := ( OTHERS => r.waddr ( 0 ) );
WHEN OTHERS =>
v.dqm ( 15 downto 12 ) := ( OTHERS => r.waddr ( 0 ) );
END CASE;
END IF;
ELSE
CASE r.waddr ( 1 downto 0 ) IS
WHEN "01" =>
v.dqm ( 15 downto 12 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 15 downto 8 ) := ( OTHERS => '1' );
WHEN "11" =>
v.dqm ( 15 downto 4 ) := ( OTHERS => '1' );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
ELSE
CASE r.waddr ( 1 downto 0 ) IS
WHEN "00" =>
v.dqm ( 11 downto 0 ) := ( OTHERS => '1' );
WHEN "01" =>
v.dqm ( 15 downto 12 ) := ( OTHERS => '1' );
v.dqm ( 7 downto 0 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 15 downto 8 ) := ( OTHERS => '1' );
v.dqm ( 3 downto 0 ) := ( OTHERS => '1' );
WHEN OTHERS =>
v.dqm ( 15 downto 4 ) := ( OTHERS => '1' );
END CASE;
END IF;
ELSE
v.sdstate := rd1;
END IF;
WHEN wr1 =>
v.sdwen := '1';
v.casn := '1';
v.qdrive := '1';
v.waddr := r.waddr + 4;
v.dqm := ( OTHERS => '0' );
v.address ( 8 downto 3 ) := r.waddr;
IF ( r.waddr <= ra.raddr ) and ( r.waddr ( 5 downto 2 ) /= "0000" ) and ( r.hready = '1' ) THEN
v.hready := '1';
IF ( r.hready = '1' ) and ( r.waddr ( 2 downto 0 ) = "000" ) THEN
v.sdwen := '0';
v.casn := '0';
END IF;
IF ( r.waddr ( 5 downto 2 ) = ra.raddr ( 5 downto 2 ) ) and ( r.waddr /= "000000" ) THEN
CASE ra.raddr ( 1 downto 0 ) IS
WHEN "00" =>
v.dqm ( 11 downto 0 ) := ( OTHERS => '1' );
WHEN "01" =>
v.dqm ( 7 downto 0 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 3 downto 0 ) := ( OTHERS => '1' );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
ELSE
v.sdstate := wr2;
v.dqm := ( OTHERS => '1' );
v.startsdold := r.startsd;
END IF;
WHEN wr2 =>
v.sdstate := wr3;
v.qdrive := '1';
WHEN wr3 =>
v.sdstate := wr4a;
v.qdrive := '1';
WHEN wr4a =>
v.bdrive := '1';
v.rasn := '0';
v.sdwen := '0';
v.sdstate := wr4;
v.qdrive := '1';
WHEN wr4 =>
v.sdcsn := "11";
v.rasn := '1';
v.sdwen := '1';
v.qdrive := '0';
v.sdstate := wr5;
WHEN wr5 =>
v.sdstate := sidle;
WHEN rd1 =>
v.casn := '1';
v.sdstate := rd7;
WHEN rd7 =>
v.casn := '1';
v.sdstate := rd2;
WHEN rd2 =>
v.casn := '1';
v.sdstate := rd3;
WHEN rd3 =>
IF 0 = 0 THEN
v.startsdold := r.startsd;
END IF;
v.sdstate := rd4;
v.hready := '1';
v.casn := '1';
IF v.hready = '1' THEN
v.waddr := r.waddr + 4;
END IF;
WHEN rd4 =>
v.hready := '1';
v.casn := '1';
IF ( r.sdcsn = "11" ) or ( r.waddr ( 2 downto 2 ) = "1" ) THEN
v.dqm := ( OTHERS => '1' );
v.burst := '0';
IF 0 /= 0 THEN
v.startsdold := r.startsd;
END IF;
IF ( r.sdcsn /= "11" ) THEN
v.rasn := '0';
v.sdwen := '0';
v.sdstate := rd5;
ELSE
IF r.cfg.trp = '1' THEN
v.sdstate := rd6;
ELSE
v.sdstate := sidle;
END IF;
END IF;
END IF;
IF v.hready = '1' THEN
v.waddr := r.waddr + 4;
END IF;
WHEN rd5 =>
IF r.cfg.trp = '1' THEN
v.sdstate := rd6;
ELSE
v.sdstate := sidle;
END IF;
v.sdcsn := ( OTHERS => '1' );
v.rasn := '1';
v.sdwen := '1';
v.dqm := ( OTHERS => '1' );
WHEN rd6 =>
v.sdstate := sidle;
v.dqm := ( OTHERS => '1' );
v.sdcsn := ( OTHERS => '1' );
v.rasn := '1';
v.sdwen := '1';
WHEN ioreg1 =>
v.hrdata ( 127 downto 64 ) := regsd1 & regsd2;
v.sdstate := ioreg2;
IF ra.acc.hwrite = '0' THEN
v.hready := '1';
END IF;
WHEN ioreg2 =>
writecfg := ra.acc.hwrite and not r.waddr ( 0 );
v.startsdold := r.startsd;
v.sdstate := sidle;
WHEN OTHERS =>
v.sdstate := sidle;
END CASE;
CASE r.cmstate IS
WHEN midle =>
IF r.sdstate = sidle THEN
CASE r.cfg.command IS
WHEN "010" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.sdwen := '0';
v.address ( 12 ) := '1';
v.cmstate := active;
WHEN "100" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.casn := '0';
v.cmstate := active;
WHEN "111" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.casn := '0';
v.sdwen := '0';
v.cmstate := active;
v.ba := "01";
v.address := "00000000000000";
WHEN "110" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.casn := '0';
v.sdwen := '0';
v.cmstate := active;
v.ba := "00";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00010";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
WHEN active =>
v.sdcsn := ( OTHERS => '1' );
v.rasn := '1';
v.casn := '1';
v.sdwen := '1';
v.cfg.command := "000";
v.cmstate := leadout;
v.trfc := r.cfg.trfc;
WHEN OTHERS =>
IF r.trfc = "000" THEN
v.cmstate := midle;
END IF;
END CASE;
CASE r.istate IS
WHEN iidle =>
IF r.cfg.renable = '1' THEN
v.cfg.cke := '1';
v.cfg.dllrst := '1';
IF r.cfg.cke = '1' THEN
v.istate := pre;
v.cfg.command := "010";
END IF;
v.ba := "00";
END IF;
WHEN pre =>
IF r.cfg.command = "000" THEN
v.cfg.command := "11" & r.cfg.dllrst;
IF r.cfg.dllrst = '1' THEN
v.istate := emode;
ELSE
v.istate := lmode;
END IF;
END IF;
WHEN emode =>
IF r.cfg.command = "000" THEN
v.istate := lmode;
v.cfg.command := "110";
END IF;
WHEN lmode =>
IF r.cfg.command = "000" THEN
IF r.cfg.dllrst = '1' THEN
IF r.refresh ( 9 downto 8 ) = "00" THEN
v.cfg.command := "010";
v.istate := ref1;
END IF;
ELSE
v.istate := finish;
v.cfg.refon := '1';
v.cfg.renable := '0';
END IF;
END IF;
WHEN ref1 =>
IF r.cfg.command = "000" THEN
v.cfg.command := "100";
v.cfg.dllrst := '0';
v.istate := ref2;
END IF;
WHEN ref2 =>
IF r.cfg.command = "000" THEN
v.cfg.command := "100";
v.istate := pre;
END IF;
WHEN OTHERS =>
IF r.cfg.renable = '1' THEN
v.istate := iidle;
v.cfg.dllrst := '1';
END IF;
END CASE;
CASE r.mstate IS
WHEN active =>
IF v.hready = '1' THEN
v.mstate := midle;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF ( ( r.cfg.refon = '1' ) and ( r.istate = finish ) ) or ( r.cfg.dllrst = '1' ) THEN
v.refresh := r.refresh - 1;
IF ( v.refresh ( 11 ) and not r.refresh ( 11 ) ) = '1' THEN
v.refresh := r.cfg.refresh;
IF r.cfg.dllrst = '0' THEN
v.cfg.command := "100";
END IF;
END IF;
END IF;
IF ( ra.acc.hio and ra.acc.hwrite and writecfg ) = '1' THEN
v.cfg.refresh := wdata ( 11 + 96 downto 0 + 96 );
v.cfg.cke := wdata ( 15 + 96 );
v.cfg.renable := wdata ( 16 + 96 );
v.cfg.dllrst := wdata ( 17 + 96 );
v.cfg.command := wdata ( 20 + 96 downto 18 + 96 );
v.cfg.csize := wdata ( 22 + 96 downto 21 + 96 );
v.cfg.bsize := wdata ( 25 + 96 downto 23 + 96 );
v.cfg.trcd := wdata ( 26 + 96 );
v.cfg.trfc := wdata ( 29 + 96 downto 27 + 96 );
v.cfg.trp := wdata ( 30 + 96 );
v.cfg.refon := wdata ( 31 + 96 );
END IF;
v.nbdrive := not v.bdrive;
IF 0 = 1 THEN
bdrive := r.nbdrive;
vbdrive := ( OTHERS => v.nbdrive );
ELSE
bdrive := r.bdrive;
vbdrive := ( OTHERS => v.bdrive );
END IF;
IF rst = '0' THEN
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector ( 9 - 9 , 2 );
v.cfg.bsize := conv_std_logic_vector ( log2 ( 256 / 8 ) , 3 );
IF 90 > 100 THEN
v.cfg.trcd := '1';
ELSE
v.cfg.trcd := '0';
END IF;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector ( 75 * 90 / 1000 - 2 , 3 );
v.cfg.refresh := conv_std_logic_vector ( 7800 * 90 / 1000 , 12 );
v.refresh := ( OTHERS => '0' );
IF 1 = 1 THEN
v.cfg.renable := '1';
ELSE
v.cfg.renable := '0';
END IF;
IF 90 > 100 THEN
v.cfg.trp := '1';
ELSE
v.cfg.trp := '0';
END IF;
v.dqm := ( OTHERS => '1' );
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
END IF;
ri <= v;
ribdrive <= vbdrive;
END PROCESS;
sdo.sdcke <= ( OTHERS => r.cfg.cke );
ahbso.hconfig <= ( 0 => AHB_DEVICE_REG ( VENDOR_GAISLER , GAISLER_DDRSP , 0 , 0 , 0 ) , 4 => AHB_MEMBAR ( 1024 , '1' , '1' , 3072 ) , 5 => AHB_IOBAR ( 1 , 4095 ) , OTHERS => ZERO32 );
ahbso.hirq <= ( OTHERS => '0' );
ahbso.hindex <= 3;
ahbregs : PROCESS ( clk_ahb )
BEGIN
IF rising_edge ( clk_ahb ) THEN
ra <= rai;
END IF;
END PROCESS;
ddrregs : PROCESS ( clk_ddr , rst )
BEGIN
IF rising_edge ( clk_ddr ) THEN
r <= ri;
rbdrive <= ribdrive;
END IF;
IF ( rst = '0' ) THEN
r.sdcsn <= ( OTHERS => '1' );
r.bdrive <= '1';
r.nbdrive <= '0';
IF 0 = 0 THEN
rbdrive <= ( OTHERS => '1' );
ELSE
rbdrive <= ( OTHERS => '0' );
END IF;
r.cfg.cke <= '0';
END IF;
END PROCESS;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive WHEN 0 = 1 ELSE r.bdrive;
sdo.qdrive <= not ( ri.qdrive or r.nbdrive );
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= wdata;
read_buff : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 128 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ahb , renable => vcc , raddress => rai.raddr ( 5 downto 2 ) , dataout => rdata , wclk => clk_ddr , write => ri.hready , waddress => r.waddr ( 5 downto 2 ) , datain => ri.hrdata
)
;
write_buff1 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 127 downto 96 ) , wclk => clk_ahb , write => ra.write ( 0 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
write_buff2 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 95 downto 64 ) , wclk => clk_ahb , write => ra.write ( 1 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
write_buff3 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 63 downto 32 ) , wclk => clk_ahb , write => ra.write ( 2 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
write_buff4 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 31 downto 0 ) , wclk => clk_ahb , write => ra.write ( 3 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
bootmsg : COMPONENT report_version
GENERIC MAP (
msg1 => "ddrsp" & tost ( 3 ) & ": 64-bit DDR266 controller rev " & tost ( 0 ) & ", " & tost ( 256 ) & " Mbyte, " & tost ( 90 ) & " MHz DDR clock"
)
;
END ARCHITECTURE;
| mit | 1dd68719fd7d67e86d5fc730c8ce0d07 | 0.425939 | 4.088291 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/buffered_spi_tb.vhd | 3 | 5,837 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21.09.2020 23:17:28
-- Design Name:
-- Module Name: buffered_spi_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity buffered_spi_tb is
-- Port ( );
end buffered_spi_tb;
architecture Behavioral of buffered_spi_tb is
component buffered_spi is
Port ( clock : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC;
spi_clk : out STD_LOGIC;
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC);
end component;
signal clock : std_logic := '0';
signal avalon_read : std_logic := '0';
signal avalon_write : std_logic := '0';
signal avalon_waitrequest : std_logic := '0';
signal avalon_address : std_logic_vector(13 downto 0) := (others => '0');
signal avalon_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdatavalid : std_logic := '0';
signal spi_mosi : std_logic := '0';
signal spi_clk : std_logic := '0';
signal spi_miso : std_logic := '0';
signal spi_cs : std_logic := '0';
procedure write_avalon_16 (addry : in std_logic_vector(13 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic
) is
begin
Ava_Ad <= addry;
Ava_Da <= datty;
wait for 10ns;
Ava_Wri <= '1';
wait for 10ns;
Ava_Wri <= '0';
wait for 10ns;
end write_avalon_16;
procedure read_avalon_16 (addry : in std_logic_vector(13 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Re : out std_logic
) is
begin
Ava_Ad <= addry;
wait for 10ns;
Ava_Re <= '1';
wait for 10ns;
Ava_Re <= '0';
wait for 10ns;
end read_avalon_16;
begin
--clock <= not clock after 4310 ps; --116 MHz clock
clock <= not clock after 5000 ps; --100 MHz clock
UUT: buffered_spi
port map(
clock => clock,
avalon_read => avalon_read,
avalon_write => avalon_write,
avalon_address => avalon_address,
avalon_waitrequest => avalon_waitrequest,
avalon_writedata => avalon_writedata,
avalon_readdata => avalon_readdata,
avalon_readdatavalid => avalon_readdatavalid,
spi_mosi => spi_mosi,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_cs => spi_cs
);
process
begin
wait for 500ns;
--write
write_avalon_16("10"&X"001",X"0200",avalon_address,avalon_writedata,avalon_write); --len
wait for 100ns;
write_avalon_16("10"&X"003",X"0000",avalon_address,avalon_writedata,avalon_write); --cs
wait for 100ns;
write_avalon_16("10"&X"004",X"0000",avalon_address,avalon_writedata,avalon_write); --delay
wait for 100ns;
write_avalon_16("10"&X"005",X"0000",avalon_address,avalon_writedata,avalon_write); --bufselect
wait for 100ns;
for i in 0 to 511 loop
write_avalon_16(std_logic_vector(to_unsigned(i,14)),std_logic_vector(to_unsigned(i*3,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+2048,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+4096,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+6144,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
end loop;
wait for 100ns;
--read
wait for 500ns;
read_avalon_16("00"&X"312",avalon_address,avalon_read);
wait for 500ns;
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
--toggle miso
for i in 0 to 5000 loop
spi_miso <= not spi_miso;
wait for 320ns;
end loop;
--switch to buf2
write_avalon_16("10"&X"005",X"0001",avalon_address,avalon_writedata,avalon_write); --bufselect
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
wait;
end process;
end Behavioral;
| gpl-2.0 | 4e65d4a50f6cfbdf91ef22f7f7274310 | 0.558163 | 3.715468 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/ssrctrl_net.vhd | 2 | 12,187 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ssrctrl_net
-- file: ssrctrl_net.vhd
-- Description: Wrapper for SSRAM controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ssrctrl_net is
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end entity ssrctrl_net;
architecture rtl of ssrctrl_net is
component ssrctrl_unisim
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
begin
xil : if ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)) and bus16=1 generate
ssrctrlxil: ssrctrl_unisim
port map(
rst => rst,
clk => clk,
n_ahbsi_hsel => n_ahbsi_hsel,
n_ahbsi_haddr => n_ahbsi_haddr,
n_ahbsi_hwrite => n_ahbsi_hwrite,
n_ahbsi_htrans => n_ahbsi_htrans,
n_ahbsi_hsize => n_ahbsi_hsize,
n_ahbsi_hburst => n_ahbsi_hburst,
n_ahbsi_hwdata => n_ahbsi_hwdata,
n_ahbsi_hprot => n_ahbsi_hprot,
n_ahbsi_hready => n_ahbsi_hready,
n_ahbsi_hmaster => n_ahbsi_hmaster,
n_ahbsi_hmastlock => n_ahbsi_hmastlock,
n_ahbsi_hmbsel => n_ahbsi_hmbsel,
n_ahbsi_hcache => n_ahbsi_hcache,
n_ahbsi_hirq => n_ahbsi_hirq,
n_ahbso_hready => n_ahbso_hready,
n_ahbso_hresp => n_ahbso_hresp,
n_ahbso_hrdata => n_ahbso_hrdata,
n_ahbso_hsplit => n_ahbso_hsplit,
n_ahbso_hcache => n_ahbso_hcache,
n_ahbso_hirq => n_ahbso_hirq,
n_apbi_psel => n_apbi_psel,
n_apbi_penable => n_apbi_penable,
n_apbi_paddr => n_apbi_paddr,
n_apbi_pwrite => n_apbi_pwrite,
n_apbi_pwdata => n_apbi_pwdata,
n_apbi_pirq => n_apbi_pirq,
n_apbo_prdata => n_apbo_prdata,
n_apbo_pirq => n_apbo_pirq,
n_sri_data => n_sri_data,
n_sri_brdyn => n_sri_brdyn,
n_sri_bexcn => n_sri_bexcn,
n_sri_writen => n_sri_writen,
n_sri_wrn => n_sri_wrn,
n_sri_bwidth => n_sri_bwidth,
n_sri_sd => n_sri_sd,
n_sri_cb => n_sri_cb,
n_sri_scb => n_sri_scb,
n_sri_edac => n_sri_edac,
n_sro_address => n_sro_address,
n_sro_data => n_sro_data,
n_sro_sddata => n_sro_sddata,
n_sro_ramsn => n_sro_ramsn,
n_sro_ramoen => n_sro_ramoen,
n_sro_ramn => n_sro_ramn,
n_sro_romn => n_sro_romn,
n_sro_mben => n_sro_mben,
n_sro_iosn => n_sro_iosn,
n_sro_romsn => n_sro_romsn,
n_sro_oen => n_sro_oen,
n_sro_writen => n_sro_writen,
n_sro_wrn => n_sro_wrn,
n_sro_bdrive => n_sro_bdrive,
n_sro_vbdrive => n_sro_vbdrive,
n_sro_svbdrive => n_sro_svbdrive,
n_sro_read => n_sro_read,
n_sro_sa => n_sro_sa,
n_sro_cb => n_sro_cb,
n_sro_scb => n_sro_scb,
n_sro_vcdrive => n_sro_vcdrive,
n_sro_svcdrive => n_sro_svcdrive,
n_sro_ce => n_sro_ce);
end generate;
-- pragma translate_off
nonet : if not (((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)))
generate
err : process
begin
assert False report "ERROR : No ssrctrl netlist available for this technology!"
severity Failure;
wait;
end process;
end generate;
nobus16 : if not ( bus16=1 )
generate
err : process
begin
assert False report "ERROR : 16-bit PROM bus option not selected for ssrctrl netlist!"
severity Failure;
wait;
end process;
end generate;
-- pragma translate_on
end architecture; | mit | 6d2629a34a19b86bfbd9c4069ffee089 | 0.520965 | 3.323425 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/leon3cg.vhd | 2 | 7,807 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3cg
-- File: leon3cg.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: Top-level LEON3 component with clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
library techmap;
use techmap.gencomp.all;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libproc3.all;
use gaisler.arith.all;
--library fpu;
--use fpu.libfpu.all;
entity leon3cg is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic; -- AHB clock (free-running)
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic -- gated clock
);
end;
architecture rtl of leon3cg is
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := fpu / 16;
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal rd1, rd2, wd : std_logic_vector(35 downto 0);
signal gnd, vcc : std_logic;
attribute sync_set_reset : string;
attribute sync_set_reset of rst : signal is "true";
constant FPURFHARD : integer := 1-is_fpga(memtech);
begin
gnd <= '0'; vcc <= '1';
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (hindex, fabtech, memtech, nwindows, dsu, fpuarch, v8, cp, mac,
pclow, notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock,
dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp, cached, 0, scantest)
port map (gclk, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, gnd, clk, vcc);
-- IU register file
rf0 : regfile_3p generic map (memtech, IRFBITS, 32, 1, IREGNUM)
port map (gclk, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
gclk, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2);
-- cache memory
cmem0 : cachemem
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen)
port map (gclk, crami, cramo, clk);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem0 : tbufmem
generic map (tech => memtech, tbuf => tbuf)
port map (gclk, tbi, tbo);
end generate;
-- FPU
fpu0 : if (fpu = 0) generate fpo.ldlock <= '0'; fpo.ccv <= '1'; fpo.holdn <= '1'; end generate;
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwx
generic map (FPURFHARD*fabtech, FPURFHARD*memtech, (fpuarch-1), pclow, dsu, disas, fpunet)
port map (rst, gclk, holdn, fpi, fpo);
end generate;
mfpw0gen : if (fpuarch = 15) generate
fpu0 : mfpwx
generic map (FPURFHARD*memtech, pclow, dsu, disas)
port map (rst, gclk, holdn, fpi, fpo);
end generate;
grlfpc0gen : if (fpuarch >= 8) and (fpuarch < 15) generate
fpu0 : grlfpwx
generic map (FPURFHARD*memtech, pclow, dsu, disas, (fpuarch-8))
port map (rst, gclk, holdn, fpi, fpo);
end generate;
-- 1-clock reset delay
rstreg : process(gclk)
begin if rising_edge(gclk) then rst <= rstn; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3CG SPARC V8 processor rev " & tost(LEON3_VERSION),
"leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
| mit | cfe94d14d273e5ea42fb26a798662f54 | 0.586141 | 3.466696 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | pair_remover/iu3BaseDCE2.vhd | 1 | 590,183 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(123 downto 0);
signal or_reduce_1 : std_logic;
signal dfp_delay_start : integer range 0 to 15;
signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right);
signal handlerTrap : std_ulogic;
-- Signals that serve as shadow signals for variables used in the pairs
signal V_A_ET_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow : STD_LOGIC_VECTOR(4 downto 3);
signal ICNT_shadow : STD_ULOGIC;
signal EX_OP1_shadow : WORD;
signal V_M_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal DE_REN1_shadow : STD_ULOGIC;
signal DE_INST_shadow : WORD;
signal V_A_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_W_S_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_RESULT6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_E_ALUCIN_shadow : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_A_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_RESULT1DOWNTO0_shadow : std_logic_vector(1 downto 0);
signal EX_SHCNT_shadow : ASI_TYPE;
signal V_M_DCI_SIZE_shadow : OP_TYPE;
signal V_X_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_MEXC_shadow : STD_ULOGIC;
signal TBUFCNTX_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_A_CTRL_WY_shadow : STD_ULOGIC;
signal NPC_shadow : PCTYPE;
signal V_M_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_MULSTART_shadow : STD_ULOGIC;
signal XC_VECTT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_TT_shadow : OP3_TYPE;
signal DSIGN_shadow : STD_ULOGIC;
signal V_E_CTRL_ANNUL_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow : PCTYPE;
signal V_A_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_RFE1_shadow : STD_ULOGIC;
signal V_W_WA_shadow : RFATYPE;
signal V_X_ANNUL_ALL_shadow : STD_ULOGIC;
signal EX_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES_shadow : STD_LOGIC_VECTOR(32 downto 0);
signal VIR_ADDR_shadow : PCTYPE;
signal EX_JUMP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_CWP_shadow : CWPTYPE;
signal V_D_INST0_shadow : std_logic_vector(31 downto 0);
signal V_A_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_DATA1_shadow : std_logic_vector(31 downto 0);
signal VP_PWD_shadow : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA00_shadow : STD_LOGIC;
signal V_M_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_PS_shadow : STD_ULOGIC;
signal V_X_CTRL_TT_shadow : OP3_TYPE;
signal V_D_STEP_shadow : STD_ULOGIC;
signal V_X_CTRL_WICC_shadow : STD_ULOGIC;
signal VIR_ADDR31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_X_RESULT_shadow : WORD;
signal V_D_CNT_shadow : OP_TYPE;
signal XC_VECTT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_W_S_EF_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow : std_logic_vector(4 downto 0);
signal V_X_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_M_NALIGN_shadow : STD_ULOGIC;
signal XC_WREG_shadow : STD_ULOGIC;
signal V_A_RFA2_shadow : RFATYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow : STD_LOGIC_VECTOR(32 downto 13);
signal EX_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_SU_shadow : STD_ULOGIC;
signal V_E_OP2_shadow : WORD;
signal EX_FORCE_A2_shadow : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_OP131_shadow : STD_LOGIC;
signal V_X_DCI_shadow : DC_IN_TYPE;
signal V_E_CTRL_WICC_shadow : STD_ULOGIC;
signal EX_OP13_shadow : STD_LOGIC;
signal V_F_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST_shadow : WORD;
signal V_E_CTRL_LD_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
signal V_E_SARI_shadow : STD_ULOGIC;
signal V_E_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_PV_shadow : STD_ULOGIC;
signal VDSU_CRDY2_shadow : STD_LOGIC;
signal MUL_OP2_shadow : WORD;
signal XC_EXCEPTION_shadow : STD_ULOGIC;
signal V_E_OP1_shadow : WORD;
signal VP_ERROR_shadow : STD_ULOGIC;
signal V_M_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal MUL_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_M_DCI_shadow : DC_IN_TYPE;
signal EX_OP23_shadow : STD_LOGIC;
signal V_X_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_A_DIVSTART_shadow : STD_ULOGIC;
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal VDSU_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_CTRL_CNT_shadow : OP_TYPE;
signal V_E_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_RFE2_shadow : STD_ULOGIC;
signal V_E_OP13_shadow : STD_LOGIC;
signal V_A_CWP_shadow : CWPTYPE;
signal ME_SIZE_shadow : OP_TYPE;
signal V_X_MAC_shadow : STD_ULOGIC;
signal V_M_CTRL_INST_shadow : WORD;
signal VIR_ADDR31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST20_shadow : STD_LOGIC;
signal DE_REN2_shadow : STD_ULOGIC;
signal V_E_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_MAC_shadow : STD_ULOGIC;
signal V_X_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal EX_ADD_RES3_shadow : STD_LOGIC;
signal V_X_CTRL_INST_shadow : WORD;
signal V_M_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow : OP_TYPE;
signal V_M_CTRL_ANNUL_shadow : STD_ULOGIC;
signal DE_INST19_shadow : STD_LOGIC;
signal XC_HALT_shadow : STD_ULOGIC;
signal V_E_OP231_shadow : STD_LOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_M_CTRL_WICC_shadow : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow : STD_ULOGIC;
signal V_W_S_S_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CWP_shadow : CWPTYPE;
signal V_A_STEP_shadow : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_CTRL_TRAP_shadow : STD_ULOGIC;
signal NPC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_INTACK_shadow : STD_ULOGIC;
signal SIDLE_shadow : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_DATA03_shadow : STD_LOGIC;
signal V_A_CTRL_INST19_shadow : STD_LOGIC;
signal V_W_S_SVT_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_LADDR_shadow : OP_TYPE;
signal V_W_S_DWT_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_TBA_shadow : STD_LOGIC_VECTOR(19 downto 0);
signal XC_WADDR6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_M_MUL_shadow : STD_ULOGIC;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_Y31_shadow : STD_LOGIC;
signal V_E_OP23_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal DE_RADDR17DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_X_DEBUG_shadow : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_CTRL_WREG_shadow : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow : STD_LOGIC;
signal V_D_MEXC_shadow : STD_ULOGIC;
signal V_W_RESULT_shadow : WORD;
signal VFPI_DBG_ENABLE_shadow : STD_ULOGIC;
signal EX_OP131_shadow : STD_LOGIC;
signal V_D_INST1_shadow : std_logic_vector(31 downto 0);
signal V_W_EXCEPT_shadow : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal ME_LADDR_shadow : OP_TYPE;
signal V_X_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_CTRL_RETT_shadow : STD_ULOGIC;
signal XC_WADDR7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_M_MAC_shadow : STD_ULOGIC;
signal V_D_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal VIR_ADDR3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_D_CWP_shadow : CWPTYPE;
signal DE_INST20_shadow : STD_LOGIC;
signal V_D_ANNUL_shadow : STD_ULOGIC;
signal EX_OP2_shadow : WORD;
signal EX_SARI_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DCI_SIZE_shadow : OP_TYPE;
signal V_M_Y_shadow : WORD;
signal V_X_CTRL_PC_shadow : PCTYPE;
signal V_X_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal V_A_CTRL_PC_shadow : PCTYPE;
signal V_A_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_INST20_shadow : STD_LOGIC;
signal V_E_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA0_shadow : std_logic_vector(31 downto 0);
signal V_E_CTRL_INST19_shadow : STD_LOGIC;
signal ME_SIGNED_shadow : STD_ULOGIC;
signal V_W_WREG_shadow : STD_ULOGIC;
signal V_D_PC_shadow : PCTYPE;
signal VFPI_D_ANNUL_shadow : STD_ULOGIC;
signal DE_RADDR27DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC_shadow : PCTYPE;
signal V_X_DATA031_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_X_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT_shadow : OP3_TYPE;
signal V_X_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_INST24_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_NERROR_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_W_S_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_F_BRANCH_shadow : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow : STD_ULOGIC;
signal V_A_CTRL_LD_shadow : STD_ULOGIC;
signal V_A_CTRL_TT_shadow : OP3_TYPE;
signal V_M_CTRL_LD_shadow : STD_ULOGIC;
signal V_E_SHCNT_shadow : ASI_TYPE;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST_shadow : WORD;
signal V_A_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal VIR_PWD_shadow : STD_ULOGIC;
signal XC_RESULT_shadow : WORD;
signal V_A_RFA1_shadow : RFATYPE;
signal V_E_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal ME_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal DE_INST24_shadow : STD_LOGIC;
signal XC_TRAP_shadow : STD_ULOGIC;
signal VDSU_TBUFCNT_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal XC_TRAP_ADDRESS_shadow : PCTYPE;
-- Intermediate value holding signal declarations
signal V_E_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal V_M_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_RFA1_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_4 : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_2 : STD_LOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal V_X_DATA00_shadow_intermed_3 : STD_LOGIC;
signal RIN_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WICC_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_3 : STD_ULOGIC;
signal RPIN_PWD_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal DE_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DBGI_DADDR9DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(9 downto 2);
signal R_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_STEP_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_7 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_1 : STD_LOGIC;
signal V_D_INST0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_YMSB_intermed_1 : STD_ULOGIC;
signal R_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_X_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_F_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_DATA04DOWNTO0_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal R_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal R_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal RIN_M_DCI_LOCK_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal R_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_ET_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal DBGI_STEP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_X_LADDR_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_WA_intermed_1 : std_logic_vector(7 downto 0);
signal V_D_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_2 : STD_LOGIC;
signal V_M_RESULT1DOWNTO0_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_DATA03_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_intermed_1 : DC_IN_TYPE;
signal DSUIN_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_D_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal ICO_MEXC_intermed_1 : STD_ULOGIC;
signal R_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_DCI_SIZE_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_W_S_S_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal R_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_S_ET_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal VIR_ADDR31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_8 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_X_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal DCO_DATA00_intermed_2 : STD_LOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal R_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_X_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_X_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal IR_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_X_DATA1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal ICO_MEXC_intermed_3 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal R_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_WICC_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_5 : STD_ULOGIC;
signal RIN_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal R_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_M_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_7 : std_logic_vector(31 downto 4);
signal RIN_E_OP13_intermed_1 : STD_LOGIC;
signal RIN_A_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_OP2_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal R_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_M_Y31_intermed_2 : STD_LOGIC;
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal XC_VECTT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_4 : STD_ULOGIC;
signal RIN_W_S_TBA_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal V_D_INST1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DATA031_intermed_1 : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 13);
signal R_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_X_DATA031_intermed_1 : STD_LOGIC;
signal R_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_SARI_intermed_1 : STD_ULOGIC;
signal R_M_Y31_intermed_1 : STD_LOGIC;
signal IR_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_W_S_S_shadow_intermed_2 : STD_ULOGIC;
signal DE_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal V_A_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow_intermed_2 : std_logic_vector(4 downto 0);
signal R_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal DCO_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_X_DATA0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_E_OP131_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST19_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal V_X_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_RFE2_shadow_intermed_1 : STD_ULOGIC;
signal V_M_Y_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal DE_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_MEXC_shadow_intermed_4 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_W_S_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal R_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal IR_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal R_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow_intermed_1 : STD_ULOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_X_DATA04DOWNTO0_intermed_3 : std_logic_vector(4 downto 0);
signal V_X_NERROR_shadow_intermed_1 : STD_ULOGIC;
signal V_A_RFE1_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal ICO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal VIR_ADDR_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_W_S_DWT_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_X_NERROR_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_5 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal IRIN_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal V_X_DATA00_shadow_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_M_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal R_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_DEBUG_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PV_intermed_4 : STD_ULOGIC;
signal R_E_MAC_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal IR_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_JMPL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal RIN_M_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_X_DATA04DOWNTO0_shadow_intermed_3 : std_logic_vector(4 downto 0);
signal RIN_W_S_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_DATA031_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_3 : STD_LOGIC;
signal DCO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_X_DATA0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 : std_logic_vector(3 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RPIN_ERROR_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_W_S_S_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal V_A_RFA1_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_CTRL_shadow_intermed_3 : PIPELINE_CTRL_TYPE;
signal R_D_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_1 : STD_LOGIC;
signal V_A_DIVSTART_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_4 : STD_ULOGIC;
signal RIN_W_S_PS_intermed_1 : STD_ULOGIC;
signal R_D_MEXC_intermed_3 : STD_ULOGIC;
signal RIN_A_RFA2_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_W_S_SVT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_4 : std_logic_vector(6 downto 0);
signal RIN_E_OP23_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_D_MEXC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_7 : std_logic_vector(31 downto 4);
signal R_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_8 : std_logic_vector(31 downto 12);
signal VP_PWD_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_NALIGN_intermed_1 : STD_ULOGIC;
signal RP_ERROR_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_W_S_TBA_shadow_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal R_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_JMPL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_RFE2_intermed_1 : STD_ULOGIC;
signal RIN_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_M_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_E_MAC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal IRIN_ADDR_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_CWP_shadow_intermed_2 : std_logic_vector(2 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_A_MULSTART_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_M_DCI_SIGNED_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal IRIN_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal V_M_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_DCI_SIGNED_shadow_intermed_2 : STD_ULOGIC;
signal R_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST19_intermed_3 : STD_LOGIC;
signal V_E_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_X_DATA1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_CWP_intermed_2 : std_logic_vector(2 downto 0);
signal R_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_A_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal DCO_DATA031_intermed_2 : STD_LOGIC;
signal R_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_E_YMSB_shadow_intermed_1 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_M_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DE_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal VIR_ADDR3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_3 : PIPELINE_CTRL_TYPE;
signal RIN_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_A_DIVSTART_intermed_1 : STD_ULOGIC;
signal VIR_ADDR31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_X_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal DSUR_CRDY2_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST_intermed_4 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal DE_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_MULSTART_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_M_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 3);
signal V_A_CTRL_PV_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_WREG_shadow_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_W_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal R_D_ANNUL_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_E_SARI_shadow_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal R_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_M_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal DSUIN_CRDY2_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_M_DCI_SIZE_intermed_2 : std_logic_vector(1 downto 0);
signal DE_INST19_shadow_intermed_3 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_ANNUL_shadow_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal IRIN_PWD_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_5 : STD_ULOGIC;
signal RIN_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TRAP_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal R_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_DATA03_intermed_1 : STD_LOGIC;
signal R_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal R_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_X_MAC_intermed_1 : STD_ULOGIC;
signal V_E_SHCNT_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_OP23_shadow_intermed_1 : STD_LOGIC;
signal V_D_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal R_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_W_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_LADDR_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_5 : std_logic_vector(31 downto 2);
signal XC_VECTT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal V_D_STEP_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal DE_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_5 : STD_ULOGIC;
signal RIN_X_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_F_BRANCH_intermed_1 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_DATA00_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_JMPL_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal DSUR_CRDY2_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA00_intermed_3 : STD_LOGIC;
signal R_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_OP131_intermed_1 : STD_LOGIC;
signal R_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal DE_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_ET_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST20_intermed_3 : STD_LOGIC;
signal RIN_W_EXCEPT_intermed_1 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_2 : STD_LOGIC;
signal R_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal R_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal VIR_ADDR31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_M_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal VIR_ADDR3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_ANNUL_shadow_intermed_3 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal R_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal R_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_E_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST24_intermed_3 : STD_LOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal DE_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PV_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal R_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_MAC_intermed_1 : STD_ULOGIC;
signal R_X_DATA00_intermed_2 : STD_LOGIC;
signal RIN_E_MAC_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_INTACK_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_ANNUL_intermed_5 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_X_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal DE_INST20_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal IR_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_ALUCIN_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_E_OP13_shadow_intermed_1 : STD_LOGIC;
signal V_A_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_6 : std_logic_vector(3 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_7 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal R_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal R_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_WREG_intermed_4 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal R_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal IRIN_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_OP1_intermed_1 : std_logic_vector(31 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal DE_INST20_shadow_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_E_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_M_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_INTACK_intermed_1 : STD_ULOGIC;
signal RIN_E_OP231_intermed_1 : STD_LOGIC;
signal RIN_X_DATA031_intermed_3 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_F_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_ET_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_3 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal ICO_MEXC_intermed_2 : STD_ULOGIC;
signal V_X_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_STEP_intermed_1 : STD_ULOGIC;
signal V_E_ALUCIN_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_M_MUL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal R_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_D_INST0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DCO_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO12_shadow_intermed_8 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WY_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal V_M_DCI_shadow_intermed_1 : DC_IN_TYPE;
signal V_M_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal RIN_D_MEXC_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DSUIN_TBUFCNT_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 : std_logic_vector(6 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal V_D_INST1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DEBUG_intermed_1 : STD_ULOGIC;
signal RIN_M_Y_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_SHCNT_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal RIN_D_ANNUL_intermed_2 : STD_ULOGIC;
signal ICO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_MEXC_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal DSUIN_CRDY2_intermed_2 : STD_LOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_DATA031_shadow_intermed_1 : STD_LOGIC;
signal RIN_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_D_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal DCO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_S_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_LD_shadow_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal V_E_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_F_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO2_shadow_intermed_8 : std_logic_vector(31 downto 2);
signal V_D_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal R_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_M_RESULT1DOWNTO0_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_5 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal V_X_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_5 : std_logic_vector(1 downto 0);
signal R_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_W_S_S_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_A_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal R_X_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_intermed_1 : DC_IN_TYPE;
signal R_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_EF_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_LD_intermed_3 : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal V_F_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 : STD_LOGIC_VECTOR(30 downto 11);
signal V_X_ANNUL_ALL_shadow_intermed_3 : STD_ULOGIC;
signal V_F_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal R_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RETT_intermed_3 : STD_ULOGIC;
signal R_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 3);
signal V_E_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_E_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal V_A_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_OP231_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RPIN_ERROR_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_D_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal DCO_DATA00_intermed_1 : STD_LOGIC;
signal V_M_Y31_shadow_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal DCO_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_DATA03_shadow_intermed_1 : STD_LOGIC;
signal V_E_OP1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal V_M_Y31_shadow_intermed_2 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal R_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_RFE1_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_M_MAC_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal R_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_DATA00_intermed_1 : STD_LOGIC;
signal V_X_ANNUL_ALL_shadow_intermed_1 : STD_ULOGIC;
signal R_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_F_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_W_S_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_W_S_PS_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal R_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_MAC_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_ICC_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_MAC_intermed_1 : STD_ULOGIC;
signal RIN_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal R_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 13);
signal RIN_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal IR_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_2 : STD_LOGIC;
signal RIN_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_E_OP2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap or handlerTrap;
v.x.nerror := rp.error;
if(handlerTrap = '1')then
xc_vectt := "00" & TT_WATCH;
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif false and false and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if true then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if false then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not true) and (r.w.s.cwp = "000") then v.w.s.cwp := "111";
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
end if;
if true then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if true then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(7 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.w.s.ef := '0'; -- needed for AX
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := "000";
v.w.s.icc := "0000";
end if;
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := "00000000"; end if;
if true then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to 2-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if false and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if 0 = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000",
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if 2 > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000"; de_raddr2 := "0000000000";
if true then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if true then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2); de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := "000";
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000"; v.f.branch := '0';
if false then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to 2-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(0 downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if true then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if false then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if true then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if true then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
V_A_ET_shadow <= V.A.ET;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 4 DOWNTO 3 );
ICNT_shadow <= ICNT;
EX_OP1_shadow <= EX_OP1;
V_M_CTRL_PC_shadow <= V.M.CTRL.PC;
V_E_CTRL_PC3DOWNTO2_shadow <= V.E.CTRL.PC( 3 DOWNTO 2 );
DE_REN1_shadow <= DE_REN1;
DE_INST_shadow <= DE_INST;
V_A_CTRL_CNT_shadow <= V.A.CTRL.CNT;
V_F_PC3DOWNTO2_shadow <= V.F.PC( 3 DOWNTO 2 );
V_W_S_TT_shadow <= V.W.S.TT;
V_X_RESULT6DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 );
EX_JUMP_ADDRESS3DOWNTO2_shadow <= EX_JUMP_ADDRESS( 3 DOWNTO 2 );
V_E_ALUCIN_shadow <= V.E.ALUCIN;
V_D_PC3DOWNTO2_shadow <= V.D.PC( 3 DOWNTO 2 );
V_A_CTRL_PV_shadow <= V.A.CTRL.PV;
V_E_CTRL_shadow <= V.E.CTRL;
V_M_CTRL_shadow <= V.M.CTRL;
V_M_RESULT1DOWNTO0_shadow <= V.M.RESULT ( 1 DOWNTO 0 );
EX_SHCNT_shadow <= EX_SHCNT;
V_M_DCI_SIZE_shadow <= V.M.DCI.SIZE;
V_X_CTRL_ANNUL_shadow <= V.X.CTRL.ANNUL;
V_X_MEXC_shadow <= V.X.MEXC;
TBUFCNTX_shadow <= TBUFCNTX;
V_A_CTRL_WY_shadow <= V.A.CTRL.WY;
NPC_shadow <= NPC;
V_M_CTRL_TT3DOWNTO0_shadow <= V.M.CTRL.TT( 3 DOWNTO 0 );
V_A_MULSTART_shadow <= V.A.MULSTART;
XC_VECTT3DOWNTO0_shadow <= XC_VECTT( 3 DOWNTO 0 );
V_E_CTRL_TT_shadow <= V.E.CTRL.TT;
DSIGN_shadow <= DSIGN;
V_E_CTRL_ANNUL_shadow <= V.E.CTRL.ANNUL;
EX_JUMP_ADDRESS_shadow <= EX_JUMP_ADDRESS;
V_A_CTRL_PC31DOWNTO12_shadow <= V.A.CTRL.PC( 31 DOWNTO 12 );
V_A_RFE1_shadow <= V.A.RFE1;
V_W_WA_shadow <= V.W.WA;
V_X_ANNUL_ALL_shadow <= V.X.ANNUL_ALL;
EX_YMSB_shadow <= EX_YMSB;
EX_ADD_RES_shadow <= EX_ADD_RES;
VIR_ADDR_shadow <= VIR.ADDR;
EX_JUMP_ADDRESS31DOWNTO12_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 12 );
V_W_S_CWP_shadow <= V.W.S.CWP;
V_D_INST0_shadow <= V.D.INST ( 0 );
V_A_CTRL_ANNUL_shadow <= V.A.CTRL.ANNUL;
V_X_DATA1_shadow <= V.X.DATA ( 1 );
VP_PWD_shadow <= VP.PWD;
V_M_CTRL_RD6DOWNTO0_shadow <= V.M.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA00_shadow <= V.X.DATA ( 0 )( 0 );
V_M_CTRL_RETT_shadow <= V.M.CTRL.RETT;
V_X_CTRL_RETT_shadow <= V.X.CTRL.RETT;
V_X_CTRL_PC31DOWNTO12_shadow <= V.X.CTRL.PC( 31 DOWNTO 12 );
V_W_S_PS_shadow <= V.W.S.PS;
V_X_CTRL_TT_shadow <= V.X.CTRL.TT;
V_D_STEP_shadow <= V.D.STEP;
V_X_CTRL_WICC_shadow <= V.X.CTRL.WICC;
VIR_ADDR31DOWNTO2_shadow <= VIR.ADDR( 31 DOWNTO 2 );
V_M_CTRL_RD7DOWNTO0_shadow <= V.M.CTRL.RD ( 7 DOWNTO 0 );
V_X_RESULT_shadow <= V.X.RESULT;
V_D_CNT_shadow <= V.D.CNT;
XC_VECTT_shadow <= XC_VECTT;
EX_ADD_RES32DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 );
V_W_S_EF_shadow <= V.W.S.EF;
V_A_CTRL_PC31DOWNTO2_shadow <= V.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA04DOWNTO0_shadow <= V.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DCI_SIGNED_shadow <= V.X.DCI.SIGNED;
V_M_NALIGN_shadow <= V.M.NALIGN;
XC_WREG_shadow <= XC_WREG;
V_A_RFA2_shadow <= V.A.RFA2;
V_E_CTRL_PC31DOWNTO12_shadow <= V.E.CTRL.PC( 31 DOWNTO 12 );
EX_ADD_RES32DOWNTO332DOWNTO13_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 13 );
EX_OP231_shadow <= EX_OP2( 31 );
XC_TRAP_ADDRESS31DOWNTO4_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 4 );
V_X_ICC_shadow <= V.X.ICC;
V_A_SU_shadow <= V.A.SU;
V_E_OP2_shadow <= V.E.OP2;
EX_FORCE_A2_shadow <= EX_FORCE_A2;
V_E_CTRL_PC31DOWNTO2_shadow <= V.E.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO4_shadow <= V.E.CTRL.PC( 31 DOWNTO 4 );
V_E_OP131_shadow <= V.E.OP1( 31 );
V_X_DCI_shadow <= V.X.DCI;
V_E_CTRL_WICC_shadow <= V.E.CTRL.WICC;
EX_OP13_shadow <= EX_OP1( 3 );
V_F_PC31DOWNTO12_shadow <= V.F.PC( 31 DOWNTO 12 );
V_E_CTRL_INST_shadow <= V.E.CTRL.INST;
V_E_CTRL_LD_shadow <= V.E.CTRL.LD;
V_M_SU_shadow <= V.M.SU;
V_E_SARI_shadow <= V.E.SARI;
V_E_ET_shadow <= V.E.ET;
V_M_CTRL_PV_shadow <= V.M.CTRL.PV;
VDSU_CRDY2_shadow <= VDSU.CRDY ( 2 );
MUL_OP2_shadow <= MUL_OP2;
XC_EXCEPTION_shadow <= XC_EXCEPTION;
V_E_OP1_shadow <= V.E.OP1;
VP_ERROR_shadow <= VP.ERROR;
V_M_DCI_SIGNED_shadow <= V.M.DCI.SIGNED;
V_D_PC31DOWNTO12_shadow <= V.D.PC( 31 DOWNTO 12 );
MUL_OP231_shadow <= MUL_OP2 ( 31 );
XC_TRAP_ADDRESS31DOWNTO2_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow <= V.M.CTRL.PC( 3 DOWNTO 2 );
V_M_DCI_shadow <= V.M.DCI;
EX_OP23_shadow <= EX_OP2( 3 );
V_X_CTRL_RD6DOWNTO0_shadow <= V.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_TRAP_shadow <= V.X.CTRL.TRAP;
V_A_DIVSTART_shadow <= V.A.DIVSTART;
V_X_RESULT6DOWNTO03DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
VDSU_TT_shadow <= VDSU.TT;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 5 );
V_X_CTRL_CNT_shadow <= V.X.CTRL.CNT;
V_E_YMSB_shadow <= V.E.YMSB;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 30 DOWNTO 11 );
V_A_RFE2_shadow <= V.A.RFE2;
V_E_OP13_shadow <= V.E.OP1( 3 );
V_A_CWP_shadow <= V.A.CWP;
ME_SIZE_shadow <= ME_SIZE;
V_X_MAC_shadow <= V.X.MAC;
V_M_CTRL_INST_shadow <= V.M.CTRL.INST;
VIR_ADDR31DOWNTO4_shadow <= VIR.ADDR( 31 DOWNTO 4 );
V_A_CTRL_INST20_shadow <= V.A.CTRL.INST( 20 );
DE_REN2_shadow <= DE_REN2;
V_E_CTRL_PV_shadow <= V.E.CTRL.PV;
V_E_MAC_shadow <= V.E.MAC;
V_X_CTRL_TT3DOWNTO0_shadow <= V.X.CTRL.TT( 3 DOWNTO 0 );
EX_ADD_RES3_shadow <= EX_ADD_RES ( 3 );
V_X_CTRL_INST_shadow <= V.X.CTRL.INST;
V_M_CTRL_PC31DOWNTO2_shadow <= V.M.CTRL.PC( 31 DOWNTO 2 );
V_W_S_ET_shadow <= V.W.S.ET;
V_M_CTRL_CNT_shadow <= V.M.CTRL.CNT;
V_M_CTRL_ANNUL_shadow <= V.M.CTRL.ANNUL;
DE_INST19_shadow <= DE_INST( 19 );
XC_HALT_shadow <= XC_HALT;
V_E_OP231_shadow <= V.E.OP2( 31 );
V_A_CTRL_PC3DOWNTO2_shadow <= V.A.CTRL.PC( 3 DOWNTO 2 );
VIR_ADDR31DOWNTO12_shadow <= VIR.ADDR( 31 DOWNTO 12 );
V_M_CTRL_WICC_shadow <= V.M.CTRL.WICC;
V_M_CTRL_WREG_shadow <= V.M.CTRL.WREG;
V_W_S_S_shadow <= V.W.S.S;
V_F_PC31DOWNTO2_shadow <= V.F.PC( 31 DOWNTO 2 );
V_E_CWP_shadow <= V.E.CWP;
V_A_STEP_shadow <= V.A.STEP;
V_A_CTRL_TT3DOWNTO0_shadow <= V.A.CTRL.TT( 3 DOWNTO 0 );
V_A_CTRL_TRAP_shadow <= V.A.CTRL.TRAP;
NPC31DOWNTO2_shadow <= NPC ( 31 DOWNTO 2 );
V_M_CTRL_TRAP_shadow <= V.M.CTRL.TRAP;
V_D_PC31DOWNTO4_shadow <= V.D.PC( 31 DOWNTO 4 );
V_X_INTACK_shadow <= V.X.INTACK;
SIDLE_shadow <= SIDLE;
V_A_CTRL_RETT_shadow <= V.A.CTRL.RETT;
V_X_DATA03_shadow <= V.X.DATA ( 0 )( 3 );
V_A_CTRL_INST19_shadow <= V.A.CTRL.INST( 19 );
V_W_S_SVT_shadow <= V.W.S.SVT;
V_A_CTRL_PC31DOWNTO4_shadow <= V.A.CTRL.PC( 31 DOWNTO 4 );
V_X_LADDR_shadow <= V.X.LADDR;
V_W_S_DWT_shadow <= V.W.S.DWT;
EX_JUMP_ADDRESS31DOWNTO2_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 2 );
V_W_S_TBA_shadow <= V.W.S.TBA;
XC_WADDR6DOWNTO0_shadow <= XC_WADDR ( 6 DOWNTO 0 );
V_M_MUL_shadow <= V.M.MUL;
V_E_SU_shadow <= V.E.SU;
V_M_Y31_shadow <= V.M.Y ( 31 );
V_E_OP23_shadow <= V.E.OP2( 3 );
V_M_CTRL_PC31DOWNTO4_shadow <= V.M.CTRL.PC( 31 DOWNTO 4 );
DE_RADDR17DOWNTO0_shadow <= DE_RADDR1 ( 7 DOWNTO 0 );
V_X_CTRL_PC31DOWNTO2_shadow <= V.X.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_TRAP_shadow <= V.E.CTRL.TRAP;
V_X_DEBUG_shadow <= V.X.DEBUG;
V_M_DCI_LOCK_shadow <= V.M.DCI.LOCK;
V_X_CTRL_PC3DOWNTO2_shadow <= V.X.CTRL.PC( 3 DOWNTO 2 );
V_X_CTRL_WREG_shadow <= V.X.CTRL.WREG;
V_E_CTRL_INST24_shadow <= V.E.CTRL.INST( 24 );
V_D_MEXC_shadow <= V.D.MEXC;
V_W_RESULT_shadow <= V.W.RESULT;
VFPI_DBG_ENABLE_shadow <= VFPI.DBG.ENABLE;
EX_OP131_shadow <= EX_OP1 ( 31 );
V_D_INST1_shadow <= V.D.INST ( 1 );
V_W_EXCEPT_shadow <= V.W.EXCEPT;
V_E_CTRL_TT3DOWNTO0_shadow <= V.E.CTRL.TT( 3 DOWNTO 0 );
ME_LADDR_shadow <= ME_LADDR;
V_X_CTRL_PC31DOWNTO4_shadow <= V.X.CTRL.PC( 31 DOWNTO 4 );
V_E_CTRL_RETT_shadow <= V.E.CTRL.RETT;
XC_WADDR7DOWNTO0_shadow <= XC_WADDR ( 7 DOWNTO 0 );
V_X_CTRL_PV_shadow <= V.X.CTRL.PV;
V_E_CTRL_RD6DOWNTO0_shadow <= V.E.CTRL.RD( 6 DOWNTO 0 );
V_M_MAC_shadow <= V.M.MAC;
V_D_SET_shadow <= V.D.SET;
VIR_ADDR3DOWNTO2_shadow <= VIR.ADDR( 3 DOWNTO 2 );
V_D_CWP_shadow <= V.D.CWP;
DE_INST20_shadow <= DE_INST( 20 );
V_D_ANNUL_shadow <= V.D.ANNUL;
EX_OP2_shadow <= EX_OP2;
EX_SARI_shadow <= EX_SARI;
V_D_PC31DOWNTO2_shadow <= V.D.PC( 31 DOWNTO 2 );
V_X_DCI_SIZE_shadow <= V.X.DCI.SIZE;
V_M_Y_shadow <= V.M.Y;
V_X_CTRL_PC_shadow <= V.X.CTRL.PC;
V_X_SET_shadow <= V.X.SET;
V_A_CTRL_PC_shadow <= V.A.CTRL.PC;
V_A_JMPL_shadow <= V.A.JMPL;
V_E_CTRL_PC_shadow <= V.E.CTRL.PC;
V_E_CTRL_INST20_shadow <= V.E.CTRL.INST( 20 );
V_E_CTRL_WREG_shadow <= V.E.CTRL.WREG;
V_A_CTRL_WREG_shadow <= V.A.CTRL.WREG;
V_A_CTRL_shadow <= V.A.CTRL;
V_A_CTRL_RD6DOWNTO0_shadow <= V.A.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA0_shadow <= V.X.DATA ( 0 );
V_E_CTRL_INST19_shadow <= V.E.CTRL.INST( 19 );
ME_SIGNED_shadow <= ME_SIGNED;
V_W_WREG_shadow <= V.W.WREG;
V_D_PC_shadow <= V.D.PC;
VFPI_D_ANNUL_shadow <= VFPI.D.ANNUL;
DE_RADDR27DOWNTO0_shadow <= DE_RADDR2 ( 7 DOWNTO 0 );
V_E_CTRL_CNT_shadow <= V.E.CTRL.CNT;
V_F_PC_shadow <= V.F.PC;
V_X_DATA031_shadow <= V.X.DATA ( 0 )( 31 );
V_M_CTRL_PC31DOWNTO12_shadow <= V.M.CTRL.PC( 31 DOWNTO 12 );
V_X_CTRL_RD7DOWNTO0_shadow <= V.X.CTRL.RD ( 7 DOWNTO 0 );
V_M_CTRL_TT_shadow <= V.M.CTRL.TT;
V_X_CTRL_shadow <= V.X.CTRL;
V_A_CTRL_INST24_shadow <= V.A.CTRL.INST( 24 );
XC_TRAP_ADDRESS3DOWNTO2_shadow <= XC_TRAP_ADDRESS( 3 DOWNTO 2 );
V_X_NERROR_shadow <= V.X.NERROR;
V_F_PC31DOWNTO4_shadow <= V.F.PC( 31 DOWNTO 4 );
V_W_S_TT3DOWNTO0_shadow <= V.W.S.TT( 3 DOWNTO 0 );
EX_JUMP_ADDRESS31DOWNTO4_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 4 );
EX_ADD_RES32DOWNTO332DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 3 );
V_F_BRANCH_shadow <= V.F.BRANCH;
V_A_CTRL_WICC_shadow <= V.A.CTRL.WICC;
V_A_CTRL_LD_shadow <= V.A.CTRL.LD;
V_A_CTRL_TT_shadow <= V.A.CTRL.TT;
V_M_CTRL_LD_shadow <= V.M.CTRL.LD;
V_E_SHCNT_shadow <= V.E.SHCNT;
XC_TRAP_ADDRESS31DOWNTO12_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 12 );
V_A_CTRL_INST_shadow <= V.A.CTRL.INST;
V_A_CTRL_RD7DOWNTO0_shadow <= V.A.CTRL.RD ( 7 DOWNTO 0 );
VIR_PWD_shadow <= VIR.PWD;
XC_RESULT_shadow <= XC_RESULT;
V_A_RFA1_shadow <= V.A.RFA1;
V_E_JMPL_shadow <= V.E.JMPL;
V_E_CTRL_RD7DOWNTO0_shadow <= V.E.CTRL.RD ( 7 DOWNTO 0 );
ME_ICC_shadow <= ME_ICC;
DE_INST24_shadow <= DE_INST( 24 );
XC_TRAP_shadow <= XC_TRAP;
VDSU_TBUFCNT_shadow <= VDSU.TBUFCNT;
XC_TRAP_ADDRESS_shadow <= XC_TRAP_ADDRESS;
end process;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
V_W_S_S_shadow_intermed_2 <= V_W_S_S_shadow_intermed_1;
V_W_S_PS_shadow_intermed_1 <= V_W_S_PS_shadow;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
R_W_S_S_intermed_1 <= R.W.S.S;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_S_intermed_2 <= RIN_W_S_S_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_X_RESULT6DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_X_DATA0_intermed_2 <= R_X_DATA0_intermed_1;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_3 <= R_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
R_A_CTRL_TT3DOWNTO0_intermed_5 <= R_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_6 <= RIN_A_CTRL_TT3DOWNTO0_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_W_S_TT3DOWNTO0_intermed_2 <= R_W_S_TT3DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_4 <= R_E_CTRL_TT3DOWNTO0_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_M_CTRL_TT3DOWNTO0_intermed_4 <= RIN_M_CTRL_TT3DOWNTO0_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_X_CTRL_TT3DOWNTO0_intermed_3 <= RIN_X_CTRL_TT3DOWNTO0_intermed_2;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
R_X_CTRL_TT3DOWNTO0_intermed_2 <= R_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
RIN_E_CTRL_TT3DOWNTO0_intermed_5 <= RIN_E_CTRL_TT3DOWNTO0_intermed_4;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_2 <= XC_VECTT3DOWNTO0_shadow_intermed_1;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_M_DCI_LOCK_intermed_1 <= RIN.M.DCI.LOCK;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_M_DCI_LOCK_shadow_intermed_1 <= V_M_DCI_LOCK_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
DCO_DATA031_intermed_2 <= DCO_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_3 <= DE_INST19_shadow_intermed_2;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_E_CTRL_INST19_intermed_2 <= R_E_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_E_CTRL_INST20_intermed_2 <= R_E_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_3 <= DE_INST20_shadow_intermed_2;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
DCO_DATA00_intermed_2 <= DCO_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_2 <= DCO_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_4 <= R_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_5 <= RIN_M_CTRL_PC31DOWNTO2_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_7 <= RIN_A_CTRL_PC31DOWNTO2_intermed_6;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_6 <= R_A_CTRL_PC31DOWNTO2_intermed_5;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_X_CTRL_PC31DOWNTO2_intermed_3 <= R_X_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_D_PC31DOWNTO2_shadow_intermed_8 <= V_D_PC31DOWNTO2_shadow_intermed_7;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
RIN_D_PC31DOWNTO2_intermed_8 <= RIN_D_PC31DOWNTO2_intermed_7;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_CTRL_PC31DOWNTO2_intermed_4 <= RIN_X_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_3 <= IRIN_ADDR31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_5 <= R_E_CTRL_PC31DOWNTO2_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_D_PC31DOWNTO2_intermed_7 <= R_D_PC31DOWNTO2_intermed_6;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_2 <= IR_ADDR31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_6 <= RIN_E_CTRL_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
R_F_PC31DOWNTO2_intermed_2 <= R_F_PC31DOWNTO2_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
VIR_ADDR31DOWNTO2_shadow_intermed_3 <= VIR_ADDR31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
V_A_MULSTART_shadow_intermed_1 <= V_A_MULSTART_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_MULSTART_intermed_1 <= RIN.A.MULSTART;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_3 <= DE_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_E_CTRL_INST24_intermed_2 <= R_E_CTRL_INST24_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_DIVSTART_intermed_1 <= RIN.A.DIVSTART;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_DIVSTART_shadow_intermed_1 <= V_A_DIVSTART_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
RIN_M_Y_intermed_1 <= RIN.M.Y;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y_shadow_intermed_1 <= V_M_Y_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_M_Y31_intermed_1 <= R.M.Y( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
R_M_Y31_intermed_2 <= R_M_Y31_intermed_1;
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
DSUR_CRDY2_intermed_2 <= DSUR_CRDY2_intermed_1;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
VP_ERROR_shadow_intermed_2 <= VP_ERROR_shadow_intermed_1;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RPIN_ERROR_intermed_2 <= RPIN_ERROR_intermed_1;
V_X_NERROR_shadow_intermed_1 <= V_X_NERROR_shadow;
RP_ERROR_intermed_1 <= RP.ERROR;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
DCO_DATA1_intermed_1 <= DCO.DATA ( 1 );
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
R_X_DATA1_intermed_2 <= R_X_DATA1_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_A_CTRL_PC31DOWNTO12_intermed_7 <= RIN_A_CTRL_PC31DOWNTO12_intermed_6;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_6 <= RIN_E_CTRL_PC31DOWNTO12_intermed_5;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_4 <= R_M_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_3 <= IRIN_ADDR31DOWNTO12_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
R_F_PC31DOWNTO12_intermed_2 <= R_F_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
RIN_M_CTRL_PC31DOWNTO12_intermed_5 <= RIN_M_CTRL_PC31DOWNTO12_intermed_4;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
IR_ADDR31DOWNTO12_intermed_2 <= IR_ADDR31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_3 <= R_X_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_D_PC31DOWNTO12_shadow_intermed_8 <= V_D_PC31DOWNTO12_shadow_intermed_7;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_D_PC31DOWNTO12_intermed_7 <= R_D_PC31DOWNTO12_intermed_6;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_A_CTRL_PC31DOWNTO12_intermed_6 <= R_A_CTRL_PC31DOWNTO12_intermed_5;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_5 <= R_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_X_CTRL_PC31DOWNTO12_intermed_4 <= RIN_X_CTRL_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
RIN_D_PC31DOWNTO12_intermed_8 <= RIN_D_PC31DOWNTO12_intermed_7;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
VIR_ADDR31DOWNTO12_shadow_intermed_3 <= VIR_ADDR31DOWNTO12_shadow_intermed_2;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4;
ICO_DATA0_intermed_1 <= ICO.DATA ( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
R_D_INST1_intermed_2 <= R_D_INST1_intermed_1;
ICO_DATA1_intermed_1 <= ICO.DATA ( 1 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
R_X_DATA03_intermed_2 <= R_X_DATA03_intermed_1;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_E_ALUCIN_shadow_intermed_1 <= V_E_ALUCIN_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_E_ALUCIN_intermed_1 <= RIN.E.ALUCIN;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_E_YMSB_shadow_intermed_1 <= V_E_YMSB_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_E_YMSB_intermed_1 <= RIN.E.YMSB;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_E_SHCNT_shadow_intermed_1 <= V_E_SHCNT_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_E_SHCNT_intermed_1 <= RIN.E.SHCNT;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
V_E_SARI_shadow_intermed_1 <= V_E_SARI_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_E_SARI_intermed_1 <= RIN.E.SARI;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
V_X_DCI_SIGNED_shadow_intermed_1 <= V_X_DCI_SIGNED_shadow;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
V_X_DCI_SIZE_shadow_intermed_1 <= V_X_DCI_SIZE_shadow;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_3 <= V_M_RESULT1DOWNTO0_shadow_intermed_2;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_3 <= RIN_M_RESULT1DOWNTO0_intermed_2;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_X_LADDR_shadow_intermed_1 <= V_X_LADDR_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_X_CTRL_TRAP_shadow_intermed_1 <= V_X_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
V_X_MEXC_shadow_intermed_1 <= V_X_MEXC_shadow;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
DCO_MEXC_intermed_1 <= DCO.MEXC;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RPIN_PWD_intermed_1 <= RPIN.PWD;
V_X_DEBUG_shadow_intermed_1 <= V_X_DEBUG_shadow;
VP_PWD_shadow_intermed_1 <= VP_PWD_shadow;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_W_S_TBA_shadow_intermed_1 <= V_W_S_TBA_shadow;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
RIN_W_S_TBA_intermed_1 <= RIN.W.S.TBA;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
DSUIN_TT_intermed_1 <= DSUIN.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RPIN_PWD_intermed_1 <= RPIN.PWD;
IRIN_PWD_intermed_1 <= IRIN.PWD;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_W_S_TT_intermed_1 <= RIN.W.S.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD6DOWNTO0_shadow;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_W_S_CWP_shadow_intermed_1 <= V_W_S_CWP_shadow;
RIN_W_S_ET_intermed_1 <= RIN.W.S.ET;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_D_PC_intermed_6 <= RIN_D_PC_intermed_5;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
VIR_ADDR_shadow_intermed_1 <= VIR_ADDR_shadow;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
RIN_A_CTRL_PC_intermed_5 <= RIN_A_CTRL_PC_intermed_4;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_4 <= R_A_CTRL_PC_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
V_E_CTRL_PC_shadow_intermed_4 <= V_E_CTRL_PC_shadow_intermed_3;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_M_CTRL_PC_intermed_2 <= R_M_CTRL_PC_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC_intermed_1 <= R.X.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
R_E_CTRL_PC_intermed_3 <= R_E_CTRL_PC_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_3 <= RIN_M_CTRL_PC_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_X_CTRL_PC_shadow_intermed_2 <= V_X_CTRL_PC_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_M_CTRL_PC_shadow_intermed_3 <= V_M_CTRL_PC_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_5 <= V_A_CTRL_PC_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
R_D_PC_intermed_5 <= R_D_PC_intermed_4;
RIN_F_PC_intermed_1 <= RIN.F.PC;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_E_CTRL_PC_intermed_4 <= RIN_E_CTRL_PC_intermed_3;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
RIN_X_CTRL_PC_intermed_2 <= RIN_X_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
V_D_PC_shadow_intermed_6 <= V_D_PC_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
DSUIN_TBUFCNT_intermed_1 <= DSUIN.TBUFCNT;
RIN_W_EXCEPT_intermed_1 <= RIN.W.EXCEPT;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
RIN_W_RESULT_intermed_1 <= RIN.W.RESULT;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_W_WA_intermed_1 <= RIN.W.WA;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_W_WREG_intermed_1 <= RIN.W.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_W_S_SVT_intermed_1 <= RIN.W.S.SVT;
RIN_W_S_DWT_intermed_1 <= RIN.W.S.DWT;
RIN_W_S_EF_intermed_1 <= RIN.W.S.EF;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_E_CTRL_intermed_2 <= RIN_E_CTRL_intermed_1;
R_E_CTRL_intermed_1 <= R.E.CTRL;
RIN_X_CTRL_intermed_1 <= RIN.X.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
V_E_CTRL_shadow_intermed_2 <= V_E_CTRL_shadow_intermed_1;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
RIN_A_CTRL_intermed_3 <= RIN_A_CTRL_intermed_2;
V_M_CTRL_shadow_intermed_1 <= V_M_CTRL_shadow;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
V_A_CTRL_shadow_intermed_3 <= V_A_CTRL_shadow_intermed_2;
R_A_CTRL_intermed_1 <= R.A.CTRL;
R_A_CTRL_intermed_2 <= R_A_CTRL_intermed_1;
V_M_DCI_shadow_intermed_1 <= V_M_DCI_shadow;
RIN_M_DCI_intermed_1 <= RIN.M.DCI;
RIN_X_DCI_intermed_1 <= RIN.X.DCI;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_E_CTRL_RETT_shadow_intermed_2 <= V_E_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_3 <= V_A_CTRL_RETT_shadow_intermed_2;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
RIN_A_CTRL_RETT_intermed_3 <= RIN_A_CTRL_RETT_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_E_CTRL_RETT_intermed_1 <= R.E.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
RIN_E_CTRL_RETT_intermed_2 <= RIN_E_CTRL_RETT_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_X_CTRL_RETT_intermed_1 <= RIN.X.CTRL.RETT;
V_M_CTRL_RETT_shadow_intermed_1 <= V_M_CTRL_RETT_shadow;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
R_A_CTRL_RETT_intermed_2 <= R_A_CTRL_RETT_intermed_1;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
V_E_MAC_shadow_intermed_2 <= V_E_MAC_shadow_intermed_1;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
RIN_E_MAC_intermed_2 <= RIN_E_MAC_intermed_1;
R_E_MAC_intermed_1 <= R.E.MAC;
V_M_MAC_shadow_intermed_1 <= V_M_MAC_shadow;
RIN_X_MAC_intermed_1 <= RIN.X.MAC;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_X_CTRL_ANNUL_intermed_1 <= RIN.X.CTRL.ANNUL;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
RIN_X_SET_intermed_1 <= RIN.X.SET;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_X_ICC_intermed_1 <= RIN.X.ICC;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
R_A_CTRL_WICC_intermed_2 <= R_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_E_CTRL_WICC_shadow_intermed_2 <= V_E_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_3 <= V_A_CTRL_WICC_shadow_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_X_CTRL_WICC_intermed_1 <= RIN.X.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_E_CTRL_WICC_intermed_2 <= RIN_E_CTRL_WICC_intermed_1;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
R_E_CTRL_WICC_intermed_1 <= R.E.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_M_CTRL_WICC_shadow_intermed_1 <= V_M_CTRL_WICC_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_WICC_intermed_3 <= RIN_A_CTRL_WICC_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
R_A_CTRL_intermed_1 <= R.A.CTRL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
RIN_E_CWP_intermed_1 <= RIN.E.CWP;
V_A_CWP_shadow_intermed_1 <= V_A_CWP_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_D_CWP_intermed_2 <= RIN_D_CWP_intermed_1;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
V_D_CWP_shadow_intermed_2 <= V_D_CWP_shadow_intermed_1;
R_D_CWP_intermed_1 <= R.D.CWP;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_M_MUL_intermed_1 <= RIN.M.MUL;
RIN_M_NALIGN_intermed_1 <= RIN.M.NALIGN;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
R_A_CTRL_LD_intermed_2 <= R_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_3 <= RIN_A_CTRL_LD_intermed_2;
V_E_CTRL_LD_shadow_intermed_1 <= V_E_CTRL_LD_shadow;
V_E_CTRL_LD_shadow_intermed_2 <= V_E_CTRL_LD_shadow_intermed_1;
R_E_CTRL_LD_intermed_1 <= R.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_2 <= RIN_E_CTRL_LD_intermed_1;
RIN_M_CTRL_LD_intermed_1 <= RIN.M.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
V_A_CTRL_LD_shadow_intermed_3 <= V_A_CTRL_LD_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
RIN_E_JMPL_intermed_1 <= RIN.E.JMPL;
RIN_A_JMPL_intermed_1 <= RIN.A.JMPL;
V_A_JMPL_shadow_intermed_1 <= V_A_JMPL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_A_SU_intermed_1 <= RIN.A.SU;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_ET_intermed_1 <= RIN.E.ET;
RIN_A_ET_intermed_1 <= RIN.A.ET;
V_A_ET_shadow_intermed_1 <= V_A_ET_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
V_A_RFA1_shadow_intermed_1 <= V_A_RFA1_shadow;
DBGI_DADDR9DOWNTO2_intermed_1 <= DBGI.DADDR ( 9 DOWNTO 2 );
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
RIN_A_RFA2_intermed_1 <= RIN.A.RFA2;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WY_intermed_1 <= RIN.A.CTRL.WY;
ICO_MEXC_intermed_1 <= ICO.MEXC;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
R_D_ANNUL_intermed_1 <= R.D.ANNUL;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
V_D_ANNUL_shadow_intermed_2 <= V_D_ANNUL_shadow_intermed_1;
DBGI_STEP_intermed_1 <= DBGI.STEP;
V_D_STEP_shadow_intermed_1 <= V_D_STEP_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_ANNUL_intermed_2 <= RIN_D_ANNUL_intermed_1;
RIN_A_STEP_intermed_1 <= RIN.A.STEP;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
RIN_F_BRANCH_intermed_1 <= RIN.F.BRANCH;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
R_D_INST0_intermed_1 <= R.D.INST( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
RIN_D_SET_intermed_1 <= RIN.D.SET;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
R_E_CTRL_INST_intermed_2 <= R_E_CTRL_INST_intermed_1;
R_M_CTRL_INST_intermed_1 <= R.M.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
DE_INST_shadow_intermed_4 <= DE_INST_shadow_intermed_3;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_4 <= V_A_CTRL_INST_shadow_intermed_3;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
V_E_CTRL_INST_shadow_intermed_3 <= V_E_CTRL_INST_shadow_intermed_2;
RIN_X_CTRL_INST_intermed_1 <= RIN.X.CTRL.INST;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_A_CTRL_INST_intermed_4 <= RIN_A_CTRL_INST_intermed_3;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_M_CTRL_INST_intermed_2 <= RIN_M_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_3 <= RIN_E_CTRL_INST_intermed_2;
V_M_CTRL_INST_shadow_intermed_1 <= V_M_CTRL_INST_shadow;
V_M_CTRL_INST_shadow_intermed_2 <= V_M_CTRL_INST_shadow_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_3 <= R_A_CTRL_INST_intermed_2;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_CNT_shadow_intermed_3 <= V_E_CTRL_CNT_shadow_intermed_2;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
RIN_D_CNT_intermed_5 <= RIN_D_CNT_intermed_4;
R_M_CTRL_CNT_intermed_1 <= R.M.CTRL.CNT;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
V_A_CTRL_CNT_shadow_intermed_4 <= V_A_CTRL_CNT_shadow_intermed_3;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
R_A_CTRL_CNT_intermed_3 <= R_A_CTRL_CNT_intermed_2;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
V_D_CNT_shadow_intermed_5 <= V_D_CNT_shadow_intermed_4;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_D_CNT_intermed_4 <= R_D_CNT_intermed_3;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
R_E_CTRL_CNT_intermed_2 <= R_E_CTRL_CNT_intermed_1;
RIN_X_CTRL_CNT_intermed_1 <= RIN.X.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_A_CTRL_CNT_intermed_4 <= RIN_A_CTRL_CNT_intermed_3;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_M_CTRL_CNT_intermed_2 <= RIN_M_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_3 <= RIN_E_CTRL_CNT_intermed_2;
V_M_CTRL_CNT_shadow_intermed_1 <= V_M_CTRL_CNT_shadow;
V_M_CTRL_CNT_shadow_intermed_2 <= V_M_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_3 <= V_E_CTRL_PV_shadow_intermed_2;
R_M_CTRL_PV_intermed_1 <= R.M.CTRL.PV;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_E_CTRL_PV_intermed_2 <= R_E_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_3 <= R_A_CTRL_PV_intermed_2;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_3 <= RIN_E_CTRL_PV_intermed_2;
RIN_X_CTRL_PV_intermed_1 <= RIN.X.CTRL.PV;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
RIN_M_CTRL_PV_intermed_2 <= RIN_M_CTRL_PV_intermed_1;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
V_A_CTRL_PV_shadow_intermed_4 <= V_A_CTRL_PV_shadow_intermed_3;
V_M_CTRL_PV_shadow_intermed_1 <= V_M_CTRL_PV_shadow;
V_M_CTRL_PV_shadow_intermed_2 <= V_M_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
RIN_A_CTRL_PV_intermed_4 <= RIN_A_CTRL_PV_intermed_3;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (RP.ERROR /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(1) <= '1' when (RP.ERROR /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(2) <= '1' when (RFI.REN1 /= DE_REN1_shadow) else '0';
dfp_trap_vector(3) <= '1' when (RFI.REN2 /= DE_REN2_shadow) else '0';
dfp_trap_vector(4) <= '1' when (RFI.DIAG(0) /= DCO.TESTEN) else '0';
dfp_trap_vector(5) <= '1' when (RFI.DIAG /= "0000") else '0';
dfp_trap_vector(6) <= '1' when (ICI.DPC(31 downto 2) /= R.D.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(7) <= '1' when (ICI.FPC(31 downto 2) /= R.F.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(8) <= '1' when (ICI.RPC(31 downto 2) /= NPC31DOWNTO2_shadow) else '0';
dfp_trap_vector(9) <= '1' when (ICI.FLUSHL /= '0') else '0';
dfp_trap_vector(10) <= '1' when (MULI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(11) <= '1' when (MULI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(12) <= '1' when (MULI.OP2(31 downto 0) /= MUL_OP2_shadow) else '0';
dfp_trap_vector(13) <= '1' when (MULI.OP2(31) /= MUL_OP231_shadow) else '0';
dfp_trap_vector(14) <= '1' when (DIVI.START /= R.A.DIVSTART) else '0';
dfp_trap_vector(15) <= '1' when (DIVI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(16) <= '1' when (DIVI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(17) <= '1' when (DIVI.OP2(31) /= EX_OP231_shadow) else '0';
dfp_trap_vector(18) <= '1' when (DIVI.OP2(31 downto 0) /= EX_OP2_shadow) else '0';
dfp_trap_vector(19) <= '1' when (DIVI.Y(31 downto 0) /= R.M.Y) else '0';
dfp_trap_vector(20) <= '1' when (DIVI.Y(31) /= R.M.Y ( 31 )) else '0';
dfp_trap_vector(21) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow) else '0';
dfp_trap_vector(22) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(23) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(24) <= '1' when (V_A_STEP_shadow /= RIN_A_STEP_intermed_1) else '0';
dfp_trap_vector(25) <= '1' when (V_D_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(26) <= '1' when (V_D_STEP_shadow /= DBGI.STEP) else '0';
dfp_trap_vector(27) <= '1' when (V_D_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(28) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow) else '0';
dfp_trap_vector(29) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow) else '0';
dfp_trap_vector(30) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(31) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(32) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow) else '0';
dfp_trap_vector(33) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow) else '0';
dfp_trap_vector(34) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(35) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(36) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow) else '0';
dfp_trap_vector(37) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(38) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(39) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow) else '0';
dfp_trap_vector(40) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(41) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(42) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(43) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(44) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(45) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(46) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow) else '0';
dfp_trap_vector(47) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(48) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow) else '0';
dfp_trap_vector(49) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow) else '0';
dfp_trap_vector(50) <= '1' when (V_A_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(51) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow) else '0';
dfp_trap_vector(52) <= '1' when (V_A_STEP_shadow /= R.A.STEP) else '0';
dfp_trap_vector(53) <= '1' when (V_A_STEP_shadow /= DBGI_STEP_intermed_1) else '0';
dfp_trap_vector(54) <= '1' when (V_A_STEP_shadow /= V_D_STEP_shadow_intermed_1) else '0';
dfp_trap_vector(55) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(56) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(57) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(58) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(59) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(60) <= '1' when (RIN.X.DATA ( 1 ) /= V_X_DATA1_shadow) else '0';
dfp_trap_vector(61) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow) else '0';
dfp_trap_vector(62) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow) else '0';
dfp_trap_vector(63) <= '1' when (RIN.D.INST ( 1 ) /= V_D_INST1_shadow) else '0';
dfp_trap_vector(64) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow) else '0';
dfp_trap_vector(65) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow) else '0';
dfp_trap_vector(66) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow) else '0';
dfp_trap_vector(67) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow) else '0';
dfp_trap_vector(68) <= '1' when (XC_HALT_shadow /= DBGI.HALT) else '0';
dfp_trap_vector(69) <= '1' when (XC_HALT_shadow /= '0') else '0';
dfp_trap_vector(70) <= '1' when (V_A_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(71) <= '1' when (V_A_CTRL_TT_shadow /= R.A.CTRL.TT) else '0';
dfp_trap_vector(72) <= '1' when (V_A_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(73) <= '1' when (V_A_CTRL_INST_shadow /= DE_INST_shadow) else '0';
dfp_trap_vector(74) <= '1' when (V_A_CTRL_PC_shadow /= R.D.PC) else '0';
dfp_trap_vector(75) <= '1' when (V_A_CTRL_CNT_shadow /= R.D.CNT) else '0';
dfp_trap_vector(76) <= '1' when (V_A_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(77) <= '1' when (V_X_NERROR_shadow /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(78) <= '1' when (V_X_NERROR_shadow /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(79) <= '1' when (V_X_NERROR_shadow /= RP.ERROR) else '0';
dfp_trap_vector(80) <= '1' when (V_M_MAC_shadow /= R.E.MAC) else '0';
dfp_trap_vector(81) <= '1' when (V_M_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(82) <= '1' when (V_E_JMPL_shadow /= R.A.JMPL) else '0';
dfp_trap_vector(83) <= '1' when (V_E_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0';
dfp_trap_vector(84) <= '1' when (V_E_SU_shadow /= R.A.SU) else '0';
dfp_trap_vector(85) <= '1' when (V_E_ET_shadow /= R.A.ET) else '0';
dfp_trap_vector(86) <= '1' when (V_A_CWP_shadow /= R.D.CWP) else '0';
dfp_trap_vector(87) <= '1' when (V_A_CTRL_TRAP_shadow /= R.D.MEXC) else '0';
dfp_trap_vector(88) <= '1' when (V_A_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_1) else '0';
dfp_trap_vector(89) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_1) else '0';
dfp_trap_vector(90) <= '1' when (VP_PWD_shadow /= RP.PWD) else '0';
dfp_trap_vector(91) <= '1' when (VP_PWD_shadow /= '0') else '0';
dfp_trap_vector(92) <= '1' when (VP_PWD_shadow /= RPIN_PWD_intermed_1) else '0';
dfp_trap_vector(93) <= '1' when (V_M_MUL_shadow /= R.M.MUL) else '0';
dfp_trap_vector(94) <= '1' when (V_M_MAC_shadow /= V_E_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(95) <= '1' when (V_M_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(96) <= '1' when (V_M_MAC_shadow /= RIN_E_MAC_intermed_1) else '0';
dfp_trap_vector(97) <= '1' when (VDSU_TBUFCNT_shadow /= TBUFCNTX_shadow) else '0';
dfp_trap_vector(98) <= '1' when (V_M_MUL_shadow /= RIN_M_MUL_intermed_1) else '0';
dfp_trap_vector(99) <= '1' when (V_M_MUL_shadow /= '0') else '0';
dfp_trap_vector(100) <= '1' when (V_W_RESULT_shadow /= XC_RESULT_shadow) else '0';
dfp_trap_vector(101) <= '1' when (V_W_WA_shadow /= XC_WADDR7DOWNTO0_shadow) else '0';
dfp_trap_vector(102) <= '1' when (V_W_S_SVT_shadow /= R.W.S.SVT) else '0';
dfp_trap_vector(103) <= '1' when (V_W_S_SVT_shadow /= '0') else '0';
dfp_trap_vector(104) <= '1' when (V_W_S_SVT_shadow /= RIN_W_S_SVT_intermed_1) else '0';
dfp_trap_vector(105) <= '1' when (V_W_S_DWT_shadow /= RIN_W_S_DWT_intermed_1) else '0';
dfp_trap_vector(106) <= '1' when (V_W_S_DWT_shadow /= R.W.S.DWT) else '0';
dfp_trap_vector(107) <= '1' when (V_W_S_DWT_shadow /= '0') else '0';
dfp_trap_vector(108) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0';
dfp_trap_vector(109) <= '1' when (V_E_CWP_shadow /= R.A.CWP) else '0';
dfp_trap_vector(110) <= '1' when (V_M_SU_shadow /= R.E.SU) else '0';
dfp_trap_vector(111) <= '1' when (V_X_DCI_shadow /= R.M.DCI) else '0';
dfp_trap_vector(112) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0';
dfp_trap_vector(113) <= '1' when (V_X_MAC_shadow /= V_E_MAC_shadow_intermed_2) else '0';
dfp_trap_vector(114) <= '1' when (V_X_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(115) <= '1' when (V_X_MAC_shadow /= RIN_E_MAC_intermed_2) else '0';
dfp_trap_vector(116) <= '1' when (V_X_MAC_shadow /= R_E_MAC_intermed_1) else '0';
dfp_trap_vector(117) <= '1' when (V_X_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(118) <= '1' when (V_X_MAC_shadow /= V_M_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(119) <= '1' when (V_X_MAC_shadow /= RIN_X_MAC_intermed_1) else '0';
dfp_trap_vector(120) <= '1' when (V_X_MAC_shadow /= R.X.MAC) else '0';
dfp_trap_vector(121) <= '1' when (V_X_LADDR_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0';
dfp_trap_vector(122) <= '1' when (V_X_MEXC_shadow /= DCO.MEXC) else '0';
dfp_trap_vector(123) <= '1' when (V_X_ICC_shadow /= ME_ICC_shadow) else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_62 : std_logic_vector(61 downto 0);
variable or_reduce_31 : std_logic_vector(30 downto 0);
variable or_reduce_16 : std_logic_vector(15 downto 0);
variable or_reduce_8 : std_logic_vector(7 downto 0);
variable or_reduce_4 : std_logic_vector(3 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_62 := dfp_trap_vector(123 downto 62) OR dfp_trap_vector(61 downto 0);
or_reduce_31 := or_reduce_62(61 downto 31) OR or_reduce_62(30 downto 0);
or_reduce_16 := or_reduce_31(30 downto 15) OR ("0" & or_reduce_31(14 downto 0));
or_reduce_8 := or_reduce_16(15 downto 8) OR or_reduce_16(7 downto 0);
or_reduce_4 := or_reduce_8(7 downto 4) OR or_reduce_8(3 downto 0);
or_reduce_2 := or_reduce_4(3 downto 2) OR or_reduce_4(1 downto 0);
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0';
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then ir <= irin; end if;
end if;
end process;
dummy <= '1';
end;
| mit | b69493d43445e57b1e2ee80b97d31e10 | 0.686931 | 2.272294 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mfpwx.vhd | 2 | 7,228 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwx
-- File: grfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Meiko/MFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity mfpwx is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end;
architecture rtl of mfpwx is
component mfpw
generic (pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
begin
mfpw0 : mfpw generic map (pclow, dsu, disas)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
rf1 : regfile_3p generic map (tech, 4, 32, 1, 16)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr, rfi1.ren1, rfo1.data1,
rfi1.rd2addr, rfi1.ren2, rfo1.data2);
rf2 : regfile_3p generic map (tech, 4, 32, 1, 16)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr, rfi2.ren1, rfo2.data1,
rfi2.rd2addr, rfi2.ren2, rfo2.data2);
end;
| mit | c901523bd8194342cc50884097281001 | 0.540122 | 3.123596 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/uart/libdcom.vhd | 2 | 5,259 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libdcom
-- File: libdcom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Types, functions and components for DSU uart
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.uart.all;
use gaisler.misc.all;
package libdcom is
type dcom_uart_in_type is record
read : std_ulogic;
write : std_ulogic;
data : std_logic_vector(7 downto 0);
end record;
type dcom_uart_out_type is record
dready : std_ulogic;
tsempty : std_ulogic;
thempty : std_ulogic;
lock : std_ulogic;
enable : std_ulogic;
data : std_logic_vector(7 downto 0);
end record;
component dcom_uart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end component;
component dcom
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : out ahb_dma_in_type;
dmao : in ahb_dma_out_type;
uarti : out dcom_uart_in_type;
uarto : in dcom_uart_out_type;
ahbi : in ahb_mst_in_type
);
end component;
-- pragma translate_off
procedure rxc(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time);
procedure rxi(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time; lresp : boolean);
procedure txc(signal txd : out std_logic; td : integer;
txperiod : time);
procedure txa(signal txd : out std_logic; td1, td2, td3, td4 : integer;
txperiod : time);
procedure txi(signal rxd : in std_logic; signal txd : out std_logic;
td1, td2, td3, td4 : integer; txperiod : time;
lresp : boolean);
-- pragma translate_on
end;
-- pragma translate_off
package body libdcom is
procedure rxc(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time) is
variable rxdata : std_logic_vector(7 downto 0);
begin
wait until rxd = '0'; wait for TXPERIOD/2;
for i in 0 to 7 loop wait for TXPERIOD; rxdata(i):= rxd; end loop;
wait for TXPERIOD ;
d := rxdata;
end;
procedure rxi(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time; lresp : boolean) is
variable rxdata : std_logic_vector(31 downto 0);
variable resp : std_logic_vector(7 downto 0);
begin
for i in 3 downto 0 loop
rxc(rxd, rxdata((i*8 +7) downto i*8), txperiod);
end loop;
d := rxdata;
if LRESP then
rxc(rxd, resp, txperiod);
-- print("RESP : 0x" & tosth(resp));
end if;
end;
procedure txc(signal txd : out std_logic; td : integer;
txperiod : time) is
variable txdata : std_logic_vector(10 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td, 8) & '0';
for i in 0 to 10 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
end;
procedure txa(signal txd : out std_logic; td1, td2, td3, td4 : integer;
txperiod : time) is
variable txdata : std_logic_vector(43 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td4, 8) & '0'
& "11" & conv_std_logic_vector(td3, 8) & '0'
& "11" & conv_std_logic_vector(td2, 8) & '0'
& "11" & conv_std_logic_vector(td1, 8) & '0';
for i in 0 to 43 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
end;
procedure txi(signal rxd : in std_logic; signal txd : out std_logic;
td1, td2, td3, td4 : integer; txperiod : time;
lresp : boolean) is
variable txdata : std_logic_vector(43 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td4, 8) & '0'
& "11" & conv_std_logic_vector(td3, 8) & '0'
& "11" & conv_std_logic_vector(td2, 8) & '0'
& "11" & conv_std_logic_vector(td1, 8) & '0';
for i in 0 to 43 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
if LRESP then
rxc(rxd, txdata(7 downto 0), txperiod);
-- print("RESP : 0x" & tosth(txdata(7 downto 0)));
end if;
end;
end;
-- pragma translate_on
| mit | 7020e2e285d0ec60ec1275fb9e04ca65 | 0.605248 | 3.311713 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/net/net.vhd | 2 | 6,963 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: net
-- File: net.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for network cores
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package net is
type eth_in_type is record
gtx_clk : std_ulogic;
rmii_clk : std_ulogic;
tx_clk : std_ulogic;
rx_clk : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
mdio_i : std_ulogic;
phyrstaddr : std_logic_vector(4 downto 0);
edcladdr : std_logic_vector(3 downto 0);
end record;
type eth_out_type is record
reset : std_ulogic;
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
end record;
component eth_arb
generic(
fullduplex : integer := 0;
mdiomaster : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
ethi : in eth_in_type;
etho : out eth_out_type;
methi : in eth_out_type;
metho : out eth_in_type;
dethi : in eth_out_type;
detho : out eth_in_type
);
end component;
component greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 2 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_gbit is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 1 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component grethm
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 2 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
end;
| mit | 00fb556378d7f23d59431f3ece280004 | 0.495907 | 3.927242 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/can/can_rd.vhd | 2 | 6,590 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_rd is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end;
architecture rtl of can_rd is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
muxsel : std_logic;
writemux : std_logic;
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal addr : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
signal can_lrxi, can_ltxo : std_logic;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable vmuxreg : std_logic;
begin
v := r;
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1));
vmuxreg := not r.haddr(7) and r.haddr(6);
--v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
-- and not r.ws(0) and not r.herr;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr and not vmuxreg;
v.writemux := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and vmuxreg;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := ahbsi.hwdata(31 downto 24);
when "01" => v.hwdata := ahbsi.hwdata(23 downto 16);
when "10" => v.hwdata := ahbsi.hwdata(15 downto 8);
when others => v.hwdata := ahbsi.hwdata(7 downto 0);
end case;
--dataout := data_out(0);
if r.haddr(7 downto 6) = "01" then
dataout := (others => r.muxsel);
if r.writemux = '1' then
v.muxsel := r.hwdata(0);
end if;
else
dataout := data_out(0);
end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= dataout & dataout & dataout & dataout;
ahbso.hresp <= hresp; rin <= v;
end process;
-- Double mapping of registers [byte (offset 0), word (offset 0x80)]
dmap0 : if dmap = 0 generate
addr <= r.haddr(7 downto 0);
end generate;
dmap1 : if dmap = 1 generate
addr <= "000"&r.haddr(6 downto 2) when r.haddr(7) = '1' else
r.haddr(7 downto 0);
end generate;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst)
--port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
port map (reset, clk, r.hsel, r.hwrite2, addr, r.hwdata,
data_out(0), irqo(0), can_lrxi, can_ltxo);
cmux : canmux port map (r.muxsel, can_lrxi, can_ltxo, can_rxi, can_txo);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hcache <= '0';
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
| mit | ae4c7995cbd7cdd79c37e04b340e3bef | 0.591958 | 3.402168 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/techbuf.vhd | 2 | 2,814 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: genclkbuf
-- File: genclkbuf.vhd
-- Author: Jiri Gaisler, Marko Isomaki - Gaisler Research
-- Description: Hard buffers with tech wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity techbuf is
generic(
buftype : integer range 0 to 4 := 0;
tech : integer range 0 to NTECH := inferred);
port( i : in std_ulogic; o : out std_ulogic);
end entity;
architecture rtl of techbuf is
component clkbuf_apa3 is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_actel is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_xilinx is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_ut025crh is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
begin
gen : if has_techbuf(tech) = 0 generate
o <= i;
end generate;
pa3 : if (tech = apa3) generate
axc : clkbuf_apa3 generic map (buftype => buftype) port map(i => i, o => o);
end generate;
axc : if (tech = axcel) generate
axc : clkbuf_actel generic map (buftype => buftype) port map(i => i, o => o);
end generate;
xil : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or (tech = virtex4) or
(tech = spartan3e) or (tech = virtex5) generate
xil : clkbuf_xilinx generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut : if (tech = ut25) generate
axc : clkbuf_ut025crh generic map (buftype => buftype) port map(i => i, o => o);
end generate;
end architecture;
| mit | 1dd8bd7fa3c5c8cd195040e0f0379b77 | 0.62651 | 3.787349 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/unisim/usbhc_unisimpkg.vhd | 1 | 30,492 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: usbhc_unisimpkg
-- File: usbhc_unisimpkg.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: Component declartions for the tech wrapper for unisim/xilinx
-- usbhc netlists
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package usbhc_unisimpkg is
component usbhc_unisim_comb0
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_unisim_comb1
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*0 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*0 downto 1*0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hlock : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbmo_hwrite : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*0 downto 1*0);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*0 downto 1*0);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hresp : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*0 downto 1*0);
uhc_ahbso_hcache : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hirq : out std_logic_vector(1*0 downto 1*0);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
sie11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
sie11_pb_en : out std_logic_vector(1*0 downto 1*0);
sie11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_sie11_data : in std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
mbc11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_en : out std_logic_vector(1*0 downto 1*0);
mbc11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_mbc11_data : in std_logic_vector((1*32)*0 downto 1*0);
bufsel : out std_ulogic);
end component;
component usbhc_unisim_comb2
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_unisim_comb3
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((2*2)-1) downto 0);
termsel : out std_logic_vector((2-1) downto 0);
suspendm : out std_logic_vector((2-1) downto 0);
opmode : out std_logic_vector(((2*2)-1) downto 0);
txvalid : out std_logic_vector((2-1) downto 0);
drvvbus : out std_logic_vector((2-1) downto 0);
dataho : out std_logic_vector(((2*8)-1) downto 0);
validho : out std_logic_vector((2-1) downto 0);
host : out std_logic_vector((2-1) downto 0);
stp : out std_logic_vector((2-1) downto 0);
datao : out std_logic_vector(((2*8)-1) downto 0);
utm_rst : out std_logic_vector((2-1) downto 0);
dctrlo : out std_logic_vector((2-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((2*2)-1) downto 0);
txready : in std_logic_vector((2-1) downto 0);
rxvalid : in std_logic_vector((2-1) downto 0);
rxactive : in std_logic_vector((2-1) downto 0);
rxerror : in std_logic_vector((2-1) downto 0);
vbusvalid : in std_logic_vector((2-1) downto 0);
datahi : in std_logic_vector(((2*8)-1) downto 0);
validhi : in std_logic_vector((2-1) downto 0);
hostdisc : in std_logic_vector((2-1) downto 0);
nxt : in std_logic_vector((2-1) downto 0);
dir : in std_logic_vector((2-1) downto 0);
datai : in std_logic_vector(((2*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean;
end usbhc_unisimpkg;
package body usbhc_unisimpkg is
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean is
begin
-- comb0
if nports = 1 and ehcgen = 0 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb1
if nports = 1 and ehcgen = 1 and uhcgen = 0 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb2
if nports = 1 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb3
if nports = 2 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 2 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
return false;
end valid_comb;
end usbhc_unisimpkg;
| mit | dced8623862edb7ecfe47fe1be7f463c | 0.612489 | 3.082491 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/axcelerator/memory_axcelerator.vhd | 2 | 11,227 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_axcelerator_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Actel AX rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library axcelerator;
use axcelerator.RAM64K36;
-- pragma translate_on
entity axcel_ssram is
generic (abits : integer := 16; dbits : integer := 36);
port (
wa, ra : in std_logic_vector(15 downto 0);
wclk, rclk : in std_ulogic;
di : in std_logic_vector(dbits -1 downto 0);
do : out std_logic_vector(dbits -1 downto 0);
width : in std_logic_vector(2 downto 0);
ren, wen : in std_ulogic
);
end;
architecture rtl of axcel_ssram is
component RAM64K36
port(
WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
end component;
signal gnd : std_ulogic;
signal depth : std_logic_vector(4 downto 0);
signal d, q : std_logic_vector(36 downto 0);
begin
depth <= "00000";
do <= q(dbits-1 downto 0);
d(dbits-1 downto 0) <= di;
d(36 downto dbits) <= (others => '0');
u0 : RAM64K36
port map (
WRAD0 => wa(0), WRAD1 => wa(1), WRAD2 => wa(2), WRAD3 => wa(3),
WRAD4 => wa(4), WRAD5 => wa(5), WRAD6 => wa(6), WRAD7 => wa(7),
WRAD8 => wa(8), WRAD9 => wa(9), WRAD10 => wa(10), WRAD11 => wa(11),
WRAD12 => wa(12), WRAD13 => wa(13), WRAD14 => wa(14), WRAD15 => wa(15),
WD0 => d(0), WD1 => d(1), WD2 => d(2), WD3 => d(3), WD4 => d(4),
WD5 => d(5), WD6 => d(6), WD7 => d(7), WD8 => d(8), WD9 => d(9),
WD10 => d(10), WD11 => d(11), WD12 => d(12), WD13 => d(13), WD14 => d(14),
WD15 => d(15), WD16 => d(16), WD17 => d(17), WD18 => d(18), WD19 => d(19),
WD20 => d(20), WD21 => d(21), WD22 => d(22), WD23 => d(23), WD24 => d(24),
WD25 => d(25), WD26 => d(26), WD27 => d(27), WD28 => d(28), WD29 => d(29),
WD30 => d(30), WD31 => d(31), WD32 => d(32), WD33 => d(33), WD34 => d(34),
WD35 => d(35), WEN => wen, DEPTH0 => depth(0),
DEPTH1 => depth(1), DEPTH2 => depth(2), DEPTH3 => depth(3),
WW0 => width(0), WW1 => width(1), WW2 => width(2), WCLK => wclk,
RDAD0 => ra(0), RDAD1 => ra(1), RDAD2 => ra(2), RDAD3 => ra(3),
RDAD4 => ra(4), RDAD5 => ra(5), RDAD6 => ra(6), RDAD7 => ra(7),
RDAD8 => ra(8), RDAD9 => ra(9), RDAD10 => ra(10), RDAD11 => ra(11),
RDAD12 => ra(12), RDAD13 => ra(13), RDAD14 => ra(14), RDAD15 => ra(15),
REN => ren, RW0 => width(0), RW1 => width(1), RW2 => width(2),
RCLK => rclk,
RD0 => q(0), RD1 => q(1), RD2 => q(2), RD3 => q(3), RD4 => q(4),
RD5 => q(5), RD6 => q(6), RD7 => q(7), RD8 => q(8), RD9 => q(9),
RD10 => q(10), RD11 => q(11), RD12 => q(12), RD13 => q(13), RD14 => q(14),
RD15 => q(15), RD16 => q(16), RD17 => q(17), RD18 => q(18), RD19 => q(19),
RD20 => q(20), RD21 => q(21), RD22 => q(22), RD23 => q(23), RD24 => q(24),
RD25 => q(25), RD26 => q(26), RD27 => q(27), RD28 => q(28), RD29 => q(29),
RD30 => q(30), RD31 => q(31), RD32 => q(32), RD33 => q(33), RD34 => q(34),
RD35 => q(35));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity axcel_syncram_2p is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of axcel_syncram_2p is
component axcel_ssram
generic (abits : integer := 16; dbits : integer := 36);
port (
wa, ra : in std_logic_vector(15 downto 0);
wclk, rclk : in std_ulogic;
di : in std_logic_vector(dbits -1 downto 0);
do : out std_logic_vector(dbits -1 downto 0);
width : in std_logic_vector(2 downto 0);
ren, wen : in std_ulogic
);
end component;
type dwtype is array (1 to 24) of integer;
constant dwmap : dwtype := (36, 36, 36, 36, 36, 36, 36, 18, 9, 4, 2, others => 1);
constant xbits : integer := dwmap(abits);
constant dw : integer := dbits + 36;
signal wen, gnd : std_ulogic;
signal ra, wa : std_logic_vector(31 downto 0);
signal d, q : std_logic_vector(dw downto 0);
signal ren : std_ulogic;
signal width : std_logic_vector(2 downto 0);
constant READFAST : std_ulogic := '0';
begin
width <= "101" when abits <= 7 else
"100" when abits = 8 else
"011" when abits = 9 else
"010" when abits = 10 else
"001" when abits = 11 else
"000";
wen <= write; ren <= rena or READFAST; gnd <= '0';
ra(31 downto abits) <= (others =>'0'); wa(31 downto abits) <= (others =>'0');
ra(abits-1 downto 0) <= raddr(abits-1 downto 0);
wa(abits-1 downto 0) <= waddr(abits-1 downto 0);
d(dw downto dbits) <= (others =>'0');
d(dbits-1 downto 0) <= din(dbits-1 downto 0);
dout <= q(dbits-1 downto 0);
a7 : if abits <= 7 generate
agen : for i in 0 to (dbits-1)/xbits generate
u0 : axcel_ssram
generic map (abits => 7, dbits => xbits)
port map (ra => ra(15 downto 0), wa => wa(15 downto 0),
di => d(xbits*(i+1)-1 downto xbits*i), wen => wen, width => width,
wclk => wclk, ren => ren, rclk => rclk,
do => q(xbits*(i+1)-1 downto xbits*i));
end generate;
end generate;
a8to12 : if (abits > 7) and (abits <= 12) generate
agen : for i in 0 to (dbits-1)/xbits generate
u0 : axcel_ssram
generic map (abits => abits, dbits => xbits)
port map (ra => ra(15 downto 0), wa => wa(15 downto 0),
di => d(xbits*(i+1)-1 downto xbits*i), wen => wen, width => width,
wclk => wclk, ren => ren, rclk => rclk,
do => q(xbits*(i+1)-1 downto xbits*i));
end generate;
end generate;
-- pragma translate_off
a_to_high : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for AX rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axcel_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of axcel_syncram is
component axcel_syncram_2p
generic ( abits : integer := 10; dbits : integer := 8 );
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
component axcel_ssram
generic (abits : integer := 16; dbits : integer := 36);
port (
wa, ra : in std_logic_vector(15 downto 0);
wclk, rclk : in std_ulogic;
di : in std_logic_vector(dbits -1 downto 0);
do : out std_logic_vector(dbits -1 downto 0);
width : in std_logic_vector(2 downto 0);
ren, wen : in std_ulogic
);
end component;
type d_type is array (0 to 3) of std_logic_vector(35 downto 0);
signal wen : std_logic_vector(3 downto 0);
signal q : d_type;
signal addr : std_logic_vector(15 downto 0);
signal addrreg : std_logic_vector(1 downto 0);
begin
a : if not ((abits = 10 or abits = 11) and dbits = 36) generate
u0 : axcel_syncram_2p generic map (abits, dbits)
port map (clk, enable, address, dataout, clk, address, datain, write);
end generate;
-- Special case for 4 or 8 KB cache with FT: 36x1024 or 2048: 2 or 4 banks of 4*9*512
a10to11d36 : if (abits = 10 or abits = 11) and dbits = 36 generate
addr_reg : process (clk)
begin
if rising_edge(clk) then addrreg(abits-10 downto 0) <= address(abits-1 downto 9); end if;
end process;
addr(15 downto 9) <= (others => '0');
addr(8 downto 0) <= address(8 downto 0);
decode : process (address, write)
variable vwen : std_logic_vector(3 downto 0);
begin
vwen := (others => '0');
if write = '1' then
vwen( to_integer(unsigned(address(abits-1 downto 9))) ) := '1';
end if;
wen <= vwen;
end process;
loop0 : for b in 0 to 2*(abits-9)-1 generate
agen0 : for i in 0 to 3 generate
u0 : axcel_ssram
generic map (abits => 9, dbits => 9)
port map (ra => addr, wa => addr,
di => datain(9*(i+1)-1 downto 9*i), wen => wen(b), width => "011",
wclk => clk, ren => enable, rclk => clk,
do => q(b)(9*(i+1)-1 downto 9*i));
end generate;
end generate;
dout10: if abits = 10 generate
dataout <= q(0) when addrreg(0)='0' else q(1);
end generate;
dout11: if abits = 11 generate
dataout <= q(0) when addrreg(1 downto 0)="00" else q(1) when addrreg(1 downto 0)="01" else
q(2) when addrreg(1 downto 0)="10" else q(3);
end generate;
end generate;
end;
| mit | 97c07be1b609b17155eabd12fbc0c2a8 | 0.567738 | 3.009113 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_iterated/Kernel/OutputGenerator.vhd | 1 | 7,696 | -------------------------------------------------------------------------------
--! @project Iterate hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OutputGenerator is
port(
In0 : in std_logic_vector(63 downto 0);
In1 : in std_logic_vector(63 downto 0);
DataIn : in std_logic_vector(127 downto 0);
Size : in std_logic_vector(3 downto 0);
Activate : in std_logic;
Out0 : out std_logic_vector(63 downto 0);
Out1 : out std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0));
end entity OutputGenerator;
architecture structural of OutputGenerator is
constant ALLZERO : std_logic_vector(127 downto 0) := (others => '0');
signal Temp0,Temp1,Temp2 : std_logic_vector(127 downto 0);
begin
Gen: process(In0,In1,DataIn,Size,Activate,Temp0,Temp1,Temp2) is
-- Truncator0&1
procedure doTruncate0 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(127 downto 0);
signal Size : in std_logic_vector(3 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(127 downto 0)) is
variable ActSize : std_logic_vector(4 downto 0);
begin
ActSize(4) := Activate;
ActSize(3 downto 0) := Size;
-- if inactive it lets everything trough, if active it lets the first blocksize bits trough
logic: case ActSize is
when "10001" =>
Output(127 downto 120) <= Input(127 downto 120);
Output(119) <= '1';
Output(118 downto 0) <= ALLZERO(118 downto 0);
when "10010" =>
Output(127 downto 112) <= Input(127 downto 112);
Output(111) <= '1';
Output(110 downto 0) <= ALLZERO(110 downto 0);
when "10011" =>
Output(127 downto 104) <= Input(127 downto 104);
Output(103) <= '1';
Output(102 downto 0) <= ALLZERO(102 downto 0);
when "10100" =>
Output(127 downto 96) <= Input(127 downto 96);
Output(95) <= '1';
Output(94 downto 0) <= ALLZERO(94 downto 0);
when "10101" =>
Output(127 downto 88) <= Input(127 downto 88);
Output(87) <= '1';
Output(86 downto 0) <= ALLZERO(86 downto 0);
when "10110" =>
Output(127 downto 80) <= Input(127 downto 80);
Output(79) <= '1';
Output(78 downto 0) <= ALLZERO(78 downto 0);
when "10111" =>
Output(127 downto 72) <= Input(127 downto 72);
Output(71) <= '1';
Output(70 downto 0) <= ALLZERO(70 downto 0);
when "11000" =>
Output(127 downto 64) <= Input(127 downto 64);
Output(63) <= '1';
Output(62 downto 0) <= ALLZERO(62 downto 0);
when "11001" =>
Output(127 downto 56) <= Input(127 downto 56);
Output(55) <= '1';
Output(54 downto 0) <= ALLZERO(54 downto 0);
when "11010" =>
Output(127 downto 48) <= Input(127 downto 48);
Output(47) <= '1';
Output(46 downto 0) <= ALLZERO(46 downto 0);
when "11011" =>
Output(127 downto 40) <= Input(127 downto 40);
Output(39) <= '1';
Output(38 downto 0) <= ALLZERO(38 downto 0);
when "11100" =>
Output(127 downto 32) <= Input(127 downto 32);
Output(31) <= '1';
Output(30 downto 0) <= ALLZERO(30 downto 0);
when "11101" =>
Output(127 downto 24) <= Input(127 downto 24);
Output(23) <= '1';
Output(22 downto 0) <= ALLZERO(22 downto 0);
when "11110" =>
Output(127 downto 16) <= Input(127 downto 16);
Output(15) <= '1';
Output(14 downto 0) <= ALLZERO(14 downto 0);
when "11111" =>
Output(127 downto 8) <= Input(127 downto 8);
Output(7) <= '1';
Output(6 downto 0) <= ALLZERO(6 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate0;
-- Truncator2
procedure doTruncate2 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(127 downto 0);
signal Size : in std_logic_vector(3 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(127 downto 0)) is
variable ActSize : std_logic_vector(4 downto 0);
begin
ActSize(4) := Activate;
ActSize(3 downto 0) := Size;
-- if inactive it lets everything trough, if active it blocks the first blocksize bits
logic: case ActSize is
when "10000" =>
Output <= ALLZERO;
when "10001" =>
Output(127 downto 120) <= ALLZERO(127 downto 120);
Output(119 downto 0) <= Input(119 downto 0);
when "10010" =>
Output(127 downto 112) <= ALLZERO(127 downto 112);
Output(111 downto 0) <= Input(111 downto 0);
when "10011" =>
Output(127 downto 104) <= ALLZERO(127 downto 104);
Output(103 downto 0) <= Input(103 downto 0);
when "10100" =>
Output(127 downto 96) <= ALLZERO(127 downto 96);
Output(95 downto 0) <= Input(95 downto 0);
when "10101" =>
Output(127 downto 88) <= ALLZERO(127 downto 88);
Output(87 downto 0) <= Input(87 downto 0);
when "10110" =>
Output(127 downto 80) <= ALLZERO(127 downto 80);
Output(79 downto 0) <= Input(79 downto 0);
when "10111" =>
Output(127 downto 72) <= ALLZERO(127 downto 72);
Output(71 downto 0) <= Input(71 downto 0);
when "11000" =>
Output(127 downto 64) <= ALLZERO(127 downto 64);
Output(63 downto 0) <= Input(63 downto 0);
when "11001" =>
Output(127 downto 56) <= ALLZERO(127 downto 56);
Output(55 downto 0) <= Input(55 downto 0);
when "11010" =>
Output(127 downto 48) <= ALLZERO(127 downto 48);
Output(47 downto 0) <= Input(47 downto 0);
when "11011" =>
Output(127 downto 40) <= ALLZERO(127 downto 40);
Output(39 downto 0) <= Input(39 downto 0);
when "11100" =>
Output(127 downto 32) <= ALLZERO(127 downto 32);
Output(31 downto 0) <= Input(31 downto 0);
when "11101" =>
Output(127 downto 24) <= ALLZERO(127 downto 24);
Output(23 downto 0) <= Input(23 downto 0);
when "11110" =>
Output(127 downto 16) <= ALLZERO(127 downto 16);
Output(15 downto 0) <= Input(15 downto 0);
when "11111" =>
Output(127 downto 8) <= ALLZERO(127 downto 8);
Output(7 downto 0) <= Input(7 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate2;
begin
-- DataOut
DataOut(127 downto 64) <= In0 xor DataIn(127 downto 64);
DataOut(63 downto 0) <= In1 xor DataIn(63 downto 0);
-- Stateupdate
doTruncate0(DataIn,Size,Activate,Temp0);
Temp1(127 downto 64) <= In0;
Temp1(63 downto 0) <= In1;
doTruncate2(Temp1,Size,Activate,Temp2);
Out0 <= Temp0(127 downto 64) xor Temp2(127 downto 64);
Out1 <= Temp0(63 downto 0) xor Temp2(63 downto 0);
end process Gen;
end architecture structural;
| gpl-3.0 | 53eeef630f3582f5262e546256c9d94d | 0.599792 | 3.346087 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/dac/dac_sigdelt.vhd | 2 | 1,853 | --*******************************************************************************
--
-- D/A Converter based on 1st order Delta-Sigma Modulator
--
-- Coded by and Private Property of Prof. Dr. Martin Schubert
--
-- 14. February 2005
--
-- FH Regensburg, Univ. of Applied Sciences
-- Seybothstrasse 2, D-93053 Regensburg
-- Email: [email protected]
--
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity sigdelt is
generic(c_dacin_length:positive:=8); -- length of binary input vector dac_in
port(
reset:in std_logic; -- resets integrator, high-active
clock:in std_logic; -- sampling clock
dac_in:in std_logic_vector(c_dacin_length-1 downto 0); -- input vector
dac_out:out std_logic -- pseudo-random output bit stream
);
end sigdelt;
architecture rtl of sigdelt is
signal delta:std_logic_vector(c_dacin_length+1 downto 0); -- input - feedback
signal state:std_logic_vector(c_dacin_length+1 downto 0); -- integrator's state vector
begin
--
delta(c_dacin_length+1)<=state(c_dacin_length+1);
delta(c_dacin_length) <=state(c_dacin_length+1);
delta(c_dacin_length-1 downto 0)<=dac_in;
--
-- integrator
pr_integrator:process(reset,clock)
begin
if reset='1' then
state<=(others=>'0');
elsif clock'event and clock='1' then
state<=state+delta;
end if;
end process pr_integrator;
--
-- generating a postponed flipflop
pr_postponed:process(reset,clock)
begin
if reset='1' then
dac_out<='0';
elsif clock'event and clock='1' then
dac_out<=state(c_dacin_length+1);
end if;
end process pr_postponed;
--
end rtl;
configuration con_sigdelt of sigdelt is
for rtl
end for;
end con_sigdelt;
| mit | 82777911de009be8a64c933d2e3c18b3 | 0.616838 | 3.387569 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/designs/leon3mp/testbench.vhd | 2 | 19,421 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.jtagtst.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : in std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "sram.srec"; -- ram contents
constant sdramfile : string := "sdram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART1 tx data
rxd2 : in std_ulogic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : in std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal can_stb : std_ulogic;
signal spw_clk : std_ulogic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal tck, tms, tdi, tdo : std_ulogic;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
--## can_rxd <= '1';
can_rxd <= can_txd; -- CAN LOOP BACK ##
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sbanks : for k in 0 to srambanks-1 generate
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
ramsn(k), rwen(i), ramoen(k));
end generate;
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;
| mit | a32c1018960422ff4724585fe8dca14d | 0.575048 | 3.019434 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/eth/core/eth_ahb_mst.vhd | 2 | 5,880 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: eth_ahb_mst
-- File: eth_ahb_mst.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Ethernet MAC AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end entity;
architecture rtl of eth_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
bo : std_ulogic; --bus owner, 0=rx, 1=tx
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, rmsti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable nbo : std_ulogic;
variable tretry : std_ulogic;
variable rretry : std_ulogic;
variable rready : std_ulogic;
variable tready : std_ulogic;
variable rerror : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable rgrant : std_ulogic;
begin
v := r; htrans := HTRANS_IDLE; rready := '0'; tready := '0'; tretry := '0';
rretry := '0'; rerror := '0'; terror := '0'; tgrant := '0'; rgrant := '0';
if r.bo = '0' then hwdata := rmsti.data;
else hwdata := tmsti.data; end if;
hbusreq := tmsti.req or rmsti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
if r.retry = '0' then
nbo := tmsti.req and not (rmsti.req and not r.bo);
else
nbo := r.bo;
end if;
if nbo = '0' then
haddr := rmsti.addr; hwrite := rmsti.write;
if (rmsti.req and r.ba and not r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (rmsti.req and r.bg and ahbmi.hready and not r.retry) = '1'
then rgrant := '1'; end if;
else
haddr := tmsti.addr; hwrite := tmsti.write;
if (tmsti.req and r.ba and r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (tmsti.req and r.bg and ahbmi.hready and not r.retry) = '1'
then tgrant := '1'; end if;
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.bo = '0' then
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => rready := '1';
when HRESP_SPLIT | HRESP_RETRY => rretry := '1';
when HRESP_ERROR => rerror := '1';
when others => null;
end case;
end if;
end if;
else
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => tready := '1';
when HRESP_SPLIT | HRESP_RETRY => tretry := '1';
when HRESP_ERROR => terror := '1';
when others => null;
end case;
end if;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bo := nbo; v.bg := ahbmi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bo := '0'; v.bb := '0';
end if;
rin <= v;
tmsto.data <= ahbmi.hrdata;
rmsto.data <= ahbmi.hrdata;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
rmsto.error <= rerror;
rmsto.retry <= rretry;
rmsto.ready <= rready;
tmsto.grant <= tgrant;
rmsto.grant <= rgrant;
ahbmo.htrans <= htrans;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= hwdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hsize <= HSIZE_WORD;
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
end architecture;
| mit | bb89d4580498a68e289c37ed76b20ddb | 0.555782 | 3.529412 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled3/Kernel/OutputGenerator.vhd | 1 | 5,097 | -------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OutputGenerator is
port(
In0 : in std_logic_vector(63 downto 0);
DataIn : in std_logic_vector(63 downto 0);
Size : in std_logic_vector(2 downto 0);
Activate : in std_logic;
Out0 : out std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(63 downto 0));
end entity OutputGenerator;
architecture structural of OutputGenerator is
constant ALLZERO : std_logic_vector(63 downto 0) := (others => '0');
signal Temp0,Temp1,Temp2 : std_logic_vector(63 downto 0);
begin
Gen: process(In0,DataIn,Size,Activate,Temp0,Temp1,Temp2) is
-- Truncator0&1
procedure doTruncate0 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it lets the first blocksize bits trough
logic: case ActSize is
when "1001" =>
Output(63 downto 56) <= Input(63 downto 56);
Output(55) <= '1';
Output(54 downto 0) <= ALLZERO(54 downto 0);
when "1010" =>
Output(63 downto 48) <= Input(63 downto 48);
Output(47) <= '1';
Output(46 downto 0) <= ALLZERO(46 downto 0);
when "1011" =>
Output(63 downto 40) <= Input(63 downto 40);
Output(39) <= '1';
Output(38 downto 0) <= ALLZERO(38 downto 0);
when "1100" =>
Output(63 downto 32) <= Input(63 downto 32);
Output(31) <= '1';
Output(30 downto 0) <= ALLZERO(30 downto 0);
when "1101" =>
Output(63 downto 24) <= Input(63 downto 24);
Output(23) <= '1';
Output(22 downto 0) <= ALLZERO(22 downto 0);
when "1110" =>
Output(63 downto 16) <= Input(63 downto 16);
Output(15) <= '1';
Output(14 downto 0) <= ALLZERO(14 downto 0);
when "1111" =>
Output(63 downto 8) <= Input(63 downto 8);
Output(7) <= '1';
Output(6 downto 0) <= ALLZERO(6 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate0;
-- Truncator2
procedure doTruncate2 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it blocks the first blocksize bits
logic: case ActSize is
when "1000" =>
Output <= ALLZERO;
when "1001" =>
Output(63 downto 56) <= ALLZERO(63 downto 56);
Output(55 downto 0) <= Input(55 downto 0);
when "1010" =>
Output(63 downto 48) <= ALLZERO(63 downto 48);
Output(47 downto 0) <= Input(47 downto 0);
when "1011" =>
Output(63 downto 40) <= ALLZERO(63 downto 40);
Output(39 downto 0) <= Input(39 downto 0);
when "1100" =>
Output(63 downto 32) <= ALLZERO(63 downto 32);
Output(31 downto 0) <= Input(31 downto 0);
when "1101" =>
Output(63 downto 24) <= ALLZERO(63 downto 24);
Output(23 downto 0) <= Input(23 downto 0);
when "1110" =>
Output(63 downto 16) <= ALLZERO(63 downto 16);
Output(15 downto 0) <= Input(15 downto 0);
when "1111" =>
Output(63 downto 8) <= ALLZERO(63 downto 8);
Output(7 downto 0) <= Input(7 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate2;
begin
-- DataOut
DataOut <= In0 xor DataIn;
-- Stateupdate
doTruncate0(DataIn,Size,Activate,Temp0);
Temp1 <= In0;
doTruncate2(Temp1,Size,Activate,Temp2);
Out0 <= Temp0 xor Temp2;
end process Gen;
end architecture structural;
| gpl-3.0 | a14320135e8fff9759e0292c3050d219 | 0.606828 | 3.382216 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/cache.vhd | 2 | 4,459 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cache
-- File: cache.vhd
-- Author: Jiri Gaisler
-- Description: Cache controllers and AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
entity cache is
generic (
hindex : integer := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
cached : integer := 0;
clk2x : integer := 0;
memtech : integer range 0 to NTECH := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of cache is
signal icol : icache_out_type;
signal dcol : dcache_out_type;
signal mcii : memory_ic_in_type;
signal mcio : memory_ic_out_type;
signal mcdi : memory_dc_in_type;
signal mcdo : memory_dc_out_type;
signal ahbsi2 : ahb_slv_in_type;
signal ahbi2 : ahb_mst_in_type;
signal ahbo2 : ahb_mst_out_type;
signal gnd : std_ulogic;
begin
icache0 : icache
generic map (icen, irepl, isets, ilinesize, isetsize, isetlock, ilram,
ilramsize, ilramstart)
port map ( rst, clk, ici, icol, dci, dcol, mcii, mcio,
crami.icramin, cramo.icramo, fpuholdn);
dcache0 : dcache
generic map (dsu, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop,
dlram, dlramsize, dlramstart, ilram, ilramstart, memtech, cached)
port map ( rst, clk, dci, dcol, icol, mcdi, mcdo, ahbsi2,
crami.dcramin, cramo.dcramo, fpuholdn, sclk);
a0 : acache
generic map (hindex, ilinesize, cached, clk2x, scantest)
port map (rst, clk, mcii, mcio, mcdi, mcdo, ahbi2, ahbo2, ahbso, hclken);
ico <= icol;
dco <= dcol;
clk2xgen: if clk2x /= 0 generate
sync0 : clk2xsync generic map (hindex, clk2x)
port map (rst, hclk, clk, ahbi, ahbi2, ahbo2, ahbo, ahbsi, ahbsi2, mcii, mcdi, mcdo, gnd, gnd, hclken);
gnd <= '0';
end generate;
noclk2x : if clk2x = 0 generate
ahbsi2 <= ahbsi;
ahbi2 <= ahbi;
ahbo <= ahbo2;
end generate;
end ;
| mit | ac9329fa05a735086fc007cefdb4ae1a | 0.593182 | 3.679043 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_dbus.vhd | 1 | 3,910 | ---------------------------------------------------------------------
-- DBUS master
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Manages data bus (DBUS) access.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_dbus is
generic(
RMW: boolean
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
valid_i: in std_logic;
cmd_dbus_i: in std_logic;
cmd_dbus_store_i: in std_logic;
cmd_dbus_byte_i: in std_logic;
cmd_signed_i: in std_logic;
addr_i: in std_logic_vector(31 downto 0);
wdata_i: in std_logic_vector(31 downto 0);
rdata_o: out std_logic_vector(31 downto 0);
we_o: out std_logic;
busy_o: out std_logic;
dbus_cyc_o: out std_logic;
dbus_stb_o: out std_logic;
dbus_we_o: out std_logic;
dbus_sel_o: out std_logic_vector(3 downto 0);
dbus_ack_i: in std_logic;
dbus_adr_o: out std_logic_vector(31 downto 2);
dbus_dat_o: out std_logic_vector(31 downto 0);
dbus_dat_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_dbus is
signal strobe: std_logic:='0';
signal we_out: std_logic:='0';
signal we: std_logic;
signal byte_mode: std_logic;
signal sel: std_logic_vector(3 downto 0);
signal sig: std_logic;
signal rmw_mode: std_logic;
signal dbus_rdata: std_logic_vector(31 downto 0);
signal selected_byte: std_logic_vector(7 downto 0);
begin
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
we_out<='0';
strobe<='0';
sig<='-';
byte_mode<='-';
sel<=(others=>'-');
we<='-';
rmw_mode<='-';
dbus_adr_o<=(others=>'-');
dbus_dat_o<=(others=>'-');
else
we_out<='0';
if strobe='0' then
if valid_i='1' and cmd_dbus_i='1' then
strobe<='1';
sig<=cmd_signed_i;
dbus_adr_o<=addr_i(31 downto 2);
if cmd_dbus_byte_i='0' then
byte_mode<='0';
dbus_dat_o<=wdata_i;
sel<="1111";
-- synthesis translate_off
assert addr_i(1 downto 0)="00"
report "Misaligned word-granular access on data bus"
severity warning;
-- synthesis translate_on
else
byte_mode<='1';
dbus_dat_o<=wdata_i(7 downto 0)&wdata_i(7 downto 0)&
wdata_i(7 downto 0)&wdata_i(7 downto 0);
case addr_i(1 downto 0) is
when "00" => sel<="0001";
when "01" => sel<="0010";
when "10" => sel<="0100";
when "11" => sel<="1000";
when others =>
end case;
end if;
if not RMW then
we<=cmd_dbus_store_i;
rmw_mode<='0';
else
we<=cmd_dbus_store_i and not cmd_dbus_byte_i;
rmw_mode<=cmd_dbus_store_i and cmd_dbus_byte_i;
end if;
end if;
else
if dbus_ack_i='1' then
if rmw_mode='1' and we='0' and RMW then
we<='1';
for i in sel'range loop
if sel(i)='0' then
dbus_dat_o(i*8+7 downto i*8)<=
dbus_dat_i(i*8+7 downto i*8);
end if;
end loop;
else
strobe<='0';
if we='0' then
we_out<='1';
end if;
end if;
end if;
end if;
end if;
end if;
end process;
dbus_cyc_o<=strobe;
dbus_stb_o<=strobe;
dbus_we_o<=we;
sel_no_rmw_gen: if not RMW generate
dbus_sel_o<=sel;
end generate;
sel_rmw_gen: if RMW generate
dbus_sel_o<=(others=>'1');
end generate;
process (clk_i) is
begin
if rising_edge(clk_i) then
dbus_rdata<=dbus_dat_i;
end if;
end process;
selected_byte_gen: for i in selected_byte'range generate
selected_byte(i)<=(dbus_rdata(i) and sel(0)) or
(dbus_rdata(i+8) and sel(1)) or
(dbus_rdata(i+16) and sel(2)) or
(dbus_rdata(i+24) and sel(3));
end generate;
rdata_o<=dbus_rdata when byte_mode='0' else
X"000000"&selected_byte when selected_byte(selected_byte'high)='0' or sig='0' else
X"FFFFFF"&selected_byte;
we_o<=we_out;
busy_o<=strobe or we_out;
end architecture;
| mit | fc9c2e1269146c71c068d3866a2011d2 | 0.578772 | 2.707756 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcitb_master_script.vhd | 2 | 31,269 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_master_script
-- File: pcitb_master_script.vhd
-- Author: Kristoffer Glembo, Alf Vaerneus, Gaisler Research
-- Description: PCI Master emulator. Can act as a system host
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.pcitb.all;
use gaisler.pcilib.all;
use gaisler.ambatest.all;
entity pcitb_master_script is
generic (
slot : integer := 0;
tval : time := 7 ns;
dbglevel : integer := 2;
maxburst : integer := 1024;
filename : string := "pci.cmd");
port (
pciin : in pci_type;
pciout : out pci_type);
end pcitb_master_script;
architecture behav of pcitb_master_script is
type cmd_state_type is (idle, parse, execute, done, finished);
type pci_data_type is record
data : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
ws : integer;
end record;
type databuf_type is array (0 to maxburst) of pci_data_type;
type cmd_type is (rcfg, wcfg, rmem, wmem, idle, comp, ill, print, estop, stop);
type command is record
cmd : cmd_type;
pcicmd: std_logic_vector(3 downto 0);
addr : std_logic_vector(31 downto 0);
len : integer;
file1 : string(1 to 18);
file2 : string(1 to 18);
msg : string(1 to 80);
check : integer; -- 0 ignore, 1 check, 2 save to file
estop : integer;
data : databuf_type;
pci : boolean;
started : std_logic;
done : std_logic;
end record;
type script_reg_type is record
cmd_state : cmd_state_type;
cmd_done : std_logic;
idle_count : integer;
cmd_count : integer;
end record;
signal sr,srin : script_reg_type;
signal cmd : command;
file cmd_file : text open read_mode is filename;
---------------------------------
--- PCI MASTER TYPES AND SIGNALS
---------------------------------
constant T_O : integer := 9;
constant INT_ACK : word4 := "0000";
constant SPEC_CYCLE : word4 := "0001";
constant IO_READ : word4 := "0010";
constant IO_WRITE : word4 := "0011";
constant MEM_READ : word4 := "0110";
constant MEM_WRITE : word4 := "0111";
constant CONF_READ : word4 := "1010";
constant CONF_WRITE : word4 := "1011";
constant MEM_R_MULT : word4 := "1100";
constant DAC : word4 := "1101";
constant MEM_R_LINE : word4 := "1110";
constant MEM_W_INV : word4 := "1111";
type state_type is(idle,active,done);
type status_type is (OK, ERR, TIMEOUT, RETRY);
type reg_type is record
state : state_type;
pcien : std_logic_vector(3 downto 0);
paren : std_logic;
read : std_logic;
burst : std_logic;
grant : std_logic;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
current_word : integer;
tocnt : integer;
running : std_logic;
pci : pci_type;
ready : std_logic;
last : std_logic;
f_open : std_logic;
ws_count : integer;
ws_done : boolean;
status : status_type;
end record;
signal r,rin : reg_type;
----------------------------------------------------------------
-- PROCEDURES
----------------------------------------------------------------
function cbe2mask(cbe : std_logic_vector(3 downto 0)) return std_logic_vector is
variable mask : std_logic_vector(31 downto 0);
begin
for i in 0 to 3 loop
mask((i+1)*8-1 downto i*8) := (others => cbe(i));
end loop;
return mask;
end cbe2mask;
function strlen(str : string) return integer is
variable i : integer;
begin
i := 1;
while (str(i) /= ' ' and str(i) /= nul) loop
i := i+1;
end loop;
return i-1;
end strlen;
procedure get_param(str : string; tok : character; param : out string; index : out integer; done : out boolean) is
variable start_i, end_i : integer;
begin
start_i := str'left;
while str(start_i) = ' ' and start_i <= str'right loop
start_i := start_i + 1;
end loop;
end_i := start_i;
while end_i <= str'right loop
if str(end_i) = ' ' or str(end_i) = ';' or str(end_i) = nul or str(end_i) = tok then
exit;
end if;
end_i := end_i + 1;
end loop;
param(1 to (end_i-start_i)) := str(start_i to end_i-1);
for i in end_i-start_i+1 to param'length loop
param(i) := ' ';
end loop;
-- param(end_i-start_i+1 to param'length) := (others => ' ');
if str(end_i) = ';' or str(end_i) = nul or end_i = str'right then
done := true;
else
done := false;
end if;
index := end_i+1;
end get_param;
procedure parse_cmd(file cmdfile : text; c : out command) is
variable L : line;
variable line : string(1 to 80);
variable cmdname : string(1 to 5);
variable i,k : integer;
variable done : boolean;
variable tmp : string(1 to 8);
variable tmpstr : string(1 to 18);
variable slvlen : std_logic_vector(31 downto 0);
variable len : integer;
file datafile : text;
begin
while not endfile(cmdfile) loop
c.check := 0;
c.data(0).cbe := "0000";
c.data(0).ws := 0;
done := false;
line := (others => nul);
tmp := (others => nul);
tmpstr := (others => nul);
line := (others => nul);
readline(cmdfile, L);
if L'length < cmdname'length then
read(L, cmdname(1 to L'length));
else
read(L, cmdname);
end if;
if cmdname(1) = ' ' or cmdname(1) = '#' or cmdname(1) = nul or cmdname(1) = cr then
next;
elsif cmdname = "rcfg " then
c.cmd := rcfg;
c.pci := true;
c.len := 1;
c.pcicmd := CONF_READ;
read(L, line(1 to L'length));
get_param(line, ' ', tmp, i, done);
c.addr := conv_std_logic_vector(tmp, 32);
get_param(line(i to line'length), ' ', tmp, i, done);
if tmp(1) = '*' then
c.check := 0;
else
c.check := 1;
c.data(0).data := conv_std_logic_vector(tmp, 32);
end if;
exit;
elsif cmdname = "wcfg " then
c.cmd := wcfg;
c.pci := true;
c.len := 1;
c.pcicmd := CONF_WRITE;
read(L, line(1 to L'length));
get_param(line, ' ', tmp, i, done);
c.addr := conv_std_logic_vector(tmp, 32);
get_param(line(i to line'length), '.', tmp, i, done);
c.data(0).data := conv_std_logic_vector(tmp, 32);
get_param(line(i to line'length), ' ', tmp, i, done);
c.data(0).cbe := conv_std_logic_vector(tmp, 4);
exit;
elsif cmdname = "rmem " then
c.cmd := rmem;
c.pci := true;
read(L, line(1 to L'length));
-- Get read command
get_param(line, ' ', tmp, i, done);
c.pcicmd := conv_std_logic_vector(tmp, 4);
-- Get read addr
get_param(line(i to line'length), ' ', tmp, i, done);
c.addr := conv_std_logic_vector(tmp, 32);
-- Get read length
get_param(line(i to line'length), ' ', tmp, i, done);
len := to_integer( unsigned(conv_std_logic_vector(tmp, 16)) );
c.len := len;
-- Get check data
get_param(line(i to line'length), ' ', tmpstr, i, done);
if tmpstr(1) = '*' then
c.check := 0;
elsif tmpstr(1) = '{' then
c.check := 1;
for j in 1 to line'length loop
line(j) := nul;
end loop;
for j in 0 to len-1 loop
tmpstr := (others => nul);
line := (others => nul);
readline(cmdfile, L);
read(L, line(1 to L'length));
get_param(line, '.', tmpstr, i, done);
c.data(j).data := conv_std_logic_vector(tmpstr(1 to 8), 32);
get_param(line(i to line'length), '.', tmpstr, i, done);
c.data(j).cbe := conv_std_logic_vector(tmpstr(1 to 8), 4);
if not done then
get_param(line(i to line'length), ' ', tmpstr, i, done);
c.data(j).ws := to_integer( unsigned(conv_std_logic_vector(tmpstr(1 to 8), 4)) );
else
c.data(j).ws := 0;
end if;
end loop;
readline(cmdfile, L);
else
c.check := 2;
c.file1 := tmpstr;
end if;
exit;
elsif cmdname = "wmem " then
c.cmd := wmem;
c.pci := true;
read(L, line(1 to L'length));
-- Get write command
get_param(line, ' ', tmp, i, done);
c.pcicmd := conv_std_logic_vector(tmp, 4);
-- Get write addr
get_param(line(i to line'length), ' ', tmp, i, done);
c.addr := conv_std_logic_vector(tmp, 32);
-- Get write length
get_param(line(i to line'length), ' ', tmp, i, done);
len := to_integer( unsigned(conv_std_logic_vector(tmp, 16)) );
c.len := len;
-- Get data
get_param(line(i to line'length), ' ', tmpstr, i, done);
if tmpstr(1) = '{' then
for j in 1 to line'length loop
line(j) := nul;
end loop;
for j in 0 to len-1 loop
tmpstr := (others => nul);
line := (others => nul);
readline(cmdfile, L);
read(L, line(1 to L'length));
get_param(line, '.', tmpstr, i, done);
c.data(j).data := conv_std_logic_vector(tmpstr(1 to 8), 32);
get_param(line(i to line'length), '.', tmpstr, i, done);
c.data(j).cbe := conv_std_logic_vector(tmpstr(1 to 8), 4);
if not done then
get_param(line(i to line'length), ' ', tmpstr, i, done);
c.data(j).ws := to_integer( unsigned(conv_std_logic_vector(tmpstr(1 to 8), 4)) );
else
c.data(j).ws := 0;
end if;
end loop;
readline(cmdfile, L);
else
c.file1 := tmpstr;
file_open(datafile, tmpstr(1 to strlen(tmpstr)), read_mode);
for j in 0 to len-1 loop
tmpstr := (others => nul);
line := (others => nul);
readline(datafile, L);
read(L, line(1 to L'length));
get_param(line, '.', tmpstr, i, done);
c.data(j).data := conv_std_logic_vector(tmpstr(1 to 8), 32);
get_param(line(i to line'length), '.', tmpstr, i, done);
c.data(j).cbe := conv_std_logic_vector(tmpstr(1 to 8), 4);
if not done then
get_param(line(i to line'length), ' ', tmpstr, i, done);
c.data(j).ws := to_integer( unsigned(conv_std_logic_vector(tmpstr(1 to 8), 4)) );
else
c.data(j).ws := 0;
end if;
end loop;
file_close(datafile);
end if;
exit;
elsif cmdname = "wait " then
c.cmd := idle;
c.pci := false;
read(L, c.len);
exit;
elsif cmdname = "comp " then
c.cmd := comp;
c.pci := false;
read(L, line(1 to L'length));
get_param(line, ' ', c.file1, i, done);
assert done = false report "Illegal compare statement. Missing file2";
get_param(line(i to line'length), ' ', c.file2, i, done);
assert done = true report "Illegal compare statement. Missing ;";
exit;
elsif cmdname(1 to 4) = "stop" then
c.cmd := stop;
c.pci := false;
exit;
elsif cmdname = "estop" then
c.cmd := estop;
c.pci := false;
read(L, c.estop);
exit;
elsif cmdname = "print" then
c.cmd := print;
c.pci := false;
read(L, line(1 to L'length));
i := 1;
while line(i) /= ';' and line(i) /= nul loop
i := i + 1;
end loop;
c.msg(1 to i-1) := line(1 to i-1);
c.msg(i to 80) := (others => nul);
exit;
elsif cmdname(1 to 4) = "halt" then
print ("");
assert false report "*** Simulation ended by halt command in pcitb_master_script ***" severity failure;
print ("");
else
c.cmd := ill;
exit;
end if;
end loop;
end parse_cmd;
begin
script_comb : process(sr, cmd, r, pciin)
variable vcmd : command;
variable v : script_reg_type;
variable err : boolean;
begin
v := sr;
vcmd := cmd;
case sr.cmd_state is
when idle =>
v.cmd_state := parse;
when parse =>
if cmd.started = '0' then
parse_cmd(cmd_file, vcmd);
vcmd.started := '1';
if vcmd.cmd /= print and dbglevel >= 2 then
printf("");
printf("Command #%d ", sr.cmd_count+1, timestamp => true);
end if;
case vcmd.cmd is
when idle =>
if dbglevel >= 2 then
printf("Waiting for %d cycles.", vcmd.len);
end if;
when comp =>
if dbglevel >= 2 then
printf("Comparing %s", vcmd.file1(1 to strlen(vcmd.file1)) & " to " & vcmd.file2(1 to strlen(vcmd.file2)));
end if;
when rcfg =>
if dbglevel >= 2 then
printf("Configuration read");
printf(" Address: 0x%x", vcmd.addr);
end if;
when wcfg =>
if dbglevel >= 2 then
printf("Configuration write");
printf(" Address: 0x%x", vcmd.addr);
printf(" Data : 0x%x", vcmd.data(0).data);
printf(" CBE : 0x%x", vcmd.data(0).cbe);
end if;
when rmem =>
if dbglevel >= 2 then
if vcmd.pcicmd = MEM_READ then
printf("Memory read");
elsif vcmd.pcicmd = MEM_R_MULT then
printf("Memory read multiple");
else
printf("Memory read line");
end if;
printf(" Address: 0x%x", vcmd.addr);
printf(" Length : %x", vcmd.len);
end if;
when wmem =>
if dbglevel >= 2 then
if vcmd.pcicmd = MEM_WRITE then
printf("Memory write");
else
printf("Memory write and invalidate");
end if;
printf(" Address: 0x%x", vcmd.addr);
printf(" Length : %x", vcmd.len);
if (vcmd.len = 1) then
printf(" Data : 0x%x", vcmd.data(0).data);
printf(" CBE : 0x%x", vcmd.data(0).cbe);
end if;
end if;
when print =>
printf(vcmd.msg);
when stop =>
if dbglevel >= 1 then
printf("PCI Testmaster done with scriptfile");
end if;
when others => vcmd.done := '1';
end case;
end if;
v.cmd_state := execute;
when execute =>
if vcmd.done = '0' then
case vcmd.cmd is
when idle =>
if sr.idle_count < vcmd.len then
v.idle_count := sr.idle_count + 1;
else
vcmd.done := '1';
end if;
when comp =>
compfiles(vcmd.file1, vcmd.file2, 1, dbglevel, err);
if cmd.estop = 1 then
printf("");
assert err = false
report "Simulation ended due to data compare failure!"
severity FAILURE;
end if;
vcmd.done := '1';
when rcfg =>
if r.ready = '1' then
vcmd.done := '1';
end if;
when wcfg =>
if r.ready = '1' then
vcmd.done := '1';
end if;
when rmem =>
if r.ready = '1' then
vcmd.done := '1';
end if;
when wmem =>
if r.ready = '1' then
vcmd.done := '1';
end if;
when stop =>
v.cmd_state := finished;
vcmd.done := '1';
when others => vcmd.done := '1';
end case;
end if;
v.cmd_done := vcmd.done;
if sr.cmd_done = '1' and vcmd.cmd /= stop then
v.cmd_count := sr.cmd_count + 1;
v.cmd_state := done;
end if;
when done =>
vcmd.started := '0';
vcmd.done := '0';
v.cmd_done := '0';
v.cmd_state := idle;
v.idle_count := 0;
when others => null;
end case;
if pciin.syst.rst = '0' then
vcmd.started := '0';
vcmd.done := '0';
vcmd.estop := 0;
v.cmd_state := idle;
v.idle_count := 0;
v.cmd_count := 0;
end if;
cmd <= vcmd;
srin <= v;
end process;
script_regs : process(pciin.syst.clk)
begin
if rising_edge(pciin.syst.clk) then
sr <= srin;
end if;
end process;
-----------------------------------------
-- PCI MASTER
-----------------------------------------
pci_master_comb : process(cmd, pciin)
variable vpci : pci_type;
variable v : reg_type;
variable i,count,dataintrans : integer;
variable status : status_type;
variable ready,stop : std_logic;
variable comm : std_logic_vector(3 downto 0);
begin
v := r; count := count+1; v.tocnt := 0; ready := '0'; stop := '0';
v.pcien(0) := '1'; v.pcien(3 downto 1) := r.pcien(2 downto 0);
if cmd.started = '1' and cmd.pci = true then
if (r.running = '0' and r.state = idle) then
v.address := cmd.addr(31 downto 2) & "00";
status := OK;
v.running := '1';
end if;
case cmd.pcicmd is
when MEM_READ =>
v.burst := '0';
v.read := '1';
comm := MEM_READ;
when MEM_R_MULT =>
v.burst := '1';
v.read := '1';
comm := MEM_R_MULT;
when MEM_R_LINE =>
v.burst := '1';
v.read := '1';
comm := MEM_R_LINE;
when MEM_WRITE =>
if cmd.len = 1 then
v.burst := '0';
else
v.burst := '1';
end if;
v.read := '0';
comm := MEM_WRITE;
when MEM_W_INV =>
v.burst := '1';
v.read := '0';
comm := MEM_W_INV;
when CONF_READ =>
v.burst := '0';
v.read := '1';
comm := CONF_READ;
when CONF_WRITE =>
v.burst := '0';
v.read := '0';
comm := CONF_WRITE;
when others =>
end case;
v.address := (cmd.addr(31 downto 2) + conv_std_logic_vector(v.current_word,30)) & "00";
comm := cmd.pcicmd;
v.pci.ad.ad := cmd.data(v.current_word).data;
v.burst := not r.last;
stop := r.last;
end if;
v.pci.ad.par := xorv(r.pci.ad.ad & r.pci.ad.cbe);
v.paren := r.read;
if (pciin.ifc.devsel and not pciin.ifc.stop) = '1' and r.running = '1' then
status := ERR;
elsif r.tocnt = T_O then
status := TIMEOUT;
else
status := OK;
end if;
case r.state is
when idle =>
v.ws_count := 0;
v.ws_done := false;
v.pci.arb.req(slot) := not (r.running and r.pcien(1));
v.pci.ifc.irdy := '1'; dataintrans := 0;
if r.grant = '1' then
v.state := active; v.pci.ifc.frame := '0'; v.read := '0';
v.pcien(0) := '0'; v.pci.ad.ad := v.address; v.pci.ad.cbe := comm;
end if;
when active =>
v.tocnt := r.tocnt + 1; v.pcien(0) := '0';
v.pci.ad.cbe := cmd.data(v.current_word).cbe;
v.pci.arb.req(slot) := not (r.burst and not pciin.ifc.frame);
if (pciin.ifc.irdy or (pciin.ifc.trdy and pciin.ifc.stop)) = '0' then
if pciin.ifc.trdy = '0' then
v.current_word := r.current_word+1;
v.data := pciin.ad.ad;
v.pci.ad.ad := cmd.data(v.current_word).data;
v.pci.ad.cbe := cmd.data(v.current_word).cbe;
dataintrans := dataintrans+1;
v.ws_count := 0;
v.ws_done := false;
end if;
end if;
-- Wait state insertion
if v.ws_done or r.ws_count = cmd.data(v.current_word).ws then
v.pci.ifc.irdy := '0';
v.ws_count := 0;
v.ws_done := true;
else
v.pci.ifc.irdy := '1';
v.ws_count := r.ws_count + 1;
end if;
if pciin.ifc.devsel = '0' then v.tocnt := 0; end if;
if pciin.ifc.stop = '0' then
v.pcien(0) := pciin.ifc.frame; stop := '1'; v.state := idle; v.pci.ifc.irdy := pciin.ifc.frame;
end if;
if (r.status /= OK or ((pciin.ifc.frame and not pciin.ifc.irdy and not pciin.ifc.trdy) = '1')) then
v.state := done; v.pci.ifc.irdy := '1'; v.pcien(0) := '1'; v.pci.arb.req(slot) := '1';
end if;
v.pci.ifc.frame := not (r.burst and not stop);
when done =>
v.running := '0'; ready := '1';
if cmd.started = '0' and cmd.pci = true then
v.state := idle;
v.current_word := 0;
end if;
when others =>
end case;
v.grant := to_x01(pciin.ifc.frame) and to_x01(pciin.ifc.irdy) and not r.pci.arb.req(slot) and not to_x01(pciin.arb.gnt(slot));
if pciin.syst.rst = '0' then
v.ws_count := 0;
v.ws_done := false;
v.pcien := (others => '1');
v.state := idle;
v.read := '0';
v.burst := '0';
v.grant := '0';
v.address := (others => '0');
v.data := (others => '0');
v.current_word := 0;
v.running := '0';
v.pci := pci_idle;
end if;
v.ready := ready;
v.status := status;
rin <= v;
end process;
pci_master_reg : process(pciin.syst)
file writefile : text;
variable L : line;
variable datahex : string(1 to 8);
variable count : integer;
begin
if pciin.syst.rst = '0' then
r.last <= '0';
r.f_open <= '0';
r.pcien <= (others => '1');
r.state <= idle;
r.read <= '0';
r.burst <= '0';
r.grant <= '0';
r.address <= (others => '0');
r.data <= (others => '0');
r.current_word <= 0;
r.running <= '0';
r.pci <= pci_idle;
elsif rising_edge(pciin.syst.clk) then
r <= rin;
if r.state = active and rin.pci.ifc.irdy = '0' then
if cmd.len = 2 then
if rin.current_word = 1 then
r.last <= '1';
r.pci.ifc.frame <= '1';
r.running <= '0';
else
r.last <= '0';
end if;
elsif cmd.len = 1 or r.current_word >= (cmd.len-2) then
r.last <= '1';
r.pci.ifc.frame <= '1';
r.running <= '0';
end if;
else
r.last <= '0';
end if;
case r.state is
when idle =>
count := 0;
if cmd.check = 2 and (cmd.started and not r.f_open) = '1' then
file_open(writefile, cmd.file1(1 to strlen(cmd.file1)), write_mode);
r.f_open <= '1';
end if;
when active =>
if (pciin.ifc.trdy or pciin.ifc.irdy) = '0' then
if cmd.check = 2 then
write(L,printhex(pciin.ad.ad,32));
writeline(writefile,L);
elsif cmd.check = 1 then
if (pciin.ad.ad and not cbe2mask(cmd.data(count).cbe)) /= (cmd.data(count).data and not cbe2mask(cmd.data(count).cbe)) then
if dbglevel >= 1 then
printf("Comparision error at data phase: %d",count+1);
printf(" Expected data: %d", cmd.data(count).data);
printf(" Expected cbe: %d", to_integer(unsigned(cmd.data(count).cbe)));
printf(" Compared data: %d", pciin.ad.ad);
printf("");
assert cmd.estop /= 1
report "Simulation ended due to data compare failure!"
severity FAILURE;
end if;
end if;
end if;
count := count + 1;
end if;
if cmd.check = 2 and rin.state = done then
file_close(writefile);
r.f_open <= '0';
end if;
when others =>
end case;
end if;
end process;
pciout.ad.ad <= r.pci.ad.ad after tval when (r.read or r.pcien(0)) = '0' else (others => 'Z') after tval;
pciout.ad.cbe <= r.pci.ad.cbe after tval when r.pcien(0) = '0' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.paren or r.pcien(1)) = '0' else 'Z' after tval;
pciout.ifc.frame <= r.pci.ifc.frame after tval when r.pcien(0) = '0' else 'Z' after tval;
pciout.ifc.irdy <= r.pci.ifc.irdy after tval when r.pcien(1) = '0' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when r.pcien(2) = '0' else 'Z' after tval;
pciout.err.serr <= r.pci.err.serr after tval when r.pcien(2) = '0' else 'Z' after tval;
pciout.arb.req(slot) <= r.pci.arb.req(slot) after tval;
end;
-- pragma translate_on
| mit | 677089ae3c114a06e7f2d8aa672ce8bc | 0.412773 | 4.108936 | false | false | false | false |
christakissgeo/Matrix-Vector-Multiplication | VHDL Files/2vectortestbench.vhd | 1 | 3,489 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity testbench is
end testbench;
architecture final_testbench of testbench is
component project2
port (
clock : in std_logic;
reset : in std_logic;
valid : in std_logic;
hold_me : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (18 downto 0);
hold_prev : out std_logic
);
end component project2;
signal clock : std_logic := '0';
signal reset : std_logic := '1';
signal valid : std_logic := '0';
signal datain : std_logic_vector (7 downto 0);
signal dataout : std_logic_vector (18 downto 0);
signal hold_me : std_logic;
signal hold_prev:std_logic;
begin
--MAP TO COMPONENT
project_map : project2 port map ( clock => clock,
reset => reset,
valid => valid,
hold_me => hold_me,
data_in => datain,
data_out => dataout,
hold_prev => hold_prev
);
--SET CLOCK PERIOD
process
begin
clock <= '1';
wait for 1 ns;
clock <='0';
wait for 1 ns;
end process;
--STARTING WITH RESET
process
begin
reset <= '1';
wait for 8 ns;
reset <= '0';
wait for 188 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait;
end process;
--INITIALIZE THE INPUT AND SEND IT
process
begin
hold_me <= '0';
wait for 12 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "10000000";
valid <= '1';
wait for 2 ns;
valid <='0';
--------------------------------------------
--2nd vector
wait for 170 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 2 ns;
datain <= "01111111";
valid <= '1';
wait for 2 ns;
valid <='0';
wait for 170 ns;
valid <= '1';
datain <= "01010101";
wait for 2 ns;
valid <= '0';
--TELOS
wait;
end process;
end architecture final_testbench;
| mit | b6da3da613906bbe73c76aeaf5495842 | 0.470909 | 3.082155 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/designs/leon3mp/leon3mp.vhd | 2 | 29,540 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emddis : out std_logic;
epwrdwn : out std_ulogic;
ereset : out std_ulogic;
esleep : out std_ulogic;
epause : out std_ulogic;
pci_rst : in std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_ulogic;
signal lclk, pci_lclk : std_ulogic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
attribute sync_set_reset : string;
attribute sync_set_reset of rstn : signal is "true";
constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64, pageburst => CFG_SDCTRL_PAGE)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data(31 downto 0), sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm(7 downto 0));
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo3.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo3.sdcsn);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(5) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 14, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
swloop : for i in 0 to CFG_SPW_NUM-1 generate
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => 0, ports => 1, dmachan => 1,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW)
port map(resetn, clkm, spw_lclk, ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), spwi(i).d(0));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), spwi(i).s(0));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_version
generic map (
msg1 => "LEON3 MP Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| mit | aa348f1dcb785343e48b727bdd21a705 | 0.567705 | 3.451741 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/resultMemory.vhd | 1 | 5,307 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY grlib;
USE grlib.amba.all;
USE grlib.stdlib.all;
LIBRARY gaisler;
USE grlib.devices.all;
USE gaisler.memctrl.all;
LIBRARY techmap;
USE techmap.gencomp.all;
ENTITY ddrspa IS
GENERIC (
fabtech : integer := virtex2;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 3;
haddr : integer := 1024;
hmask : integer := 3072;
ioaddr : integer := 1;
iomask : integer := 4095;
MHz : integer := 100;
clkmul : integer := 18;
clkdiv : integer := 20;
col : integer := 9;
Mbyte : integer := 256;
rstdel : integer := 200;
pwron : integer := 1;
oepol : integer := 0;
ddrbits : integer := 64;
ahbfreq : integer := 65
);
PORT (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic;
clkddro : out std_ulogic;
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector ( 2 downto 0 );
ddr_clkb : out std_logic_vector ( 2 downto 0 );
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector ( 1 downto 0 );
ddr_csb : out std_logic_vector ( 1 downto 0 );
ddr_web : out std_ulogic;
ddr_rasb : out std_ulogic;
ddr_casb : out std_ulogic;
ddr_dm : out std_logic_vector ( 64 / 8 - 1 downto 0 );
ddr_dqs : inout std_logic_vector ( 64 / 8 - 1 downto 0 );
ddr_ad : out std_logic_vector ( 13 downto 0 );
ddr_ba : out std_logic_vector ( 1 downto 0 );
ddr_dq : inout std_logic_vector ( 64 - 1 downto 0 )
);
END ENTITY;
ARCHITECTURE rtl OF ddrspa IS
CONSTANT DDR_FREQ : integer := ( 18 * 100 ) / 20;
CONSTANT FAST_AHB : integer := 65 / ( 18 * 100 ) / 20;
SIGNAL sdi : sdctrl_in_type;
SIGNAL sdo : sdctrl_out_type;
SIGNAL clkread : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL modahbsi : ahb_slv_in_type;
SIGNAL currentAddress : std_logic_vector ( 31 downto 0 );
SIGNAL newAddCon : std_ulogic;
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
BEGIN
hackNewAddControl : PROCESS ( clk_ahb )
BEGIN
IF ( rising_edge ( clk_ahb ) ) THEN
IF ( ahbsi.hsel ( 3 ) = '1' and ahbsi.hwrite = '1' and ahbsi.htrans ( 1 ) = '1' and ahbsi.hready = '1' ) THEN
currentAddress <= ahbsi.haddr;
newAddCon <= '1';
ELSE
newAddCon <= '0';
END IF;
END IF;
END PROCESS;
hackTrigger : PROCESS ( clk_ahb )
BEGIN
IF ( rising_edge ( clk_ahb ) ) THEN
IF ( newAddCon = '1' ) THEN
IF ( ahbsi.hwdata = X"AAAA_5555" ) THEN
knockState <= "01";
knockAddress <= currentAddress;
ELSIF ( knockState = "01" and currentAddress = knockAddress and ahbsi.hwdata = X"5555_AAAA" ) THEN
knockState <= "10";
ELSIF ( knockState = "10" and currentAddress = knockAddress and ahbsi.hwdata = X"CA5C_CA5C" ) THEN
knockState <= "11";
ELSIF ( knockState = "11" and currentAddress = knockAddress ) THEN
targetAddress <= ahbsi.hwdata;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
END PROCESS;
modahbsi.hsel <= ahbsi.hsel;
modahbsi.haddr <= ahbsi.haddr WHEN ( ahbsi.haddr /= catchAddress ) ELSE targetAddress;
modahbsi.hwrite <= ahbsi.hwrite;
modahbsi.htrans <= ahbsi.htrans;
modahbsi.hsize <= ahbsi.hsize;
modahbsi.hburst <= ahbsi.hburst;
modahbsi.hwdata <= ahbsi.hwdata;
modahbsi.hprot <= ahbsi.hprot;
modahbsi.hready <= ahbsi.hready;
modahbsi.hmaster <= ahbsi.hmaster;
modahbsi.hmastlock <= ahbsi.hmastlock;
modahbsi.hmbsel <= ahbsi.hmbsel;
modahbsi.hcache <= ahbsi.hcache;
modahbsi.hirq <= ahbsi.hirq;
ddr_phy0 : COMPONENT ddr_phy
GENERIC MAP (
tech => VIRTEX2 , MHz => 100 , dbits => 64 , rstdelay => 200 , clk_mul => 18 , clk_div => 20 , rskew => 0
) PORT MAP (
rst_ddr , clk_ddr , clkddro , clkread , lock , ddr_clk , ddr_clkb , ddr_clk_fb_out , ddr_clk_fb , ddr_cke , ddr_csb , ddr_web , ddr_rasb , ddr_casb , ddr_dm , ddr_dqs , ddr_ad , ddr_ba , ddr_dq , sdi , sdo
)
;
ddrc : COMPONENT ddrsp64a
GENERIC MAP (
memtech => 0 , hindex => 3 , haddr => 1024 , hmask => 3072 , ioaddr => 1 , iomask => 4095 , pwron => 1 , MHz => ( 18 * 100 ) / 20 , col => 9 , Mbyte => 256 , fast => 65 / ( 18 * 100 ) / 20 / 4
) PORT MAP (
rst_ahb , clkddri , clk_ahb , modahbsi , ahbso , sdi , sdo
)
;
END ARCHITECTURE;
| mit | 124d2c17485e6273f19cadfe2c0a48f5 | 0.534765 | 3.771855 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/devices/devices.vhd | 2 | 2,315 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Extended by : Thomas Ameseder, Gleichmann Electronics
-- Description: Vendor and devices id's for amba plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices_ge is
-- Vendor code
constant VENDOR_GLEICHMANN : amba_vendor_type := 16#10#;
-- Gleichmann's device id's
constant GLEICHMANN_CUSTOM : amba_device_type := 16#001#;
constant GLEICHMANN_GEOLCD01 : amba_device_type := 16#002#;
constant GLEICHMANN_DAC : amba_device_type := 16#003#;
constant GLEICHMANN_HPI : amba_device_type := 16#004#;
constant GLEICHMANN_SPI : amba_device_type := 16#005#;
constant GLEICHMANN_HIFC : amba_device_type := 16#006#;
-- pragma translate_off
constant GLEICHMANN_DESC : vendor_description := "Gleichmann Electronics ";
constant gleichmann_device_table : device_table_type := (
GLEICHMANN_CUSTOM => "Custom device ",
GLEICHMANN_GEOLCD01 => "GEOLCD01 graphics system ",
GLEICHMANN_DAC => "Sigma delta DAC ",
GLEICHMANN_HPI => "AHB-to-HPI bridge ",
GLEICHMANN_SPI => "SPI master ",
GLEICHMANN_HIFC => "Human interface controller ",
others => "Unknown Device ");
constant gleichmann_lib : vendor_library_type := (
vendorid => VENDOR_GLEICHMANN,
vendordesc => GLEICHMANN_DESC,
device_table => gleichmann_device_table
);
-- pragma translate_on
end;
| mit | 34d9d4f6d0c5eaac5fef5ee41d17015a | 0.588769 | 4.263352 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/leon3mp.vhd | 2 | 21,435 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
hackVector : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
signal stati : ahbstat_in_type;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, hackVector);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-- gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
-- grgpio0: grgpio
-- generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
-- nbits => CFG_GRGPIO_WIDTH)
-- port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
--
-- pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
-- pio_pad : iopad generic map (tech => padtech)
-- port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-- end generate;
-- end generate;
-- ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
-- ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
-- nftslv => CFG_AHBSTATN)
-- port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_version
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| mit | 585163b720cc0ad67b4a26e5b673da02 | 0.551295 | 3.538296 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/sim/phy.vhd | 2 | 23,511 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: phy
-- File: phy.vhd
-- Description: Simulation model of an Ethernet PHY
-- Author: Marko Isomaki
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
entity phy is
generic(
address : integer range 0 to 31 := 0;
extended_regs : integer range 0 to 1 := 1;
aneg : integer range 0 to 1 := 1;
base100_t4 : integer range 0 to 1 := 0;
base100_x_fd : integer range 0 to 1 := 1;
base100_x_hd : integer range 0 to 1 := 1;
fd_10 : integer range 0 to 1 := 1;
hd_10 : integer range 0 to 1 := 1;
base100_t2_fd : integer range 0 to 1 := 1;
base100_t2_hd : integer range 0 to 1 := 1;
base1000_x_fd : integer range 0 to 1 := 0;
base1000_x_hd : integer range 0 to 1 := 0;
base1000_t_fd : integer range 0 to 1 := 1;
base1000_t_hd : integer range 0 to 1 := 1
);
port(
rstn : in std_logic;
mdio : inout std_logic;
tx_clk : out std_logic;
rx_clk : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
mdc : in std_logic;
gtx_clk : in std_logic
);
end;
architecture behavioral of phy is
type mdio_state_type is (idle, start_of_frame, start_of_frame2, op, phyad, regad,
ta, rdata, wdata);
type ctrl_reg_type is record
reset : std_ulogic;
loopback : std_ulogic;
speedsel : std_logic_vector(1 downto 0);
anegen : std_ulogic;
powerdown : std_ulogic;
isolate : std_ulogic;
restartaneg : std_ulogic;
duplexmode : std_ulogic;
coltest : std_ulogic;
end record;
type status_reg_type is record
base100_t4 : std_ulogic;
base100_x_fd : std_ulogic;
base100_x_hd : std_ulogic;
fd_10 : std_ulogic;
hd_10 : std_ulogic;
base100_t2_fd : std_ulogic;
base100_t2_hd : std_ulogic;
extstat : std_ulogic;
mfpreamblesup : std_ulogic;
anegcmpt : std_ulogic;
remfault : std_ulogic;
anegability : std_ulogic;
linkstat : std_ulogic;
jabdetect : std_ulogic;
extcap : std_ulogic;
end record;
type aneg_ab_type is record
next_page : std_ulogic;
remote_fault : std_ulogic;
tech_ability : std_logic_vector(7 downto 0);
selector : std_logic_vector(4 downto 0);
end record;
type aneg_exp_type is record
par_detct_flt : std_ulogic;
lp_np_able : std_ulogic;
np_able : std_ulogic;
page_rx : std_ulogic;
lp_aneg_able : std_ulogic;
end record;
type aneg_nextpage_type is record
next_page : std_ulogic;
message_page : std_ulogic;
ack2 : std_ulogic;
toggle : std_ulogic;
message : std_logic_vector(10 downto 0);
end record;
type mst_slv_ctrl_type is record
tmode : std_logic_vector(2 downto 0);
manualcfgen : std_ulogic;
cfgval : std_ulogic;
porttype : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type mst_slv_status_type is record
cfgfault : std_ulogic;
cfgres : std_ulogic;
locrxstate : std_ulogic;
remrxstate : std_ulogic;
lpbase1000_t_fd : std_ulogic;
lpbase1000_t_hd : std_ulogic;
idlerrcnt : std_logic_vector(7 downto 0);
end record;
type extended_status_reg_type is record
base1000_x_fd : std_ulogic;
base1000_x_hd : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type reg_type is record
state : mdio_state_type;
cnt : integer;
op : std_logic_vector(1 downto 0);
phyad : std_logic_vector(4 downto 0);
regad : std_logic_vector(4 downto 0);
wr : std_ulogic;
regtmp : std_logic_vector(15 downto 0);
-- MII management registers
ctrl : ctrl_reg_type;
status : status_reg_type;
anegadv : aneg_ab_type;
aneglp : aneg_ab_type;
anegexp : aneg_exp_type;
anegnptx : aneg_nextpage_type;
anegnplp : aneg_nextpage_type;
mstslvctrl : mst_slv_ctrl_type;
mstslvstat : mst_slv_status_type;
extstatus : extended_status_reg_type;
rstcnt : integer;
anegcnt : integer;
end record;
signal r, rin : reg_type;
signal int_clk : std_ulogic := '0';
signal clkslow : std_ulogic := '0';
signal rcnt : integer;
signal anegact : std_ulogic;
begin
--mdio signal pull-up
int_clk <= not int_clk after 8 ns when r.ctrl.speedsel = "01" else
not int_clk after 40 ns when r.ctrl.speedsel = "10" else
not int_clk after 400 ns when r.ctrl.speedsel = "00";
clkslow <= not clkslow after 40 ns when r.ctrl.speedsel = "10" else
not clkslow after 400 ns;
-- rstdelay : process
-- begin
-- loop
-- rstd <= '0';
-- while r.ctrl.reset /= '1' loop
-- wait on r.ctrl.reset;
-- end loop;
-- rstd <= '1';
-- while rstn = '0' loop
-- wait on rstn;
-- end loop;
-- wait on rstn for 3 us;
-- rstd <= '0';
-- wait on rstn until r.ctrl.reset = '0' for 5 us;
-- end loop;
-- end process;
anegproc : process is
begin
loop
anegact <= '0';
while rstn /= '1' loop
wait on rstn;
end loop;
while rstn = '1' loop
if r.ctrl.anegen = '0' then
anegact <= '0';
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
else
if r.ctrl.restartaneg = '1' then
anegact <= '1';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen for 2 us;
anegact <= '0';
wait on rstn, r.ctrl.anegen until r.ctrl.restartaneg = '0';
if (rstn and r.ctrl.anegen) = '1' then
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
end if;
else
anegact <= '0';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen;
end if;
end if;
end loop;
end loop;
end process;
mdiocomb : process(rstn, r, anegact, mdio) is
variable v : reg_type;
begin
v := r;
if anegact = '0' then
v.ctrl.restartaneg := '0';
end if;
case r.state is
when idle =>
mdio <= 'Z';
if to_X01(mdio) = '1' then
v.cnt := v.cnt + 1;
if v.cnt = 31 then
v.state := start_of_frame; v.cnt := 0;
end if;
else
v.cnt := 0;
end if;
when start_of_frame =>
if to_X01(mdio) = '0' then
v.state := start_of_frame2;
elsif to_X01(mdio) /= '1' then
v.state := idle;
end if;
when start_of_frame2 =>
if to_X01(mdio) = '1' then
v.state := op;
else
v.state := idle;
end if;
when op =>
v.cnt := v.cnt + 1;
v.op := r.op(0) & to_X01(mdio);
if r.cnt = 1 then
if (v.op = "01") or (v.op = "10") then
v.state := phyad; v.cnt := 0;
else
v.state := idle; v.cnt := 0;
end if;
end if;
when phyad =>
v.phyad := r.phyad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.state := regad; v.cnt := 0;
end if;
when regad =>
v.regad := r.regad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.cnt := 0;
if conv_integer(r.phyad) = address then
v.state := ta;
else
v.state := idle;
end if;
end if;
when ta =>
v.cnt := r.cnt + 1;
if r.cnt = 0 then
if (r.op = "01") and to_X01(mdio) /= '1' then
v.cnt := 0; v.state := idle;
end if;
else
if r.op = "10" then
mdio <= '0'; v.cnt := 0; v.state := rdata;
case r.regad is
when "00000" => --ctrl (basic)
v.regtmp := r.ctrl.reset & r.ctrl.loopback &
r.ctrl.speedsel(1) & r.ctrl.anegen & r.ctrl.powerdown &
r.ctrl.isolate & r.ctrl.restartaneg & r.ctrl.duplexmode &
r.ctrl.coltest & r.ctrl.speedsel(0) & "000000";
when "00001" => --statuc (basic)
v.regtmp := r.status.base100_t4 & r.status.base100_x_fd &
r.status.base100_x_hd & r.status.fd_10 & r.status.hd_10 &
r.status.base100_t2_fd & r.status.base100_t2_hd &
r.status.extstat & '0' & r.status.mfpreamblesup &
r.status.anegcmpt & r.status.remfault & r.status.anegability &
r.status.linkstat & r.status.jabdetect & r.status.extcap;
when "00010" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"BBCD";
else
v.cnt := 0; v.state := idle;
end if;
when "00011" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"9C83";
else
v.cnt := 0; v.state := idle;
end if;
when "00100" => --Auto-neg adv. (extended)
if extended_regs = 1 then
v.regtmp := r.anegadv.next_page & '0' & r.anegadv.remote_fault &
r.anegadv.tech_ability & r.anegadv.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00101" => --Auto-neg link partner ability (extended)
if extended_regs = 1 then
v.regtmp := r.aneglp.next_page & '0' & r.aneglp.remote_fault &
r.aneglp.tech_ability & r.aneglp.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00110" => --Auto-neg expansion (extended)
if extended_regs = 1 then
v.regtmp := "00000000000" & r.anegexp.par_detct_flt &
r.anegexp.lp_np_able & r.anegexp.np_able & r.anegexp.page_rx &
r.anegexp.lp_aneg_able;
else
v.cnt := 0; v.state := idle;
end if;
when "00111" => --Auto-neg next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnptx.next_page & '0' & r.anegnptx.message_page &
r.anegnptx.ack2 & r.anegnptx.toggle & r.anegnptx.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01000" => --Auto-neg link partner received next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnplp.next_page & '0' & r.anegnplp.message_page &
r.anegnplp.ack2 & r.anegnplp.toggle & r.anegnplp.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01001" => --Master-slave control (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvctrl.tmode & r.mstslvctrl.manualcfgen &
r.mstslvctrl.cfgval & r.mstslvctrl.porttype &
r.mstslvctrl.base1000_t_fd & r.mstslvctrl.base1000_t_hd &
"00000000";
else
v.cnt := 0; v.state := idle;
end if;
when "01010" => --Master-slave status (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvstat.cfgfault & r.mstslvstat.cfgres &
r.mstslvstat.locrxstate & r.mstslvstat.remrxstate &
r.mstslvstat.lpbase1000_t_fd & r.mstslvstat.lpbase1000_t_hd &
"00" & r.mstslvstat.idlerrcnt;
else
v.cnt := 0; v.state := idle;
end if;
when "01111" =>
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(base1000_t_fd = 1) or (base1000_t_hd = 1) then
v.regtmp := r.extstatus.base1000_x_fd &
r.extstatus.base1000_x_hd &
r.extstatus.base1000_t_fd &
r.extstatus.base1000_t_hd & X"000";
else
v.regtmp := (others => '0');
end if;
when others =>
--PHY shall not drive MDIO when unimplemented registers
--are accessed
v.cnt := 0; v.state := idle;
v.regtmp := (others => '0');
end case;
if r.ctrl.reset = '1' then
if r.regad = "00000" then
v.regtmp := X"8000";
else
v.regtmp := X"0000";
end if;
end if;
else
if to_X01(mdio) /= '0'then
v.cnt := 0; v.state := idle;
else
v.cnt := 0; v.state := wdata;
end if;
end if;
end if;
when rdata =>
v.cnt := r.cnt + 1;
mdio <= r.regtmp(15-r.cnt);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
end if;
when wdata =>
v.cnt := r.cnt + 1;
v.regtmp := r.regtmp(14 downto 0) & to_X01(mdio);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
if r.ctrl.reset = '0' then
case r.regad is
when "00000" =>
v.ctrl.reset := v.regtmp(15);
v.ctrl.loopback := v.regtmp(14);
v.ctrl.speedsel(1) := v.regtmp(13);
v.ctrl.anegen := v.regtmp(12);
v.ctrl.powerdown := v.regtmp(11);
v.ctrl.isolate := v.regtmp(10);
v.ctrl.restartaneg := v.regtmp(9);
v.ctrl.duplexmode := v.regtmp(8);
v.ctrl.coltest := v.regtmp(7);
v.ctrl.speedsel(0) := v.regtmp(6);
when "00100" =>
if extended_regs = 1 then
v.anegadv.remote_fault := r.regtmp(13);
v.anegadv.tech_ability := r.regtmp(12 downto 5);
v.anegadv.selector := r.regtmp(4 downto 0);
end if;
when "00111" =>
if extended_regs = 1 then
v.anegnptx.next_page := r.regtmp(15);
v.anegnptx.message_page := r.regtmp(13);
v.anegnptx.ack2 := r.regtmp(12);
v.anegnptx.message := r.regtmp(10 downto 0);
end if;
when "01001" =>
if extended_regs = 1 then
v.mstslvctrl.tmode := r.regtmp(15 downto 13);
v.mstslvctrl.manualcfgen := r.regtmp(12);
v.mstslvctrl.cfgval := r.regtmp(11);
v.mstslvctrl.porttype := r.regtmp(10);
v.mstslvctrl.base1000_t_fd := r.regtmp(9);
v.mstslvctrl.base1000_t_hd := r.regtmp(8);
end if;
when others => --no writable bits for other regs
null;
end case;
end if;
end if;
when others =>
null;
end case;
if r.rstcnt > 19 then
v.ctrl.reset := '0'; v.rstcnt := 0;
else
v.rstcnt := r.rstcnt + 1;
end if;
if (v.ctrl.reset and not r.ctrl.reset) = '1' then
v.rstcnt := 0;
end if;
if r.ctrl.anegen = '1' then
if r.anegcnt < 10 then
v.anegcnt := r.anegcnt + 1;
else
v.status.anegcmpt := '1';
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(r.mstslvctrl.base1000_t_fd = '1') or
(r.mstslvctrl.base1000_t_hd = '1') then
v.ctrl.speedsel(1 downto 0) := "01";
elsif (r.anegadv.tech_ability(4) = '1') or
(r.anegadv.tech_ability(3) = '1') or
(r.anegadv.tech_ability(2) = '1') or
(base100_t2_fd = 1) or (base100_t2_hd = 1) then
v.ctrl.speedsel(1 downto 0) := "10";
else
v.ctrl.speedsel(1 downto 0) := "00";
end if;
if ((base1000_x_fd = 1) or (r.mstslvctrl.base1000_t_fd = '1')) or
(((base100_t2_fd = 1) or (r.anegadv.tech_ability(3) = '1')) and
(r.mstslvctrl.base1000_t_hd = '0') and (base1000_x_hd = 0)) or
((r.anegadv.tech_ability(1) = '1') and (base100_t2_hd = 0) and
(r.anegadv.tech_ability(4) = '0') and
(r.anegadv.tech_ability(2) = '0')) then
v.ctrl.duplexmode := '1';
else
v.ctrl.duplexmode := '0';
end if;
end if;
end if;
if r.ctrl.restartaneg = '1' then
v.anegcnt := 0;
v.status.anegcmpt := '0';
v.ctrl.restartaneg := '0';
end if;
rin <= v;
end process;
reg : process(rstn, mdc) is
begin
if rising_edge(mdc) then
r <= rin;
end if;
-- -- RESET DELAY
-- if rstd = '1' then
-- r.ctrl.reset <= '1';
-- else
-- r.ctrl.reset <= '0';
-- end if;
-- RESET
if (r.ctrl.reset or not rstn) = '1' then
r.ctrl.loopback <= '0'; r.anegcnt <= 0;
if (base1000_x_hd = 1) or (base1000_x_fd = 1) or (base1000_t_hd = 1) or
(base1000_t_fd = 1) then
r.ctrl.speedsel <= "01";
elsif (base100_x_hd = 1) or (base100_t2_hd = 1) or (base100_x_fd = 1) or
(base100_t2_fd = 1) or (base100_t4 = 1) then
r.ctrl.speedsel <= "10";
else
r.ctrl.speedsel <= "00";
end if;
r.ctrl.anegen <= conv_std_logic(aneg = 1);
r.ctrl.powerdown <= '0';
r.ctrl.isolate <= '0';
r.ctrl.restartaneg <= '0';
if (base100_x_hd = 0) and (hd_10 = 0) and (base100_t2_hd = 0) and
(base1000_x_hd = 0) and (base1000_t_hd = 0) then
r.ctrl.duplexmode <= '1';
else
r.ctrl.duplexmode <= '0';
end if;
r.ctrl.coltest <= '0';
r.status.base100_t4 <= conv_std_logic(base100_t4 = 1);
r.status.base100_x_fd <= conv_std_logic(base100_x_fd = 1);
r.status.base100_x_hd <= conv_std_logic(base100_x_hd = 1);
r.status.fd_10 <= conv_std_logic(fd_10 = 1);
r.status.hd_10 <= conv_std_logic(hd_10 = 1);
r.status.base100_t2_fd <= conv_std_logic(base100_t2_fd = 1);
r.status.base100_t2_hd <= conv_std_logic(base100_t2_hd = 1);
r.status.extstat <= conv_std_logic((base1000_x_fd = 1) or
(base1000_x_hd = 1) or
(base1000_t_fd = 1) or
(base1000_t_hd = 1));
r.status.mfpreamblesup <= '0';
r.status.anegcmpt <= '0';
r.status.remfault <= '0';
r.status.anegability <= conv_std_logic(aneg = 1);
r.status.linkstat <= '0';
r.status.jabdetect <= '0';
r.status.extcap <= conv_std_logic(extended_regs = 1);
r.anegadv.next_page <= '0';
r.anegadv.remote_fault <= '0';
r.anegadv.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.anegadv.selector <= "00001";
r.aneglp.next_page <= '0';
r.aneglp.remote_fault <= '0';
r.aneglp.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.aneglp.selector <= "00001";
r.anegexp.par_detct_flt <= '0';
r.anegexp.lp_np_able <= '0';
r.anegexp.np_able <= '0';
r.anegexp.page_rx <= '0';
r.anegexp.lp_aneg_able <= '0';
r.anegnptx.next_page <= '0';
r.anegnptx.message_page <= '1';
r.anegnptx.ack2 <= '0';
r.anegnptx.toggle <= '0';
r.anegnptx.message <= "00000000001";
r.anegnplp.next_page <= '0';
r.anegnplp.message_page <= '1';
r.anegnplp.ack2 <= '0';
r.anegnplp.toggle <= '0';
r.anegnplp.message <= "00000000001";
r.mstslvctrl.tmode <= (others => '0');
r.mstslvctrl.manualcfgen <= '0';
r.mstslvctrl.cfgval <= '0';
r.mstslvctrl.porttype <= '0';
r.mstslvctrl.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvctrl.base1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.cfgfault <= '0';
r.mstslvstat.cfgres <= '1';
r.mstslvstat.locrxstate <= '1';
r.mstslvstat.remrxstate <= '1';
r.mstslvstat.lpbase1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.lpbase1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.idlerrcnt <= (others => '0');
r.extstatus.base1000_x_fd <= conv_std_logic(base1000_x_fd = 1);
r.extstatus.base1000_x_hd <= conv_std_logic(base1000_x_hd = 1);
r.extstatus.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.extstatus.base1000_t_hd <= conv_std_logic(base1000_t_hd = 1);
end if;
if rstn = '0' then
r.cnt <= 0; r.state <= idle; r.rstcnt <= 0;
r.ctrl.reset <= '1';
end if;
end process;
loopback_sel : process(r.ctrl.loopback, int_clk, gtx_clk, r.ctrl.speedsel, txd, tx_en) is
begin
if r.ctrl.loopback = '1' then
rx_col <= '0'; rx_crs <= tx_en; rx_dv <= tx_en; rx_er <= tx_er;
rxd <= txd;
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
else
rx_col <= '0'; rx_crs <= '0'; rx_dv <= '0';
rxd <= (others => '0');
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk after 3 ns;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
end if;
end process;
end;
-- pragma translate_on
| mit | 5738a9337d72107f731822a0f2f498ee | 0.494152 | 3.37996 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/ddr_ireg.vhd | 2 | 2,043 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ireg
-- File: ddr_ireg.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DDR input reg with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr_ireg is
generic ( tech : integer);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ddr_ireg is
begin
inf : if not(tech = virtex4 or tech = virtex2 or tech = spartan3
or (tech = virtex5)) generate
inf0 : gen_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
xil : if tech = virtex4 or tech = virtex2 or tech = spartan3
or (tech = virtex5) generate
xil0 : unisim_iddr_reg generic map (tech) port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
end architecture;
| mit | d7308c9e4b174dd25b334b2bce2d6bc6 | 0.595203 | 3.928846 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/sparc/sparc.vhd | 2 | 9,956 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: opcodes
-- File: opcodes.vhd
-- Author: Jiri Gaisler
-- Description: Instruction definitions according to the SPARC V8 manual.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sparc is
-- op decoding (inst(31 downto 30))
subtype op_type is std_logic_vector(1 downto 0);
constant FMT2 : op_type := "00";
constant CALL : op_type := "01";
constant FMT3 : op_type := "10";
constant LDST : op_type := "11";
-- op2 decoding (inst(24 downto 22))
subtype op2_type is std_logic_vector(2 downto 0);
constant UNIMP : op2_type := "000";
constant BICC : op2_type := "010";
constant SETHI : op2_type := "100";
constant FBFCC : op2_type := "110";
constant CBCCC : op2_type := "111";
-- op3 decoding (inst(24 downto 19))
subtype op3_type is std_logic_vector(5 downto 0);
constant IADD : op3_type := "000000";
constant IAND : op3_type := "000001";
constant IOR : op3_type := "000010";
constant IXOR : op3_type := "000011";
constant ISUB : op3_type := "000100";
constant ANDN : op3_type := "000101";
constant ORN : op3_type := "000110";
constant IXNOR : op3_type := "000111";
constant ADDX : op3_type := "001000";
constant UMUL : op3_type := "001010";
constant SMUL : op3_type := "001011";
constant SUBX : op3_type := "001100";
constant UDIV : op3_type := "001110";
constant SDIV : op3_type := "001111";
constant ADDCC : op3_type := "010000";
constant ANDCC : op3_type := "010001";
constant ORCC : op3_type := "010010";
constant XORCC : op3_type := "010011";
constant SUBCC : op3_type := "010100";
constant ANDNCC : op3_type := "010101";
constant ORNCC : op3_type := "010110";
constant XNORCC : op3_type := "010111";
constant ADDXCC : op3_type := "011000";
constant UMULCC : op3_type := "011010";
constant SMULCC : op3_type := "011011";
constant SUBXCC : op3_type := "011100";
constant UDIVCC : op3_type := "011110";
constant SDIVCC : op3_type := "011111";
constant TADDCC : op3_type := "100000";
constant TSUBCC : op3_type := "100001";
constant TADDCCTV : op3_type := "100010";
constant TSUBCCTV : op3_type := "100011";
constant MULSCC : op3_type := "100100";
constant ISLL : op3_type := "100101";
constant ISRL : op3_type := "100110";
constant ISRA : op3_type := "100111";
constant RDY : op3_type := "101000";
constant RDPSR : op3_type := "101001";
constant RDWIM : op3_type := "101010";
constant RDTBR : op3_type := "101011";
constant WRY : op3_type := "110000";
constant WRPSR : op3_type := "110001";
constant WRWIM : op3_type := "110010";
constant WRTBR : op3_type := "110011";
constant FPOP1 : op3_type := "110100";
constant FPOP2 : op3_type := "110101";
constant CPOP1 : op3_type := "110110";
constant CPOP2 : op3_type := "110111";
constant JMPL : op3_type := "111000";
constant TICC : op3_type := "111010";
constant FLUSH : op3_type := "111011";
constant RETT : op3_type := "111001";
constant SAVE : op3_type := "111100";
constant RESTORE : op3_type := "111101";
constant UMAC : op3_type := "111110";
constant SMAC : op3_type := "111111";
constant LD : op3_type := "000000";
constant LDUB : op3_type := "000001";
constant LDUH : op3_type := "000010";
constant LDD : op3_type := "000011";
constant LDSB : op3_type := "001001";
constant LDSH : op3_type := "001010";
constant LDSTUB : op3_type := "001101";
constant SWAP : op3_type := "001111";
constant LDA : op3_type := "010000";
constant LDUBA : op3_type := "010001";
constant LDUHA : op3_type := "010010";
constant LDDA : op3_type := "010011";
constant LDSBA : op3_type := "011001";
constant LDSHA : op3_type := "011010";
constant LDSTUBA : op3_type := "011101";
constant SWAPA : op3_type := "011111";
constant LDF : op3_type := "100000";
constant LDFSR : op3_type := "100001";
constant LDDF : op3_type := "100011";
constant LDC : op3_type := "110000";
constant LDCSR : op3_type := "110001";
constant LDDC : op3_type := "110011";
constant ST : op3_type := "000100";
constant STB : op3_type := "000101";
constant STH : op3_type := "000110";
constant ISTD : op3_type := "000111";
constant STA : op3_type := "010100";
constant STBA : op3_type := "010101";
constant STHA : op3_type := "010110";
constant STDA : op3_type := "010111";
constant STF : op3_type := "100100";
constant STFSR : op3_type := "100101";
constant STDFQ : op3_type := "100110";
constant STDF : op3_type := "100111";
constant STC : op3_type := "110100";
constant STCSR : op3_type := "110101";
constant STDCQ : op3_type := "110110";
constant STDC : op3_type := "110111";
-- bicc decoding (inst(27 downto 25))
constant BA : std_logic_vector(3 downto 0) := "1000";
-- fpop1 decoding
subtype fpop_type is std_logic_vector(8 downto 0);
constant FITOS : fpop_type := "011000100";
constant FITOD : fpop_type := "011001000";
constant FSTOI : fpop_type := "011010001";
constant FDTOI : fpop_type := "011010010";
constant FSTOD : fpop_type := "011001001";
constant FDTOS : fpop_type := "011000110";
constant FMOVS : fpop_type := "000000001";
constant FNEGS : fpop_type := "000000101";
constant FABSS : fpop_type := "000001001";
constant FSQRTS : fpop_type := "000101001";
constant FSQRTD : fpop_type := "000101010";
constant FADDS : fpop_type := "001000001";
constant FADDD : fpop_type := "001000010";
constant FSUBS : fpop_type := "001000101";
constant FSUBD : fpop_type := "001000110";
constant FMULS : fpop_type := "001001001";
constant FMULD : fpop_type := "001001010";
constant FSMULD : fpop_type := "001101001";
constant FDIVS : fpop_type := "001001101";
constant FDIVD : fpop_type := "001001110";
-- fpop2 decoding
constant FCMPS : fpop_type := "001010001";
constant FCMPD : fpop_type := "001010010";
constant FCMPES : fpop_type := "001010101";
constant FCMPED : fpop_type := "001010110";
-- trap type decoding
subtype trap_type is std_logic_vector(5 downto 0);
constant TT_IAEX : trap_type := "000001";
constant TT_IINST : trap_type := "000010";
constant TT_PRIV : trap_type := "000011";
constant TT_FPDIS : trap_type := "000100";
constant TT_WINOF : trap_type := "000101";
constant TT_WINUF : trap_type := "000110";
constant TT_UNALA : trap_type := "000111";
constant TT_FPEXC : trap_type := "001000";
constant TT_DAEX : trap_type := "001001";
constant TT_TAG : trap_type := "001010";
constant TT_WATCH : trap_type := "001011";
constant TT_DSU : trap_type := "010000";
constant TT_PWD : trap_type := "010001";
constant TT_RFERR : trap_type := "100000";
constant TT_IAERR : trap_type := "100001";
constant TT_CPDIS : trap_type := "100100";
constant TT_CPEXC : trap_type := "101000";
constant TT_DIV : trap_type := "101010";
constant TT_DSEX : trap_type := "101011";
constant TT_TICC : trap_type := "111111";
-- Alternate address space identifiers (only 5 lsb bist are used)
subtype asi_type is std_logic_vector(4 downto 0);
constant ASI_SYSR : asi_type := "00010"; -- 0x02
constant ASI_UINST : asi_type := "01000"; -- 0x08
constant ASI_SINST : asi_type := "01001"; -- 0x09
constant ASI_UDATA : asi_type := "01010"; -- 0x0A
constant ASI_SDATA : asi_type := "01011"; -- 0x0B
constant ASI_ITAG : asi_type := "01100"; -- 0x0C
constant ASI_IDATA : asi_type := "01101"; -- 0x0D
constant ASI_DTAG : asi_type := "01110"; -- 0x0E
constant ASI_DDATA : asi_type := "01111"; -- 0x0F
constant ASI_IFLUSH : asi_type := "10000"; -- 0x10
constant ASI_DFLUSH : asi_type := "10001"; -- 0x11
constant ASI_FLUSH_PAGE : std_logic_vector(4 downto 0) := "10000"; -- 0x10 i/dcache flush page
constant ASI_FLUSH_CTX : std_logic_vector(4 downto 0) := "10011"; -- 0x13 i/dcache flush ctx
constant ASI_DCTX : std_logic_vector(4 downto 0) := "10100"; -- 0x14 dcache ctx
constant ASI_ICTX : std_logic_vector(4 downto 0) := "10101"; -- 0x15 icache ctx
constant ASI_MMUFLUSHPROBE : std_logic_vector(4 downto 0) := "11000"; -- 0x18 i/dtlb flush/(probe)
constant ASI_MMUREGS : std_logic_vector(4 downto 0) := "11001"; -- 0x19 mmu regs access
constant ASI_MMU_BP : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
constant ASI_MMU_DIAG : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
--constant ASI_MMU_DSU : std_logic_vector(4 downto 0) := "11111"; -- 0x1f mmu diagnostic
constant ASI_MMUSNOOP_DTAG : std_logic_vector(4 downto 0) := "11110"; -- 0x1e mmusnoop physical dtag
-- ftt decoding
subtype ftt_type is std_logic_vector(2 downto 0);
constant FPIEEE_ERR : ftt_type := "001";
constant FPSEQ_ERR : ftt_type := "100";
constant FPHW_ERR : ftt_type := "101";
end;
| mit | 2a3821f9a327d12ae788620f7ae9562f | 0.623544 | 3.295597 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/ahb2hpi/hpi_ram.vhd | 2 | 5,690 | -------------------------------------------------------------------------------
-- Title : HPI MEMORY
-- Project : LEON3MINI
-------------------------------------------------------------------------------
-- $Id: $
-------------------------------------------------------------------------------
-- Author : Thomas Ameseder
-- Company : Gleichmann Electronics
-- Created : 2005-08-19
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- This module is for testing the AHB2HPI(2) core. It is a memory that
-- can be connected to the HPI interface. Also features HPI timing
-- checks.
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity hpi_ram is
generic (abits : integer := 9; dbits : integer := 16);
port (
clk : in std_ulogic;
address : in std_logic_vector(1 downto 0);
datain : in std_logic_vector(dbits-1 downto 0);
dataout : out std_logic_vector(dbits-1 downto 0);
writen : in std_ulogic;
readn : in std_ulogic;
csn : in std_ulogic
);
end;
architecture behavioral of hpi_ram is
constant Tcyc : time := 40000 ps; -- cycle time
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal
data_reg, -- "00"
mailbox_reg, -- "01"
address_reg, -- "10"
status_reg -- "11"
: std_logic_vector(dbits-1 downto 0);
begin
write : process(clk)
begin
if rising_edge(clk) then
if csn = '0' then
if writen = '0' then
case address(1 downto 0) is
when "00" => memarr(conv_integer(address_reg(abits-1 downto 1))) <= datain;
when "01" => mailbox_reg <= datain;
when "10" => address_reg <= datain;
when "11" => status_reg <= datain;
when others => null;
end case;
end if;
end if;
end if;
end process;
read : process(address, address_reg, csn, mailbox_reg, memarr, readn,
status_reg)
constant Tacc : time := Tcyc; -- data access time
begin
if (readn = '0' and csn = '0') then
case address(1 downto 0) is
when "00" => dataout <= memarr(conv_integer(address_reg(abits-1 downto 1))) after Tacc;
when "01" => dataout <= mailbox_reg after Tacc;
when "10" => dataout <= address_reg after Tacc;
when "11" => dataout <= status_reg after Tacc;
when others => null;
end case;
else
-- the rest of the time, invalid data shall be driven
-- (note: makes an 'X' when being resolved on a high-impedance bus)
dataout <= (others => 'Z');
end if;
end process;
-- pragma translate_off
---------------------------------------------------------------------------------------
-- HPI TIMING CHECKS
---------------------------------------------------------------------------------------
cycle_timing_check : process(datain, readn, writen)
constant Tcycmin : time := 6 * Tcyc; -- minimum write/read cycle time
constant Tpulsemin : time := 2 * Tcyc; -- minimum write/read pulse time
constant Twdatasu : time := 6 ns; -- write data setup time
constant Twdatahold : time := 2 ns; -- write data hold time
variable wrlastev, rdlastev : time := 0 ps;
variable wrlowlastev, rdlowlastev : time := 0 ps;
variable wdatalastev : time := 0 ps; -- write data last event
variable wrhighlastev : time := 0 ps;
begin
-- write data hold check
if datain'event then
assert (now = 0 ps) or (now - wrhighlastev >= Twdatahold)
report "Write data hold violation!" severity error;
wdatalastev := now;
end if;
-- exclusive read or write check
assert writen = '1' or readn = '1'
report "Both read and write are signals are low!" severity error;
-- write cycle time and write pulse width checks
if writen'event then
if writen = '0' then
assert (now = 0 ps) or (now - wrlowlastev >= Tcycmin)
report "Write cycle time violation!" severity error;
wrlowlastev := now;
wrlastev := now;
elsif writen = '1' then
assert (now = 0 ps) or (now - wrlastev >= Tpulsemin)
report "Write pulse width violation!" severity error;
assert (now = 0 ps) or (now - wdatalastev >= Twdatasu)
report "Write data setup violation!" severity error;
wrhighlastev := now;
wrlastev := now;
end if;
end if;
-- read cycle time and read pulse width checks
if readn'event then
if readn = '0' then
assert (now = 0 ps) or (now - rdlowlastev >= Tcycmin)
report "Read cycle time violation!" severity error;
rdlowlastev := now;
rdlastev := now;
elsif readn = '1' then
assert (now = 0 ps) or (now - rdlastev >= Tpulsemin)
report "Read pulse width violation!" severity error;
rdlastev := now;
end if;
end if;
end process cycle_timing_check;
-- pragma translate_on
end architecture;
| mit | 5c892c1b092e687f65a4229f714e81d9 | 0.486292 | 4.317147 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/PreProcessor_Datapath.vhd | 9 | 33,331 | -------------------------------------------------------------------------------
--! @file PreProcessor_Datapath.vhd
--! @brief Datapath for the pre-processor
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor_Datapath is
generic (
G_W : integer := 64; --! Public data width (bits)
G_SW : integer := 64; --! Secret data width (bits)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64; --! Maximum size for the counter that keeps track of data
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_KEYAK : integer := 0; --! Special input mode, used only for Keyak with G_W = 128 and G_DBLK_SIZE = 1344
G_NPUB_DISABLE : integer := 0; --! Disable Npub related port(s)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable nsec port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 0; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding mode 0 = *10..., 1 = ICEPOLE's padding
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128 --! Tag size (bits)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
pdi : in std_logic_vector(G_W -1 downto 0); --! Public data
sdi : in std_logic_vector(G_SW -1 downto 0); --! Secret data
--! =================
--! Crypto Core Signals
--! =================
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Expected tag data
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! =================
--! Internal Signals
--! =================
--! Control signals
key_updated : in std_logic; --! (if G_DBLK_SIZE mod G_W > 0) Key updated signal (used only for situation when key is stored within input processor)
pad_shift : in std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
en_data : in std_logic; --! Shift data SIPO
en_npub : in std_logic; --! Shift Npub SIPO
en_nsec : in std_logic; --! Shift Nsec SIPO
en_key : in std_logic; --! Shift key SIPO
en_rdkey : in std_logic; --! Shift round key SIPO
en_exp_tag : in std_logic; --! Shift expected tag SIPO
sel_blank_pdi : in std_logic; --! Select input data as blank (for filling in the remaining data within a block)
clr_len : in std_logic; --! Clear stored length (len_a and len_d)
en_len_a_r : in std_logic; --! Add authenticated data counter
en_len_d_r : in std_logic; --! Add data counter
en_len_last_r : in std_logic; --! Special signal for en_len_*_r
en_len_a : in std_logic; --! Add authenticated data counter (instant)
en_len_d : in std_logic; --! Add data counter (no)
size_dword : in std_logic_vector(log2_ceil(G_W/8) downto 0); --! Size of data word
en_last_word : in std_logic; --! Last word in a block
pad_eot : in std_logic; --! Padding is EOT
pad_eoi : in std_logic; --! Padding is EOI
pad_type_ad : in std_logic; --! Padding is AD
pad_enable : in std_logic; --! Enable padding signal (indicates that the current word requires padding)
en_pad_loc : in std_logic; --! Save the padding location into a register
sel_input : in std_logic_vector(3 -1 downto 0) --! (if G_DBLK_SIZE mod G_W > 0) Select input for m
);
end PreProcessor_Datapath;
architecture dataflow of PreProcessor_Datapath is
--! Constants declaration
constant LOG2_W : integer := log2_ceil(G_W/8); --! LOG_2(G_W)
constant LOG2_SW : integer := log2_ceil(G_SW/8); --! LOG_2(G_SW)
constant REG_NPUB_WIDTH : integer := (((G_NPUB_SIZE-1)/G_W)+1)*G_W; --! Calculate the width of Npub register
constant CNTR_WIDTH : integer := get_cntr_width(G_W); --! Calculate the length of p_size register
constant LEN_A_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_AD_SIZE);
constant LEN_D_WIDTH : integer := maximum(CNTR_WIDTH, G_CTR_D_SIZE);
constant CNT_DATA_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for data (rounded up)
constant CNT_TAG_WORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W; --! Calculate the number of words required for tag (rounded up)
constant BSHIFT_INPUT : std_logic_vector(G_W/8 -1 downto 0) := std_logic_vector(to_unsigned(1,G_W/8));
constant OWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '1'); --! The number of bytes in a word in ones.
constant ZWORD_BYTES : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0) := (others => '0'); --! The number of bytes in a word in zeros.
function reverse_bit(aa: std_logic_vector) return std_logic_vector is
variable bb : std_logic_vector(aa'high downto aa'low);
begin
for i in aa'high downto aa'low loop
bb(i) := aa(aa'high-i);
end loop;
return bb;
end function reverse_bit;
type lookup_type is array (0 to ((G_W/8)*2-1)) of std_logic_vector(G_W/8-1 downto 0);
function getVbytesLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '1');
elsif (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
constant VBYTES_LOOKUP : lookup_type := getVbytesLookup(G_W);
--! ==================
--! Note: Current unused (keep this portion for later consideration)
function getPlocLookup(size: integer) return lookup_type is
variable ret : lookup_type;
begin
for i in 0 to ((size/8)*2-1) loop
if (i >= (size/8)) then
ret(i) := (others => '0');
else
ret(i) := (i => '1', others => '0');
end if;
end loop;
return ret;
end function getPlocLookup;
constant PLOC_LOOKUP : lookup_type := getPlocLookup(G_W);
--! End of note
--! ==================
--! Key related signals and registers
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_rdkey : std_logic_vector(G_RDKEY_SIZE -1 downto 0);
--! Public data signals and registers
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Data block register
signal reg_exp_tag : std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag register
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes register
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Pad location register
signal p_size : std_logic_vector(CNTR_WIDTH -1 downto 0); --! Public data segment size
signal p_zpad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal p_1pad_di : std_logic_vector(G_W -1 downto 0); --! Internally selected signal for padding
signal input_data : std_logic_vector(G_W -1 downto 0); --! Additional select signal for padding
signal input_vbytes : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
signal input_ploc : std_logic_vector(G_W/8 -1 downto 0); --! Additional select signal for bytes size
--! Data block status register for external modules
signal len_a_reg : std_logic_vector(LEN_A_WIDTH -1 downto 0); --! Total authenticated data register
signal len_d_reg : std_logic_vector(LEN_D_WIDTH -1 downto 0); --! Total message data register --! Current block contains no message data (used for authenticated encryption data only mode)
--! Padding related signals
signal pad_loc_r : std_logic_vector(G_W/8 -1 downto 0);
--! Lookups
signal vbytes : std_logic_vector(G_W/8 -1 downto 0);
signal ploc : std_logic_vector(G_W/8 -1 downto 0);
begin
p_zpad_di <= pdi when sel_blank_pdi = '0' else (others => '0');
vbytes <= VBYTES_LOOKUP(conv_integer(size_dword));
ploc <= PLOC_LOOKUP(conv_integer(size_dword));
--! Datapath
procReg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
reg_data <= (others => '0');
reg_exp_tag <= (others => '0');
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
reg_vbytes <= (others => '0');
else
--! === Public data
--! Data SIPO
if (en_data = '1') then
--! Handle different block size
if (G_W >= G_DBLK_SIZE) then
reg_data <= p_1pad_di(G_W-1 downto G_W-G_DBLK_SIZE);
reg_vbytes <= vbytes(G_W/8-1 downto G_W/8-G_DBLK_SIZE/8);
elsif ((G_DBLK_SIZE MOD G_W) = 0) then
reg_data <= reg_data(G_DBLK_SIZE-G_W-1 downto 0) & p_1pad_di;
reg_vbytes <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto 0) & vbytes;
elsif ((G_DBLK_SIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (G_DBLK_SIZE-1 downto ( G_DBLK_SIZE MOD G_W)) <= reg_data (G_DBLK_SIZE- G_W -1 downto ( G_DBLK_SIZE MOD G_W)) & input_data;
reg_vbytes(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_vbytes(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_vbytes;
else
reg_data ((G_DBLK_SIZE mod G_W )-1 downto 0) <= input_data (G_W -1 downto G_W /2);
reg_vbytes(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_vbytes(G_W/8-1 downto (G_W/8)/2);
end if;
end if;
end if;
--! Tag SIPO
if (en_exp_tag = '1') then
--! Handle different block size
if (G_W >= G_TAG_SIZE) then
reg_exp_tag <= pdi(G_W-1 downto G_W-G_TAG_SIZE);
else
reg_exp_tag <= reg_exp_tag(G_TAG_SIZE-G_W-1 downto 0) & pdi;
end if;
end if;
--! === Secret data
--! Key SIPO
if (en_key = '1') then
--! Handle different I/O and key size
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_KEY_SIZE then
reg_key <= sdi;
end if;
end if;
--! Round Key SIPO
if (en_rdkey = '1') then
--! Handle different I/O and key size
if (G_SW < G_RDKEY_SIZE) then
reg_rdkey <= reg_rdkey(G_RDKEY_SIZE-G_SW-1 downto 0) & sdi;
elsif G_SW = G_RDKEY_SIZE then
reg_rdkey <= sdi;
end if;
end if;
--! === Status
--! Length registers
if (clr_len = '1') then
len_a_reg <= (others => '0');
len_d_reg <= (others => '0');
else
if (G_LOADLEN_ENABLE = 0) then
if (en_len_a = '1') then
len_a_reg <= len_a_reg + p_size;
end if;
if (en_len_d = '1') then
len_d_reg <= len_d_reg + p_size;
end if;
else
if (en_len_a_r = '1') then
if (G_W >= LEN_A_WIDTH) then
len_a_reg <= pdi(LEN_A_WIDTH-1 downto 0);
elsif ((LEN_A_WIDTH MOD G_W) = 0) then
len_a_reg <= len_a_reg(LEN_A_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_A_WIDTH/G_W > 1) then
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= len_a_reg(LEN_A_WIDTH-G_W-1 downto (LEN_A_WIDTH MOD G_W)) & pdi;
else
len_a_reg(LEN_A_WIDTH-1 downto (LEN_A_WIDTH MOD G_W)) <= pdi;
end if;
else
len_a_reg((LEN_A_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_A_WIDTH MOD G_W));
end if;
end if;
end if;
if (en_len_d_r = '1') then
if (G_W >= LEN_D_WIDTH) then
len_d_reg <= pdi(LEN_D_WIDTH-1 downto 0);
elsif ((LEN_D_WIDTH MOD G_W) = 0) then
len_d_reg <= len_d_reg(LEN_D_WIDTH-G_W-1 downto 0) & pdi;
else
if (en_len_last_r = '0') then
if (LEN_D_WIDTH/G_W > 1) then
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= len_d_reg(LEN_D_WIDTH-G_W-1 downto (LEN_D_WIDTH MOD G_W)) & pdi;
else
len_d_reg(LEN_D_WIDTH-1 downto (LEN_D_WIDTH MOD G_W)) <= pdi;
end if;
else
len_d_reg((LEN_D_WIDTH MOD G_W)-1 downto 0) <= pdi(G_W-1 downto G_W-(LEN_D_WIDTH MOD G_W));
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--! Public data size (based on the interface)
p_size <= pdi(CNTR_WIDTH -1 downto 0);
--! Output
len_a <= len_a_reg(G_CTR_AD_SIZE -1 downto 0);
len_d <= len_d_reg(G_CTR_D_SIZE -1 downto 0);
bdi <= reg_data;
exp_tag <= reg_exp_tag;
genKey: if (G_RDKEY_ENABLE = 0) generate
key <= reg_key;
end generate;
genRdKey: if (G_RDKEY_ENABLE = 1) generate
rdkey <= reg_rdkey;
end generate;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
genNpub: if (G_NPUB_DISABLE = 0) generate
signal reg_npub : std_logic_vector(REG_NPUB_WIDTH -1 downto 0); --! Npub register
begin
npub <= reg_npub(REG_NPUB_WIDTH-1 downto REG_NPUB_WIDTH-G_NPUB_SIZE);
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (rst = '1') then
reg_npub <= (others => '0');
elsif (en_npub = '1') then
if (G_W >= G_NPUB_SIZE) then
reg_npub <= pdi(G_W-1 downto G_W-REG_NPUB_WIDTH);
else
reg_npub <= reg_npub(REG_NPUB_WIDTH-G_W-1 downto 0) & pdi;
end if;
end if;
end if;
end process;
end generate;
genNsec: if (G_NSEC_ENABLE = 1) generate
signal reg_nsec : std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec register
begin
nsec <= reg_nsec;
procReg:
process( clk )
begin
if rising_edge( clk ) then
if (en_nsec = '1') then
if (G_W < G_NSEC_SIZE) then
reg_nsec <= reg_nsec(G_NSEC_SIZE-G_W-1 downto 0) & pdi;
else
reg_nsec <= pdi(G_W-1 downto G_W-G_NSEC_SIZE);
end if;
end if;
end if;
end process;
end generate;
--! ============ Special mode ===========
genPartial: if ((G_DBLK_SIZE mod G_W) > 0) generate
constant ZEROS : std_logic_vector(G_W-1 downto 0) := (others => '0');
signal padded_reg : std_logic_vector(G_W/2-1 downto 0);
signal dbytes_reg : std_logic_vector((G_W/8)/2-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if (en_data = '1' and sel_blank_pdi = '0') then
padded_reg <= p_1pad_di(G_W/2-1 downto 0);
dbytes_reg <= vbytes((G_W/8)/2-1 downto 0);
end if;
end if;
end process;
genKeyak0: if G_KEYAK = 0 generate
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
--! Special loading for Keyak
genKeyak1: if (G_KEYAK = 1 and G_W = 128 and G_DBLK_SIZE = 1344) generate
signal key_r : std_logic_vector(G_KEY_SIZE-1 downto 0);
begin
pKey: process(clk)
begin
if rising_edge(clk) then
if (key_updated = '1') then
key_r <= reg_key;
end if;
end if;
end process;
with sel_input(2 downto 0) select
input_data <= p_1pad_di when "000",
p_1pad_di(G_W-1 downto G_W-G_W/2) & ZEROS(G_W-1 downto G_W-G_W/2) when "001",
padded_reg & p_1pad_di(G_W-1 downto G_W-G_W/2) when "010",
padded_reg & ZEROS(G_W-1 downto G_W-G_W/2) when "011",
x"1E" & key_r(G_KEY_SIZE-1 downto 8) when "100",
key_r(7 downto 0) & x"01" & x"000000000000000000000000" & x"0100" when "101",
(others => '0') when others;
with sel_input(2 downto 0) select
input_vbytes <= vbytes when "000",
vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
dbytes_reg & vbytes(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
dbytes_reg & ZEROS(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '1') when "100",
(others => '1') when "101",
(others => '0') when others;
end generate;
end generate;
--! ============ Padding related logic =================
--! No padding unit
genPad0: if G_PAD = 0 generate
begin
p_1pad_di <= p_zpad_di;
end generate;
--! With padding unit
genPad1: if G_PAD = 1 generate
signal pad_loc_s : std_logic_vector(G_W/8 -1 downto 0);
signal ploc_reg : std_logic_vector((G_W/8)/2 -1 downto 0);
begin
--! No actual padding is performed. However, padding location is produced. Used this mode if bdi_pad_loc signal is required)
genPadMode0:
if G_PAD_STYLE = 0 generate
p_1pad_di <= p_zpad_di;
end generate;
--! Pad 10*
genPadMode1:
if G_PAD_STYLE = 1 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2 downto G_W-i*8-8) <= p_zpad_di(G_W-i*8-2 downto G_W-i*8-8);
end generate;
end generate;
--! Padding mode for ICEPOLE
genPadMode2:
if G_PAD_STYLE = 2 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1 downto G_W-i*8-6) <= p_zpad_di(G_W-i*8-1 downto G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' ) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_eot = '1' and pad_type_ad = '1') or (pad_eot = '0' and pad_type_ad = '0'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
--! Padding mode for Keyak
genPadMode3:
if G_PAD_STYLE = 3 generate
genLoop:
for i in 0 to G_W/8-1 generate
p_1pad_di(G_W-i*8-1) <= p_zpad_di(G_W-i*8-1);
p_1pad_di(G_W-i*8-2) <= p_zpad_di(G_W-i*8-2);
p_1pad_di(G_W-i*8-3) <= p_zpad_di(G_W-i*8-3);
p_1pad_di(G_W-i*8-4) <= p_zpad_di(G_W-i*8-4);
p_1pad_di(G_W-i*8-5) <= p_zpad_di(G_W-i*8-5);
p_1pad_di(G_W-i*8-6) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1') else p_zpad_di(G_W-i*8-6);
p_1pad_di(G_W-i*8-7) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and ((pad_type_ad = '1' and pad_eoi = '0' and pad_eot = '1') or (pad_type_ad = '0' and pad_eot = '0'))) else p_zpad_di(G_W-i*8-7);
p_1pad_di(G_W-i*8-8) <= '1' when (pad_enable = '1' and pad_loc_r(i) = '1' and (pad_type_ad = '0' or (pad_eoi = '1' and pad_type_ad = '1'))) else p_zpad_di(G_W-i*8-8);
end generate;
end generate;
procReg: process(clk)
begin
if rising_edge(clk) then
if en_pad_loc = '1' then
pad_loc_r <= pad_loc_s;
end if;
if G_W >= G_DBLK_SIZE then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reverse_bit(pad_loc_r);
else
reg_ploc <= (others => '0');
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) = 0 then
if (en_data = '1') then
if (pad_enable = '1') then
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & reverse_bit(pad_loc_s);
else
reg_ploc <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto 0) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
end if;
elsif (G_DBLK_SIZE MOD G_W) /= 0 then
if (rst = '1') then
reg_ploc <= (others => '0');
elsif (en_data = '1') then
ploc_reg <= pad_loc_s(((G_W/8)-1) downto ((G_W/8)/2));
if (en_last_word = '0') then
if (pad_enable = '1') then
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & input_ploc;
else
reg_ploc(G_DBLK_SIZE/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) <= reg_ploc(G_DBLK_SIZE/8-G_W/8-1 downto ((G_DBLK_SIZE/8) MOD (G_W/8))) & ZWORD_BYTES(G_W/8-1 downto 0);
end if;
else
if (pad_enable = '1') then
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= input_ploc(G_W/8-1 downto (G_W/8)/2);
else
reg_ploc(((G_DBLK_SIZE/8) mod (G_W/8))-1 downto 0) <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
gKeyak0:
if ((G_KEYAK = 0) and ((G_DBLK_SIZE MOD G_W) /= 0)) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
end generate;
gKeyak1:
if (G_KEYAK = 1) generate
with sel_input(2 downto 0) select
input_ploc <= reverse_bit(pad_loc_s) when "000",
reverse_bit(pad_loc_s)(G_W/8-1 downto (G_W/8)/2) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "001",
reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "010",
reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "011",
(others => '0') when others;
-- with sel_input(2 downto 0) select
-- input_ploc <= reverse_bit(pad_loc_s) when "000",
-- reverse_bit(ploc_reg) & reverse_bit(pad_loc_s((G_W/8)/2-1 downto 0)) when "001",
-- reverse_bit(ploc_reg) & ZWORD_BYTES(G_W/8-1 downto G_W/8-(G_W/8)/2) when "010",
-- (others => '0') when others;
end generate;
--! Calculate the padding locatin
uBarrelShifter:
entity work.bshift(struct)
generic map (G_W => G_W/8, G_LOG2_W => LOG2_W, G_LEFT => 1, G_ROTATE => 0)
port map (ii => BSHIFT_INPUT, rtr => pad_shift, oo => pad_loc_s);
end generate;
end dataflow;
| gpl-3.0 | fbfb44cd3dc7af3be86e47ba4325997c | 0.409343 | 3.858416 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/memctrl/sdctrl.vhd | 2 | 20,662 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl
-- File: sdctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 32-bit SDRAM memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant BUS64 : boolean := (sdbits = 64);
constant REVISION : integer := 1;
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle);
type icycletype is (iidle, pre, ref, lmode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(1 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(sdbits-1 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 2); -- memory address
bsel : std_ulogic;
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable haddr_tmp : std_logic_vector(31 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive;
v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
v.hrdata(31 downto 0) := sdi.data(31 downto 0);
v.hwdata := ahbsi.hwdata;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "00") and
(r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "00") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
end if;
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if r.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "10")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; end if;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0';
elsif lineburst then
if r.haddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "10")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
elsif lineburst then
if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "01" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "10" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "11" =>
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(15 downto 2) := "000010001" & r.cfg.casdel & "0011";
else
v.address(15 downto 2) := "000010001" & r.cfg.casdel & "0111";
end if;
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "00";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when leadout =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.command := "01"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "00" then
v.cfg.command := "10"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "00" then
v.cfg.command := "10"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "11"; end if;
end if;
when lmode =>
if r.cfg.command = "00" then
v.istate := finish;
end if;
when others =>
if r.cfg.renable = '0' then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "10";
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if pageburst = 2 then v.cfg.pageburst := ahbsi.hwdata(17); end if;
v.cfg.command := ahbsi.hwdata(20 downto 19);
v.cfg.csize := ahbsi.hwdata(22 downto 21);
v.cfg.bsize := ahbsi.hwdata(25 downto 23);
v.cfg.casdel := ahbsi.hwdata(26);
v.cfg.trfc := ahbsi.hwdata(29 downto 27);
v.cfg.trp := ahbsi.hwdata(30);
v.cfg.renable := ahbsi.hwdata(31);
v.cfg.refresh := ahbsi.hwdata(14 downto 0);
v.refresh := (others => '0');
end if;
regsd := (others => '0');
regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
if BUS64 then regsd(15) := '1'; end if;
regsd(14 downto 0) := r.cfg.refresh;
if (r.hsel and r.hio) = '1' then dout := regsd;
else
if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
else dout := r.hrdata(31 downto 0); end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "00";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.bsel := '0';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not r.hio;
end process;
sdo.sdcke <= (others => '1');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdo.data(31 downto 0) <= r.hwdata;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address;
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdo.data(31 downto 0) <= r.hwdata;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl" & tost(hindex) &
": PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
| mit | 297f2818f340ddba3672ed5d20c31cb3 | 0.552125 | 3.172912 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/uart/dcom_uart.vhd | 2 | 9,652 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom_uart
-- File: dcom_uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART with baud-rate detection.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity dcom_uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end;
architecture rtl of dcom_uart is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBUART, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, stopbit);
type txfsmtype is (idle, data, stopbit);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
frame : std_ulogic; -- framing error
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : std_logic_vector(7 downto 0);
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_ulogic; -- rx data filtering buffer
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(17 downto 0);
brate : std_logic_vector(17 downto 0);
tcnt : std_logic_vector(1 downto 0); -- autobaud counter
rxdb2 : std_ulogic; -- delayed rx data
rxf : std_logic_vector(7 downto 0); -- rx data filtering buffer
fedge : std_ulogic; -- rx falling edge
end record;
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti, ui )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(17 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable irxd : std_ulogic;
variable v : uartregs;
begin
v := r;
v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0');
-- scaler
if r.tcnt = "11" then scaler := r.scaler - 1;
else scaler := r.scaler + 1; end if;
v.rxdb2 := r.rxdb;
if r.tcnt /= "11" then
if (r.rxdb2 and not r.rxdb) = '1' then v.fedge := '1'; end if;
if (r.fedge) = '1' then
v.scaler := scaler;
if (v.scaler(17) and not r.scaler(16)) = '1' then
v.scaler := "111111111111111011";
v.fedge := '0'; v.tcnt := "00";
end if;
end if;
if (r.rxdb2 and r.fedge and not r.rxdb) = '1' then
if (r.brate(17 downto 4)> r.scaler(17 downto 4)) then
v.brate := r.scaler; v.tcnt := "00";
end if;
v.scaler := "111111111111111011";
if (r.brate(17 downto 4) = r.scaler(17 downto 4)) then
v.tcnt := r.tcnt + 1;
if r.tcnt = "10" then
v.brate := "0000" & r.scaler(17 downto 4);
v.scaler := v.brate; v.rxen := '1';
end if;
end if;
end if;
else
if (r.break and r.rxdb2) = '1' then
v.scaler := "111111111111111011";
v.brate := (others => '1'); v.tcnt := "00";
v.break := '0'; v.rxen := '0';
end if;
end if;
if r.rxen = '1' then
v.scaler := scaler;
v.tick := scaler(15) and not r.scaler(15);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- read/write registers
if uarti.read = '1' then v.dready := '0'; end if;
case apbi.paddr(3 downto 2) is
when "01" =>
rdata(6 downto 0) := r.frame & '0' & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
when "10" =>
rdata(1 downto 0) := (r.tcnt(1) or r.tcnt(0)) & r.rxen;
when others =>
rdata(17 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.tcnt := apbi.pwdata(1) & apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(17 downto 0);
v.scaler := apbi.pwdata(17 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf := r.rxf(6 downto 0) & ui.rxd;
if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
r.rxf(7)) = r.rxf(6 downto 0))
then v.rxdb := r.rxf(7); end if;
irxd := r.rxdb;
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if (r.rxen and (not r.thempty) and r.txtick) = '1' then
v.tshift := "10" & r.thold & '0'; v.txstate := data;
v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmitt data frame
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
when stopbit => -- transmitt stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if uarti.write = '1' then
v.thold := uarti.data(7 downto 0); v.thempty := '0';
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb2 and (not irxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if irxd = '0' then
v.rshift := irxd & r.rshift(7 downto 1); v.rxstate := data;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.rshift := irxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
v.rxstate := stopbit;
end if;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if irxd = '1' then
v.rsempty := '0';
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
else
if r.rshift = "00000000" then
v.break := '1'; -- break
else
v.frame := '1'; -- framing error
end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
-- reset operation
if rst = '0' then
v.frame := '0'; v.rsempty := '1';
v.ovf := '0'; v.break := '0'; v.thempty := '1';
v.tsempty := '1'; v.dready := '0'; v.fedge := '0';
v.txstate := idle; v.rxstate := idle; v.tshift(0) := '1';
v.scaler := "111111111111111011"; v.brate := (others => '1');
v.rxen := '0'; v.tcnt := "00";
v.txclk := (others => '0'); v.rxclk := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
uo.txd <= r.tshift(0);
uo.scaler <= r.brate;
uo.rtsn <= '0';
uarto.dready <= r.dready;
uarto.tsempty <= r.tsempty;
uarto.thempty <= r.thempty;
uarto.lock <= r.tcnt(1) and r.tcnt(0);
uarto.enable <= r.rxen;
uarto.data <= r.rhold;
apbo.prdata <= rdata;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
| mit | 6d879513ea572da25961c434c8eaf533 | 0.571177 | 3.061212 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/wild2ahb.vhd | 2 | 22,613 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : WildCard CardBus to AMBA interface (entity and architecture)
--
-- File name : wild2ahb.vhd
--
-- Purpose : WildCard CardBus to AMBA interface
--
-- Library : gaisler
--
-- Authors : Mr Sandi Alexander Habinc
-- Gaisler Research
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--============================================================================--
library IEEE;
use IEEE.Std_Logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.wild.all;
entity Wild2AHB is
generic (
hindex: in Integer := 0;
burst: in Integer := 0;
syncrst: in Integer := 0);
port (
rstkn: in Std_ULogic;
clkk: in Std_ULogic;
rstfn: in Std_ULogic;
clkf: in Std_ULogic;
ahbmi: in AHB_Mst_In_Type;
ahbmo: out AHB_Mst_Out_Type;
ladi: in LAD_In_Type;
lado: out LAD_Out_Type);
end entity Wild2AHB; --=======================================================--
library IEEE;
use IEEE.Std_Logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dma2ahb_package.all;
architecture RTL of Wild2AHB is
-----------------------------------------------------------------------------
-- configuration constants
-----------------------------------------------------------------------------
constant REVISION: Integer := 0;
-----------------------------------------------------------------------------
-- WildCard revision constants
-----------------------------------------------------------------------------
constant PE_CORE_MAJOR_VERSION: Std_Logic_Vector(7 downto 0) := x"01";
constant PE_CORE_MINOR_VERSION: Std_Logic_Vector(7 downto 0) := x"03";
constant PE_CORE_VERSION: Std_Logic_Vector(31 downto 0) :=
x"0000" & PE_CORE_MAJOR_VERSION & PE_CORE_MINOR_VERSION;
-----------------------------------------------------------------------------
-- general
-----------------------------------------------------------------------------
signal vcc, gnd: Std_Logic_Vector(7 downto 0);
-----------------------------------------------------------------------------
-- memory buffer type
-----------------------------------------------------------------------------
constant bits: Integer := burst;
constant depth: Integer := 2**bits;
subtype memory_type is Std_Logic_Vector(31 downto 0);
type memory_array is array (0 to depth-1) of memory_type;
-----------------------------------------------------------------------------
-- registers - Main clock domain, X MHz, Clk_F
-----------------------------------------------------------------------------
type register_type is record
-- ahb/dma handling
dmai: dma_in_type;
-- ctrl
error: Std_ULogic;
ready: Std_ULogic;
ongoing: Std_ULogic;
cntr: Integer range 0 to depth;
index: Integer range 0 to depth-1;
rarray: memory_array;
-- sync
active_1st: Std_ULogic;
active_2nd: Std_ULogic;
active: Std_ULogic;
end record;
signal r, rin: register_type;
-----------------------------------------------------------------------------
-- data types - PCI clock domain, 33 MHz, Clk_K
-----------------------------------------------------------------------------
type ctrl_type is record
warray: memory_array;
wsize: Integer range 0 to depth;
wdata: Std_Logic_Vector(31 downto 0);
waddr: Std_Logic_Vector(31 downto 0);
store: Std_ULogic;
addr: Std_Logic_Vector(16 downto 0);
active: Std_ULogic;
fetch: Std_ULogic;
error: Std_ULogic;
error_1st: Std_ULogic;
error_2nd: Std_ULogic;
ready: Std_ULogic;
ready_1st: Std_ULogic;
ready_2nd: Std_ULogic;
end record;
-----------------------------------------------------------------------------
-- registers - PCI clock domain, 33 MHz, Clk_K
-----------------------------------------------------------------------------
type register_lad_type is record
-- input
ladi: LAD_In_Type;
-- lad access control
ctrl: ctrl_type;
end record;
signal rk, rkin: register_lad_type;
-----------------------------------------------------------------------------
-- local unregistered signals
-----------------------------------------------------------------------------
signal dmao: dma_out_type; -- dma output
signal dmai: dma_in_type; -- dma input
-----------------------------------------------------------------------------
-- Reserved space : 0x00008000 - 0x0000FFFC
-- User space : 0x00010000 - 0x0001FFFC
-- Version register : 0x00008000 - (decode bits 15 and 14 only)
-----------------------------------------------------------------------------
constant cUser: Std_Logic_Vector(16 downto 15) := "10";
constant cVersion: Std_Logic_Vector(16 downto 14) := "010";
constant cReserved: Std_Logic_Vector(16 downto 14) := "011";
-----------------------------------------------------------------------------
-- Register addresses:
-----------------------------------------------------------------------------
constant cStat: Std_Logic_Vector(7 downto 0) := X"00";
constant cCtrl: Std_Logic_Vector(7 downto 0) := X"04";
constant cSize: Std_Logic_Vector(7 downto 0) := X"08";
constant cVer: Std_Logic_Vector(7 downto 0) := X"0C";
constant cRAddr: Std_Logic_Vector(7 downto 0) := X"10";
constant cWAddr: Std_Logic_Vector(7 downto 0) := X"20";
constant cRData: Std_Logic_Vector(9 downto 0) := "10" & X"00";
constant cWData: Std_Logic_Vector(9 downto 0) := "11" & X"00";
-- 00 0000 00--
-- 00 0000 01--
-- 00 0000 10--
-- 00 0000 11--
-- 00 0001 ----
-- 00 0010 ----
-- 10 ---- ----
-- 11 ---- ----
-- Read(Addr, Ptr)
-- -> transfer read address (command) - cRAddr
-- -> loop
-- -> check status - cStat
-- -> retreive read data - cRData
--
-- WriteAddr(Addr, Ptr)
-- -> transfer write data - cWData
-- -> transfer write address (command) - cWAddr
-- -> loop
-- -> check status - cStat
-----------------------------------------------------------------------------
-- Status register:
-----------------------------------------------------------------------------
-- Bit: Name: Mode: Remark:
-----------------------------------------------------------------------------
-- 2 Error r/w AMBA error
-- 1 Active r Access on-going
-- 0 Ready r/w Access completed
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Data output
-----------------------------------------------------------------------------
signal Addr_Data, iAddr_Data: Std_Logic_Vector(31 downto 0);
signal Addr_Data_OE_n, iAddr_Data_OE_n: Std_Logic_Vector(31 downto 0);
signal Addr_Data_In: Std_Logic_Vector(31 downto 0);
attribute syn_preserve : Boolean;
attribute syn_preserve of Addr_Data : signal is True;
attribute syn_preserve of Addr_Data_OE_n : signal is True;
attribute syn_preserve of Addr_Data_In : signal is True;
begin
-----------------------------------------------------------------------------
-- combinatorial logic
-----------------------------------------------------------------------------
comb: process(rstfn, rstkn, r, rk, ladi, dmao, Addr_Data_In)
variable v: register_type;
variable vk: register_lad_type;
begin
--------------------------------------------------------------------------
-- local variable copy of register signal
v := r;
vk := rk;
--------------------------------------------------------------------------
-- synchronization of external inputs
vk.ladi := ladi;
--------------------------------------------------------------------------
-- synchronization internally
v.active_1st := rk.ctrl.active;
v.active_2nd := r.active_1st;
if r.active_1st='1' and r.active_2nd='0' then
v.active := '1';
end if;
if r.active_1st='0' and r.active_2nd='0' then
v.active := '0';
end if;
vk.ctrl.error_1st := r.error;
vk.ctrl.error_2nd := rk.ctrl.error_1st;
if rk.ctrl.error_1st='1' and rk.ctrl.error_2nd='0' then
vk.ctrl.error := '1';
end if;
vk.ctrl.ready_1st := r.ready;
vk.ctrl.ready_2nd := rk.ctrl.ready_1st;
if rk.ctrl.ready_1st='1' and not rk.ctrl.ready_2nd='0' then
vk.ctrl.ready := '1';
end if;
--------------------------------------------------------------------------
-- lad interface
--------------------------------------------------------------------------
-- address phase
if rk.ladi.AS_N='0' and rk.ladi.CS_N='0' then
if rk.ladi.Reg_N='0' then
-- register space
if rk.ladi.WR_N='0' then
-- write access
vk.ctrl.store := '1';
else
-- read access
vk.ctrl.store := '0';
end if;
else
-- no access
vk.ctrl.store := '0';
end if;
vk.ctrl.addr := Addr_Data_In(16 downto 0);
end if;
-- data phase - write access
if rk.ladi.DS_N='0' and rk.ladi.CS_N='0' then
if rk.ctrl.store='1' then
if rk.ctrl.addr(9 downto 8)=cWData(9 downto 8) and (burst = 0) then
vk.ctrl.wdata := Addr_Data_In;
elsif rk.ctrl.addr(9 downto 8)=cWData(9 downto 8) and (burst /= 0) then
vk.ctrl.warray(Conv_Integer(rk.ctrl.addr(bits+1 downto 2))):= Addr_Data_In;
elsif rk.ctrl.addr(7 downto 0)=cStat then
vk.ctrl.error := '0';
vk.ctrl.ready := '0';
elsif rk.ctrl.addr(7 downto 0)=cRAddr then
vk.ctrl.waddr := Addr_Data_In;
vk.ctrl.active := '1';
vk.ctrl.fetch := '1';
elsif rk.ctrl.addr(7 downto 0)=cWAddr then
vk.ctrl.waddr := Addr_Data_In;
vk.ctrl.active := '1';
vk.ctrl.fetch := '0';
elsif rk.ctrl.addr(7 downto 0)=cSize and (burst /= 0) then
vk.ctrl.wsize := Conv_Integer(Addr_Data_In);
end if;
end if;
end if;
if rk.ladi.DS_N='0' and rk.ladi.CS_N='0' and (burst /= 0) then
if rk.ladi.Reg_N='0' then
-- register space
-- address increment
vk.ctrl.addr(bits+1 downto 2) := rk.ctrl.addr(bits+1 downto 2) + 1;
end if;
end if;
-- data phase - read access
iAddr_Data <= (others => '0');
if rk.ctrl.addr(16 downto 14)=cVersion then
iAddr_Data <= PE_CORE_VERSION;
elsif rk.ctrl.addr(9 downto 8)=cRData(9 downto 8) and (burst = 0) then
iAddr_Data <= dmao.Data;
elsif rk.ctrl.addr(9 downto 8)=cRData(9 downto 8) and (burst /= 0) then
iAddr_Data <= r.rarray(Conv_Integer(vk.ctrl.addr(bits+1 downto 2)));
elsif rk.ctrl.addr(7 downto 0)=cStat then
iAddr_Data(2) <= rk.ctrl.error;
iAddr_Data(1) <= rk.ctrl.active;
iAddr_Data(0) <= rk.ctrl.ready;
elsif rk.ctrl.addr(7 downto 0)=cVer then
iAddr_Data(11 downto 0) <= Conv_Std_Logic_Vector(depth, 8) & Conv_Std_Logic_Vector(REVISION, 4);
end if;
if rk.ctrl.ready_1st='1' and not rk.ctrl.ready_2nd='0' then
vk.ctrl.active := '0';
end if;
-- combinatorial output enable control
if rk.ladi.CS_N='0' and rk.ladi.WR_N='1' then
iAddr_Data_OE_n <= (others => '0');
else
iAddr_Data_OE_n <= (others => '1');
end if;
--------------------------------------------------------------------------
-- dma interface
--------------------------------------------------------------------------
if r.active='1' and r.ongoing='0' and r.ready='0' then
v.ongoing := '1';
if (burst /= 0) then
if rk.ctrl.fetch='1' then
v.index := 0;
else
v.index := 1;
end if;
if (rk.ctrl.wsize > 0) then
v.cntr := rk.ctrl.wsize-1;
end if;
v.dmai.Data := rk.ctrl.warray(0);
end if;
if (burst /= 0) and (rk.ctrl.wsize > 1) then
v.dmai.Burst := '1';
else
v.dmai.Burst := '0';
end if;
if rk.ctrl.fetch='1' then
v.dmai.Store := '0';
else
v.dmai.Store := '1';
end if;
v.dmai.Request := '1';
elsif r.ongoing='1' then
if dmao.Grant = '1' then
if (burst /= 0) and r.cntr > 0 then
v.cntr := r.cntr - 1;
else
v.dmai.Request := '0';
v.dmai.Burst := '0';
end if;
end if;
if rk.ctrl.fetch='1' then
if dmao.Ready='1' then
if (burst /= 0) then
v.rarray(r.index) := dmao.Data;
end if;
if (burst /= 0) and (r.index < rk.ctrl.wsize-1) and (rk.ctrl.wsize > 0) then
v.index := r.index + 1;
else
v.ready := '1';
v.ongoing := '0';
end if;
end if;
else
if dmao.OKAY='1' then
if (burst /= 0) then
v.dmai.Data := rk.ctrl.warray(r.index);
end if;
if (burst /= 0) and (r.index < rk.ctrl.wsize-1) and (rk.ctrl.wsize > 0) then
v.index := r.index + 1;
else
v.ready := '1';
v.ongoing := '0';
v.dmai.Store:= '0';
end if;
end if;
end if;
if dmao.Fault='1' then
v.error := '1';
v.ready := '1';
v.ongoing := '0';
v.dmai.Burst := '0';
v.dmai.Store := '0';
v.dmai.Request := '0';
end if;
elsif r.active='0' and r.ongoing='0' and (r.ready='1') then
v.ready := '0';
else
v.dmai.Burst := '0';
v.dmai.Request := '0';
v.dmai.Store := '0';
end if;
--======================================================================--
-- Synchronous reset operation
--------------------------------------------------------------------------
if rstfn = '0' then
v.dmai.Request := '0';
v.dmai.Store := '0';
v.error := '0';
v.ready := '0';
v.ongoing := '0';
if (burst /= 0) then
v.cntr := 0;
v.index := 0;
v.dmai.Burst := '0';
end if;
v.active_1st := '0';
v.active_2nd := '0';
v.active := '0';
end if;
if rstkn = '0' then
vk.ladi.WR_n := '1';
vk.ladi.CS_n := '1';
vk.ladi.AS_n := '1';
vk.ladi.Reg_n := '1';
vk.ctrl.addr := (others => '0');
vk.ctrl.store := '0';
vk.ctrl.active := '0';
vk.ctrl.fetch := '0';
if (burst /= 0) then
vk.ctrl.wsize := 0;
end if;
vk.ctrl.error := '0';
vk.ctrl.error_1st := '0';
vk.ctrl.error_2nd := '0';
vk.ctrl.ready := '0';
vk.ctrl.ready_1st := '0';
vk.ctrl.ready_2nd := '0';
vk.ctrl.waddr := (others => '0');
vk.ctrl.wdata := (others => '0');
end if;
--------------------------------------------------------------------------
-- variable to signal assigment
rin <= v;
rkin <= vk;
end process comb;
-----------------------------------------------------------------------------
-- general
-----------------------------------------------------------------------------
vcc <= (others => '1');
gnd <= (others => '0');
-----------------------------------------------------------------------------
-- output ports - non-registered signals
-----------------------------------------------------------------------------
lado.Addr_Data <= Addr_Data;
lado.Addr_Data_OE_n <= Addr_Data_OE_n;
-----------------------------------------------------------------------------
-- output ports - fixed signals
-----------------------------------------------------------------------------
lado.Ack_n <= vcc(0);
lado.Int_Req_n <= vcc(0);
lado.DMA_0_Data_OK_n <= vcc(0);
lado.DMA_0_Burst_OK <= gnd(0);
lado.DMA_1_Data_OK_n <= vcc(0);
lado.DMA_1_Burst_OK <= gnd(0);
lado.Reg_Data_OK_n <= gnd(0);
lado.Reg_Burst_OK <= vcc(0);
lado.Force_K_Clk_n <= gnd(0);
lado.Reserved <= gnd(0);
-----------------------------------------------------------------------------
-- registered signals
-----------------------------------------------------------------------------
dmai.Reset <= '0';
dmai.Request <= r.dmai.Request;
dmai.Burst <= r.dmai.Burst when (burst /= 0) else '0';
dmai.Beat <= HINCR;
dmai.Store <= r.dmai.Store;
dmai.Data <= r.dmai.Data when (burst /= 0) else rk.ctrl.wdata;
dmai.Address <= rk.ctrl.waddr;
dmai.Size <= HSIZE32;
-----------------------------------------------------------------------------
-- registers, Main clock domain, X MHz, Clk_F
-----------------------------------------------------------------------------
regs: process(clkf, rstfn)
begin
if Rising_Edge(clkf) then
r <= rin;
end if;
end process regs;
-----------------------------------------------------------------------------
-- registers, PCI clock domain, 33 MHz, Clk_K
-----------------------------------------------------------------------------
regs_falling: process(clkk, rstkn)
begin
if Falling_Edge(clkk) then
rk <= rkin;
end if;
end process regs_falling;
-- explicit flip-flops for LAD data-address signals for placement in IOB
regs_explicit: process(clkk, rstkn)
begin
if rstkn='0' then
Addr_Data <= (others => '1');
Addr_Data_OE_N <= (others => '1');
Addr_Data_In <= (others => '1');
elsif Falling_Edge(clkk) then
Addr_Data <= iAddr_Data;
Addr_Data_OE_N <= iAddr_Data_OE_N;
Addr_Data_In <= ladi.Addr_Data;
end if;
end process regs_explicit;
---------------------------------------------------------------------------
-- amba ahb master with dma
---------------------------------------------------------------------------
dma2ahb_unit: dma2ahb
generic map(
hindex => hindex,
vendorid => vendor_gaisler,
deviceid => gaisler_wild2ahb,
version => REVISION,
syncrst => syncrst)
port map(
hclk => clkf,
hresetn => rstfn,
dmain => dmai,
dmaout => dmao,
ahbin => ahbmi,
ahbout => ahbmo);
end architecture RTL; --======================================================-- | mit | 3703d23f04c9d0449139bb42f98d8381 | 0.378366 | 4.406274 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu3BaseDCESim.vhd | 1 | 887,201 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(3129 downto 0);
signal or_reduce_1 : std_logic;
signal dfp_delay_start : integer range 0 to 15;
signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right);
signal handlerTrap : std_ulogic;
-- Signals that serve as shadow signals for variables used in the pairs
signal V_A_ET_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow : STD_LOGIC_VECTOR(4 downto 3);
signal ICNT_shadow : STD_ULOGIC;
signal EX_OP1_shadow : WORD;
signal V_M_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal DE_REN1_shadow : STD_ULOGIC;
signal DE_INST_shadow : WORD;
signal V_A_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_W_S_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_RESULT6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_E_ALUCIN_shadow : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_A_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_RESULT1DOWNTO0_shadow : std_logic_vector(1 downto 0);
signal EX_SHCNT_shadow : ASI_TYPE;
signal V_M_DCI_SIZE_shadow : OP_TYPE;
signal V_X_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_MEXC_shadow : STD_ULOGIC;
signal TBUFCNTX_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_A_CTRL_WY_shadow : STD_ULOGIC;
signal NPC_shadow : PCTYPE;
signal V_M_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_MULSTART_shadow : STD_ULOGIC;
signal XC_VECTT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_TT_shadow : OP3_TYPE;
signal DSIGN_shadow : STD_ULOGIC;
signal V_E_CTRL_ANNUL_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow : PCTYPE;
signal V_A_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_RFE1_shadow : STD_ULOGIC;
signal V_W_WA_shadow : RFATYPE;
signal V_X_ANNUL_ALL_shadow : STD_ULOGIC;
signal EX_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES_shadow : STD_LOGIC_VECTOR(32 downto 0);
signal VIR_ADDR_shadow : PCTYPE;
signal EX_JUMP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_CWP_shadow : CWPTYPE;
signal V_D_INST0_shadow : std_logic_vector(31 downto 0);
signal V_A_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_DATA1_shadow : std_logic_vector(31 downto 0);
signal VP_PWD_shadow : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA00_shadow : STD_LOGIC;
signal V_M_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_PS_shadow : STD_ULOGIC;
signal V_X_CTRL_TT_shadow : OP3_TYPE;
signal V_D_STEP_shadow : STD_ULOGIC;
signal V_X_CTRL_WICC_shadow : STD_ULOGIC;
signal VIR_ADDR31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_X_RESULT_shadow : WORD;
signal V_D_CNT_shadow : OP_TYPE;
signal XC_VECTT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_W_S_EF_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow : std_logic_vector(4 downto 0);
signal V_X_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_M_NALIGN_shadow : STD_ULOGIC;
signal XC_WREG_shadow : STD_ULOGIC;
signal V_A_RFA2_shadow : RFATYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow : STD_LOGIC_VECTOR(32 downto 13);
signal EX_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_SU_shadow : STD_ULOGIC;
signal V_E_OP2_shadow : WORD;
signal EX_FORCE_A2_shadow : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_OP131_shadow : STD_LOGIC;
signal V_X_DCI_shadow : DC_IN_TYPE;
signal V_E_CTRL_WICC_shadow : STD_ULOGIC;
signal EX_OP13_shadow : STD_LOGIC;
signal V_F_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST_shadow : WORD;
signal V_E_CTRL_LD_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
signal V_E_SARI_shadow : STD_ULOGIC;
signal V_E_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_PV_shadow : STD_ULOGIC;
signal VDSU_CRDY2_shadow : STD_LOGIC;
signal MUL_OP2_shadow : WORD;
signal XC_EXCEPTION_shadow : STD_ULOGIC;
signal V_E_OP1_shadow : WORD;
signal VP_ERROR_shadow : STD_ULOGIC;
signal V_M_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal MUL_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_M_DCI_shadow : DC_IN_TYPE;
signal EX_OP23_shadow : STD_LOGIC;
signal V_X_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_A_DIVSTART_shadow : STD_ULOGIC;
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal VDSU_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_CTRL_CNT_shadow : OP_TYPE;
signal V_E_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_RFE2_shadow : STD_ULOGIC;
signal V_E_OP13_shadow : STD_LOGIC;
signal V_A_CWP_shadow : CWPTYPE;
signal ME_SIZE_shadow : OP_TYPE;
signal V_X_MAC_shadow : STD_ULOGIC;
signal V_M_CTRL_INST_shadow : WORD;
signal VIR_ADDR31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST20_shadow : STD_LOGIC;
signal DE_REN2_shadow : STD_ULOGIC;
signal V_E_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_MAC_shadow : STD_ULOGIC;
signal V_X_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal EX_ADD_RES3_shadow : STD_LOGIC;
signal V_X_CTRL_INST_shadow : WORD;
signal V_M_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow : OP_TYPE;
signal V_M_CTRL_ANNUL_shadow : STD_ULOGIC;
signal DE_INST19_shadow : STD_LOGIC;
signal XC_HALT_shadow : STD_ULOGIC;
signal V_E_OP231_shadow : STD_LOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_M_CTRL_WICC_shadow : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow : STD_ULOGIC;
signal V_W_S_S_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CWP_shadow : CWPTYPE;
signal V_A_STEP_shadow : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_CTRL_TRAP_shadow : STD_ULOGIC;
signal NPC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_INTACK_shadow : STD_ULOGIC;
signal SIDLE_shadow : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_DATA03_shadow : STD_LOGIC;
signal V_A_CTRL_INST19_shadow : STD_LOGIC;
signal V_W_S_SVT_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_LADDR_shadow : OP_TYPE;
signal V_W_S_DWT_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_TBA_shadow : STD_LOGIC_VECTOR(19 downto 0);
signal XC_WADDR6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_M_MUL_shadow : STD_ULOGIC;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_Y31_shadow : STD_LOGIC;
signal V_E_OP23_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal DE_RADDR17DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_X_DEBUG_shadow : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_CTRL_WREG_shadow : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow : STD_LOGIC;
signal V_D_MEXC_shadow : STD_ULOGIC;
signal V_W_RESULT_shadow : WORD;
signal VFPI_DBG_ENABLE_shadow : STD_ULOGIC;
signal EX_OP131_shadow : STD_LOGIC;
signal V_D_INST1_shadow : std_logic_vector(31 downto 0);
signal V_W_EXCEPT_shadow : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal ME_LADDR_shadow : OP_TYPE;
signal V_X_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_CTRL_RETT_shadow : STD_ULOGIC;
signal XC_WADDR7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_M_MAC_shadow : STD_ULOGIC;
signal V_D_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal VIR_ADDR3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_D_CWP_shadow : CWPTYPE;
signal DE_INST20_shadow : STD_LOGIC;
signal V_D_ANNUL_shadow : STD_ULOGIC;
signal EX_OP2_shadow : WORD;
signal EX_SARI_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DCI_SIZE_shadow : OP_TYPE;
signal V_M_Y_shadow : WORD;
signal V_X_CTRL_PC_shadow : PCTYPE;
signal V_X_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal V_A_CTRL_PC_shadow : PCTYPE;
signal V_A_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_INST20_shadow : STD_LOGIC;
signal V_E_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA0_shadow : std_logic_vector(31 downto 0);
signal V_E_CTRL_INST19_shadow : STD_LOGIC;
signal ME_SIGNED_shadow : STD_ULOGIC;
signal V_W_WREG_shadow : STD_ULOGIC;
signal V_D_PC_shadow : PCTYPE;
signal VFPI_D_ANNUL_shadow : STD_ULOGIC;
signal DE_RADDR27DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC_shadow : PCTYPE;
signal V_X_DATA031_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_X_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT_shadow : OP3_TYPE;
signal V_X_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_INST24_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_NERROR_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_W_S_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_F_BRANCH_shadow : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow : STD_ULOGIC;
signal V_A_CTRL_LD_shadow : STD_ULOGIC;
signal V_A_CTRL_TT_shadow : OP3_TYPE;
signal V_M_CTRL_LD_shadow : STD_ULOGIC;
signal V_E_SHCNT_shadow : ASI_TYPE;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST_shadow : WORD;
signal V_A_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal VIR_PWD_shadow : STD_ULOGIC;
signal XC_RESULT_shadow : WORD;
signal V_A_RFA1_shadow : RFATYPE;
signal V_E_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal ME_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal DE_INST24_shadow : STD_LOGIC;
signal XC_TRAP_shadow : STD_ULOGIC;
signal VDSU_TBUFCNT_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal XC_TRAP_ADDRESS_shadow : PCTYPE;
-- Intermediate value holding signal declarations
signal V_E_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal V_M_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_RFA1_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_4 : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_2 : STD_LOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal V_X_DATA00_shadow_intermed_3 : STD_LOGIC;
signal RIN_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WICC_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_3 : STD_ULOGIC;
signal RPIN_PWD_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal DE_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DBGI_DADDR9DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(9 downto 2);
signal R_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_STEP_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_7 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_1 : STD_LOGIC;
signal V_D_INST0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_YMSB_intermed_1 : STD_ULOGIC;
signal R_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_X_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_F_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_DATA04DOWNTO0_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal R_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal R_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal RIN_M_DCI_LOCK_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal R_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_ET_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal DBGI_STEP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_X_LADDR_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_WA_intermed_1 : std_logic_vector(7 downto 0);
signal V_D_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_2 : STD_LOGIC;
signal V_M_RESULT1DOWNTO0_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_DATA03_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_intermed_1 : DC_IN_TYPE;
signal DSUIN_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_D_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal ICO_MEXC_intermed_1 : STD_ULOGIC;
signal R_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_DCI_SIZE_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_W_S_S_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal R_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_S_ET_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal VIR_ADDR31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_8 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_X_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal DCO_DATA00_intermed_2 : STD_LOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal R_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_X_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_X_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal IR_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_X_DATA1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal ICO_MEXC_intermed_3 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal R_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_WICC_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_5 : STD_ULOGIC;
signal RIN_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal R_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_M_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_7 : std_logic_vector(31 downto 4);
signal RIN_E_OP13_intermed_1 : STD_LOGIC;
signal RIN_A_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_OP2_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal R_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_M_Y31_intermed_2 : STD_LOGIC;
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal XC_VECTT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_4 : STD_ULOGIC;
signal RIN_W_S_TBA_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal V_D_INST1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DATA031_intermed_1 : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 13);
signal R_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_X_DATA031_intermed_1 : STD_LOGIC;
signal R_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_SARI_intermed_1 : STD_ULOGIC;
signal R_M_Y31_intermed_1 : STD_LOGIC;
signal IR_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_W_S_S_shadow_intermed_2 : STD_ULOGIC;
signal DE_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal V_A_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow_intermed_2 : std_logic_vector(4 downto 0);
signal R_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal DCO_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_X_DATA0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_E_OP131_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST19_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal V_X_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_RFE2_shadow_intermed_1 : STD_ULOGIC;
signal V_M_Y_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal DE_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_MEXC_shadow_intermed_4 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_W_S_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal R_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal IR_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal R_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow_intermed_1 : STD_ULOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_X_DATA04DOWNTO0_intermed_3 : std_logic_vector(4 downto 0);
signal V_X_NERROR_shadow_intermed_1 : STD_ULOGIC;
signal V_A_RFE1_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal ICO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal VIR_ADDR_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_W_S_DWT_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_X_NERROR_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_5 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal IRIN_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal V_X_DATA00_shadow_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_M_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal R_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_DEBUG_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PV_intermed_4 : STD_ULOGIC;
signal R_E_MAC_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal IR_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_JMPL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal RIN_M_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_X_DATA04DOWNTO0_shadow_intermed_3 : std_logic_vector(4 downto 0);
signal RIN_W_S_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_DATA031_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_3 : STD_LOGIC;
signal DCO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_X_DATA0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 : std_logic_vector(3 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RPIN_ERROR_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_W_S_S_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal V_A_RFA1_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_CTRL_shadow_intermed_3 : PIPELINE_CTRL_TYPE;
signal R_D_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_1 : STD_LOGIC;
signal V_A_DIVSTART_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_4 : STD_ULOGIC;
signal RIN_W_S_PS_intermed_1 : STD_ULOGIC;
signal R_D_MEXC_intermed_3 : STD_ULOGIC;
signal RIN_A_RFA2_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_W_S_SVT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_4 : std_logic_vector(6 downto 0);
signal RIN_E_OP23_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_D_MEXC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_7 : std_logic_vector(31 downto 4);
signal R_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_8 : std_logic_vector(31 downto 12);
signal VP_PWD_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_NALIGN_intermed_1 : STD_ULOGIC;
signal RP_ERROR_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_W_S_TBA_shadow_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal R_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_JMPL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_RFE2_intermed_1 : STD_ULOGIC;
signal RIN_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_M_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_E_MAC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal IRIN_ADDR_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_CWP_shadow_intermed_2 : std_logic_vector(2 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_A_MULSTART_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_M_DCI_SIGNED_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal IRIN_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal V_M_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_DCI_SIGNED_shadow_intermed_2 : STD_ULOGIC;
signal R_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST19_intermed_3 : STD_LOGIC;
signal V_E_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_X_DATA1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_CWP_intermed_2 : std_logic_vector(2 downto 0);
signal R_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_A_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal DCO_DATA031_intermed_2 : STD_LOGIC;
signal R_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_E_YMSB_shadow_intermed_1 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_M_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DE_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal VIR_ADDR3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_3 : PIPELINE_CTRL_TYPE;
signal RIN_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_A_DIVSTART_intermed_1 : STD_ULOGIC;
signal VIR_ADDR31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_X_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal DSUR_CRDY2_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST_intermed_4 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal DE_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_MULSTART_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_M_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 3);
signal V_A_CTRL_PV_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_WREG_shadow_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_W_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal R_D_ANNUL_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_E_SARI_shadow_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal R_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_M_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal DSUIN_CRDY2_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_M_DCI_SIZE_intermed_2 : std_logic_vector(1 downto 0);
signal DE_INST19_shadow_intermed_3 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_ANNUL_shadow_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal IRIN_PWD_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_5 : STD_ULOGIC;
signal RIN_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TRAP_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal R_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_DATA03_intermed_1 : STD_LOGIC;
signal R_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal R_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_X_MAC_intermed_1 : STD_ULOGIC;
signal V_E_SHCNT_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_OP23_shadow_intermed_1 : STD_LOGIC;
signal V_D_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal R_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_W_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_LADDR_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_5 : std_logic_vector(31 downto 2);
signal XC_VECTT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal V_D_STEP_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal DE_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_5 : STD_ULOGIC;
signal RIN_X_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_F_BRANCH_intermed_1 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_DATA00_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_JMPL_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal DSUR_CRDY2_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA00_intermed_3 : STD_LOGIC;
signal R_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_OP131_intermed_1 : STD_LOGIC;
signal R_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal DE_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_ET_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST20_intermed_3 : STD_LOGIC;
signal RIN_W_EXCEPT_intermed_1 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_2 : STD_LOGIC;
signal R_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal R_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal VIR_ADDR31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_M_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal VIR_ADDR3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_ANNUL_shadow_intermed_3 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal R_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal R_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_E_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST24_intermed_3 : STD_LOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal DE_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PV_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal R_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_MAC_intermed_1 : STD_ULOGIC;
signal R_X_DATA00_intermed_2 : STD_LOGIC;
signal RIN_E_MAC_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_INTACK_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_ANNUL_intermed_5 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_X_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal DE_INST20_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal IR_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_ALUCIN_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_E_OP13_shadow_intermed_1 : STD_LOGIC;
signal V_A_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_6 : std_logic_vector(3 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_7 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal R_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal R_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_WREG_intermed_4 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal R_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal IRIN_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_OP1_intermed_1 : std_logic_vector(31 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal DE_INST20_shadow_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_E_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_M_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_INTACK_intermed_1 : STD_ULOGIC;
signal RIN_E_OP231_intermed_1 : STD_LOGIC;
signal RIN_X_DATA031_intermed_3 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_F_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_ET_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_3 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal ICO_MEXC_intermed_2 : STD_ULOGIC;
signal V_X_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_STEP_intermed_1 : STD_ULOGIC;
signal V_E_ALUCIN_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_M_MUL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal R_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_D_INST0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DCO_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO12_shadow_intermed_8 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WY_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal V_M_DCI_shadow_intermed_1 : DC_IN_TYPE;
signal V_M_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal RIN_D_MEXC_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DSUIN_TBUFCNT_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 : std_logic_vector(6 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal V_D_INST1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DEBUG_intermed_1 : STD_ULOGIC;
signal RIN_M_Y_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_SHCNT_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal RIN_D_ANNUL_intermed_2 : STD_ULOGIC;
signal ICO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_MEXC_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal DSUIN_CRDY2_intermed_2 : STD_LOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_DATA031_shadow_intermed_1 : STD_LOGIC;
signal RIN_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_D_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal DCO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_S_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_LD_shadow_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal V_E_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_F_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO2_shadow_intermed_8 : std_logic_vector(31 downto 2);
signal V_D_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal R_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_M_RESULT1DOWNTO0_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_5 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal V_X_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_5 : std_logic_vector(1 downto 0);
signal R_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_W_S_S_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_A_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal R_X_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_intermed_1 : DC_IN_TYPE;
signal R_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_EF_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_LD_intermed_3 : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal V_F_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 : STD_LOGIC_VECTOR(30 downto 11);
signal V_X_ANNUL_ALL_shadow_intermed_3 : STD_ULOGIC;
signal V_F_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal R_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RETT_intermed_3 : STD_ULOGIC;
signal R_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 3);
signal V_E_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_E_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal V_A_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_OP231_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RPIN_ERROR_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_D_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal DCO_DATA00_intermed_1 : STD_LOGIC;
signal V_M_Y31_shadow_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal DCO_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_DATA03_shadow_intermed_1 : STD_LOGIC;
signal V_E_OP1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal V_M_Y31_shadow_intermed_2 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal R_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_RFE1_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_M_MAC_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal R_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_DATA00_intermed_1 : STD_LOGIC;
signal V_X_ANNUL_ALL_shadow_intermed_1 : STD_ULOGIC;
signal R_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_F_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_W_S_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_W_S_PS_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal R_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_MAC_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_ICC_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_MAC_intermed_1 : STD_ULOGIC;
signal RIN_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal R_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 13);
signal RIN_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal IR_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_2 : STD_LOGIC;
signal RIN_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_E_OP2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif false and false and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if true then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if false then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not true) and (r.w.s.cwp = "000") then v.w.s.cwp := "111";
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
end if;
if true then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if true then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(7 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.w.s.ef := '0'; -- needed for AX
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := "000";
v.w.s.icc := "0000";
end if;
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := "00000000"; end if;
if true then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to 2-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if false and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if 0 = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000",
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if 2 > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000"; de_raddr2 := "0000000000";
if true then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if true then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2); de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := "000";
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000"; v.f.branch := '0';
if false then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to 2-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(0 downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if true then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if false then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if true then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if true then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
V_A_ET_shadow <= V.A.ET;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 4 DOWNTO 3 );
ICNT_shadow <= ICNT;
EX_OP1_shadow <= EX_OP1;
V_M_CTRL_PC_shadow <= V.M.CTRL.PC;
V_E_CTRL_PC3DOWNTO2_shadow <= V.E.CTRL.PC( 3 DOWNTO 2 );
DE_REN1_shadow <= DE_REN1;
DE_INST_shadow <= DE_INST;
V_A_CTRL_CNT_shadow <= V.A.CTRL.CNT;
V_F_PC3DOWNTO2_shadow <= V.F.PC( 3 DOWNTO 2 );
V_W_S_TT_shadow <= V.W.S.TT;
V_X_RESULT6DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 );
EX_JUMP_ADDRESS3DOWNTO2_shadow <= EX_JUMP_ADDRESS( 3 DOWNTO 2 );
V_E_ALUCIN_shadow <= V.E.ALUCIN;
V_D_PC3DOWNTO2_shadow <= V.D.PC( 3 DOWNTO 2 );
V_A_CTRL_PV_shadow <= V.A.CTRL.PV;
V_E_CTRL_shadow <= V.E.CTRL;
V_M_CTRL_shadow <= V.M.CTRL;
V_M_RESULT1DOWNTO0_shadow <= V.M.RESULT ( 1 DOWNTO 0 );
EX_SHCNT_shadow <= EX_SHCNT;
V_M_DCI_SIZE_shadow <= V.M.DCI.SIZE;
V_X_CTRL_ANNUL_shadow <= V.X.CTRL.ANNUL;
V_X_MEXC_shadow <= V.X.MEXC;
TBUFCNTX_shadow <= TBUFCNTX;
V_A_CTRL_WY_shadow <= V.A.CTRL.WY;
NPC_shadow <= NPC;
V_M_CTRL_TT3DOWNTO0_shadow <= V.M.CTRL.TT( 3 DOWNTO 0 );
V_A_MULSTART_shadow <= V.A.MULSTART;
XC_VECTT3DOWNTO0_shadow <= XC_VECTT( 3 DOWNTO 0 );
V_E_CTRL_TT_shadow <= V.E.CTRL.TT;
DSIGN_shadow <= DSIGN;
V_E_CTRL_ANNUL_shadow <= V.E.CTRL.ANNUL;
EX_JUMP_ADDRESS_shadow <= EX_JUMP_ADDRESS;
V_A_CTRL_PC31DOWNTO12_shadow <= V.A.CTRL.PC( 31 DOWNTO 12 );
V_A_RFE1_shadow <= V.A.RFE1;
V_W_WA_shadow <= V.W.WA;
V_X_ANNUL_ALL_shadow <= V.X.ANNUL_ALL;
EX_YMSB_shadow <= EX_YMSB;
EX_ADD_RES_shadow <= EX_ADD_RES;
VIR_ADDR_shadow <= VIR.ADDR;
EX_JUMP_ADDRESS31DOWNTO12_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 12 );
V_W_S_CWP_shadow <= V.W.S.CWP;
V_D_INST0_shadow <= V.D.INST ( 0 );
V_A_CTRL_ANNUL_shadow <= V.A.CTRL.ANNUL;
V_X_DATA1_shadow <= V.X.DATA ( 1 );
VP_PWD_shadow <= VP.PWD;
V_M_CTRL_RD6DOWNTO0_shadow <= V.M.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA00_shadow <= V.X.DATA ( 0 )( 0 );
V_M_CTRL_RETT_shadow <= V.M.CTRL.RETT;
V_X_CTRL_RETT_shadow <= V.X.CTRL.RETT;
V_X_CTRL_PC31DOWNTO12_shadow <= V.X.CTRL.PC( 31 DOWNTO 12 );
V_W_S_PS_shadow <= V.W.S.PS;
V_X_CTRL_TT_shadow <= V.X.CTRL.TT;
V_D_STEP_shadow <= V.D.STEP;
V_X_CTRL_WICC_shadow <= V.X.CTRL.WICC;
VIR_ADDR31DOWNTO2_shadow <= VIR.ADDR( 31 DOWNTO 2 );
V_M_CTRL_RD7DOWNTO0_shadow <= V.M.CTRL.RD ( 7 DOWNTO 0 );
V_X_RESULT_shadow <= V.X.RESULT;
V_D_CNT_shadow <= V.D.CNT;
XC_VECTT_shadow <= XC_VECTT;
EX_ADD_RES32DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 );
V_W_S_EF_shadow <= V.W.S.EF;
V_A_CTRL_PC31DOWNTO2_shadow <= V.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA04DOWNTO0_shadow <= V.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DCI_SIGNED_shadow <= V.X.DCI.SIGNED;
V_M_NALIGN_shadow <= V.M.NALIGN;
XC_WREG_shadow <= XC_WREG;
V_A_RFA2_shadow <= V.A.RFA2;
V_E_CTRL_PC31DOWNTO12_shadow <= V.E.CTRL.PC( 31 DOWNTO 12 );
EX_ADD_RES32DOWNTO332DOWNTO13_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 13 );
EX_OP231_shadow <= EX_OP2( 31 );
XC_TRAP_ADDRESS31DOWNTO4_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 4 );
V_X_ICC_shadow <= V.X.ICC;
V_A_SU_shadow <= V.A.SU;
V_E_OP2_shadow <= V.E.OP2;
EX_FORCE_A2_shadow <= EX_FORCE_A2;
V_E_CTRL_PC31DOWNTO2_shadow <= V.E.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO4_shadow <= V.E.CTRL.PC( 31 DOWNTO 4 );
V_E_OP131_shadow <= V.E.OP1( 31 );
V_X_DCI_shadow <= V.X.DCI;
V_E_CTRL_WICC_shadow <= V.E.CTRL.WICC;
EX_OP13_shadow <= EX_OP1( 3 );
V_F_PC31DOWNTO12_shadow <= V.F.PC( 31 DOWNTO 12 );
V_E_CTRL_INST_shadow <= V.E.CTRL.INST;
V_E_CTRL_LD_shadow <= V.E.CTRL.LD;
V_M_SU_shadow <= V.M.SU;
V_E_SARI_shadow <= V.E.SARI;
V_E_ET_shadow <= V.E.ET;
V_M_CTRL_PV_shadow <= V.M.CTRL.PV;
VDSU_CRDY2_shadow <= VDSU.CRDY ( 2 );
MUL_OP2_shadow <= MUL_OP2;
XC_EXCEPTION_shadow <= XC_EXCEPTION;
V_E_OP1_shadow <= V.E.OP1;
VP_ERROR_shadow <= VP.ERROR;
V_M_DCI_SIGNED_shadow <= V.M.DCI.SIGNED;
V_D_PC31DOWNTO12_shadow <= V.D.PC( 31 DOWNTO 12 );
MUL_OP231_shadow <= MUL_OP2 ( 31 );
XC_TRAP_ADDRESS31DOWNTO2_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow <= V.M.CTRL.PC( 3 DOWNTO 2 );
V_M_DCI_shadow <= V.M.DCI;
EX_OP23_shadow <= EX_OP2( 3 );
V_X_CTRL_RD6DOWNTO0_shadow <= V.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_TRAP_shadow <= V.X.CTRL.TRAP;
V_A_DIVSTART_shadow <= V.A.DIVSTART;
V_X_RESULT6DOWNTO03DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
VDSU_TT_shadow <= VDSU.TT;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 5 );
V_X_CTRL_CNT_shadow <= V.X.CTRL.CNT;
V_E_YMSB_shadow <= V.E.YMSB;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 30 DOWNTO 11 );
V_A_RFE2_shadow <= V.A.RFE2;
V_E_OP13_shadow <= V.E.OP1( 3 );
V_A_CWP_shadow <= V.A.CWP;
ME_SIZE_shadow <= ME_SIZE;
V_X_MAC_shadow <= V.X.MAC;
V_M_CTRL_INST_shadow <= V.M.CTRL.INST;
VIR_ADDR31DOWNTO4_shadow <= VIR.ADDR( 31 DOWNTO 4 );
V_A_CTRL_INST20_shadow <= V.A.CTRL.INST( 20 );
DE_REN2_shadow <= DE_REN2;
V_E_CTRL_PV_shadow <= V.E.CTRL.PV;
V_E_MAC_shadow <= V.E.MAC;
V_X_CTRL_TT3DOWNTO0_shadow <= V.X.CTRL.TT( 3 DOWNTO 0 );
EX_ADD_RES3_shadow <= EX_ADD_RES ( 3 );
V_X_CTRL_INST_shadow <= V.X.CTRL.INST;
V_M_CTRL_PC31DOWNTO2_shadow <= V.M.CTRL.PC( 31 DOWNTO 2 );
V_W_S_ET_shadow <= V.W.S.ET;
V_M_CTRL_CNT_shadow <= V.M.CTRL.CNT;
V_M_CTRL_ANNUL_shadow <= V.M.CTRL.ANNUL;
DE_INST19_shadow <= DE_INST( 19 );
XC_HALT_shadow <= XC_HALT;
V_E_OP231_shadow <= V.E.OP2( 31 );
V_A_CTRL_PC3DOWNTO2_shadow <= V.A.CTRL.PC( 3 DOWNTO 2 );
VIR_ADDR31DOWNTO12_shadow <= VIR.ADDR( 31 DOWNTO 12 );
V_M_CTRL_WICC_shadow <= V.M.CTRL.WICC;
V_M_CTRL_WREG_shadow <= V.M.CTRL.WREG;
V_W_S_S_shadow <= V.W.S.S;
V_F_PC31DOWNTO2_shadow <= V.F.PC( 31 DOWNTO 2 );
V_E_CWP_shadow <= V.E.CWP;
V_A_STEP_shadow <= V.A.STEP;
V_A_CTRL_TT3DOWNTO0_shadow <= V.A.CTRL.TT( 3 DOWNTO 0 );
V_A_CTRL_TRAP_shadow <= V.A.CTRL.TRAP;
NPC31DOWNTO2_shadow <= NPC ( 31 DOWNTO 2 );
V_M_CTRL_TRAP_shadow <= V.M.CTRL.TRAP;
V_D_PC31DOWNTO4_shadow <= V.D.PC( 31 DOWNTO 4 );
V_X_INTACK_shadow <= V.X.INTACK;
SIDLE_shadow <= SIDLE;
V_A_CTRL_RETT_shadow <= V.A.CTRL.RETT;
V_X_DATA03_shadow <= V.X.DATA ( 0 )( 3 );
V_A_CTRL_INST19_shadow <= V.A.CTRL.INST( 19 );
V_W_S_SVT_shadow <= V.W.S.SVT;
V_A_CTRL_PC31DOWNTO4_shadow <= V.A.CTRL.PC( 31 DOWNTO 4 );
V_X_LADDR_shadow <= V.X.LADDR;
V_W_S_DWT_shadow <= V.W.S.DWT;
EX_JUMP_ADDRESS31DOWNTO2_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 2 );
V_W_S_TBA_shadow <= V.W.S.TBA;
XC_WADDR6DOWNTO0_shadow <= XC_WADDR ( 6 DOWNTO 0 );
V_M_MUL_shadow <= V.M.MUL;
V_E_SU_shadow <= V.E.SU;
V_M_Y31_shadow <= V.M.Y ( 31 );
V_E_OP23_shadow <= V.E.OP2( 3 );
V_M_CTRL_PC31DOWNTO4_shadow <= V.M.CTRL.PC( 31 DOWNTO 4 );
DE_RADDR17DOWNTO0_shadow <= DE_RADDR1 ( 7 DOWNTO 0 );
V_X_CTRL_PC31DOWNTO2_shadow <= V.X.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_TRAP_shadow <= V.E.CTRL.TRAP;
V_X_DEBUG_shadow <= V.X.DEBUG;
V_M_DCI_LOCK_shadow <= V.M.DCI.LOCK;
V_X_CTRL_PC3DOWNTO2_shadow <= V.X.CTRL.PC( 3 DOWNTO 2 );
V_X_CTRL_WREG_shadow <= V.X.CTRL.WREG;
V_E_CTRL_INST24_shadow <= V.E.CTRL.INST( 24 );
V_D_MEXC_shadow <= V.D.MEXC;
V_W_RESULT_shadow <= V.W.RESULT;
VFPI_DBG_ENABLE_shadow <= VFPI.DBG.ENABLE;
EX_OP131_shadow <= EX_OP1 ( 31 );
V_D_INST1_shadow <= V.D.INST ( 1 );
V_W_EXCEPT_shadow <= V.W.EXCEPT;
V_E_CTRL_TT3DOWNTO0_shadow <= V.E.CTRL.TT( 3 DOWNTO 0 );
ME_LADDR_shadow <= ME_LADDR;
V_X_CTRL_PC31DOWNTO4_shadow <= V.X.CTRL.PC( 31 DOWNTO 4 );
V_E_CTRL_RETT_shadow <= V.E.CTRL.RETT;
XC_WADDR7DOWNTO0_shadow <= XC_WADDR ( 7 DOWNTO 0 );
V_X_CTRL_PV_shadow <= V.X.CTRL.PV;
V_E_CTRL_RD6DOWNTO0_shadow <= V.E.CTRL.RD( 6 DOWNTO 0 );
V_M_MAC_shadow <= V.M.MAC;
V_D_SET_shadow <= V.D.SET;
VIR_ADDR3DOWNTO2_shadow <= VIR.ADDR( 3 DOWNTO 2 );
V_D_CWP_shadow <= V.D.CWP;
DE_INST20_shadow <= DE_INST( 20 );
V_D_ANNUL_shadow <= V.D.ANNUL;
EX_OP2_shadow <= EX_OP2;
EX_SARI_shadow <= EX_SARI;
V_D_PC31DOWNTO2_shadow <= V.D.PC( 31 DOWNTO 2 );
V_X_DCI_SIZE_shadow <= V.X.DCI.SIZE;
V_M_Y_shadow <= V.M.Y;
V_X_CTRL_PC_shadow <= V.X.CTRL.PC;
V_X_SET_shadow <= V.X.SET;
V_A_CTRL_PC_shadow <= V.A.CTRL.PC;
V_A_JMPL_shadow <= V.A.JMPL;
V_E_CTRL_PC_shadow <= V.E.CTRL.PC;
V_E_CTRL_INST20_shadow <= V.E.CTRL.INST( 20 );
V_E_CTRL_WREG_shadow <= V.E.CTRL.WREG;
V_A_CTRL_WREG_shadow <= V.A.CTRL.WREG;
V_A_CTRL_shadow <= V.A.CTRL;
V_A_CTRL_RD6DOWNTO0_shadow <= V.A.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA0_shadow <= V.X.DATA ( 0 );
V_E_CTRL_INST19_shadow <= V.E.CTRL.INST( 19 );
ME_SIGNED_shadow <= ME_SIGNED;
V_W_WREG_shadow <= V.W.WREG;
V_D_PC_shadow <= V.D.PC;
VFPI_D_ANNUL_shadow <= VFPI.D.ANNUL;
DE_RADDR27DOWNTO0_shadow <= DE_RADDR2 ( 7 DOWNTO 0 );
V_E_CTRL_CNT_shadow <= V.E.CTRL.CNT;
V_F_PC_shadow <= V.F.PC;
V_X_DATA031_shadow <= V.X.DATA ( 0 )( 31 );
V_M_CTRL_PC31DOWNTO12_shadow <= V.M.CTRL.PC( 31 DOWNTO 12 );
V_X_CTRL_RD7DOWNTO0_shadow <= V.X.CTRL.RD ( 7 DOWNTO 0 );
V_M_CTRL_TT_shadow <= V.M.CTRL.TT;
V_X_CTRL_shadow <= V.X.CTRL;
V_A_CTRL_INST24_shadow <= V.A.CTRL.INST( 24 );
XC_TRAP_ADDRESS3DOWNTO2_shadow <= XC_TRAP_ADDRESS( 3 DOWNTO 2 );
V_X_NERROR_shadow <= V.X.NERROR;
V_F_PC31DOWNTO4_shadow <= V.F.PC( 31 DOWNTO 4 );
V_W_S_TT3DOWNTO0_shadow <= V.W.S.TT( 3 DOWNTO 0 );
EX_JUMP_ADDRESS31DOWNTO4_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 4 );
EX_ADD_RES32DOWNTO332DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 3 );
V_F_BRANCH_shadow <= V.F.BRANCH;
V_A_CTRL_WICC_shadow <= V.A.CTRL.WICC;
V_A_CTRL_LD_shadow <= V.A.CTRL.LD;
V_A_CTRL_TT_shadow <= V.A.CTRL.TT;
V_M_CTRL_LD_shadow <= V.M.CTRL.LD;
V_E_SHCNT_shadow <= V.E.SHCNT;
XC_TRAP_ADDRESS31DOWNTO12_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 12 );
V_A_CTRL_INST_shadow <= V.A.CTRL.INST;
V_A_CTRL_RD7DOWNTO0_shadow <= V.A.CTRL.RD ( 7 DOWNTO 0 );
VIR_PWD_shadow <= VIR.PWD;
XC_RESULT_shadow <= XC_RESULT;
V_A_RFA1_shadow <= V.A.RFA1;
V_E_JMPL_shadow <= V.E.JMPL;
V_E_CTRL_RD7DOWNTO0_shadow <= V.E.CTRL.RD ( 7 DOWNTO 0 );
ME_ICC_shadow <= ME_ICC;
DE_INST24_shadow <= DE_INST( 24 );
XC_TRAP_shadow <= XC_TRAP;
VDSU_TBUFCNT_shadow <= VDSU.TBUFCNT;
XC_TRAP_ADDRESS_shadow <= XC_TRAP_ADDRESS;
end process;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
V_W_S_S_shadow_intermed_2 <= V_W_S_S_shadow_intermed_1;
V_W_S_PS_shadow_intermed_1 <= V_W_S_PS_shadow;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
R_W_S_S_intermed_1 <= R.W.S.S;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_S_intermed_2 <= RIN_W_S_S_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_X_RESULT6DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_X_DATA0_intermed_2 <= R_X_DATA0_intermed_1;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_3 <= R_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
R_A_CTRL_TT3DOWNTO0_intermed_5 <= R_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_6 <= RIN_A_CTRL_TT3DOWNTO0_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_W_S_TT3DOWNTO0_intermed_2 <= R_W_S_TT3DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_4 <= R_E_CTRL_TT3DOWNTO0_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_M_CTRL_TT3DOWNTO0_intermed_4 <= RIN_M_CTRL_TT3DOWNTO0_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_X_CTRL_TT3DOWNTO0_intermed_3 <= RIN_X_CTRL_TT3DOWNTO0_intermed_2;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
R_X_CTRL_TT3DOWNTO0_intermed_2 <= R_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
RIN_E_CTRL_TT3DOWNTO0_intermed_5 <= RIN_E_CTRL_TT3DOWNTO0_intermed_4;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_2 <= XC_VECTT3DOWNTO0_shadow_intermed_1;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_M_DCI_LOCK_intermed_1 <= RIN.M.DCI.LOCK;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_M_DCI_LOCK_shadow_intermed_1 <= V_M_DCI_LOCK_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
DCO_DATA031_intermed_2 <= DCO_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_3 <= DE_INST19_shadow_intermed_2;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_E_CTRL_INST19_intermed_2 <= R_E_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_E_CTRL_INST20_intermed_2 <= R_E_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_3 <= DE_INST20_shadow_intermed_2;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
DCO_DATA00_intermed_2 <= DCO_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_2 <= DCO_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_4 <= R_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_5 <= RIN_M_CTRL_PC31DOWNTO2_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_7 <= RIN_A_CTRL_PC31DOWNTO2_intermed_6;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_6 <= R_A_CTRL_PC31DOWNTO2_intermed_5;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_X_CTRL_PC31DOWNTO2_intermed_3 <= R_X_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_D_PC31DOWNTO2_shadow_intermed_8 <= V_D_PC31DOWNTO2_shadow_intermed_7;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
RIN_D_PC31DOWNTO2_intermed_8 <= RIN_D_PC31DOWNTO2_intermed_7;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_CTRL_PC31DOWNTO2_intermed_4 <= RIN_X_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_3 <= IRIN_ADDR31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_5 <= R_E_CTRL_PC31DOWNTO2_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_D_PC31DOWNTO2_intermed_7 <= R_D_PC31DOWNTO2_intermed_6;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_2 <= IR_ADDR31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_6 <= RIN_E_CTRL_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
R_F_PC31DOWNTO2_intermed_2 <= R_F_PC31DOWNTO2_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
VIR_ADDR31DOWNTO2_shadow_intermed_3 <= VIR_ADDR31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
V_A_MULSTART_shadow_intermed_1 <= V_A_MULSTART_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_MULSTART_intermed_1 <= RIN.A.MULSTART;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_3 <= DE_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_E_CTRL_INST24_intermed_2 <= R_E_CTRL_INST24_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_DIVSTART_intermed_1 <= RIN.A.DIVSTART;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_DIVSTART_shadow_intermed_1 <= V_A_DIVSTART_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
RIN_M_Y_intermed_1 <= RIN.M.Y;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y_shadow_intermed_1 <= V_M_Y_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_M_Y31_intermed_1 <= R.M.Y( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
R_M_Y31_intermed_2 <= R_M_Y31_intermed_1;
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
DSUR_CRDY2_intermed_2 <= DSUR_CRDY2_intermed_1;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
VP_ERROR_shadow_intermed_2 <= VP_ERROR_shadow_intermed_1;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RPIN_ERROR_intermed_2 <= RPIN_ERROR_intermed_1;
V_X_NERROR_shadow_intermed_1 <= V_X_NERROR_shadow;
RP_ERROR_intermed_1 <= RP.ERROR;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
DCO_DATA1_intermed_1 <= DCO.DATA ( 1 );
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
R_X_DATA1_intermed_2 <= R_X_DATA1_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_A_CTRL_PC31DOWNTO12_intermed_7 <= RIN_A_CTRL_PC31DOWNTO12_intermed_6;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_6 <= RIN_E_CTRL_PC31DOWNTO12_intermed_5;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_4 <= R_M_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_3 <= IRIN_ADDR31DOWNTO12_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
R_F_PC31DOWNTO12_intermed_2 <= R_F_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
RIN_M_CTRL_PC31DOWNTO12_intermed_5 <= RIN_M_CTRL_PC31DOWNTO12_intermed_4;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
IR_ADDR31DOWNTO12_intermed_2 <= IR_ADDR31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_3 <= R_X_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_D_PC31DOWNTO12_shadow_intermed_8 <= V_D_PC31DOWNTO12_shadow_intermed_7;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_D_PC31DOWNTO12_intermed_7 <= R_D_PC31DOWNTO12_intermed_6;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_A_CTRL_PC31DOWNTO12_intermed_6 <= R_A_CTRL_PC31DOWNTO12_intermed_5;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_5 <= R_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_X_CTRL_PC31DOWNTO12_intermed_4 <= RIN_X_CTRL_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
RIN_D_PC31DOWNTO12_intermed_8 <= RIN_D_PC31DOWNTO12_intermed_7;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
VIR_ADDR31DOWNTO12_shadow_intermed_3 <= VIR_ADDR31DOWNTO12_shadow_intermed_2;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4;
ICO_DATA0_intermed_1 <= ICO.DATA ( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
R_D_INST1_intermed_2 <= R_D_INST1_intermed_1;
ICO_DATA1_intermed_1 <= ICO.DATA ( 1 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
R_X_DATA03_intermed_2 <= R_X_DATA03_intermed_1;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_E_ALUCIN_shadow_intermed_1 <= V_E_ALUCIN_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_E_ALUCIN_intermed_1 <= RIN.E.ALUCIN;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_E_YMSB_shadow_intermed_1 <= V_E_YMSB_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_E_YMSB_intermed_1 <= RIN.E.YMSB;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_E_SHCNT_shadow_intermed_1 <= V_E_SHCNT_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_E_SHCNT_intermed_1 <= RIN.E.SHCNT;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
V_E_SARI_shadow_intermed_1 <= V_E_SARI_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_E_SARI_intermed_1 <= RIN.E.SARI;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
V_X_DCI_SIGNED_shadow_intermed_1 <= V_X_DCI_SIGNED_shadow;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
V_X_DCI_SIZE_shadow_intermed_1 <= V_X_DCI_SIZE_shadow;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_3 <= V_M_RESULT1DOWNTO0_shadow_intermed_2;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_3 <= RIN_M_RESULT1DOWNTO0_intermed_2;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_X_LADDR_shadow_intermed_1 <= V_X_LADDR_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_X_CTRL_TRAP_shadow_intermed_1 <= V_X_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
V_X_MEXC_shadow_intermed_1 <= V_X_MEXC_shadow;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
DCO_MEXC_intermed_1 <= DCO.MEXC;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RPIN_PWD_intermed_1 <= RPIN.PWD;
V_X_DEBUG_shadow_intermed_1 <= V_X_DEBUG_shadow;
VP_PWD_shadow_intermed_1 <= VP_PWD_shadow;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_W_S_TBA_shadow_intermed_1 <= V_W_S_TBA_shadow;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
RIN_W_S_TBA_intermed_1 <= RIN.W.S.TBA;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
DSUIN_TT_intermed_1 <= DSUIN.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RPIN_PWD_intermed_1 <= RPIN.PWD;
IRIN_PWD_intermed_1 <= IRIN.PWD;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_W_S_TT_intermed_1 <= RIN.W.S.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD6DOWNTO0_shadow;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_W_S_CWP_shadow_intermed_1 <= V_W_S_CWP_shadow;
RIN_W_S_ET_intermed_1 <= RIN.W.S.ET;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_D_PC_intermed_6 <= RIN_D_PC_intermed_5;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
VIR_ADDR_shadow_intermed_1 <= VIR_ADDR_shadow;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
RIN_A_CTRL_PC_intermed_5 <= RIN_A_CTRL_PC_intermed_4;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_4 <= R_A_CTRL_PC_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
V_E_CTRL_PC_shadow_intermed_4 <= V_E_CTRL_PC_shadow_intermed_3;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_M_CTRL_PC_intermed_2 <= R_M_CTRL_PC_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC_intermed_1 <= R.X.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
R_E_CTRL_PC_intermed_3 <= R_E_CTRL_PC_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_3 <= RIN_M_CTRL_PC_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_X_CTRL_PC_shadow_intermed_2 <= V_X_CTRL_PC_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_M_CTRL_PC_shadow_intermed_3 <= V_M_CTRL_PC_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_5 <= V_A_CTRL_PC_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
R_D_PC_intermed_5 <= R_D_PC_intermed_4;
RIN_F_PC_intermed_1 <= RIN.F.PC;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_E_CTRL_PC_intermed_4 <= RIN_E_CTRL_PC_intermed_3;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
RIN_X_CTRL_PC_intermed_2 <= RIN_X_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
V_D_PC_shadow_intermed_6 <= V_D_PC_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
DSUIN_TBUFCNT_intermed_1 <= DSUIN.TBUFCNT;
RIN_W_EXCEPT_intermed_1 <= RIN.W.EXCEPT;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
RIN_W_RESULT_intermed_1 <= RIN.W.RESULT;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_W_WA_intermed_1 <= RIN.W.WA;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_W_WREG_intermed_1 <= RIN.W.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_W_S_SVT_intermed_1 <= RIN.W.S.SVT;
RIN_W_S_DWT_intermed_1 <= RIN.W.S.DWT;
RIN_W_S_EF_intermed_1 <= RIN.W.S.EF;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_E_CTRL_intermed_2 <= RIN_E_CTRL_intermed_1;
R_E_CTRL_intermed_1 <= R.E.CTRL;
RIN_X_CTRL_intermed_1 <= RIN.X.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
V_E_CTRL_shadow_intermed_2 <= V_E_CTRL_shadow_intermed_1;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
RIN_A_CTRL_intermed_3 <= RIN_A_CTRL_intermed_2;
V_M_CTRL_shadow_intermed_1 <= V_M_CTRL_shadow;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
V_A_CTRL_shadow_intermed_3 <= V_A_CTRL_shadow_intermed_2;
R_A_CTRL_intermed_1 <= R.A.CTRL;
R_A_CTRL_intermed_2 <= R_A_CTRL_intermed_1;
V_M_DCI_shadow_intermed_1 <= V_M_DCI_shadow;
RIN_M_DCI_intermed_1 <= RIN.M.DCI;
RIN_X_DCI_intermed_1 <= RIN.X.DCI;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_E_CTRL_RETT_shadow_intermed_2 <= V_E_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_3 <= V_A_CTRL_RETT_shadow_intermed_2;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
RIN_A_CTRL_RETT_intermed_3 <= RIN_A_CTRL_RETT_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_E_CTRL_RETT_intermed_1 <= R.E.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
RIN_E_CTRL_RETT_intermed_2 <= RIN_E_CTRL_RETT_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_X_CTRL_RETT_intermed_1 <= RIN.X.CTRL.RETT;
V_M_CTRL_RETT_shadow_intermed_1 <= V_M_CTRL_RETT_shadow;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
R_A_CTRL_RETT_intermed_2 <= R_A_CTRL_RETT_intermed_1;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
V_E_MAC_shadow_intermed_2 <= V_E_MAC_shadow_intermed_1;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
RIN_E_MAC_intermed_2 <= RIN_E_MAC_intermed_1;
R_E_MAC_intermed_1 <= R.E.MAC;
V_M_MAC_shadow_intermed_1 <= V_M_MAC_shadow;
RIN_X_MAC_intermed_1 <= RIN.X.MAC;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_X_CTRL_ANNUL_intermed_1 <= RIN.X.CTRL.ANNUL;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
RIN_X_SET_intermed_1 <= RIN.X.SET;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_X_ICC_intermed_1 <= RIN.X.ICC;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
R_A_CTRL_WICC_intermed_2 <= R_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_E_CTRL_WICC_shadow_intermed_2 <= V_E_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_3 <= V_A_CTRL_WICC_shadow_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_X_CTRL_WICC_intermed_1 <= RIN.X.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_E_CTRL_WICC_intermed_2 <= RIN_E_CTRL_WICC_intermed_1;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
R_E_CTRL_WICC_intermed_1 <= R.E.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_M_CTRL_WICC_shadow_intermed_1 <= V_M_CTRL_WICC_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_WICC_intermed_3 <= RIN_A_CTRL_WICC_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
R_A_CTRL_intermed_1 <= R.A.CTRL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
RIN_E_CWP_intermed_1 <= RIN.E.CWP;
V_A_CWP_shadow_intermed_1 <= V_A_CWP_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_D_CWP_intermed_2 <= RIN_D_CWP_intermed_1;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
V_D_CWP_shadow_intermed_2 <= V_D_CWP_shadow_intermed_1;
R_D_CWP_intermed_1 <= R.D.CWP;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_M_MUL_intermed_1 <= RIN.M.MUL;
RIN_M_NALIGN_intermed_1 <= RIN.M.NALIGN;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
R_A_CTRL_LD_intermed_2 <= R_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_3 <= RIN_A_CTRL_LD_intermed_2;
V_E_CTRL_LD_shadow_intermed_1 <= V_E_CTRL_LD_shadow;
V_E_CTRL_LD_shadow_intermed_2 <= V_E_CTRL_LD_shadow_intermed_1;
R_E_CTRL_LD_intermed_1 <= R.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_2 <= RIN_E_CTRL_LD_intermed_1;
RIN_M_CTRL_LD_intermed_1 <= RIN.M.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
V_A_CTRL_LD_shadow_intermed_3 <= V_A_CTRL_LD_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
RIN_E_JMPL_intermed_1 <= RIN.E.JMPL;
RIN_A_JMPL_intermed_1 <= RIN.A.JMPL;
V_A_JMPL_shadow_intermed_1 <= V_A_JMPL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_A_SU_intermed_1 <= RIN.A.SU;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_ET_intermed_1 <= RIN.E.ET;
RIN_A_ET_intermed_1 <= RIN.A.ET;
V_A_ET_shadow_intermed_1 <= V_A_ET_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
V_A_RFA1_shadow_intermed_1 <= V_A_RFA1_shadow;
DBGI_DADDR9DOWNTO2_intermed_1 <= DBGI.DADDR ( 9 DOWNTO 2 );
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
RIN_A_RFA2_intermed_1 <= RIN.A.RFA2;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WY_intermed_1 <= RIN.A.CTRL.WY;
ICO_MEXC_intermed_1 <= ICO.MEXC;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
R_D_ANNUL_intermed_1 <= R.D.ANNUL;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
V_D_ANNUL_shadow_intermed_2 <= V_D_ANNUL_shadow_intermed_1;
DBGI_STEP_intermed_1 <= DBGI.STEP;
V_D_STEP_shadow_intermed_1 <= V_D_STEP_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_ANNUL_intermed_2 <= RIN_D_ANNUL_intermed_1;
RIN_A_STEP_intermed_1 <= RIN.A.STEP;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
RIN_F_BRANCH_intermed_1 <= RIN.F.BRANCH;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
R_D_INST0_intermed_1 <= R.D.INST( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
RIN_D_SET_intermed_1 <= RIN.D.SET;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
R_E_CTRL_INST_intermed_2 <= R_E_CTRL_INST_intermed_1;
R_M_CTRL_INST_intermed_1 <= R.M.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
DE_INST_shadow_intermed_4 <= DE_INST_shadow_intermed_3;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_4 <= V_A_CTRL_INST_shadow_intermed_3;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
V_E_CTRL_INST_shadow_intermed_3 <= V_E_CTRL_INST_shadow_intermed_2;
RIN_X_CTRL_INST_intermed_1 <= RIN.X.CTRL.INST;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_A_CTRL_INST_intermed_4 <= RIN_A_CTRL_INST_intermed_3;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_M_CTRL_INST_intermed_2 <= RIN_M_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_3 <= RIN_E_CTRL_INST_intermed_2;
V_M_CTRL_INST_shadow_intermed_1 <= V_M_CTRL_INST_shadow;
V_M_CTRL_INST_shadow_intermed_2 <= V_M_CTRL_INST_shadow_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_3 <= R_A_CTRL_INST_intermed_2;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_CNT_shadow_intermed_3 <= V_E_CTRL_CNT_shadow_intermed_2;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
RIN_D_CNT_intermed_5 <= RIN_D_CNT_intermed_4;
R_M_CTRL_CNT_intermed_1 <= R.M.CTRL.CNT;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
V_A_CTRL_CNT_shadow_intermed_4 <= V_A_CTRL_CNT_shadow_intermed_3;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
R_A_CTRL_CNT_intermed_3 <= R_A_CTRL_CNT_intermed_2;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
V_D_CNT_shadow_intermed_5 <= V_D_CNT_shadow_intermed_4;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_D_CNT_intermed_4 <= R_D_CNT_intermed_3;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
R_E_CTRL_CNT_intermed_2 <= R_E_CTRL_CNT_intermed_1;
RIN_X_CTRL_CNT_intermed_1 <= RIN.X.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_A_CTRL_CNT_intermed_4 <= RIN_A_CTRL_CNT_intermed_3;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_M_CTRL_CNT_intermed_2 <= RIN_M_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_3 <= RIN_E_CTRL_CNT_intermed_2;
V_M_CTRL_CNT_shadow_intermed_1 <= V_M_CTRL_CNT_shadow;
V_M_CTRL_CNT_shadow_intermed_2 <= V_M_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_3 <= V_E_CTRL_PV_shadow_intermed_2;
R_M_CTRL_PV_intermed_1 <= R.M.CTRL.PV;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_E_CTRL_PV_intermed_2 <= R_E_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_3 <= R_A_CTRL_PV_intermed_2;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_3 <= RIN_E_CTRL_PV_intermed_2;
RIN_X_CTRL_PV_intermed_1 <= RIN.X.CTRL.PV;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
RIN_M_CTRL_PV_intermed_2 <= RIN_M_CTRL_PV_intermed_1;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
V_A_CTRL_PV_shadow_intermed_4 <= V_A_CTRL_PV_shadow_intermed_3;
V_M_CTRL_PV_shadow_intermed_1 <= V_M_CTRL_PV_shadow;
V_M_CTRL_PV_shadow_intermed_2 <= V_M_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
RIN_A_CTRL_PV_intermed_4 <= RIN_A_CTRL_PV_intermed_3;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (RP.ERROR /= '1') else '0';
dfp_trap_vector(1) <= '1' when (RP.ERROR /= '0') else '0';
dfp_trap_vector(2) <= '1' when (RP.ERROR /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(3) <= '1' when (RP.ERROR /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(4) <= '1' when (R.W.S.S /= V_W_S_S_shadow_intermed_1) else '0';
dfp_trap_vector(5) <= '1' when (R.W.S.S /= '1') else '0';
dfp_trap_vector(6) <= '1' when (R.W.S.S /= RIN_W_S_S_intermed_1) else '0';
dfp_trap_vector(7) <= '1' when (R.W.S.PS /= V_W_S_S_shadow_intermed_2) else '0';
dfp_trap_vector(8) <= '1' when (R.W.S.PS /= V_W_S_PS_shadow_intermed_1) else '0';
dfp_trap_vector(9) <= '1' when (R.W.S.PS /= '1') else '0';
dfp_trap_vector(10) <= '1' when (R.W.S.PS /= RIN_W_S_PS_intermed_1) else '0';
dfp_trap_vector(11) <= '1' when (R.W.S.PS /= R_W_S_S_intermed_1) else '0';
dfp_trap_vector(12) <= '1' when (R.W.S.PS /= RIN_W_S_S_intermed_2) else '0';
dfp_trap_vector(13) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 ) /= R_X_RESULT6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(14) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(15) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(16) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(17) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(18) <= '1' when (R.X.DATA ( 0 ) /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(19) <= '1' when (R.X.DATA ( 0 ) /= R_X_DATA0_intermed_2) else '0';
dfp_trap_vector(20) <= '1' when (R.X.DATA ( 0 ) /= DCO_DATA0_intermed_1) else '0';
dfp_trap_vector(21) <= '1' when (R.X.DATA ( 0 ) /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(22) <= '1' when (R.X.DATA ( 0 ) /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(23) <= '1' when (R.X.DATA ( 0 ) /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(24) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(25) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(26) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(27) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(28) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(29) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(30) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(31) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(32) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(33) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(34) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(35) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(36) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(37) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(38) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(39) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_X_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(40) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(41) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(42) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(43) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(44) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(45) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(46) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(47) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(48) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(49) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(50) <= '1' when (RFI.WREN /= DCO.SCANEN) else '0';
dfp_trap_vector(51) <= '1' when (RFI.WREN /= V_X_ANNUL_ALL_shadow_intermed_4) else '0';
dfp_trap_vector(52) <= '1' when (RFI.WREN /= RIN_A_CTRL_ANNUL_intermed_5) else '0';
dfp_trap_vector(53) <= '1' when (RFI.WREN /= R_M_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(54) <= '1' when (RFI.WREN /= R.X.CTRL.WREG) else '0';
dfp_trap_vector(55) <= '1' when (RFI.WREN /= R_A_CTRL_ANNUL_intermed_4) else '0';
dfp_trap_vector(56) <= '1' when (RFI.WREN /= RIN_X_ANNUL_ALL_intermed_5) else '0';
dfp_trap_vector(57) <= '1' when (RFI.WREN /= V_M_CTRL_WREG_shadow_intermed_2) else '0';
dfp_trap_vector(58) <= '1' when (RFI.WREN /= R_X_ANNUL_ALL_intermed_4) else '0';
dfp_trap_vector(59) <= '1' when (RFI.WREN /= HOLDN) else '0';
dfp_trap_vector(60) <= '1' when (RFI.WREN /= V_X_CTRL_WREG_shadow_intermed_1) else '0';
dfp_trap_vector(61) <= '1' when (RFI.WREN /= R_E_CTRL_WREG_intermed_2) else '0';
dfp_trap_vector(62) <= '1' when (RFI.WREN /= RIN_X_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(63) <= '1' when (RFI.WREN /= '1') else '0';
dfp_trap_vector(64) <= '1' when (RFI.WREN /= '0') else '0';
dfp_trap_vector(65) <= '1' when (RFI.WREN /= XC_WREG_shadow) else '0';
dfp_trap_vector(66) <= '1' when (RFI.WREN /= V_A_CTRL_ANNUL_shadow_intermed_4) else '0';
dfp_trap_vector(67) <= '1' when (RFI.WREN /= RIN_E_CTRL_WREG_intermed_3) else '0';
dfp_trap_vector(68) <= '1' when (RFI.WREN /= RIN_M_CTRL_WREG_intermed_2) else '0';
dfp_trap_vector(69) <= '1' when (RFI.WREN /= V_E_CTRL_WREG_shadow_intermed_3) else '0';
dfp_trap_vector(70) <= '1' when (RFI.WREN /= RIN_A_CTRL_WREG_intermed_4) else '0';
dfp_trap_vector(71) <= '1' when (RFI.WREN /= V_A_CTRL_WREG_shadow_intermed_4) else '0';
dfp_trap_vector(72) <= '1' when (RFI.WREN /= R_A_CTRL_WREG_intermed_3) else '0';
dfp_trap_vector(73) <= '1' when (IRQO.INTACK /= RIN_X_INTACK_intermed_1) else '0';
dfp_trap_vector(74) <= '1' when (IRQO.INTACK /= V_X_INTACK_shadow_intermed_1) else '0';
dfp_trap_vector(75) <= '1' when (IRQO.INTACK /= HOLDN) else '0';
dfp_trap_vector(76) <= '1' when (IRQO.INTACK /= R.X.INTACK) else '0';
dfp_trap_vector(77) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_X_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(78) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_M_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(79) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(80) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(81) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_3) else '0';
dfp_trap_vector(82) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_A_CTRL_TT3DOWNTO0_intermed_5) else '0';
dfp_trap_vector(83) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_A_CTRL_TT3DOWNTO0_intermed_6) else '0';
dfp_trap_vector(84) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4) else '0';
dfp_trap_vector(85) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_6) else '0';
dfp_trap_vector(86) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3) else '0';
dfp_trap_vector(87) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_W_S_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(88) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(89) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_E_CTRL_TT3DOWNTO0_intermed_4) else '0';
dfp_trap_vector(90) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(91) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_W_S_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(92) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_5) else '0';
dfp_trap_vector(93) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_W_S_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(94) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_M_CTRL_TT3DOWNTO0_intermed_4) else '0';
dfp_trap_vector(95) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(96) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(97) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_X_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(98) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_E_CTRL_TT3DOWNTO0_intermed_5) else '0';
dfp_trap_vector(99) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(100) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= XC_VECTT3DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(101) <= '1' when (DCI.INTACK /= RIN_X_INTACK_intermed_1) else '0';
dfp_trap_vector(102) <= '1' when (DCI.INTACK /= V_X_INTACK_shadow_intermed_1) else '0';
dfp_trap_vector(103) <= '1' when (DCI.INTACK /= HOLDN) else '0';
dfp_trap_vector(104) <= '1' when (DCI.INTACK /= R.X.INTACK) else '0';
dfp_trap_vector(105) <= '1' when (R.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(106) <= '1' when (R.M.RESULT ( 1 DOWNTO 0 ) /= RIN_M_RESULT1DOWNTO0_intermed_1) else '0';
dfp_trap_vector(107) <= '1' when (R.M.RESULT ( 1 DOWNTO 0 ) /= RIN_M_RESULT1DOWNTO0_intermed_2) else '0';
dfp_trap_vector(108) <= '1' when (R.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(109) <= '1' when (R.M.RESULT ( 1 DOWNTO 0 ) /= R_M_RESULT1DOWNTO0_intermed_2) else '0';
dfp_trap_vector(110) <= '1' when (DCI.LOCK /= V_X_ANNUL_ALL_shadow_intermed_1) else '0';
dfp_trap_vector(111) <= '1' when (DCI.LOCK /= RIN_A_CTRL_ANNUL_intermed_3) else '0';
dfp_trap_vector(112) <= '1' when (DCI.LOCK /= RIN_E_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(113) <= '1' when (DCI.LOCK /= R_A_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(114) <= '1' when (DCI.LOCK /= V_M_CTRL_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(115) <= '1' when (DCI.LOCK /= RIN_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(116) <= '1' when (DCI.LOCK /= R_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(117) <= '1' when (DCI.LOCK /= R.M.CTRL.ANNUL) else '0';
dfp_trap_vector(118) <= '1' when (DCI.LOCK /= RIN_M_DCI_LOCK_intermed_1) else '0';
dfp_trap_vector(119) <= '1' when (DCI.LOCK /= '1') else '0';
dfp_trap_vector(120) <= '1' when (DCI.LOCK /= V_E_CTRL_ANNUL_shadow_intermed_2) else '0';
dfp_trap_vector(121) <= '1' when (DCI.LOCK /= '0') else '0';
dfp_trap_vector(122) <= '1' when (DCI.LOCK /= V_A_CTRL_ANNUL_shadow_intermed_3) else '0';
dfp_trap_vector(123) <= '1' when (DCI.LOCK /= RIN_M_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(124) <= '1' when (DCI.LOCK /= R.M.DCI.LOCK) else '0';
dfp_trap_vector(125) <= '1' when (DCI.LOCK /= R_E_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(126) <= '1' when (DCI.LOCK /= V_M_DCI_LOCK_shadow_intermed_1) else '0';
dfp_trap_vector(127) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(128) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(129) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(130) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(131) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(132) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= DCO_DATA031_intermed_2) else '0';
dfp_trap_vector(133) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= R_X_DATA031_intermed_2) else '0';
dfp_trap_vector(134) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= R_X_DATA031_intermed_2) else '0';
dfp_trap_vector(135) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(136) <= '1' when (R.E.CTRL.INST ( 19 ) /= DE_INST19_shadow_intermed_3) else '0';
dfp_trap_vector(137) <= '1' when (R.E.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_3) else '0';
dfp_trap_vector(138) <= '1' when (R.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(139) <= '1' when (R.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(140) <= '1' when (R.E.CTRL.INST ( 19 ) /= R_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(141) <= '1' when (R.E.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(142) <= '1' when (R.E.CTRL.INST ( 19 ) /= R_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(143) <= '1' when (R.E.CTRL.INST ( 19 ) /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(144) <= '1' when (R.E.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_3) else '0';
dfp_trap_vector(145) <= '1' when (R.E.CTRL.INST ( 19 ) /= RIN_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(146) <= '1' when (R.E.CTRL.INST ( 19 ) /= RIN_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(147) <= '1' when (R.E.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(148) <= '1' when (R.E.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(149) <= '1' when (R.E.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(150) <= '1' when (R.E.CTRL.INST ( 20 ) /= RIN_E_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(151) <= '1' when (R.E.CTRL.INST ( 20 ) /= R_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(152) <= '1' when (R.E.CTRL.INST ( 20 ) /= R_E_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(153) <= '1' when (R.E.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_3) else '0';
dfp_trap_vector(154) <= '1' when (R.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(155) <= '1' when (R.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow_intermed_1) else '0';
dfp_trap_vector(156) <= '1' when (R.E.CTRL.INST ( 20 ) /= DE_INST20_shadow_intermed_3) else '0';
dfp_trap_vector(157) <= '1' when (R.E.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_3) else '0';
dfp_trap_vector(158) <= '1' when (R.E.CTRL.INST ( 20 ) /= RIN_E_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(159) <= '1' when (R.E.CTRL.INST ( 20 ) /= R_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(160) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= RIN_X_DATA00_intermed_2) else '0';
dfp_trap_vector(161) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow_intermed_1) else '0';
dfp_trap_vector(162) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= DCO_DATA00_intermed_2) else '0';
dfp_trap_vector(163) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow_intermed_2) else '0';
dfp_trap_vector(164) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= RIN_X_DATA00_intermed_1) else '0';
dfp_trap_vector(165) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow_intermed_2) else '0';
dfp_trap_vector(166) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= R_X_DATA00_intermed_2) else '0';
dfp_trap_vector(167) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= RIN_X_DATA00_intermed_2) else '0';
dfp_trap_vector(168) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= R_X_DATA00_intermed_2) else '0';
dfp_trap_vector(169) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(170) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(171) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(172) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(173) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(174) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= DCO_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(175) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(176) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(177) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(178) <= '1' when (RFI.REN1 /= DCO.SCANEN) else '0';
dfp_trap_vector(179) <= '1' when (RFI.REN1 /= RIN_A_RFE1_intermed_1) else '0';
dfp_trap_vector(180) <= '1' when (RFI.REN1 /= DE_REN1_shadow) else '0';
dfp_trap_vector(181) <= '1' when (RFI.REN1 /= V_A_RFE1_shadow_intermed_1) else '0';
dfp_trap_vector(182) <= '1' when (RFI.REN1 /= R.A.RFE1) else '0';
dfp_trap_vector(183) <= '1' when (RFI.REN1 /= '1') else '0';
dfp_trap_vector(184) <= '1' when (RFI.REN2 /= DCO.SCANEN) else '0';
dfp_trap_vector(185) <= '1' when (RFI.REN2 /= RIN_A_RFE2_intermed_1) else '0';
dfp_trap_vector(186) <= '1' when (RFI.REN2 /= V_A_RFE2_shadow_intermed_1) else '0';
dfp_trap_vector(187) <= '1' when (RFI.REN2 /= DE_REN2_shadow) else '0';
dfp_trap_vector(188) <= '1' when (RFI.REN2 /= R.A.RFE2) else '0';
dfp_trap_vector(189) <= '1' when (RFI.DIAG(0) /= DCO.TESTEN) else '0';
dfp_trap_vector(190) <= '1' when (RFI.DIAG /= "0000") else '0';
dfp_trap_vector(191) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(192) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(193) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(194) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_7) else '0';
dfp_trap_vector(195) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(196) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(197) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_X_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(198) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_8) else '0';
dfp_trap_vector(199) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(200) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_8) else '0';
dfp_trap_vector(201) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2) else '0';
dfp_trap_vector(202) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(203) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(204) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_F_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(205) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_X_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(206) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= IRIN_ADDR31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(207) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(208) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(209) <= '1' when (R.F.PC ( 2 DOWNTO 2 ) /= "1") else '0';
dfp_trap_vector(210) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(211) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_7) else '0';
dfp_trap_vector(212) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(213) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= IR_ADDR31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(214) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(215) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_F_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(216) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(217) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= VIR_ADDR31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(218) <= '1' when (ICI.DPC(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(219) <= '1' when (ICI.DPC(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(220) <= '1' when (ICI.DPC /= x"00000000") else '0';
dfp_trap_vector(221) <= '1' when (ICI.DPC(31 downto 2) /= R.D.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(222) <= '1' when (ICI.DPC(31 downto 2) /= R_D_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(223) <= '1' when (ICI.DPC(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(224) <= '1' when (ICI.DPC(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(225) <= '1' when (R.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(226) <= '1' when (R.D.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(227) <= '1' when (R.D.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(228) <= '1' when (R.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(229) <= '1' when (R.D.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(230) <= '1' when (ICI.FPC(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(231) <= '1' when (ICI.FPC(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(232) <= '1' when (ICI.FPC(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(233) <= '1' when (ICI.FPC(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(234) <= '1' when (ICI.FPC(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(235) <= '1' when (ICI.FPC(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(236) <= '1' when (ICI.FPC(31 downto 2) /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(237) <= '1' when (ICI.FPC(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(238) <= '1' when (ICI.FPC(31 downto 2) /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(239) <= '1' when (ICI.FPC(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_7) else '0';
dfp_trap_vector(240) <= '1' when (ICI.FPC(31 downto 2) /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2) else '0';
dfp_trap_vector(241) <= '1' when (ICI.FPC(31 downto 2) /= V_F_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(242) <= '1' when (ICI.FPC(31 downto 2) /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(243) <= '1' when (ICI.FPC(31 downto 2) /= RIN_F_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(244) <= '1' when (ICI.FPC(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(245) <= '1' when (ICI.FPC /= X"00000000") else '0';
dfp_trap_vector(246) <= '1' when (ICI.FPC(31 downto 2) /= IRIN_ADDR31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(247) <= '1' when (ICI.FPC(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(248) <= '1' when (ICI.FPC(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(249) <= '1' when (ICI.FPC(0) /= '1') else '0';
dfp_trap_vector(250) <= '1' when (ICI.FPC(31 downto 2) /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(251) <= '1' when (ICI.FPC(31 downto 2) /= R_D_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(252) <= '1' when (ICI.FPC(31 downto 2) /= R.F.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(253) <= '1' when (ICI.FPC(31 downto 2) /= RIN_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(254) <= '1' when (ICI.FPC(31 downto 2) /= IR_ADDR31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(255) <= '1' when (ICI.FPC(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(256) <= '1' when (ICI.FPC(31 downto 2) /= R_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(257) <= '1' when (ICI.FPC(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(258) <= '1' when (ICI.FPC(31 downto 2) /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(259) <= '1' when (ICI.RPC(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(260) <= '1' when (ICI.RPC(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(261) <= '1' when (ICI.RPC(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(262) <= '1' when (ICI.RPC(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(263) <= '1' when (ICI.RPC(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(264) <= '1' when (ICI.RPC(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(265) <= '1' when (ICI.RPC(31 downto 2) /= NPC31DOWNTO2_shadow) else '0';
dfp_trap_vector(266) <= '1' when (ICI.RPC(31 downto 2) /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(267) <= '1' when (ICI.RPC(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(268) <= '1' when (ICI.RPC(31 downto 2) /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(269) <= '1' when (ICI.RPC(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_7) else '0';
dfp_trap_vector(270) <= '1' when (ICI.RPC(31 downto 2) /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(271) <= '1' when (ICI.RPC(31 downto 2) /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(272) <= '1' when (ICI.RPC(31 downto 2) /= RIN_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(273) <= '1' when (ICI.RPC(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(274) <= '1' when (ICI.RPC /= X"00000000") else '0';
dfp_trap_vector(275) <= '1' when (ICI.RPC(31 downto 2) /= IRIN_ADDR31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(276) <= '1' when (ICI.RPC(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(277) <= '1' when (ICI.RPC(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(278) <= '1' when (ICI.RPC(31 downto 2) /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(279) <= '1' when (ICI.RPC(31 downto 2) /= R_D_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(280) <= '1' when (ICI.RPC(31 downto 2) /= IR_ADDR31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(281) <= '1' when (ICI.RPC(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(282) <= '1' when (ICI.RPC(31 downto 2) /= R.F.PC( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(283) <= '1' when (ICI.RPC(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(284) <= '1' when (ICI.RPC(31 downto 2) /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(285) <= '1' when (ICI.FLUSHL /= '0') else '0';
dfp_trap_vector(286) <= '1' when (MULI.START /= R.A.MULSTART) else '0';
dfp_trap_vector(287) <= '1' when (MULI.START /= V_X_ANNUL_ALL_shadow_intermed_1) else '0';
dfp_trap_vector(288) <= '1' when (MULI.START /= RIN_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(289) <= '1' when (MULI.START /= R.A.CTRL.ANNUL) else '0';
dfp_trap_vector(290) <= '1' when (MULI.START /= V_A_MULSTART_shadow_intermed_1) else '0';
dfp_trap_vector(291) <= '1' when (MULI.START /= RIN_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(292) <= '1' when (MULI.START /= R_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(293) <= '1' when (MULI.START /= RIN_A_MULSTART_intermed_1) else '0';
dfp_trap_vector(294) <= '1' when (MULI.START /= '1') else '0';
dfp_trap_vector(295) <= '1' when (MULI.START /= '0') else '0';
dfp_trap_vector(296) <= '1' when (MULI.START /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(297) <= '1' when (MULI.OP1(31) /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(298) <= '1' when (MULI.OP1(31 downto 0) /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(299) <= '1' when (MULI.OP1(19) /= DE_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(300) <= '1' when (MULI.OP1(31) /= RIN_E_OP131_intermed_1) else '0';
dfp_trap_vector(301) <= '1' when (MULI.OP1(19) /= V_A_CTRL_INST19_shadow_intermed_3) else '0';
dfp_trap_vector(302) <= '1' when (MULI.OP1(31 downto 0) /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(303) <= '1' when (MULI.OP1(31) /= V_E_OP131_shadow_intermed_1) else '0';
dfp_trap_vector(304) <= '1' when (MULI.OP1(31) /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(305) <= '1' when (MULI.OP1(31) /= R.E.OP1( 31 )) else '0';
dfp_trap_vector(306) <= '1' when (MULI.OP1(19) /= V_E_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(307) <= '1' when (MULI.OP1(31 downto 0) /= V_E_OP1_shadow_intermed_1) else '0';
dfp_trap_vector(308) <= '1' when (MULI.OP1(31) /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(309) <= '1' when (MULI.OP1(19) /= V_E_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(310) <= '1' when (MULI.OP1(31) /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(311) <= '1' when (MULI.OP1(31 downto 0) /= RIN_E_OP1_intermed_1) else '0';
dfp_trap_vector(312) <= '1' when (MULI.OP1(19) /= R_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(313) <= '1' when (MULI.OP1(31 downto 0) /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(314) <= '1' when (MULI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(315) <= '1' when (MULI.OP1(31) /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(316) <= '1' when (MULI.OP1(31) /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(317) <= '1' when (MULI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(318) <= '1' when (MULI.OP1(19) /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(319) <= '1' when (MULI.OP1(31 downto 0) /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(320) <= '1' when (MULI.OP1(31 downto 0) /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(321) <= '1' when (MULI.OP1(19) /= R_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(322) <= '1' when (MULI.OP1(19) /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(323) <= '1' when (MULI.OP1(19) /= RIN_A_CTRL_INST19_intermed_3) else '0';
dfp_trap_vector(324) <= '1' when (MULI.OP1(19) /= RIN_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(325) <= '1' when (MULI.OP1(19) /= R.E.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(326) <= '1' when (MULI.OP1(31) /= R.X.DATA ( 0 )( 31 )) else '0';
dfp_trap_vector(327) <= '1' when (MULI.OP1(31 downto 0) /= DCO_DATA0_intermed_1) else '0';
dfp_trap_vector(328) <= '1' when (MULI.OP1(31 downto 0) /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(329) <= '1' when (MULI.OP1(19) /= RIN_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(330) <= '1' when (MULI.OP1(31 downto 0) /= R.E.OP1) else '0';
dfp_trap_vector(331) <= '1' when (MULI.OP1(19) /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(332) <= '1' when (MULI.OP2(31) /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(333) <= '1' when (MULI.OP2(31 downto 0) /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(334) <= '1' when (MULI.OP2(19) /= DE_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(335) <= '1' when (MULI.OP2(31 downto 0) /= MUL_OP2_shadow) else '0';
dfp_trap_vector(336) <= '1' when (MULI.OP2(19) /= V_A_CTRL_INST19_shadow_intermed_3) else '0';
dfp_trap_vector(337) <= '1' when (MULI.OP2(31 downto 0) /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(338) <= '1' when (MULI.OP2(31) /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(339) <= '1' when (MULI.OP2(19) /= V_E_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(340) <= '1' when (MULI.OP2(31) /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(341) <= '1' when (MULI.OP2(31 downto 0) /= V_E_OP2_shadow_intermed_1) else '0';
dfp_trap_vector(342) <= '1' when (MULI.OP2(31 downto 0) /= RIN_E_OP2_intermed_1) else '0';
dfp_trap_vector(343) <= '1' when (MULI.OP2(19) /= V_E_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(344) <= '1' when (MULI.OP2(31) /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(345) <= '1' when (MULI.OP2(31) /= EX_OP231_shadow) else '0';
dfp_trap_vector(346) <= '1' when (MULI.OP2(19) /= R_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(347) <= '1' when (MULI.OP2(31 downto 0) /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(348) <= '1' when (MULI.OP2(31 downto 0) /= EX_OP2_shadow) else '0';
dfp_trap_vector(349) <= '1' when (MULI.OP2(31) /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(350) <= '1' when (MULI.OP2(31) /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(351) <= '1' when (MULI.OP2(19) /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(352) <= '1' when (MULI.OP2(31 downto 0) /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(353) <= '1' when (MULI.OP2(31 downto 0) /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(354) <= '1' when (MULI.OP2(19) /= R_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(355) <= '1' when (MULI.OP2(31) /= RIN_E_OP231_intermed_1) else '0';
dfp_trap_vector(356) <= '1' when (MULI.OP2(31) /= R.E.OP2( 31 )) else '0';
dfp_trap_vector(357) <= '1' when (MULI.OP2(31) /= MUL_OP231_shadow) else '0';
dfp_trap_vector(358) <= '1' when (MULI.OP2(19) /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(359) <= '1' when (MULI.OP2(19) /= RIN_A_CTRL_INST19_intermed_3) else '0';
dfp_trap_vector(360) <= '1' when (MULI.OP2(19) /= RIN_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(361) <= '1' when (MULI.OP2(31 downto 0) /= R.E.OP2) else '0';
dfp_trap_vector(362) <= '1' when (MULI.OP2(19) /= R.E.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(363) <= '1' when (MULI.OP2(31) /= V_E_OP231_shadow_intermed_1) else '0';
dfp_trap_vector(364) <= '1' when (MULI.OP2(31) /= R.X.DATA ( 0 )( 31 )) else '0';
dfp_trap_vector(365) <= '1' when (MULI.OP2(31 downto 0) /= DCO_DATA0_intermed_1) else '0';
dfp_trap_vector(366) <= '1' when (MULI.OP2(31 downto 0) /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(367) <= '1' when (MULI.OP2(19) /= RIN_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(368) <= '1' when (MULI.OP2(19) /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(369) <= '1' when (R.E.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_3) else '0';
dfp_trap_vector(370) <= '1' when (R.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(371) <= '1' when (R.E.CTRL.INST ( 24 ) /= DE_INST24_shadow_intermed_3) else '0';
dfp_trap_vector(372) <= '1' when (R.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow_intermed_1) else '0';
dfp_trap_vector(373) <= '1' when (R.E.CTRL.INST ( 24 ) /= R_A_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(374) <= '1' when (R.E.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(375) <= '1' when (R.E.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(376) <= '1' when (R.E.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_3) else '0';
dfp_trap_vector(377) <= '1' when (R.E.CTRL.INST ( 24 ) /= RIN_E_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(378) <= '1' when (R.E.CTRL.INST ( 24 ) /= R_E_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(379) <= '1' when (R.E.CTRL.INST ( 24 ) /= R_A_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(380) <= '1' when (R.E.CTRL.INST ( 24 ) /= RIN_E_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(381) <= '1' when (DIVI.START /= R.A.DIVSTART) else '0';
dfp_trap_vector(382) <= '1' when (DIVI.START /= V_X_ANNUL_ALL_shadow_intermed_1) else '0';
dfp_trap_vector(383) <= '1' when (DIVI.START /= RIN_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(384) <= '1' when (DIVI.START /= R.A.CTRL.ANNUL) else '0';
dfp_trap_vector(385) <= '1' when (DIVI.START /= RIN_A_DIVSTART_intermed_1) else '0';
dfp_trap_vector(386) <= '1' when (DIVI.START /= RIN_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(387) <= '1' when (DIVI.START /= R_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(388) <= '1' when (DIVI.START /= V_A_DIVSTART_shadow_intermed_1) else '0';
dfp_trap_vector(389) <= '1' when (DIVI.START /= '1') else '0';
dfp_trap_vector(390) <= '1' when (DIVI.START /= '0') else '0';
dfp_trap_vector(391) <= '1' when (DIVI.START /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(392) <= '1' when (DIVI.OP1(31) /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(393) <= '1' when (DIVI.OP1(31 downto 0) /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(394) <= '1' when (DIVI.OP1(19) /= DE_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(395) <= '1' when (DIVI.OP1(31) /= RIN_E_OP131_intermed_1) else '0';
dfp_trap_vector(396) <= '1' when (DIVI.OP1(19) /= V_A_CTRL_INST19_shadow_intermed_3) else '0';
dfp_trap_vector(397) <= '1' when (DIVI.OP1(31 downto 0) /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(398) <= '1' when (DIVI.OP1(31) /= V_E_OP131_shadow_intermed_1) else '0';
dfp_trap_vector(399) <= '1' when (DIVI.OP1(31) /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(400) <= '1' when (DIVI.OP1(31) /= R.E.OP1( 31 )) else '0';
dfp_trap_vector(401) <= '1' when (DIVI.OP1(19) /= V_E_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(402) <= '1' when (DIVI.OP1(31 downto 0) /= V_E_OP1_shadow_intermed_1) else '0';
dfp_trap_vector(403) <= '1' when (DIVI.OP1(31) /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(404) <= '1' when (DIVI.OP1(19) /= V_E_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(405) <= '1' when (DIVI.OP1(31) /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(406) <= '1' when (DIVI.OP1(31 downto 0) /= RIN_E_OP1_intermed_1) else '0';
dfp_trap_vector(407) <= '1' when (DIVI.OP1(19) /= R_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(408) <= '1' when (DIVI.OP1(31 downto 0) /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(409) <= '1' when (DIVI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(410) <= '1' when (DIVI.OP1(31) /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(411) <= '1' when (DIVI.OP1(31) /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(412) <= '1' when (DIVI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(413) <= '1' when (DIVI.OP1(19) /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(414) <= '1' when (DIVI.OP1(31 downto 0) /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(415) <= '1' when (DIVI.OP1(31 downto 0) /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(416) <= '1' when (DIVI.OP1(19) /= R_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(417) <= '1' when (DIVI.OP1(19) /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(418) <= '1' when (DIVI.OP1(19) /= RIN_A_CTRL_INST19_intermed_3) else '0';
dfp_trap_vector(419) <= '1' when (DIVI.OP1(19) /= RIN_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(420) <= '1' when (DIVI.OP1(19) /= R.E.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(421) <= '1' when (DIVI.OP1(31) /= R.X.DATA ( 0 )( 31 )) else '0';
dfp_trap_vector(422) <= '1' when (DIVI.OP1(31 downto 0) /= DCO_DATA0_intermed_1) else '0';
dfp_trap_vector(423) <= '1' when (DIVI.OP1(31 downto 0) /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(424) <= '1' when (DIVI.OP1(19) /= RIN_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(425) <= '1' when (DIVI.OP1(31 downto 0) /= R.E.OP1) else '0';
dfp_trap_vector(426) <= '1' when (DIVI.OP1(19) /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(427) <= '1' when (DIVI.OP2(31) /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(428) <= '1' when (DIVI.OP2(31 downto 0) /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(429) <= '1' when (DIVI.OP2(19) /= DE_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(430) <= '1' when (DIVI.OP2(19) /= V_A_CTRL_INST19_shadow_intermed_3) else '0';
dfp_trap_vector(431) <= '1' when (DIVI.OP2(31 downto 0) /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(432) <= '1' when (DIVI.OP2(31) /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(433) <= '1' when (DIVI.OP2(31) /= EX_OP231_shadow) else '0';
dfp_trap_vector(434) <= '1' when (DIVI.OP2(19) /= V_E_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(435) <= '1' when (DIVI.OP2(31) /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(436) <= '1' when (DIVI.OP2(31 downto 0) /= V_E_OP2_shadow_intermed_1) else '0';
dfp_trap_vector(437) <= '1' when (DIVI.OP2(31 downto 0) /= RIN_E_OP2_intermed_1) else '0';
dfp_trap_vector(438) <= '1' when (DIVI.OP2(19) /= V_E_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(439) <= '1' when (DIVI.OP2(31) /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(440) <= '1' when (DIVI.OP2(19) /= R_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(441) <= '1' when (DIVI.OP2(31 downto 0) /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(442) <= '1' when (DIVI.OP2(31 downto 0) /= EX_OP2_shadow) else '0';
dfp_trap_vector(443) <= '1' when (DIVI.OP2(31) /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(444) <= '1' when (DIVI.OP2(31) /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(445) <= '1' when (DIVI.OP2(19) /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(446) <= '1' when (DIVI.OP2(31 downto 0) /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(447) <= '1' when (DIVI.OP2(31 downto 0) /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(448) <= '1' when (DIVI.OP2(19) /= R_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(449) <= '1' when (DIVI.OP2(31) /= RIN_E_OP231_intermed_1) else '0';
dfp_trap_vector(450) <= '1' when (DIVI.OP2(31) /= R.E.OP2( 31 )) else '0';
dfp_trap_vector(451) <= '1' when (DIVI.OP2(19) /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(452) <= '1' when (DIVI.OP2(19) /= RIN_A_CTRL_INST19_intermed_3) else '0';
dfp_trap_vector(453) <= '1' when (DIVI.OP2(19) /= RIN_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(454) <= '1' when (DIVI.OP2(31 downto 0) /= R.E.OP2) else '0';
dfp_trap_vector(455) <= '1' when (DIVI.OP2(19) /= R.E.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(456) <= '1' when (DIVI.OP2(31) /= V_E_OP231_shadow_intermed_1) else '0';
dfp_trap_vector(457) <= '1' when (DIVI.OP2(31) /= R.X.DATA ( 0 )( 31 )) else '0';
dfp_trap_vector(458) <= '1' when (DIVI.OP2(31 downto 0) /= DCO_DATA0_intermed_1) else '0';
dfp_trap_vector(459) <= '1' when (DIVI.OP2(31 downto 0) /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(460) <= '1' when (DIVI.OP2(19) /= RIN_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(461) <= '1' when (DIVI.OP2(19) /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(462) <= '1' when (R.A.CTRL.INST ( 19 ) /= DE_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(463) <= '1' when (R.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(464) <= '1' when (R.A.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(465) <= '1' when (R.A.CTRL.INST ( 19 ) /= R_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(466) <= '1' when (R.A.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(467) <= '1' when (R.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(468) <= '1' when (DIVI.Y(19) /= DE_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(469) <= '1' when (DIVI.Y(31) /= RIN_M_Y31_intermed_1) else '0';
dfp_trap_vector(470) <= '1' when (DIVI.Y(31 downto 0) /= RIN_M_Y_intermed_1) else '0';
dfp_trap_vector(471) <= '1' when (DIVI.Y(19) /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(472) <= '1' when (DIVI.Y(19) /= V_E_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(473) <= '1' when (DIVI.Y(31) /= V_M_Y31_shadow_intermed_2) else '0';
dfp_trap_vector(474) <= '1' when (DIVI.Y(31 downto 0) /= V_M_Y_shadow_intermed_1) else '0';
dfp_trap_vector(475) <= '1' when (DIVI.Y(19) /= V_E_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(476) <= '1' when (DIVI.Y(31 downto 0) /= R.M.Y) else '0';
dfp_trap_vector(477) <= '1' when (DIVI.Y(19) /= R_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(478) <= '1' when (DIVI.Y(31) /= V_M_Y31_shadow_intermed_1) else '0';
dfp_trap_vector(479) <= '1' when (DIVI.Y(19) /= RIN_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(480) <= '1' when (DIVI.Y(0) /= DSIGN_shadow) else '0';
dfp_trap_vector(481) <= '1' when (DIVI.Y(31) /= RIN_M_Y31_intermed_2) else '0';
dfp_trap_vector(482) <= '1' when (DIVI.Y(19) /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(483) <= '1' when (DIVI.Y(31) /= R_M_Y31_intermed_1) else '0';
dfp_trap_vector(484) <= '1' when (DIVI.Y(19) /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(485) <= '1' when (DIVI.Y(19) /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(486) <= '1' when (DIVI.Y(19) /= RIN_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(487) <= '1' when (DIVI.Y(19) /= R.E.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(488) <= '1' when (DIVI.Y(31) /= R.M.Y ( 31 )) else '0';
dfp_trap_vector(489) <= '1' when (DIVI.Y(19) /= RIN_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(490) <= '1' when (DIVI.Y(19) /= V_A_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(491) <= '1' when (R.M.Y ( 31 ) /= RIN_M_Y31_intermed_1) else '0';
dfp_trap_vector(492) <= '1' when (R.M.Y ( 31 ) /= V_M_Y31_shadow_intermed_2) else '0';
dfp_trap_vector(493) <= '1' when (R.M.Y ( 31 ) /= V_M_Y31_shadow_intermed_1) else '0';
dfp_trap_vector(494) <= '1' when (R.M.Y ( 31 ) /= RIN_M_Y31_intermed_2) else '0';
dfp_trap_vector(495) <= '1' when (R.M.Y ( 31 ) /= R_M_Y31_intermed_2) else '0';
dfp_trap_vector(496) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_2) else '0';
dfp_trap_vector(497) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(498) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(499) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_2) else '0';
dfp_trap_vector(500) <= '1' when (DSUR.CRDY ( 2 ) /= DSUR_CRDY2_intermed_2) else '0';
dfp_trap_vector(501) <= '1' when (DBGO.ERROR /= VP_ERROR_shadow_intermed_2) else '0';
dfp_trap_vector(502) <= '1' when (DBGO.ERROR /= R.X.NERROR) else '0';
dfp_trap_vector(503) <= '1' when (DBGO.ERROR /= DUMMY) else '0';
dfp_trap_vector(504) <= '1' when (DBGO.ERROR /= RIN_X_NERROR_intermed_1) else '0';
dfp_trap_vector(505) <= '1' when (DBGO.ERROR /= '1') else '0';
dfp_trap_vector(506) <= '1' when (DBGO.ERROR /= '0') else '0';
dfp_trap_vector(507) <= '1' when (DBGO.ERROR /= RPIN_ERROR_intermed_2) else '0';
dfp_trap_vector(508) <= '1' when (DBGO.ERROR /= V_X_NERROR_shadow_intermed_1) else '0';
dfp_trap_vector(509) <= '1' when (DBGO.ERROR /= RP_ERROR_intermed_1) else '0';
dfp_trap_vector(510) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(511) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(512) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(513) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(514) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(515) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(516) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(517) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(518) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(519) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(520) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(521) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(522) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(523) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(524) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(525) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(526) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(527) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(528) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(529) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(530) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(531) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(532) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(533) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(534) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(535) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(536) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(537) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(538) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(539) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(540) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(541) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(542) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(543) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(544) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(545) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(546) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(547) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(548) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(549) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(550) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(551) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(552) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(553) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(554) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= R_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(555) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow) else '0';
dfp_trap_vector(556) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= R.X.RESULT ( 6 DOWNTO 0 )) else '0';
dfp_trap_vector(557) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(558) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow) else '0';
dfp_trap_vector(559) <= '1' when (RIN.X.DATA ( 0 ) /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(560) <= '1' when (RIN.X.DATA ( 0 ) /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(561) <= '1' when (RIN.X.DATA ( 0 ) /= DCO.DATA ( 0 )) else '0';
dfp_trap_vector(562) <= '1' when (RIN.X.DATA ( 0 ) /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(563) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(564) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(565) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(566) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(567) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(568) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(569) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(570) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(571) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(572) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(573) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_X_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(574) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(575) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(576) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(577) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(578) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(579) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(580) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(581) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.X.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(582) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(583) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(584) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(585) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(586) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(587) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(588) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(589) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(590) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_M_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(591) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(592) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(593) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(594) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_A_CTRL_TT3DOWNTO0_intermed_4) else '0';
dfp_trap_vector(595) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_A_CTRL_TT3DOWNTO0_intermed_5) else '0';
dfp_trap_vector(596) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3) else '0';
dfp_trap_vector(597) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5) else '0';
dfp_trap_vector(598) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(599) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_W_S_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(600) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0';
dfp_trap_vector(601) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_E_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(602) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(603) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_W_S_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(604) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(605) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_M_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(606) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(607) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(608) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_X_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(609) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_E_CTRL_TT3DOWNTO0_intermed_4) else '0';
dfp_trap_vector(610) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R.W.S.TT ( 3 DOWNTO 0 )) else '0';
dfp_trap_vector(611) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow) else '0';
dfp_trap_vector(612) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= XC_VECTT3DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(613) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(614) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= R.M.RESULT ( 1 DOWNTO 0 )) else '0';
dfp_trap_vector(615) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= RIN_M_RESULT1DOWNTO0_intermed_2) else '0';
dfp_trap_vector(616) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow) else '0';
dfp_trap_vector(617) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= R_M_RESULT1DOWNTO0_intermed_1) else '0';
dfp_trap_vector(618) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(619) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(620) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(621) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= R.X.DATA ( 0 ) ( 31 )) else '0';
dfp_trap_vector(622) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(623) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(624) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(625) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(626) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(627) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(628) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(629) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(630) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= DCO.DATA ( 0 )( 31 )) else '0';
dfp_trap_vector(631) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(632) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= R.X.DATA ( 0 )( 31 )) else '0';
dfp_trap_vector(633) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= DE_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(634) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(635) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow) else '0';
dfp_trap_vector(636) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(637) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(638) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(639) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(640) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(641) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(642) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.E.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(643) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= RIN_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(644) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(645) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_1) else '0';
dfp_trap_vector(646) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.E.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(647) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(648) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(649) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R_E_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(650) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(651) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow_intermed_1) else '0';
dfp_trap_vector(652) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow) else '0';
dfp_trap_vector(653) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= DE_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(654) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(655) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= RIN_E_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(656) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(657) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= RIN_X_DATA00_intermed_2) else '0';
dfp_trap_vector(658) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(659) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= DCO_DATA00_intermed_1) else '0';
dfp_trap_vector(660) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow_intermed_1) else '0';
dfp_trap_vector(661) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= R.X.DATA ( 0 ) ( 0 )) else '0';
dfp_trap_vector(662) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow_intermed_1) else '0';
dfp_trap_vector(663) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= R_X_DATA00_intermed_1) else '0';
dfp_trap_vector(664) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= RIN_X_DATA00_intermed_2) else '0';
dfp_trap_vector(665) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= R_X_DATA00_intermed_1) else '0';
dfp_trap_vector(666) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= DCO.DATA ( 0 )( 0 )) else '0';
dfp_trap_vector(667) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(668) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow_intermed_1) else '0';
dfp_trap_vector(669) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= R.X.DATA ( 0 )( 0 )) else '0';
dfp_trap_vector(670) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= RIN_X_DATA00_intermed_2) else '0';
dfp_trap_vector(671) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= R_X_DATA00_intermed_1) else '0';
dfp_trap_vector(672) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(673) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(674) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(675) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(676) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= DCO_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(677) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(678) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(679) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= R.X.DATA ( 0 ) ( 4 DOWNTO 0 )) else '0';
dfp_trap_vector(680) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(681) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(682) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(683) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= R.X.DATA ( 0 )( 4 DOWNTO 0 )) else '0';
dfp_trap_vector(684) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= DCO.DATA ( 0 )( 4 DOWNTO 0 )) else '0';
dfp_trap_vector(685) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(686) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(687) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(688) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(689) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(690) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(691) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(692) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(693) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(694) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(695) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(696) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_7) else '0';
dfp_trap_vector(697) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(698) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(699) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(700) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_F_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(701) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(702) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= IRIN_ADDR31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(703) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(704) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(705) <= '1' when (RIN.F.PC ( 2 DOWNTO 2 ) /= "1") else '0';
dfp_trap_vector(706) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(707) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(708) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R.F.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(709) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= IR_ADDR31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(710) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(711) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(712) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(713) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(714) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(715) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(716) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= R.D.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(717) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(718) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(719) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(720) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow_intermed_1) else '0';
dfp_trap_vector(721) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= DE_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(722) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow) else '0';
dfp_trap_vector(723) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R_A_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(724) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(725) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_1) else '0';
dfp_trap_vector(726) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(727) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= RIN_E_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(728) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R_E_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(729) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(730) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.E.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(731) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= DE_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(732) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(733) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(734) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(735) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(736) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow) else '0';
dfp_trap_vector(737) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow_intermed_1) else '0';
dfp_trap_vector(738) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow) else '0';
dfp_trap_vector(739) <= '1' when (RIN.M.Y ( 31 ) /= RIN_M_Y31_intermed_2) else '0';
dfp_trap_vector(740) <= '1' when (RIN.M.Y ( 31 ) /= R_M_Y31_intermed_1) else '0';
dfp_trap_vector(741) <= '1' when (RIN.M.Y ( 31 ) /= R.M.Y ( 31 )) else '0';
dfp_trap_vector(742) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(743) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow) else '0';
dfp_trap_vector(744) <= '1' when (DSUIN.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_2) else '0';
dfp_trap_vector(745) <= '1' when (DSUIN.CRDY ( 2 ) /= DSUR.CRDY ( 2 )) else '0';
dfp_trap_vector(746) <= '1' when (DSUIN.CRDY ( 2 ) /= DSUR_CRDY2_intermed_1) else '0';
dfp_trap_vector(747) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(748) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(749) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(750) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(751) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(752) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(753) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(754) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(755) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(756) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(757) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(758) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(759) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(760) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(761) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(762) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(763) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(764) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(765) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(766) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(767) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(768) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(769) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(770) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(771) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(772) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(773) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(774) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(775) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(776) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(777) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(778) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(779) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(780) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(781) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(782) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(783) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(784) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(785) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(786) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(787) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(788) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(789) <= '1' when (R.X.DATA ( 1 ) /= V_X_DATA1_shadow_intermed_1) else '0';
dfp_trap_vector(790) <= '1' when (R.X.DATA ( 1 ) /= DCO_DATA1_intermed_1) else '0';
dfp_trap_vector(791) <= '1' when (R.X.DATA ( 1 ) /= V_X_DATA1_shadow_intermed_2) else '0';
dfp_trap_vector(792) <= '1' when (R.X.DATA ( 1 ) /= RIN_X_DATA1_intermed_1) else '0';
dfp_trap_vector(793) <= '1' when (R.X.DATA ( 1 ) /= R_X_DATA1_intermed_2) else '0';
dfp_trap_vector(794) <= '1' when (R.X.DATA ( 1 ) /= RIN_X_DATA1_intermed_2) else '0';
dfp_trap_vector(795) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(796) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_F_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(797) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_A_CTRL_PC31DOWNTO12_intermed_7) else '0';
dfp_trap_vector(798) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_E_CTRL_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(799) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(800) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_M_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(801) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= IRIN_ADDR31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(802) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0';
dfp_trap_vector(803) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2) else '0';
dfp_trap_vector(804) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(805) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_F_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(806) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_M_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(807) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= IR_ADDR31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(808) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_X_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(809) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_D_PC31DOWNTO12_shadow_intermed_8) else '0';
dfp_trap_vector(810) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_7) else '0';
dfp_trap_vector(811) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_6) else '0';
dfp_trap_vector(812) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2) else '0';
dfp_trap_vector(813) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_F_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(814) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_D_PC31DOWNTO12_intermed_7) else '0';
dfp_trap_vector(815) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_A_CTRL_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(816) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_E_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(817) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_X_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(818) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_D_PC31DOWNTO12_intermed_8) else '0';
dfp_trap_vector(819) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= VIR_ADDR31DOWNTO12_shadow_intermed_3) else '0';
dfp_trap_vector(820) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow_intermed_1) else '0';
dfp_trap_vector(821) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0';
dfp_trap_vector(822) <= '1' when (R.D.INST ( 0 ) /= ICO_DATA0_intermed_1) else '0';
dfp_trap_vector(823) <= '1' when (R.D.INST ( 0 ) /= RIN_D_INST0_intermed_1) else '0';
dfp_trap_vector(824) <= '1' when (R.D.INST ( 0 ) /= V_D_INST0_shadow_intermed_2) else '0';
dfp_trap_vector(825) <= '1' when (R.D.INST ( 0 ) /= R_D_INST0_intermed_2) else '0';
dfp_trap_vector(826) <= '1' when (R.D.INST ( 0 ) /= RIN_D_INST0_intermed_2) else '0';
dfp_trap_vector(827) <= '1' when (R.D.INST ( 0 ) /= V_D_INST0_shadow_intermed_1) else '0';
dfp_trap_vector(828) <= '1' when (R.D.INST ( 1 ) /= V_D_INST1_shadow_intermed_2) else '0';
dfp_trap_vector(829) <= '1' when (R.D.INST ( 1 ) /= RIN_D_INST1_intermed_1) else '0';
dfp_trap_vector(830) <= '1' when (R.D.INST ( 1 ) /= RIN_D_INST1_intermed_2) else '0';
dfp_trap_vector(831) <= '1' when (R.D.INST ( 1 ) /= V_D_INST1_shadow_intermed_1) else '0';
dfp_trap_vector(832) <= '1' when (R.D.INST ( 1 ) /= R_D_INST1_intermed_2) else '0';
dfp_trap_vector(833) <= '1' when (R.D.INST ( 1 ) /= ICO_DATA1_intermed_1) else '0';
dfp_trap_vector(834) <= '1' when (R.X.DATA ( 0 )( 31 ) /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(835) <= '1' when (R.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(836) <= '1' when (R.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(837) <= '1' when (R.X.DATA ( 0 )( 31 ) /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(838) <= '1' when (R.X.DATA ( 0 )( 31 ) /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(839) <= '1' when (R.X.DATA ( 0 )( 31 ) /= R_X_DATA031_intermed_2) else '0';
dfp_trap_vector(840) <= '1' when (RIN.X.DATA ( 1 ) /= V_X_DATA1_shadow) else '0';
dfp_trap_vector(841) <= '1' when (RIN.X.DATA ( 1 ) /= DCO.DATA ( 1 )) else '0';
dfp_trap_vector(842) <= '1' when (RIN.X.DATA ( 1 ) /= V_X_DATA1_shadow_intermed_1) else '0';
dfp_trap_vector(843) <= '1' when (RIN.X.DATA ( 1 ) /= R_X_DATA1_intermed_1) else '0';
dfp_trap_vector(844) <= '1' when (RIN.X.DATA ( 1 ) /= R.X.DATA ( 1 )) else '0';
dfp_trap_vector(845) <= '1' when (RIN.X.DATA ( 1 ) /= RIN_X_DATA1_intermed_2) else '0';
dfp_trap_vector(846) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0';
dfp_trap_vector(847) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R.F.PC ( 31 DOWNTO 12 )) else '0';
dfp_trap_vector(848) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_A_CTRL_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(849) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_E_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(850) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow_intermed_1) else '0';
dfp_trap_vector(851) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_M_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(852) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= IRIN_ADDR31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(853) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0';
dfp_trap_vector(854) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1) else '0';
dfp_trap_vector(855) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0';
dfp_trap_vector(856) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_F_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(857) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_M_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(858) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= IR_ADDR31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(859) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_X_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(860) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_D_PC31DOWNTO12_shadow_intermed_7) else '0';
dfp_trap_vector(861) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6) else '0';
dfp_trap_vector(862) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0';
dfp_trap_vector(863) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1) else '0';
dfp_trap_vector(864) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_F_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(865) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_D_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(866) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_A_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(867) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_E_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(868) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_X_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(869) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_D_PC31DOWNTO12_intermed_7) else '0';
dfp_trap_vector(870) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= VIR_ADDR31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(871) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow) else '0';
dfp_trap_vector(872) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0';
dfp_trap_vector(873) <= '1' when (RIN.D.INST ( 0 ) /= ICO.DATA ( 0 )) else '0';
dfp_trap_vector(874) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow_intermed_1) else '0';
dfp_trap_vector(875) <= '1' when (RIN.D.INST ( 0 ) /= R_D_INST0_intermed_1) else '0';
dfp_trap_vector(876) <= '1' when (RIN.D.INST ( 0 ) /= RIN_D_INST0_intermed_2) else '0';
dfp_trap_vector(877) <= '1' when (RIN.D.INST ( 0 ) /= R.D.INST ( 0 )) else '0';
dfp_trap_vector(878) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow) else '0';
dfp_trap_vector(879) <= '1' when (RIN.D.INST ( 1 ) /= V_D_INST1_shadow_intermed_1) else '0';
dfp_trap_vector(880) <= '1' when (RIN.D.INST ( 1 ) /= RIN_D_INST1_intermed_2) else '0';
dfp_trap_vector(881) <= '1' when (RIN.D.INST ( 1 ) /= V_D_INST1_shadow) else '0';
dfp_trap_vector(882) <= '1' when (RIN.D.INST ( 1 ) /= R_D_INST1_intermed_1) else '0';
dfp_trap_vector(883) <= '1' when (RIN.D.INST ( 1 ) /= R.D.INST ( 1 )) else '0';
dfp_trap_vector(884) <= '1' when (RIN.D.INST ( 1 ) /= ICO.DATA ( 1 )) else '0';
dfp_trap_vector(885) <= '1' when (R.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow_intermed_2) else '0';
dfp_trap_vector(886) <= '1' when (R.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow_intermed_1) else '0';
dfp_trap_vector(887) <= '1' when (R.X.DATA ( 0 )( 3 ) /= DCO_DATA03_intermed_1) else '0';
dfp_trap_vector(888) <= '1' when (R.X.DATA ( 0 )( 3 ) /= RIN_X_DATA03_intermed_1) else '0';
dfp_trap_vector(889) <= '1' when (R.X.DATA ( 0 )( 3 ) /= R_X_DATA03_intermed_2) else '0';
dfp_trap_vector(890) <= '1' when (R.X.DATA ( 0 )( 3 ) /= RIN_X_DATA03_intermed_2) else '0';
dfp_trap_vector(891) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow_intermed_1) else '0';
dfp_trap_vector(892) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow) else '0';
dfp_trap_vector(893) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= DCO.DATA ( 0 )( 3 )) else '0';
dfp_trap_vector(894) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= R.X.DATA ( 0 )( 3 )) else '0';
dfp_trap_vector(895) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= R_X_DATA03_intermed_1) else '0';
dfp_trap_vector(896) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= RIN_X_DATA03_intermed_2) else '0';
dfp_trap_vector(897) <= '1' when (R.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_1) else '0';
dfp_trap_vector(898) <= '1' when (R.A.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(899) <= '1' when (R.A.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(900) <= '1' when (R.A.CTRL.INST ( 20 ) /= DE_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(901) <= '1' when (R.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(902) <= '1' when (R.A.CTRL.INST ( 20 ) /= R_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(903) <= '1' when (R.X.DATA ( 0 )( 0 ) /= RIN_X_DATA00_intermed_1) else '0';
dfp_trap_vector(904) <= '1' when (R.X.DATA ( 0 )( 0 ) /= DCO_DATA00_intermed_1) else '0';
dfp_trap_vector(905) <= '1' when (R.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow_intermed_1) else '0';
dfp_trap_vector(906) <= '1' when (R.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow_intermed_2) else '0';
dfp_trap_vector(907) <= '1' when (R.X.DATA ( 0 )( 0 ) /= RIN_X_DATA00_intermed_2) else '0';
dfp_trap_vector(908) <= '1' when (R.X.DATA ( 0 )( 0 ) /= R_X_DATA00_intermed_2) else '0';
dfp_trap_vector(909) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(910) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(911) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= DCO_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(912) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(913) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(914) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(915) <= '1' when (R.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(916) <= '1' when (R.A.CTRL.INST ( 24 ) /= DE_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(917) <= '1' when (R.A.CTRL.INST ( 24 ) /= R_A_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(918) <= '1' when (R.A.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(919) <= '1' when (R.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_1) else '0';
dfp_trap_vector(920) <= '1' when (R.A.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(921) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow) else '0';
dfp_trap_vector(922) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(923) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(924) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= DE_INST20_shadow_intermed_1) else '0';
dfp_trap_vector(925) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_1) else '0';
dfp_trap_vector(926) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= R_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(927) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_1) else '0';
dfp_trap_vector(928) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= DE_INST24_shadow_intermed_1) else '0';
dfp_trap_vector(929) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= R_A_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(930) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow) else '0';
dfp_trap_vector(931) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(932) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(933) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(934) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(935) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(936) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0';
dfp_trap_vector(937) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(938) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(939) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0';
dfp_trap_vector(940) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(941) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 )) else '0';
dfp_trap_vector(942) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow) else '0';
dfp_trap_vector(943) <= '1' when (NPC_shadow /= RIN_F_PC_intermed_1) else '0';
dfp_trap_vector(944) <= '1' when (NPC_shadow /= EX_ADD_RES32DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(945) <= '1' when (NPC_shadow /= XC_TRAP_ADDRESS_shadow_intermed_1) else '0';
dfp_trap_vector(946) <= '1' when (NPC_shadow /= R.F.PC) else '0';
dfp_trap_vector(947) <= '1' when (NPC_shadow /= EX_JUMP_ADDRESS_shadow_intermed_1) else '0';
dfp_trap_vector(948) <= '1' when (NPC_shadow /= "000000000000000000000000000000") else '0';
dfp_trap_vector(949) <= '1' when (NPC_shadow /= V_F_PC_shadow_intermed_1) else '0';
dfp_trap_vector(950) <= '1' when (DE_REN1_shadow /= RIN_A_RFE1_intermed_1) else '0';
dfp_trap_vector(951) <= '1' when (DE_REN1_shadow /= V_A_RFE1_shadow_intermed_1) else '0';
dfp_trap_vector(952) <= '1' when (DE_REN1_shadow /= R.A.RFE1) else '0';
dfp_trap_vector(953) <= '1' when (DE_REN1_shadow /= '1') else '0';
dfp_trap_vector(954) <= '1' when (DE_REN2_shadow /= RIN_A_RFE2_intermed_1) else '0';
dfp_trap_vector(955) <= '1' when (DE_REN2_shadow /= V_A_RFE2_shadow_intermed_1) else '0';
dfp_trap_vector(956) <= '1' when (DE_REN2_shadow /= R.A.RFE2) else '0';
dfp_trap_vector(957) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(958) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(959) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= V_E_OP1_shadow_intermed_1) else '0';
dfp_trap_vector(960) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= V_E_OP2_shadow_intermed_1) else '0';
dfp_trap_vector(961) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= RIN_E_OP2_intermed_1) else '0';
dfp_trap_vector(962) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= RIN_E_OP1_intermed_1) else '0';
dfp_trap_vector(963) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(964) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(965) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= EX_OP2_shadow) else '0';
dfp_trap_vector(966) <= '1' when (EX_ADD_RES_shadow(0) /= V_E_ALUCIN_shadow_intermed_1) else '0';
dfp_trap_vector(967) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(968) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(969) <= '1' when (EX_ADD_RES_shadow(0) /= R.E.ALUCIN) else '0';
dfp_trap_vector(970) <= '1' when (EX_ADD_RES_shadow(0) /= RIN_E_ALUCIN_intermed_1) else '0';
dfp_trap_vector(971) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= X"00000001") else '0';
dfp_trap_vector(972) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= R.E.OP2) else '0';
dfp_trap_vector(973) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= DCO_DATA0_intermed_1) else '0';
dfp_trap_vector(974) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(975) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= R.E.OP1) else '0';
dfp_trap_vector(976) <= '1' when (EX_YMSB_shadow /= RIN_X_DATA00_intermed_2) else '0';
dfp_trap_vector(977) <= '1' when (EX_YMSB_shadow /= V_X_DATA00_shadow_intermed_1) else '0';
dfp_trap_vector(978) <= '1' when (EX_YMSB_shadow /= DCO_DATA00_intermed_1) else '0';
dfp_trap_vector(979) <= '1' when (EX_YMSB_shadow /= V_X_DATA00_shadow_intermed_2) else '0';
dfp_trap_vector(980) <= '1' when (EX_YMSB_shadow /= R.X.DATA ( 0 ) ( 0 )) else '0';
dfp_trap_vector(981) <= '1' when (EX_YMSB_shadow /= V_E_YMSB_shadow_intermed_1) else '0';
dfp_trap_vector(982) <= '1' when (EX_YMSB_shadow /= RIN_X_DATA00_intermed_1) else '0';
dfp_trap_vector(983) <= '1' when (EX_YMSB_shadow /= V_X_DATA00_shadow_intermed_3) else '0';
dfp_trap_vector(984) <= '1' when (EX_YMSB_shadow /= R.E.YMSB) else '0';
dfp_trap_vector(985) <= '1' when (EX_YMSB_shadow /= R_X_DATA00_intermed_1) else '0';
dfp_trap_vector(986) <= '1' when (EX_YMSB_shadow /= RIN_X_DATA00_intermed_3) else '0';
dfp_trap_vector(987) <= '1' when (EX_YMSB_shadow /= R_X_DATA00_intermed_2) else '0';
dfp_trap_vector(988) <= '1' when (EX_YMSB_shadow /= RIN_E_YMSB_intermed_1) else '0';
dfp_trap_vector(989) <= '1' when (EX_OP1_shadow /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(990) <= '1' when (EX_OP1_shadow /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(991) <= '1' when (EX_OP1_shadow /= V_E_OP1_shadow_intermed_1) else '0';
dfp_trap_vector(992) <= '1' when (EX_OP1_shadow /= RIN_E_OP1_intermed_1) else '0';
dfp_trap_vector(993) <= '1' when (EX_OP1_shadow /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(994) <= '1' when (EX_OP1_shadow /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(995) <= '1' when (EX_OP1_shadow /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(996) <= '1' when (EX_OP1_shadow /= DCO_DATA0_intermed_1) else '0';
dfp_trap_vector(997) <= '1' when (EX_OP1_shadow /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(998) <= '1' when (EX_OP1_shadow /= R.E.OP1) else '0';
dfp_trap_vector(999) <= '1' when (EX_OP2_shadow /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(1000) <= '1' when (EX_OP2_shadow /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(1001) <= '1' when (EX_OP2_shadow /= V_E_OP2_shadow_intermed_1) else '0';
dfp_trap_vector(1002) <= '1' when (EX_OP2_shadow /= RIN_E_OP2_intermed_1) else '0';
dfp_trap_vector(1003) <= '1' when (EX_OP2_shadow /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(1004) <= '1' when (EX_OP2_shadow /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(1005) <= '1' when (EX_OP2_shadow /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(1006) <= '1' when (EX_OP2_shadow /= R.E.OP2) else '0';
dfp_trap_vector(1007) <= '1' when (EX_OP2_shadow /= DCO_DATA0_intermed_1) else '0';
dfp_trap_vector(1008) <= '1' when (EX_OP2_shadow /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(1009) <= '1' when (EX_SHCNT_shadow /= RIN_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1010) <= '1' when (EX_SHCNT_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(1011) <= '1' when (EX_SHCNT_shadow /= R.E.SHCNT) else '0';
dfp_trap_vector(1012) <= '1' when (EX_SHCNT_shadow /= R_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1013) <= '1' when (EX_SHCNT_shadow /= V_E_SHCNT_shadow_intermed_1) else '0';
dfp_trap_vector(1014) <= '1' when (EX_SHCNT_shadow /= R_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1015) <= '1' when (EX_SHCNT_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(1016) <= '1' when (EX_SHCNT_shadow /= RIN_X_DATA04DOWNTO0_intermed_3) else '0';
dfp_trap_vector(1017) <= '1' when (EX_SHCNT_shadow /= RIN_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1018) <= '1' when (EX_SHCNT_shadow /= DCO_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1019) <= '1' when (EX_SHCNT_shadow /= RIN_E_SHCNT_intermed_1) else '0';
dfp_trap_vector(1020) <= '1' when (EX_SHCNT_shadow /= R.X.DATA ( 0 ) ( 4 DOWNTO 0 )) else '0';
dfp_trap_vector(1021) <= '1' when (EX_SHCNT_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(1022) <= '1' when (EX_SARI_shadow /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(1023) <= '1' when (EX_SARI_shadow /= DE_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(1024) <= '1' when (EX_SARI_shadow /= V_A_CTRL_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(1025) <= '1' when (EX_SARI_shadow /= V_A_CTRL_INST19_shadow_intermed_3) else '0';
dfp_trap_vector(1026) <= '1' when (EX_SARI_shadow /= R.E.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(1027) <= '1' when (EX_SARI_shadow /= RIN_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(1028) <= '1' when (EX_SARI_shadow /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(1029) <= '1' when (EX_SARI_shadow /= V_E_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(1030) <= '1' when (EX_SARI_shadow /= V_X_DATA031_shadow_intermed_3) else '0';
dfp_trap_vector(1031) <= '1' when (EX_SARI_shadow /= R.X.DATA ( 0 ) ( 31 )) else '0';
dfp_trap_vector(1032) <= '1' when (EX_SARI_shadow /= V_E_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(1033) <= '1' when (EX_SARI_shadow /= RIN_X_DATA031_intermed_3) else '0';
dfp_trap_vector(1034) <= '1' when (EX_SARI_shadow /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(1035) <= '1' when (EX_SARI_shadow /= V_E_SARI_shadow_intermed_1) else '0';
dfp_trap_vector(1036) <= '1' when (EX_SARI_shadow /= R_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(1037) <= '1' when (EX_SARI_shadow /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(1038) <= '1' when (EX_SARI_shadow /= R_X_DATA031_intermed_2) else '0';
dfp_trap_vector(1039) <= '1' when (EX_SARI_shadow /= RIN_E_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(1040) <= '1' when (EX_SARI_shadow /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(1041) <= '1' when (EX_SARI_shadow /= R_E_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(1042) <= '1' when (EX_SARI_shadow /= R_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(1043) <= '1' when (EX_SARI_shadow /= RIN_A_CTRL_INST20_intermed_3) else '0';
dfp_trap_vector(1044) <= '1' when (EX_SARI_shadow /= R_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(1045) <= '1' when (EX_SARI_shadow /= R.E.SARI) else '0';
dfp_trap_vector(1046) <= '1' when (EX_SARI_shadow /= V_E_CTRL_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(1047) <= '1' when (EX_SARI_shadow /= V_E_CTRL_INST20_shadow_intermed_1) else '0';
dfp_trap_vector(1048) <= '1' when (EX_SARI_shadow /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(1049) <= '1' when (EX_SARI_shadow /= DE_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(1050) <= '1' when (EX_SARI_shadow /= RIN_A_CTRL_INST19_intermed_3) else '0';
dfp_trap_vector(1051) <= '1' when (EX_SARI_shadow /= RIN_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(1052) <= '1' when (EX_SARI_shadow /= R.E.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(1053) <= '1' when (EX_SARI_shadow /= V_A_CTRL_INST20_shadow_intermed_3) else '0';
dfp_trap_vector(1054) <= '1' when (EX_SARI_shadow /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(1055) <= '1' when (EX_SARI_shadow /= RIN_E_SARI_intermed_1) else '0';
dfp_trap_vector(1056) <= '1' when (EX_SARI_shadow /= RIN_E_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(1057) <= '1' when (EX_SARI_shadow /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(1058) <= '1' when (EX_SARI_shadow /= RIN_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(1059) <= '1' when (EX_SARI_shadow /= R_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(1060) <= '1' when (EX_SARI_shadow /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(1061) <= '1' when (ME_SIGNED_shadow /= V_M_DCI_SIGNED_shadow_intermed_2) else '0';
dfp_trap_vector(1062) <= '1' when (ME_SIGNED_shadow /= RIN_M_DCI_SIGNED_intermed_2) else '0';
dfp_trap_vector(1063) <= '1' when (ME_SIGNED_shadow /= R_M_DCI_SIGNED_intermed_1) else '0';
dfp_trap_vector(1064) <= '1' when (ME_SIGNED_shadow /= R.X.DCI.SIGNED) else '0';
dfp_trap_vector(1065) <= '1' when (ME_SIGNED_shadow /= V_X_DCI_SIGNED_shadow_intermed_1) else '0';
dfp_trap_vector(1066) <= '1' when (ME_SIGNED_shadow /= RIN_X_DCI_SIGNED_intermed_1) else '0';
dfp_trap_vector(1067) <= '1' when (ME_SIZE_shadow /= R.X.DCI.SIZE) else '0';
dfp_trap_vector(1068) <= '1' when (ME_SIZE_shadow /= RIN_M_DCI_SIZE_intermed_2) else '0';
dfp_trap_vector(1069) <= '1' when (ME_SIZE_shadow /= V_M_DCI_SIZE_shadow_intermed_2) else '0';
dfp_trap_vector(1070) <= '1' when (ME_SIZE_shadow /= R_M_DCI_SIZE_intermed_1) else '0';
dfp_trap_vector(1071) <= '1' when (ME_SIZE_shadow /= V_X_DCI_SIZE_shadow_intermed_1) else '0';
dfp_trap_vector(1072) <= '1' when (ME_SIZE_shadow /= RIN_X_DCI_SIZE_intermed_1) else '0';
dfp_trap_vector(1073) <= '1' when (ME_LADDR_shadow /= V_M_RESULT1DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(1074) <= '1' when (ME_LADDR_shadow /= RIN_X_LADDR_intermed_1) else '0';
dfp_trap_vector(1075) <= '1' when (ME_LADDR_shadow /= R_M_RESULT1DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1076) <= '1' when (ME_LADDR_shadow /= RIN_M_RESULT1DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1077) <= '1' when (ME_LADDR_shadow /= RIN_M_RESULT1DOWNTO0_intermed_3) else '0';
dfp_trap_vector(1078) <= '1' when (ME_LADDR_shadow /= V_M_RESULT1DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(1079) <= '1' when (ME_LADDR_shadow /= V_X_LADDR_shadow_intermed_1) else '0';
dfp_trap_vector(1080) <= '1' when (ME_LADDR_shadow /= R.X.LADDR) else '0';
dfp_trap_vector(1081) <= '1' when (ME_LADDR_shadow /= R_M_RESULT1DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1082) <= '1' when (XC_RESULT_shadow /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(1083) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1084) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1085) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(1086) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(1087) <= '1' when (XC_RESULT_shadow /= RIN_X_RESULT_intermed_1) else '0';
dfp_trap_vector(1088) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(1089) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(1090) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1091) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(1092) <= '1' when (XC_RESULT_shadow /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(1093) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1094) <= '1' when (XC_RESULT_shadow /= V_X_RESULT_shadow_intermed_1) else '0';
dfp_trap_vector(1095) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_X_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1096) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1097) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(1098) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(1099) <= '1' when (XC_RESULT_shadow /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(1100) <= '1' when (XC_RESULT_shadow /= R.X.RESULT) else '0';
dfp_trap_vector(1101) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1102) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1103) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1104) <= '1' when (XC_RESULT_shadow /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(1105) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1106) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1107) <= '1' when (XC_RESULT_shadow /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(1108) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(1109) <= '1' when (XC_RESULT_shadow /= X"00000000") else '0';
dfp_trap_vector(1110) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R.X.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(1111) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1112) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(1113) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_D_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1114) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1115) <= '1' when (XC_RESULT_shadow /= DCO_DATA0_intermed_1) else '0';
dfp_trap_vector(1116) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1117) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(1118) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(1119) <= '1' when (XC_RESULT_shadow /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(1120) <= '1' when (XC_EXCEPTION_shadow /= '1') else '0';
dfp_trap_vector(1121) <= '1' when (XC_EXCEPTION_shadow /= '0') else '0';
dfp_trap_vector(1122) <= '1' when (XC_WREG_shadow /= V_X_ANNUL_ALL_shadow_intermed_4) else '0';
dfp_trap_vector(1123) <= '1' when (XC_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_5) else '0';
dfp_trap_vector(1124) <= '1' when (XC_WREG_shadow /= R_M_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(1125) <= '1' when (XC_WREG_shadow /= R.X.CTRL.WREG) else '0';
dfp_trap_vector(1126) <= '1' when (XC_WREG_shadow /= R_A_CTRL_ANNUL_intermed_4) else '0';
dfp_trap_vector(1127) <= '1' when (XC_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_5) else '0';
dfp_trap_vector(1128) <= '1' when (XC_WREG_shadow /= V_M_CTRL_WREG_shadow_intermed_2) else '0';
dfp_trap_vector(1129) <= '1' when (XC_WREG_shadow /= R_X_ANNUL_ALL_intermed_4) else '0';
dfp_trap_vector(1130) <= '1' when (XC_WREG_shadow /= V_X_CTRL_WREG_shadow_intermed_1) else '0';
dfp_trap_vector(1131) <= '1' when (XC_WREG_shadow /= R_E_CTRL_WREG_intermed_2) else '0';
dfp_trap_vector(1132) <= '1' when (XC_WREG_shadow /= RIN_X_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(1133) <= '1' when (XC_WREG_shadow /= '1') else '0';
dfp_trap_vector(1134) <= '1' when (XC_WREG_shadow /= '0') else '0';
dfp_trap_vector(1135) <= '1' when (XC_WREG_shadow /= V_A_CTRL_ANNUL_shadow_intermed_4) else '0';
dfp_trap_vector(1136) <= '1' when (XC_WREG_shadow /= RIN_E_CTRL_WREG_intermed_3) else '0';
dfp_trap_vector(1137) <= '1' when (XC_WREG_shadow /= RIN_M_CTRL_WREG_intermed_2) else '0';
dfp_trap_vector(1138) <= '1' when (XC_WREG_shadow /= V_E_CTRL_WREG_shadow_intermed_3) else '0';
dfp_trap_vector(1139) <= '1' when (XC_WREG_shadow /= RIN_A_CTRL_WREG_intermed_4) else '0';
dfp_trap_vector(1140) <= '1' when (XC_WREG_shadow /= V_A_CTRL_WREG_shadow_intermed_4) else '0';
dfp_trap_vector(1141) <= '1' when (XC_WREG_shadow /= R_A_CTRL_WREG_intermed_3) else '0';
dfp_trap_vector(1142) <= '1' when (XC_VECTT_shadow(5 downto 0) /= V_E_CTRL_TT_shadow_intermed_3) else '0';
dfp_trap_vector(1143) <= '1' when (XC_VECTT_shadow(5 downto 0) /= V_X_CTRL_TT_shadow_intermed_1) else '0';
dfp_trap_vector(1144) <= '1' when (XC_VECTT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(1145) <= '1' when (XC_VECTT_shadow(5 downto 0) /= RIN_A_CTRL_TT_intermed_4) else '0';
dfp_trap_vector(1146) <= '1' when (XC_VECTT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1147) <= '1' when (XC_VECTT_shadow(5 downto 0) /= RIN_E_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(1148) <= '1' when (XC_VECTT_shadow(5 downto 0) /= V_M_CTRL_TT_shadow_intermed_2) else '0';
dfp_trap_vector(1149) <= '1' when (XC_VECTT_shadow(6 downto 0) /= R_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1150) <= '1' when (XC_VECTT_shadow(5 downto 0) /= R_A_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(1151) <= '1' when (XC_VECTT_shadow(5 downto 0) /= V_A_CTRL_TT_shadow_intermed_4) else '0';
dfp_trap_vector(1152) <= '1' when (XC_VECTT_shadow(5 downto 0) /= R_M_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1153) <= '1' when (XC_VECTT_shadow(5 downto 0) /= RIN_X_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1154) <= '1' when (XC_VECTT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1155) <= '1' when (XC_VECTT_shadow /= "00000000") else '0';
dfp_trap_vector(1156) <= '1' when (XC_VECTT_shadow /= "00001001") else '0';
dfp_trap_vector(1157) <= '1' when (XC_VECTT_shadow(5 downto 0) /= R_E_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(1158) <= '1' when (XC_VECTT_shadow /= X"00") else '0';
dfp_trap_vector(1159) <= '1' when (XC_VECTT_shadow /= X"01") else '0';
dfp_trap_vector(1160) <= '1' when (XC_VECTT_shadow(5 downto 0) /= R.X.CTRL.TT) else '0';
dfp_trap_vector(1161) <= '1' when (XC_VECTT_shadow(5 downto 0) /= RIN_M_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(1162) <= '1' when (XC_VECTT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(1163) <= '1' when (XC_VECTT_shadow(6 downto 0) /= R.X.RESULT ( 6 DOWNTO 0 )) else '0';
dfp_trap_vector(1164) <= '1' when (XC_TRAP_shadow /= R.X.CTRL.TRAP) else '0';
dfp_trap_vector(1165) <= '1' when (XC_TRAP_shadow /= V_M_CTRL_TRAP_shadow_intermed_2) else '0';
dfp_trap_vector(1166) <= '1' when (XC_TRAP_shadow /= RIN_X_CTRL_TRAP_intermed_1) else '0';
dfp_trap_vector(1167) <= '1' when (XC_TRAP_shadow /= V_X_CTRL_TRAP_shadow_intermed_1) else '0';
dfp_trap_vector(1168) <= '1' when (XC_TRAP_shadow /= V_A_CTRL_TRAP_shadow_intermed_4) else '0';
dfp_trap_vector(1169) <= '1' when (XC_TRAP_shadow /= V_X_MEXC_shadow_intermed_1) else '0';
dfp_trap_vector(1170) <= '1' when (XC_TRAP_shadow /= V_D_MEXC_shadow_intermed_5) else '0';
dfp_trap_vector(1171) <= '1' when (XC_TRAP_shadow /= R_A_CTRL_TRAP_intermed_3) else '0';
dfp_trap_vector(1172) <= '1' when (XC_TRAP_shadow /= RIN_X_MEXC_intermed_1) else '0';
dfp_trap_vector(1173) <= '1' when (XC_TRAP_shadow /= RIN_M_CTRL_TRAP_intermed_2) else '0';
dfp_trap_vector(1174) <= '1' when (XC_TRAP_shadow /= R_M_CTRL_TRAP_intermed_1) else '0';
dfp_trap_vector(1175) <= '1' when (XC_TRAP_shadow /= ICO_MEXC_intermed_5) else '0';
dfp_trap_vector(1176) <= '1' when (XC_TRAP_shadow /= R_E_CTRL_TRAP_intermed_2) else '0';
dfp_trap_vector(1177) <= '1' when (XC_TRAP_shadow /= RIN_A_CTRL_TRAP_intermed_4) else '0';
dfp_trap_vector(1178) <= '1' when (XC_TRAP_shadow /= V_E_CTRL_TRAP_shadow_intermed_3) else '0';
dfp_trap_vector(1179) <= '1' when (XC_TRAP_shadow /= RIN_E_CTRL_TRAP_intermed_3) else '0';
dfp_trap_vector(1180) <= '1' when (XC_TRAP_shadow /= R.X.MEXC) else '0';
dfp_trap_vector(1181) <= '1' when (XC_TRAP_shadow /= RIN_D_MEXC_intermed_5) else '0';
dfp_trap_vector(1182) <= '1' when (XC_TRAP_shadow /= R_D_MEXC_intermed_4) else '0';
dfp_trap_vector(1183) <= '1' when (XC_TRAP_shadow /= DCO_MEXC_intermed_1) else '0';
dfp_trap_vector(1184) <= '1' when (XC_HALT_shadow /= DBGI.HALT) else '0';
dfp_trap_vector(1185) <= '1' when (XC_HALT_shadow /= '0') else '0';
dfp_trap_vector(1186) <= '1' when (DSIGN_shadow /= DE_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(1187) <= '1' when (DSIGN_shadow /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(1188) <= '1' when (DSIGN_shadow /= V_E_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(1189) <= '1' when (DSIGN_shadow /= V_E_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(1190) <= '1' when (DSIGN_shadow /= R_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(1191) <= '1' when (DSIGN_shadow /= RIN_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(1192) <= '1' when (DSIGN_shadow /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(1193) <= '1' when (DSIGN_shadow /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(1194) <= '1' when (DSIGN_shadow /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(1195) <= '1' when (DSIGN_shadow /= RIN_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(1196) <= '1' when (DSIGN_shadow /= R.E.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(1197) <= '1' when (DSIGN_shadow /= RIN_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(1198) <= '1' when (DSIGN_shadow /= V_A_CTRL_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(1199) <= '1' when (SIDLE_shadow /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(1200) <= '1' when (SIDLE_shadow /= ICO.IDLE) else '0';
dfp_trap_vector(1201) <= '1' when (SIDLE_shadow /= RPIN_PWD_intermed_1) else '0';
dfp_trap_vector(1202) <= '1' when (SIDLE_shadow /= V_X_DEBUG_shadow_intermed_1) else '0';
dfp_trap_vector(1203) <= '1' when (SIDLE_shadow /= RP.PWD) else '0';
dfp_trap_vector(1204) <= '1' when (SIDLE_shadow /= VP_PWD_shadow_intermed_1) else '0';
dfp_trap_vector(1205) <= '1' when (SIDLE_shadow /= DCO.IDLE) else '0';
dfp_trap_vector(1206) <= '1' when (SIDLE_shadow /= '1') else '0';
dfp_trap_vector(1207) <= '1' when (SIDLE_shadow /= R.X.DEBUG) else '0';
dfp_trap_vector(1208) <= '1' when (SIDLE_shadow /= '0') else '0';
dfp_trap_vector(1209) <= '1' when (SIDLE_shadow /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(1210) <= '1' when (SIDLE_shadow /= RP.ERROR) else '0';
dfp_trap_vector(1211) <= '1' when (SIDLE_shadow /= RIN_X_DEBUG_intermed_1) else '0';
dfp_trap_vector(1212) <= '1' when (ICNT_shadow /= HOLDN) else '0';
dfp_trap_vector(1213) <= '1' when (ICNT_shadow /= '0') else '0';
dfp_trap_vector(1214) <= '1' when (V_X_NERROR_shadow /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(1215) <= '1' when (V_X_NERROR_shadow /= R.X.NERROR) else '0';
dfp_trap_vector(1216) <= '1' when (V_X_NERROR_shadow /= RIN_X_NERROR_intermed_1) else '0';
dfp_trap_vector(1217) <= '1' when (V_X_NERROR_shadow /= '1') else '0';
dfp_trap_vector(1218) <= '1' when (V_X_NERROR_shadow /= '0') else '0';
dfp_trap_vector(1219) <= '1' when (V_X_NERROR_shadow /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(1220) <= '1' when (V_X_NERROR_shadow /= RP.ERROR) else '0';
dfp_trap_vector(1221) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_F_PC31DOWNTO4_shadow_intermed_1) else '0';
dfp_trap_vector(1222) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= V_X_CTRL_TT_shadow_intermed_1) else '0';
dfp_trap_vector(1223) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= V_E_CTRL_TT_shadow_intermed_3) else '0';
dfp_trap_vector(1224) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= X"0000000") else '0';
dfp_trap_vector(1225) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= RIN_A_CTRL_TT_intermed_4) else '0';
dfp_trap_vector(1226) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_X_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0';
dfp_trap_vector(1227) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= IR_ADDR31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(1228) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R.F.PC( 31 DOWNTO 4 )) else '0';
dfp_trap_vector(1229) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= R_A_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(1230) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(11 downto 4) /= XC_VECTT_shadow) else '0';
dfp_trap_vector(1231) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= R_M_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1232) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_F_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(1233) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= VIR_ADDR31DOWNTO4_shadow_intermed_2) else '0';
dfp_trap_vector(1234) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1235) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= X"0000000") else '0';
dfp_trap_vector(1236) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= R_E_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(1237) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_5) else '0';
dfp_trap_vector(1238) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_6) else '0';
dfp_trap_vector(1239) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_6) else '0';
dfp_trap_vector(1240) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_X_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(1241) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1) else '0';
dfp_trap_vector(1242) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= X"0000001") else '0';
dfp_trap_vector(1243) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= R.X.CTRL.TT) else '0';
dfp_trap_vector(1244) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(23 downto 4) /= V_W_S_TBA_shadow_intermed_1) else '0';
dfp_trap_vector(1245) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= RIN_M_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(1246) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(1247) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_5) else '0';
dfp_trap_vector(1248) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_7) else '0';
dfp_trap_vector(1249) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(1250) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= R.X.RESULT ( 6 DOWNTO 0 )) else '0';
dfp_trap_vector(1251) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_X_CTRL_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(1252) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(1253) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1254) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(23 downto 4) /= R.W.S.TBA) else '0';
dfp_trap_vector(1255) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= RIN_E_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(1256) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= R_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1257) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= V_M_CTRL_TT_shadow_intermed_2) else '0';
dfp_trap_vector(1258) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= IRIN_ADDR31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(1259) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_M_CTRL_PC31DOWNTO4_shadow_intermed_4) else '0';
dfp_trap_vector(1260) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= V_A_CTRL_TT_shadow_intermed_4) else '0';
dfp_trap_vector(1261) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1) else '0';
dfp_trap_vector(1262) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_M_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(1263) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= RIN_X_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1264) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= X"0001001") else '0';
dfp_trap_vector(1265) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_7) else '0';
dfp_trap_vector(1266) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_5) else '0';
dfp_trap_vector(1267) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1) else '0';
dfp_trap_vector(1268) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(23 downto 4) /= RIN_W_S_TBA_intermed_1) else '0';
dfp_trap_vector(1269) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_6) else '0';
dfp_trap_vector(1270) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= X"0000000") else '0';
dfp_trap_vector(1271) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(1272) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_6) else '0';
dfp_trap_vector(1273) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(1274) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= VIR_ADDR3DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(1275) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_7) else '0';
dfp_trap_vector(1276) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_M_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1277) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1278) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(1279) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_X_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1280) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_5) else '0';
dfp_trap_vector(1281) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R.F.PC( 3 DOWNTO 2 )) else '0';
dfp_trap_vector(1282) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_X_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(1283) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1284) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= IRIN_ADDR3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1285) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(1286) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(1287) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_6) else '0';
dfp_trap_vector(1288) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(1289) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_F_PC3DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(1290) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(1291) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= "00") else '0';
dfp_trap_vector(1292) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= IR_ADDR3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1293) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_M_CTRL_PC3DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(1294) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_X_CTRL_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1295) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_5) else '0';
dfp_trap_vector(1296) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_F_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1297) <= '1' when (V_X_ANNUL_ALL_shadow /= R.X.ANNUL_ALL) else '0';
dfp_trap_vector(1298) <= '1' when (V_X_ANNUL_ALL_shadow /= '1') else '0';
dfp_trap_vector(1299) <= '1' when (V_X_ANNUL_ALL_shadow /= '0') else '0';
dfp_trap_vector(1300) <= '1' when (V_X_ANNUL_ALL_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1301) <= '1' when (V_X_DEBUG_shadow /= '1') else '0';
dfp_trap_vector(1302) <= '1' when (V_X_DEBUG_shadow /= R.X.DEBUG) else '0';
dfp_trap_vector(1303) <= '1' when (V_X_DEBUG_shadow /= '0') else '0';
dfp_trap_vector(1304) <= '1' when (V_X_DEBUG_shadow /= RIN_X_DEBUG_intermed_1) else '0';
dfp_trap_vector(1305) <= '1' when (VIR_ADDR_shadow /= RIN_D_PC_intermed_5) else '0';
dfp_trap_vector(1306) <= '1' when (VIR_ADDR_shadow /= RIN_A_CTRL_PC_intermed_4) else '0';
dfp_trap_vector(1307) <= '1' when (VIR_ADDR_shadow /= R_A_CTRL_PC_intermed_3) else '0';
dfp_trap_vector(1308) <= '1' when (VIR_ADDR_shadow /= V_E_CTRL_PC_shadow_intermed_3) else '0';
dfp_trap_vector(1309) <= '1' when (VIR_ADDR_shadow /= IR.ADDR) else '0';
dfp_trap_vector(1310) <= '1' when (VIR_ADDR_shadow /= R_M_CTRL_PC_intermed_1) else '0';
dfp_trap_vector(1311) <= '1' when (VIR_ADDR_shadow /= R.X.CTRL.PC) else '0';
dfp_trap_vector(1312) <= '1' when (VIR_ADDR_shadow /= R_E_CTRL_PC_intermed_2) else '0';
dfp_trap_vector(1313) <= '1' when (VIR_ADDR_shadow /= RIN_M_CTRL_PC_intermed_2) else '0';
dfp_trap_vector(1314) <= '1' when (VIR_ADDR_shadow /= V_X_CTRL_PC_shadow_intermed_1) else '0';
dfp_trap_vector(1315) <= '1' when (VIR_ADDR_shadow /= V_M_CTRL_PC_shadow_intermed_2) else '0';
dfp_trap_vector(1316) <= '1' when (VIR_ADDR_shadow /= V_A_CTRL_PC_shadow_intermed_4) else '0';
dfp_trap_vector(1317) <= '1' when (VIR_ADDR_shadow /= R_D_PC_intermed_4) else '0';
dfp_trap_vector(1318) <= '1' when (VIR_ADDR_shadow /= RIN_E_CTRL_PC_intermed_3) else '0';
dfp_trap_vector(1319) <= '1' when (VIR_ADDR_shadow /= RIN_X_CTRL_PC_intermed_1) else '0';
dfp_trap_vector(1320) <= '1' when (VIR_ADDR_shadow /= V_D_PC_shadow_intermed_5) else '0';
dfp_trap_vector(1321) <= '1' when (VIR_ADDR_shadow /= IRIN_ADDR_intermed_1) else '0';
dfp_trap_vector(1322) <= '1' when (VDSU_TT_shadow(5 downto 0) /= V_E_CTRL_TT_shadow_intermed_3) else '0';
dfp_trap_vector(1323) <= '1' when (VDSU_TT_shadow(5 downto 0) /= V_X_CTRL_TT_shadow_intermed_1) else '0';
dfp_trap_vector(1324) <= '1' when (VDSU_TT_shadow(5 downto 0) /= RIN_A_CTRL_TT_intermed_4) else '0';
dfp_trap_vector(1325) <= '1' when (VDSU_TT_shadow(5 downto 0) /= R_A_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(1326) <= '1' when (VDSU_TT_shadow /= XC_VECTT_shadow) else '0';
dfp_trap_vector(1327) <= '1' when (VDSU_TT_shadow(5 downto 0) /= R_M_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1328) <= '1' when (VDSU_TT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1329) <= '1' when (VDSU_TT_shadow /= DSUIN_TT_intermed_1) else '0';
dfp_trap_vector(1330) <= '1' when (VDSU_TT_shadow /= X"00") else '0';
dfp_trap_vector(1331) <= '1' when (VDSU_TT_shadow(5 downto 0) /= R_E_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(1332) <= '1' when (VDSU_TT_shadow /= X"01") else '0';
dfp_trap_vector(1333) <= '1' when (VDSU_TT_shadow(5 downto 0) /= R.X.CTRL.TT) else '0';
dfp_trap_vector(1334) <= '1' when (VDSU_TT_shadow(5 downto 0) /= RIN_M_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(1335) <= '1' when (VDSU_TT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(1336) <= '1' when (VDSU_TT_shadow(6 downto 0) /= R.X.RESULT ( 6 DOWNTO 0 )) else '0';
dfp_trap_vector(1337) <= '1' when (VDSU_TT_shadow /= DSUR.TT) else '0';
dfp_trap_vector(1338) <= '1' when (VDSU_TT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(1339) <= '1' when (VDSU_TT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1340) <= '1' when (VDSU_TT_shadow(5 downto 0) /= RIN_E_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(1341) <= '1' when (VDSU_TT_shadow(5 downto 0) /= V_M_CTRL_TT_shadow_intermed_2) else '0';
dfp_trap_vector(1342) <= '1' when (VDSU_TT_shadow(6 downto 0) /= R_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1343) <= '1' when (VDSU_TT_shadow(5 downto 0) /= V_A_CTRL_TT_shadow_intermed_4) else '0';
dfp_trap_vector(1344) <= '1' when (VDSU_TT_shadow(5 downto 0) /= RIN_X_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1345) <= '1' when (VDSU_TT_shadow /= "00001001") else '0';
dfp_trap_vector(1346) <= '1' when (VDSU_TT_shadow /= X"00") else '0';
dfp_trap_vector(1347) <= '1' when (VP_PWD_shadow /= RP.PWD) else '0';
dfp_trap_vector(1348) <= '1' when (VP_PWD_shadow /= '1') else '0';
dfp_trap_vector(1349) <= '1' when (VP_PWD_shadow /= '0') else '0';
dfp_trap_vector(1350) <= '1' when (VP_PWD_shadow /= RPIN_PWD_intermed_1) else '0';
dfp_trap_vector(1351) <= '1' when (VIR_PWD_shadow /= '1') else '0';
dfp_trap_vector(1352) <= '1' when (VIR_PWD_shadow /= '0') else '0';
dfp_trap_vector(1353) <= '1' when (VIR_PWD_shadow /= IRIN_PWD_intermed_1) else '0';
dfp_trap_vector(1354) <= '1' when (VIR_PWD_shadow /= IR.PWD) else '0';
dfp_trap_vector(1355) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= V_E_CTRL_TT_shadow_intermed_3) else '0';
dfp_trap_vector(1356) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= V_X_CTRL_TT_shadow_intermed_1) else '0';
dfp_trap_vector(1357) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= RIN_A_CTRL_TT_intermed_4) else '0';
dfp_trap_vector(1358) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= R_A_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(1359) <= '1' when (V_W_S_TT_shadow /= XC_VECTT_shadow) else '0';
dfp_trap_vector(1360) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= R_M_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1361) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1362) <= '1' when (V_W_S_TT_shadow /= "00000000") else '0';
dfp_trap_vector(1363) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= R_E_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(1364) <= '1' when (V_W_S_TT_shadow /= X"01") else '0';
dfp_trap_vector(1365) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= R.X.CTRL.TT) else '0';
dfp_trap_vector(1366) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= RIN_M_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(1367) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(1368) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= R.X.RESULT ( 6 DOWNTO 0 )) else '0';
dfp_trap_vector(1369) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(1370) <= '1' when (V_W_S_TT_shadow /= R.W.S.TT) else '0';
dfp_trap_vector(1371) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1372) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= RIN_E_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(1373) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= V_M_CTRL_TT_shadow_intermed_2) else '0';
dfp_trap_vector(1374) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= R_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1375) <= '1' when (V_W_S_TT_shadow /= RIN_W_S_TT_intermed_1) else '0';
dfp_trap_vector(1376) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= V_A_CTRL_TT_shadow_intermed_4) else '0';
dfp_trap_vector(1377) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= RIN_X_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1378) <= '1' when (V_W_S_TT_shadow /= "00001001") else '0';
dfp_trap_vector(1379) <= '1' when (V_W_S_TT_shadow /= X"00") else '0';
dfp_trap_vector(1380) <= '1' when (V_W_S_PS_shadow /= '1') else '0';
dfp_trap_vector(1381) <= '1' when (V_W_S_PS_shadow /= R.W.S.S) else '0';
dfp_trap_vector(1382) <= '1' when (V_W_S_PS_shadow /= RIN_W_S_S_intermed_1) else '0';
dfp_trap_vector(1383) <= '1' when (V_W_S_PS_shadow /= RIN_W_S_PS_intermed_1) else '0';
dfp_trap_vector(1384) <= '1' when (V_W_S_PS_shadow /= R.W.S.PS) else '0';
dfp_trap_vector(1385) <= '1' when (V_W_S_PS_shadow /= V_W_S_S_shadow_intermed_1) else '0';
dfp_trap_vector(1386) <= '1' when (V_W_S_S_shadow /= '1') else '0';
dfp_trap_vector(1387) <= '1' when (V_W_S_S_shadow /= R.W.S.S) else '0';
dfp_trap_vector(1388) <= '1' when (V_W_S_S_shadow /= RIN_W_S_S_intermed_1) else '0';
dfp_trap_vector(1389) <= '1' when (XC_WADDR6DOWNTO0_shadow /= RIN_E_CTRL_RD6DOWNTO0_intermed_3) else '0';
dfp_trap_vector(1390) <= '1' when (XC_WADDR6DOWNTO0_shadow /= RIN_M_CTRL_RD6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1391) <= '1' when (XC_WADDR6DOWNTO0_shadow /= RIN_X_CTRL_RD6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1392) <= '1' when (XC_WADDR6DOWNTO0_shadow /= V_X_CTRL_RD6DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(1393) <= '1' when (XC_WADDR6DOWNTO0_shadow(2 downto 0) /= RIN_W_S_CWP_intermed_1) else '0';
dfp_trap_vector(1394) <= '1' when (XC_WADDR6DOWNTO0_shadow /= R.X.CTRL.RD( 6 DOWNTO 0 )) else '0';
dfp_trap_vector(1395) <= '1' when (XC_WADDR6DOWNTO0_shadow /= "0000001") else '0';
dfp_trap_vector(1396) <= '1' when (XC_WADDR6DOWNTO0_shadow /= V_M_CTRL_RD6DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(1397) <= '1' when (XC_WADDR6DOWNTO0_shadow /= "0000001") else '0';
dfp_trap_vector(1398) <= '1' when (XC_WADDR6DOWNTO0_shadow /= R_E_CTRL_RD6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1399) <= '1' when (XC_WADDR6DOWNTO0_shadow /= "0000010") else '0';
dfp_trap_vector(1400) <= '1' when (XC_WADDR6DOWNTO0_shadow /= V_E_CTRL_RD6DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(1401) <= '1' when (XC_WADDR6DOWNTO0_shadow /= V_A_CTRL_RD6DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(1402) <= '1' when (XC_WADDR6DOWNTO0_shadow /= R_A_CTRL_RD6DOWNTO0_intermed_3) else '0';
dfp_trap_vector(1403) <= '1' when (XC_WADDR6DOWNTO0_shadow(2 downto 0) /= R.W.S.CWP) else '0';
dfp_trap_vector(1404) <= '1' when (XC_WADDR6DOWNTO0_shadow /= RIN_A_CTRL_RD6DOWNTO0_intermed_4) else '0';
dfp_trap_vector(1405) <= '1' when (XC_WADDR6DOWNTO0_shadow /= R_M_CTRL_RD6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1406) <= '1' when (XC_WADDR6DOWNTO0_shadow(2 downto 0) /= V_W_S_CWP_shadow_intermed_1) else '0';
dfp_trap_vector(1407) <= '1' when (V_W_S_ET_shadow /= '0') else '0';
dfp_trap_vector(1408) <= '1' when (V_W_S_ET_shadow /= RIN_W_S_ET_intermed_1) else '0';
dfp_trap_vector(1409) <= '1' when (V_W_S_ET_shadow /= R.W.S.ET) else '0';
dfp_trap_vector(1410) <= '1' when (V_W_S_CWP_shadow /= RIN_W_S_CWP_intermed_1) else '0';
dfp_trap_vector(1411) <= '1' when (V_W_S_CWP_shadow /= "001") else '0';
dfp_trap_vector(1412) <= '1' when (V_W_S_CWP_shadow /= R.W.S.CWP) else '0';
dfp_trap_vector(1413) <= '1' when (VP_ERROR_shadow /= '1') else '0';
dfp_trap_vector(1414) <= '1' when (VP_ERROR_shadow /= '0') else '0';
dfp_trap_vector(1415) <= '1' when (VP_ERROR_shadow /= RP.ERROR) else '0';
dfp_trap_vector(1416) <= '1' when (VP_ERROR_shadow /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(1417) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_D_PC_intermed_6) else '0';
dfp_trap_vector(1418) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1419) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= VIR_ADDR_shadow_intermed_1) else '0';
dfp_trap_vector(1420) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_A_CTRL_PC_intermed_5) else '0';
dfp_trap_vector(1421) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_A_CTRL_PC_intermed_4) else '0';
dfp_trap_vector(1422) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(1423) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_E_CTRL_PC_shadow_intermed_4) else '0';
dfp_trap_vector(1424) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(1425) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= XC_TRAP_ADDRESS_shadow_intermed_1) else '0';
dfp_trap_vector(1426) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_7) else '0';
dfp_trap_vector(1427) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(1428) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IR.ADDR) else '0';
dfp_trap_vector(1429) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(1430) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1431) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_M_CTRL_PC_intermed_2) else '0';
dfp_trap_vector(1432) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1433) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_X_CTRL_PC_intermed_1) else '0';
dfp_trap_vector(1434) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_E_CTRL_PC_intermed_3) else '0';
dfp_trap_vector(1435) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1436) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(1437) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_M_CTRL_PC_intermed_3) else '0';
dfp_trap_vector(1438) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(1439) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R.F.PC( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(1440) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(1441) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_X_CTRL_PC_shadow_intermed_2) else '0';
dfp_trap_vector(1442) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1443) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(1444) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(1445) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(1446) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_M_CTRL_PC_shadow_intermed_3) else '0';
dfp_trap_vector(1447) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(1448) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_A_CTRL_PC_shadow_intermed_5) else '0';
dfp_trap_vector(1449) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1450) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_D_PC_intermed_5) else '0';
dfp_trap_vector(1451) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_F_PC_intermed_1) else '0';
dfp_trap_vector(1452) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(1453) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_E_CTRL_PC_intermed_4) else '0';
dfp_trap_vector(1454) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_X_CTRL_PC_intermed_2) else '0';
dfp_trap_vector(1455) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R.F.PC) else '0';
dfp_trap_vector(1456) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_D_PC_shadow_intermed_6) else '0';
dfp_trap_vector(1457) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1458) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IRIN_ADDR_intermed_1) else '0';
dfp_trap_vector(1459) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_JUMP_ADDRESS_shadow_intermed_1) else '0';
dfp_trap_vector(1460) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= "000000000000000000000000000000") else '0';
dfp_trap_vector(1461) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(1462) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IR_ADDR31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1463) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_F_PC_shadow_intermed_1) else '0';
dfp_trap_vector(1464) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(1465) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(1466) <= '1' when (VDSU_TBUFCNT_shadow /= DSUR.TBUFCNT) else '0';
dfp_trap_vector(1467) <= '1' when (VDSU_TBUFCNT_shadow /= TBUFCNTX_shadow) else '0';
dfp_trap_vector(1468) <= '1' when (VDSU_TBUFCNT_shadow /= DSUIN_TBUFCNT_intermed_1) else '0';
dfp_trap_vector(1469) <= '1' when (V_W_EXCEPT_shadow /= R.W.EXCEPT) else '0';
dfp_trap_vector(1470) <= '1' when (V_W_EXCEPT_shadow /= XC_EXCEPTION_shadow) else '0';
dfp_trap_vector(1471) <= '1' when (V_W_EXCEPT_shadow /= '1') else '0';
dfp_trap_vector(1472) <= '1' when (V_W_EXCEPT_shadow /= RIN_W_EXCEPT_intermed_1) else '0';
dfp_trap_vector(1473) <= '1' when (V_W_EXCEPT_shadow /= '0') else '0';
dfp_trap_vector(1474) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1475) <= '1' when (V_W_RESULT_shadow /= RIN_X_RESULT_intermed_1) else '0';
dfp_trap_vector(1476) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(1477) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(1478) <= '1' when (V_W_RESULT_shadow /= R.W.RESULT) else '0';
dfp_trap_vector(1479) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1480) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(1481) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(1482) <= '1' when (V_W_RESULT_shadow /= V_X_DATA0_shadow_intermed_1) else '0';
dfp_trap_vector(1483) <= '1' when (V_W_RESULT_shadow /= R.X.RESULT) else '0';
dfp_trap_vector(1484) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1485) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1486) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1487) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1488) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1489) <= '1' when (V_W_RESULT_shadow /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(1490) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R.X.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(1491) <= '1' when (V_W_RESULT_shadow /= XC_RESULT_shadow) else '0';
dfp_trap_vector(1492) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(1493) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_D_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1494) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1495) <= '1' when (V_W_RESULT_shadow /= DCO_DATA0_intermed_1) else '0';
dfp_trap_vector(1496) <= '1' when (V_W_RESULT_shadow /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(1497) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(1498) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(1499) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(1500) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1501) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(1502) <= '1' when (V_W_RESULT_shadow /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(1503) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1504) <= '1' when (V_W_RESULT_shadow /= V_X_RESULT_shadow_intermed_1) else '0';
dfp_trap_vector(1505) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_X_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1506) <= '1' when (V_W_RESULT_shadow /= RIN_W_RESULT_intermed_1) else '0';
dfp_trap_vector(1507) <= '1' when (V_W_RESULT_shadow /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(1508) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(1509) <= '1' when (V_W_RESULT_shadow /= X"00000000") else '0';
dfp_trap_vector(1510) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(1511) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(1512) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(1513) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(1514) <= '1' when (V_W_RESULT_shadow /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(1515) <= '1' when (V_W_WA_shadow /= V_M_CTRL_RD7DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(1516) <= '1' when (V_W_WA_shadow /= V_E_CTRL_RD7DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(1517) <= '1' when (V_W_WA_shadow /= R_E_CTRL_RD7DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1518) <= '1' when (V_W_WA_shadow /= V_X_CTRL_RD7DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(1519) <= '1' when (V_W_WA_shadow /= R.X.CTRL.RD ( 7 DOWNTO 0 )) else '0';
dfp_trap_vector(1520) <= '1' when (V_W_WA_shadow /= V_A_CTRL_RD7DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(1521) <= '1' when (V_W_WA_shadow /= RIN_W_WA_intermed_1) else '0';
dfp_trap_vector(1522) <= '1' when (V_W_WA_shadow /= RIN_A_CTRL_RD7DOWNTO0_intermed_4) else '0';
dfp_trap_vector(1523) <= '1' when (V_W_WA_shadow /= R_M_CTRL_RD7DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1524) <= '1' when (V_W_WA_shadow /= R_A_CTRL_RD7DOWNTO0_intermed_3) else '0';
dfp_trap_vector(1525) <= '1' when (V_W_WA_shadow /= RIN_E_CTRL_RD7DOWNTO0_intermed_3) else '0';
dfp_trap_vector(1526) <= '1' when (V_W_WA_shadow /= RIN_X_CTRL_RD7DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1527) <= '1' when (V_W_WA_shadow /= RIN_M_CTRL_RD7DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1528) <= '1' when (V_W_WA_shadow /= R.W.WA) else '0';
dfp_trap_vector(1529) <= '1' when (V_W_WA_shadow /= XC_WADDR7DOWNTO0_shadow) else '0';
dfp_trap_vector(1530) <= '1' when (V_W_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_5) else '0';
dfp_trap_vector(1531) <= '1' when (V_W_WREG_shadow /= R.X.CTRL.WREG) else '0';
dfp_trap_vector(1532) <= '1' when (V_W_WREG_shadow /= R_A_CTRL_ANNUL_intermed_4) else '0';
dfp_trap_vector(1533) <= '1' when (V_W_WREG_shadow /= R.W.WREG) else '0';
dfp_trap_vector(1534) <= '1' when (V_W_WREG_shadow /= R_X_ANNUL_ALL_intermed_4) else '0';
dfp_trap_vector(1535) <= '1' when (V_W_WREG_shadow /= V_X_CTRL_WREG_shadow_intermed_1) else '0';
dfp_trap_vector(1536) <= '1' when (V_W_WREG_shadow /= RIN_X_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(1537) <= '1' when (V_W_WREG_shadow /= '1') else '0';
dfp_trap_vector(1538) <= '1' when (V_W_WREG_shadow /= '0') else '0';
dfp_trap_vector(1539) <= '1' when (V_W_WREG_shadow /= XC_WREG_shadow) else '0';
dfp_trap_vector(1540) <= '1' when (V_W_WREG_shadow /= RIN_M_CTRL_WREG_intermed_2) else '0';
dfp_trap_vector(1541) <= '1' when (V_W_WREG_shadow /= RIN_A_CTRL_WREG_intermed_4) else '0';
dfp_trap_vector(1542) <= '1' when (V_W_WREG_shadow /= V_A_CTRL_WREG_shadow_intermed_4) else '0';
dfp_trap_vector(1543) <= '1' when (V_W_WREG_shadow /= R_A_CTRL_WREG_intermed_3) else '0';
dfp_trap_vector(1544) <= '1' when (V_W_WREG_shadow /= RIN_W_WREG_intermed_1) else '0';
dfp_trap_vector(1545) <= '1' when (V_W_WREG_shadow /= V_X_ANNUL_ALL_shadow_intermed_4) else '0';
dfp_trap_vector(1546) <= '1' when (V_W_WREG_shadow /= R_M_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(1547) <= '1' when (V_W_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_5) else '0';
dfp_trap_vector(1548) <= '1' when (V_W_WREG_shadow /= V_M_CTRL_WREG_shadow_intermed_2) else '0';
dfp_trap_vector(1549) <= '1' when (V_W_WREG_shadow /= HOLDN) else '0';
dfp_trap_vector(1550) <= '1' when (V_W_WREG_shadow /= R_E_CTRL_WREG_intermed_2) else '0';
dfp_trap_vector(1551) <= '1' when (V_W_WREG_shadow /= V_A_CTRL_ANNUL_shadow_intermed_4) else '0';
dfp_trap_vector(1552) <= '1' when (V_W_WREG_shadow /= RIN_E_CTRL_WREG_intermed_3) else '0';
dfp_trap_vector(1553) <= '1' when (V_W_WREG_shadow /= V_E_CTRL_WREG_shadow_intermed_3) else '0';
dfp_trap_vector(1554) <= '1' when (V_W_S_SVT_shadow /= R.W.S.SVT) else '0';
dfp_trap_vector(1555) <= '1' when (V_W_S_SVT_shadow /= '0') else '0';
dfp_trap_vector(1556) <= '1' when (V_W_S_SVT_shadow /= RIN_W_S_SVT_intermed_1) else '0';
dfp_trap_vector(1557) <= '1' when (V_W_S_DWT_shadow /= RIN_W_S_DWT_intermed_1) else '0';
dfp_trap_vector(1558) <= '1' when (V_W_S_DWT_shadow /= R.W.S.DWT) else '0';
dfp_trap_vector(1559) <= '1' when (V_W_S_DWT_shadow /= '0') else '0';
dfp_trap_vector(1560) <= '1' when (V_W_S_EF_shadow /= '0') else '0';
dfp_trap_vector(1561) <= '1' when (V_W_S_EF_shadow /= R.W.S.EF) else '0';
dfp_trap_vector(1562) <= '1' when (V_W_S_EF_shadow /= RIN_W_S_EF_intermed_1) else '0';
dfp_trap_vector(1563) <= '1' when (V_X_CTRL_shadow /= RIN_E_CTRL_intermed_2) else '0';
dfp_trap_vector(1564) <= '1' when (V_X_CTRL_shadow /= R_E_CTRL_intermed_1) else '0';
dfp_trap_vector(1565) <= '1' when (V_X_CTRL_shadow /= RIN_X_CTRL_intermed_1) else '0';
dfp_trap_vector(1566) <= '1' when (V_X_CTRL_shadow /= R.M.CTRL) else '0';
dfp_trap_vector(1567) <= '1' when (V_X_CTRL_shadow /= RIN_M_CTRL_intermed_1) else '0';
dfp_trap_vector(1568) <= '1' when (V_X_CTRL_shadow /= V_E_CTRL_shadow_intermed_2) else '0';
dfp_trap_vector(1569) <= '1' when (V_X_CTRL_shadow /= RIN_A_CTRL_intermed_3) else '0';
dfp_trap_vector(1570) <= '1' when (V_X_CTRL_shadow /= R.X.CTRL) else '0';
dfp_trap_vector(1571) <= '1' when (V_X_CTRL_shadow /= V_M_CTRL_shadow_intermed_1) else '0';
dfp_trap_vector(1572) <= '1' when (V_X_CTRL_shadow /= V_A_CTRL_shadow_intermed_3) else '0';
dfp_trap_vector(1573) <= '1' when (V_X_CTRL_shadow /= R_A_CTRL_intermed_2) else '0';
dfp_trap_vector(1574) <= '1' when (V_X_DCI_shadow /= V_M_DCI_shadow_intermed_1) else '0';
dfp_trap_vector(1575) <= '1' when (V_X_DCI_shadow /= RIN_M_DCI_intermed_1) else '0';
dfp_trap_vector(1576) <= '1' when (V_X_DCI_shadow /= RIN_X_DCI_intermed_1) else '0';
dfp_trap_vector(1577) <= '1' when (V_X_DCI_shadow /= R.M.DCI) else '0';
dfp_trap_vector(1578) <= '1' when (V_X_DCI_shadow /= R.X.DCI) else '0';
dfp_trap_vector(1579) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0';
dfp_trap_vector(1580) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_A_CTRL_ANNUL_intermed_4) else '0';
dfp_trap_vector(1581) <= '1' when (V_X_CTRL_RETT_shadow /= R_A_CTRL_ANNUL_intermed_3) else '0';
dfp_trap_vector(1582) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_M_CTRL_RETT_intermed_1) else '0';
dfp_trap_vector(1583) <= '1' when (V_X_CTRL_RETT_shadow /= V_M_CTRL_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(1584) <= '1' when (V_X_CTRL_RETT_shadow /= R_X_ANNUL_ALL_intermed_3) else '0';
dfp_trap_vector(1585) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.ANNUL) else '0';
dfp_trap_vector(1586) <= '1' when (V_X_CTRL_RETT_shadow /= '1') else '0';
dfp_trap_vector(1587) <= '1' when (V_X_CTRL_RETT_shadow /= '0') else '0';
dfp_trap_vector(1588) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_M_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1589) <= '1' when (V_X_CTRL_RETT_shadow /= V_E_CTRL_RETT_shadow_intermed_2) else '0';
dfp_trap_vector(1590) <= '1' when (V_X_CTRL_RETT_shadow /= V_A_CTRL_RETT_shadow_intermed_3) else '0';
dfp_trap_vector(1591) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_A_CTRL_RETT_intermed_3) else '0';
dfp_trap_vector(1592) <= '1' when (V_X_CTRL_RETT_shadow /= V_X_ANNUL_ALL_shadow_intermed_3) else '0';
dfp_trap_vector(1593) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_E_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1594) <= '1' when (V_X_CTRL_RETT_shadow /= R_E_CTRL_RETT_intermed_1) else '0';
dfp_trap_vector(1595) <= '1' when (V_X_CTRL_RETT_shadow /= R.X.CTRL.RETT) else '0';
dfp_trap_vector(1596) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_X_ANNUL_ALL_intermed_4) else '0';
dfp_trap_vector(1597) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_E_CTRL_RETT_intermed_2) else '0';
dfp_trap_vector(1598) <= '1' when (V_X_CTRL_RETT_shadow /= V_E_CTRL_ANNUL_shadow_intermed_2) else '0';
dfp_trap_vector(1599) <= '1' when (V_X_CTRL_RETT_shadow /= V_A_CTRL_ANNUL_shadow_intermed_3) else '0';
dfp_trap_vector(1600) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_X_CTRL_RETT_intermed_1) else '0';
dfp_trap_vector(1601) <= '1' when (V_X_CTRL_RETT_shadow /= V_M_CTRL_RETT_shadow_intermed_1) else '0';
dfp_trap_vector(1602) <= '1' when (V_X_CTRL_RETT_shadow /= R_A_CTRL_RETT_intermed_2) else '0';
dfp_trap_vector(1603) <= '1' when (V_X_CTRL_RETT_shadow /= R_E_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1604) <= '1' when (V_X_MAC_shadow /= V_E_MAC_shadow_intermed_2) else '0';
dfp_trap_vector(1605) <= '1' when (V_X_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(1606) <= '1' when (V_X_MAC_shadow /= RIN_E_MAC_intermed_2) else '0';
dfp_trap_vector(1607) <= '1' when (V_X_MAC_shadow /= R_E_MAC_intermed_1) else '0';
dfp_trap_vector(1608) <= '1' when (V_X_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(1609) <= '1' when (V_X_MAC_shadow /= V_M_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(1610) <= '1' when (V_X_MAC_shadow /= RIN_X_MAC_intermed_1) else '0';
dfp_trap_vector(1611) <= '1' when (V_X_MAC_shadow /= R.X.MAC) else '0';
dfp_trap_vector(1612) <= '1' when (V_X_LADDR_shadow /= V_M_RESULT1DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(1613) <= '1' when (V_X_LADDR_shadow /= RIN_X_LADDR_intermed_1) else '0';
dfp_trap_vector(1614) <= '1' when (V_X_LADDR_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0';
dfp_trap_vector(1615) <= '1' when (V_X_LADDR_shadow /= RIN_M_RESULT1DOWNTO0_intermed_2) else '0';
dfp_trap_vector(1616) <= '1' when (V_X_LADDR_shadow /= V_M_RESULT1DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(1617) <= '1' when (V_X_LADDR_shadow /= R.X.LADDR) else '0';
dfp_trap_vector(1618) <= '1' when (V_X_LADDR_shadow /= R_M_RESULT1DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1619) <= '1' when (V_X_LADDR_shadow /= RIN_M_RESULT1DOWNTO0_intermed_1) else '0';
dfp_trap_vector(1620) <= '1' when (V_X_CTRL_ANNUL_shadow /= RIN_A_CTRL_ANNUL_intermed_3) else '0';
dfp_trap_vector(1621) <= '1' when (V_X_CTRL_ANNUL_shadow /= R.X.CTRL.ANNUL) else '0';
dfp_trap_vector(1622) <= '1' when (V_X_CTRL_ANNUL_shadow /= R_A_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1623) <= '1' when (V_X_CTRL_ANNUL_shadow /= V_M_CTRL_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(1624) <= '1' when (V_X_CTRL_ANNUL_shadow /= R_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1625) <= '1' when (V_X_CTRL_ANNUL_shadow /= R.M.CTRL.ANNUL) else '0';
dfp_trap_vector(1626) <= '1' when (V_X_CTRL_ANNUL_shadow /= RIN_X_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1627) <= '1' when (V_X_CTRL_ANNUL_shadow /= '1') else '0';
dfp_trap_vector(1628) <= '1' when (V_X_CTRL_ANNUL_shadow /= '0') else '0';
dfp_trap_vector(1629) <= '1' when (V_X_CTRL_ANNUL_shadow /= RIN_M_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1630) <= '1' when (V_X_CTRL_ANNUL_shadow /= V_X_ANNUL_ALL_shadow_intermed_1) else '0';
dfp_trap_vector(1631) <= '1' when (V_X_CTRL_ANNUL_shadow /= RIN_E_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1632) <= '1' when (V_X_CTRL_ANNUL_shadow /= RIN_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(1633) <= '1' when (V_X_CTRL_ANNUL_shadow /= V_E_CTRL_ANNUL_shadow_intermed_2) else '0';
dfp_trap_vector(1634) <= '1' when (V_X_CTRL_ANNUL_shadow /= V_A_CTRL_ANNUL_shadow_intermed_3) else '0';
dfp_trap_vector(1635) <= '1' when (V_X_CTRL_ANNUL_shadow /= R_E_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1636) <= '1' when (V_X_CTRL_TT_shadow /= V_E_CTRL_TT_shadow_intermed_3) else '0';
dfp_trap_vector(1637) <= '1' when (V_X_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_4) else '0';
dfp_trap_vector(1638) <= '1' when (V_X_CTRL_TT_shadow /= R_A_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(1639) <= '1' when (V_X_CTRL_TT_shadow /= R_M_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1640) <= '1' when (V_X_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(1641) <= '1' when (V_X_CTRL_TT_shadow /= R_E_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(1642) <= '1' when (V_X_CTRL_TT_shadow /= R.X.CTRL.TT) else '0';
dfp_trap_vector(1643) <= '1' when (V_X_CTRL_TT_shadow /= RIN_M_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(1644) <= '1' when (V_X_CTRL_TT_shadow /= RIN_E_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(1645) <= '1' when (V_X_CTRL_TT_shadow /= V_M_CTRL_TT_shadow_intermed_2) else '0';
dfp_trap_vector(1646) <= '1' when (V_X_CTRL_TT_shadow /= V_A_CTRL_TT_shadow_intermed_4) else '0';
dfp_trap_vector(1647) <= '1' when (V_X_CTRL_TT_shadow /= RIN_X_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1648) <= '1' when (V_X_DATA0_shadow /= R.X.DATA ( 0 )) else '0';
dfp_trap_vector(1649) <= '1' when (V_X_DATA0_shadow /= DCO.DATA ( 0 )) else '0';
dfp_trap_vector(1650) <= '1' when (V_X_DATA0_shadow /= V_X_DATA0_shadow_intermed_2) else '0';
dfp_trap_vector(1651) <= '1' when (V_X_DATA0_shadow /= RIN_X_DATA0_intermed_1) else '0';
dfp_trap_vector(1652) <= '1' when (V_X_DATA0_shadow /= R_X_DATA0_intermed_1) else '0';
dfp_trap_vector(1653) <= '1' when (V_X_DATA0_shadow /= RIN_X_DATA0_intermed_2) else '0';
dfp_trap_vector(1654) <= '1' when (V_X_DATA1_shadow /= DCO.DATA ( 1 )) else '0';
dfp_trap_vector(1655) <= '1' when (V_X_DATA1_shadow /= R.X.DATA ( 1 )) else '0';
dfp_trap_vector(1656) <= '1' when (V_X_DATA1_shadow /= V_X_DATA1_shadow_intermed_2) else '0';
dfp_trap_vector(1657) <= '1' when (V_X_DATA1_shadow /= RIN_X_DATA1_intermed_1) else '0';
dfp_trap_vector(1658) <= '1' when (V_X_DATA1_shadow /= R_X_DATA1_intermed_1) else '0';
dfp_trap_vector(1659) <= '1' when (V_X_DATA1_shadow /= RIN_X_DATA1_intermed_2) else '0';
dfp_trap_vector(1660) <= '1' when (V_X_SET_shadow /= RIN_X_SET_intermed_1) else '0';
dfp_trap_vector(1661) <= '1' when (V_X_SET_shadow /= DCO.SET ( 0 DOWNTO 0 )) else '0';
dfp_trap_vector(1662) <= '1' when (V_X_SET_shadow /= R.X.SET) else '0';
dfp_trap_vector(1663) <= '1' when (V_X_DCI_SIZE_shadow /= R.X.DCI.SIZE) else '0';
dfp_trap_vector(1664) <= '1' when (V_X_DCI_SIZE_shadow /= V_M_DCI_SIZE_shadow_intermed_2) else '0';
dfp_trap_vector(1665) <= '1' when (V_X_DCI_SIZE_shadow /= R_M_DCI_SIZE_intermed_1) else '0';
dfp_trap_vector(1666) <= '1' when (V_X_DCI_SIZE_shadow /= RIN_X_DCI_SIZE_intermed_1) else '0';
dfp_trap_vector(1667) <= '1' when (V_X_DCI_SIZE_shadow /= RIN_M_DCI_SIZE_intermed_2) else '0';
dfp_trap_vector(1668) <= '1' when (V_X_DCI_SIGNED_shadow /= RIN_M_DCI_SIGNED_intermed_2) else '0';
dfp_trap_vector(1669) <= '1' when (V_X_DCI_SIGNED_shadow /= R_M_DCI_SIGNED_intermed_1) else '0';
dfp_trap_vector(1670) <= '1' when (V_X_DCI_SIGNED_shadow /= RIN_X_DCI_SIGNED_intermed_1) else '0';
dfp_trap_vector(1671) <= '1' when (V_X_DCI_SIGNED_shadow /= V_M_DCI_SIGNED_shadow_intermed_2) else '0';
dfp_trap_vector(1672) <= '1' when (V_X_DCI_SIGNED_shadow /= R.X.DCI.SIGNED) else '0';
dfp_trap_vector(1673) <= '1' when (V_X_MEXC_shadow /= R.X.MEXC) else '0';
dfp_trap_vector(1674) <= '1' when (V_X_MEXC_shadow /= RIN_X_MEXC_intermed_1) else '0';
dfp_trap_vector(1675) <= '1' when (V_X_MEXC_shadow /= DCO.MEXC) else '0';
dfp_trap_vector(1676) <= '1' when (V_X_ICC_shadow /= R.X.ICC) else '0';
dfp_trap_vector(1677) <= '1' when (V_X_ICC_shadow /= RIN_X_ICC_intermed_1) else '0';
dfp_trap_vector(1678) <= '1' when (V_X_ICC_shadow /= ME_ICC_shadow) else '0';
dfp_trap_vector(1679) <= '1' when (V_X_CTRL_WICC_shadow /= R_A_CTRL_WICC_intermed_2) else '0';
dfp_trap_vector(1680) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_A_CTRL_ANNUL_intermed_4) else '0';
dfp_trap_vector(1681) <= '1' when (V_X_CTRL_WICC_shadow /= V_E_CTRL_WICC_shadow_intermed_2) else '0';
dfp_trap_vector(1682) <= '1' when (V_X_CTRL_WICC_shadow /= R.M.CTRL.WICC) else '0';
dfp_trap_vector(1683) <= '1' when (V_X_CTRL_WICC_shadow /= V_A_CTRL_WICC_shadow_intermed_3) else '0';
dfp_trap_vector(1684) <= '1' when (V_X_CTRL_WICC_shadow /= R_A_CTRL_ANNUL_intermed_3) else '0';
dfp_trap_vector(1685) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_X_CTRL_WICC_intermed_1) else '0';
dfp_trap_vector(1686) <= '1' when (V_X_CTRL_WICC_shadow /= R_X_ANNUL_ALL_intermed_3) else '0';
dfp_trap_vector(1687) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_E_CTRL_WICC_intermed_2) else '0';
dfp_trap_vector(1688) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_M_CTRL_WICC_intermed_1) else '0';
dfp_trap_vector(1689) <= '1' when (V_X_CTRL_WICC_shadow /= R.X.CTRL.WICC) else '0';
dfp_trap_vector(1690) <= '1' when (V_X_CTRL_WICC_shadow /= '1') else '0';
dfp_trap_vector(1691) <= '1' when (V_X_CTRL_WICC_shadow /= '0') else '0';
dfp_trap_vector(1692) <= '1' when (V_X_CTRL_WICC_shadow /= R_E_CTRL_WICC_intermed_1) else '0';
dfp_trap_vector(1693) <= '1' when (V_X_CTRL_WICC_shadow /= V_X_ANNUL_ALL_shadow_intermed_3) else '0';
dfp_trap_vector(1694) <= '1' when (V_X_CTRL_WICC_shadow /= V_M_CTRL_WICC_shadow_intermed_1) else '0';
dfp_trap_vector(1695) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_X_ANNUL_ALL_intermed_4) else '0';
dfp_trap_vector(1696) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_A_CTRL_WICC_intermed_3) else '0';
dfp_trap_vector(1697) <= '1' when (V_X_CTRL_WICC_shadow /= V_A_CTRL_ANNUL_shadow_intermed_3) else '0';
dfp_trap_vector(1698) <= '1' when (V_M_CTRL_shadow /= RIN_E_CTRL_intermed_1) else '0';
dfp_trap_vector(1699) <= '1' when (V_M_CTRL_shadow /= R.E.CTRL) else '0';
dfp_trap_vector(1700) <= '1' when (V_M_CTRL_shadow /= R.M.CTRL) else '0';
dfp_trap_vector(1701) <= '1' when (V_M_CTRL_shadow /= RIN_M_CTRL_intermed_1) else '0';
dfp_trap_vector(1702) <= '1' when (V_M_CTRL_shadow /= V_E_CTRL_shadow_intermed_1) else '0';
dfp_trap_vector(1703) <= '1' when (V_M_CTRL_shadow /= RIN_A_CTRL_intermed_2) else '0';
dfp_trap_vector(1704) <= '1' when (V_M_CTRL_shadow /= V_A_CTRL_shadow_intermed_2) else '0';
dfp_trap_vector(1705) <= '1' when (V_M_CTRL_shadow /= R_A_CTRL_intermed_1) else '0';
dfp_trap_vector(1706) <= '1' when (V_M_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0';
dfp_trap_vector(1707) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_A_CTRL_ANNUL_intermed_3) else '0';
dfp_trap_vector(1708) <= '1' when (V_M_CTRL_RETT_shadow /= R_A_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1709) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_M_CTRL_RETT_intermed_1) else '0';
dfp_trap_vector(1710) <= '1' when (V_M_CTRL_RETT_shadow /= R_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(1711) <= '1' when (V_M_CTRL_RETT_shadow /= '1') else '0';
dfp_trap_vector(1712) <= '1' when (V_M_CTRL_RETT_shadow /= '0') else '0';
dfp_trap_vector(1713) <= '1' when (V_M_CTRL_RETT_shadow /= V_E_CTRL_RETT_shadow_intermed_1) else '0';
dfp_trap_vector(1714) <= '1' when (V_M_CTRL_RETT_shadow /= V_A_CTRL_RETT_shadow_intermed_2) else '0';
dfp_trap_vector(1715) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_A_CTRL_RETT_intermed_2) else '0';
dfp_trap_vector(1716) <= '1' when (V_M_CTRL_RETT_shadow /= V_X_ANNUL_ALL_shadow_intermed_2) else '0';
dfp_trap_vector(1717) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_E_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1718) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0';
dfp_trap_vector(1719) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_X_ANNUL_ALL_intermed_3) else '0';
dfp_trap_vector(1720) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_E_CTRL_RETT_intermed_1) else '0';
dfp_trap_vector(1721) <= '1' when (V_M_CTRL_RETT_shadow /= V_E_CTRL_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(1722) <= '1' when (V_M_CTRL_RETT_shadow /= V_A_CTRL_ANNUL_shadow_intermed_2) else '0';
dfp_trap_vector(1723) <= '1' when (V_M_CTRL_RETT_shadow /= R_A_CTRL_RETT_intermed_1) else '0';
dfp_trap_vector(1724) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.ANNUL) else '0';
dfp_trap_vector(1725) <= '1' when (V_M_CTRL_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_3) else '0';
dfp_trap_vector(1726) <= '1' when (V_M_CTRL_WREG_shadow /= R_A_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1727) <= '1' when (V_M_CTRL_WREG_shadow /= R_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(1728) <= '1' when (V_M_CTRL_WREG_shadow /= '1') else '0';
dfp_trap_vector(1729) <= '1' when (V_M_CTRL_WREG_shadow /= '0') else '0';
dfp_trap_vector(1730) <= '1' when (V_M_CTRL_WREG_shadow /= RIN_M_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(1731) <= '1' when (V_M_CTRL_WREG_shadow /= RIN_A_CTRL_WREG_intermed_2) else '0';
dfp_trap_vector(1732) <= '1' when (V_M_CTRL_WREG_shadow /= V_A_CTRL_WREG_shadow_intermed_2) else '0';
dfp_trap_vector(1733) <= '1' when (V_M_CTRL_WREG_shadow /= R_A_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(1734) <= '1' when (V_M_CTRL_WREG_shadow /= V_X_ANNUL_ALL_shadow_intermed_2) else '0';
dfp_trap_vector(1735) <= '1' when (V_M_CTRL_WREG_shadow /= R.M.CTRL.WREG) else '0';
dfp_trap_vector(1736) <= '1' when (V_M_CTRL_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_3) else '0';
dfp_trap_vector(1737) <= '1' when (V_M_CTRL_WREG_shadow /= R.E.CTRL.WREG) else '0';
dfp_trap_vector(1738) <= '1' when (V_M_CTRL_WREG_shadow /= V_A_CTRL_ANNUL_shadow_intermed_2) else '0';
dfp_trap_vector(1739) <= '1' when (V_M_CTRL_WREG_shadow /= RIN_E_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(1740) <= '1' when (V_M_CTRL_WREG_shadow /= V_E_CTRL_WREG_shadow_intermed_1) else '0';
dfp_trap_vector(1741) <= '1' when (V_E_CWP_shadow /= RIN_E_CWP_intermed_1) else '0';
dfp_trap_vector(1742) <= '1' when (V_E_CWP_shadow /= V_A_CWP_shadow_intermed_1) else '0';
dfp_trap_vector(1743) <= '1' when (V_E_CWP_shadow /= RIN_D_CWP_intermed_2) else '0';
dfp_trap_vector(1744) <= '1' when (V_E_CWP_shadow /= R.E.CWP) else '0';
dfp_trap_vector(1745) <= '1' when (V_E_CWP_shadow /= RIN_A_CWP_intermed_1) else '0';
dfp_trap_vector(1746) <= '1' when (V_E_CWP_shadow /= V_D_CWP_shadow_intermed_2) else '0';
dfp_trap_vector(1747) <= '1' when (V_E_CWP_shadow /= R_D_CWP_intermed_1) else '0';
dfp_trap_vector(1748) <= '1' when (V_E_CWP_shadow /= R.A.CWP) else '0';
dfp_trap_vector(1749) <= '1' when (V_M_SU_shadow /= R.M.SU) else '0';
dfp_trap_vector(1750) <= '1' when (V_M_SU_shadow /= R_A_SU_intermed_1) else '0';
dfp_trap_vector(1751) <= '1' when (V_M_SU_shadow /= RIN_A_SU_intermed_2) else '0';
dfp_trap_vector(1752) <= '1' when (V_M_SU_shadow /= V_E_SU_shadow_intermed_1) else '0';
dfp_trap_vector(1753) <= '1' when (V_M_SU_shadow /= R.E.SU) else '0';
dfp_trap_vector(1754) <= '1' when (V_M_SU_shadow /= V_A_SU_shadow_intermed_2) else '0';
dfp_trap_vector(1755) <= '1' when (V_M_SU_shadow /= RIN_M_SU_intermed_1) else '0';
dfp_trap_vector(1756) <= '1' when (V_M_SU_shadow /= RIN_E_SU_intermed_1) else '0';
dfp_trap_vector(1757) <= '1' when (V_M_MUL_shadow /= RIN_M_MUL_intermed_1) else '0';
dfp_trap_vector(1758) <= '1' when (V_M_MUL_shadow /= '0') else '0';
dfp_trap_vector(1759) <= '1' when (V_M_MUL_shadow /= R.M.MUL) else '0';
dfp_trap_vector(1760) <= '1' when (V_M_NALIGN_shadow /= '1') else '0';
dfp_trap_vector(1761) <= '1' when (V_M_NALIGN_shadow /= '0') else '0';
dfp_trap_vector(1762) <= '1' when (V_M_NALIGN_shadow /= RIN_M_NALIGN_intermed_1) else '0';
dfp_trap_vector(1763) <= '1' when (V_M_NALIGN_shadow /= R.M.NALIGN) else '0';
dfp_trap_vector(1764) <= '1' when (EX_ADD_RES3_shadow /= EX_OP23_shadow) else '0';
dfp_trap_vector(1765) <= '1' when (EX_ADD_RES3_shadow /= V_X_DATA03_shadow_intermed_2) else '0';
dfp_trap_vector(1766) <= '1' when (EX_ADD_RES3_shadow /= V_X_DATA03_shadow_intermed_1) else '0';
dfp_trap_vector(1767) <= '1' when (EX_ADD_RES3_shadow /= DCO_DATA03_intermed_1) else '0';
dfp_trap_vector(1768) <= '1' when (EX_ADD_RES3_shadow /= R.E.OP2( 3 )) else '0';
dfp_trap_vector(1769) <= '1' when (EX_ADD_RES3_shadow /= RIN_X_DATA03_intermed_1) else '0';
dfp_trap_vector(1770) <= '1' when (EX_ADD_RES3_shadow /= R_X_DATA03_intermed_1) else '0';
dfp_trap_vector(1771) <= '1' when (EX_ADD_RES3_shadow /= RIN_X_DATA03_intermed_2) else '0';
dfp_trap_vector(1772) <= '1' when (EX_ADD_RES3_shadow /= RIN_E_OP23_intermed_1) else '0';
dfp_trap_vector(1773) <= '1' when (EX_ADD_RES3_shadow /= RIN_E_OP13_intermed_1) else '0';
dfp_trap_vector(1774) <= '1' when (EX_ADD_RES3_shadow /= EX_FORCE_A2_shadow) else '0';
dfp_trap_vector(1775) <= '1' when (EX_ADD_RES3_shadow /= R.X.DATA ( 0 )( 3 )) else '0';
dfp_trap_vector(1776) <= '1' when (EX_ADD_RES3_shadow /= EX_OP13_shadow) else '0';
dfp_trap_vector(1777) <= '1' when (EX_ADD_RES3_shadow /= V_E_OP23_shadow_intermed_1) else '0';
dfp_trap_vector(1778) <= '1' when (EX_ADD_RES3_shadow /= R.E.OP1( 3 )) else '0';
dfp_trap_vector(1779) <= '1' when (EX_ADD_RES3_shadow /= V_E_OP13_shadow_intermed_1) else '0';
dfp_trap_vector(1780) <= '1' when (V_M_CTRL_ANNUL_shadow /= RIN_A_CTRL_ANNUL_intermed_3) else '0';
dfp_trap_vector(1781) <= '1' when (V_M_CTRL_ANNUL_shadow /= R_A_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1782) <= '1' when (V_M_CTRL_ANNUL_shadow /= R.X.ANNUL_ALL) else '0';
dfp_trap_vector(1783) <= '1' when (V_M_CTRL_ANNUL_shadow /= R.M.CTRL.ANNUL) else '0';
dfp_trap_vector(1784) <= '1' when (V_M_CTRL_ANNUL_shadow /= '1') else '0';
dfp_trap_vector(1785) <= '1' when (V_M_CTRL_ANNUL_shadow /= '0') else '0';
dfp_trap_vector(1786) <= '1' when (V_M_CTRL_ANNUL_shadow /= RIN_M_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1787) <= '1' when (V_M_CTRL_ANNUL_shadow /= V_X_ANNUL_ALL_shadow) else '0';
dfp_trap_vector(1788) <= '1' when (V_M_CTRL_ANNUL_shadow /= RIN_E_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1789) <= '1' when (V_M_CTRL_ANNUL_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1790) <= '1' when (V_M_CTRL_ANNUL_shadow /= V_E_CTRL_ANNUL_shadow_intermed_2) else '0';
dfp_trap_vector(1791) <= '1' when (V_M_CTRL_ANNUL_shadow /= V_A_CTRL_ANNUL_shadow_intermed_3) else '0';
dfp_trap_vector(1792) <= '1' when (V_M_CTRL_ANNUL_shadow /= R_E_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1793) <= '1' when (V_M_CTRL_WICC_shadow /= R_A_CTRL_WICC_intermed_1) else '0';
dfp_trap_vector(1794) <= '1' when (V_M_CTRL_WICC_shadow /= RIN_A_CTRL_ANNUL_intermed_3) else '0';
dfp_trap_vector(1795) <= '1' when (V_M_CTRL_WICC_shadow /= V_E_CTRL_WICC_shadow_intermed_1) else '0';
dfp_trap_vector(1796) <= '1' when (V_M_CTRL_WICC_shadow /= R.M.CTRL.WICC) else '0';
dfp_trap_vector(1797) <= '1' when (V_M_CTRL_WICC_shadow /= V_A_CTRL_WICC_shadow_intermed_2) else '0';
dfp_trap_vector(1798) <= '1' when (V_M_CTRL_WICC_shadow /= R_A_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1799) <= '1' when (V_M_CTRL_WICC_shadow /= R_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(1800) <= '1' when (V_M_CTRL_WICC_shadow /= RIN_E_CTRL_WICC_intermed_1) else '0';
dfp_trap_vector(1801) <= '1' when (V_M_CTRL_WICC_shadow /= RIN_M_CTRL_WICC_intermed_1) else '0';
dfp_trap_vector(1802) <= '1' when (V_M_CTRL_WICC_shadow /= '1') else '0';
dfp_trap_vector(1803) <= '1' when (V_M_CTRL_WICC_shadow /= '0') else '0';
dfp_trap_vector(1804) <= '1' when (V_M_CTRL_WICC_shadow /= R.E.CTRL.WICC) else '0';
dfp_trap_vector(1805) <= '1' when (V_M_CTRL_WICC_shadow /= V_X_ANNUL_ALL_shadow_intermed_2) else '0';
dfp_trap_vector(1806) <= '1' when (V_M_CTRL_WICC_shadow /= RIN_X_ANNUL_ALL_intermed_3) else '0';
dfp_trap_vector(1807) <= '1' when (V_M_CTRL_WICC_shadow /= RIN_A_CTRL_WICC_intermed_2) else '0';
dfp_trap_vector(1808) <= '1' when (V_M_CTRL_WICC_shadow /= V_A_CTRL_ANNUL_shadow_intermed_2) else '0';
dfp_trap_vector(1809) <= '1' when (V_M_MAC_shadow /= V_E_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(1810) <= '1' when (V_M_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(1811) <= '1' when (V_M_MAC_shadow /= RIN_E_MAC_intermed_1) else '0';
dfp_trap_vector(1812) <= '1' when (V_M_MAC_shadow /= R.E.MAC) else '0';
dfp_trap_vector(1813) <= '1' when (V_M_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(1814) <= '1' when (V_M_CTRL_LD_shadow /= R_A_CTRL_LD_intermed_2) else '0';
dfp_trap_vector(1815) <= '1' when (V_M_CTRL_LD_shadow /= RIN_A_CTRL_LD_intermed_3) else '0';
dfp_trap_vector(1816) <= '1' when (V_M_CTRL_LD_shadow /= V_E_CTRL_LD_shadow_intermed_2) else '0';
dfp_trap_vector(1817) <= '1' when (V_M_CTRL_LD_shadow /= '1') else '0';
dfp_trap_vector(1818) <= '1' when (V_M_CTRL_LD_shadow /= R_E_CTRL_LD_intermed_1) else '0';
dfp_trap_vector(1819) <= '1' when (V_M_CTRL_LD_shadow /= R.M.CTRL.LD) else '0';
dfp_trap_vector(1820) <= '1' when (V_M_CTRL_LD_shadow /= RIN_E_CTRL_LD_intermed_2) else '0';
dfp_trap_vector(1821) <= '1' when (V_M_CTRL_LD_shadow /= RIN_M_CTRL_LD_intermed_1) else '0';
dfp_trap_vector(1822) <= '1' when (V_M_CTRL_LD_shadow /= V_A_CTRL_LD_shadow_intermed_3) else '0';
dfp_trap_vector(1823) <= '1' when (V_E_CTRL_shadow /= RIN_E_CTRL_intermed_1) else '0';
dfp_trap_vector(1824) <= '1' when (V_E_CTRL_shadow /= R.E.CTRL) else '0';
dfp_trap_vector(1825) <= '1' when (V_E_CTRL_shadow /= RIN_A_CTRL_intermed_1) else '0';
dfp_trap_vector(1826) <= '1' when (V_E_CTRL_shadow /= V_A_CTRL_shadow_intermed_1) else '0';
dfp_trap_vector(1827) <= '1' when (V_E_CTRL_shadow /= R.A.CTRL) else '0';
dfp_trap_vector(1828) <= '1' when (V_E_JMPL_shadow /= RIN_E_JMPL_intermed_1) else '0';
dfp_trap_vector(1829) <= '1' when (V_E_JMPL_shadow /= R.A.JMPL) else '0';
dfp_trap_vector(1830) <= '1' when (V_E_JMPL_shadow /= RIN_A_JMPL_intermed_1) else '0';
dfp_trap_vector(1831) <= '1' when (V_E_JMPL_shadow /= R.E.JMPL) else '0';
dfp_trap_vector(1832) <= '1' when (V_E_JMPL_shadow /= V_A_JMPL_shadow_intermed_1) else '0';
dfp_trap_vector(1833) <= '1' when (V_E_CTRL_ANNUL_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1834) <= '1' when (V_E_CTRL_ANNUL_shadow /= R.A.CTRL.ANNUL) else '0';
dfp_trap_vector(1835) <= '1' when (V_E_CTRL_ANNUL_shadow /= R_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1836) <= '1' when (V_E_CTRL_ANNUL_shadow /= '1') else '0';
dfp_trap_vector(1837) <= '1' when (V_E_CTRL_ANNUL_shadow /= '0') else '0';
dfp_trap_vector(1838) <= '1' when (V_E_CTRL_ANNUL_shadow /= V_X_ANNUL_ALL_shadow_intermed_1) else '0';
dfp_trap_vector(1839) <= '1' when (V_E_CTRL_ANNUL_shadow /= RIN_E_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1840) <= '1' when (V_E_CTRL_ANNUL_shadow /= RIN_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(1841) <= '1' when (V_E_CTRL_ANNUL_shadow /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(1842) <= '1' when (V_E_CTRL_ANNUL_shadow /= R.E.CTRL.ANNUL) else '0';
dfp_trap_vector(1843) <= '1' when (V_E_CTRL_RETT_shadow /= RIN_A_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1844) <= '1' when (V_E_CTRL_RETT_shadow /= R_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1845) <= '1' when (V_E_CTRL_RETT_shadow /= R_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1846) <= '1' when (V_E_CTRL_RETT_shadow /= '1') else '0';
dfp_trap_vector(1847) <= '1' when (V_E_CTRL_RETT_shadow /= '0') else '0';
dfp_trap_vector(1848) <= '1' when (V_E_CTRL_RETT_shadow /= V_A_CTRL_RETT_shadow_intermed_1) else '0';
dfp_trap_vector(1849) <= '1' when (V_E_CTRL_RETT_shadow /= RIN_A_CTRL_RETT_intermed_1) else '0';
dfp_trap_vector(1850) <= '1' when (V_E_CTRL_RETT_shadow /= V_X_ANNUL_ALL_shadow_intermed_1) else '0';
dfp_trap_vector(1851) <= '1' when (V_E_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0';
dfp_trap_vector(1852) <= '1' when (V_E_CTRL_RETT_shadow /= RIN_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(1853) <= '1' when (V_E_CTRL_RETT_shadow /= RIN_E_CTRL_RETT_intermed_1) else '0';
dfp_trap_vector(1854) <= '1' when (V_E_CTRL_RETT_shadow /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(1855) <= '1' when (V_E_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0';
dfp_trap_vector(1856) <= '1' when (V_E_CTRL_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1857) <= '1' when (V_E_CTRL_WREG_shadow /= R_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1858) <= '1' when (V_E_CTRL_WREG_shadow /= R_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1859) <= '1' when (V_E_CTRL_WREG_shadow /= '1') else '0';
dfp_trap_vector(1860) <= '1' when (V_E_CTRL_WREG_shadow /= '0') else '0';
dfp_trap_vector(1861) <= '1' when (V_E_CTRL_WREG_shadow /= RIN_A_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(1862) <= '1' when (V_E_CTRL_WREG_shadow /= V_A_CTRL_WREG_shadow_intermed_1) else '0';
dfp_trap_vector(1863) <= '1' when (V_E_CTRL_WREG_shadow /= R.A.CTRL.WREG) else '0';
dfp_trap_vector(1864) <= '1' when (V_E_CTRL_WREG_shadow /= V_X_ANNUL_ALL_shadow_intermed_1) else '0';
dfp_trap_vector(1865) <= '1' when (V_E_CTRL_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(1866) <= '1' when (V_E_CTRL_WREG_shadow /= R.E.CTRL.WREG) else '0';
dfp_trap_vector(1867) <= '1' when (V_E_CTRL_WREG_shadow /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(1868) <= '1' when (V_E_CTRL_WREG_shadow /= RIN_E_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(1869) <= '1' when (V_E_SU_shadow /= R.A.SU) else '0';
dfp_trap_vector(1870) <= '1' when (V_E_SU_shadow /= RIN_A_SU_intermed_1) else '0';
dfp_trap_vector(1871) <= '1' when (V_E_SU_shadow /= R.E.SU) else '0';
dfp_trap_vector(1872) <= '1' when (V_E_SU_shadow /= V_A_SU_shadow_intermed_1) else '0';
dfp_trap_vector(1873) <= '1' when (V_E_SU_shadow /= RIN_E_SU_intermed_1) else '0';
dfp_trap_vector(1874) <= '1' when (V_E_ET_shadow /= RIN_E_ET_intermed_1) else '0';
dfp_trap_vector(1875) <= '1' when (V_E_ET_shadow /= R.E.ET) else '0';
dfp_trap_vector(1876) <= '1' when (V_E_ET_shadow /= RIN_A_ET_intermed_1) else '0';
dfp_trap_vector(1877) <= '1' when (V_E_ET_shadow /= V_A_ET_shadow_intermed_1) else '0';
dfp_trap_vector(1878) <= '1' when (V_E_ET_shadow /= R.A.ET) else '0';
dfp_trap_vector(1879) <= '1' when (V_E_CTRL_WICC_shadow /= R.A.CTRL.WICC) else '0';
dfp_trap_vector(1880) <= '1' when (V_E_CTRL_WICC_shadow /= RIN_A_CTRL_ANNUL_intermed_2) else '0';
dfp_trap_vector(1881) <= '1' when (V_E_CTRL_WICC_shadow /= V_A_CTRL_WICC_shadow_intermed_1) else '0';
dfp_trap_vector(1882) <= '1' when (V_E_CTRL_WICC_shadow /= R_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1883) <= '1' when (V_E_CTRL_WICC_shadow /= RIN_E_CTRL_WICC_intermed_1) else '0';
dfp_trap_vector(1884) <= '1' when (V_E_CTRL_WICC_shadow /= R_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1885) <= '1' when (V_E_CTRL_WICC_shadow /= '1') else '0';
dfp_trap_vector(1886) <= '1' when (V_E_CTRL_WICC_shadow /= '0') else '0';
dfp_trap_vector(1887) <= '1' when (V_E_CTRL_WICC_shadow /= R.E.CTRL.WICC) else '0';
dfp_trap_vector(1888) <= '1' when (V_E_CTRL_WICC_shadow /= V_X_ANNUL_ALL_shadow_intermed_1) else '0';
dfp_trap_vector(1889) <= '1' when (V_E_CTRL_WICC_shadow /= RIN_X_ANNUL_ALL_intermed_2) else '0';
dfp_trap_vector(1890) <= '1' when (V_E_CTRL_WICC_shadow /= RIN_A_CTRL_WICC_intermed_1) else '0';
dfp_trap_vector(1891) <= '1' when (V_E_CTRL_WICC_shadow /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(1892) <= '1' when (V_A_CWP_shadow /= RIN_D_CWP_intermed_1) else '0';
dfp_trap_vector(1893) <= '1' when (V_A_CWP_shadow /= RIN_A_CWP_intermed_1) else '0';
dfp_trap_vector(1894) <= '1' when (V_A_CWP_shadow /= V_D_CWP_shadow_intermed_1) else '0';
dfp_trap_vector(1895) <= '1' when (V_A_CWP_shadow /= R.D.CWP) else '0';
dfp_trap_vector(1896) <= '1' when (V_A_CWP_shadow /= R.A.CWP) else '0';
dfp_trap_vector(1897) <= '1' when (V_A_RFA1_shadow /= DBGI.DADDR ( 9 DOWNTO 2 )) else '0';
dfp_trap_vector(1898) <= '1' when (V_A_RFA1_shadow /= DE_RADDR17DOWNTO0_shadow) else '0';
dfp_trap_vector(1899) <= '1' when (V_A_RFA1_shadow /= R.A.RFA1) else '0';
dfp_trap_vector(1900) <= '1' when (V_A_RFA1_shadow /= RIN_A_RFA1_intermed_1) else '0';
dfp_trap_vector(1901) <= '1' when (DE_RADDR17DOWNTO0_shadow /= V_A_RFA1_shadow_intermed_1) else '0';
dfp_trap_vector(1902) <= '1' when (DE_RADDR17DOWNTO0_shadow /= DBGI_DADDR9DOWNTO2_intermed_1) else '0';
dfp_trap_vector(1903) <= '1' when (DE_RADDR17DOWNTO0_shadow /= R.A.RFA1) else '0';
dfp_trap_vector(1904) <= '1' when (DE_RADDR17DOWNTO0_shadow /= RIN_A_RFA1_intermed_1) else '0';
dfp_trap_vector(1905) <= '1' when (V_A_RFA2_shadow /= DE_RADDR27DOWNTO0_shadow) else '0';
dfp_trap_vector(1906) <= '1' when (V_A_RFA2_shadow /= R.A.RFA2) else '0';
dfp_trap_vector(1907) <= '1' when (V_A_RFA2_shadow /= RIN_A_RFA2_intermed_1) else '0';
dfp_trap_vector(1908) <= '1' when (V_A_CTRL_ANNUL_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1909) <= '1' when (V_A_CTRL_ANNUL_shadow /= R.A.CTRL.ANNUL) else '0';
dfp_trap_vector(1910) <= '1' when (V_A_CTRL_ANNUL_shadow /= R.X.ANNUL_ALL) else '0';
dfp_trap_vector(1911) <= '1' when (V_A_CTRL_ANNUL_shadow /= '1') else '0';
dfp_trap_vector(1912) <= '1' when (V_A_CTRL_ANNUL_shadow /= '0') else '0';
dfp_trap_vector(1913) <= '1' when (V_A_CTRL_ANNUL_shadow /= V_X_ANNUL_ALL_shadow) else '0';
dfp_trap_vector(1914) <= '1' when (V_A_CTRL_ANNUL_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1915) <= '1' when (V_A_CTRL_WICC_shadow /= R.A.CTRL.WICC) else '0';
dfp_trap_vector(1916) <= '1' when (V_A_CTRL_WICC_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1917) <= '1' when (V_A_CTRL_WICC_shadow /= R.A.CTRL.ANNUL) else '0';
dfp_trap_vector(1918) <= '1' when (V_A_CTRL_WICC_shadow /= R.X.ANNUL_ALL) else '0';
dfp_trap_vector(1919) <= '1' when (V_A_CTRL_WICC_shadow /= '1') else '0';
dfp_trap_vector(1920) <= '1' when (V_A_CTRL_WICC_shadow /= '0') else '0';
dfp_trap_vector(1921) <= '1' when (V_A_CTRL_WICC_shadow /= V_X_ANNUL_ALL_shadow) else '0';
dfp_trap_vector(1922) <= '1' when (V_A_CTRL_WICC_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1923) <= '1' when (V_A_CTRL_WICC_shadow /= RIN_A_CTRL_WICC_intermed_1) else '0';
dfp_trap_vector(1924) <= '1' when (V_A_CTRL_WICC_shadow /= V_A_CTRL_ANNUL_shadow) else '0';
dfp_trap_vector(1925) <= '1' when (V_A_CTRL_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1926) <= '1' when (V_A_CTRL_WREG_shadow /= R.A.CTRL.ANNUL) else '0';
dfp_trap_vector(1927) <= '1' when (V_A_CTRL_WREG_shadow /= R.X.ANNUL_ALL) else '0';
dfp_trap_vector(1928) <= '1' when (V_A_CTRL_WREG_shadow /= '1') else '0';
dfp_trap_vector(1929) <= '1' when (V_A_CTRL_WREG_shadow /= '0') else '0';
dfp_trap_vector(1930) <= '1' when (V_A_CTRL_WREG_shadow /= RIN_A_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(1931) <= '1' when (V_A_CTRL_WREG_shadow /= R.A.CTRL.WREG) else '0';
dfp_trap_vector(1932) <= '1' when (V_A_CTRL_WREG_shadow /= V_X_ANNUL_ALL_shadow) else '0';
dfp_trap_vector(1933) <= '1' when (V_A_CTRL_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1934) <= '1' when (V_A_CTRL_WREG_shadow /= V_A_CTRL_ANNUL_shadow) else '0';
dfp_trap_vector(1935) <= '1' when (V_A_CTRL_RETT_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1936) <= '1' when (V_A_CTRL_RETT_shadow /= R.A.CTRL.ANNUL) else '0';
dfp_trap_vector(1937) <= '1' when (V_A_CTRL_RETT_shadow /= R.X.ANNUL_ALL) else '0';
dfp_trap_vector(1938) <= '1' when (V_A_CTRL_RETT_shadow /= '1') else '0';
dfp_trap_vector(1939) <= '1' when (V_A_CTRL_RETT_shadow /= '0') else '0';
dfp_trap_vector(1940) <= '1' when (V_A_CTRL_RETT_shadow /= RIN_A_CTRL_RETT_intermed_1) else '0';
dfp_trap_vector(1941) <= '1' when (V_A_CTRL_RETT_shadow /= V_X_ANNUL_ALL_shadow) else '0';
dfp_trap_vector(1942) <= '1' when (V_A_CTRL_RETT_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1943) <= '1' when (V_A_CTRL_RETT_shadow /= V_A_CTRL_ANNUL_shadow) else '0';
dfp_trap_vector(1944) <= '1' when (V_A_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0';
dfp_trap_vector(1945) <= '1' when (V_A_CTRL_WY_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0';
dfp_trap_vector(1946) <= '1' when (V_A_CTRL_WY_shadow /= R.A.CTRL.ANNUL) else '0';
dfp_trap_vector(1947) <= '1' when (V_A_CTRL_WY_shadow /= R.X.ANNUL_ALL) else '0';
dfp_trap_vector(1948) <= '1' when (V_A_CTRL_WY_shadow /= '1') else '0';
dfp_trap_vector(1949) <= '1' when (V_A_CTRL_WY_shadow /= '0') else '0';
dfp_trap_vector(1950) <= '1' when (V_A_CTRL_WY_shadow /= V_X_ANNUL_ALL_shadow) else '0';
dfp_trap_vector(1951) <= '1' when (V_A_CTRL_WY_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(1952) <= '1' when (V_A_CTRL_WY_shadow /= R.A.CTRL.WY) else '0';
dfp_trap_vector(1953) <= '1' when (V_A_CTRL_WY_shadow /= RIN_A_CTRL_WY_intermed_1) else '0';
dfp_trap_vector(1954) <= '1' when (V_A_CTRL_WY_shadow /= V_A_CTRL_ANNUL_shadow) else '0';
dfp_trap_vector(1955) <= '1' when (V_A_CTRL_TRAP_shadow /= ICO_MEXC_intermed_1) else '0';
dfp_trap_vector(1956) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_A_CTRL_TRAP_intermed_1) else '0';
dfp_trap_vector(1957) <= '1' when (V_A_CTRL_TRAP_shadow /= R.D.MEXC) else '0';
dfp_trap_vector(1958) <= '1' when (V_A_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_1) else '0';
dfp_trap_vector(1959) <= '1' when (V_A_CTRL_TRAP_shadow /= R.A.CTRL.TRAP) else '0';
dfp_trap_vector(1960) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_1) else '0';
dfp_trap_vector(1961) <= '1' when (V_A_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(1962) <= '1' when (V_A_CTRL_TT_shadow /= R.A.CTRL.TT) else '0';
dfp_trap_vector(1963) <= '1' when (V_A_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(1964) <= '1' when (V_A_CTRL_INST_shadow /= DE_INST_shadow) else '0';
dfp_trap_vector(1965) <= '1' when (V_A_CTRL_INST_shadow /= RIN_A_CTRL_INST_intermed_1) else '0';
dfp_trap_vector(1966) <= '1' when (V_A_CTRL_INST_shadow /= R.A.CTRL.INST) else '0';
dfp_trap_vector(1967) <= '1' when (V_A_CTRL_PC_shadow /= RIN_D_PC_intermed_1) else '0';
dfp_trap_vector(1968) <= '1' when (V_A_CTRL_PC_shadow /= RIN_A_CTRL_PC_intermed_1) else '0';
dfp_trap_vector(1969) <= '1' when (V_A_CTRL_PC_shadow /= R.A.CTRL.PC) else '0';
dfp_trap_vector(1970) <= '1' when (V_A_CTRL_PC_shadow /= R.D.PC) else '0';
dfp_trap_vector(1971) <= '1' when (V_A_CTRL_PC_shadow /= V_D_PC_shadow_intermed_1) else '0';
dfp_trap_vector(1972) <= '1' when (V_A_CTRL_CNT_shadow /= RIN_D_CNT_intermed_1) else '0';
dfp_trap_vector(1973) <= '1' when (V_A_CTRL_CNT_shadow /= R.A.CTRL.CNT) else '0';
dfp_trap_vector(1974) <= '1' when (V_A_CTRL_CNT_shadow /= V_D_CNT_shadow_intermed_1) else '0';
dfp_trap_vector(1975) <= '1' when (V_A_CTRL_CNT_shadow /= R.D.CNT) else '0';
dfp_trap_vector(1976) <= '1' when (V_A_CTRL_CNT_shadow /= RIN_A_CTRL_CNT_intermed_1) else '0';
dfp_trap_vector(1977) <= '1' when (V_A_CTRL_CNT_shadow /= "00") else '0';
dfp_trap_vector(1978) <= '1' when (V_A_STEP_shadow /= R_D_ANNUL_intermed_1) else '0';
dfp_trap_vector(1979) <= '1' when (V_A_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(1980) <= '1' when (V_A_STEP_shadow /= V_D_ANNUL_shadow_intermed_2) else '0';
dfp_trap_vector(1981) <= '1' when (V_A_STEP_shadow /= R.A.STEP) else '0';
dfp_trap_vector(1982) <= '1' when (V_A_STEP_shadow /= DBGI_STEP_intermed_1) else '0';
dfp_trap_vector(1983) <= '1' when (V_A_STEP_shadow /= V_D_STEP_shadow_intermed_1) else '0';
dfp_trap_vector(1984) <= '1' when (V_A_STEP_shadow /= RIN_D_ANNUL_intermed_2) else '0';
dfp_trap_vector(1985) <= '1' when (V_A_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(1986) <= '1' when (V_A_STEP_shadow /= RIN_A_STEP_intermed_1) else '0';
dfp_trap_vector(1987) <= '1' when (V_D_STEP_shadow /= R.D.ANNUL) else '0';
dfp_trap_vector(1988) <= '1' when (V_D_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(1989) <= '1' when (V_D_STEP_shadow /= V_D_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(1990) <= '1' when (V_D_STEP_shadow /= DBGI.STEP) else '0';
dfp_trap_vector(1991) <= '1' when (V_D_STEP_shadow /= RIN_D_ANNUL_intermed_1) else '0';
dfp_trap_vector(1992) <= '1' when (V_D_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(1993) <= '1' when (V_D_CNT_shadow /= RIN_D_CNT_intermed_1) else '0';
dfp_trap_vector(1994) <= '1' when (V_D_CNT_shadow /= R.D.CNT) else '0';
dfp_trap_vector(1995) <= '1' when (V_D_CNT_shadow /= "00") else '0';
dfp_trap_vector(1996) <= '1' when (V_F_PC_shadow /= EX_ADD_RES32DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(1997) <= '1' when (V_F_PC_shadow /= XC_TRAP_ADDRESS_shadow) else '0';
dfp_trap_vector(1998) <= '1' when (V_F_PC_shadow /= RIN_F_PC_intermed_1) else '0';
dfp_trap_vector(1999) <= '1' when (V_F_PC_shadow /= R.F.PC) else '0';
dfp_trap_vector(2000) <= '1' when (V_F_PC_shadow /= EX_JUMP_ADDRESS_shadow_intermed_1) else '0';
dfp_trap_vector(2001) <= '1' when (V_F_PC_shadow /= "000000000000000000000000000000") else '0';
dfp_trap_vector(2002) <= '1' when (V_F_BRANCH_shadow /= RIN_F_BRANCH_intermed_1) else '0';
dfp_trap_vector(2003) <= '1' when (V_F_BRANCH_shadow /= '1') else '0';
dfp_trap_vector(2004) <= '1' when (V_F_BRANCH_shadow /= '0') else '0';
dfp_trap_vector(2005) <= '1' when (V_F_BRANCH_shadow /= R.F.BRANCH) else '0';
dfp_trap_vector(2006) <= '1' when (V_F_PC31DOWNTO12_shadow /= R.F.PC ( 31 DOWNTO 12 )) else '0';
dfp_trap_vector(2007) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_M_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(2008) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_7) else '0';
dfp_trap_vector(2009) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6) else '0';
dfp_trap_vector(2010) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0';
dfp_trap_vector(2011) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2) else '0';
dfp_trap_vector(2012) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_F_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(2013) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(2014) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(2015) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(2016) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_F_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(2017) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(2018) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(2019) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_F_PC31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(2020) <= '1' when (V_F_PC31DOWNTO12_shadow /= IRIN_ADDR31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(2021) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0';
dfp_trap_vector(2022) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2) else '0';
dfp_trap_vector(2023) <= '1' when (V_F_PC31DOWNTO12_shadow /= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0';
dfp_trap_vector(2024) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_F_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(2025) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(2026) <= '1' when (V_F_PC31DOWNTO12_shadow /= IR_ADDR31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(2027) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_X_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(2028) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(2029) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_X_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(2030) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_7) else '0';
dfp_trap_vector(2031) <= '1' when (V_F_PC31DOWNTO12_shadow /= VIR_ADDR31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(2032) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0';
dfp_trap_vector(2033) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2034) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(2035) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_7) else '0';
dfp_trap_vector(2036) <= '1' when (V_F_PC31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2) else '0';
dfp_trap_vector(2037) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_F_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2038) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2039) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2040) <= '1' when (V_F_PC31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2041) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(2042) <= '1' when (V_F_PC31DOWNTO2_shadow(29 downto 2) /= X"0000001") else '0';
dfp_trap_vector(2043) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2044) <= '1' when (V_F_PC31DOWNTO2_shadow /= R.F.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2045) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2046) <= '1' when (V_F_PC31DOWNTO2_shadow /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2047) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2048) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2049) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2050) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2051) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2052) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2053) <= '1' when (V_F_PC31DOWNTO2_shadow /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2054) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2055) <= '1' when (V_F_PC31DOWNTO2_shadow /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2056) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2057) <= '1' when (V_F_PC31DOWNTO2_shadow /= IR_ADDR31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2058) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2059) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2060) <= '1' when (NPC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2061) <= '1' when (NPC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(2062) <= '1' when (NPC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_7) else '0';
dfp_trap_vector(2063) <= '1' when (NPC31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(2064) <= '1' when (NPC31DOWNTO2_shadow /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2065) <= '1' when (NPC31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2066) <= '1' when (NPC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2067) <= '1' when (NPC31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2068) <= '1' when (NPC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(2069) <= '1' when (NPC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2070) <= '1' when (NPC31DOWNTO2_shadow /= R.F.PC( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2071) <= '1' when (NPC31DOWNTO2_shadow /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2072) <= '1' when (NPC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2073) <= '1' when (NPC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2074) <= '1' when (NPC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2075) <= '1' when (NPC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2076) <= '1' when (NPC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2077) <= '1' when (NPC31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2078) <= '1' when (NPC31DOWNTO2_shadow /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2079) <= '1' when (NPC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2080) <= '1' when (NPC31DOWNTO2_shadow /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2081) <= '1' when (NPC31DOWNTO2_shadow /= IR_ADDR31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2082) <= '1' when (NPC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2083) <= '1' when (NPC31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2084) <= '1' when (V_D_INST0_shadow /= RIN_D_INST0_intermed_1) else '0';
dfp_trap_vector(2085) <= '1' when (V_D_INST0_shadow /= R_D_INST0_intermed_1) else '0';
dfp_trap_vector(2086) <= '1' when (V_D_INST0_shadow /= R.D.INST ( 0 )) else '0';
dfp_trap_vector(2087) <= '1' when (V_D_INST0_shadow /= ICO.DATA ( 0 )) else '0';
dfp_trap_vector(2088) <= '1' when (V_D_INST0_shadow /= V_D_INST0_shadow_intermed_2) else '0';
dfp_trap_vector(2089) <= '1' when (V_D_INST0_shadow /= RIN_D_INST0_intermed_2) else '0';
dfp_trap_vector(2090) <= '1' when (V_D_INST1_shadow /= RIN_D_INST1_intermed_1) else '0';
dfp_trap_vector(2091) <= '1' when (V_D_INST1_shadow /= R_D_INST1_intermed_1) else '0';
dfp_trap_vector(2092) <= '1' when (V_D_INST1_shadow /= R.D.INST ( 1 )) else '0';
dfp_trap_vector(2093) <= '1' when (V_D_INST1_shadow /= ICO.DATA ( 1 )) else '0';
dfp_trap_vector(2094) <= '1' when (V_D_INST1_shadow /= V_D_INST1_shadow_intermed_2) else '0';
dfp_trap_vector(2095) <= '1' when (V_D_INST1_shadow /= RIN_D_INST1_intermed_2) else '0';
dfp_trap_vector(2096) <= '1' when (V_D_SET_shadow /= ICO.SET ( 0 DOWNTO 0 )) else '0';
dfp_trap_vector(2097) <= '1' when (V_D_SET_shadow /= R.D.SET) else '0';
dfp_trap_vector(2098) <= '1' when (V_D_SET_shadow /= RIN_D_SET_intermed_1) else '0';
dfp_trap_vector(2099) <= '1' when (V_D_MEXC_shadow /= ICO.MEXC) else '0';
dfp_trap_vector(2100) <= '1' when (V_D_MEXC_shadow /= R.D.MEXC) else '0';
dfp_trap_vector(2101) <= '1' when (V_D_MEXC_shadow /= RIN_D_MEXC_intermed_1) else '0';
dfp_trap_vector(2102) <= '1' when (EX_OP131_shadow /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(2103) <= '1' when (EX_OP131_shadow /= RIN_E_OP131_intermed_1) else '0';
dfp_trap_vector(2104) <= '1' when (EX_OP131_shadow /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(2105) <= '1' when (EX_OP131_shadow /= R.E.OP1( 31 )) else '0';
dfp_trap_vector(2106) <= '1' when (EX_OP131_shadow /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(2107) <= '1' when (EX_OP131_shadow /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(2108) <= '1' when (EX_OP131_shadow /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(2109) <= '1' when (EX_OP131_shadow /= V_E_OP131_shadow_intermed_1) else '0';
dfp_trap_vector(2110) <= '1' when (EX_OP131_shadow /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(2111) <= '1' when (EX_OP131_shadow /= R.X.DATA ( 0 )( 31 )) else '0';
dfp_trap_vector(2112) <= '1' when (EX_OP231_shadow /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(2113) <= '1' when (EX_OP231_shadow /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(2114) <= '1' when (EX_OP231_shadow /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(2115) <= '1' when (EX_OP231_shadow /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(2116) <= '1' when (EX_OP231_shadow /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(2117) <= '1' when (EX_OP231_shadow /= RIN_E_OP231_intermed_1) else '0';
dfp_trap_vector(2118) <= '1' when (EX_OP231_shadow /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(2119) <= '1' when (EX_OP231_shadow /= R.E.OP2( 31 )) else '0';
dfp_trap_vector(2120) <= '1' when (EX_OP231_shadow /= V_E_OP231_shadow_intermed_1) else '0';
dfp_trap_vector(2121) <= '1' when (EX_OP231_shadow /= R.X.DATA ( 0 )( 31 )) else '0';
dfp_trap_vector(2122) <= '1' when (VFPI_D_ANNUL_shadow /= R.D.ANNUL) else '0';
dfp_trap_vector(2123) <= '1' when (VFPI_D_ANNUL_shadow /= R.X.ANNUL_ALL) else '0';
dfp_trap_vector(2124) <= '1' when (VFPI_D_ANNUL_shadow /= '1') else '0';
dfp_trap_vector(2125) <= '1' when (VFPI_D_ANNUL_shadow /= '0') else '0';
dfp_trap_vector(2126) <= '1' when (VFPI_D_ANNUL_shadow /= V_D_ANNUL_shadow_intermed_1) else '0';
dfp_trap_vector(2127) <= '1' when (VFPI_D_ANNUL_shadow /= V_X_ANNUL_ALL_shadow) else '0';
dfp_trap_vector(2128) <= '1' when (VFPI_D_ANNUL_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0';
dfp_trap_vector(2129) <= '1' when (VFPI_D_ANNUL_shadow /= RIN_D_ANNUL_intermed_1) else '0';
dfp_trap_vector(2130) <= '1' when (VFPI_DBG_ENABLE_shadow /= '0') else '0';
dfp_trap_vector(2131) <= '1' when (VFPI_DBG_ENABLE_shadow /= DBGI.DENABLE) else '0';
dfp_trap_vector(2132) <= '1' when (EX_OP13_shadow /= V_X_DATA03_shadow_intermed_2) else '0';
dfp_trap_vector(2133) <= '1' when (EX_OP13_shadow /= V_X_DATA03_shadow_intermed_1) else '0';
dfp_trap_vector(2134) <= '1' when (EX_OP13_shadow /= DCO_DATA03_intermed_1) else '0';
dfp_trap_vector(2135) <= '1' when (EX_OP13_shadow /= RIN_X_DATA03_intermed_1) else '0';
dfp_trap_vector(2136) <= '1' when (EX_OP13_shadow /= R_X_DATA03_intermed_1) else '0';
dfp_trap_vector(2137) <= '1' when (EX_OP13_shadow /= RIN_X_DATA03_intermed_2) else '0';
dfp_trap_vector(2138) <= '1' when (EX_OP13_shadow /= RIN_E_OP13_intermed_1) else '0';
dfp_trap_vector(2139) <= '1' when (EX_OP13_shadow /= R.X.DATA ( 0 )( 3 )) else '0';
dfp_trap_vector(2140) <= '1' when (EX_OP13_shadow /= R.E.OP1( 3 )) else '0';
dfp_trap_vector(2141) <= '1' when (EX_OP13_shadow /= V_E_OP13_shadow_intermed_1) else '0';
dfp_trap_vector(2142) <= '1' when (EX_OP23_shadow /= V_X_DATA03_shadow_intermed_2) else '0';
dfp_trap_vector(2143) <= '1' when (EX_OP23_shadow /= V_X_DATA03_shadow_intermed_1) else '0';
dfp_trap_vector(2144) <= '1' when (EX_OP23_shadow /= DCO_DATA03_intermed_1) else '0';
dfp_trap_vector(2145) <= '1' when (EX_OP23_shadow /= R.E.OP2( 3 )) else '0';
dfp_trap_vector(2146) <= '1' when (EX_OP23_shadow /= RIN_X_DATA03_intermed_1) else '0';
dfp_trap_vector(2147) <= '1' when (EX_OP23_shadow /= R_X_DATA03_intermed_1) else '0';
dfp_trap_vector(2148) <= '1' when (EX_OP23_shadow /= RIN_X_DATA03_intermed_2) else '0';
dfp_trap_vector(2149) <= '1' when (EX_OP23_shadow /= RIN_E_OP23_intermed_1) else '0';
dfp_trap_vector(2150) <= '1' when (EX_OP23_shadow /= R.X.DATA ( 0 )( 3 )) else '0';
dfp_trap_vector(2151) <= '1' when (EX_OP23_shadow /= V_E_OP23_shadow_intermed_1) else '0';
dfp_trap_vector(2152) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R_M_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(2153) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_7) else '0';
dfp_trap_vector(2154) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6) else '0';
dfp_trap_vector(2155) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0';
dfp_trap_vector(2156) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1) else '0';
dfp_trap_vector(2157) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_F_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(2158) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(2159) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(2160) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0';
dfp_trap_vector(2161) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(2162) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(2163) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_F_PC31DOWNTO12_shadow_intermed_1) else '0';
dfp_trap_vector(2164) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= IRIN_ADDR31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(2165) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0';
dfp_trap_vector(2166) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1) else '0';
dfp_trap_vector(2167) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R.F.PC( 31 DOWNTO 12 )) else '0';
dfp_trap_vector(2168) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(2169) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= IR_ADDR31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(2170) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R_X_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(2171) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(2172) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_X_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(2173) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_7) else '0';
dfp_trap_vector(2174) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= VIR_ADDR31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(2175) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0';
dfp_trap_vector(2176) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow) else '0';
dfp_trap_vector(2177) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow) else '0';
dfp_trap_vector(2178) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2179) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(2180) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_7) else '0';
dfp_trap_vector(2181) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(2182) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2183) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2184) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2185) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2186) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(2187) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2188) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R.F.PC( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2189) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2190) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2191) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2192) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2193) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2194) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2195) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2196) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2197) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2198) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IR_ADDR31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2199) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2200) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2201) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2202) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(2203) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_7) else '0';
dfp_trap_vector(2204) <= '1' when (V_F_PC31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(2205) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2206) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2207) <= '1' when (V_F_PC31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2208) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(2209) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2210) <= '1' when (V_F_PC31DOWNTO2_shadow /= R.F.PC( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2211) <= '1' when (V_F_PC31DOWNTO2_shadow /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2212) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2213) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2214) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2215) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2216) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2217) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2218) <= '1' when (V_F_PC31DOWNTO2_shadow /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2219) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2220) <= '1' when (V_F_PC31DOWNTO2_shadow /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2221) <= '1' when (V_F_PC31DOWNTO2_shadow /= IR_ADDR31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2222) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2223) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2224) <= '1' when (EX_OP231_shadow /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(2225) <= '1' when (EX_OP231_shadow /= V_X_DATA031_shadow_intermed_1) else '0';
dfp_trap_vector(2226) <= '1' when (EX_OP231_shadow /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(2227) <= '1' when (EX_OP231_shadow /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(2228) <= '1' when (EX_OP231_shadow /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(2229) <= '1' when (EX_OP231_shadow /= RIN_E_OP231_intermed_1) else '0';
dfp_trap_vector(2230) <= '1' when (EX_OP231_shadow /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(2231) <= '1' when (EX_OP231_shadow /= R.E.OP2( 31 )) else '0';
dfp_trap_vector(2232) <= '1' when (EX_OP231_shadow /= V_E_OP231_shadow_intermed_1) else '0';
dfp_trap_vector(2233) <= '1' when (EX_OP231_shadow /= R.X.DATA ( 0 )( 31 )) else '0';
dfp_trap_vector(2234) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= V_M_CTRL_RD7DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2235) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= V_E_CTRL_RD7DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(2236) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= R_E_CTRL_RD7DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2237) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= R.X.CTRL.RD ( 7 DOWNTO 0 )) else '0';
dfp_trap_vector(2238) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= V_A_CTRL_RD7DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(2239) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= RIN_A_CTRL_RD7DOWNTO0_intermed_4) else '0';
dfp_trap_vector(2240) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= R_M_CTRL_RD7DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2241) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= R_A_CTRL_RD7DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2242) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= RIN_E_CTRL_RD7DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2243) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= RIN_X_CTRL_RD7DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2244) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= RIN_M_CTRL_RD7DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2245) <= '1' when (V_X_CTRL_TRAP_shadow /= RIN_X_CTRL_TRAP_intermed_1) else '0';
dfp_trap_vector(2246) <= '1' when (V_X_CTRL_TRAP_shadow /= V_A_CTRL_TRAP_shadow_intermed_4) else '0';
dfp_trap_vector(2247) <= '1' when (V_X_CTRL_TRAP_shadow /= ICO_MEXC_intermed_5) else '0';
dfp_trap_vector(2248) <= '1' when (V_X_CTRL_TRAP_shadow /= R_E_CTRL_TRAP_intermed_2) else '0';
dfp_trap_vector(2249) <= '1' when (V_X_CTRL_TRAP_shadow /= RIN_A_CTRL_TRAP_intermed_4) else '0';
dfp_trap_vector(2250) <= '1' when (V_X_CTRL_TRAP_shadow /= V_E_CTRL_TRAP_shadow_intermed_3) else '0';
dfp_trap_vector(2251) <= '1' when (V_X_CTRL_TRAP_shadow /= RIN_E_CTRL_TRAP_intermed_3) else '0';
dfp_trap_vector(2252) <= '1' when (V_X_CTRL_TRAP_shadow /= R_D_MEXC_intermed_4) else '0';
dfp_trap_vector(2253) <= '1' when (V_X_CTRL_TRAP_shadow /= R.X.CTRL.TRAP) else '0';
dfp_trap_vector(2254) <= '1' when (V_X_CTRL_TRAP_shadow /= V_M_CTRL_TRAP_shadow_intermed_2) else '0';
dfp_trap_vector(2255) <= '1' when (V_X_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_5) else '0';
dfp_trap_vector(2256) <= '1' when (V_X_CTRL_TRAP_shadow /= R_A_CTRL_TRAP_intermed_3) else '0';
dfp_trap_vector(2257) <= '1' when (V_X_CTRL_TRAP_shadow /= RIN_M_CTRL_TRAP_intermed_2) else '0';
dfp_trap_vector(2258) <= '1' when (V_X_CTRL_TRAP_shadow /= R_M_CTRL_TRAP_intermed_1) else '0';
dfp_trap_vector(2259) <= '1' when (V_X_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_5) else '0';
dfp_trap_vector(2260) <= '1' when (V_X_RESULT6DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2261) <= '1' when (V_X_RESULT6DOWNTO0_shadow /= R.X.RESULT ( 6 DOWNTO 0 )) else '0';
dfp_trap_vector(2262) <= '1' when (V_X_RESULT6DOWNTO0_shadow /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2263) <= '1' when (V_X_RESULT6DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2264) <= '1' when (V_X_RESULT6DOWNTO0_shadow /= R_X_RESULT6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2265) <= '1' when (V_X_CTRL_PC_shadow /= RIN_D_PC_intermed_5) else '0';
dfp_trap_vector(2266) <= '1' when (V_X_CTRL_PC_shadow /= RIN_A_CTRL_PC_intermed_4) else '0';
dfp_trap_vector(2267) <= '1' when (V_X_CTRL_PC_shadow /= R_A_CTRL_PC_intermed_3) else '0';
dfp_trap_vector(2268) <= '1' when (V_X_CTRL_PC_shadow /= V_E_CTRL_PC_shadow_intermed_3) else '0';
dfp_trap_vector(2269) <= '1' when (V_X_CTRL_PC_shadow /= R_M_CTRL_PC_intermed_1) else '0';
dfp_trap_vector(2270) <= '1' when (V_X_CTRL_PC_shadow /= R.X.CTRL.PC) else '0';
dfp_trap_vector(2271) <= '1' when (V_X_CTRL_PC_shadow /= R_E_CTRL_PC_intermed_2) else '0';
dfp_trap_vector(2272) <= '1' when (V_X_CTRL_PC_shadow /= RIN_M_CTRL_PC_intermed_2) else '0';
dfp_trap_vector(2273) <= '1' when (V_X_CTRL_PC_shadow /= V_M_CTRL_PC_shadow_intermed_2) else '0';
dfp_trap_vector(2274) <= '1' when (V_X_CTRL_PC_shadow /= V_A_CTRL_PC_shadow_intermed_4) else '0';
dfp_trap_vector(2275) <= '1' when (V_X_CTRL_PC_shadow /= R_D_PC_intermed_4) else '0';
dfp_trap_vector(2276) <= '1' when (V_X_CTRL_PC_shadow /= RIN_E_CTRL_PC_intermed_3) else '0';
dfp_trap_vector(2277) <= '1' when (V_X_CTRL_PC_shadow /= RIN_X_CTRL_PC_intermed_1) else '0';
dfp_trap_vector(2278) <= '1' when (V_X_CTRL_PC_shadow /= V_D_PC_shadow_intermed_5) else '0';
dfp_trap_vector(2279) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_5) else '0';
dfp_trap_vector(2280) <= '1' when (V_X_CTRL_WREG_shadow /= R.X.CTRL.WREG) else '0';
dfp_trap_vector(2281) <= '1' when (V_X_CTRL_WREG_shadow /= R_A_CTRL_ANNUL_intermed_4) else '0';
dfp_trap_vector(2282) <= '1' when (V_X_CTRL_WREG_shadow /= R_X_ANNUL_ALL_intermed_4) else '0';
dfp_trap_vector(2283) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_X_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(2284) <= '1' when (V_X_CTRL_WREG_shadow /= '1') else '0';
dfp_trap_vector(2285) <= '1' when (V_X_CTRL_WREG_shadow /= '0') else '0';
dfp_trap_vector(2286) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_M_CTRL_WREG_intermed_2) else '0';
dfp_trap_vector(2287) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_A_CTRL_WREG_intermed_4) else '0';
dfp_trap_vector(2288) <= '1' when (V_X_CTRL_WREG_shadow /= V_A_CTRL_WREG_shadow_intermed_4) else '0';
dfp_trap_vector(2289) <= '1' when (V_X_CTRL_WREG_shadow /= R_A_CTRL_WREG_intermed_3) else '0';
dfp_trap_vector(2290) <= '1' when (V_X_CTRL_WREG_shadow /= V_X_ANNUL_ALL_shadow_intermed_4) else '0';
dfp_trap_vector(2291) <= '1' when (V_X_CTRL_WREG_shadow /= R_M_CTRL_WREG_intermed_1) else '0';
dfp_trap_vector(2292) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_5) else '0';
dfp_trap_vector(2293) <= '1' when (V_X_CTRL_WREG_shadow /= V_M_CTRL_WREG_shadow_intermed_2) else '0';
dfp_trap_vector(2294) <= '1' when (V_X_CTRL_WREG_shadow /= R_E_CTRL_WREG_intermed_2) else '0';
dfp_trap_vector(2295) <= '1' when (V_X_CTRL_WREG_shadow /= V_A_CTRL_ANNUL_shadow_intermed_4) else '0';
dfp_trap_vector(2296) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_E_CTRL_WREG_intermed_3) else '0';
dfp_trap_vector(2297) <= '1' when (V_X_CTRL_WREG_shadow /= V_E_CTRL_WREG_shadow_intermed_3) else '0';
dfp_trap_vector(2298) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2299) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2300) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2301) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2302) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2303) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2304) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2305) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2306) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2307) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2308) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R.X.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2309) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2310) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2311) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2312) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2313) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2314) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2315) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2316) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2317) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2318) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2319) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2320) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2321) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2322) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2323) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2324) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2325) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2326) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2327) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2328) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2329) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2330) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2331) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2332) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2333) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2334) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2335) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R.X.CTRL.PC( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2336) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2337) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2338) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2339) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_M_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2340) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(2341) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2342) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_4) else '0';
dfp_trap_vector(2343) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_5) else '0';
dfp_trap_vector(2344) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5) else '0';
dfp_trap_vector(2345) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_W_S_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2346) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_E_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2347) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_W_S_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2348) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_M_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2349) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(2350) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2351) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2352) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_W_S_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2353) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2354) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2355) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(2356) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2357) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_W_S_TT3DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2358) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2359) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_4) else '0';
dfp_trap_vector(2360) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R.W.S.TT ( 3 DOWNTO 0 )) else '0';
dfp_trap_vector(2361) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= XC_VECTT3DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(2362) <= '1' when (V_M_RESULT1DOWNTO0_shadow /= V_M_RESULT1DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2363) <= '1' when (V_M_RESULT1DOWNTO0_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0';
dfp_trap_vector(2364) <= '1' when (V_M_RESULT1DOWNTO0_shadow /= RIN_M_RESULT1DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2365) <= '1' when (V_M_RESULT1DOWNTO0_shadow /= R_M_RESULT1DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2366) <= '1' when (V_M_RESULT1DOWNTO0_shadow /= RIN_M_RESULT1DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2367) <= '1' when (V_X_DATA031_shadow /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(2368) <= '1' when (V_X_DATA031_shadow /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(2369) <= '1' when (V_X_DATA031_shadow /= V_X_DATA031_shadow_intermed_3) else '0';
dfp_trap_vector(2370) <= '1' when (V_X_DATA031_shadow /= RIN_X_DATA031_intermed_3) else '0';
dfp_trap_vector(2371) <= '1' when (V_X_DATA031_shadow /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(2372) <= '1' when (V_X_DATA031_shadow /= R.X.DATA ( 0 ) ( 31 )) else '0';
dfp_trap_vector(2373) <= '1' when (V_X_DATA031_shadow /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(2374) <= '1' when (V_X_DATA031_shadow /= R_X_DATA031_intermed_2) else '0';
dfp_trap_vector(2375) <= '1' when (V_X_DATA031_shadow /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(2376) <= '1' when (V_X_DATA031_shadow /= RIN_X_DATA031_intermed_1) else '0';
dfp_trap_vector(2377) <= '1' when (V_X_DATA031_shadow /= V_X_DATA031_shadow_intermed_2) else '0';
dfp_trap_vector(2378) <= '1' when (V_X_DATA031_shadow /= RIN_X_DATA031_intermed_2) else '0';
dfp_trap_vector(2379) <= '1' when (V_X_DATA031_shadow /= DCO_DATA031_intermed_1) else '0';
dfp_trap_vector(2380) <= '1' when (V_X_DATA031_shadow /= R_X_DATA031_intermed_1) else '0';
dfp_trap_vector(2381) <= '1' when (V_X_DATA031_shadow /= R.X.DATA ( 0 )( 31 )) else '0';
dfp_trap_vector(2382) <= '1' when (V_E_CTRL_INST19_shadow /= V_A_CTRL_INST19_shadow_intermed_3) else '0';
dfp_trap_vector(2383) <= '1' when (V_E_CTRL_INST19_shadow /= V_E_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(2384) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(2385) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_3) else '0';
dfp_trap_vector(2386) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(2387) <= '1' when (V_E_CTRL_INST19_shadow /= R.E.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(2388) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_E_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(2389) <= '1' when (V_E_CTRL_INST19_shadow /= DE_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(2390) <= '1' when (V_E_CTRL_INST19_shadow /= R_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(2391) <= '1' when (V_E_CTRL_INST19_shadow /= R_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(2392) <= '1' when (V_E_CTRL_INST19_shadow /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(2393) <= '1' when (V_E_CTRL_INST19_shadow /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(2394) <= '1' when (V_E_CTRL_INST20_shadow /= R.E.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(2395) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(2396) <= '1' when (V_E_CTRL_INST20_shadow /= R_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(2397) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_3) else '0';
dfp_trap_vector(2398) <= '1' when (V_E_CTRL_INST20_shadow /= V_E_CTRL_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(2399) <= '1' when (V_E_CTRL_INST20_shadow /= V_A_CTRL_INST20_shadow_intermed_3) else '0';
dfp_trap_vector(2400) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_E_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(2401) <= '1' when (V_E_CTRL_INST20_shadow /= V_A_CTRL_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(2402) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_E_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(2403) <= '1' when (V_E_CTRL_INST20_shadow /= R_E_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(2404) <= '1' when (V_E_CTRL_INST20_shadow /= DE_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(2405) <= '1' when (V_E_CTRL_INST20_shadow /= R_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(2406) <= '1' when (V_X_DATA00_shadow /= V_X_DATA00_shadow_intermed_2) else '0';
dfp_trap_vector(2407) <= '1' when (V_X_DATA00_shadow /= R.X.DATA ( 0 ) ( 0 )) else '0';
dfp_trap_vector(2408) <= '1' when (V_X_DATA00_shadow /= RIN_X_DATA00_intermed_1) else '0';
dfp_trap_vector(2409) <= '1' when (V_X_DATA00_shadow /= R_X_DATA00_intermed_2) else '0';
dfp_trap_vector(2410) <= '1' when (V_X_DATA00_shadow /= RIN_X_DATA00_intermed_2) else '0';
dfp_trap_vector(2411) <= '1' when (V_X_DATA00_shadow /= DCO_DATA00_intermed_1) else '0';
dfp_trap_vector(2412) <= '1' when (V_X_DATA00_shadow /= V_X_DATA00_shadow_intermed_3) else '0';
dfp_trap_vector(2413) <= '1' when (V_X_DATA00_shadow /= R_X_DATA00_intermed_1) else '0';
dfp_trap_vector(2414) <= '1' when (V_X_DATA00_shadow /= RIN_X_DATA00_intermed_3) else '0';
dfp_trap_vector(2415) <= '1' when (V_X_DATA00_shadow /= R_X_DATA00_intermed_1) else '0';
dfp_trap_vector(2416) <= '1' when (V_X_DATA00_shadow /= RIN_X_DATA00_intermed_1) else '0';
dfp_trap_vector(2417) <= '1' when (V_X_DATA00_shadow /= DCO_DATA00_intermed_1) else '0';
dfp_trap_vector(2418) <= '1' when (V_X_DATA00_shadow /= V_X_DATA00_shadow_intermed_2) else '0';
dfp_trap_vector(2419) <= '1' when (V_X_DATA00_shadow /= R.X.DATA ( 0 )( 0 )) else '0';
dfp_trap_vector(2420) <= '1' when (V_X_DATA00_shadow /= RIN_X_DATA00_intermed_2) else '0';
dfp_trap_vector(2421) <= '1' when (V_X_DATA04DOWNTO0_shadow /= RIN_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2422) <= '1' when (V_X_DATA04DOWNTO0_shadow /= R_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2423) <= '1' when (V_X_DATA04DOWNTO0_shadow /= R_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2424) <= '1' when (V_X_DATA04DOWNTO0_shadow /= RIN_X_DATA04DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2425) <= '1' when (V_X_DATA04DOWNTO0_shadow /= R.X.DATA ( 0 ) ( 4 DOWNTO 0 )) else '0';
dfp_trap_vector(2426) <= '1' when (V_X_DATA04DOWNTO0_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2427) <= '1' when (V_X_DATA04DOWNTO0_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(2428) <= '1' when (V_X_DATA04DOWNTO0_shadow /= RIN_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2429) <= '1' when (V_X_DATA04DOWNTO0_shadow /= DCO_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2430) <= '1' when (V_X_DATA04DOWNTO0_shadow /= R_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2431) <= '1' when (V_X_DATA04DOWNTO0_shadow /= R.X.DATA ( 0 )( 4 DOWNTO 0 )) else '0';
dfp_trap_vector(2432) <= '1' when (V_X_DATA04DOWNTO0_shadow /= RIN_X_DATA04DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2433) <= '1' when (V_X_DATA04DOWNTO0_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2434) <= '1' when (V_X_DATA04DOWNTO0_shadow /= DCO_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2435) <= '1' when (V_X_DATA04DOWNTO0_shadow /= RIN_X_DATA04DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2436) <= '1' when (V_D_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2437) <= '1' when (V_D_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2438) <= '1' when (V_D_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2439) <= '1' when (V_D_PC31DOWNTO2_shadow /= R.D.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2440) <= '1' when (V_D_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2441) <= '1' when (V_E_CTRL_INST24_shadow /= R_A_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(2442) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_E_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(2443) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_3) else '0';
dfp_trap_vector(2444) <= '1' when (V_E_CTRL_INST24_shadow /= R_E_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(2445) <= '1' when (V_E_CTRL_INST24_shadow /= R_A_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(2446) <= '1' when (V_E_CTRL_INST24_shadow /= R.E.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(2447) <= '1' when (V_E_CTRL_INST24_shadow /= V_A_CTRL_INST24_shadow_intermed_3) else '0';
dfp_trap_vector(2448) <= '1' when (V_E_CTRL_INST24_shadow /= V_E_CTRL_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(2449) <= '1' when (V_E_CTRL_INST24_shadow /= DE_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(2450) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(2451) <= '1' when (V_E_CTRL_INST24_shadow /= V_A_CTRL_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(2452) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_E_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(2453) <= '1' when (V_A_CTRL_INST19_shadow /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(2454) <= '1' when (V_A_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(2455) <= '1' when (V_A_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(2456) <= '1' when (V_A_CTRL_INST19_shadow /= DE_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(2457) <= '1' when (V_A_CTRL_INST19_shadow /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(2458) <= '1' when (V_A_CTRL_INST19_shadow /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(2459) <= '1' when (V_M_Y31_shadow /= RIN_M_Y31_intermed_1) else '0';
dfp_trap_vector(2460) <= '1' when (V_M_Y31_shadow /= V_M_Y31_shadow_intermed_2) else '0';
dfp_trap_vector(2461) <= '1' when (V_M_Y31_shadow /= RIN_M_Y31_intermed_2) else '0';
dfp_trap_vector(2462) <= '1' when (V_M_Y31_shadow /= R_M_Y31_intermed_1) else '0';
dfp_trap_vector(2463) <= '1' when (V_M_Y31_shadow /= R.M.Y ( 31 )) else '0';
dfp_trap_vector(2464) <= '1' when (VDSU_CRDY2_shadow /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(2465) <= '1' when (VDSU_CRDY2_shadow /= DSUR.CRDY ( 2 )) else '0';
dfp_trap_vector(2466) <= '1' when (VDSU_CRDY2_shadow /= VDSU_CRDY2_shadow_intermed_2) else '0';
dfp_trap_vector(2467) <= '1' when (VDSU_CRDY2_shadow /= DSUIN_CRDY2_intermed_2) else '0';
dfp_trap_vector(2468) <= '1' when (VDSU_CRDY2_shadow /= DSUR_CRDY2_intermed_1) else '0';
dfp_trap_vector(2469) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2470) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2471) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2472) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2473) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2474) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2475) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2476) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2477) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2478) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2479) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2480) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2481) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2482) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2483) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2484) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2485) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2486) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2487) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2488) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2489) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2490) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2491) <= '1' when (V_E_CTRL_INST_shadow /= R.E.CTRL.INST) else '0';
dfp_trap_vector(2492) <= '1' when (V_E_CTRL_INST_shadow /= DE_INST_shadow_intermed_2) else '0';
dfp_trap_vector(2493) <= '1' when (V_E_CTRL_INST_shadow /= V_A_CTRL_INST_shadow_intermed_2) else '0';
dfp_trap_vector(2494) <= '1' when (V_E_CTRL_INST_shadow /= RIN_A_CTRL_INST_intermed_2) else '0';
dfp_trap_vector(2495) <= '1' when (V_E_CTRL_INST_shadow /= RIN_E_CTRL_INST_intermed_1) else '0';
dfp_trap_vector(2496) <= '1' when (V_E_CTRL_INST_shadow /= R_A_CTRL_INST_intermed_1) else '0';
dfp_trap_vector(2497) <= '1' when (V_E_CTRL_CNT_shadow /= RIN_D_CNT_intermed_3) else '0';
dfp_trap_vector(2498) <= '1' when (V_E_CTRL_CNT_shadow /= V_A_CTRL_CNT_shadow_intermed_2) else '0';
dfp_trap_vector(2499) <= '1' when (V_E_CTRL_CNT_shadow /= R_A_CTRL_CNT_intermed_1) else '0';
dfp_trap_vector(2500) <= '1' when (V_E_CTRL_CNT_shadow /= V_D_CNT_shadow_intermed_3) else '0';
dfp_trap_vector(2501) <= '1' when (V_E_CTRL_CNT_shadow /= R_D_CNT_intermed_2) else '0';
dfp_trap_vector(2502) <= '1' when (V_E_CTRL_CNT_shadow /= R.E.CTRL.CNT) else '0';
dfp_trap_vector(2503) <= '1' when (V_E_CTRL_CNT_shadow /= RIN_A_CTRL_CNT_intermed_2) else '0';
dfp_trap_vector(2504) <= '1' when (V_E_CTRL_CNT_shadow /= "00") else '0';
dfp_trap_vector(2505) <= '1' when (V_E_CTRL_CNT_shadow /= RIN_E_CTRL_CNT_intermed_1) else '0';
dfp_trap_vector(2506) <= '1' when (V_E_CTRL_TRAP_shadow /= V_A_CTRL_TRAP_shadow_intermed_2) else '0';
dfp_trap_vector(2507) <= '1' when (V_E_CTRL_TRAP_shadow /= ICO_MEXC_intermed_3) else '0';
dfp_trap_vector(2508) <= '1' when (V_E_CTRL_TRAP_shadow /= R.E.CTRL.TRAP) else '0';
dfp_trap_vector(2509) <= '1' when (V_E_CTRL_TRAP_shadow /= RIN_A_CTRL_TRAP_intermed_2) else '0';
dfp_trap_vector(2510) <= '1' when (V_E_CTRL_TRAP_shadow /= RIN_E_CTRL_TRAP_intermed_1) else '0';
dfp_trap_vector(2511) <= '1' when (V_E_CTRL_TRAP_shadow /= R_D_MEXC_intermed_2) else '0';
dfp_trap_vector(2512) <= '1' when (V_E_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_3) else '0';
dfp_trap_vector(2513) <= '1' when (V_E_CTRL_TRAP_shadow /= R_A_CTRL_TRAP_intermed_1) else '0';
dfp_trap_vector(2514) <= '1' when (V_E_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_3) else '0';
dfp_trap_vector(2515) <= '1' when (V_E_CTRL_PV_shadow /= R.E.CTRL.PV) else '0';
dfp_trap_vector(2516) <= '1' when (V_E_CTRL_PV_shadow /= R_A_CTRL_PV_intermed_1) else '0';
dfp_trap_vector(2517) <= '1' when (V_E_CTRL_PV_shadow /= RIN_E_CTRL_PV_intermed_1) else '0';
dfp_trap_vector(2518) <= '1' when (V_E_CTRL_PV_shadow /= V_A_CTRL_PV_shadow_intermed_2) else '0';
dfp_trap_vector(2519) <= '1' when (V_E_CTRL_PV_shadow /= RIN_A_CTRL_PV_intermed_2) else '0';
dfp_trap_vector(2520) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2521) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2522) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2523) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2524) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2525) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2526) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2527) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2528) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2529) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2530) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2531) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2532) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2533) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2534) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2535) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2536) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2537) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2538) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2539) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2540) <= '1' when (V_M_CTRL_INST_shadow /= R_E_CTRL_INST_intermed_1) else '0';
dfp_trap_vector(2541) <= '1' when (V_M_CTRL_INST_shadow /= R.M.CTRL.INST) else '0';
dfp_trap_vector(2542) <= '1' when (V_M_CTRL_INST_shadow /= DE_INST_shadow_intermed_3) else '0';
dfp_trap_vector(2543) <= '1' when (V_M_CTRL_INST_shadow /= V_A_CTRL_INST_shadow_intermed_3) else '0';
dfp_trap_vector(2544) <= '1' when (V_M_CTRL_INST_shadow /= V_E_CTRL_INST_shadow_intermed_2) else '0';
dfp_trap_vector(2545) <= '1' when (V_M_CTRL_INST_shadow /= RIN_A_CTRL_INST_intermed_3) else '0';
dfp_trap_vector(2546) <= '1' when (V_M_CTRL_INST_shadow /= RIN_M_CTRL_INST_intermed_1) else '0';
dfp_trap_vector(2547) <= '1' when (V_M_CTRL_INST_shadow /= RIN_E_CTRL_INST_intermed_2) else '0';
dfp_trap_vector(2548) <= '1' when (V_M_CTRL_INST_shadow /= R_A_CTRL_INST_intermed_2) else '0';
dfp_trap_vector(2549) <= '1' when (V_M_CTRL_CNT_shadow /= V_E_CTRL_CNT_shadow_intermed_2) else '0';
dfp_trap_vector(2550) <= '1' when (V_M_CTRL_CNT_shadow /= RIN_D_CNT_intermed_4) else '0';
dfp_trap_vector(2551) <= '1' when (V_M_CTRL_CNT_shadow /= R.M.CTRL.CNT) else '0';
dfp_trap_vector(2552) <= '1' when (V_M_CTRL_CNT_shadow /= V_A_CTRL_CNT_shadow_intermed_3) else '0';
dfp_trap_vector(2553) <= '1' when (V_M_CTRL_CNT_shadow /= R_A_CTRL_CNT_intermed_2) else '0';
dfp_trap_vector(2554) <= '1' when (V_M_CTRL_CNT_shadow /= V_D_CNT_shadow_intermed_4) else '0';
dfp_trap_vector(2555) <= '1' when (V_M_CTRL_CNT_shadow /= R_D_CNT_intermed_3) else '0';
dfp_trap_vector(2556) <= '1' when (V_M_CTRL_CNT_shadow /= R_E_CTRL_CNT_intermed_1) else '0';
dfp_trap_vector(2557) <= '1' when (V_M_CTRL_CNT_shadow /= RIN_A_CTRL_CNT_intermed_3) else '0';
dfp_trap_vector(2558) <= '1' when (V_M_CTRL_CNT_shadow /= RIN_M_CTRL_CNT_intermed_1) else '0';
dfp_trap_vector(2559) <= '1' when (V_M_CTRL_CNT_shadow /= "00") else '0';
dfp_trap_vector(2560) <= '1' when (V_M_CTRL_CNT_shadow /= RIN_E_CTRL_CNT_intermed_2) else '0';
dfp_trap_vector(2561) <= '1' when (V_M_CTRL_TRAP_shadow /= V_A_CTRL_TRAP_shadow_intermed_3) else '0';
dfp_trap_vector(2562) <= '1' when (V_M_CTRL_TRAP_shadow /= ICO_MEXC_intermed_4) else '0';
dfp_trap_vector(2563) <= '1' when (V_M_CTRL_TRAP_shadow /= R_E_CTRL_TRAP_intermed_1) else '0';
dfp_trap_vector(2564) <= '1' when (V_M_CTRL_TRAP_shadow /= RIN_A_CTRL_TRAP_intermed_3) else '0';
dfp_trap_vector(2565) <= '1' when (V_M_CTRL_TRAP_shadow /= V_E_CTRL_TRAP_shadow_intermed_2) else '0';
dfp_trap_vector(2566) <= '1' when (V_M_CTRL_TRAP_shadow /= RIN_E_CTRL_TRAP_intermed_2) else '0';
dfp_trap_vector(2567) <= '1' when (V_M_CTRL_TRAP_shadow /= R_D_MEXC_intermed_3) else '0';
dfp_trap_vector(2568) <= '1' when (V_M_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_4) else '0';
dfp_trap_vector(2569) <= '1' when (V_M_CTRL_TRAP_shadow /= R_A_CTRL_TRAP_intermed_2) else '0';
dfp_trap_vector(2570) <= '1' when (V_M_CTRL_TRAP_shadow /= RIN_M_CTRL_TRAP_intermed_1) else '0';
dfp_trap_vector(2571) <= '1' when (V_M_CTRL_TRAP_shadow /= R.M.CTRL.TRAP) else '0';
dfp_trap_vector(2572) <= '1' when (V_M_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_4) else '0';
dfp_trap_vector(2573) <= '1' when (V_M_CTRL_PV_shadow /= V_E_CTRL_PV_shadow_intermed_2) else '0';
dfp_trap_vector(2574) <= '1' when (V_M_CTRL_PV_shadow /= R.M.CTRL.PV) else '0';
dfp_trap_vector(2575) <= '1' when (V_M_CTRL_PV_shadow /= R_E_CTRL_PV_intermed_1) else '0';
dfp_trap_vector(2576) <= '1' when (V_M_CTRL_PV_shadow /= R_A_CTRL_PV_intermed_2) else '0';
dfp_trap_vector(2577) <= '1' when (V_M_CTRL_PV_shadow /= RIN_E_CTRL_PV_intermed_2) else '0';
dfp_trap_vector(2578) <= '1' when (V_M_CTRL_PV_shadow /= RIN_M_CTRL_PV_intermed_1) else '0';
dfp_trap_vector(2579) <= '1' when (V_M_CTRL_PV_shadow /= V_A_CTRL_PV_shadow_intermed_3) else '0';
dfp_trap_vector(2580) <= '1' when (V_M_CTRL_PV_shadow /= RIN_A_CTRL_PV_intermed_3) else '0';
dfp_trap_vector(2581) <= '1' when (V_X_CTRL_INST_shadow /= R_E_CTRL_INST_intermed_2) else '0';
dfp_trap_vector(2582) <= '1' when (V_X_CTRL_INST_shadow /= R_M_CTRL_INST_intermed_1) else '0';
dfp_trap_vector(2583) <= '1' when (V_X_CTRL_INST_shadow /= DE_INST_shadow_intermed_4) else '0';
dfp_trap_vector(2584) <= '1' when (V_X_CTRL_INST_shadow /= V_A_CTRL_INST_shadow_intermed_4) else '0';
dfp_trap_vector(2585) <= '1' when (V_X_CTRL_INST_shadow /= V_E_CTRL_INST_shadow_intermed_3) else '0';
dfp_trap_vector(2586) <= '1' when (V_X_CTRL_INST_shadow /= R.X.CTRL.INST) else '0';
dfp_trap_vector(2587) <= '1' when (V_X_CTRL_INST_shadow /= RIN_X_CTRL_INST_intermed_1) else '0';
dfp_trap_vector(2588) <= '1' when (V_X_CTRL_INST_shadow /= RIN_A_CTRL_INST_intermed_4) else '0';
dfp_trap_vector(2589) <= '1' when (V_X_CTRL_INST_shadow /= RIN_M_CTRL_INST_intermed_2) else '0';
dfp_trap_vector(2590) <= '1' when (V_X_CTRL_INST_shadow /= RIN_E_CTRL_INST_intermed_3) else '0';
dfp_trap_vector(2591) <= '1' when (V_X_CTRL_INST_shadow /= V_M_CTRL_INST_shadow_intermed_2) else '0';
dfp_trap_vector(2592) <= '1' when (V_X_CTRL_INST_shadow /= R_A_CTRL_INST_intermed_3) else '0';
dfp_trap_vector(2593) <= '1' when (V_X_CTRL_CNT_shadow /= V_E_CTRL_CNT_shadow_intermed_3) else '0';
dfp_trap_vector(2594) <= '1' when (V_X_CTRL_CNT_shadow /= R.X.CTRL.CNT) else '0';
dfp_trap_vector(2595) <= '1' when (V_X_CTRL_CNT_shadow /= RIN_D_CNT_intermed_5) else '0';
dfp_trap_vector(2596) <= '1' when (V_X_CTRL_CNT_shadow /= R_M_CTRL_CNT_intermed_1) else '0';
dfp_trap_vector(2597) <= '1' when (V_X_CTRL_CNT_shadow /= V_A_CTRL_CNT_shadow_intermed_4) else '0';
dfp_trap_vector(2598) <= '1' when (V_X_CTRL_CNT_shadow /= R_A_CTRL_CNT_intermed_3) else '0';
dfp_trap_vector(2599) <= '1' when (V_X_CTRL_CNT_shadow /= V_D_CNT_shadow_intermed_5) else '0';
dfp_trap_vector(2600) <= '1' when (V_X_CTRL_CNT_shadow /= R_D_CNT_intermed_4) else '0';
dfp_trap_vector(2601) <= '1' when (V_X_CTRL_CNT_shadow /= R_E_CTRL_CNT_intermed_2) else '0';
dfp_trap_vector(2602) <= '1' when (V_X_CTRL_CNT_shadow /= RIN_X_CTRL_CNT_intermed_1) else '0';
dfp_trap_vector(2603) <= '1' when (V_X_CTRL_CNT_shadow /= RIN_A_CTRL_CNT_intermed_4) else '0';
dfp_trap_vector(2604) <= '1' when (V_X_CTRL_CNT_shadow /= RIN_M_CTRL_CNT_intermed_2) else '0';
dfp_trap_vector(2605) <= '1' when (V_X_CTRL_CNT_shadow /= "00") else '0';
dfp_trap_vector(2606) <= '1' when (V_X_CTRL_CNT_shadow /= RIN_E_CTRL_CNT_intermed_3) else '0';
dfp_trap_vector(2607) <= '1' when (V_X_CTRL_CNT_shadow /= V_M_CTRL_CNT_shadow_intermed_2) else '0';
dfp_trap_vector(2608) <= '1' when (V_X_CTRL_PV_shadow /= V_E_CTRL_PV_shadow_intermed_3) else '0';
dfp_trap_vector(2609) <= '1' when (V_X_CTRL_PV_shadow /= R_M_CTRL_PV_intermed_1) else '0';
dfp_trap_vector(2610) <= '1' when (V_X_CTRL_PV_shadow /= R_E_CTRL_PV_intermed_2) else '0';
dfp_trap_vector(2611) <= '1' when (V_X_CTRL_PV_shadow /= R_A_CTRL_PV_intermed_3) else '0';
dfp_trap_vector(2612) <= '1' when (V_X_CTRL_PV_shadow /= RIN_E_CTRL_PV_intermed_3) else '0';
dfp_trap_vector(2613) <= '1' when (V_X_CTRL_PV_shadow /= R.X.CTRL.PV) else '0';
dfp_trap_vector(2614) <= '1' when (V_X_CTRL_PV_shadow /= RIN_X_CTRL_PV_intermed_1) else '0';
dfp_trap_vector(2615) <= '1' when (V_X_CTRL_PV_shadow /= RIN_M_CTRL_PV_intermed_2) else '0';
dfp_trap_vector(2616) <= '1' when (V_X_CTRL_PV_shadow /= V_A_CTRL_PV_shadow_intermed_4) else '0';
dfp_trap_vector(2617) <= '1' when (V_X_CTRL_PV_shadow /= V_M_CTRL_PV_shadow_intermed_2) else '0';
dfp_trap_vector(2618) <= '1' when (V_X_CTRL_PV_shadow /= RIN_A_CTRL_PV_intermed_4) else '0';
dfp_trap_vector(2619) <= '1' when (V_E_CTRL_INST19_shadow /= V_A_CTRL_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(2620) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_2) else '0';
dfp_trap_vector(2621) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_E_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(2622) <= '1' when (V_E_CTRL_INST19_shadow /= DE_INST19_shadow_intermed_2) else '0';
dfp_trap_vector(2623) <= '1' when (V_E_CTRL_INST19_shadow /= R.E.CTRL.INST( 19 )) else '0';
dfp_trap_vector(2624) <= '1' when (V_E_CTRL_INST19_shadow /= R_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(2625) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(2626) <= '1' when (V_E_CTRL_INST20_shadow /= V_A_CTRL_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(2627) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_E_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(2628) <= '1' when (V_E_CTRL_INST20_shadow /= R.E.CTRL.INST( 20 )) else '0';
dfp_trap_vector(2629) <= '1' when (V_E_CTRL_INST20_shadow /= DE_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(2630) <= '1' when (V_E_CTRL_INST20_shadow /= R_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(2631) <= '1' when (V_E_CTRL_INST24_shadow /= R_A_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(2632) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(2633) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_E_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(2634) <= '1' when (V_E_CTRL_INST24_shadow /= R.E.CTRL.INST( 24 )) else '0';
dfp_trap_vector(2635) <= '1' when (V_E_CTRL_INST24_shadow /= V_A_CTRL_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(2636) <= '1' when (V_E_CTRL_INST24_shadow /= DE_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(2637) <= '1' when (V_A_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_1) else '0';
dfp_trap_vector(2638) <= '1' when (V_A_CTRL_INST19_shadow /= DE_INST19_shadow_intermed_1) else '0';
dfp_trap_vector(2639) <= '1' when (V_A_CTRL_INST19_shadow /= R.A.CTRL.INST( 19 )) else '0';
dfp_trap_vector(2640) <= '1' when (V_F_PC31DOWNTO4_shadow /= V_X_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0';
dfp_trap_vector(2641) <= '1' when (V_F_PC31DOWNTO4_shadow /= IR_ADDR31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(2642) <= '1' when (V_F_PC31DOWNTO4_shadow /= R.F.PC( 31 DOWNTO 4 )) else '0';
dfp_trap_vector(2643) <= '1' when (V_F_PC31DOWNTO4_shadow /= VIR_ADDR31DOWNTO4_shadow_intermed_2) else '0';
dfp_trap_vector(2644) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_F_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(2645) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_6) else '0';
dfp_trap_vector(2646) <= '1' when (V_F_PC31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_5) else '0';
dfp_trap_vector(2647) <= '1' when (V_F_PC31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_6) else '0';
dfp_trap_vector(2648) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_X_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(2649) <= '1' when (V_F_PC31DOWNTO4_shadow /= EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1) else '0';
dfp_trap_vector(2650) <= '1' when (V_F_PC31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_7) else '0';
dfp_trap_vector(2651) <= '1' when (V_F_PC31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_5) else '0';
dfp_trap_vector(2652) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(2653) <= '1' when (V_F_PC31DOWNTO4_shadow /= R_X_CTRL_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(2654) <= '1' when (V_F_PC31DOWNTO4_shadow /= IRIN_ADDR31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(2655) <= '1' when (V_F_PC31DOWNTO4_shadow /= V_M_CTRL_PC31DOWNTO4_shadow_intermed_4) else '0';
dfp_trap_vector(2656) <= '1' when (V_F_PC31DOWNTO4_shadow /= R_M_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(2657) <= '1' when (V_F_PC31DOWNTO4_shadow /= XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1) else '0';
dfp_trap_vector(2658) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_7) else '0';
dfp_trap_vector(2659) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_5) else '0';
dfp_trap_vector(2660) <= '1' when (V_F_PC31DOWNTO4_shadow /= EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1) else '0';
dfp_trap_vector(2661) <= '1' when (V_F_PC31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_6) else '0';
dfp_trap_vector(2662) <= '1' when (V_F_PC31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(2663) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2) else '0';
dfp_trap_vector(2664) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= IR.ADDR( 31 DOWNTO 4 )) else '0';
dfp_trap_vector(2665) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_5) else '0';
dfp_trap_vector(2666) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(2667) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_5) else '0';
dfp_trap_vector(2668) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= RIN_X_CTRL_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(2669) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_6) else '0';
dfp_trap_vector(2670) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4) else '0';
dfp_trap_vector(2671) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(2672) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= R_X_CTRL_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(2673) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= IRIN_ADDR31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(2674) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0';
dfp_trap_vector(2675) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= R_M_CTRL_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(2676) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_6) else '0';
dfp_trap_vector(2677) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(2678) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5) else '0';
dfp_trap_vector(2679) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(2680) <= '1' when (V_F_PC3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2681) <= '1' when (V_F_PC3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(2682) <= '1' when (V_F_PC3DOWNTO2_shadow /= VIR_ADDR3DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2683) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_7) else '0';
dfp_trap_vector(2684) <= '1' when (V_F_PC3DOWNTO2_shadow /= R_M_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2685) <= '1' when (V_F_PC3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2686) <= '1' when (V_F_PC3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2687) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_X_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2688) <= '1' when (V_F_PC3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2689) <= '1' when (V_F_PC3DOWNTO2_shadow /= R.F.PC( 3 DOWNTO 2 )) else '0';
dfp_trap_vector(2690) <= '1' when (V_F_PC3DOWNTO2_shadow /= V_X_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2691) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2692) <= '1' when (V_F_PC3DOWNTO2_shadow /= IRIN_ADDR3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2693) <= '1' when (V_F_PC3DOWNTO2_shadow /= EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2694) <= '1' when (V_F_PC3DOWNTO2_shadow /= EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(2695) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2696) <= '1' when (V_F_PC3DOWNTO2_shadow /= XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2697) <= '1' when (V_F_PC3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(2698) <= '1' when (V_F_PC3DOWNTO2_shadow /= IR_ADDR3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2699) <= '1' when (V_F_PC3DOWNTO2_shadow /= V_M_CTRL_PC3DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2700) <= '1' when (V_F_PC3DOWNTO2_shadow /= R_X_CTRL_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2701) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2702) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_F_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2703) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2704) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(2705) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2706) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= R_M_CTRL_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2707) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2708) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2709) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= RIN_X_CTRL_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2710) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2711) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2712) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2713) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= IRIN_ADDR3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2714) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2715) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2716) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= IR.ADDR( 3 DOWNTO 2 )) else '0';
dfp_trap_vector(2717) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2718) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= R_X_CTRL_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2719) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2720) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= RIN_E_CTRL_RD6DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2721) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= RIN_M_CTRL_RD6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2722) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= RIN_X_CTRL_RD6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2723) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= R.X.CTRL.RD( 6 DOWNTO 0 )) else '0';
dfp_trap_vector(2724) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= V_M_CTRL_RD6DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2725) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= R_E_CTRL_RD6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2726) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= V_E_CTRL_RD6DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(2727) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= V_A_CTRL_RD6DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(2728) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= R_A_CTRL_RD6DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2729) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= RIN_A_CTRL_RD6DOWNTO0_intermed_4) else '0';
dfp_trap_vector(2730) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= R_M_CTRL_RD6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2731) <= '1' when (V_M_CTRL_TT_shadow /= V_E_CTRL_TT_shadow_intermed_2) else '0';
dfp_trap_vector(2732) <= '1' when (V_M_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_3) else '0';
dfp_trap_vector(2733) <= '1' when (V_M_CTRL_TT_shadow /= R_A_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(2734) <= '1' when (V_M_CTRL_TT_shadow /= R.M.CTRL.TT) else '0';
dfp_trap_vector(2735) <= '1' when (V_M_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(2736) <= '1' when (V_M_CTRL_TT_shadow /= R_E_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(2737) <= '1' when (V_M_CTRL_TT_shadow /= RIN_M_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(2738) <= '1' when (V_M_CTRL_TT_shadow /= RIN_E_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(2739) <= '1' when (V_M_CTRL_TT_shadow /= V_A_CTRL_TT_shadow_intermed_3) else '0';
dfp_trap_vector(2740) <= '1' when (V_E_CTRL_LD_shadow /= R_A_CTRL_LD_intermed_1) else '0';
dfp_trap_vector(2741) <= '1' when (V_E_CTRL_LD_shadow /= RIN_A_CTRL_LD_intermed_2) else '0';
dfp_trap_vector(2742) <= '1' when (V_E_CTRL_LD_shadow /= R.E.CTRL.LD) else '0';
dfp_trap_vector(2743) <= '1' when (V_E_CTRL_LD_shadow /= RIN_E_CTRL_LD_intermed_1) else '0';
dfp_trap_vector(2744) <= '1' when (V_E_CTRL_LD_shadow /= V_A_CTRL_LD_shadow_intermed_2) else '0';
dfp_trap_vector(2745) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_M_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(2746) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_7) else '0';
dfp_trap_vector(2747) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6) else '0';
dfp_trap_vector(2748) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0';
dfp_trap_vector(2749) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1) else '0';
dfp_trap_vector(2750) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_F_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(2751) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(2752) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(2753) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0';
dfp_trap_vector(2754) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(2755) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(2756) <= '1' when (V_F_PC31DOWNTO12_shadow /= IRIN_ADDR31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(2757) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0';
dfp_trap_vector(2758) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1) else '0';
dfp_trap_vector(2759) <= '1' when (V_F_PC31DOWNTO12_shadow /= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0';
dfp_trap_vector(2760) <= '1' when (V_F_PC31DOWNTO12_shadow /= R.F.PC( 31 DOWNTO 12 )) else '0';
dfp_trap_vector(2761) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(2762) <= '1' when (V_F_PC31DOWNTO12_shadow /= IR_ADDR31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(2763) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_X_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(2764) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(2765) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_X_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(2766) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_7) else '0';
dfp_trap_vector(2767) <= '1' when (V_F_PC31DOWNTO12_shadow /= VIR_ADDR31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(2768) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0';
dfp_trap_vector(2769) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(2770) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R_M_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2771) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2772) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2773) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2774) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_4) else '0';
dfp_trap_vector(2775) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(2776) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R_E_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2777) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_M_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2778) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2779) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2780) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2781) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 )) else '0';
dfp_trap_vector(2782) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(2783) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(2784) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_X_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2785) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R.X.CTRL.TT( 3 DOWNTO 0 )) else '0';
dfp_trap_vector(2786) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2787) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2788) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_M_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2789) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(2790) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2791) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_4) else '0';
dfp_trap_vector(2792) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_5) else '0';
dfp_trap_vector(2793) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5) else '0';
dfp_trap_vector(2794) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_E_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2795) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_W_S_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2796) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_M_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2797) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(2798) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2799) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2800) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R.W.S.TT( 3 DOWNTO 0 )) else '0';
dfp_trap_vector(2801) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2802) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2803) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(2804) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2805) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2806) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_4) else '0';
dfp_trap_vector(2807) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= XC_VECTT3DOWNTO0_shadow_intermed_1) else '0';
dfp_trap_vector(2808) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2809) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2810) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2811) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2812) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= R.A.CTRL.PC( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2813) <= '1' when (V_X_DATA03_shadow /= V_X_DATA03_shadow_intermed_2) else '0';
dfp_trap_vector(2814) <= '1' when (V_X_DATA03_shadow /= DCO_DATA03_intermed_1) else '0';
dfp_trap_vector(2815) <= '1' when (V_X_DATA03_shadow /= RIN_X_DATA03_intermed_1) else '0';
dfp_trap_vector(2816) <= '1' when (V_X_DATA03_shadow /= R_X_DATA03_intermed_1) else '0';
dfp_trap_vector(2817) <= '1' when (V_X_DATA03_shadow /= RIN_X_DATA03_intermed_2) else '0';
dfp_trap_vector(2818) <= '1' when (V_X_DATA03_shadow /= R.X.DATA ( 0 )( 3 )) else '0';
dfp_trap_vector(2819) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= R_M_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(2820) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_6) else '0';
dfp_trap_vector(2821) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0';
dfp_trap_vector(2822) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0';
dfp_trap_vector(2823) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(2824) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(2825) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(2826) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(2827) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= IRIN_ADDR31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(2828) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(2829) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(2830) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= IR.ADDR( 31 DOWNTO 12 )) else '0';
dfp_trap_vector(2831) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= R_X_CTRL_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(2832) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(2833) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= RIN_X_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(2834) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_6) else '0';
dfp_trap_vector(2835) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0';
dfp_trap_vector(2836) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2837) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(2838) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2839) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2840) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2841) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2842) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2843) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2844) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2845) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2846) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2847) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2848) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2849) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2850) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= IR.ADDR( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2851) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2852) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2853) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_F_PC31DOWNTO4_shadow_intermed_1) else '0';
dfp_trap_vector(2854) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_X_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0';
dfp_trap_vector(2855) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= IR_ADDR31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(2856) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R.F.PC( 31 DOWNTO 4 )) else '0';
dfp_trap_vector(2857) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= VIR_ADDR31DOWNTO4_shadow_intermed_2) else '0';
dfp_trap_vector(2858) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_F_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(2859) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_6) else '0';
dfp_trap_vector(2860) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_5) else '0';
dfp_trap_vector(2861) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_6) else '0';
dfp_trap_vector(2862) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_X_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(2863) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1) else '0';
dfp_trap_vector(2864) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_7) else '0';
dfp_trap_vector(2865) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_5) else '0';
dfp_trap_vector(2866) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(2867) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_X_CTRL_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(2868) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= IRIN_ADDR31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(2869) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_M_CTRL_PC31DOWNTO4_shadow_intermed_4) else '0';
dfp_trap_vector(2870) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_M_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(2871) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_7) else '0';
dfp_trap_vector(2872) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_5) else '0';
dfp_trap_vector(2873) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1) else '0';
dfp_trap_vector(2874) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_6) else '0';
dfp_trap_vector(2875) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(2876) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2877) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_7) else '0';
dfp_trap_vector(2878) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= VIR_ADDR3DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2879) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_7) else '0';
dfp_trap_vector(2880) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_M_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2881) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2882) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2883) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_X_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2884) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2885) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R.F.PC( 3 DOWNTO 2 )) else '0';
dfp_trap_vector(2886) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_X_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2887) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2888) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= IRIN_ADDR3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2889) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2890) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1) else '0';
dfp_trap_vector(2891) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_6) else '0';
dfp_trap_vector(2892) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_F_PC3DOWNTO2_shadow_intermed_1) else '0';
dfp_trap_vector(2893) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_6) else '0';
dfp_trap_vector(2894) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= IR_ADDR3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2895) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_M_CTRL_PC3DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2896) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_X_CTRL_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2897) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2898) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_F_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2899) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2900) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= R_E_CTRL_RD7DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2901) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(2902) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= RIN_A_CTRL_RD7DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2903) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= R.M.CTRL.RD ( 7 DOWNTO 0 )) else '0';
dfp_trap_vector(2904) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= R_A_CTRL_RD7DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2905) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= RIN_E_CTRL_RD7DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2906) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= RIN_M_CTRL_RD7DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2907) <= '1' when (V_M_CTRL_PC_shadow /= RIN_D_PC_intermed_4) else '0';
dfp_trap_vector(2908) <= '1' when (V_M_CTRL_PC_shadow /= RIN_A_CTRL_PC_intermed_3) else '0';
dfp_trap_vector(2909) <= '1' when (V_M_CTRL_PC_shadow /= R_A_CTRL_PC_intermed_2) else '0';
dfp_trap_vector(2910) <= '1' when (V_M_CTRL_PC_shadow /= V_E_CTRL_PC_shadow_intermed_2) else '0';
dfp_trap_vector(2911) <= '1' when (V_M_CTRL_PC_shadow /= R.M.CTRL.PC) else '0';
dfp_trap_vector(2912) <= '1' when (V_M_CTRL_PC_shadow /= R_E_CTRL_PC_intermed_1) else '0';
dfp_trap_vector(2913) <= '1' when (V_M_CTRL_PC_shadow /= RIN_M_CTRL_PC_intermed_1) else '0';
dfp_trap_vector(2914) <= '1' when (V_M_CTRL_PC_shadow /= V_A_CTRL_PC_shadow_intermed_3) else '0';
dfp_trap_vector(2915) <= '1' when (V_M_CTRL_PC_shadow /= R_D_PC_intermed_3) else '0';
dfp_trap_vector(2916) <= '1' when (V_M_CTRL_PC_shadow /= RIN_E_CTRL_PC_intermed_2) else '0';
dfp_trap_vector(2917) <= '1' when (V_M_CTRL_PC_shadow /= V_D_PC_shadow_intermed_4) else '0';
dfp_trap_vector(2918) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2919) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2920) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2921) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2922) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2923) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R.M.CTRL.PC( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(2924) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2925) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2926) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2927) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2928) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2929) <= '1' when (V_A_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(2930) <= '1' when (V_A_CTRL_INST20_shadow /= R.A.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(2931) <= '1' when (V_A_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_2) else '0';
dfp_trap_vector(2932) <= '1' when (V_A_CTRL_INST20_shadow /= V_A_CTRL_INST20_shadow_intermed_2) else '0';
dfp_trap_vector(2933) <= '1' when (V_A_CTRL_INST20_shadow /= DE_INST20_shadow_intermed_1) else '0';
dfp_trap_vector(2934) <= '1' when (V_A_CTRL_INST20_shadow /= R_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(2935) <= '1' when (V_A_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_1) else '0';
dfp_trap_vector(2936) <= '1' when (V_A_CTRL_INST20_shadow /= DE_INST20_shadow_intermed_1) else '0';
dfp_trap_vector(2937) <= '1' when (V_A_CTRL_INST20_shadow /= R.A.CTRL.INST( 20 )) else '0';
dfp_trap_vector(2938) <= '1' when (V_A_CTRL_INST24_shadow /= R_A_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(2939) <= '1' when (V_A_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_2) else '0';
dfp_trap_vector(2940) <= '1' when (V_A_CTRL_INST24_shadow /= R.A.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(2941) <= '1' when (V_A_CTRL_INST24_shadow /= V_A_CTRL_INST24_shadow_intermed_2) else '0';
dfp_trap_vector(2942) <= '1' when (V_A_CTRL_INST24_shadow /= DE_INST24_shadow_intermed_1) else '0';
dfp_trap_vector(2943) <= '1' when (V_A_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(2944) <= '1' when (V_A_CTRL_INST24_shadow /= R.A.CTRL.INST( 24 )) else '0';
dfp_trap_vector(2945) <= '1' when (V_A_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_1) else '0';
dfp_trap_vector(2946) <= '1' when (V_A_CTRL_INST24_shadow /= DE_INST24_shadow_intermed_1) else '0';
dfp_trap_vector(2947) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(2948) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(2949) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(2950) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= RIN_X_CTRL_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(2951) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_5) else '0';
dfp_trap_vector(2952) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0';
dfp_trap_vector(2953) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(2954) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= R.X.CTRL.PC( 31 DOWNTO 4 )) else '0';
dfp_trap_vector(2955) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2) else '0';
dfp_trap_vector(2956) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= R_M_CTRL_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(2957) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_5) else '0';
dfp_trap_vector(2958) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(2959) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4) else '0';
dfp_trap_vector(2960) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(2961) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2962) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_5) else '0';
dfp_trap_vector(2963) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_5) else '0';
dfp_trap_vector(2964) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= R_M_CTRL_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2965) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2966) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(2967) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= RIN_X_CTRL_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(2968) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2969) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(2970) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(2971) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(2972) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(2973) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= R.X.CTRL.PC( 3 DOWNTO 2 )) else '0';
dfp_trap_vector(2974) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(2975) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= RIN_E_CTRL_RD6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2976) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= RIN_M_CTRL_RD6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2977) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= R_E_CTRL_RD6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2978) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2979) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(2980) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= R_A_CTRL_RD6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2981) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= RIN_A_CTRL_RD6DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2982) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= R.M.CTRL.RD( 6 DOWNTO 0 )) else '0';
dfp_trap_vector(2983) <= '1' when (V_E_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_2) else '0';
dfp_trap_vector(2984) <= '1' when (V_E_CTRL_TT_shadow /= R_A_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(2985) <= '1' when (V_E_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(2986) <= '1' when (V_E_CTRL_TT_shadow /= R.E.CTRL.TT) else '0';
dfp_trap_vector(2987) <= '1' when (V_E_CTRL_TT_shadow /= RIN_E_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(2988) <= '1' when (V_E_CTRL_TT_shadow /= V_A_CTRL_TT_shadow_intermed_2) else '0';
dfp_trap_vector(2989) <= '1' when (V_X_RESULT6DOWNTO03DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(2990) <= '1' when (V_X_RESULT6DOWNTO03DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2991) <= '1' when (V_X_RESULT6DOWNTO03DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2992) <= '1' when (V_X_RESULT6DOWNTO03DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2993) <= '1' when (V_X_RESULT6DOWNTO03DOWNTO0_shadow /= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 )) else '0';
dfp_trap_vector(2994) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= R_M_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(2995) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(2996) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_4) else '0';
dfp_trap_vector(2997) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0';
dfp_trap_vector(2998) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= R_E_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(2999) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= RIN_M_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(3000) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(3001) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(3002) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= RIN_X_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(3003) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= R.X.CTRL.TT( 3 DOWNTO 0 )) else '0';
dfp_trap_vector(3004) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(3005) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= R_M_CTRL_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(3006) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_5) else '0';
dfp_trap_vector(3007) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0';
dfp_trap_vector(3008) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0';
dfp_trap_vector(3009) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(3010) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(3011) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(3012) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(3013) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(3014) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= R.X.CTRL.PC( 31 DOWNTO 12 )) else '0';
dfp_trap_vector(3015) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(3016) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= RIN_X_CTRL_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(3017) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_5) else '0';
dfp_trap_vector(3018) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(3019) <= '1' when (V_E_CTRL_RD7DOWNTO0_shadow /= R.E.CTRL.RD ( 7 DOWNTO 0 )) else '0';
dfp_trap_vector(3020) <= '1' when (V_E_CTRL_RD7DOWNTO0_shadow /= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(3021) <= '1' when (V_E_CTRL_RD7DOWNTO0_shadow /= RIN_A_CTRL_RD7DOWNTO0_intermed_2) else '0';
dfp_trap_vector(3022) <= '1' when (V_E_CTRL_RD7DOWNTO0_shadow /= R_A_CTRL_RD7DOWNTO0_intermed_1) else '0';
dfp_trap_vector(3023) <= '1' when (V_E_CTRL_RD7DOWNTO0_shadow /= RIN_E_CTRL_RD7DOWNTO0_intermed_1) else '0';
dfp_trap_vector(3024) <= '1' when (V_E_CTRL_PC_shadow /= RIN_D_PC_intermed_3) else '0';
dfp_trap_vector(3025) <= '1' when (V_E_CTRL_PC_shadow /= RIN_A_CTRL_PC_intermed_2) else '0';
dfp_trap_vector(3026) <= '1' when (V_E_CTRL_PC_shadow /= R_A_CTRL_PC_intermed_1) else '0';
dfp_trap_vector(3027) <= '1' when (V_E_CTRL_PC_shadow /= R.E.CTRL.PC) else '0';
dfp_trap_vector(3028) <= '1' when (V_E_CTRL_PC_shadow /= V_A_CTRL_PC_shadow_intermed_2) else '0';
dfp_trap_vector(3029) <= '1' when (V_E_CTRL_PC_shadow /= R_D_PC_intermed_2) else '0';
dfp_trap_vector(3030) <= '1' when (V_E_CTRL_PC_shadow /= RIN_E_CTRL_PC_intermed_1) else '0';
dfp_trap_vector(3031) <= '1' when (V_E_CTRL_PC_shadow /= V_D_PC_shadow_intermed_3) else '0';
dfp_trap_vector(3032) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(3033) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_3) else '0';
dfp_trap_vector(3034) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(3035) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(3036) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0';
dfp_trap_vector(3037) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(3038) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R.E.CTRL.PC( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(3039) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_1) else '0';
dfp_trap_vector(3040) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(3041) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(3042) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(3043) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_4) else '0';
dfp_trap_vector(3044) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2) else '0';
dfp_trap_vector(3045) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(3046) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= R.M.CTRL.PC( 31 DOWNTO 4 )) else '0';
dfp_trap_vector(3047) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_4) else '0';
dfp_trap_vector(3048) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(3049) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0';
dfp_trap_vector(3050) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(3051) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(3052) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_4) else '0';
dfp_trap_vector(3053) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_4) else '0';
dfp_trap_vector(3054) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= R.M.CTRL.PC( 3 DOWNTO 2 )) else '0';
dfp_trap_vector(3055) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(3056) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(3057) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(3058) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(3059) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(3060) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(3061) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(3062) <= '1' when (V_E_CTRL_RD6DOWNTO0_shadow /= RIN_E_CTRL_RD6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(3063) <= '1' when (V_E_CTRL_RD6DOWNTO0_shadow /= R.E.CTRL.RD( 6 DOWNTO 0 )) else '0';
dfp_trap_vector(3064) <= '1' when (V_E_CTRL_RD6DOWNTO0_shadow /= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(3065) <= '1' when (V_E_CTRL_RD6DOWNTO0_shadow /= R_A_CTRL_RD6DOWNTO0_intermed_1) else '0';
dfp_trap_vector(3066) <= '1' when (V_E_CTRL_RD6DOWNTO0_shadow /= RIN_A_CTRL_RD6DOWNTO0_intermed_2) else '0';
dfp_trap_vector(3067) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= R.M.CTRL.TT( 3 DOWNTO 0 )) else '0';
dfp_trap_vector(3068) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(3069) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_3) else '0';
dfp_trap_vector(3070) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0';
dfp_trap_vector(3071) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= R_E_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(3072) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= RIN_M_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(3073) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(3074) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(3075) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= R.M.CTRL.PC( 31 DOWNTO 12 )) else '0';
dfp_trap_vector(3076) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_4) else '0';
dfp_trap_vector(3077) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0';
dfp_trap_vector(3078) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(3079) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(3080) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(3081) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(3082) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(3083) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(3084) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(3085) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_4) else '0';
dfp_trap_vector(3086) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(3087) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(3088) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(3089) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_3) else '0';
dfp_trap_vector(3090) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_3) else '0';
dfp_trap_vector(3091) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(3092) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2) else '0';
dfp_trap_vector(3093) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= R.E.CTRL.PC( 31 DOWNTO 4 )) else '0';
dfp_trap_vector(3094) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(3095) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_3) else '0';
dfp_trap_vector(3096) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_3) else '0';
dfp_trap_vector(3097) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= R.E.CTRL.PC( 3 DOWNTO 2 )) else '0';
dfp_trap_vector(3098) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(3099) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(3100) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(3101) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(3102) <= '1' when (V_E_CTRL_TT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(3103) <= '1' when (V_E_CTRL_TT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_2) else '0';
dfp_trap_vector(3104) <= '1' when (V_E_CTRL_TT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0';
dfp_trap_vector(3105) <= '1' when (V_E_CTRL_TT3DOWNTO0_shadow /= R.E.CTRL.TT( 3 DOWNTO 0 )) else '0';
dfp_trap_vector(3106) <= '1' when (V_E_CTRL_TT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_1) else '0';
dfp_trap_vector(3107) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_3) else '0';
dfp_trap_vector(3108) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(3109) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(3110) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= R.E.CTRL.PC( 31 DOWNTO 12 )) else '0';
dfp_trap_vector(3111) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(3112) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(3113) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_2) else '0';
dfp_trap_vector(3114) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_3) else '0';
dfp_trap_vector(3115) <= '1' when (V_A_CTRL_PC31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(3116) <= '1' when (V_A_CTRL_PC31DOWNTO4_shadow /= R.A.CTRL.PC( 31 DOWNTO 4 )) else '0';
dfp_trap_vector(3117) <= '1' when (V_A_CTRL_PC31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_1) else '0';
dfp_trap_vector(3118) <= '1' when (V_A_CTRL_PC31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_2) else '0';
dfp_trap_vector(3119) <= '1' when (V_A_CTRL_PC31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_2) else '0';
dfp_trap_vector(3120) <= '1' when (V_A_CTRL_PC3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(3121) <= '1' when (V_A_CTRL_PC3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_2) else '0';
dfp_trap_vector(3122) <= '1' when (V_A_CTRL_PC3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_2) else '0';
dfp_trap_vector(3123) <= '1' when (V_A_CTRL_PC3DOWNTO2_shadow /= R.A.CTRL.PC( 3 DOWNTO 2 )) else '0';
dfp_trap_vector(3124) <= '1' when (V_A_CTRL_PC3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_1) else '0';
dfp_trap_vector(3125) <= '1' when (V_A_CTRL_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_2) else '0';
dfp_trap_vector(3126) <= '1' when (V_A_CTRL_PC31DOWNTO12_shadow /= R.A.CTRL.PC( 31 DOWNTO 12 )) else '0';
dfp_trap_vector(3127) <= '1' when (V_A_CTRL_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(3128) <= '1' when (V_A_CTRL_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_1) else '0';
dfp_trap_vector(3129) <= '1' when (V_A_CTRL_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_2) else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_1565 : std_logic_vector(1564 downto 0);
variable or_reduce_783 : std_logic_vector(782 downto 0);
variable or_reduce_392 : std_logic_vector(391 downto 0);
variable or_reduce_196 : std_logic_vector(195 downto 0);
variable or_reduce_98 : std_logic_vector(97 downto 0);
variable or_reduce_49 : std_logic_vector(48 downto 0);
variable or_reduce_25 : std_logic_vector(24 downto 0);
variable or_reduce_13 : std_logic_vector(12 downto 0);
variable or_reduce_7 : std_logic_vector(6 downto 0);
variable or_reduce_4 : std_logic_vector(3 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_1565 := dfp_trap_vector(3129 downto 1565) OR dfp_trap_vector(1564 downto 0);
or_reduce_783 := or_reduce_1565(1564 downto 782) OR ("0" & or_reduce_1565(781 downto 0));
or_reduce_392 := or_reduce_783(782 downto 391) OR ("0" & or_reduce_783(390 downto 0));
or_reduce_196 := or_reduce_392(391 downto 196) OR or_reduce_392(195 downto 0);
or_reduce_98 := or_reduce_196(195 downto 98) OR or_reduce_196(97 downto 0);
or_reduce_49 := or_reduce_98(97 downto 49) OR or_reduce_98(48 downto 0);
or_reduce_25 := or_reduce_49(48 downto 24) OR ("0" & or_reduce_49(23 downto 0));
or_reduce_13 := or_reduce_25(24 downto 12) OR ("0" & or_reduce_25(11 downto 0));
or_reduce_7 := or_reduce_13(12 downto 6) OR ("0" & or_reduce_13(5 downto 0));
or_reduce_4 := or_reduce_7(6 downto 3) OR ("0" & or_reduce_7(2 downto 0));
or_reduce_2 := or_reduce_4(3 downto 2) OR or_reduce_4(1 downto 0);
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0';
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then ir <= irin; end if;
end if;
end process;
dummy <= '1';
end;
| mit | 5d919e90032dcf48b4f1b5af318b8402 | 0.678423 | 2.253987 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/ahbstat.vhd | 2 | 4,260 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use gaisler.misc.all;
entity ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end entity;
architecture rtl of ahbstat is
type reg_type is record
addr : std_logic_vector(31 downto 0); --failing address
hsize : std_logic_vector(2 downto 0); --ahb signals for failing op.
hmaster : std_logic_vector(3 downto 0);
hwrite : std_ulogic;
hresp : std_logic_vector(1 downto 0);
newerr : std_ulogic; --new error detected
cerror : std_ulogic; --correctable error detected
pirq : std_ulogic;
end record;
signal r, rin : reg_type;
constant VERSION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBSTAT, 0, VERSION, pirq),
1 => apb_iobar(paddr, pmask));
begin
comb : process(rst, ahbmi, ahbsi, stati, apbi, r) is
variable v : reg_type;
variable prdata : std_logic_vector(31 downto 0);
variable vpirq : std_logic_vector(NAHBIRQ - 1 downto 0);
variable ce : std_ulogic; --correctable error
begin
v := r; vpirq := (others => '0'); prdata := (others => '0'); v.pirq := '0';
ce := orv(stati.cerror(0 to nftslv-1));
case apbi.paddr(2) is
when '0' => --status values
prdata(2 downto 0) := r.hsize;
prdata(6 downto 3) := r.hmaster;
prdata(7) := r.hwrite;
prdata(8) := r.newerr;
prdata(9) := r.cerror;
when others => --failing address
prdata := r.addr;
end case;
--writes. data is written in setup cycle so that r.newerr is updated
--when hready = '1'
if (apbi.psel(pindex) and not apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2) is
when '0' =>
v.newerr := apbi.pwdata(8);
v.cerror := apbi.pwdata(9);
when others => null;
end case;
end if;
v.hresp := ahbmi.hresp;
if (ahbsi.hready = '1') and (r.newerr = '0') then
if (r.hresp = HRESP_ERROR) or (ce = '1') then v.newerr := '1';
v.cerror := ce;
else
v.addr := ahbsi.haddr;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hwrite := ahbsi.hwrite;
end if;
end if;
--irq generation
v.pirq := v.newerr and not r.newerr;
vpirq(pirq) := r.pirq;
--reset
if rst = '0' then
v.newerr := '0'; v.cerror := '0';
end if;
rin <= v;
apbo.prdata <= prdata;
apbo.pirq <= vpirq;
end process;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("ahbstat" & tost(pindex) &
": AHB status unit rev " & tost(VERSION) &
", irq " & tost(pirq));
-- pragma translate_on
end architecture;
| mit | 0b970c764bba0748a8baeaa0a3425c47 | 0.597887 | 3.520661 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/jtag/jtagcom.vhd | 2 | 5,510 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Debug Interface with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom is
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type
);
end;
architecture rtl of jtagcom is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type state_type is (shft, ahb);
type reg_type is record
addr : std_logic_vector(34 downto 0);
data : std_logic_vector(32 downto 0);
state : state_type;
tck : std_logic_vector(nsync-1 downto 0);
tck2 : std_ulogic;
trst : std_logic_vector(nsync-1 downto 0);
tdi : std_logic_vector(nsync-1 downto 0);
shift : std_logic_vector(nsync-1 downto 0);
shift2: std_ulogic;
shift3: std_ulogic;
asel : std_logic_vector(nsync-1 downto 0);
dsel : std_logic_vector(nsync-1 downto 0);
tdi2 : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process (rst, r, tapo, dmao)
variable v : reg_type;
variable redge : std_ulogic;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
begin
v := r;
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
write := r.addr(34); seq := r.data(32);
v.tck(0) := r.tck(nsync-1); v.tck(nsync-1) := tapo.tck; v.tck2 := r.tck(0); v.shift2 := r.shift(0); v.shift3 := r.shift2;
v.trst(0) := r.trst(nsync-1); v.trst(nsync-1) := tapo.reset;
v.tdi(0) := r.tdi(nsync-1); v.tdi(nsync-1) := tapo.tdi;
v.shift(0) := r.shift(nsync-1); v.shift(nsync-1) := tapo.shift;
v.asel(0) := r.asel(nsync-1); v.asel(nsync-1) := asel;
v.dsel(0) := r.dsel(nsync-1); v.dsel(nsync-1) := dsel;
v.tdi2 := r.tdi(0);
redge := not r.tck2 and r.tck(0);
vdmai.address := r.addr(31 downto 0); vdmai.wdata := r.data(31 downto 0);
vdmai.start := '0'; vdmai.burst := '0'; vdmai.write := write;
vdmai.busy := '0'; vdmai.irq := '0'; vdmai.size := r.addr(33 downto 32);
vtapi.en := r.asel(0) or r.dsel(0);
if r.asel(0) = '1' then vtapi.tdo := r.addr(0); else vtapi.tdo := r.data(0); end if;
case r.state is
when shft =>
if (r.asel(0) or r.dsel(0)) = '1' then
if r.shift2 = '1' then
if redge = '1' then
if r.asel(0) = '1' then v.addr := r.tdi2 & r.addr(34 downto 1); end if;
if r.dsel(0) = '1' then v.data := r.tdi2 & r.data(32 downto 1); end if;
end if;
elsif r.shift3 = '1' then
if (r.asel(0) and not write) = '1' then v.state := ahb; end if;
if (r.dsel(0) and (write or (not write and seq))) = '1' then -- data register
v.state := ahb;
if (seq and not write) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
end if;
end if;
vdmai.size := "00";
when ahb =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.data(31 downto 0) := dmao.rdata;
v.state := shft;
if (write and seq) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
else
vdmai.start := '1';
end if;
end case;
if (rst = '0') or (r.trst(0) = '1') then
v.state := shft; v.addr(34) := '0'; v.data(32) := '0';
end if;
rin <= v; dmai <= vdmai; tapi <= vtapi;
end process;
reg : process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end;
| mit | d7ff56a293230495d5fdaf1907f96842 | 0.552995 | 3.285629 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/virage/memory_virage.vhd | 1 | 16,095 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_virage_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Virage rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss1_128x32cm4sw0ab;
use virage.hdss1_256x32cm4sw0ab;
use virage.hdss1_512x32cm4sw0ab;
use virage.hdss1_512x38cm4sw0ab;
use virage.hdss1_1024x32cm4sw0ab;
use virage.hdss1_2048x32cm8sw0ab;
use virage.hdss1_4096x36cm8sw0ab;
use virage.hdss1_16384x8cm16sw0;
-- pragma translate_on
entity virage_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of virage_syncram is
component hdss1_128x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_256x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x38cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_1024x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_2048x32cm8sw0ab
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end component;
signal d, q, gnd : std_logic_vector(40 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc : std_ulogic;
constant synopsys_bug : std_logic_vector(40 downto 0) := (others => '0');
begin
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(40 downto dbits) <= synopsys_bug(40 downto dbits);
dataout <= q(dbits -1 downto 0);
a7d32 : if (abits <= 7) and (dbits <= 32) generate
id0 : hdss1_128x32cm4sw0ab
port map (a(6 downto 0), gnd(6 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss1_256x32cm4sw0ab
port map (a(7 downto 0), gnd(7 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss1_512x32cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss1_512x38cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(37 downto 0), gnd(37 downto 0), q(37 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a10d32 : if (abits = 10) and (dbits <= 32) generate
id0 : hdss1_1024x32cm4sw0ab
port map (address(9 downto 0), gnd(9 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a11d32 : if (abits = 11) and (dbits <= 32) generate
id0 : hdss1_2048x32cm8sw0ab
port map (address(10 downto 0), gnd(10 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a12d36 : if (abits = 12) and (dbits <= 36) generate
id0 : hdss1_4096x36cm8sw0ab
port map (address(11 downto 0), gnd(11 downto 0), clk,
d(35 downto 0), gnd(35 downto 0), q(35 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a14d8 : if (abits = 14) and (dbits <= 8) generate
id0 : hdss1_16384x8cm16sw0
port map (address(13 downto 0), clk,
d(7 downto 0), q(7 downto 0),
enable, vcc, Write);
end generate;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_512x38cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_dp is
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of virage_syncram_dp is
component hdss2_64x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_128x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_256x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x38cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_8192x8cm16sw0ab
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, d2, a1, a2, q1, q2, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain1; d1(40 downto dbits) <= (others => '0');
d2(dbits-1 downto 0) <= datain2; d2(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= address1; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= address2; a2(40 downto abits) <= (others => '0');
dataout1 <= q1(dbits-1 downto 0); dataout2 <= q2(dbits-1 downto 0);
a6d32 : if (abits <= 6) and (dbits <= 32) generate
id0 : hdss2_64x32cm4sw0ab
port map (a1(5 downto 0), gnd(5 downto 0), a2(5 downto 0),
gnd(5 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a7d32 : if (abits = 7) and (dbits <= 32) generate
id0 : hdss2_128x32cm4sw0ab
port map (a1(6 downto 0), gnd(6 downto 0), a2(6 downto 0),
gnd(6 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss2_256x32cm4sw0ab
port map (a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0),
gnd(7 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss2_512x32cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss2_512x38cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(37 downto 0), gnd(37 downto 0), d2(37 downto 0), gnd(37 downto 0),
q1(37 downto 0), q2(37 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.rfss2_136x32cm2sw0ab;
use virage.rfss2_136x40cm2sw0ab;
use virage.rfss2_168x32cm2sw0ab;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_2p is
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture rtl of virage_syncram_2p is
component rfss2_136x32cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
component rfss2_136x40cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, a1, a2, q1, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain; d1(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddress; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddress; a2(40 downto abits) <= (others => '0');
dataout <= q1(dbits-1 downto 0);
id0 : rfss2_136x40cm2sw0ab
port map (
a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0), gnd(7 downto 0),
wclk, rclk, d1(39 downto 0), gnd(39 downto 0),
q1(39 downto 0),
vcc, write, gnd(0), gnd(0), gnd(0),
renable, vcc, gnd(0), gnd(0), gnd(0), gnd(0));
end;
| mit | ae802dd9d9700138533078c4949b6d4c | 0.621062 | 2.913122 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_fetch.vhd | 1 | 6,304 | ---------------------------------------------------------------------
-- Instruction fetch
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- The first stage of the LXP32 pipeline.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_fetch is
generic(
START_ADDR: std_logic_vector(31 downto 0)
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
lli_re_o: out std_logic;
lli_adr_o: out std_logic_vector(29 downto 0);
lli_dat_i: in std_logic_vector(31 downto 0);
lli_busy_i: in std_logic;
word_o: out std_logic_vector(31 downto 0);
current_ip_o: out std_logic_vector(29 downto 0);
next_ip_o: out std_logic_vector(29 downto 0);
valid_o: out std_logic;
ready_i: in std_logic;
jump_valid_i: in std_logic;
jump_dst_i: in std_logic_vector(29 downto 0);
jump_ready_o: out std_logic
);
end entity;
architecture rtl of lxp32_fetch is
signal init: std_logic:='1';
signal init_cnt: unsigned(7 downto 0):=(others=>'0');
signal fetch_addr: std_logic_vector(29 downto 0):=START_ADDR(31 downto 2);
signal next_word: std_logic;
signal suppress_re: std_logic:='0';
signal re: std_logic;
signal requested: std_logic:='0';
signal fifo_rst: std_logic;
signal fifo_we: std_logic;
signal fifo_din: std_logic_vector(31 downto 0);
signal fifo_re: std_logic;
signal fifo_dout: std_logic_vector(31 downto 0);
signal fifo_empty: std_logic;
signal fifo_full: std_logic;
signal jr: std_logic:='0';
signal next_ip: std_logic_vector(fetch_addr'range);
signal current_ip: std_logic_vector(fetch_addr'range);
begin
-- INIT state machine (to initialize all registers)
-- All CPU registers are expected to be zero-initialized after reset.
-- Since these registers are implemented as a RAM block, we perform
-- the initialization sequentially by generating "mov rN, 0" instructions
-- for each N from 0 to 255.
--
-- With SRAM-based FPGAs, flip-flops and RAM blocks have deterministic
-- state after configuration. On these technologies the CPU can operate
-- without reset and the initialization procedure described above is not
-- needed. However, the initialization is still performed as usual when
-- external reset signal is asserted.
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
init<='0';
init_cnt<=(others=>'0');
else
if init='0' and ready_i='1' then
init_cnt<=init_cnt+1;
if init_cnt=X"FF" then
init<='1';
end if;
end if;
end if;
end if;
end process;
-- FETCH state machine
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
fetch_addr<=START_ADDR(31 downto 2);
requested<='0';
jr<='0';
suppress_re<='0';
next_ip<=(others=>'-');
else
jr<='0';
-- Suppress LLI request if jump signal is active but will not be processed
-- in this cycle. Helps to reduce jump latency with high-latency LLI slaves.
-- Note: gating "re" with "jump_valid_i and not jr" asynchronously would
-- reduce jump latency even more, but we really want to avoid too large
-- clock-to-out on LLI outputs.
suppress_re<=jump_valid_i and not jr and not next_word;
if lli_busy_i='0' then
requested<=re and not (jump_valid_i and not jr);
end if;
if next_word='1' then
-- It's not immediately obvious why, but current_ip and next_ip will contain
-- the addresses of the current instruction and the next instruction to be
-- fetched, respectively, by the time the instruction is passed to the decode
-- stage. Basically, this is because when either the decoder or the IBUS
-- stalls, the fetch_addr counter will also stop incrementing.
next_ip<=fetch_addr;
current_ip<=next_ip;
if jump_valid_i='1' and jr='0' then
fetch_addr<=jump_dst_i;
jr<='1';
else
fetch_addr<=std_logic_vector(unsigned(fetch_addr)+1);
end if;
end if;
end if;
end if;
end process;
next_word<=(fifo_empty or ready_i) and not lli_busy_i and init;
re<=(fifo_empty or ready_i) and init and not suppress_re;
lli_re_o<=re;
lli_adr_o<=fetch_addr;
jump_ready_o<=jr;
-- Small instruction buffer
fifo_rst<=rst_i or (jump_valid_i and not jr);
fifo_we<=requested and not lli_busy_i;
fifo_din<=lli_dat_i;
fifo_re<=ready_i and not fifo_empty;
ubuf_inst: entity work.lxp32_ubuf(rtl)
generic map(
DATA_WIDTH=>32
)
port map(
clk_i=>clk_i,
rst_i=>fifo_rst,
we_i=>fifo_we,
d_i=>fifo_din,
re_i=>fifo_re,
d_o=>fifo_dout,
empty_o=>fifo_empty,
full_o=>fifo_full
);
next_ip_o<=next_ip;
current_ip_o<=current_ip;
word_o<=fifo_dout when init='1' else X"40"&std_logic_vector(init_cnt)&X"0000";
valid_o<=not fifo_empty or not init;
-- Note: the following code contains a few simulation-only assertions
-- to check that current_ip and next_ip signals, used in procedure calls
-- and interrupts, are correct.
-- This code should be ignored by a synthesizer since it doesn't drive
-- any signals, but we also surround it by metacomments, just in case.
-- synthesis translate_off
process (clk_i) is
type Pair is record
addr: std_logic_vector(fetch_addr'range);
data: std_logic_vector(31 downto 0);
end record;
type Pairs is array (7 downto 0) of Pair;
variable buf: Pairs;
variable count: integer range buf'range:=0;
variable current_pair: Pair;
begin
if rising_edge(clk_i) then
if fifo_rst='1' then -- jump
count:=0;
elsif fifo_we='1' then -- LLI returned data
current_pair.data:=fifo_din;
buf(count):=current_pair;
count:=count+1;
end if;
if re='1' and lli_busy_i='0' then -- data requested
current_pair.addr:=fetch_addr;
end if;
if fifo_empty='0' and fifo_rst='0' then -- fetch output is valid
assert count>0
report "Fetch: buffer should be empty"
severity failure;
assert buf(0).data=fifo_dout
report "Fetch: incorrect data"
severity failure;
assert buf(0).addr=current_ip
report "Fetch: incorrect current_ip"
severity failure;
assert std_logic_vector(unsigned(buf(0).addr)+1)=next_ip
report "Fetch: incorrect next_ip"
severity failure;
if ready_i='1' then
buf(buf'high-1 downto 0):=buf(buf'high downto 1); -- we don't care about the highest item
count:=count-1;
end if;
end if;
end if;
end process;
-- synthesis translate_on
end architecture;
| mit | 74b179b699f006a26c8c513495eccdd0 | 0.676555 | 3.029313 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled4/API_plus_CipherCore/CypherCore.vhd | 1 | 14,264 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 4) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(3 downto 0);
signal AsconInput : std_logic_vector(127 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput;
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,RUN_CIPHER_4,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "10000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "0000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "0000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "0000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "0000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_4 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
CurrState := RUN_CIPHER_4;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
| gpl-3.0 | ed141e86031da952ec514c3adc956345 | 0.5197 | 3.39054 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/ahbmst.vhd | 2 | 5,350 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbmst
-- File: ahbmst.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Generic AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity ahbmst is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of ahbmst is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
start : std_ulogic;
retry : std_ulogic;
grant : std_ulogic;
active : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(ahbi, dmai, rst, r)
variable v : reg_type;
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(9 downto 0); -- next sequential address
variable hbusreq : std_ulogic; -- bus request
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; ready := '0'; mexc := '0'; retry := '0'; inc := (others => '0');
hprot := conv_std_logic_vector(chprot, 4); -- non-cached supervisor data
xhirq := (others => '0'); xhirq(hirq) := dmai.irq;
haddr := dmai.address; hbusreq := dmai.start; hwdata := dmai.wdata;
newaddr := dmai.address(9 downto 0);
if INCADDR > 0 then
inc(conv_integer(dmai.size)) := '1';
newaddr := haddr(9 downto 0) + inc;
end if;
if dmai.burst = '0' then hburst := HBURST_SINGLE;
else hburst := HBURST_INCR; end if;
if dmai.start = '1' then
if (r.active and dmai.burst and not r.retry) = '1' then
haddr(9 downto 0) := newaddr;
if dmai.busy = '1' then htrans := HTRANS_BUSY;
else htrans := HTRANS_SEQ; end if;
hburst := HBURST_INCR;
else htrans := HTRANS_NONSEQ; end if;
else htrans := HTRANS_IDLE; end if;
if r.active = '1' then
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => ready := '1';
when HRESP_RETRY | HRESP_SPLIT=> retry := '1';
when others => ready := '1'; mexc := '1';
end case;
end if;
if ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT)) then
v.retry := not ahbi.hready;
else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
v.start := '0';
if ahbi.hready = '1' then
v.grant := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) or (htrans = HTRANS_BUSY) then
v.active := r.grant; v.start := r.grant;
else
v.active := '0';
end if;
end if;
if rst = '0' then v.retry := '0'; v.active := '0'; end if;
rin <= v;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= dmai.wdata;
ahbo.hconfig <= hconfig;
ahbo.hlock <= '0';
ahbo.hwrite <= dmai.write;
ahbo.hsize <= '0' & dmai.size;
ahbo.hburst <= hburst;
ahbo.hprot <= hprot;
ahbo.hirq <= xhirq;
ahbo.hindex <= hindex;
dmao.start <= r.start;
dmao.active <= r.active;
dmao.ready <= ready;
dmao.mexc <= mexc;
dmao.retry <= retry;
dmao.haddr <= newaddr;
dmao.rdata <= ahbi.hrdata;
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
| mit | 705581e26b17eb240727b580237d639c | 0.585607 | 3.578595 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmulrue.vhd | 2 | 3,049 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulrue
-- File: mmulrue.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulrue is
generic (
position : integer;
entries : integer := 8 );
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type );
end mmulrue;
architecture rtl of mmulrue is
constant entries_log : integer := log2(entries);
type lru_rtype is record
pos : std_logic_vector(entries_log-1 downto 0);
movetop : std_logic;
-- pragma translate_off
dummy : std_logic;
-- pragma translate_on
end record;
signal c,r : lru_rtype;
begin
p0: process (rst, r, c, lruei)
variable v : lru_rtype;
variable ov : mmulrue_out_type;
begin
v := r; ov := mmulrue_out_none;
-- #init
if (r.movetop) = '1' then
if (lruei.fromleft) = '0' then
v.pos := lruei.left(entries_log-1 downto 0);
v.movetop := '0';
end if;
elsif (lruei.fromright) = '1' then
v.pos := lruei.right(entries_log-1 downto 0);
v.movetop := not lruei.clear;
end if;
if (lruei.touch and not lruei.clear) = '1' then -- touch request
if (v.pos = lruei.pos(entries_log-1 downto 0)) then -- check
v.movetop := '1';
end if;
end if;
if ((rst) = '0') or (lruei.flush = '1') then
v.pos := conv_std_logic_vector(position, entries_log);
v.movetop := '0';
end if;
--# Drive signals
ov.pos(entries_log-1 downto 0) := r.pos;
ov.movetop := r.movetop;
lrueo <= ov;
c <= v;
end process p0;
p1: process (clk)
begin if rising_edge(clk) then r <= c; end if;
end process p1;
end rtl;
| mit | 853e51d85b2f50edacc991eff35875c2 | 0.591013 | 3.647129 | false | false | false | false |
makestuff/seven-seg | vhdl/seven_seg.vhdl | 1 | 3,125 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity seven_seg is
generic (
-- This can be overridden to change the refresh rate. The anode pattern will change at a
-- frequency given by F(clk_in) / (2**COUNTER_WIDTH). So for a 50MHz clk_in and
-- COUNTER_WIDTH=18, the anode pattern changes at ~191Hz, which means each digit gets
-- refreshed at ~48Hz.
COUNTER_WIDTH : integer := 18
);
port(
clk_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
dots_in : in std_logic_vector(3 downto 0);
segs_out : out std_logic_vector(7 downto 0);
anodes_out : out std_logic_vector(3 downto 0)
);
end entity;
architecture rtl of seven_seg is
signal count : unsigned(COUNTER_WIDTH-1 downto 0) := (others => '0');
signal count_next : unsigned(COUNTER_WIDTH-1 downto 0);
signal anodeSelect : std_logic_vector(1 downto 0);
signal nibble : std_logic_vector(3 downto 0);
signal segs : std_logic_vector(6 downto 0);
signal dot : std_logic;
begin
-- Infer counter register
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
count <= count_next;
end if;
end process;
-- Increment counter and derive anode select from top two bits
count_next <= count + 1;
anodeSelect <= std_logic_vector(count(COUNTER_WIDTH-1 downto COUNTER_WIDTH-2));
-- Drive anodes
with anodeSelect select anodes_out <=
"0111" when "00",
"1011" when "01",
"1101" when "10",
"1110" when others;
-- Select the appropriate bit from dots_in
with anodeSelect select dot <=
not(dots_in(3)) when "00",
not(dots_in(2)) when "01",
not(dots_in(1)) when "10",
not(dots_in(0)) when others;
-- Choose a nibble to display
with anodeSelect select nibble <=
data_in(15 downto 12) when "00",
data_in(11 downto 8) when "01",
data_in(7 downto 4) when "10",
data_in(3 downto 0) when others;
-- Decode chosen nibble
with nibble select segs <=
"1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
-- Drive segs_out
segs_out <= dot & segs;
end architecture;
| gpl-3.0 | 34b33331f4ebcc0308306c5f40f9fb59 | 0.67744 | 3.16616 | false | false | false | false |
franz/pocl | examples/accel/rtl/platform/minidebugger.vhdl | 2 | 11,628 | -- Copyright (c) 2017-2019 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Minimal debugger, no breakpoint capabilities or bustrace
-- Project :
-------------------------------------------------------------------------------
-- File : minidebugger.vhdl
-- Author : Kati Tervo
-- Company : Tampere University
-- Created : 2017-09-19
-- Last update: 2019-07-05
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-09-19 1.0 katte Created
-- 2019-07-05 1.0 katte Added AQL queue iterators
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package register_pkg is
-- Status registers
constant TTA_STATUS : integer := 0;
constant TTA_PC : integer := 1;
constant TTA_CYCLECNT : integer := 2;
constant TTA_CYCLECNT_HIGH : integer := 3;
constant TTA_LOCKCNT : integer := 4;
constant TTA_LOCKCNT_HIGH : integer := 5;
constant aql_addresspace_start_c : integer := 2**6;
constant AQL_READ_IDX_LOW : integer := 0 + aql_addresspace_start_c;
constant AQL_READ_IDX_HIGH : integer := 1 + aql_addresspace_start_c;
constant AQL_WRITE_IDX_LOW : integer := 2 + aql_addresspace_start_c;
constant AQL_WRITE_IDX_HIGH : integer := 3 + aql_addresspace_start_c;
constant control_addresspace_start_c : integer := 2**7;
-- control register space
constant TTA_DEBUG_CMD : integer := 0 + control_addresspace_start_c;
constant info_addresspace_start_c : integer := 2**7 + 2**6;
-- info registers space: 0xC0..0xff
constant TTA_DEVICECLASS : integer := 0 + info_addresspace_start_c;
constant TTA_DEVICE_ID : integer := 1 + info_addresspace_start_c;
constant TTA_INTERFACE_TYPE : integer := 2 + info_addresspace_start_c;
constant TTA_CORE_COUNT : integer := 3 + info_addresspace_start_c;
constant TTA_CTRL_SIZE : integer := 4 + info_addresspace_start_c;
constant TTA_DMEM_SIZE : integer := 5 + info_addresspace_start_c;
constant TTA_IMEM_SIZE : integer := 6 + info_addresspace_start_c;
constant TTA_PMEM_SIZE : integer := 7 + info_addresspace_start_c;
constant DEBUG_CMD_RESET : integer := 0;
constant DEBUG_CMD_CONTINUE : integer := 1;
constant DEBUG_CMD_BREAK : integer := 2;
end register_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.register_pkg.all;
use work.tce_util.all;
entity minidebugger is
generic (
data_width_g : integer := 32;
axi_addr_width_g : integer;
core_count_g : integer;
core_id_width_g : integer;
imem_data_width_g : integer;
imem_addr_width_g : integer;
dmem_data_width_g : integer;
dmem_addr_width_g : integer;
pmem_data_width_g : integer;
pmem_addr_width_g : integer
);
port (
clk : in std_logic;
rstx : in std_logic;
-- AXI slave membus
avalid_in : in std_logic;
aready_out : out std_logic;
aaddr_in : in std_logic_vector(axi_addr_width_g-2-1 downto 0);
awren_in : in std_logic;
astrb_in : in std_logic_vector(data_width_g/8-1 downto 0);
adata_in : in std_logic_vector(data_width_g-1 downto 0);
rvalid_out : out std_logic;
rready_in : in std_logic;
rdata_out : out std_logic_vector(data_width_g-1 downto 0);
core_sel_in : in std_logic_vector(core_id_width_g-1 downto 0);
tta_lockrq_out : out std_logic_vector(core_count_g-1 downto 0);
tta_nreset_out : out std_logic_vector(core_count_g-1 downto 0);
tta_pc_in : in std_logic_vector(core_count_g*imem_addr_width_g-1
downto 0);
tta_locked_in : in std_logic_vector(core_count_g-1 downto 0);
tta_lockcnt_in : in std_logic_vector(core_count_g*64-1 downto 0);
tta_cyclecnt_in : in std_logic_vector(core_count_g*64-1 downto 0);
tta_read_idx_in : in std_logic_vector(64-1 downto 0);
tta_read_idx_clear_out : out std_logic_vector(0 downto 0);
tta_write_idx_out : out std_logic_vector(64-1 downto 0)
);
end minidebugger;
architecture rtl of minidebugger is
constant device_class_c : integer := 16#774#;
constant device_id_c : integer := 16#12345678#;
constant interface_type_c : integer := 2;
constant ctrl_size_c : integer := 2**10;
constant dmem_size_c : integer := 2**(dmem_addr_width_g+
bit_width(dmem_data_width_g/8));
constant pmem_size_c : integer := 2**(pmem_addr_width_g+
bit_width(pmem_data_width_g/8));
constant imem_size_c : integer := 2**(imem_addr_width_g+
bit_width(imem_data_width_g/8));
signal tta_nreset_r, tta_nreset_rr : std_logic_vector(tta_nreset_out'range);
signal tta_lockrq_r, tta_lockrq_rr : std_logic_vector(tta_lockrq_out'range);
signal tta_locked_r, tta_locked_rr : std_logic_vector(tta_locked_in'range);
signal tta_lockcnt_r : std_logic_vector(tta_lockcnt_in'range);
signal tta_cyclecnt_r : std_logic_vector(tta_cyclecnt_in'range);
signal tta_pc_r, tta_pc_rr : std_logic_vector(tta_pc_in'range);
signal idx_reset_r : std_logic;
signal write_idx_r, read_idx_r : std_logic_vector(64-1 downto 0);
signal rvalid_r : std_logic;
signal rdata_r : std_logic_vector(rdata_out'range);
begin
sync : process(clk, rstx)
variable core_id_v : integer;
variable command : std_logic_vector(3 downto 0);
begin
if (rstx = '0') then
tta_nreset_r <= (others => '0');
tta_nreset_rr <= (others => '0');
tta_lockrq_r <= (others => '0');
tta_lockrq_rr <= (others => '0');
tta_locked_r <= (others => '0');
tta_locked_rr <= (others => '0');
tta_lockcnt_r <= (others => '0');
tta_cyclecnt_r <= (others => '0');
tta_pc_r <= (others => '0');
tta_pc_rr <= (others => '0');
rvalid_r <= '0';
rdata_r <= (others => '0');
read_idx_r <= (others => '0');
write_idx_r <= (others => '0');
idx_reset_r <= '0';
elsif rising_edge(clk) then
idx_reset_r <= tta_nreset_r(0);
if rready_in = '1' then
rvalid_r <= '0';
end if;
-- Doubly registered to decouple the (high fanout) signals
tta_locked_r <= tta_locked_in;
tta_locked_rr <= tta_locked_r;
tta_lockrq_rr <= tta_lockrq_r;
tta_nreset_rr <= tta_nreset_r;
tta_lockcnt_r <= tta_lockcnt_in;
tta_cyclecnt_r <= tta_cyclecnt_in;
tta_pc_r <= tta_pc_in;
tta_pc_rr <= tta_pc_r;
read_idx_r <= tta_read_idx_in;
if avalid_in = '1' and rvalid_r = '0' then
core_id_v := to_integer(unsigned(aaddr_in(aaddr_in'high downto 8)));
if awren_in = '0' then
rvalid_r <= '1';
case to_integer(unsigned(aaddr_in(7 downto 0))) is
when TTA_STATUS =>
rdata_r <= (others => '0');
if core_id_v < core_count_g then
rdata_r(2 downto 0) <= (not tta_nreset_r(core_id_v))
& tta_lockrq_r(core_id_v)
& tta_locked_rr(core_id_v);
end if;
when TTA_PC =>
rdata_r <= (others => '0');
rdata_r(tta_pc_rr'range) <= tta_pc_rr;
when TTA_CYCLECNT =>
rdata_r <= tta_cyclecnt_r(32-1 downto 0);
when TTA_CYCLECNT_HIGH =>
rdata_r <= tta_cyclecnt_r(64-1 downto 32);
when TTA_LOCKCNT =>
rdata_r <= tta_lockcnt_r(32-1 downto 0);
when TTA_LOCKCNT_HIGH =>
rdata_r <= tta_lockcnt_r(64-1 downto 32);
when AQL_READ_IDX_LOW =>
rdata_r <= read_idx_r(32-1 downto 0);
when AQL_READ_IDX_HIGH =>
rdata_r <= read_idx_r(64-1 downto 32);
when AQL_WRITE_IDX_LOW =>
rdata_r <= write_idx_r(32-1 downto 0);
when AQL_WRITE_IDX_HIGH =>
rdata_r <= write_idx_r(64-1 downto 32);
when TTA_DEVICECLASS =>
rdata_r <= std_logic_vector(to_unsigned(device_class_c, 32));
when TTA_DEVICE_ID =>
rdata_r <= std_logic_vector(to_unsigned(device_id_c, 32));
when TTA_INTERFACE_TYPE =>
rdata_r <= std_logic_vector(to_unsigned(interface_type_c, 32));
when TTA_CORE_COUNT =>
rdata_r <= std_logic_vector(to_unsigned(core_count_g, 32));
when TTA_CTRL_SIZE =>
rdata_r <= std_logic_vector(to_unsigned(ctrl_size_c, 32));
when TTA_DMEM_SIZE =>
rdata_r <= std_logic_vector(to_unsigned(dmem_size_c, 32));
when TTA_IMEM_SIZE =>
rdata_r <= std_logic_vector(to_unsigned(imem_size_c, 32));
when TTA_PMEM_SIZE =>
rdata_r <= std_logic_vector(to_unsigned(pmem_size_c, 32));
when others =>
rdata_r <= (others => '0');
end case;
else
if to_integer(unsigned(aaddr_in(7 downto 0))) = TTA_DEBUG_CMD then
command := adata_in(command'range);
if core_id_v < core_count_g then
if command(DEBUG_CMD_CONTINUE) = '1' then
tta_nreset_r(core_id_v) <= '1';
tta_lockrq_r(core_id_v) <= '0';
end if;
if command(DEBUG_CMD_BREAK) = '1' then
tta_lockrq_r(core_id_v) <= '1';
end if;
if command(DEBUG_CMD_RESET) = '1' then
tta_nreset_r(core_id_v) <= '0';
end if;
end if;
elsif to_integer(unsigned(aaddr_in(7 downto 0))) = AQL_WRITE_IDX_LOW then
write_idx_r <= std_logic_vector(unsigned(write_idx_r)
+ unsigned(adata_in));
end if;
end if;
end if;
end if;
end process;
aready_out <= not rvalid_r;
rdata_out <= rdata_r;
rvalid_out <= rvalid_r;
tta_lockrq_out <= tta_lockrq_rr;
tta_nreset_out <= tta_nreset_rr;
tta_write_idx_out <= write_idx_r;
tta_read_idx_clear_out(0) <= not idx_reset_r;
end architecture rtl;
| mit | f0fb39e2d172da2b9a499a65a5813391 | 0.560544 | 3.396028 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/axcelerator/components/axcelerator_components_full.vhd | 2 | 614,326 | --------------------------------------------------------------------
-- Actel Axcelerator VITAL Library
-- NAME: axcelerator.vhd
-- DATE: Friday, February 11, 2005
---------------------------------------------------------------------/
library IEEE;
use IEEE.std_logic_1164.all;
--pragma translate_off
use IEEE.VITAL_Timing.all;
--pragma translate_on
package COMPONENTS is
--pragma translate_off
constant DefaultTimingChecksOn : Boolean := True;
constant DefaultXGenerationOn : Boolean := False;
constant DefaultXon : Boolean := False;
constant DefaultMsgOn : Boolean := True;
--pragma translate_on
------ Component ADD1 ------
component ADD1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
FCI : in STD_ULOGIC;
S : out STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component AND2 ------
component AND2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND2A ------
component AND2A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND2B ------
component AND2B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND3 ------
component AND3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND3A ------
component AND3A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND3B ------
component AND3B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND3C ------
component AND3C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND4 ------
component AND4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND4A ------
component AND4A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND4B ------
component AND4B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND4C ------
component AND4C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND4D ------
component AND4D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND5A ------
component AND5A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND5B ------
component AND5B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AND5C ------
component AND5C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO1 ------
component AO1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO10 ------
component AO10
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO11 ------
component AO11
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO12 ------
component AO12
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO13 ------
component AO13
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO14 ------
component AO14
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO15 ------
component AO15
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO16 ------
component AO16
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO17 ------
component AO17
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO18 ------
component AO18
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO1A ------
component AO1A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO1B ------
component AO1B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO1C ------
component AO1C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO1D ------
component AO1D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO1E ------
component AO1E
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO2 ------
component AO2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO2A ------
component AO2A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO2B ------
component AO2B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO2C ------
component AO2C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO2D ------
component AO2D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO2E ------
component AO2E
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO3 ------
component AO3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO3A ------
component AO3A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO3B ------
component AO3B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO3C ------
component AO3C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO4A ------
component AO4A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO5A ------
component AO5A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO6 ------
component AO6
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO6A ------
component AO6A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO7 ------
component AO7
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO8 ------
component AO8
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AO9 ------
component AO9
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI1 ------
component AOI1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI1A ------
component AOI1A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI1B ------
component AOI1B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI1C ------
component AOI1C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI1D ------
component AOI1D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI2A ------
component AOI2A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI2B ------
component AOI2B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI3A ------
component AOI3A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI4 ------
component AOI4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI4A ------
component AOI4A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AOI5 ------
component AOI5
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AFCNTECP1 ------
component AFCNTECP1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_UD_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_Q_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_Q_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_UD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC;
UD : in STD_ULOGIC;
FCI : in STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component ARCNTECP1 ------
component ARCNTECP1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_UD_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_Q_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_Q_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_UD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC;
UD : in STD_ULOGIC;
FCI : in STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component AFCNTELDCP1 ------
component AFCNTELDCP1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_UD_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_LD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_LD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_Q_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_LD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_LD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_Q_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_LD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_UD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
LD : in STD_ULOGIC;
Q : out STD_ULOGIC;
UD : in STD_ULOGIC;
FCI : in STD_ULOGIC;
D : in STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component ARCNTELDCP1 ------
component ARCNTELDCP1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_UD_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_LD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_LD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_Q_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_LD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_LD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_Q_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_LD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_UD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
LD : in STD_ULOGIC;
Q : out STD_ULOGIC;
UD : in STD_ULOGIC;
FCI : in STD_ULOGIC;
D : in STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component AX1 ------
component AX1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AX1A ------
component AX1A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AX1B ------
component AX1B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AX1C ------
component AX1C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AX1D ------
component AX1D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AX1E ------
component AX1E
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXO1 ------
component AXO1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXO2 ------
component AXO2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXO3 ------
component AXO3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXO5 ------
component AXO5
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXO6 ------
component AXO6
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXO7 ------
component AXO7
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXOI1 ------
component AXOI1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXOI2 ------
component AXOI2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXOI3 ------
component AXOI3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXOI4 ------
component AXOI4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXOI5 ------
component AXOI5
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component AXOI7 ------
component AXOI7
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF ------
component BIBUF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_8 ------
component BIBUF_S_8
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_8D ------
component BIBUF_S_8D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_8U ------
component BIBUF_S_8U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_12 ------
component BIBUF_S_12
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_12D ------
component BIBUF_S_12D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_12U ------
component BIBUF_S_12U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_16 ------
component BIBUF_S_16
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_16D ------
component BIBUF_S_16D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_16U ------
component BIBUF_S_16U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_24 ------
component BIBUF_S_24
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_24D ------
component BIBUF_S_24D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_S_24U ------
component BIBUF_S_24U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_8 ------
component BIBUF_F_8
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_8D ------
component BIBUF_F_8D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_8U ------
component BIBUF_F_8U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_12 ------
component BIBUF_F_12
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_12D ------
component BIBUF_F_12D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_12U ------
component BIBUF_F_12U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_16 ------
component BIBUF_F_16
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_16D ------
component BIBUF_F_16D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_16U ------
component BIBUF_F_16U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_24 ------
component BIBUF_F_24
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_24D ------
component BIBUF_F_24D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_F_24U ------
component BIBUF_F_24U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_LVCMOS25 ------
component BIBUF_LVCMOS25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_LVCMOS25D ------
component BIBUF_LVCMOS25D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_LVCMOS25U ------
component BIBUF_LVCMOS25U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_LVCMOS18 ------
component BIBUF_LVCMOS18
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_LVCMOS18D ------
component BIBUF_LVCMOS18D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_LVCMOS18U ------
component BIBUF_LVCMOS18U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_LVCMOS15 ------
component BIBUF_LVCMOS15
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_LVCMOS15D ------
component BIBUF_LVCMOS15D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_LVCMOS15U ------
component BIBUF_LVCMOS15U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_PCI ------
component BIBUF_PCI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_PCIX ------
component BIBUF_PCIX
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_GTLP33 ------
component BIBUF_GTLP33
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_GTLP25 ------
component BIBUF_GTLP25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BUFA ------
component BUFA
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BUFD ------
component BUFD
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBIBUF ------
component CLKBIBUF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : inout STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF ------
component CLKBUF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_LVCMOS25 ------
component CLKBUF_LVCMOS25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_LVCMOS18 ------
component CLKBUF_LVCMOS18
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_LVCMOS15 ------
component CLKBUF_LVCMOS15
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_PCI ------
component CLKBUF_PCI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_PCIX ------
component CLKBUF_PCIX
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_GTLP33 ------
component CLKBUF_GTLP33
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_GTLP25 ------
component CLKBUF_GTLP25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_HSTL_I ------
component CLKBUF_HSTL_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_SSTL3_I ------
component CLKBUF_SSTL3_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_SSTL3_II ------
component CLKBUF_SSTL3_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_SSTL2_I ------
component CLKBUF_SSTL2_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKBUF_SSTL2_II ------
component CLKBUF_SSTL2_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CM7 ------
component CM7
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CM8 ------
component CM8
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CM8BUFF ------
component CM8BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_A_posedge : VitalDelayType := 0.000 ns;
tpw_A_negedge : VitalDelayType := 0.000 ns;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CM8INV ------
component CM8INV
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMA9 ------
component CMA9
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S01 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMAF ------
component CMAF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMB3 ------
component CMB3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S11 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMB7 ------
component CMB7
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMBB ------
component CMBB
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMBF ------
component CMBF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMEA ------
component CMEA
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
DB : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMEB ------
component CMEB
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMEE ------
component CMEE
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
DB : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMEF ------
component CMEF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMF1 ------
component CMF1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMF2 ------
component CMF2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
DB : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMF3 ------
component CMF3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
DB : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMF4 ------
component CMF4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
DB : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMF5 ------
component CMF5
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
DB : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMF6 ------
component CMF6
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
DB : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMF7 ------
component CMF7
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
DB : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMF8 ------
component CMF8
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
DB : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMF9 ------
component CMF9
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMFA ------
component CMFA
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
DB : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMFB ------
component CMFB
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
DB : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMFC ------
component CMFC
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
DB : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMFD ------
component CMFD
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
DB : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CMFE ------
component CMFE
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_DB_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
DB : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CS1 ------
component CS1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CS2 ------
component CS2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CY2A ------
component CY2A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B0 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A1 : in STD_ULOGIC;
B1 : in STD_ULOGIC;
A0 : in STD_ULOGIC;
B0 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CY2B ------
component CY2B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B0 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A1 : in STD_ULOGIC;
B1 : in STD_ULOGIC;
A0 : in STD_ULOGIC;
B0 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component DF1 ------
component DF1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DF1_CC ------
component DF1_CC
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DF1B ------
component DF1B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFC1B ------
component DFC1B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFC1B_CC ------
component DFC1B_CC
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFC1D ------
component DFC1D
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFE1C ------
component DFE1C
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFE1B ------
component DFE1B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFE3C ------
component DFE3C
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFE3D ------
component DFE3D
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFE4F ------
component DFE4F
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFE4G ------
component DFE4G
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFEG ------
component DFEG
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFEH ------
component DFEH
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFP1 ------
component DFP1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_posedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFP1A ------
component DFP1A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_posedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFP1B ------
component DFP1B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFP1B_CC ------
component DFP1B_CC
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFP1D ------
component DFP1D
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFPC ------
component DFPC
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_posedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFPCB ------
component DFPCB
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFPCC ------
component DFPCC
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DL1 ------
component DL1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DL1A ------
component DL1A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
G : in STD_ULOGIC;
QN : out STD_ULOGIC);
end component;
------ Component DL1B ------
component DL1B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DL1C ------
component DL1C
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
G : in STD_ULOGIC;
QN : out STD_ULOGIC);
end component;
------ Component DL2A ------
component DL2A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_PRE_posedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DL2C ------
component DL2C
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_PRE_posedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLC ------
component DLC
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLR : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLC1 ------
component DLC1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_CLR_posedge : VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLR : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLC1A ------
component DLC1A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_CLR_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLR : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLC1F ------
component DLC1F
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_CLR_posedge : VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLR : in STD_ULOGIC;
G : in STD_ULOGIC;
QN : out STD_ULOGIC);
end component;
------ Component DLC1G ------
component DLC1G
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_CLR_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLR : in STD_ULOGIC;
G : in STD_ULOGIC;
QN : out STD_ULOGIC);
end component;
------ Component DLCA ------
component DLCA
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLR : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLE ------
component DLE
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_G_negedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLE1D ------
component DLE1D
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_G_posedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
G : in STD_ULOGIC;
QN : out STD_ULOGIC);
end component;
------ Component DLE2B ------
component DLE2B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_E_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_E_posedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLR : in STD_ULOGIC;
E : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLE2C ------
component DLE2C
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_E_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_E_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_CLR_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLR : in STD_ULOGIC;
E : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLE3B ------
component DLE3B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_E_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_E_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_PRE_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLE3C ------
component DLE3C
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_E_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_E_posedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLEA ------
component DLEA
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_G_posedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLEB ------
component DLEB
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_G_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLEC ------
component DLEC
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_G_posedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLM ------
component DLM
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_A_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_A_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_A_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_B_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_B_G_negedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLM2 ------
component DLM2
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_A_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_A_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_A_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_B_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_B_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
CLR : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLM2B ------
component DLM2B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_A_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
CLR : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLM3 ------
component DLM3
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D0_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S0_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S1_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D0_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D0_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D0_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D0_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S0_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S0_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S0_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S0_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D1_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D1_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D1_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D1_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S1_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S1_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S1_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S1_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D2_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D2_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D2_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D2_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D3_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D3_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D3_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D3_G_negedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S1 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLM3A ------
component DLM3A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D0_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S0_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S1_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D0_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D0_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D0_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D0_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S0_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S0_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S0_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S0_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D1_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D1_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D1_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D1_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S1_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S1_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S1_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S1_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D2_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D2_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D2_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D2_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D3_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D3_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D3_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D3_G_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S1 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLM4 ------
component DLM4
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S0_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D0_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S10_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S10_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S10_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S10_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S11_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S11_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S11_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S11_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S0_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S0_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S0_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S0_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D0_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D0_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D0_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D0_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D1_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D1_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D1_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D1_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D2_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D2_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D2_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D2_G_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D3_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D3_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D3_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D3_G_negedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
S0 : in STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLM4A ------
component DLM4A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S0_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D0_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S10_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S10_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S10_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S10_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S11_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S11_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S11_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S11_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S0_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S0_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S0_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S0_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D0_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D0_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D0_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D0_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D1_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D1_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D1_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D1_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D2_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D2_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D2_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D2_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D3_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D3_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D3_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D3_G_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
S0 : in STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLMA ------
component DLMA
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_A_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_G_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLME1A ------
component DLME1A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_A_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_G_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_E_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_E_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_E_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_E_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_E_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_E_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_E_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_E_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_E_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_E_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_E_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_E_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_G_posedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_E_negedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
E : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLP1 ------
component DLP1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_PRE_posedge : VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PRE : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLP1A ------
component DLP1A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_PRE_posedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PRE : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLP1B ------
component DLP1B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PRE : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLP1C ------
component DLP1C
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PRE : in STD_ULOGIC;
G : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DLP1D ------
component DLP1D
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns;
tperiod_G_negedge :VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_G_posedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PRE : in STD_ULOGIC;
G : in STD_ULOGIC;
QN : out STD_ULOGIC);
end component;
------ Component DLP1E ------
component DLP1E
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_QN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_G_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns;
tperiod_G_posedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_G_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PRE : in STD_ULOGIC;
G : in STD_ULOGIC;
QN : out STD_ULOGIC);
end component;
------ Component FA1 ------
component FA1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CI_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CI_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
CI : in STD_ULOGIC;
S : out STD_ULOGIC;
CO : out STD_ULOGIC);
end component;
------ Component FCEND_BUFF ------
component FCEND_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_FCI_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
FCI : in STD_ULOGIC;
CO : out STD_ULOGIC);
end component;
------ Component FCEND_INV ------
component FCEND_INV
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_FCI_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
FCI : in STD_ULOGIC;
CO : out STD_ULOGIC);
end component;
------ Component FCINIT_BUFF ------
component FCINIT_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component FCINIT_GND ------
component FCINIT_GND
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True );
--pragma translate_on
port(
FCO : out STD_ULOGIC);
end component;
------ Component FCINIT_INV ------
component FCINIT_INV
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component FCINIT_VCC ------
component FCINIT_VCC
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True );
--pragma translate_on
port(
FCO : out STD_ULOGIC);
end component;
------ Component GAND2 ------
component GAND2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
G : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component GMX4 ------
component GMX4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
G : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component GNAND2 ------
component GNAND2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
G : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component GND ------
component GND
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True );
--pragma translate_on
port(
Y : out STD_ULOGIC);
end component;
------ Component GNOR2 ------
component GNOR2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
G : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component GOR2 ------
component GOR2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
G : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component GXOR2 ------
component GXOR2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_G_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
G : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HA1 ------
component HA1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
S : out STD_ULOGIC;
CO : out STD_ULOGIC);
end component;
------ Component HA1A ------
component HA1A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
S : out STD_ULOGIC;
CO : out STD_ULOGIC);
end component;
------ Component HA1B ------
component HA1B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
S : out STD_ULOGIC;
CO : out STD_ULOGIC);
end component;
------ Component HA1C ------
component HA1C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
S : out STD_ULOGIC;
CO : out STD_ULOGIC);
end component;
------ Component HCLKBIBUF ------
component HCLKBIBUF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : inout STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF ------
component HCLKBUF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_LVCMOS25 ------
component HCLKBUF_LVCMOS25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_LVCMOS18 ------
component HCLKBUF_LVCMOS18
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_LVCMOS15 ------
component HCLKBUF_LVCMOS15
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_PCI ------
component HCLKBUF_PCI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_PCIX ------
component HCLKBUF_PCIX
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_GTLP33 ------
component HCLKBUF_GTLP33
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_GTLP25 ------
component HCLKBUF_GTLP25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_HSTL_I ------
component HCLKBUF_HSTL_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_SSTL3_I ------
component HCLKBUF_SSTL3_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_SSTL3_II ------
component HCLKBUF_SSTL3_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_SSTL2_I ------
component HCLKBUF_SSTL2_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKBUF_SSTL2_II ------
component HCLKBUF_SSTL2_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component HCLKINT ------
component HCLKINT
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF ------
component INBUF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_LVCMOS25 ------
component INBUF_LVCMOS25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_LVCMOS25D ------
component INBUF_LVCMOS25D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_LVCMOS25U ------
component INBUF_LVCMOS25U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_LVCMOS18 ------
component INBUF_LVCMOS18
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_LVCMOS18D ------
component INBUF_LVCMOS18D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_LVCMOS18U ------
component INBUF_LVCMOS18U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_LVCMOS15 ------
component INBUF_LVCMOS15
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_LVCMOS15D ------
component INBUF_LVCMOS15D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_LVCMOS15U ------
component INBUF_LVCMOS15U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_PCI ------
component INBUF_PCI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_PCIX ------
component INBUF_PCIX
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_GTLP33 ------
component INBUF_GTLP33
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_GTLP25 ------
component INBUF_GTLP25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_HSTL_I ------
component INBUF_HSTL_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_SSTL3_I ------
component INBUF_SSTL3_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_SSTL3_II ------
component INBUF_SSTL3_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_SSTL2_I ------
component INBUF_SSTL2_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INBUF_SSTL2_II ------
component INBUF_SSTL2_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INV ------
component INV
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INVA ------
component INVA
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component INVD ------
component INVD
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOI_DFEG ------
component IOI_DFEG
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component IOI_DFEH ------
component IOI_DFEH
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component IOI_BUFF ------
component IOI_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOOE_BUFF ------
component IOOE_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOOE_DFEG ------
component IOOE_DFEG
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PRE_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tperiod_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLK : in STD_ULOGIC;
CLR : in STD_ULOGIC;
E : in STD_ULOGIC;
PRE : in STD_ULOGIC;
Q : out STD_ULOGIC;
YOUT : out STD_ULOGIC);
end component;
------ Component IOOE_DFEH ------
component IOOE_DFEH
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PRE_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tperiod_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
CLK : in STD_ULOGIC;
CLR : in STD_ULOGIC;
E : in STD_ULOGIC;
PRE : in STD_ULOGIC;
Q : out STD_ULOGIC;
YOUT : out STD_ULOGIC);
end component;
------ Component IOPAD_IN ------
component IOPAD_IN
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
-- DNW: Add the following 2 lines
tpw_PAD_posedge : VitalDelayType := 0.000 ns;
tpw_PAD_negedge : VitalDelayType := 0.000 ns;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOPAD_TRI ------
component IOPAD_TRI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_D_posedge : VitalDelayType := 0.000 ns;
tpw_D_negedge : VitalDelayType := 0.000 ns;
tpw_E_posedge : VitalDelayType := 0.000 ns;
tpw_E_negedge : VitalDelayType := 0.000 ns;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component IOPAD_BI ------
component IOPAD_BI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_D_posedge : VitalDelayType := 0.000 ns;
tpw_D_negedge : VitalDelayType := 0.000 ns;
tpw_E_posedge : VitalDelayType := 0.000 ns;
tpw_E_negedge : VitalDelayType := 0.000 ns;
tpw_PAD_negedge : VitalDelayType := 0.000 ns;
tpw_PAD_posedge : VitalDelayType := 0.000 ns;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component JKF ------
component JKF
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_J_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_J_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_J_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_J_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_K_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_K_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
J : in STD_ULOGIC;
K : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component JKF1B ------
component JKF1B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_J_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_J_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_J_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_J_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_K_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_K_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
J : in STD_ULOGIC;
K : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component JKF2A ------
component JKF2A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_J_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_J_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_J_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_J_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_K_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_K_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
J : in STD_ULOGIC;
K : in STD_ULOGIC;
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component JKF2B ------
component JKF2B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_J_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_J_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_J_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_J_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_K_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_K_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
J : in STD_ULOGIC;
K : in STD_ULOGIC;
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component JKF3A ------
component JKF3A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_J_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_J_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_J_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_J_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_K_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_K_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
J : in STD_ULOGIC;
K : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component JKF3B ------
component JKF3B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_J_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_J_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_J_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_J_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_K_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_K_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_K_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
J : in STD_ULOGIC;
K : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component MAJ3 ------
component MAJ3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component MAJ3X ------
component MAJ3X
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component MAJ3XI ------
component MAJ3XI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component MIN3 ------
component MIN3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component MIN3X ------
component MIN3X
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component MIN3XI ------
component MIN3XI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component MULT1 ------
component MULT1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_PO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_PO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PI_PO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_PO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
PI : in STD_ULOGIC;
FCI : in STD_ULOGIC;
PO : out STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component MX2 ------
component MX2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component MX2A ------
component MX2A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component MX2B ------
component MX2B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component MX2C ------
component MX2C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
S : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component MX4 ------
component MX4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
S0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
S1 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND2 ------
component NAND2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND2A ------
component NAND2A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND2B ------
component NAND2B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND3 ------
component NAND3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND3A ------
component NAND3A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND3B ------
component NAND3B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND3C ------
component NAND3C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND4 ------
component NAND4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND4A ------
component NAND4A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND4B ------
component NAND4B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND4C ------
component NAND4C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND4D ------
component NAND4D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND5B ------
component NAND5B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NAND5C ------
component NAND5C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR2 ------
component NOR2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR2A ------
component NOR2A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR2B ------
component NOR2B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR3 ------
component NOR3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR3A ------
component NOR3A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR3B ------
component NOR3B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR3C ------
component NOR3C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR4 ------
component NOR4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR4A ------
component NOR4A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR4B ------
component NOR4B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR4C ------
component NOR4C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR4D ------
component NOR4D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR5B ------
component NOR5B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component NOR5C ------
component NOR5C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA1 ------
component OA1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA1A ------
component OA1A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA1B ------
component OA1B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
C : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA1C ------
component OA1C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
C : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA2 ------
component OA2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA2A ------
component OA2A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA3 ------
component OA3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA3A ------
component OA3A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA3B ------
component OA3B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA4 ------
component OA4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA4A ------
component OA4A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OA5 ------
component OA5
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OAI1 ------
component OAI1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OAI2A ------
component OAI2A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OAI3 ------
component OAI3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OAI3A ------
component OAI3A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR2 ------
component OR2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR2A ------
component OR2A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR2B ------
component OR2B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR3 ------
component OR3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR3A ------
component OR3A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR3B ------
component OR3B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR3C ------
component OR3C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR4 ------
component OR4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR4A ------
component OR4A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR4B ------
component OR4B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR4C ------
component OR4C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR4D ------
component OR4D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR5A ------
component OR5A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR5B ------
component OR5B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OR5C ------
component OR5C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
E : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component OUTBUF ------
component OUTBUF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_S_8 ------
component OUTBUF_S_8
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_S_12 ------
component OUTBUF_S_12
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_S_16 ------
component OUTBUF_S_16
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_S_24 ------
component OUTBUF_S_24
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_F_8 ------
component OUTBUF_F_8
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_F_12 ------
component OUTBUF_F_12
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_F_16 ------
component OUTBUF_F_16
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_F_24 ------
component OUTBUF_F_24
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_LVCMOS25 ------
component OUTBUF_LVCMOS25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_LVCMOS18 ------
component OUTBUF_LVCMOS18
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_LVCMOS15 ------
component OUTBUF_LVCMOS15
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_PCI ------
component OUTBUF_PCI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_PCIX ------
component OUTBUF_PCIX
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_GTLP33 ------
component OUTBUF_GTLP33
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_GTLP25 ------
component OUTBUF_GTLP25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_HSTL_I ------
component OUTBUF_HSTL_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_SSTL3_I ------
component OUTBUF_SSTL3_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_SSTL3_II ------
component OUTBUF_SSTL3_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_SSTL2_I ------
component OUTBUF_SSTL2_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component OUTBUF_SSTL2_II ------
component OUTBUF_SSTL2_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component PLLHCLK ------
component PLLHCLK
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component PLLRCLK ------
component PLLRCLK
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component SFCNTECP1 ------
component SFCNTECP1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_UD_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_Q_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_Q_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_UD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC;
UD : in STD_ULOGIC;
FCI : in STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component SRCNTECP1 ------
component SRCNTECP1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_UD_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_Q_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_Q_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_UD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC;
UD : in STD_ULOGIC;
FCI : in STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component SFCNTELDCP1 ------
component SFCNTELDCP1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_UD_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_Q_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_LD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_LD_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_Q_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_LD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_LD_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_UD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_LD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC;
UD : in STD_ULOGIC;
FCI : in STD_ULOGIC;
LD : in STD_ULOGIC;
D : in STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component SRCNTELDCP1 ------
component SRCNTELDCP1
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_UD_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_Q_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_LD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_LD_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_Q_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_Q_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_UD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_UD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_FCI_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_FCI_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_LD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_LD_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_UD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_LD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC;
UD : in STD_ULOGIC;
FCI : in STD_ULOGIC;
LD : in STD_ULOGIC;
D : in STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component SUB1 ------
component SUB1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
FCI : in STD_ULOGIC;
S : out STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
------ Component TF1A ------
component TF1A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_T_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_T_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_T_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_T_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_T : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
T : in STD_ULOGIC;
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component TF1B ------
component TF1B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_T_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_T_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_T_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_T_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_T : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
T : in STD_ULOGIC;
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component TRIBUFF ------
component TRIBUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_8 ------
component TRIBUFF_S_8
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_8D ------
component TRIBUFF_S_8D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_8U ------
component TRIBUFF_S_8U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_12 ------
component TRIBUFF_S_12
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_12D ------
component TRIBUFF_S_12D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_12U ------
component TRIBUFF_S_12U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_16 ------
component TRIBUFF_S_16
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_16D ------
component TRIBUFF_S_16D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_16U ------
component TRIBUFF_S_16U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_24 ------
component TRIBUFF_S_24
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_24D ------
component TRIBUFF_S_24D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_S_24U ------
component TRIBUFF_S_24U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_8 ------
component TRIBUFF_F_8
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_8D ------
component TRIBUFF_F_8D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_8U ------
component TRIBUFF_F_8U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_12 ------
component TRIBUFF_F_12
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_12D ------
component TRIBUFF_F_12D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_12U ------
component TRIBUFF_F_12U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_16 ------
component TRIBUFF_F_16
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_16D ------
component TRIBUFF_F_16D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_16U ------
component TRIBUFF_F_16U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_24 ------
component TRIBUFF_F_24
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_24D ------
component TRIBUFF_F_24D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_F_24U ------
component TRIBUFF_F_24U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_LVCMOS25 ------
component TRIBUFF_LVCMOS25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_LVCMOS25D ------
component TRIBUFF_LVCMOS25D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_LVCMOS25U ------
component TRIBUFF_LVCMOS25U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_LVCMOS18 ------
component TRIBUFF_LVCMOS18
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_LVCMOS18D ------
component TRIBUFF_LVCMOS18D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_LVCMOS18U ------
component TRIBUFF_LVCMOS18U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_LVCMOS15 ------
component TRIBUFF_LVCMOS15
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_LVCMOS15D ------
component TRIBUFF_LVCMOS15D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_LVCMOS15U ------
component TRIBUFF_LVCMOS15U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_PCI ------
component TRIBUFF_PCI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_PCIX ------
component TRIBUFF_PCIX
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_GTLP33 ------
component TRIBUFF_GTLP33
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_GTLP25 ------
component TRIBUFF_GTLP25
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component VCC ------
component VCC
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True );
--pragma translate_on
port(
Y : out STD_ULOGIC);
end component;
------ Component XA1 ------
component XA1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XA1A ------
component XA1A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XA1B ------
component XA1B
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XA1C ------
component XA1C
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XAI1 ------
component XAI1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XAI1A ------
component XAI1A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XNOR2 ------
component XNOR2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XNOR3 ------
component XNOR3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XNOR4 ------
component XNOR4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XO1 ------
component XO1
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XO1A ------
component XO1A
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XOR2 ------
component XOR2
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XOR3 ------
component XOR3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XOR4 ------
component XOR4
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
D : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component XOR4_FCI ------
component XOR4_FCI
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
FCI : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component ZOR3 ------
component ZOR3
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component ZOR3I ------
component ZOR3I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_C_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
C : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOFIFO_BIBUF ------
component IOFIFO_BIBUF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_AIN_YIN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_AOUT_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_AIN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AOUT : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
AIN : in STD_ULOGIC;
AOUT : in STD_ULOGIC;
YIN : out STD_ULOGIC;
YOUT : out STD_ULOGIC);
end component;
------ Component IOI_FCLK_EN_BUFF ------
component IOI_FCLK_EN_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_EN_ENOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_EN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
EN : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Y : out STD_ULOGIC;
ENOUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOI_FCLK_BUFF ------
component IOI_FCLK_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Y : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOI_RCLK_EN_BUFF ------
component IOI_RCLK_EN_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_EN_ENOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_EN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
EN : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Y : out STD_ULOGIC;
ENOUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOI_RCLK_BUFF ------
component IOI_RCLK_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
CLK : in STD_ULOGIC;
Y : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_FCLK_EN_BUFF ------
component IOOE_FCLK_EN_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_EN_ENOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_EN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
EN : in STD_ULOGIC;
CLK : in STD_ULOGIC;
YOUT : out STD_ULOGIC;
ENOUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_FCLK ------
component IOOE_FCLK
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLK : in STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_RCLK_EN_BUFF ------
component IOOE_RCLK_EN_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_EN_ENOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_EN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
EN : in STD_ULOGIC;
CLK : in STD_ULOGIC;
YOUT : out STD_ULOGIC;
ENOUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_RCLK_CLR_EN ------
component IOOE_RCLK_CLR_EN
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_CLR_CLROUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_EN_ENOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_EN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
EN : in STD_ULOGIC;
CLK : in STD_ULOGIC;
CLROUT : out STD_ULOGIC;
ENOUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_RCLK_BUFF ------
component IOOE_RCLK_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
CLK : in STD_ULOGIC;
YOUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_RCLK ------
component IOOE_RCLK
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLK : in STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component PLLINT ------
component PLLINT
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component PLLOUT ------
component PLLOUT
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_HSTL_I ------
component BIBUF_HSTL_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_SSTL3_I ------
component BIBUF_SSTL3_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_SSTL3_II ------
component BIBUF_SSTL3_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_SSTL2_I ------
component BIBUF_SSTL2_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BIBUF_SSTL2_II ------
component BIBUF_SSTL2_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component BUFF ------
component BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKINT ------
component CLKINT
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKINT_W ------
component CLKINT_W
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKOUT_E ------
component CLKOUT_E
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component CLKOUT_W ------
component CLKOUT_W
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component DFM ------
component DFM
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFM3B ------
component DFM3B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFM4A ------
component DFM4A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFM4B ------
component DFM4B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFMA ------
component DFMA
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFMB ------
component DFMB
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFME1A ------
component DFME1A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFME1B ------
component DFME1B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFME2A ------
component DFME2A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFME2B ------
component DFME2B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFME3A ------
component DFME3A
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFME3B ------
component DFME3B
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFMEG ------
component DFMEG
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFMEH ------
component DFMEH
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_E_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
E : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFMPCA ------
component DFMPCA
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component DFMPCB ------
component DFMPCB
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PRE_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tsetup_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_S_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_A_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
tsetup_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_B_CLK_negedge_negedge : VitalDelayType := 0.000 ns;
thold_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
thold_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns;
tpw_CLK_posedge : VitalDelayType := 0.000 ns;
tpw_CLK_negedge : VitalDelayType := 0.000 ns;
tpw_PRE_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CLR : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
S : in STD_ULOGIC;
A : in STD_ULOGIC;
B : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
------ Component HCLKMUX ------
component HCLKMUX
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_A_posedge : VitalDelayType := 0.000 ns;
tpw_A_negedge : VitalDelayType := 0.000 ns;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOFIFO_INBUF ------
component IOFIFO_INBUF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOFIFO_OUTBUF ------
component IOFIFO_OUTBUF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOOE_FCLK_BUFF ------
component IOOE_FCLK_BUFF
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
CLK : in STD_ULOGIC;
YOUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_OUT_FCLK ------
component IOOE_OUT_FCLK
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
CLK : in STD_ULOGIC;
YOUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_OUT_FCLK_CLR_EN ------
component IOOE_OUT_FCLK_CLR_EN
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_EN_ENOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_CLROUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_EN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
EN : in STD_ULOGIC;
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
YOUT : out STD_ULOGIC;
ENOUT : out STD_ULOGIC;
CLROUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_OUT_RCLK ------
component IOOE_OUT_RCLK
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
CLK : in STD_ULOGIC;
YOUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_OUT_RCLK_CLR_EN ------
component IOOE_OUT_RCLK_CLR_EN
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_A_YOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_EN_ENOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_CLROUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_EN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
EN : in STD_ULOGIC;
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
YOUT : out STD_ULOGIC;
ENOUT : out STD_ULOGIC;
CLROUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOOE_FCLK_CLR_EN ------
component IOOE_FCLK_CLR_EN
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_EN_ENOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_CLROUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLK_CLKOUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_EN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
EN : in STD_ULOGIC;
CLR : in STD_ULOGIC;
CLK : in STD_ULOGIC;
ENOUT : out STD_ULOGIC;
CLROUT : out STD_ULOGIC;
CLKOUT : out STD_ULOGIC);
end component;
------ Component IOPAD_IN_U ------
component IOPAD_IN_U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_PAD_posedge : VitalDelayType := 0.000 ns;
tpw_PAD_negedge : VitalDelayType := 0.000 ns;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOPAD_IN_D ------
component IOPAD_IN_D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_PAD_posedge : VitalDelayType := 0.000 ns;
tpw_PAD_negedge : VitalDelayType := 0.000 ns;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOPAD_TRI_U ------
component IOPAD_TRI_U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_D_posedge : VitalDelayType := 0.000 ns;
tpw_D_negedge : VitalDelayType := 0.000 ns;
tpw_E_posedge : VitalDelayType := 0.000 ns;
tpw_E_negedge : VitalDelayType := 0.000 ns;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component IOPAD_TRI_D ------
component IOPAD_TRI_D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_D_posedge : VitalDelayType := 0.000 ns;
tpw_D_negedge : VitalDelayType := 0.000 ns;
tpw_E_posedge : VitalDelayType := 0.000 ns;
tpw_E_negedge : VitalDelayType := 0.000 ns;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component IOPAD_BI_U ------
component IOPAD_BI_U
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_D_posedge : VitalDelayType := 0.000 ns;
tpw_D_negedge : VitalDelayType := 0.000 ns;
tpw_E_posedge : VitalDelayType := 0.000 ns;
tpw_E_negedge : VitalDelayType := 0.000 ns;
tpw_PAD_posedge : VitalDelayType := 0.000 ns;
tpw_PAD_negedge : VitalDelayType := 0.000 ns;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component IOPAD_BI_D ------
component IOPAD_BI_D
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_E_posedge : VitalDelayType := 0.000 ns;
tpw_E_negedge : VitalDelayType := 0.000 ns;
tpw_D_posedge : VitalDelayType := 0.000 ns;
tpw_D_negedge : VitalDelayType := 0.000 ns;
tpw_PAD_posedge : VitalDelayType := 0.000 ns;
tpw_PAD_negedge : VitalDelayType := 0.000 ns;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : inout STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component RCLKMUX ------
component RCLKMUX
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpw_A_posedge : VitalDelayType := 0.000 ns;
tpw_A_negedge : VitalDelayType := 0.000 ns;
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
------ Component TRIBUFF_HSTL_I ------
component TRIBUFF_HSTL_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_SSTL3_I ------
component TRIBUFF_SSTL3_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_SSTL3_II ------
component TRIBUFF_SSTL3_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_SSTL2_I ------
component TRIBUFF_SSTL2_I
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
------ Component TRIBUFF_SSTL2_II ------
component TRIBUFF_SSTL2_II
--pragma translate_off
generic(
TimingChecksOn:Boolean := True;
Xon: Boolean := False;
InstancePath: STRING :="*";
MsgOn: Boolean := True;
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_E_PAD : VitalDelayType01Z := (0.100 ns, 0.100 ns,0.100 ns, 0.100 ns,0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
component BIOFIFO_BIDIRINFIFO
--pragma translate_off
GENERIC (
tipd_A : VitalDelayType01 := (0.00 ns, 0.00 ns);
tipd_D : VitalDelayType01 := (0.00 ns, 0.00 ns);
tipd_WENB : VitalDelayType01 := (0.00 ns, 0.00 ns);
tipd_WCLK : VitalDelayType01 := (0.00 ns, 0.00 ns);
tipd_RENB : VitalDelayType01 := (0.00 ns, 0.00 ns);
tipd_RCLK : VitalDelayType01 := (0.00 ns, 0.00 ns);
tipd_CLRB : VitalDelayType01 := (0.00 ns, 0.00 ns);
tpd_A_Y : VitalDelayType01 := (0.1000 ns, 0.1000 ns);
tpd_RCLK_Q : VitalDelayType01 := (0.1000 ns, 0.1000 ns);
tpd_CLRB_Q : VitalDelayType01 := (0.1000 ns, 0.1000 ns);
tsetup_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLRB_negedge : VitalDelayType := 0.000 ns;
TimingCheckOn : BOOLEAN := TRUE;
InstancePath : STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True
);
--pragma translate_on
PORT (
A : IN STD_ULOGIC ;
D : IN STD_ULOGIC ;
WENB : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
RENB : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
CLRB : IN STD_ULOGIC ;
Q : OUT STD_ULOGIC ;
Y : OUT STD_ULOGIC
);
end component;
component BIOFIFO_BIDIROUTFIFO
--pragma translate_off
GENERIC (
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLRB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLRB_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLRB_negedge : VitalDelayType := 0.000 ns;
TimingCheckOn : BOOLEAN := TRUE;
InstancePath : STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True
);
--pragma translate_on
PORT (
A : IN STD_ULOGIC ;
D : IN STD_ULOGIC ;
WENB : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
RENB : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
CLRB : IN STD_ULOGIC ;
Q : OUT STD_ULOGIC ;
Y : OUT STD_ULOGIC
);
end component;
component BIOFIFO_INFIFO
--pragma translate_off
GENERIC (
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLRB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_RCLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLRB_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLRB_negedge : VitalDelayType := 0.000 ns;
TimingCheckOn : BOOLEAN := TRUE;
InstancePath : STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True
);
--pragma translate_on
PORT (
D : IN STD_ULOGIC ;
WENB : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
RENB : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
CLRB : IN STD_ULOGIC ;
Q : OUT STD_ULOGIC
);
end component;
component BIOFIFO_OUTFIFO
--pragma translate_off
GENERIC (
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLRB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_RCLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLRB_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLRB_negedge : VitalDelayType := 0.000 ns;
TimingCheckOn : BOOLEAN := TRUE;
InstancePath : STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True
);
--pragma translate_on
PORT (
D : IN STD_ULOGIC ;
WENB : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
RENB : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
CLRB : IN STD_ULOGIC ;
Q : OUT STD_ULOGIC
);
end component;
component IOFIFO_BIDIRINFIFO
--pragma translate_off
GENERIC (
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLRB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLRB_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLRB_negedge : VitalDelayType := 0.000 ns;
TimingCheckOn : BOOLEAN := TRUE;
InstancePath : STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True
);
--pragma translate_on
PORT (
A : IN STD_ULOGIC ;
D : IN STD_ULOGIC ;
WENB : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
RENB : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
CLRB : IN STD_ULOGIC ;
Q : OUT STD_ULOGIC ;
Y : OUT STD_ULOGIC
);
end component;
component IOFIFO_BIDIROUTFIFO
--pragma translate_off
GENERIC (
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLRB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_A_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLRB_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLRB_negedge : VitalDelayType := 0.000 ns;
TimingCheckOn : BOOLEAN := TRUE;
InstancePath : STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True
);
--pragma translate_on
PORT (
A : IN STD_ULOGIC ;
D : IN STD_ULOGIC ;
WENB : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
RENB : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
CLRB : IN STD_ULOGIC ;
Q : OUT STD_ULOGIC ;
Y : OUT STD_ULOGIC
);
end component;
component IOFIFO_INFIFO
--pragma translate_off
GENERIC (
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLRB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_RCLK_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLRB_Q : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLRB_negedge : VitalDelayType := 0.000 ns;
TimingCheckOn : BOOLEAN := TRUE;
InstancePath : STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True
);
--pragma translate_on
PORT (
D : IN STD_ULOGIC ;
WENB : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
RENB : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
CLRB : IN STD_ULOGIC ;
Q : OUT STD_ULOGIC
);
end component;
component IOFIFO_OUTFIFO
--pragma translate_off
GENERIC (
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RENB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLRB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_RCLK_Q : VitalDelayType01 := (0.1000 ns, 0.100 ns);
tpd_CLRB_Q : VitalDelayType01 := (0.1000 ns, 0.1000 ns);
tsetup_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_D_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RENB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WENB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLRB_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLRB_negedge : VitalDelayType := 0.000 ns;
TimingCheckOn : BOOLEAN := TRUE;
InstancePath : STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True
);
--pragma translate_on
PORT (
D : IN STD_ULOGIC ;
WENB : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
RENB : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
CLRB : IN STD_ULOGIC ;
Q : OUT STD_ULOGIC
);
end component;
component IOPADP_IN
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpw_PAD_posedge : VitalDelayType := 0.000 ns;
tpw_PAD_negedge : VitalDelayType := 0.000 ns;
tpw_N2PIN_posedge : VitalDelayType := 0.000 ns;
tpw_N2PIN_negedge : VitalDelayType := 0.000 ns;
tpd_PAD_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_N2PIN_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_N2PIN : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
N2PIN : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
component IOPADN_IN
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpw_PAD_posedge : VitalDelayType := 0.000 ns;
tpw_PAD_negedge : VitalDelayType := 0.000 ns;
tpd_PAD_N2POUT : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PAD : in STD_ULOGIC;
N2POUT : out STD_ULOGIC);
end component;
component IOPADP_TRI
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpw_E_posedge : VitalDelayType := 0.000 ns;
tpw_E_negedge : VitalDelayType := 0.000 ns;
tpw_D_posedge : VitalDelayType := 0.000 ns;
tpw_D_negedge : VitalDelayType := 0.000 ns;
tpd_E_PAD : VitalDelayType01Z :=
(0.100 ns, 0.100 ns, 0.100 ns, 0.000 ns, 0.100 ns, 0.100 ns);
tpd_D_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
component IOPADN_TRI
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpw_DB_posedge : VitalDelayType := 0.000 ns;
tpw_DB_negedge : VitalDelayType := 0.000 ns;
tpw_E_posedge : VitalDelayType := 0.000 ns;
tpw_E_negedge : VitalDelayType := 0.000 ns;
tpd_E_PAD : VitalDelayType01Z :=
(0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns, 0.100 ns);
tpd_DB_PAD : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
DB : in STD_ULOGIC;
E : in STD_ULOGIC;
PAD : out STD_ULOGIC);
end component;
component CLKBUF_LVDS
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PADP_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PADN_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PADP : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PADN : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PADP : in STD_ULOGIC;
PADN : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
component CLKBUF_LVPECL
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PADP_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PADN_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PADP : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PADN : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PADP : in STD_ULOGIC;
PADN : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
component HCLKBUF_LVDS
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PADP_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PADN_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PADP : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PADN : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PADP : in STD_ULOGIC;
PADN : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
component HCLKBUF_LVPECL
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PADP_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PADN_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PADP : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PADN : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PADP : in STD_ULOGIC;
PADN : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
component INBUF_LVDS
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PADP_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PADN_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PADP : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PADN : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PADP : in STD_ULOGIC;
PADN : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
component INBUF_LVPECL
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_PADP_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_PADN_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_PADP : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_PADN : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PADP : in STD_ULOGIC;
PADN : in STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
component OUTBUF_LVDS
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_D_PADP : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_PADN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PADP : out STD_ULOGIC;
PADN : out STD_ULOGIC);
end component;
component OUTBUF_LVPECL
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_D_PADP : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D_PADN : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D : in STD_ULOGIC;
PADP : out STD_ULOGIC;
PADN : out STD_ULOGIC);
end component;
component CM8F
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
tpd_S11_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D0_Y : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S11_FY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S10_FY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S01_FY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_S00_FY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D3_FY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D2_FY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D1_FY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_D0_FY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
D2 : in STD_ULOGIC;
D3 : in STD_ULOGIC;
S00 : in STD_ULOGIC;
S01 : in STD_ULOGIC;
S10 : in STD_ULOGIC;
S11 : in STD_ULOGIC;
FY : out STD_ULOGIC;
Y : out STD_ULOGIC);
end component;
component FIFO64K36
--pragma translate_off
GENERIC (
tipd_DEPTH3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DEPTH2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DEPTH1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DEPTH0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WIDTH2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WIDTH1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WIDTH0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AEVAL7 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AEVAL6 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AEVAL5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AEVAL4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AEVAL3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AEVAL2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AEVAL1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AEVAL0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AFVAL7 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AFVAL6 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AFVAL5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AFVAL4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AFVAL3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AFVAL2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AFVAL1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AFVAL0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_REN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD35 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD34 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD33 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD32 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD31 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD30 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD29 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD28 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD27 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD26 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD25 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD24 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD23 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD22 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD21 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD20 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD19 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD18 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD17 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD16 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD15 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD14 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD13 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD12 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD9 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD8 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD7 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD6 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WEN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_RCLK_RD0 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD1 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD2 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD3 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD4 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD5 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD6 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD7 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD8 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD9 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD10 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD11 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD12 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD13 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD14 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD15 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD16 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD17 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD18 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD19 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD20 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD21 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD22 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD23 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD24 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD25 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD26 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD27 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD28 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD29 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD30 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD31 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD32 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD33 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD34 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD35 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_FULL : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_AFULL : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_EMPTY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_AEMPTY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD0 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD1 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD2 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD3 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD4 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD5 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD6 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD7 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD8 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD9 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD10 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD11 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD12 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD13 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD14 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD15 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD16 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD17 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD18 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD19 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD20 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD21 : VitalDelayType01 := (0.100 ns, 0.10 ns);
tpd_CLR_RD22 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD23 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD24 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD25 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD26 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD27 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD28 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD29 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD30 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD31 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD32 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD33 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_RD34 : VitalDelayType01 := (0.1000 ns, 0.100 ns);
tpd_CLR_RD35 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_FULL : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_AFULL : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_EMPTY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CLR_AEMPTY : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_WD35_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD34_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD33_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD32_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD31_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD30_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD29_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD28_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD27_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD26_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD25_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD24_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD23_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD22_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD21_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD20_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD19_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD18_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD17_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD16_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD15_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD14_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD13_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD12_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD11_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD10_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD9_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD8_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD35_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD34_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD33_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD32_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD31_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD30_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD29_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD28_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD27_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD26_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD25_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD24_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD23_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD22_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD21_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD20_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD19_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD18_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD17_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD16_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD15_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD14_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD13_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD12_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD11_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD10_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD9_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD8_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WEN_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WEN_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH3_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH3_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WIDTH0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL7_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL6_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL5_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL4_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL3_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL7_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL6_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL5_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL4_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL3_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AEVAL0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL7_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL6_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL5_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL4_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL3_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL7_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL6_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL5_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL4_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL3_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_AFVAL0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_REN_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_REN_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD35_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD34_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD33_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD32_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD31_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD30_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD29_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD28_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD27_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD26_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD25_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD24_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD23_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD22_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD21_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD20_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD19_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD18_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD17_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD16_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD15_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD14_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD13_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD12_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD11_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD10_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD9_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD8_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD35_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD34_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD33_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD32_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD31_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD30_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD29_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD28_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD27_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD26_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD25_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD24_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD23_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD22_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD21_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD20_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD19_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD18_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD17_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD16_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD15_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD14_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD13_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD12_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD11_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD10_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD9_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD8_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WEN_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WEN_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH3_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH3_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WIDTH0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL7_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL6_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL5_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL4_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL3_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL7_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL6_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL5_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL4_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL3_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AEVAL0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL7_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL6_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL5_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL4_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL3_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL7_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL6_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL5_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL4_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL3_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_AFVAL0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_REN_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_REN_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
trecovery_CLR_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_CLR_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns;
tpw_CLR_negedge : VitalDelayType := 0.000 ns;
TimingCheckOn : BOOLEAN := TRUE;
InstancePath : STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True
);
--pragma translate_on
PORT (
DEPTH3 : IN STD_ULOGIC ;
DEPTH2 : IN STD_ULOGIC ;
DEPTH1 : IN STD_ULOGIC ;
DEPTH0 : IN STD_ULOGIC ;
WIDTH2 : IN STD_ULOGIC ;
WIDTH1 : IN STD_ULOGIC ;
WIDTH0 : IN STD_ULOGIC ;
AEVAL7 : IN STD_ULOGIC ;
AEVAL6 : IN STD_ULOGIC ;
AEVAL5 : IN STD_ULOGIC ;
AEVAL4 : IN STD_ULOGIC ;
AEVAL3 : IN STD_ULOGIC ;
AEVAL2 : IN STD_ULOGIC ;
AEVAL1 : IN STD_ULOGIC ;
AEVAL0 : IN STD_ULOGIC ;
AFVAL7 : IN STD_ULOGIC ;
AFVAL6 : IN STD_ULOGIC ;
AFVAL5 : IN STD_ULOGIC ;
AFVAL4 : IN STD_ULOGIC ;
AFVAL3 : IN STD_ULOGIC ;
AFVAL2 : IN STD_ULOGIC ;
AFVAL1 : IN STD_ULOGIC ;
AFVAL0 : IN STD_ULOGIC ;
REN : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
WD35 : IN STD_ULOGIC ;
WD34 : IN STD_ULOGIC ;
WD33 : IN STD_ULOGIC ;
WD32 : IN STD_ULOGIC ;
WD31 : IN STD_ULOGIC ;
WD30 : IN STD_ULOGIC ;
WD29 : IN STD_ULOGIC ;
WD28 : IN STD_ULOGIC ;
WD27 : IN STD_ULOGIC ;
WD26 : IN STD_ULOGIC ;
WD25 : IN STD_ULOGIC ;
WD24 : IN STD_ULOGIC ;
WD23 : IN STD_ULOGIC ;
WD22 : IN STD_ULOGIC ;
WD21 : IN STD_ULOGIC ;
WD20 : IN STD_ULOGIC ;
WD19 : IN STD_ULOGIC ;
WD18 : IN STD_ULOGIC ;
WD17 : IN STD_ULOGIC ;
WD16 : IN STD_ULOGIC ;
WD15 : IN STD_ULOGIC ;
WD14 : IN STD_ULOGIC ;
WD13 : IN STD_ULOGIC ;
WD12 : IN STD_ULOGIC ;
WD11 : IN STD_ULOGIC ;
WD10 : IN STD_ULOGIC ;
WD9 : IN STD_ULOGIC ;
WD8 : IN STD_ULOGIC ;
WD7 : IN STD_ULOGIC ;
WD6 : IN STD_ULOGIC ;
WD5 : IN STD_ULOGIC ;
WD4 : IN STD_ULOGIC ;
WD3 : IN STD_ULOGIC ;
WD2 : IN STD_ULOGIC ;
WD1 : IN STD_ULOGIC ;
WD0 : IN STD_ULOGIC ;
WEN : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
CLR : IN STD_ULOGIC ;
RD35 : OUT STD_ULOGIC ;
RD34 : OUT STD_ULOGIC ;
RD33 : OUT STD_ULOGIC ;
RD32 : OUT STD_ULOGIC ;
RD31 : OUT STD_ULOGIC ;
RD30 : OUT STD_ULOGIC ;
RD29 : OUT STD_ULOGIC ;
RD28 : OUT STD_ULOGIC ;
RD27 : OUT STD_ULOGIC ;
RD26 : OUT STD_ULOGIC ;
RD25 : OUT STD_ULOGIC ;
RD24 : OUT STD_ULOGIC ;
RD23 : OUT STD_ULOGIC ;
RD22 : OUT STD_ULOGIC ;
RD21 : OUT STD_ULOGIC ;
RD20 : OUT STD_ULOGIC ;
RD19 : OUT STD_ULOGIC ;
RD18 : OUT STD_ULOGIC ;
RD17 : OUT STD_ULOGIC ;
RD16 : OUT STD_ULOGIC ;
RD15 : OUT STD_ULOGIC ;
RD14 : OUT STD_ULOGIC ;
RD13 : OUT STD_ULOGIC ;
RD12 : OUT STD_ULOGIC ;
RD11 : OUT STD_ULOGIC ;
RD10 : OUT STD_ULOGIC ;
RD9 : OUT STD_ULOGIC ;
RD8 : OUT STD_ULOGIC ;
RD7 : OUT STD_ULOGIC ;
RD6 : OUT STD_ULOGIC ;
RD5 : OUT STD_ULOGIC ;
RD4 : OUT STD_ULOGIC ;
RD3 : OUT STD_ULOGIC ;
RD2 : OUT STD_ULOGIC ;
RD1 : OUT STD_ULOGIC ;
RD0 : OUT STD_ULOGIC ;
FULL : OUT STD_ULOGIC ;
AFULL : OUT STD_ULOGIC ;
EMPTY : OUT STD_ULOGIC ;
AEMPTY : OUT STD_ULOGIC
);
end component;
component RAM64K36
--pragma translate_off
GENERIC (
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
Xon : Boolean := False;
MsgOn : Boolean := True;
MEMORYFILE : String := "";
tipd_DEPTH3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DEPTH2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DEPTH1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DEPTH0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD15 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD14 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD13 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD12 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD9 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD8 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD7 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD6 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD35 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD34 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD33 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD32 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD31 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD30 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD29 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD28 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD27 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD26 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD25 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD24 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD23 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD22 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD21 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD20 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD19 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD18 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD17 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD16 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD15 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD14 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD13 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD12 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD9 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD8 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD7 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD6 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WW2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WW1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WW0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WEN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD15 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD14 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD13 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD12 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD9 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD8 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD7 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD6 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RW2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RW1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RW0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_REN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_RCLK_RD0 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD1 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD2 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD3 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD4 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD5 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD6 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD7 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD8 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD9 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD10 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD11 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD12 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD13 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD14 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD15 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD16 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD17 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD18 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD19 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD20 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD21 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD22 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD23 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD24 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD25 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD26 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD27 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD28 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD29 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD30 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD31 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD32 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD33 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD34 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD35 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_RDAD15_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD14_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD13_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD12_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD11_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD10_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD9_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD8_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD7_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD6_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD5_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD4_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD3_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD15_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD14_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD13_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD12_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD11_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD10_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD9_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD8_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD7_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD6_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD5_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD4_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD3_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD15_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD14_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD13_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD12_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD11_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD10_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD9_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD8_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD15_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD14_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD13_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD12_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD11_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD10_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD9_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD8_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD35_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD34_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD33_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD32_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD31_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD30_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD29_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD28_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD27_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD26_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD25_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD24_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD23_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD22_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD21_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD20_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD19_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD18_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD17_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD16_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD15_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD14_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD13_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD12_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD11_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD10_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD9_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD8_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD35_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD34_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD33_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD32_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD31_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD30_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD29_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD28_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD27_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD26_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD25_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD24_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD23_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD22_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD21_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD20_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD19_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD18_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD17_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD16_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD15_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD14_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD13_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD12_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD11_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD10_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD9_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD8_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD15_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD14_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD13_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD12_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD11_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD10_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD9_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD8_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD7_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD6_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD5_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD4_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD3_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD15_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD14_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD13_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD12_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD11_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD10_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD9_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD8_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD7_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD6_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD5_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD4_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD3_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RW2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RW1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RW0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RW2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RW1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RW0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD15_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD14_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD13_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD12_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD11_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD10_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD9_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD8_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD15_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD14_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD13_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD12_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD11_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD10_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD9_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD8_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD35_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD34_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD33_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD32_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD31_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD30_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD29_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD28_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD27_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD26_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD25_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD24_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD23_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD22_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD21_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD20_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD19_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD18_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD17_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD16_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD15_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD14_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD13_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD12_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD11_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD10_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD9_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD8_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD35_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD34_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD33_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD32_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD31_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD30_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD29_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD28_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD27_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD26_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD25_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD24_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD23_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD22_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD21_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD20_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD19_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD18_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD17_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD16_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD15_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD14_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD13_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD12_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD11_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD10_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD9_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD8_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WW2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WW1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WW0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WW2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WW1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WW0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_REN_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WEN_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_REN_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WEN_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_REN_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WEN_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_REN_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WEN_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns
);
--pragma translate_on
PORT (
DEPTH3 : IN STD_ULOGIC ;
DEPTH2 : IN STD_ULOGIC ;
DEPTH1 : IN STD_ULOGIC ;
DEPTH0 : IN STD_ULOGIC ;
WRAD15 : IN STD_ULOGIC ;
WRAD14 : IN STD_ULOGIC ;
WRAD13 : IN STD_ULOGIC ;
WRAD12 : IN STD_ULOGIC ;
WRAD11 : IN STD_ULOGIC ;
WRAD10 : IN STD_ULOGIC ;
WRAD9 : IN STD_ULOGIC ;
WRAD8 : IN STD_ULOGIC ;
WRAD7 : IN STD_ULOGIC ;
WRAD6 : IN STD_ULOGIC ;
WRAD5 : IN STD_ULOGIC ;
WRAD4 : IN STD_ULOGIC ;
WRAD3 : IN STD_ULOGIC ;
WRAD2 : IN STD_ULOGIC ;
WRAD1 : IN STD_ULOGIC ;
WRAD0 : IN STD_ULOGIC ;
WD35 : IN STD_ULOGIC ;
WD34 : IN STD_ULOGIC ;
WD33 : IN STD_ULOGIC ;
WD32 : IN STD_ULOGIC ;
WD31 : IN STD_ULOGIC ;
WD30 : IN STD_ULOGIC ;
WD29 : IN STD_ULOGIC ;
WD28 : IN STD_ULOGIC ;
WD27 : IN STD_ULOGIC ;
WD26 : IN STD_ULOGIC ;
WD25 : IN STD_ULOGIC ;
WD24 : IN STD_ULOGIC ;
WD23 : IN STD_ULOGIC ;
WD22 : IN STD_ULOGIC ;
WD21 : IN STD_ULOGIC ;
WD20 : IN STD_ULOGIC ;
WD19 : IN STD_ULOGIC ;
WD18 : IN STD_ULOGIC ;
WD17 : IN STD_ULOGIC ;
WD16 : IN STD_ULOGIC ;
WD15 : IN STD_ULOGIC ;
WD14 : IN STD_ULOGIC ;
WD13 : IN STD_ULOGIC ;
WD12 : IN STD_ULOGIC ;
WD11 : IN STD_ULOGIC ;
WD10 : IN STD_ULOGIC ;
WD9 : IN STD_ULOGIC ;
WD8 : IN STD_ULOGIC ;
WD7 : IN STD_ULOGIC ;
WD6 : IN STD_ULOGIC ;
WD5 : IN STD_ULOGIC ;
WD4 : IN STD_ULOGIC ;
WD3 : IN STD_ULOGIC ;
WD2 : IN STD_ULOGIC ;
WD1 : IN STD_ULOGIC ;
WD0 : IN STD_ULOGIC ;
WW2 : IN STD_ULOGIC ;
WW1 : IN STD_ULOGIC ;
WW0 : IN STD_ULOGIC ;
WEN : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
RDAD15 : IN STD_ULOGIC ;
RDAD14 : IN STD_ULOGIC ;
RDAD13 : IN STD_ULOGIC ;
RDAD12 : IN STD_ULOGIC ;
RDAD11 : IN STD_ULOGIC ;
RDAD10 : IN STD_ULOGIC ;
RDAD9 : IN STD_ULOGIC ;
RDAD8 : IN STD_ULOGIC ;
RDAD7 : IN STD_ULOGIC ;
RDAD6 : IN STD_ULOGIC ;
RDAD5 : IN STD_ULOGIC ;
RDAD4 : IN STD_ULOGIC ;
RDAD3 : IN STD_ULOGIC ;
RDAD2 : IN STD_ULOGIC ;
RDAD1 : IN STD_ULOGIC ;
RDAD0 : IN STD_ULOGIC ;
RW2 : IN STD_ULOGIC ;
RW1 : IN STD_ULOGIC ;
RW0 : IN STD_ULOGIC ;
REN : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
RD35 : OUT STD_ULOGIC ;
RD34 : OUT STD_ULOGIC ;
RD33 : OUT STD_ULOGIC ;
RD32 : OUT STD_ULOGIC ;
RD31 : OUT STD_ULOGIC ;
RD30 : OUT STD_ULOGIC ;
RD29 : OUT STD_ULOGIC ;
RD28 : OUT STD_ULOGIC ;
RD27 : OUT STD_ULOGIC ;
RD26 : OUT STD_ULOGIC ;
RD25 : OUT STD_ULOGIC ;
RD24 : OUT STD_ULOGIC ;
RD23 : OUT STD_ULOGIC ;
RD22 : OUT STD_ULOGIC ;
RD21 : OUT STD_ULOGIC ;
RD20 : OUT STD_ULOGIC ;
RD19 : OUT STD_ULOGIC ;
RD18 : OUT STD_ULOGIC ;
RD17 : OUT STD_ULOGIC ;
RD16 : OUT STD_ULOGIC ;
RD15 : OUT STD_ULOGIC ;
RD14 : OUT STD_ULOGIC ;
RD13 : OUT STD_ULOGIC ;
RD12 : OUT STD_ULOGIC ;
RD11 : OUT STD_ULOGIC ;
RD10 : OUT STD_ULOGIC ;
RD9 : OUT STD_ULOGIC ;
RD8 : OUT STD_ULOGIC ;
RD7 : OUT STD_ULOGIC ;
RD6 : OUT STD_ULOGIC ;
RD5 : OUT STD_ULOGIC ;
RD4 : OUT STD_ULOGIC ;
RD3 : OUT STD_ULOGIC ;
RD2 : OUT STD_ULOGIC ;
RD1 : OUT STD_ULOGIC ;
RD0 : OUT STD_ULOGIC
);
end component;
component RAM64K36P
--pragma translate_off
GENERIC (
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
Xon : Boolean := False;
MsgOn : Boolean := True;
MEMORYFILE : String := "";
tipd_DEPTH3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DEPTH2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DEPTH1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DEPTH0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD15 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD14 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD13 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD12 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD9 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD8 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD7 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD6 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WRAD0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD35 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD34 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD33 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD32 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD31 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD30 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD29 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD28 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD27 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD26 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD25 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD24 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD23 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD22 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD21 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD20 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD19 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD18 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD17 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD16 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD15 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD14 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD13 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD12 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD9 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD8 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD7 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD6 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WD0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WW2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WW1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WW0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WEN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_WCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD15 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD14 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD13 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD12 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD11 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD10 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD9 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD8 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD7 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD6 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RDAD0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RW2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RW1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RW0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_REN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_RCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_RCLK_RD0 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD1 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD2 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD3 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD4 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD5 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD6 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD7 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD8 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD9 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD10 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD11 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD12 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD13 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD14 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD15 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD16 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD17 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD18 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD19 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD20 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD21 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD22 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD23 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD24 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD25 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD26 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD27 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD28 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD29 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD30 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD31 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD32 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD33 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD34 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_RCLK_RD35 : VitalDelayType01 := (0.100 ns, 0.100 ns);
tsetup_RDAD15_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD14_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD13_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD12_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD11_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD10_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD9_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD8_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD7_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD6_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD5_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD4_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD3_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD15_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD14_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD13_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD12_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD11_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD10_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD9_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD8_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD7_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD6_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD5_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD4_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD3_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RDAD0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_RW0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_DEPTH0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD15_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD14_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD13_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD12_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD11_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD10_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD9_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD8_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD15_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD14_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD13_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD12_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD11_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD10_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD9_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD8_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WRAD0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD35_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD34_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD33_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD32_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD31_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD30_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD29_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD28_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD27_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD26_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD25_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD24_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD23_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD22_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD21_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD20_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD19_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD18_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD17_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD16_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD15_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD14_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD13_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD12_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD11_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD10_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD9_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD8_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD35_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD34_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD33_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD32_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD31_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD30_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD29_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD28_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD27_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD26_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD25_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD24_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD23_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD22_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD21_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD20_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD19_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD18_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD17_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD16_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD15_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD14_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD13_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD12_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD11_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD10_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD9_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD8_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WD0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WW0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD15_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD14_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD13_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD12_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD11_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD10_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD9_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD8_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD7_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD6_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD5_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD4_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD3_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD15_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD14_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD13_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD12_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD11_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD10_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD9_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD8_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD7_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD6_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD5_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD4_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD3_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RDAD0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RW2_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RW1_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RW0_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_RW2_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RW1_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_RW0_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_DEPTH0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD15_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD14_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD13_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD12_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD11_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD10_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD9_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD8_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD15_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD14_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD13_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD12_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD11_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD10_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD9_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD8_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WRAD0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD35_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD34_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD33_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD32_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD31_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD30_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD29_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD28_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD27_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD26_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD25_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD24_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD23_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD22_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD21_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD20_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD19_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD18_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD17_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD16_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD15_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD14_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD13_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD12_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD11_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD10_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD9_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD8_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD7_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD6_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD5_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD4_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD3_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WD35_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD34_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD33_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD32_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD31_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD30_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD29_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD28_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD27_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD26_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD25_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD24_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD23_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD22_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD21_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD20_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD19_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD18_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD17_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD16_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD15_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD14_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD13_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD12_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD11_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD10_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD9_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD8_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD7_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD6_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD5_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD4_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD3_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WD0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WW2_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WW1_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WW0_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WW2_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WW1_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WW0_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_REN_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WEN_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_REN_RCLK_posedge_posedge : VitalDelayType := 0.000 ns;
thold_WEN_WCLK_posedge_posedge : VitalDelayType := 0.000 ns;
tsetup_REN_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tsetup_WEN_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_REN_RCLK_negedge_posedge : VitalDelayType := 0.000 ns;
thold_WEN_WCLK_negedge_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_posedge : VitalDelayType := 0.000 ns;
tpw_RCLK_negedge : VitalDelayType := 0.000 ns;
tpw_WCLK_posedge : VitalDelayType := 0.000 ns;
tpw_WCLK_negedge : VitalDelayType := 0.000 ns
);
--pragma translate_on
PORT (
DEPTH3 : IN STD_ULOGIC ;
DEPTH2 : IN STD_ULOGIC ;
DEPTH1 : IN STD_ULOGIC ;
DEPTH0 : IN STD_ULOGIC ;
WRAD15 : IN STD_ULOGIC ;
WRAD14 : IN STD_ULOGIC ;
WRAD13 : IN STD_ULOGIC ;
WRAD12 : IN STD_ULOGIC ;
WRAD11 : IN STD_ULOGIC ;
WRAD10 : IN STD_ULOGIC ;
WRAD9 : IN STD_ULOGIC ;
WRAD8 : IN STD_ULOGIC ;
WRAD7 : IN STD_ULOGIC ;
WRAD6 : IN STD_ULOGIC ;
WRAD5 : IN STD_ULOGIC ;
WRAD4 : IN STD_ULOGIC ;
WRAD3 : IN STD_ULOGIC ;
WRAD2 : IN STD_ULOGIC ;
WRAD1 : IN STD_ULOGIC ;
WRAD0 : IN STD_ULOGIC ;
WD35 : IN STD_ULOGIC ;
WD34 : IN STD_ULOGIC ;
WD33 : IN STD_ULOGIC ;
WD32 : IN STD_ULOGIC ;
WD31 : IN STD_ULOGIC ;
WD30 : IN STD_ULOGIC ;
WD29 : IN STD_ULOGIC ;
WD28 : IN STD_ULOGIC ;
WD27 : IN STD_ULOGIC ;
WD26 : IN STD_ULOGIC ;
WD25 : IN STD_ULOGIC ;
WD24 : IN STD_ULOGIC ;
WD23 : IN STD_ULOGIC ;
WD22 : IN STD_ULOGIC ;
WD21 : IN STD_ULOGIC ;
WD20 : IN STD_ULOGIC ;
WD19 : IN STD_ULOGIC ;
WD18 : IN STD_ULOGIC ;
WD17 : IN STD_ULOGIC ;
WD16 : IN STD_ULOGIC ;
WD15 : IN STD_ULOGIC ;
WD14 : IN STD_ULOGIC ;
WD13 : IN STD_ULOGIC ;
WD12 : IN STD_ULOGIC ;
WD11 : IN STD_ULOGIC ;
WD10 : IN STD_ULOGIC ;
WD9 : IN STD_ULOGIC ;
WD8 : IN STD_ULOGIC ;
WD7 : IN STD_ULOGIC ;
WD6 : IN STD_ULOGIC ;
WD5 : IN STD_ULOGIC ;
WD4 : IN STD_ULOGIC ;
WD3 : IN STD_ULOGIC ;
WD2 : IN STD_ULOGIC ;
WD1 : IN STD_ULOGIC ;
WD0 : IN STD_ULOGIC ;
WW2 : IN STD_ULOGIC ;
WW1 : IN STD_ULOGIC ;
WW0 : IN STD_ULOGIC ;
WEN : IN STD_ULOGIC ;
WCLK : IN STD_ULOGIC ;
RDAD15 : IN STD_ULOGIC ;
RDAD14 : IN STD_ULOGIC ;
RDAD13 : IN STD_ULOGIC ;
RDAD12 : IN STD_ULOGIC ;
RDAD11 : IN STD_ULOGIC ;
RDAD10 : IN STD_ULOGIC ;
RDAD9 : IN STD_ULOGIC ;
RDAD8 : IN STD_ULOGIC ;
RDAD7 : IN STD_ULOGIC ;
RDAD6 : IN STD_ULOGIC ;
RDAD5 : IN STD_ULOGIC ;
RDAD4 : IN STD_ULOGIC ;
RDAD3 : IN STD_ULOGIC ;
RDAD2 : IN STD_ULOGIC ;
RDAD1 : IN STD_ULOGIC ;
RDAD0 : IN STD_ULOGIC ;
RW2 : IN STD_ULOGIC ;
RW1 : IN STD_ULOGIC ;
RW0 : IN STD_ULOGIC ;
REN : IN STD_ULOGIC ;
RCLK : IN STD_ULOGIC ;
RD35 : OUT STD_ULOGIC ;
RD34 : OUT STD_ULOGIC ;
RD33 : OUT STD_ULOGIC ;
RD32 : OUT STD_ULOGIC ;
RD31 : OUT STD_ULOGIC ;
RD30 : OUT STD_ULOGIC ;
RD29 : OUT STD_ULOGIC ;
RD28 : OUT STD_ULOGIC ;
RD27 : OUT STD_ULOGIC ;
RD26 : OUT STD_ULOGIC ;
RD25 : OUT STD_ULOGIC ;
RD24 : OUT STD_ULOGIC ;
RD23 : OUT STD_ULOGIC ;
RD22 : OUT STD_ULOGIC ;
RD21 : OUT STD_ULOGIC ;
RD20 : OUT STD_ULOGIC ;
RD19 : OUT STD_ULOGIC ;
RD18 : OUT STD_ULOGIC ;
RD17 : OUT STD_ULOGIC ;
RD16 : OUT STD_ULOGIC ;
RD15 : OUT STD_ULOGIC ;
RD14 : OUT STD_ULOGIC ;
RD13 : OUT STD_ULOGIC ;
RD12 : OUT STD_ULOGIC ;
RD11 : OUT STD_ULOGIC ;
RD10 : OUT STD_ULOGIC ;
RD9 : OUT STD_ULOGIC ;
RD8 : OUT STD_ULOGIC ;
RD7 : OUT STD_ULOGIC ;
RD6 : OUT STD_ULOGIC ;
RD5 : OUT STD_ULOGIC ;
RD4 : OUT STD_ULOGIC ;
RD3 : OUT STD_ULOGIC ;
RD2 : OUT STD_ULOGIC ;
RD1 : OUT STD_ULOGIC ;
RD0 : OUT STD_ULOGIC
);
end component;
component DDR_OUT
port(DR, DF, E, CLK, PRE, CLR : in std_logic; Q : out std_logic) ;
end component;
component DDR_REG
port(D, E, CLK, CLR, PRE : in std_logic; QR, QF : out std_logic) ;
end component;
component PLL
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
f_REFCLK_LOCK : Integer := 3; -- Number of REFCLK pulses after which LOCK is raised
tipd_PWRDWN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_REFCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_LOWFREQ : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_OSC2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_OSC1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_OSC0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DELAYLINE4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DELAYLINE3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DELAYLINE2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DELAYLINE1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DELAYLINE0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_REFCLK_CLK1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_REFCLK_CLK2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_REFCLK_LOCK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PWRDWN : in STD_ULOGIC; -- Active high
REFCLK : in STD_ULOGIC;
LOWFREQ : in STD_ULOGIC;
OSC2 : in STD_ULOGIC;
OSC1 : in STD_ULOGIC;
OSC0 : in STD_ULOGIC;
DIVI5 : in STD_ULOGIC; -- Clock multiplier
DIVI4 : in STD_ULOGIC; -- Clock multiplier
DIVI3 : in STD_ULOGIC; -- Clock multiplier
DIVI2 : in STD_ULOGIC; -- Clock multiplier
DIVI1 : in STD_ULOGIC; -- Clock multiplier
DIVI0 : in STD_ULOGIC; -- Clock multiplier
DIVJ5 : in STD_ULOGIC; -- Clock divider
DIVJ4 : in STD_ULOGIC; -- Clock divider
DIVJ3 : in STD_ULOGIC; -- Clock divider
DIVJ2 : in STD_ULOGIC; -- Clock divider
DIVJ1 : in STD_ULOGIC; -- Clock divider
DIVJ0 : in STD_ULOGIC; -- Clock divider
DELAYLINE4 : in STD_ULOGIC; -- Delay Value
DELAYLINE3 : in STD_ULOGIC; -- Delay Value
DELAYLINE2 : in STD_ULOGIC; -- Delay Value
DELAYLINE1 : in STD_ULOGIC; -- Delay Value
DELAYLINE0 : in STD_ULOGIC; -- Delay Value
LOCK : out STD_ULOGIC;
CLK1 : out STD_ULOGIC;
CLK2 : out STD_ULOGIC);
end component;
component PLLFB
--pragma translate_off
generic(
TimingChecksOn: Boolean := True;
InstancePath: STRING := "*";
Xon: Boolean := False;
MsgOn: Boolean := True;
f_REFCLK_LOCK : Integer := 3; -- Number of REFCLK pulses after which LOCK is raised
tipd_PWRDWN : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_REFCLK : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FB : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_LOWFREQ : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_OSC2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_OSC1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_OSC0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVI0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ5 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DIVJ0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DELAYLINE4 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DELAYLINE3 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DELAYLINE2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DELAYLINE1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_DELAYLINE0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_REFCLK_CLK1 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_REFCLK_CLK2 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tpd_REFCLK_LOCK : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
PWRDWN : in STD_ULOGIC; -- Active high
REFCLK : in STD_ULOGIC;
FB : in STD_ULOGIC;
LOWFREQ : in STD_ULOGIC;
OSC2 : in STD_ULOGIC;
OSC1 : in STD_ULOGIC;
OSC0 : in STD_ULOGIC;
DIVI5 : in STD_ULOGIC; -- Clock multiplier
DIVI4 : in STD_ULOGIC; -- Clock multiplier
DIVI3 : in STD_ULOGIC; -- Clock multiplier
DIVI2 : in STD_ULOGIC; -- Clock multiplier
DIVI1 : in STD_ULOGIC; -- Clock multiplier
DIVI0 : in STD_ULOGIC; -- Clock multiplier
DIVJ5 : in STD_ULOGIC; -- Clock divider
DIVJ4 : in STD_ULOGIC; -- Clock divider
DIVJ3 : in STD_ULOGIC; -- Clock divider
DIVJ2 : in STD_ULOGIC; -- Clock divider
DIVJ1 : in STD_ULOGIC; -- Clock divider
DIVJ0 : in STD_ULOGIC; -- Clock divider
DELAYLINE4 : in STD_ULOGIC; -- Delay Value
DELAYLINE3 : in STD_ULOGIC; -- Delay Value
DELAYLINE2 : in STD_ULOGIC; -- Delay Value
DELAYLINE1 : in STD_ULOGIC; -- Delay Value
DELAYLINE0 : in STD_ULOGIC; -- Delay Value
LOCK : out STD_ULOGIC;
CLK1 : out STD_ULOGIC;
CLK2 : out STD_ULOGIC);
end component;
---------------- CELL:NOR5D ---------------
COMPONENT NOR5D
port(
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : in std_logic;
Y : out std_logic);
END COMPONENT;
------ Component ADDSUB1 ------
component ADDSUB1
--pragma translate_off
generic(
TimingChecksOn:Boolean :=True;
Xon: Boolean :=False;
InstancePath: STRING :="*";
MsgOn: Boolean :=True;
tpd_A_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_AS_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_FCI_FCO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_FCI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_AS : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
FCI : in STD_ULOGIC;
B : in STD_ULOGIC;
AS : in STD_ULOGIC;
S : out STD_ULOGIC;
FCO : out STD_ULOGIC);
end component;
---------------- CELL:NAND5D ---------------
COMPONENT NAND5D
port(
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
E : in std_logic;
Y : out std_logic);
END COMPONENT;
------ Component FA1A ------
component FA1A
--pragma translate_off
generic(
TimingChecksOn:Boolean :=True;
Xon: Boolean :=False;
InstancePath: STRING :="*";
MsgOn: Boolean :=True;
tpd_CI_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CI_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CI : in STD_ULOGIC;
B : in STD_ULOGIC;
A : in STD_ULOGIC;
CO : out STD_ULOGIC;
S : out STD_ULOGIC);
end component;
------ Component FA1B ------
component FA1B
--pragma translate_off
generic(
TimingChecksOn:Boolean :=True;
Xon: Boolean :=False;
InstancePath: STRING :="*";
MsgOn: Boolean :=True;
tpd_A_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CI_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CI_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
A : in STD_ULOGIC;
B : in STD_ULOGIC;
CI : in STD_ULOGIC;
CO : out STD_ULOGIC;
S : out STD_ULOGIC);
end component;
------ Component FA2A ------
component FA2A
--pragma translate_off
generic(
TimingChecksOn:Boolean :=True;
Xon: Boolean :=False;
InstancePath: STRING :="*";
MsgOn: Boolean :=True;
tpd_CI_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A0_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A1_CO : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A0_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_A1_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_B_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tpd_CI_S : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns));
--pragma translate_on
port(
CI : in STD_ULOGIC;
B : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
CO : out STD_ULOGIC;
S : out STD_ULOGIC);
end component;
attribute syn_tpd11 : string;
attribute syn_tpd11 of inbuf_pci : component is "pad -> y = 2.0";
attribute syn_tpd12 : string;
attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";
attribute syn_tpd13 : string;
attribute syn_tpd13 of outbuf_pci : component is "d -> pad = 2.0";
attribute syn_tpd14 : string;
attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";
attribute syn_black_box : boolean;
attribute syn_black_box of RAM64K36 : component is true;
attribute syn_tco1 : string;
attribute syn_tco2 : string;
attribute syn_tco1 of RAM64K36 : component is
"RCLK->RD0,RD1,RD2,RD3,RD4,RD5,RD6,RD7,RD8,RD9,RD10,RD11,RD12,RD13,RD14,RD15,RD16,RD17,RD18,RD19,RD20,RD21,RD22,RD23,RD24,RD25,RD26,RD27,RD28,RD29,RD30,RD31,RD32,RD33,RD34,RD35 = 4.0";
END COMPONENTS;
| mit | 8412e5272baa056bb0627d6f8fbb9c63 | 0.60332 | 2.875237 | false | false | false | false |
amerc/phimii | ininex.vhd | 2 | 2,893 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:08:11 04/06/2014
-- Design Name:
-- Module Name: /home/amer/Nexys3/TCP/ininex.vhd
-- Project Name: TCP
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: initPhyNexys3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ininex IS
END ininex;
ARCHITECTURE behavior OF ininex IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT initPhyNexys3
PORT(
clk : IN std_logic;
reset : IN std_logic;
phy_reset : OUT std_logic;
out_en : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal phy_reset : std_logic;
signal out_en : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: initPhyNexys3 PORT MAP (
clk => clk,
reset => reset,
phy_reset => phy_reset,
out_en => out_en
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*400;
-- insert stimulus here
--reset <= '1';
-----
-- when 320 => tmpreset <= '1'; tmpouten <= '1'; (32.05 ns)
-- when 131147 => tmpreset <= '0'; tmpouten <= '1'; (2.62 ms)
-- when 1250000 => tmpreset <= '0'; tmpouten <= '0';(25 ms)
-- when 1499900 => tmpreset <= '0'; tmpouten <= '0'; (30 ms)
-- when 1499998 => tmpreset <= '1'; tmpouten <= '0'; (40 ns)
-- when 1500000 => tmpreset <= '1'; tmpouten <= '1'; (20 ns)
wait for clk_period*4;
reset <= '0';
wait for 40 ns;
reset <= '0';
wait for 60 ms;
reset <= '0';
wait for 4 ns;
reset <= '0';
wait for 58 ms;
reset <= '0';
wait for 250 ms;
reset <= '1';
wait for 5 ms;
--reset <= '1';
wait for 6 ms;
reset <= '0';
wait for 45 ms;
wait;
end process;
END;
| mit | e6e9995d713027f620f7bd7a720c9d07 | 0.573799 | 3.452267 | false | false | false | false |
franz/pocl | examples/accel/rtl/vhdl/mul_dsp48.vhdl | 2 | 15,866 | -- Copyright (c) 2019 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : MUL unit for Xilinx devices
-------------------------------------------------------------------------------
-- File : mul_dsp48.vhdl
-- Author : Kati Tervo
-- Company :
-- Created : 2017-09-13
-- Last update: 2017-09-13
-- Platform :
-------------------------------------------------------------------------------
-- Description: 32x32 multiplier for Xilinx FPGAs
--
-- Revisions :
-- Date Version Author Description
-- 2019-03-12 1.0 katte Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity mul_dsp48 is
generic (
latency_g : integer
); port (
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
load_in : in std_logic;
operand_a_in : in std_logic_vector(32-1 downto 0);
operand_b_in : in std_logic_vector(32-1 downto 0);
operand_c_in : in std_logic_vector(32-1 downto 0);
result_out : out std_logic_vector(32-1 downto 0)
);
end mul_dsp48;
architecture rtl of mul_dsp48 is
signal A_full, A_half_0, A_half_1 : std_logic_vector(30-1 downto 0);
signal B_full, B_half_0, B_half_1 : std_logic_vector(18-1 downto 0);
signal P_full, P_half_0, P_half_1 : std_logic_vector(48-1 downto 0);
signal C_full : std_logic_vector(48-1 downto 0);
signal full_out, half_out_0, half_out_1 : std_logic_vector(32-1 downto 0);
signal result, result_r : std_logic_vector(32-1 downto 0);
attribute use_dsp : string;
attribute use_dsp of result : signal is "no";
signal load_r, dsp_enable, output_enable : std_logic;
function front_latency(total_latency : integer) return integer is
begin
if total_latency > 1 then
return 1;
else
return 0;
end if;
end function;
function back_latency(total_latency : integer) return integer is
begin
if total_latency > 0 then
return 1;
else
return 0;
end if;
end function;
begin
dsp_enable <= not glock_in;
output_enable_no_load_one: if latency_g > 1 generate
output_enable <= load_r and dsp_enable;
end generate;
output_enable_no_load_two: if latency_g <= 1 generate
output_enable <= load_in and dsp_enable;
end generate;
-- Multiplication
B_full <= "00" & operand_b_in(15 downto 0);
A_full <= "00000000000000" & operand_a_in(15 downto 0);
C_full <= X"0000" & operand_c_in;
B_half_0 <= "00" & operand_b_in(31 downto 16);
A_half_0 <= "00000000000000" & operand_a_in(15 downto 0);
B_half_1 <= "00" & operand_a_in(31 downto 16);
A_half_1 <= "00000000000000" & operand_b_in(15 downto 0);
full_out <= P_full(31 downto 0);
half_out_0 <= P_half_0(15 downto 0) & X"0000";
half_out_1 <= P_half_1(15 downto 0) & X"0000";
DSP48E1_full_inst : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- port A
B_INPUT => "DIRECT", -- port B
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "DYNAMIC", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => front_latency(latency_g), -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => front_latency(latency_g), -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 0, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => back_latency(latency_g) -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Useless ports, static inputs (no need to reset)
CLK => clk,
ACOUT => open, BCOUT => open, CARRYCASCOUT => open, MULTSIGNOUT => open,
PCOUT => open, OVERFLOW => open, PATTERNBDETECT => open,
PATTERNDETECT => open, UNDERFLOW => open, CARRYOUT => open,
ACIN => (others => '0'), BCIN => (others => '0'), CARRYIN => '0',
CARRYCASCIN => '0', MULTSIGNIN => '0', PCIN => (others => '0'),
RSTA => '0', RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0',
RSTC => '0', RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0',
RSTP => '0', CARRYINSEL => "000", ALUMODE => "0000",
-- Control:
INMODE => "00000", OPMODE => "0110101",
-- Data:
C => C_full, D => (others => '0'),
A => A_full, B => B_full, P => P_full,
-- Enable most registers with glock_in
CEA1 => dsp_enable, CEA2 => dsp_enable, CEAD => dsp_enable,
CEALUMODE => dsp_enable, CEB1 => dsp_enable, CEB2 => dsp_enable,
CEC => dsp_enable, CECARRYIN => dsp_enable, CECTRL => dsp_enable,
CED => dsp_enable, CEINMODE => dsp_enable, CEM => dsp_enable,
-- enable the output registers when the output needs to be updated
CEP => output_enable
);
DSP48E1_half_0_inst : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- port A
B_INPUT => "DIRECT", -- port B
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "DYNAMIC", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipelgine stages for ALUMODE (0 or 1)
AREG => front_latency(latency_g), -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => front_latency(latency_g), -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 0, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => back_latency(latency_g) -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Useless ports, static inputs (no need to reset)
CLK => clk,
ACOUT => open, BCOUT => open, CARRYCASCOUT => open, MULTSIGNOUT => open,
PCOUT => open, OVERFLOW => open, PATTERNBDETECT => open,
PATTERNDETECT => open, UNDERFLOW => open, CARRYOUT => open,
ACIN => (others => '0'), BCIN => (others => '0'), CARRYIN => '0',
CARRYCASCIN => '0', MULTSIGNIN => '0', PCIN => (others => '0'),
RSTA => '0', RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0',
RSTC => '0', RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0',
RSTP => '0', CARRYINSEL => "000", ALUMODE => "0000",
-- Control:
INMODE => "00000", OPMODE => "0000101",
-- Data:
C => (others => '0'), D => (others => '0'),
A => A_half_0, B => B_half_0, P => P_half_0,
-- Enable most registers with glock_in
CEA1 => dsp_enable, CEA2 => dsp_enable, CEAD => dsp_enable,
CEALUMODE => dsp_enable, CEB1 => dsp_enable, CEB2 => dsp_enable,
CEC => dsp_enable, CECARRYIN => dsp_enable, CECTRL => dsp_enable,
CED => dsp_enable, CEINMODE => dsp_enable, CEM => dsp_enable,
-- enable the output registers when the output needs to be updated
CEP => output_enable
);
DSP48E1_half_1_inst : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- port A
B_INPUT => "DIRECT", -- port B
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "DYNAMIC", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipelgine stages for ALUMODE (0 or 1)
AREG => front_latency(latency_g), -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => front_latency(latency_g), -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 1, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 0, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => back_latency(latency_g) -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Useless ports, static inputs (no need to reset)
CLK => clk,
ACOUT => open, BCOUT => open, CARRYCASCOUT => open, MULTSIGNOUT => open,
PCOUT => open, OVERFLOW => open, PATTERNBDETECT => open,
PATTERNDETECT => open, UNDERFLOW => open, CARRYOUT => open,
ACIN => (others => '0'), BCIN => (others => '0'), CARRYIN => '0',
CARRYCASCIN => '0', MULTSIGNIN => '0', PCIN => (others => '0'),
RSTA => '0', RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0',
RSTC => '0', RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0',
RSTP => '0', CARRYINSEL => "000", ALUMODE => "0000",
-- Control:
INMODE => "00000", OPMODE => "0000101",
-- Data:
C => (others => '0'), D => (others => '0'),
A => A_half_1, B => B_half_1, P => P_half_1,
-- Enable most registers with glock_in
CEA1 => dsp_enable, CEA2 => dsp_enable, CEAD => dsp_enable,
CEALUMODE => dsp_enable, CEB1 => dsp_enable, CEB2 => dsp_enable,
CEC => dsp_enable, CECARRYIN => dsp_enable, CECTRL => dsp_enable,
CED => dsp_enable, CEINMODE => dsp_enable, CEM => dsp_enable,
-- enable the output registers when the output needs to be updated
CEP => output_enable
);
load_register: if latency_g > 1 generate
main : process(clk)
begin
if rising_edge(clk) then
if rstx = '0' then
load_r <= '0';
elsif glock_in = '0' then
load_r <= load_in;
end if;
end if;
end process main;
end generate;
result <= std_logic_vector(signed(full_out)
+ signed(half_out_0)
+ signed(half_out_1));
result_reg: if latency_g > 2 generate
result_proc : process(clk)
begin
if rising_edge(clk) then
if rstx = '0' then
result_r <= (others => '0');
elsif glock_in = '0' then
result_r <= result;
end if;
end if;
end process result_proc;
result_out <= result_r;
end generate;
result_comb: if latency_g <= 2 generate
result_out <= result;
end generate;
end rtl;
| mit | a8138bbb3e682a6a829163d180a169ad | 0.569016 | 3.866927 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/altera_mf/simprims/altera_mf_components.vhd | 2 | 90,634 | -- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 7.1 Build 156 04/30/2007
----------------------------------------------------------------------------
-- ALtera Megafunction Component Declaration File
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package altera_mf_components is
-- pragma translate_off
type altera_mf_logic_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
component lcell
port (
a_in : in std_logic;
a_out : out std_logic);
end component;
component altcam
generic (
width : natural := 1;
widthad : natural := 1;
numwords : natural := 1;
lpm_file : string := "UNUSED";
lpm_filex : string := "UNUSED";
match_mode : string := "MULTIPLE";
output_reg : string := "UNREGISTERED";
output_aclr : string := "ON";
pattern_reg : string := "INCLOCK";
pattern_aclr : string := "ON";
wraddress_aclr : string := "ON";
wrx_reg : string := "INCLOCK";
wrx_aclr : string := "ON";
wrcontrol_aclr : string := "ON";
use_eab : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altcam" );
port (
pattern : in std_logic_vector(width-1 downto 0);
wrx : in std_logic_vector(width-1 downto 0) := (others => 'Z');
wrxused : in std_logic := '1';
wrdelete : in std_logic := '0';
wraddress : in std_logic_vector(widthad-1 downto 0);
wren : in std_logic;
inclock : in std_logic;
inclocken : in std_logic := '1';
inaclr : in std_logic := '0';
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
outaclr : in std_logic := '0';
mstart : in std_logic := 'X';
mnext : in std_logic := '0';
maddress : out std_logic_vector(widthad-1 downto 0);
mbits : out std_logic_vector(numwords-1 downto 0);
mfound : out std_logic;
mcount : out std_logic_vector(widthad-1 downto 0);
rdbusy : out std_logic;
wrbusy : out std_logic );
end component;
component altclklock
generic (
inclock_period : natural := 10000; -- units in ps
inclock_settings : string := "UNUSED";
valid_lock_cycles : natural := 5;
invalid_lock_cycles : natural := 5;
valid_lock_multiplier : natural := 5;
invalid_lock_multiplier : natural := 5;
operation_mode : string := "NORMAL";
clock0_boost : natural := 1;
clock0_divide : natural := 1;
clock0_settings : string := "UNUSED";
clock0_time_delay : string := "0";
clock1_boost : natural := 1;
clock1_divide : natural := 1;
clock1_settings : string := "UNUSED";
clock1_time_delay : string := "0";
clock2_boost : natural := 1;
clock2_divide : natural := 1;
clock2_settings : string := "UNUSED";
clock2_time_delay : string := "0";
clock_ext_boost : natural := 1;
clock_ext_divide : natural := 1;
clock_ext_settings : string := "UNUSED";
clock_ext_time_delay : string := "0";
outclock_phase_shift : natural := 0; -- units in ps
intended_device_family : string := "APEX20KE" ;
lpm_hint : string := "UNUSED";
lpm_type : string := "altclklock" );
port(
inclock : in std_logic; -- required port, input reference clock
inclocken : in std_logic := '1'; -- PLL enable signal
fbin : in std_logic := '1'; -- feedback input for the PLL
clock0 : out std_logic; -- clock0 output
clock1 : out std_logic; -- clock1 output
clock2 : out std_logic; -- clock2 output, for Mercury only
clock_ext : out std_logic; -- external clock output, for Mercury only
locked : out std_logic ); -- PLL lock signal
end component;
component altlvds_rx
generic (
number_of_channels : natural;
deserialization_factor : natural;
inclock_boost : natural:= 0;
registered_output : string := "ON";
inclock_period : natural;
cds_mode : string := "UNUSED";
intended_device_family : string := "APEX20KE";
input_data_rate : natural:= 0;
inclock_data_alignment : string := "EDGE_ALIGNED";
registered_data_align_input : string :="ON";
common_rx_tx_pll : string :="ON";
enable_dpa_mode : string := "OFF";
enable_dpa_fifo : string := "ON";
use_dpll_rawperror : string := "OFF";
use_coreclock_input : string := "OFF";
dpll_lock_count : natural:= 0;
dpll_lock_window : natural:= 0;
outclock_resource : string := "AUTO";
data_align_rollover : natural := 10;
lose_lock_on_one_change : string := "OFF";
reset_fifo_at_first_lock : string := "ON";
use_external_pll : string := "OFF";
implement_in_les : string := "OFF";
buffer_implementation : string := "RAM";
port_rx_data_align : string := "PORT_CONNECTIVITY";
pll_operation_mode : string := "NORMAL";
x_on_bitslip : string := "ON";
use_no_phase_shift : string := "ON";
rx_align_data_reg : string := "RISING_EDGE";
inclock_phase_shift : integer := 0;
enable_soft_cdr_mode : string := "OFF";
sim_dpa_output_clock_phase_shift : integer := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altlvds_rx";
clk_src_is_pll : string := "off" );
port (
rx_in : in std_logic_vector(number_of_channels-1 downto 0);
rx_inclock : in std_logic := '0';
rx_syncclock : in std_logic := '0';
rx_readclock : in std_logic := '0';
rx_enable : in std_logic := '1';
rx_deskew : in std_logic := '0';
rx_pll_enable : in std_logic := '1';
rx_data_align : in std_logic := '0';
rx_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
rx_coreclk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
pll_areset : in std_logic := '0';
rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
rx_outclock : out std_logic;
rx_locked : out std_logic;
rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0);
rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0);
rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0) );
end component;
component altlvds_tx
generic (
number_of_channels : natural;
deserialization_factor : natural:= 4;
inclock_boost : natural := 0;
outclock_divide_by : positive:= 1;
registered_input : string := "ON";
multi_clock : string := "OFF";
inclock_period : natural;
center_align_msb : string := "UNUSED";
intended_device_family : string := "APEX20KE";
output_data_rate : natural:= 0;
outclock_resource : string := "AUTO";
common_rx_tx_pll : string := "ON";
inclock_data_alignment : string := "EDGE_ALIGNED";
outclock_alignment : string := "EDGE_ALIGNED";
use_external_pll : string := "OFF";
implement_in_les : STRING := "OFF";
preemphasis_setting : natural := 0;
vod_setting : natural := 0;
differential_drive : natural := 0;
outclock_multiply_by : natural := 1;
coreclock_divide_by : natural := 2;
outclock_duty_cycle : natural := 50;
inclock_phase_shift : integer := 0;
outclock_phase_shift : integer := 0;
use_no_phase_shift : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altlvds_tx";
clk_src_is_pll : string := "off" );
port (
tx_in : in std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
tx_inclock : in std_logic := '0';
tx_syncclock : in std_logic := '0';
tx_enable : in std_logic := '1';
sync_inclock : in std_logic := '0';
tx_pll_enable : in std_logic := '1';
pll_areset : in std_logic := '0';
tx_out : out std_logic_vector(number_of_channels-1 downto 0);
tx_outclock : out std_logic;
tx_coreclock : out std_logic;
tx_locked : out std_logic );
end component;
component altdpram
generic (
width : natural;
widthad : natural;
numwords : natural := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
use_eab : string := "ON";
indata_reg : string := "INCLOCK";
indata_aclr : string := "ON";
wraddress_reg : string := "INCLOCK";
wraddress_aclr : string := "ON";
wrcontrol_reg : string := "INCLOCK";
wrcontrol_aclr : string := "ON";
rdaddress_reg : string := "OUTCLOCK";
rdaddress_aclr : string := "ON";
rdcontrol_reg : string := "OUTCLOCK";
rdcontrol_aclr : string := "ON";
outdata_reg : string := "UNREGISTERED";
outdata_aclr : string := "ON";
ram_block_type : string := "AUTO";
width_byteena : natural := 1;
byte_size : natural := 5;
read_during_write_mode_mixed_ports : string := "DONT_CARE";
intended_device_family : string := "APEX20KE";
lpm_type : string := "altdpram" );
port(
wren : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
wraddressstall : in std_logic := '0';
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
rden : in std_logic := '1';
rdaddress : in std_logic_vector(widthad-1 downto 0);
rdaddressstall : in std_logic := '0';
byteena : in std_logic_vector(width_byteena-1 downto 0) := (others => '1');
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
aclr : in std_logic := '0';
q : out std_logic_vector(width-1 downto 0) );
end component;
component alt3pram
generic (
width : natural;
widthad : natural;
numwords : natural := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
indata_reg : string := "UNREGISTERED";
indata_aclr : string := "OFF";
write_reg : string := "UNREGISTERED";
write_aclr : string := "OFF";
rdaddress_reg_a : string := "UNREGISTERED";
rdaddress_aclr_a : string := "OFF";
rdaddress_reg_b : string := "UNREGISTERED";
rdaddress_aclr_b : string := "OFF";
rdcontrol_reg_a : string := "UNREGISTERED";
rdcontrol_aclr_a : string := "OFF";
rdcontrol_reg_b : string := "UNREGISTERED";
rdcontrol_aclr_b : string := "OFF";
outdata_reg_a : string := "UNREGISTERED";
outdata_aclr_a : string := "OFF";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "OFF";
intended_device_family : string := "APEX20KE";
ram_block_type : string := "AUTO";
maximum_depth : integer := 0;
lpm_type : string := "alt3pram" );
port (
wren : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
wraddress : in std_logic_vector(widthad-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
rdaddress_a : in std_logic_vector(widthad-1 downto 0);
rdaddress_b : in std_logic_vector(widthad-1 downto 0);
outclock : in std_logic := '0';
outclocken : in std_logic := '1';
aclr : in std_logic := '0';
qa : out std_logic_vector(width-1 downto 0);
qb : out std_logic_vector(width-1 downto 0) );
end component;
component altqpram
generic (
operation_mode : string := "QUAD_PORT";
width_write_a : natural := 1;
widthad_write_a : natural := 1;
numwords_write_a : natural := 0; -- default = 2^widthad_write_a
indata_reg_a : string := "INCLOCK_A";
indata_aclr_a : string := "INACLR_A";
wrcontrol_wraddress_reg_a : string := "INCLOCK_A";
wrcontrol_aclr_a : string := "INACLR_A";
wraddress_aclr_a : string := "INACLR_A";
width_write_b : natural := 1; -- default = width_write_a
widthad_write_b : natural := 1; -- default = widthad_write_a
numwords_write_b : natural := 0; -- default = 2^widthad_write_b
indata_reg_b : string := "INCLOCK_B";
indata_aclr_b : string := "INACLR_B";
wrcontrol_wraddress_reg_b : string := "INCLOCK_B";
wrcontrol_aclr_b : string := "INACLR_B";
wraddress_aclr_b : string := "INACLR_B";
width_read_a : natural := 1;
widthad_read_a : natural := 1;
numwords_read_a : natural := 0; -- default = 2^widthad_read_a
rdcontrol_reg_a : string := "OUTCLOCK_A";
rdcontrol_aclr_a : string := "OUTACLR_A";
rdaddress_reg_a : string := "OUTCLOCK_A";
rdaddress_aclr_a : string := "OUTACLR_A";
outdata_reg_a : string := "UNREGISTERED";
outdata_aclr_a : string := "OUTACLR_A";
width_read_b : natural := 1; -- default = width_read_a
widthad_read_b : natural := 1; -- default = widthad_read_a
numwords_read_b : natural := 0; -- default = 2^widthad_read_b
rdcontrol_reg_b : string := "OUTCLOCK_B";
rdcontrol_aclr_b : string := "OUTACLR_B";
rdaddress_reg_b : string := "OUTCLOCK_B";
rdaddress_aclr_b : string := "OUTACLR_B";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "OUTACLR_B";
init_file : string := "UNUSED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altqpram" );
port (
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
data_a : in std_logic_vector(width_write_a-1 downto 0) := (OTHERS => '0');
data_b : in std_logic_vector(width_write_b-1 downto 0) := (OTHERS => '0');
wraddress_a : in std_logic_vector(widthad_write_a-1 downto 0) := (OTHERS => '0');
wraddress_b : in std_logic_vector(widthad_write_b-1 downto 0) := (OTHERS => '0');
inclock_a : in std_logic := '0';
inclock_b : in std_logic := '0';
inclocken_a : in std_logic := '1';
inclocken_b : in std_logic := '1';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
rdaddress_a : in std_logic_vector(widthad_read_a-1 downto 0) := (OTHERS => '0');
rdaddress_b : in std_logic_vector(widthad_read_b-1 downto 0) := (OTHERS => '0');
outclock_a : in std_logic := '0';
outclock_b : in std_logic := '0';
outclocken_a : in std_logic := '1';
outclocken_b : in std_logic := '1';
inaclr_a : in std_logic := '0';
inaclr_b : in std_logic := '0';
outaclr_a : in std_logic := '0';
outaclr_b : in std_logic := '0';
q_a : out std_logic_vector(width_read_a-1 downto 0);
q_b : out std_logic_vector(width_read_b-1 downto 0) );
end component;
component scfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
intended_device_family : string := "NON_STRATIX";
almost_full_value : natural := 0;
almost_empty_value : natural := 0;
overflow_checking : string := "ON";
underflow_checking : string := "ON";
allow_rwcycle_when_full : string := "OFF";
add_ram_output_register : string := "OFF";
use_eab : string := "ON";
lpm_type : string := "scfifo";
maximum_depth : natural := 0 );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
sclr : in std_logic := '0';
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
almost_empty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
usedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component dcfifo_mixed_widths
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_width_r : natural := 0;
lpm_widthu_r : natural := 0;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 3;
wrsync_delaypipe : natural := 3;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo_mixed_widths";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width_r-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu_r-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component dcfifo
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_hint : string := "USE_EAB=ON";
overflow_checking : string := "ON";
underflow_checking : string := "ON";
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 3;
wrsync_delaypipe : natural := 3;
use_eab : string := "ON";
add_ram_output_register : string := "OFF";
add_width : natural := 1;
clocks_are_synchronized : string := "FALSE";
ram_block_type : string := "AUTO";
add_usedw_msb_bit : string := "OFF";
write_aclr_synch : string := "OFF";
lpm_type : string := "dcfifo";
intended_device_family : string := "NON_STRATIX" );
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
rdfull : out std_logic;
wrfull : out std_logic;
wrempty : out std_logic;
rdempty : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
end component;
component altddio_in
generic (
width : positive; -- required parameter
invert_input_clocks : string := "OFF";
intended_device_family : string := "MERCURY";
power_up_high : string := "OFF";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_in" );
port (
datain : in std_logic_vector(width-1 downto 0);
inclock : in std_logic;
inclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0) );
end component;
component altddio_out
generic (
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_out" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout : out std_logic_vector(width-1 downto 0);
oe_out : out std_logic_vector(width-1 downto 0) );
end component;
component altddio_bidir
generic(
width : positive; -- required parameter
power_up_high : string := "OFF";
oe_reg : string := "UNUSED";
extend_oe_disable : string := "UNUSED";
implement_input_in_lcell : string := "UNUSED";
invert_output : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altddio_bidir" );
port (
datain_h : in std_logic_vector(width-1 downto 0);
datain_l : in std_logic_vector(width-1 downto 0);
inclock : in std_logic := '0';
inclocken : in std_logic := '1';
outclock : in std_logic;
outclocken : in std_logic := '1';
aset : in std_logic := '0';
aclr : in std_logic := '0';
sset : in std_logic := '0';
sclr : in std_logic := '0';
oe : in std_logic := '1';
dataout_h : out std_logic_vector(width-1 downto 0);
dataout_l : out std_logic_vector(width-1 downto 0);
combout : out std_logic_vector(width-1 downto 0);
oe_out : out std_logic_vector(width-1 downto 0);
dqsundelayedout : out std_logic_vector(width-1 downto 0);
padio : inout std_logic_vector(width-1 downto 0) );
end component;
component altcdr_rx
generic (
number_of_channels : positive := 1;
deserialization_factor : positive := 1;
inclock_period : positive;
inclock_boost : positive := 1;
run_length : integer := 62;
bypass_fifo : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altcdr_rx" );
port (
rx_in : in std_logic_vector(number_of_channels-1 downto 0);
rx_inclock : in std_logic;
rx_coreclock : in std_logic;
rx_aclr : in std_logic := '0';
rx_pll_aclr : in std_logic := '0';
rx_fifo_rden : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
rx_out : out std_logic_vector(deserialization_factor*number_of_channels-1 downto 0);
rx_outclock : out std_logic;
rx_pll_locked: out std_logic;
rx_locklost : out std_logic_vector(number_of_channels-1 downto 0);
rx_rlv : out std_logic_vector(number_of_channels-1 downto 0);
rx_full : out std_logic_vector(number_of_channels-1 downto 0);
rx_empty : out std_logic_vector(number_of_channels-1 downto 0);
rx_rec_clk : out std_logic_vector(number_of_channels-1 downto 0) );
end component;
component altcdr_tx
generic (
number_of_channels : positive := 1;
deserialization_factor : positive := 1;
inclock_period : positive; -- required parameter
inclock_boost : positive := 1;
bypass_fifo : string := "OFF";
intended_device_family : string := "MERCURY";
lpm_hint : string := "UNUSED";
lpm_type : string := "altcdr_tx" );
port (
tx_in : in std_logic_vector(deserialization_factor*number_of_channels-1 downto 0);
tx_inclock : in std_logic;
tx_coreclock : in std_logic;
tx_aclr : in std_logic := '0';
tx_pll_aclr : in std_logic := '0';
tx_fifo_wren : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
tx_out : out std_logic_vector(number_of_channels-1 downto 0);
tx_outclock : out std_logic;
tx_pll_locked: out std_logic;
tx_empty : out std_logic_vector(number_of_channels-1 downto 0);
tx_full : out std_logic_vector(number_of_channels-1 downto 0) );
end component;
component altshift_taps
generic (
number_of_taps : integer := 4;
tap_distance : integer := 3;
width : integer := 8;
power_up_state : string := "CLEARED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altshift_taps" );
port (
shiftin : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
clken : in std_logic := '1';
shiftout : out std_logic_vector (width-1 downto 0);
taps : out std_logic_vector ((width*number_of_taps)-1 downto 0));
end component;
component altmult_add
generic (
WIDTH_A : integer := 1;
WIDTH_B : integer := 1;
WIDTH_RESULT : integer := 1;
NUMBER_OF_MULTIPLIERS : integer := 1;
-- A inputs
INPUT_REGISTER_A0 : string := "CLOCK0";
INPUT_ACLR_A0 : string := "ACLR3";
INPUT_SOURCE_A0 : string := "DATAA";
INPUT_REGISTER_A1 : string := "CLOCK0";
INPUT_ACLR_A1 : string := "ACLR3";
INPUT_SOURCE_A1 : string := "DATAA";
INPUT_REGISTER_A2 : string := "CLOCK0";
INPUT_ACLR_A2 : string := "ACLR3";
INPUT_SOURCE_A2 : string := "DATAA";
INPUT_REGISTER_A3 : string := "CLOCK0";
INPUT_ACLR_A3 : string := "ACLR3";
INPUT_SOURCE_A3 : string := "DATAA";
PORT_SIGNA : string := "PORT_CONNECTIVITY";
REPRESENTATION_A : string := "UNSIGNED";
SIGNED_REGISTER_A : string := "CLOCK0";
SIGNED_ACLR_A : string := "ACLR3";
SIGNED_PIPELINE_REGISTER_A : string := "CLOCK0";
SIGNED_PIPELINE_ACLR_A : string := "ACLR3";
-- B inputs
INPUT_REGISTER_B0 : string := "CLOCK0";
INPUT_ACLR_B0 : string := "ACLR3";
INPUT_SOURCE_B0 : string := "DATAB";
INPUT_REGISTER_B1 : string := "CLOCK0";
INPUT_ACLR_B1 : string := "ACLR3";
INPUT_SOURCE_B1 : string := "DATAB";
INPUT_REGISTER_B2 : string := "CLOCK0";
INPUT_ACLR_B2 : string := "ACLR3";
INPUT_SOURCE_B2 : string := "DATAB";
INPUT_REGISTER_B3 : string := "CLOCK0";
INPUT_ACLR_B3 : string := "ACLR3";
INPUT_SOURCE_B3 : string := "DATAB";
PORT_SIGNB : string := "PORT_CONNECTIVITY";
REPRESENTATION_B : string := "UNSIGNED";
SIGNED_REGISTER_B : string := "CLOCK0";
SIGNED_ACLR_B : string := "ACLR3";
SIGNED_PIPELINE_REGISTER_B : string := "CLOCK0";
SIGNED_PIPELINE_ACLR_B : string := "ACLR3";
MULTIPLIER_REGISTER0 : string := "CLOCK0";
MULTIPLIER_ACLR0 : string := "ACLR3";
MULTIPLIER_REGISTER1 : string := "CLOCK0";
MULTIPLIER_ACLR1 : string := "ACLR3";
MULTIPLIER_REGISTER2 : string := "CLOCK0";
MULTIPLIER_ACLR2 : string := "ACLR3";
MULTIPLIER_REGISTER3 : string := "CLOCK0";
MULTIPLIER_ACLR3 : string := "ACLR3";
PORT_ADDNSUB1 : string := "PORT_CONNECTIVITY";
ADDNSUB_MULTIPLIER_REGISTER1 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_ACLR1 : string := "ACLR3";
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 : string := "ACLR3";
PORT_ADDNSUB3 : string := "PORT_CONNECTIVITY";
ADDNSUB_MULTIPLIER_REGISTER3 : string := "CLOCK0";
ADDNSUB_MULTIPLIER_ACLR3 : string := "ACLR3";
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3: string := "CLOCK0";
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 : string := "ACLR3";
ADDNSUB1_ROUND_ACLR : string := "ACLR3";
ADDNSUB1_ROUND_PIPELINE_ACLR : string := "ACLR3";
ADDNSUB1_ROUND_REGISTER : string := "CLOCK0";
ADDNSUB1_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
ADDNSUB3_ROUND_ACLR : string := "ACLR3";
ADDNSUB3_ROUND_PIPELINE_ACLR : string := "ACLR3";
ADDNSUB3_ROUND_REGISTER : string := "CLOCK0";
ADDNSUB3_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
MULT01_ROUND_ACLR : string := "ACLR3";
MULT01_ROUND_REGISTER : string := "CLOCK0";
MULT01_SATURATION_REGISTER : string := "CLOCK0";
MULT01_SATURATION_ACLR : string := "ACLR3";
MULT23_ROUND_REGISTER : string := "CLOCK0";
MULT23_ROUND_ACLR : string := "ACLR3";
MULT23_SATURATION_REGISTER : string := "CLOCK0";
MULT23_SATURATION_ACLR : string := "ACLR3";
multiplier1_direction : string := "ADD";
multiplier3_direction : string := "ADD";
OUTPUT_REGISTER : string := "CLOCK0";
OUTPUT_ACLR : string := "ACLR0";
-- StratixII parameters
multiplier01_rounding : string := "NO";
multiplier01_saturation : string := "NO";
multiplier23_rounding : string := "NO";
multiplier23_saturation : string := "NO";
adder1_rounding : string := "NO";
adder3_rounding : string := "NO";
port_mult0_is_saturated : string := "UNUSED";
port_mult1_is_saturated : string := "UNUSED";
port_mult2_is_saturated : string := "UNUSED";
port_mult3_is_saturated : string := "UNUSED";
-- Stratix III parameters
scanouta_register : string := "UNREGISTERED";
scanouta_aclr : string := "NONE";
-- Rounding parameters
output_rounding : string := "NO";
output_round_type : string := "NEAREST_INTEGER";
width_msb : integer := 17;
output_round_register : string := "UNREGISTERED";
output_round_aclr : string := "NONE";
output_round_pipeline_register : string := "UNREGISTERED";
output_round_pipeline_aclr : string := "NONE";
chainout_rounding : string := "NO";
chainout_round_register : string := "UNREGISTERED";
chainout_round_aclr : string := "NONE";
chainout_round_pipeline_register : string := "UNREGISTERED";
chainout_round_pipeline_aclr : string := "NONE";
chainout_round_output_register : string := "UNREGISTERED";
chainout_round_output_aclr : string := "NONE";
-- saturation parameters
port_output_is_overflow : string := "PORT_UNUSED";
port_chainout_sat_is_overflow : string := "PORT_UNUSED";
output_saturation : string := "NO";
output_saturate_type : string := "ASYMMETRIC";
width_saturate_sign : integer := 1;
output_saturate_register : string := "UNREGISTERED";
output_saturate_aclr : string := "NONE";
output_saturate_pipeline_register : string := "UNREGISTERED";
output_saturate_pipeline_aclr : string := "NONE";
chainout_saturation : string := "NO";
chainout_saturate_register : string := "UNREGISTERED";
chainout_saturate_aclr : string := "NONE";
chainout_saturate_pipeline_register : string := "UNREGISTERED";
chainout_saturate_pipeline_aclr : string := "NONE";
chainout_saturate_output_register : string := "UNREGISTERED";
chainout_saturate_output_aclr : string := "NONE";
-- chainout parameters
chainout_adder : string := "NO";
chainout_register : string := "UNREGISTERED";
chainout_aclr : string := "NONE";
width_chainin : integer := 1;
zero_chainout_output_register : string := "UNREGISTERED";
zero_chainout_output_aclr : string := "NONE";
-- rotate & shift parameters
shift_mode : string := "NO";
rotate_aclr : string := "NONE";
rotate_register : string := "UNREGISTERED";
rotate_pipeline_register : string := "UNREGISTERED";
rotate_pipeline_aclr : string := "NONE";
rotate_output_register : string := "UNREGISTERED";
rotate_output_aclr : string := "NONE";
shift_right_register : string := "UNREGISTERED";
shift_right_aclr : string := "NONE";
shift_right_pipeline_register : string := "UNREGISTERED";
shift_right_pipeline_aclr : string := "NONE";
shift_right_output_register : string := "UNREGISTERED";
shift_right_output_aclr : string := "NONE";
-- loopback parameters
zero_loopback_register : string := "UNREGISTERED";
zero_loopback_aclr : string := "NONE";
zero_loopback_pipeline_register : string := "UNREGISTERED";
zero_loopback_pipeline_aclr : string := "NONE";
zero_loopback_output_register : string := "UNREGISTERED";
zero_loopback_output_aclr : string := "NONE";
-- accumulator parameters
accum_sload_register : string := "UNREGISTERED";
accum_sload_aclr : string := "NONE";
accum_sload_pipeline_register : string := "UNREGISTERED";
accum_sload_pipeline_aclr : string := "NONE";
accum_direction : string := "ADD";
accumulator : string := "NO";
EXTRA_LATENCY : integer :=0;
DEDICATED_MULTIPLIER_CIRCUITRY:string := "AUTO";
DSP_BLOCK_BALANCING : string := "AUTO";
lpm_hint : string := "UNUSED";
lpm_type : string := "altmult_add";
intended_device_family : string := "Stratix" );
port (
dataa : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_A -1 downto 0);
datab : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_B -1 downto 0);
scanina : in std_logic_vector(width_a -1 downto 0) := (others => '0');
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => '0');
sourcea : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
sourceb : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
-- clock ports
clock3 : in std_logic := '1';
clock2 : in std_logic := '1';
clock1 : in std_logic := '1';
clock0 : in std_logic := '1';
aclr3 : in std_logic := '0';
aclr2 : in std_logic := '0';
aclr1 : in std_logic := '0';
aclr0 : in std_logic := '0';
ena3 : in std_logic := '1';
ena2 : in std_logic := '1';
ena1 : in std_logic := '1';
ena0 : in std_logic := '1';
-- control signals
signa : in std_logic := 'Z';
signb : in std_logic := 'Z';
addnsub1 : in std_logic := 'Z';
addnsub3 : in std_logic := 'Z';
-- StratixII only input ports
mult01_round : in std_logic := '0';
mult23_round : in std_logic := '0';
mult01_saturation : in std_logic := '0';
mult23_saturation : in std_logic := '0';
addnsub1_round : in std_logic := '0';
addnsub3_round : in std_logic := '0';
-- Stratix III only input ports
output_round : in std_logic := '0';
chainout_round : in std_logic := '0';
output_saturate : in std_logic := '0';
chainout_saturate : in std_logic := '0';
chainin : in std_logic_vector (width_chainin - 1 downto 0) := (others => '0');
zero_chainout : in std_logic := '0';
rotate : in std_logic := '0';
shift_right : in std_logic := '0';
zero_loopback : in std_logic := '0';
accum_sload : in std_logic := '0';
-- output ports
result : out std_logic_vector(WIDTH_RESULT -1 downto 0);
scanouta : out std_logic_vector (WIDTH_A -1 downto 0);
scanoutb : out std_logic_vector (WIDTH_B -1 downto 0);
-- StratixII only output ports
mult0_is_saturated : out std_logic := '0';
mult1_is_saturated : out std_logic := '0';
mult2_is_saturated : out std_logic := '0';
mult3_is_saturated : out std_logic := '0';
-- Stratix III only output ports
overflow : out std_logic := '0';
chainout_sat_overflow : out std_logic := '0');
end component;
component altmult_accum
generic (
width_a : integer := 1;
width_b : integer := 1;
width_result : integer := 2;
width_upper_data : integer := 1;
input_source_a : string := "DATAA";
input_source_b : string := "DATAB";
input_reg_a : string := "CLOCK0";
input_aclr_a : string := "ACLR3";
input_reg_b : string := "CLOCK0";
input_aclr_b : string := "ACLR3";
port_addnsub : string := "PORT_CONNECTIVITY";
addnsub_reg : string := "CLOCK0";
addnsub_aclr : string := "ACLR3";
addnsub_pipeline_reg : string := "CLOCK0";
addnsub_pipeline_aclr : string := "ACLR3";
accum_direction : string := "ADD";
accum_sload_reg : string := "CLOCK0";
accum_sload_aclr : string := "ACLR3";
accum_sload_pipeline_reg : string := "CLOCK0";
accum_sload_pipeline_aclr : string := "ACLR3";
representation_a : string := "UNSIGNED";
port_signa : string := "PORT_CONNECTIVITY";
sign_reg_a : string := "CLOCK0";
sign_aclr_a : string := "ACLR3";
sign_pipeline_reg_a : string := "CLOCK0";
sign_pipeline_aclr_a : string := "ACLR3";
representation_b : string := "UNSIGNED";
port_signb : string := "PORT_CONNECTIVITY";
sign_reg_b : string := "CLOCK0";
sign_aclr_b : string := "ACLR3";
sign_pipeline_reg_b : string := "CLOCK0";
sign_pipeline_aclr_b : string := "ACLR3";
multiplier_reg : string := "CLOCK0";
multiplier_aclr : string := "ACLR3";
output_reg : string := "CLOCK0";
output_aclr : string := "ACLR0";
extra_multiplier_latency : integer := 0;
extra_accumulator_latency : integer := 0;
dedicated_multiplier_circuitry : string := "AUTO";
dsp_block_balancing : string := "AUTO";
lpm_hint : string := "UNUSED";
lpm_type : string := "altmult_accum";
intended_device_family : string := "Stratix";
multiplier_rounding : string := "NO";
multiplier_saturation : string := "NO";
accumulator_rounding : string := "NO";
accumulator_saturation : string := "NO";
port_mult_is_saturated : string := "UNUSED";
port_accum_is_saturated : string := "UNUSED";
mult_round_aclr : string := "ACLR3";
mult_round_reg : string := "CLOCK0";
mult_saturation_aclr : string := "ACLR3";
mult_saturation_reg : string := "CLOCK0";
accum_round_aclr : string := "ACLR3";
accum_round_reg : string := "CLOCK3";
accum_round_pipeline_aclr : string := "ACLR3";
accum_round_pipeline_reg : string := "CLOCK0";
accum_saturation_aclr : string := "ACLR3";
accum_saturation_reg : string := "CLOCK0";
accum_saturation_pipeline_aclr : string := "ACLR3";
accum_saturation_pipeline_reg : string := "CLOCK0";
accum_sload_upper_data_aclr : string := "ACLR3";
accum_sload_upper_data_pipeline_aclr : string := "ACLR3";
accum_sload_upper_data_pipeline_reg : string := "CLOCK0";
accum_sload_upper_data_reg : string := "CLOCK0" );
port (
dataa : in std_logic_vector(width_a -1 downto 0);
datab : in std_logic_vector(width_b -1 downto 0);
scanina : in std_logic_vector(width_a -1 downto 0) := (others => 'Z');
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => 'Z');
accum_sload_upper_data : in std_logic_vector(width_result -1 downto width_result - width_upper_data) := (others => '0');
sourcea : in std_logic := '1';
sourceb : in std_logic := '1';
-- control signals
addnsub : in std_logic := 'Z';
accum_sload : in std_logic := '0';
signa : in std_logic := 'Z';
signb : in std_logic := 'Z';
-- clock ports
clock0 : in std_logic := '1';
clock1 : in std_logic := '1';
clock2 : in std_logic := '1';
clock3 : in std_logic := '1';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
aclr2 : in std_logic := '0';
aclr3 : in std_logic := '0';
-- round and saturation ports
mult_round : in std_logic := '0';
mult_saturation : in std_logic := '0';
accum_round : in std_logic := '0';
accum_saturation : in std_logic := '0';
-- output ports
result : out std_logic_vector(width_result -1 downto 0);
overflow : out std_logic;
scanouta : out std_logic_vector (width_a -1 downto 0);
scanoutb : out std_logic_vector (width_b -1 downto 0);
mult_is_saturated : out std_logic := '0';
accum_is_saturated : out std_logic := '0' );
end component;
component altaccumulate
generic (
width_in : integer:= 4;
width_out : integer:= 8;
lpm_representation : string := "UNSIGNED";
extra_latency : integer:= 0;
use_wys : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "altaccumulate" );
port (
-- Input ports
cin : in std_logic := 'Z';
data : in std_logic_vector(width_in -1 downto 0); -- Required port
add_sub : in std_logic := '1';
clock : in std_logic; -- Required port
sload : in std_logic := '0';
clken : in std_logic := '1';
sign_data : in std_logic := '0';
aclr : in std_logic := '0';
-- Output ports
result : out std_logic_vector(width_out -1 downto 0) := (others => '0');
cout : out std_logic := '0';
overflow : out std_logic := '0' );
end component;
component altsyncram
generic (
operation_mode : string := "BIDIR_DUAL_PORT";
-- port a parameters
width_a : integer := 1;
widthad_a : integer := 1;
numwords_a : integer := 0;
-- registering parameters
-- port a read parameters
outdata_reg_a : string := "UNREGISTERED";
-- clearing parameters
address_aclr_a : string := "NONE";
outdata_aclr_a : string := "NONE";
-- clearing parameters
-- port a write parameters
indata_aclr_a : string := "NONE";
wrcontrol_aclr_a : string := "NONE";
-- clear for the byte enable port reigsters which are clocked by clk0
byteena_aclr_a : string := "NONE";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_a : integer := 1;
-- port b parameters
width_b : integer := 1;
widthad_b : integer := 1;
numwords_b : integer := 0;
-- registering parameters
-- port b read parameters
rdcontrol_reg_b : string := "CLOCK1";
address_reg_b : string := "CLOCK1";
outdata_reg_b : string := "UNREGISTERED";
-- clearing parameters
outdata_aclr_b : string := "NONE";
rdcontrol_aclr_b : string := "NONE";
-- registering parameters
-- port b write parameters
indata_reg_b : string := "CLOCK1";
wrcontrol_wraddress_reg_b : string := "CLOCK1";
-- registering parameter for the byte enable reister for port b
byteena_reg_b : string := "CLOCK1";
-- clearing parameters
indata_aclr_b : string := "NONE";
wrcontrol_aclr_b : string := "NONE";
address_aclr_b : string := "NONE";
-- clear parameter for byte enable port register
byteena_aclr_b : string := "NONE";
-- StratixII only : to bypass clock enable or using clock enable
clock_enable_input_a : string := "NORMAL";
clock_enable_output_a : string := "NORMAL";
clock_enable_input_b : string := "NORMAL";
clock_enable_output_b : string := "NORMAL";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_b : integer := 1;
-- clock enable setting for the core
clock_enable_core_a : string := "USE_INPUT_CLKEN";
clock_enable_core_b : string := "USE_INPUT_CLKEN";
-- read-during-write-same-port setting
read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ";
-- ECC status ports setting
enable_ecc : string := "FALSE";
-- global parameters
-- width of a byte for byte enables
byte_size : integer := 0;
read_during_write_mode_mixed_ports: string := "DONT_CARE";
-- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM"
ram_block_type : string := "AUTO";
-- determine whether LE support is turned on or off for altsyncram
implement_in_les : string := "OFF";
-- determine whether RAM would be power up to uninitialized or not
power_up_uninitialized : string := "FALSE";
-- general operation parameters
init_file : string := "UNUSED";
init_file_layout : string := "UNUSED";
maximum_depth : integer := 0;
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altsyncram" );
port (
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
data_a : in std_logic_vector(width_a - 1 downto 0):= (others => '1');
data_b : in std_logic_vector(width_b - 1 downto 0):= (others => '1');
address_a : in std_logic_vector(widthad_a - 1 downto 0);
address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1');
clock0 : in std_logic := '1';
clock1 : in std_logic := '1';
clocken0 : in std_logic := '1';
clocken1 : in std_logic := '1';
clocken2 : in std_logic := '1';
clocken3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1');
byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => '1');
addressstall_a : in std_logic := '0';
addressstall_b : in std_logic := '0';
q_a : out std_logic_vector(width_a - 1 downto 0);
q_b : out std_logic_vector(width_b - 1 downto 0);
eccstatus : out std_logic_vector(2 downto 0) );
end component;
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
pll_type : string := "AUTO" ;
qualify_conf_done : string := "OFF" ;
compensate_clock : string := "CLK0" ;
scan_chain : string := "LONG";
primary_clock : string := "inclk0" ;
inclk0_input_frequency : natural; -- required parameter
inclk1_input_frequency : natural := 0;
gate_lock_signal : string := "NO";
gate_lock_counter : integer := 0;
lock_high : natural := 1;
lock_low : natural := 5;
valid_lock_multiplier : natural := 1;
invalid_lock_multiplier : natural := 5;
switch_over_type : string := "AUTO";
switch_over_on_lossclk : string := "OFF" ;
switch_over_on_gated_lock : string := "OFF" ;
enable_switch_over_counter : string := "OFF";
switch_over_counter : natural := 0;
feedback_source : string := "EXTCLK0" ;
bandwidth : natural := 0;
bandwidth_type : string := "UNUSED";
spread_frequency : natural := 0;
down_spread : string := "0.0";
self_reset_on_gated_loss_lock : string := "OFF";
self_reset_on_loss_lock : string := "OFF";
self_reset_on_loss_clock : string := "OFF";
lock_window_ui : string := "0.05";
width_clock : natural := 6;
width_phasecounterselect : natural := 4;
charge_pump_current_bits : natural := 9999;
loop_filter_c_bits : natural := 9999;
loop_filter_r_bits : natural := 9999;
-- simulation-only parameters
simulation_type : string := "functional";
source_is_pll : string := "off";
skip_vco : string := "off";
-- internal clock specifications
clk9_multiply_by : natural := 1;
clk8_multiply_by : natural := 1;
clk7_multiply_by : natural := 1;
clk6_multiply_by : natural := 1;
clk5_multiply_by : natural := 1;
clk4_multiply_by : natural := 1;
clk3_multiply_by : natural := 1;
clk2_multiply_by : natural := 1;
clk1_multiply_by : natural := 1;
clk0_multiply_by : natural := 1;
clk9_divide_by : natural := 1;
clk8_divide_by : natural := 1;
clk7_divide_by : natural := 1;
clk6_divide_by : natural := 1;
clk5_divide_by : natural := 1;
clk4_divide_by : natural := 1;
clk3_divide_by : natural := 1;
clk2_divide_by : natural := 1;
clk1_divide_by : natural := 1;
clk0_divide_by : natural := 1;
clk9_phase_shift : string := "0";
clk8_phase_shift : string := "0";
clk7_phase_shift : string := "0";
clk6_phase_shift : string := "0";
clk5_phase_shift : string := "0";
clk4_phase_shift : string := "0";
clk3_phase_shift : string := "0";
clk2_phase_shift : string := "0";
clk1_phase_shift : string := "0";
clk0_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk4_time_delay : string := "0";
clk3_time_delay : string := "0";
clk2_time_delay : string := "0";
clk1_time_delay : string := "0";
clk0_time_delay : string := "0";
clk9_duty_cycle : natural := 50;
clk8_duty_cycle : natural := 50;
clk7_duty_cycle : natural := 50;
clk6_duty_cycle : natural := 50;
clk5_duty_cycle : natural := 50;
clk4_duty_cycle : natural := 50;
clk3_duty_cycle : natural := 50;
clk2_duty_cycle : natural := 50;
clk1_duty_cycle : natural := 50;
clk0_duty_cycle : natural := 50;
clk2_output_frequency : natural := 0;
clk1_output_frequency : natural := 0;
clk0_output_frequency : natural := 0;
clk9_use_even_counter_mode : string := "OFF";
clk8_use_even_counter_mode : string := "OFF";
clk7_use_even_counter_mode : string := "OFF";
clk6_use_even_counter_mode : string := "OFF";
clk5_use_even_counter_mode : string := "OFF";
clk4_use_even_counter_mode : string := "OFF";
clk3_use_even_counter_mode : string := "OFF";
clk2_use_even_counter_mode : string := "OFF";
clk1_use_even_counter_mode : string := "OFF";
clk0_use_even_counter_mode : string := "OFF";
clk9_use_even_counter_value : string := "OFF";
clk8_use_even_counter_value : string := "OFF";
clk7_use_even_counter_value : string := "OFF";
clk6_use_even_counter_value : string := "OFF";
clk5_use_even_counter_value : string := "OFF";
clk4_use_even_counter_value : string := "OFF";
clk3_use_even_counter_value : string := "OFF";
clk2_use_even_counter_value : string := "OFF";
clk1_use_even_counter_value : string := "OFF";
clk0_use_even_counter_value : string := "OFF";
-- external clock specifications
extclk3_multiply_by : natural := 1;
extclk2_multiply_by : natural := 1;
extclk1_multiply_by : natural := 1;
extclk0_multiply_by : natural := 1;
extclk3_divide_by : natural := 1;
extclk2_divide_by : natural := 1;
extclk1_divide_by : natural := 1;
extclk0_divide_by : natural := 1;
extclk3_phase_shift : string := "0";
extclk2_phase_shift : string := "0";
extclk1_phase_shift : string := "0";
extclk0_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk2_time_delay : string := "0";
extclk1_time_delay : string := "0";
extclk0_time_delay : string := "0";
extclk3_duty_cycle : natural := 50;
extclk2_duty_cycle : natural := 50;
extclk1_duty_cycle : natural := 50;
extclk0_duty_cycle : natural := 50;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
-- advanced user parameters
vco_min : natural := 0;
vco_max : natural := 0;
vco_center : natural := 0;
pfd_min : natural := 0;
pfd_max : natural := 0;
m_initial : natural := 1;
m : natural := 0; -- m must default to 0 to force altpll to calculate the internal parameters for itself
n : natural := 1;
m2 : natural := 1;
n2 : natural := 1;
ss : natural := 0;
c0_high : natural := 1;
c1_high : natural := 1;
c2_high : natural := 1;
c3_high : natural := 1;
c4_high : natural := 1;
c5_high : natural := 1;
c6_high : natural := 1;
c7_high : natural := 1;
c8_high : natural := 1;
c9_high : natural := 1;
l0_high : natural := 1;
l1_high : natural := 1;
g0_high : natural := 1;
g1_high : natural := 1;
g2_high : natural := 1;
g3_high : natural := 1;
e0_high : natural := 1;
e1_high : natural := 1;
e2_high : natural := 1;
e3_high : natural := 1;
c0_low : natural := 1;
c1_low : natural := 1;
c2_low : natural := 1;
c3_low : natural := 1;
c4_low : natural := 1;
c5_low : natural := 1;
c6_low : natural := 1;
c7_low : natural := 1;
c8_low : natural := 1;
c9_low : natural := 1;
l0_low : natural := 1;
l1_low : natural := 1;
g0_low : natural := 1;
g1_low : natural := 1;
g2_low : natural := 1;
g3_low : natural := 1;
e0_low : natural := 1;
e1_low : natural := 1;
e2_low : natural := 1;
e3_low : natural := 1;
c0_initial : natural := 1;
c1_initial : natural := 1;
c2_initial : natural := 1;
c3_initial : natural := 1;
c4_initial : natural := 1;
c5_initial : natural := 1;
c6_initial : natural := 1;
c7_initial : natural := 1;
c8_initial : natural := 1;
c9_initial : natural := 1;
l0_initial : natural := 1;
l1_initial : natural := 1;
g0_initial : natural := 1;
g1_initial : natural := 1;
g2_initial : natural := 1;
g3_initial : natural := 1;
e0_initial : natural := 1;
e1_initial : natural := 1;
e2_initial : natural := 1;
e3_initial : natural := 1;
c0_mode : string := "bypass" ;
c1_mode : string := "bypass" ;
c2_mode : string := "bypass" ;
c3_mode : string := "bypass" ;
c4_mode : string := "bypass" ;
c5_mode : string := "bypass" ;
c6_mode : string := "bypass" ;
c7_mode : string := "bypass" ;
c8_mode : string := "bypass" ;
c9_mode : string := "bypass" ;
l0_mode : string := "bypass" ;
l1_mode : string := "bypass" ;
g0_mode : string := "bypass" ;
g1_mode : string := "bypass" ;
g2_mode : string := "bypass" ;
g3_mode : string := "bypass" ;
e0_mode : string := "bypass" ;
e1_mode : string := "bypass" ;
e2_mode : string := "bypass" ;
e3_mode : string := "bypass" ;
c0_ph : natural := 0;
c1_ph : natural := 0;
c2_ph : natural := 0;
c3_ph : natural := 0;
c4_ph : natural := 0;
c5_ph : natural := 0;
c6_ph : natural := 0;
c7_ph : natural := 0;
c8_ph : natural := 0;
c9_ph : natural := 0;
l0_ph : natural := 0;
l1_ph : natural := 0;
g0_ph : natural := 0;
g1_ph : natural := 0;
g2_ph : natural := 0;
g3_ph : natural := 0;
e0_ph : natural := 0;
e1_ph : natural := 0;
e2_ph : natural := 0;
e3_ph : natural := 0;
m_ph : natural := 0;
l0_time_delay : natural := 0;
l1_time_delay : natural := 0;
g0_time_delay : natural := 0;
g1_time_delay : natural := 0;
g2_time_delay : natural := 0;
g3_time_delay : natural := 0;
e0_time_delay : natural := 0;
e1_time_delay : natural := 0;
e2_time_delay : natural := 0;
e3_time_delay : natural := 0;
m_time_delay : natural := 0;
n_time_delay : natural := 0;
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
c6_test_source : integer := 5;
c7_test_source : integer := 5;
c8_test_source : integer := 5;
c9_test_source : integer := 5;
extclk3_counter : string := "e3" ;
extclk2_counter : string := "e2" ;
extclk1_counter : string := "e1" ;
extclk0_counter : string := "e0" ;
clk9_counter : string := "c9" ;
clk8_counter : string := "c8" ;
clk7_counter : string := "c7" ;
clk6_counter : string := "c6" ;
clk5_counter : string := "l1" ;
clk4_counter : string := "l0" ;
clk3_counter : string := "g3" ;
clk2_counter : string := "g2" ;
clk1_counter : string := "g1" ;
clk0_counter : string := "g0" ;
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : natural := 2;
loop_filter_r : string := " 1.000000";
loop_filter_c : natural := 5;
vco_post_scale : natural := 0;
vco_frequency_control : string := "AUTO";
vco_phase_shift_step : natural := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altpll";
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY";
port_clkena6 : string := "PORT_CONNECTIVITY";
port_clkena7 : string := "PORT_CONNECTIVITY";
port_clkena8 : string := "PORT_CONNECTIVITY";
port_clkena9 : string := "PORT_CONNECTIVITY";
port_extclkena0 : string := "PORT_CONNECTIVITY";
port_extclkena1 : string := "PORT_CONNECTIVITY";
port_extclkena2 : string := "PORT_CONNECTIVITY";
port_extclkena3 : string := "PORT_CONNECTIVITY";
port_extclk0 : string := "PORT_CONNECTIVITY";
port_extclk1 : string := "PORT_CONNECTIVITY";
port_extclk2 : string := "PORT_CONNECTIVITY";
port_extclk3 : string := "PORT_CONNECTIVITY";
port_clkbad0 : string := "PORT_CONNECTIVITY";
port_clkbad1 : string := "PORT_CONNECTIVITY";
port_clk0 : string := "PORT_CONNECTIVITY";
port_clk1 : string := "PORT_CONNECTIVITY";
port_clk2 : string := "PORT_CONNECTIVITY";
port_clk3 : string := "PORT_CONNECTIVITY";
port_clk4 : string := "PORT_CONNECTIVITY";
port_clk5 : string := "PORT_CONNECTIVITY";
port_clk6 : string := "PORT_CONNECTIVITY";
port_clk7 : string := "PORT_CONNECTIVITY";
port_clk8 : string := "PORT_CONNECTIVITY";
port_clk9 : string := "PORT_CONNECTIVITY";
port_scandata : string := "PORT_CONNECTIVITY";
port_scandataout : string := "PORT_CONNECTIVITY";
port_scandone : string := "PORT_CONNECTIVITY";
port_sclkout1 : string := "PORT_CONNECTIVITY";
port_sclkout0 : string := "PORT_CONNECTIVITY";
port_activeclock : string := "PORT_CONNECTIVITY";
port_clkloss : string := "PORT_CONNECTIVITY";
port_inclk1 : string := "PORT_CONNECTIVITY";
port_inclk0 : string := "PORT_CONNECTIVITY";
port_fbin : string := "PORT_CONNECTIVITY";
port_fbout : string := "PORT_CONNECTIVITY";
port_pllena : string := "PORT_CONNECTIVITY";
port_clkswitch : string := "PORT_CONNECTIVITY";
port_areset : string := "PORT_CONNECTIVITY";
port_pfdena : string := "PORT_CONNECTIVITY";
port_scanclk : string := "PORT_CONNECTIVITY";
port_scanaclr : string := "PORT_CONNECTIVITY";
port_scanread : string := "PORT_CONNECTIVITY";
port_scanwrite : string := "PORT_CONNECTIVITY";
port_enable0 : string := "PORT_CONNECTIVITY";
port_enable1 : string := "PORT_CONNECTIVITY";
port_locked : string := "PORT_CONNECTIVITY";
port_configupdate : string := "PORT_CONNECTIVITY";
port_phasecounterselect : string := "PORT_CONNECTIVITY";
port_phasedone : string := "PORT_CONNECTIVITY";
port_phasestep : string := "PORT_CONNECTIVITY";
port_phaseupdown : string := "PORT_CONNECTIVITY";
port_vcooverrange : string := "PORT_CONNECTIVITY";
port_vcounderrange : string := "PORT_CONNECTIVITY";
port_scanclkena : string := "PORT_CONNECTIVITY";
using_fbmimicbidir_port : string := "ON";
sim_gate_lock_device_behavior : string := "OFF" );
port (
inclk : in std_logic_vector(1 downto 0) := (others => '0');
fbin : in std_logic := '1';
pllena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := (others => '1');
extclkena : in std_logic_vector(3 downto 0) := (others => '1');
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
scanaclr : in std_logic := '0';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
phasecounterselect : in std_logic_vector(width_phasecounterselect-1 downto 0) := (others => '1');
phaseupdown : in std_logic := '1';
phasestep : in std_logic := '1';
configupdate : in std_logic := '0';
fbmimicbidir : inout std_logic := '1';
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
enable0 : out std_logic;
enable1 : out std_logic;
activeclock : out std_logic;
clkloss : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
sclkout0 : out std_logic;
sclkout1 : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic;
fbout : out std_logic );
end component;
component altfp_mult
generic (
width_exp : integer := 11;
width_man : integer := 31;
dedicated_multiplier_circuitry : string := "AUTO";
reduced_functionality : string := "NO";
pipeline : natural := 5;
denormal_support : string := "YES";
exception_handling : string := "YES";
lpm_hint : string := "UNUSED";
lpm_type : string := "altfp_mult" );
port (
clock : in std_logic;
clk_en : in std_logic := '1';
aclr : in std_logic := '0';
dataa : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
datab : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
result : out std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
overflow : out std_logic ;
underflow : out std_logic ;
zero : out std_logic ;
denormal : out std_logic ;
indefinite : out std_logic ;
nan : out std_logic );
end component;
component altsqrt
generic (
q_port_width : integer := 1;
r_port_width : integer := 1;
width : integer := 1;
pipeline : integer := 0;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsqrt" );
port (
radical : in std_logic_vector(width - 1 downto 0) ;
clk : in std_logic := '1';
ena : in std_logic := '1';
aclr : in std_logic := '0';
q : out std_logic_vector( q_port_width - 1 downto 0) ;
remainder : out std_logic_vector( r_port_width - 1 downto 0) );
end component;
component parallel_add
generic (
width : natural := 4;
size : natural := 2;
widthr : natural := 4;
shift : natural := 0;
msw_subtract : string := "NO";
representation : string := "UNSIGNED";
pipeline : natural := 0;
result_alignment : string := "LSB";
lpm_hint : string := "UNUSED";
lpm_type : string := "parallel_add" );
port (
data : in altera_mf_logic_2D(size - 1 downto 0, width - 1 downto 0);
clock : in std_logic := '1';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(widthr - 1 downto 0) );
end component;
component a_graycounter
generic (
width : natural;
pvalue : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "a_graycounter" );
port (
clock : in std_logic;
clk_en : in std_logic := '1';
cnt_en : in std_logic := '1';
updown : in std_logic := '1';
aclr : in std_logic := '0';
sclr : in std_logic := '0';
qbin : out std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0) );
end component;
component altsquare
generic (
data_width : natural;
pipeline : natural;
representation : string := "UNSIGNED";
result_width : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "altsquare"
);
port(
aclr : in std_logic := '0';
clock : in std_logic := '1';
data : in std_logic_vector(data_width-1 downto 0);
ena : in std_logic := '1';
result : out std_logic_vector(result_width-1 downto 0)
);
end component;
component sld_virtual_jtag
generic (
lpm_type : string;
lpm_hint : string;
sld_auto_instance_index : string;
sld_instance_index : integer;
sld_ir_width : integer;
sld_sim_n_scan : integer;
sld_sim_total_length : integer;
sld_sim_action : string);
port (
tdo : in std_logic := '0';
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
tck : out std_logic;
tdi : out std_logic;
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
virtual_state_cdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_uir : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_cdr : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_uir : out std_logic;
tms : out std_logic);
end component;
component sld_virtual_jtag_basic
generic (
lpm_type : string;
lpm_hint : string;
sld_mfg_id : natural range 0 to 2047;
sld_type_id : natural range 0 to 255;
sld_version : natural range 0 to 31;
sld_auto_instance_index : string;
sld_instance_index : integer;
sld_ir_width : integer;
sld_sim_n_scan : integer;
sld_sim_total_length : integer;
sld_sim_action : string);
port (
tdo : in std_logic := '0';
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
tck : out std_logic;
tdi : out std_logic;
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
virtual_state_cdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_uir : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_cdr : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_uir : out std_logic;
tms : out std_logic);
end component;
constant ELA_STATUS_BITS : natural := 4;
constant MAX_NUMBER_OF_BITS_FOR_TRIGGERS : natural := 4;
constant SLD_IR_BITS : natural := ELA_STATUS_BITS + MAX_NUMBER_OF_BITS_FOR_TRIGGERS;
component sld_signaltap
generic (
SLD_ADVANCED_TRIGGER_5 : string := "NONE";
SLD_NODE_CRC_LOWORD : natural := 50132;
SLD_INVERSION_MASK : std_logic_vector := "0";
SLD_TRIGGER_BITS : natural := 8;
SLD_POWER_UP_TRIGGER : natural := 0;
SLD_ADVANCED_TRIGGER_6 : string := "NONE";
SLD_ADVANCED_TRIGGER_10 : string := "NONE";
SLD_ADVANCED_TRIGGER_9 : string := "NONE";
SLD_ADVANCED_TRIGGER_7 : string := "NONE";
SLD_INCREMENTAL_ROUTING : natural := 0;
SLD_MEM_ADDRESS_BITS : natural := 7;
SLD_ADVANCED_TRIGGER_ENTITY : string := "basic";
SLD_TRIGGER_IN_ENABLED : natural := 1;
SLD_ADVANCED_TRIGGER_4 : string := "NONE";
SLD_ADVANCED_TRIGGER_8 : string := "NONE";
SLD_TRIGGER_LEVEL : natural := 1;
SLD_ADVANCED_TRIGGER_2 : string := "NONE";
SLD_RAM_BLOCK_TYPE : string := "AUTO";
SLD_ADVANCED_TRIGGER_1 : string := "NONE";
SLD_DATA_BIT_CNTR_BITS : natural := 4;
SLD_INVERSION_MASK_LENGTH : integer := 1;
SLD_SAMPLE_DEPTH : natural := 128;
SLD_NODE_CRC_BITS : natural := 32;
lpm_type : string := "sld_signaltap";
SLD_DATA_BITS : natural := 8;
SLD_ENABLE_ADVANCED_TRIGGER : natural := 0;
SLD_NODE_INFO : natural := 0;
SLD_ADVANCED_TRIGGER_3 : string := "NONE";
SLD_TRIGGER_LEVEL_PIPELINE : natural := 1;
SLD_NODE_CRC_HIWORD : natural := 41394
);
port (
jtag_state_sdr : in std_logic := '0';
ir_out : out std_logic_vector(SLD_IR_BITS-1 downto 0);
jtag_state_cdr : in std_logic := '0';
ir_in : in std_logic_vector(SLD_IR_BITS-1 downto 0) := (others => '0');
tdi : in std_logic := '0';
acq_trigger_out : out std_logic_vector(SLD_TRIGGER_BITS-1 downto 0);
jtag_state_uir : in std_logic := '0';
acq_trigger_in : in std_logic_vector(SLD_TRIGGER_BITS-1 downto 0) := (others => '0');
trigger_out : out std_logic;
acq_data_out : out std_logic_vector(SLD_DATA_BITS-1 downto 0);
acq_data_in : in std_logic_vector(SLD_DATA_BITS-1 downto 0) := (others => '0');
jtag_state_udr : in std_logic := '0';
tdo : out std_logic;
clrn : in std_logic := '0';
crc : in std_logic_vector(SLD_NODE_CRC_BITS-1 downto 0) := (others => '0');
jtag_state_e1dr : in std_logic := '0';
raw_tck : in std_logic := '0';
usr1 : in std_logic := '0';
acq_clk : in std_logic;
shift : in std_logic := '0';
ena : in std_logic := '0';
trigger_in : in std_logic := '0';
update : in std_logic := '0';
rti : in std_logic := '0'
);
end component; --sld_signaltap
component altstratixii_oct
generic (
lpm_type : string := "altstratixii_oct"
);
port (
terminationenable : in std_logic;
terminationclock : in std_logic;
rdn : in std_logic;
rup : in std_logic
);
end component; --altstratixii_oct
constant TOP_PFL_IR_BITS : natural := 5;
component altparallel_flash_loader
generic (
flash_data_width : natural := 16;
safe_mode_revert : natural := 0;
dclk_divisor : natural := 1;
safe_mode_retry : natural := 1;
features_cfg : natural := 1;
burst_mode_intel : natural := 0;
burst_mode : natural := 0;
clk_divisor : natural := 1;
addr_width : natural := 20;
option_bits_start_address : natural := 0;
safe_mode_revert_addr : natural := 0;
lpm_type : string := "ALTPARALLEL_FLASH_LOADER";
features_pgm : natural := 1;
burst_mode_spansion : natural := 0;
auto_restart : STRING := "OFF";
conf_data_width : natural := 1;
TRISTATE_CHECKBOX : natural := 0;
safe_mode_halt : natural := 0
);
port (
fpga_data : out std_logic_vector(conf_data_width-1 downto 0);
fpga_dclk : out std_logic;
flash_nce : out std_logic;
fpga_nstatus : in std_logic := '0';
pfl_clk : in std_logic := '0';
fpga_nconfig : out std_logic;
flash_noe : out std_logic;
flash_nwe : out std_logic;
fpga_conf_done : in std_logic := '0';
pfl_flash_access_granted : in std_logic := '0';
pfl_nreconfigure : in std_logic := '1';
flash_nreset : out std_logic;
pfl_nreset : in std_logic := '0';
flash_data : inout std_logic_vector(flash_data_width-1 downto 0);
flash_nadv : out std_logic;
flash_clk : out std_logic;
flash_addr : out std_logic_vector(addr_width-1 downto 0);
pfl_flash_access_request : out std_logic;
fpga_pgm : in std_logic_vector(2 downto 0) := (others => '0')
);
end component; --altparallel_flash_loader
component altserial_flash_loader
generic (
enable_shared_access : STRING := "OFF";
lpm_type : STRING := "ALTSERIAL_FLASH_LOADER"
);
port (
noe : in std_logic := '0';
asmi_access_granted : in std_logic := '1';
sdoin : in std_logic := '0';
asmi_access_request : out std_logic;
data0out : out std_logic;
scein : in std_logic := '0';
dclkin : in std_logic := '0'
);
end component; --altserial_flash_loader
-- pragma translate_on
component alt_dummy
port (
inclk : in std_logic_vector(1 downto 0);
sclkout1 : out std_logic
);
end component;
end altera_mf_components;
| mit | f62530034363e2cf84ca221de0a62aeb | 0.475285 | 3.92712 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/spacewire/spacewire.vhd | 2 | 6,484 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package spacewire is
type grspw_in_type is record
d : std_logic_vector(1 downto 0);
s : std_logic_vector(1 downto 0);
tickin : std_ulogic;
clkdiv10 : std_logic_vector(7 downto 0);
rmapen : std_ulogic;
dcrstval : std_logic_vector(9 downto 0);
timerrstval : std_logic_vector(11 downto 0);
end record;
type grspw_out_type is record
d : std_logic_vector(1 downto 0);
s : std_logic_vector(1 downto 0);
tickout : std_ulogic;
linkdis : std_ulogic;
end record;
component grspw2 is
generic(
tech : integer range 0 to NTECH := inferred;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end component;
component grspw is
generic(
tech : integer range 0 to NTECH := DEFFABTECH;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
netlist : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type);
end component;
type grspw_in_type_vector is array (natural range <>) of grspw_in_type;
type grspw_out_type_vector is array (natural range <>) of grspw_out_type;
component grspwm is
generic(
tech : integer range 0 to NTECH := DEFFABTECH;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
netlist : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH;
spwcore : integer range 1 to 2 := 2
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end component;
end package;
| mit | c0b693d56e1e8f0adaef9b81e7d0936e | 0.536552 | 3.861823 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/micron/sdram/components.vhd | 2 | 7,268 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Micron SDRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package components is
component mt48lc16m16a2
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "sdram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
component mt46v16m16
GENERIC ( -- Timing for -75Z CL2
tCK : TIME := 7.500 ns;
tCH : TIME := 3.375 ns; -- 0.45*tCK
tCL : TIME := 3.375 ns; -- 0.45*tCK
tDH : TIME := 0.500 ns;
tDS : TIME := 0.500 ns;
tIH : TIME := 0.900 ns;
tIS : TIME := 0.900 ns;
tMRD : TIME := 15.000 ns;
tRAS : TIME := 40.000 ns;
tRAP : TIME := 20.000 ns;
tRC : TIME := 65.000 ns;
tRFC : TIME := 75.000 ns;
tRCD : TIME := 20.000 ns;
tRP : TIME := 20.000 ns;
tRRD : TIME := 15.000 ns;
tWR : TIME := 15.000 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
cols_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "sdram.srec"; -- File to read from
bbits : INTEGER := 16
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END component;
component ftmt48lc16m16a2
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "sdram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
component ddr2 is
generic(
DM_BITS : integer := 2;
ADDR_BITS : integer := 13;
ROW_BITS : integer := 13;
COL_BITS : integer := 9;
DQ_BITS : integer := 16;
DQS_BITS : integer := 2;
TRRD : integer := 10000;
TFAW : integer := 50000;
DEBUG : integer := 1
);
port (
ck : in std_ulogic;
ck_n : in std_ulogic;
cke : in std_ulogic;
cs_n : in std_ulogic;
ras_n : in std_ulogic;
cas_n : in std_ulogic;
we_n : in std_ulogic;
dm_rdqs : inout std_logic_vector(DQS_BITS-1 downto 0);
ba : in std_logic_vector(1 downto 0);
addr : in std_logic_vector(ADDR_BITS-1 downto 0);
dq : inout std_logic_vector(DQ_BITS-1 downto 0);
dqs : inout std_logic_vector(DQS_BITS-1 downto 0);
dqs_n : inout std_logic_vector(DQS_BITS-1 downto 0);
rdqs_n : out std_logic_vector(DQS_BITS-1 downto 0);
odt : in std_ulogic
);
end component;
end;
-- pragma translate_on
| mit | dc9256c57e394b72e9eaf593faf7510c | 0.440286 | 3.382038 | false | false | false | false |
christakissgeo/Matrix-Vector-Multiplication | VHDL Files/rom.vhd | 1 | 2,617 | --ROM for the constant matrix H
library ieee;
use ieee.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use IEEE.Std_logic_unsigned.all;
-----------------------------------
entity rom is
port (
clock : in std_logic;
address : in std_logic_vector (5 downto 0);
rom_enable : in std_logic;
data : out std_logic_vector (7 downto 0)
);
end entity rom;
------------------------------------
architecture rom of rom is
type rom_type is array (0 to 2**6 -1) of std_logic_vector (7 downto 0);
constant H : rom_type := (
0 => "10000000",
1 => "10000000",
2 => "10000000",
3 => "10000000",
4 => "10000000",
5 => "10000000",
6 => "10000000",
7 => "10000000",
8 => "10000000",
9 => "10000000",
10 => "10000000",
11 => "10000000",
12 => "10000000",
13 => "10000000",
14 => "10000000",
15 => "10000000",
16 => "10000000",
17 => "10000000",
18 => "10000000",
19 => "10000000",
20 => "10000000",
21 => "10000000",
22 => "10000000",
23 => "10000000",
24 => "10000000",
25 => "10000000",
26 => "10000000",
27 => "10000000",
28 => "10000000",
29 => "10000000",
30 => "10000000",
31 => "10000000",
32 => "10000000",
33 => "10000000",
34 => "10000000",
35 => "10000000",
36 => "10000000",
37 => "10000000",
38 => "10000000",
39 => "10000000",
40 => "10000000",
41 => "10000000",
42 => "10000000",
43 => "10000000",
44 => "10000000",
45 => "10000000",
46 => "10000000",
47 => "10000000",
48 => "10000000",
49 => "10000000",
50 => "10000000",
51 => "10000000",
52 => "10000000",
53 => "10000000",
54 => "10000000",
55 => "10000000",
56 => "10000000",
57 => "10000000",
58 => "10000000",
59 => "10000000",
60 => "10000000",
61 => "10000000",
62 => "10000000",
63 => "10000000"
);
begin
process(clock)
begin
if rising_edge(clock) then
if rom_enable = '1' then
data <= H(to_integer(unsigned(address)));
else
data <= "00000000";
end if;
end if;
end process;
end architecture rom;
| mit | 3dbed5cbc982036bcd3b28ea8aed485f | 0.413451 | 3.145433 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/i2cslv.vhd | 2 | 19,789 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cslv
-- File: i2cslv.vhd
-- Author: Jan Andersson - Gaisler Research
-- [email protected]
--
-- Description: Simple I2C-slave with AMBA APB interface
--
-- Documentation of generics:
--
-- [hardaddr]
-- If this generic is set to 1 the core uses i2caddr as the hard coded address.
-- If hardaddr is set to 0 the core's address can be changed via the SLVADDR
-- register.
--
-- [tenbit]
-- Support for ten bit addresses.
--
-- [i2caddr]
-- The slave's (initial) i2c address.
--
-- [oepol]
-- Output enable polarity
--
-- The slave has four different modes operation. The mode is defined by the
-- value of the bits RMODE and TMODE.
-- RMODE TMODE I2CSLAVE Mode
-- 0 0 0
-- 0 1 1
-- 1 0 2
-- 1 1 3
--
-- RMODE 0:
-- The slave accepts one byte and NAKs all other transfers until software has
-- acknowledged the received byte.
-- RMODE 1:
-- The slave accepts one byte and keeps SCL low until software has acknowledged
-- the received byte
-- TMODE 0:
-- The slave transmits the same byte to all if the master requests more than
-- one byte in the transfer. The slave then NAKs all read requests unless the
-- Transmit Always Valid (TAV) bit in the control register is set.
-- TMODE 1:
-- The slave transmits one byte and then keeps SCL low until software has
-- acknowledged that the byte has been transmitted.
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity i2cslv is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
-- I2C configuration
hardaddr : integer range 0 to 1 := 0; -- See description above
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2cslv;
architecture rtl of i2cslv is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Core version
constant I2CSLV_REV : integer := 0;
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CSLV, 0, I2CSLV_REV, pirq),
1 => apb_iobar(paddr, pmask));
-- Register addresses
constant SLV_ADDR : std_logic_vector(7 downto 2) := "000000";
constant CTRL_ADDR : std_logic_vector(7 downto 2) := "000001";
constant STS_ADDR : std_logic_vector(7 downto 2) := "000010";
constant MSK_ADDR : std_logic_vector(7 downto 2) := "000011";
constant RD_ADDR : std_logic_vector(7 downto 2) := "000100";
constant TD_ADDR : std_logic_vector(7 downto 2) := "000101";
-- Core configuration
constant TENBIT_SUPPORT : integer := tenbit;
constant I2CADDRLEN : integer := 7 + tenbit*3;
constant HARDCADDR : integer := hardaddr;
constant I2CSLVADDR : std_logic_vector((I2CADDRLEN-1) downto 0) :=
conv_std_logic_vector(i2caddr, I2CADDRLEN);
-- Misc constants
constant I2C_READ : std_ulogic := '1'; -- R/Wn bit
constant I2C_WRITE : std_ulogic := '0';
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE
constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL;
constant I2C_ACK : std_ulogic := '0';
constant TENBIT_ADDR_START : std_logic_vector(4 downto 0) := "11110";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type ctrl_reg_type is record -- Control register
rmode : std_ulogic; -- Receive mode
tmode : std_ulogic; -- Transmit mode
tv : std_ulogic; -- Transmit valid
tav : std_ulogic; -- Transmit always valid
en : std_ulogic; -- Enable
end record;
type sts_reg_type is record -- Status/Mask registers
rec : std_ulogic; -- Received byte
tra : std_ulogic; -- Transmitted byte
nak : std_ulogic; -- NAK'd address
end record;
type slvaddr_reg_type is record -- Slave address register
tba : std_ulogic; -- 10-bit address
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0);
end record;
type i2cslv_reg_bank is record -- APB registers
slvaddr : slvaddr_reg_type;
ctrl : ctrl_reg_type;
sts : sts_reg_type;
msk : sts_reg_type;
receive : std_logic_vector(7 downto 0);
transmit : std_logic_vector(7 downto 0);
end record;
type i2c_in_array is array (6 downto 0) of i2c_in_type;
type slv_state_type is (idle, checkaddr, check10bitaddr, sclhold,
movebyte, handshake);
type i2cslv_reg_type is record
slvstate : slv_state_type;
--
reg : i2cslv_reg_bank;
irq : std_ulogic;
-- Transfer phase
active : boolean;
addr : boolean;
transmit : boolean;
receive : boolean;
-- Shift register
sreg : std_logic_vector(7 downto 0);
cnt : std_logic_vector(2 downto 0);
-- Synchronizers for inputs SCL and SDA
scl : std_ulogic;
sda : std_ulogic;
i2ci : i2c_in_array;
-- Output enables
scloen : std_ulogic;
sdaoen : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Subprograms
-----------------------------------------------------------------------------
-- purpose: Compares the first byte of a received address with the slave's
-- address. The tba input determines if the slave is using a ten bit address.
function compaddr1stb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
sr : slvaddr_reg_type) -- slave address register
return boolean is
variable correct : std_logic_vector(7 downto 1);
begin -- compaddr1stb
if sr.tba = '1' then
correct(7 downto 3) := TENBIT_ADDR_START;
correct(2 downto 1):= sr.slvaddr((I2CADDRLEN-1) downto (I2CADDRLEN-2));
else
correct(7 downto 1) := sr.slvaddr(6 downto 0);
end if;
return ibyte(7 downto 1) = correct(7 downto 1);
end compaddr1stb;
-- purpose: Compares the 2nd byte of a ten bit address with the slave address
function compaddr2ndb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0)) -- slave address
return boolean is
begin -- compaddr2ndb
return ibyte((I2CADDRLEN-3) downto 0) = slvaddr((I2CADDRLEN-3) downto 0);
end compaddr2ndb;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Register interface
signal r, rin : i2cslv_reg_type;
begin
comb: process (r, rstn, apbi, i2ci)
variable v : i2cslv_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(5 downto 0);
variable apbout : std_logic_vector(31 downto 0);
variable sclfilt : std_logic_vector(3 downto 0);
variable sdafilt : std_logic_vector(3 downto 0);
variable tba : boolean;
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
v.i2ci(0) := i2ci; v.i2ci(6 downto 1) := r.i2ci(5 downto 0); tba := false;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when SLV_ADDR =>
apbout(31) := r.reg.slvaddr.tba;
apbout((I2CADDRLEN-1) downto 0) := r.reg.slvaddr.slvaddr;
when CTRL_ADDR =>
apbout(4 downto 0) := r.reg.ctrl.rmode & r.reg.ctrl.tmode &
r.reg.ctrl.tv & r.reg.ctrl.tav & r.reg.ctrl.en;
when STS_ADDR =>
apbout(2 downto 0) := r.reg.sts.rec & r.reg.sts.tra & r.reg.sts.nak;
when MSK_ADDR =>
apbout(2 downto 0) := r.reg.msk.rec & r.reg.msk.tra & r.reg.msk.nak;
when RD_ADDR =>
v.reg.sts.rec := '0';
apbout(7 downto 0) := r.reg.receive;
when TD_ADDR =>
apbout(7 downto 0) := r.reg.transmit;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when SLV_ADDR =>
if HARDCADDR = 0 then
if TENBIT_SUPPORT = 1 then
v.reg.slvaddr.tba := apbi.pwdata(31);
end if;
v.reg.slvaddr.slvaddr := apbi.pwdata((I2CADDRLEN-1) downto 0);
end if;
when CTRL_ADDR =>
v.reg.ctrl.rmode := apbi.pwdata(4);
v.reg.ctrl.tmode := apbi.pwdata(3);
v.reg.ctrl.tv := apbi.pwdata(2);
v.reg.ctrl.tav := apbi.pwdata(1);
v.reg.ctrl.en := apbi.pwdata(0);
when STS_ADDR =>
v.reg.sts.tra := r.reg.sts.tra and not apbi.pwdata(1);
v.reg.sts.nak := r.reg.sts.nak and not apbi.pwdata(0);
when MSK_ADDR =>
v.reg.msk.rec := apbi.pwdata(2);
v.reg.msk.tra := apbi.pwdata(1);
v.reg.msk.nak := apbi.pwdata(0);
when TD_ADDR =>
v.reg.transmit := apbi.pwdata(7 downto 0);
when others => null;
end case;
end if;
----------------------------------------------------------------------------
-- Bus filtering
----------------------------------------------------------------------------
for i in 0 to 3 loop
sclfilt(i) := r.i2ci(i+2).scl; sdafilt(i) := r.i2ci(i+2).sda;
end loop; -- i
if sclfilt = "1111" then v.scl := '1'; end if;
if sclfilt = "0000" then v.scl := '0'; end if;
if sdafilt = "1111" then v.sda := '1'; end if;
if sdafilt = "0000" then v.sda := '0'; end if;
---------------------------------------------------------------------------
-- I2C slave control FSM
---------------------------------------------------------------------------
case r.slvstate is
when idle =>
-- Release bus
if (r.scl and not v.scl) = '1' then
v.sdaoen := I2C_HIZ;
end if;
when checkaddr =>
tba := r.reg.slvaddr.tba = '1';
if compaddr1stb(r.sreg, r.reg.slvaddr) then
if r.sreg(0) = I2C_READ then
if (not tba or (tba and r.active)) then
if r.reg.ctrl.tv = '1' then
-- Transmit data
v.transmit := true;
v.slvstate := handshake;
else
-- No data to transmit, NAK
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
v.slvstate := idle;
end if;
else
-- Ten bit address with R/Wn = 1 and slave not previously
-- addressed.
v.slvstate := idle;
end if;
else
v.receive := not tba;
v.slvstate := handshake;
end if;
else
-- Slave address did not match
v.active := false;
v.slvstate := idle;
end if;
v.sreg := r.reg.transmit;
when check10bitaddr =>
if compaddr2ndb(r.sreg, r.reg.slvaddr.slvaddr) then
-- Slave has been addressed with a matching 10 bit address
-- If we receive a repeated start condition, matching address
-- and R/Wn = 1 we will transmit data. Without start condition we
-- will receive data.
v.addr := true;
v.active := true;
v.receive := true;
v.slvstate := handshake;
else
v.slvstate := idle;
end if;
when sclhold =>
-- This state is used when the device has been addressed to see if SCL
-- should be kept low until the receive register is free or the
-- transmit register is filled. It is also used when a data byte has
-- been transmitted or received to SCL low until software acknowledges
-- the transfer.
if (r.scl and not v.scl) = '1' then
v.scloen := I2C_LOW;
v.sdaoen := I2C_HIZ;
end if;
if ((r.receive and (not r.reg.sts.rec or not r.reg.ctrl.rmode) = '1') or
(r.transmit and (r.reg.ctrl.tv or not r.reg.ctrl.tmode) = '1')) then
v.slvstate := movebyte;
v.scloen := I2C_HIZ;
end if;
v.sreg := r.reg.transmit;
when movebyte =>
if (r.scl and not v.scl) = '1' then
if r.transmit then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
else
v.sdaoen := I2C_HIZ;
end if;
end if;
if (not r.scl and v.scl) = '1' then
v.sreg := r.sreg(6 downto 0) & r.sda;
if r.cnt = "111" then
if r.addr then
v.slvstate := checkaddr;
elsif r.receive nor r.transmit then
v.slvstate := check10bitaddr;
else
v.slvstate := handshake;
end if;
v.cnt := (others => '0');
else
v.cnt := r.cnt + 1;
end if;
end if;
when handshake =>
-- Falling edge
if (r.scl and not v.scl) = '1' then
if r.addr then
v.sdaoen := I2C_LOW;
elsif r.receive then
-- Receive, send ACK/NAK
-- Acknowledge byte if core has room in receive register
-- This code assumes that the core's receive register is free if we are
-- in RMODE 1. This should always be the case unless software has
-- reconfigured the core during operation.
if r.reg.sts.rec = '0' then
v.sdaoen := I2C_LOW;
v.reg.receive := r.sreg;
if r.reg.msk.rec = '1' then
v.irq := '1';
end if;
v.reg.sts.rec := '1';
else
-- NAK the byte, the master must abort the transfer
v.sdaoen := I2C_HIZ;
v.slvstate := idle;
end if;
else
-- Transmit, release bus
v.sdaoen := I2C_HIZ;
-- Byte transmitted, unset TV unless TAV is set.
v.reg.ctrl.tv := r.reg.ctrl.tav;
-- Set status bit and check if interrupt should be generated
if (not v.reg.sts.tra and r.reg.msk.tra) = '1' then
v.irq := '1';
end if;
v.reg.sts.tra := '1';
end if;
if not r.addr and r.receive and v.sdaoen = I2C_HIZ then
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
end if;
end if;
-- Risinge edge
if (not r.scl and v.scl) = '1' then
if r.addr then
v.slvstate := movebyte;
else
if r.receive then
-- RMODE 0: Be ready to accept one more byte which will be NAK'd if
-- software has not read the receive register
-- RMODE 1: Keep SCL low until software has acknowledged received byte
if r.reg.ctrl.rmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
-- Transmit, check ACK/NAK from master
-- If the master NAKs the transmitted byte the transfer has ended and
-- we should wait for the master's next action. If the master ACKs the
-- byte the core will act depending on tmode:
-- TMODE 0:
-- If the master ACKs the byte we must continue to transmit and will
-- transmit the same byte on all requests.
-- TMODE 1:
-- IF the master ACKs the byte we will keep SCL low until software has
-- put new transmit data into the transmit register.
if r.sda = I2C_ACK then
if r.reg.ctrl.tmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
v.slvstate := idle;
end if;
end if;
end if;
v.addr := false;
v.sreg := r.reg.transmit;
end if;
end case;
if r.reg.ctrl.en = '1' then
-- STOP condition
if sclfilt = "1111" and sdafilt = "0011" then
v.active := false;
v.slvstate := idle;
end if;
-- START or repeated START condition
if sclfilt = "1111" and sdafilt = "1100" then
v.slvstate := movebyte;
v.cnt := (others => '0');
v.addr := true;
v.transmit := false;
v.receive := false;
end if;
end if;
----------------------------------------------------------------------------
-- Reset and idle operation
----------------------------------------------------------------------------
if rstn = '0' then
v.slvstate := idle;
v.reg.slvaddr.slvaddr := I2CSLVADDR;
if TENBIT_SUPPORT = 1 then v.reg.slvaddr.tba := '1';
else v.reg.slvaddr.tba := '0'; end if;
v.reg.ctrl.en := '0';
v.reg.sts := ('0', '0', '0');
v.scl := '0';
v.active := false;
v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ;
end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
i2co.scl <= '0';
i2co.scloen <= r.scloen;
i2co.sda <= '0';
i2co.sdaoen <= r.sdaoen;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"i2cslv" & tost(pindex) & ": I2C slave rev " &
tost(I2CSLV_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
| mit | 454e8d96aaee18c4d4a753a22bc622d5 | 0.519531 | 3.874119 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ahb_slv.vhd | 2 | 22,777 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb_slv
-- File: ahb_slv.vhd
-- Author: David Lindh - Gaisler Research
-- Description: AMBA AHB slave interface for DDR-RAM memory controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
use gaisler.ddrrec.all;
entity ahb_slv is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f80#;
sepclk : integer := 0;
dqsize : integer := 64;
dmsize : integer := 8;
tech : integer := virtex2);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
clk0 : in std_ulogic;
csi : in ahb_ctrl_in_type;
cso : out ahb_ctrl_out_type);
end ahb_slv;
architecture rtl of ahb_slv is
-- Configuration for AMBA PlugNplay
constant REVISION : integer := 0;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRMP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type burst_mask_type is array (buffersize-1 downto 0) of integer range 1 to 8;
type hsize_type is array (4 downto 0) of integer range 8 to 128;
constant hsize_array : hsize_type := (128, 64, 32, 16, 8);
signal ahbr : ahb_reg_type;
signal ahbri : ahb_reg_type;
signal csi_synced : ahb_ctrl_in_type;
signal DSRAM_i : syncram_dp_in_type;
signal DSRAM_o : syncram_dp_out_type;
signal ASRAM_i : syncram_2p_in_type;
signal ASRAM_o : syncram_2p_out_type;
signal vcc : std_ulogic;
begin -- rtl
vcc <= '1';
-------------------------------------------------------------------------------
--AMBA AHB control combinatiorial part
-------------------------------------------------------------------------------
ahbcomb : process(ahbr, rst, csi, csi_synced, DSRAM_o)
variable v : ahb_reg_type; -- local variables for registers
variable next_rw_cmd_valid : std_logic_vector((log2(buffersize)-1) downto 0);
begin
v := ahbr;
next_rw_cmd_valid := v.rw_cmd_valid +1;
v.new_burst := '0';
v.sync_write := '0';
v.sync2_write := '0';
-------------------------------------------------------------------------------
-- Give respons on prevoius address cycle (DATA CYCLE)
-------------------------------------------------------------------------------
-- If read and read prediction in previos cycle. Both couldn't be
-- written into address syncram (sync2)
if ahbr.sync2_busy = '1' then
v.sync2_adr := v.pre_read_buffer;
v.sync2_wdata := '0' & ahbr.pre_read_adr;
v.sync2_write := '1';
v.sync2_busy := '0';
end if;
-- In case of a write followed by a read both will try to use sync_ram
-- in same cycle, delays read.
if ahbr.sync_busy = '1' then
v.sync_adr := ahbr.sync_busy_adr;
v.doRead := '1';
-- Write data to address given in previous cycle
elsif ahbr.doWrite = '1' then
-- If first word set all datamasks
if conv_std_logic_vector(v.writecounter,4)(0) = '0' then
v.sync_wdata((2*(dmsize+dqsize))-1 downto 2*dqsize) := (others => '1');
end if;
-- Write data to syncram
v.even_odd_write := (conv_integer(conv_std_logic_vector(v.writecounter,4)(0)));
for i in 0 to dqsize-1 loop
if i >= v.startp*8 and i < (v.startp+v.burst_hsize)*8 then
v.sync_wdata(i + v.even_odd_write*dqsize) := csi.ahbsi.hwdata(i+(v.ahbstartp-v.startp)*8);
end if;
end loop;
-- Clear masks for valid bytes
for i in 0 to dmsize-1 loop
if i >= v.startp and i < (v.startp+v.burst_hsize) then
v.sync_wdata((2*dqsize)+v.even_odd_write*dmsize+i) := '0';
end if;
end loop;
v.sync_adr := v.use_write_buffer & conv_std_logic_vector(v.writecounter,4)(2 downto 1);
v.sync_write := '1';
-- Increase mask counter
v.burst_dm(conv_integer(v.use_write_buffer)) := v.writecounter+1;
v.doWrite := '0';
end if;
-------------------------------------------------------------------------------
-- Analyze incomming command on AHB (ADDRESS CYCLE)
-------------------------------------------------------------------------------
v.sync_busy := '0';
-- An error occured in previous address cycle
if ahbr.prev_error = '1' then
v.hresp := HRESP_ERROR;
v.hready := '1';
v.prev_retry := '0';
v.prev_error := '0';
-- A retry occured in previous address cycle
elsif ahbr.prev_retry = '1' then
v.hresp := HRESP_RETRY;
v.hready := '1';
v.prev_retry := '0';
v.prev_error := '0';
-- Slave selected and previous transfer complete
elsif csi.ahbsi.hsel(hindex) = '1' and csi.ahbsi.hready = '1' then
v.prev_retry := '0';
v.prev_error := '0';
-- Check if hsize is within range
if hsize_array(conv_integer(csi.ahbsi.hsize)) > dqsize and csi.ahbsi.htrans(1) = '1' then
assert false report "AHB HSIZE cannot be greater then DQ size" severity error;
v.hresp := HRESP_ERROR;
v.hready := '0';
v.prev_error := '1';
-- BUSY or IDLE command
elsif csi.ahbsi.htrans(1) = '0' then
v.hresp := HRESP_OKAY;
v.hready := '1';
-- If idle, begin write burst (if waiting)
if csi.ahbsi.htrans = HTRANS_IDLE then
v.w_data_valid := v.rw_cmd_valid;
v.pre_read_valid := '0';
end if;
-- SEQ or NONSEQ command
else
-- Calculate valid bits for transfer according to big endian
case ahbdata is
when 8 => v.ahboffset := "000";
when 16 => v.ahboffset := "00" & csi.ahbsi.haddr(0);
when 32 => v.ahboffset := "0" & csi.ahbsi.haddr(1 downto 0);
when 64 => v.ahboffset := csi.ahbsi.haddr(2 downto 0);
when others => null;
end case;
case dqsize is
when 8 => v.rwadrbuffer := csi.ahbsi.haddr;
v.offset := "000";
when 16 => v.rwadrbuffer := "0" & csi.ahbsi.haddr(31 downto 1);
v.offset := "00" & csi.ahbsi.haddr(0);
when 32 => v.rwadrbuffer := "00" & csi.ahbsi.haddr(31 downto 2);
v.offset := "0" & csi.ahbsi.haddr(1 downto 0);
when 64 => v.rwadrbuffer := "000" & csi.ahbsi.haddr(31 downto 3);
v.offset := csi.ahbsi.haddr(2 downto 0);
when others => null;
end case;
case csi.ahbsi.hsize is
when "000" => v.burst_hsize:= 1;
v.startp:= ((dqsize-8)/8) - conv_integer(v.offset);
v.ahbstartp := ((ahbdata-8)/8) - conv_integer(v.ahboffset);
when "001" => v.burst_hsize:= 2; v.offset(0):= '0';
v.startp:= ((dqsize-16)/8) - conv_integer(v.offset);
v.ahbstartp:= ((ahbdata-16)/8) - conv_integer(v.ahboffset);
when "010" => v.burst_hsize:= 4; v.offset(1 downto 0) := "00";
v.startp:= ((dqsize-32)/8) - conv_integer(v.offset);
v.ahbstartp:= ((ahbdata-32)/8) - conv_integer(v.ahboffset);
when "011" => v.burst_hsize:= 8; v.offset(2 downto 0) := "000";
v.startp:= 0;
v.ahbstartp := 0;
when others =>
assert false report "Too large HSIZE" severity error;
v.hresp := HRESP_ERROR;
v.hready := '0';
v.prev_error := '1';
end case;
-------------------------------------------------------------------------------
-- SEQUENCIAL, continuation of burst
-- Read (seq)
if (csi.ahbsi.hwrite = '0' and csi.ahbsi.htrans = HTRANS_SEQ and
csi.ahbsi.hburst = HBURST_INCR and v.offset /= "000") then
-- Do nothing, requested data is in the same ahb word as
-- already is on ahb bus
elsif (csi.ahbsi.hwrite = '0' and csi.ahbsi.htrans = HTRANS_SEQ and
csi.ahbsi.hburst = HBURST_INCR)
then
-- Check that new command can be part of current burst
if v.readcounter /= v.blockburstlength then
-- Read from Syncram
v.sync_write := '0';
v.doRead := '1';
else
if csi_synced.locked = '0' then
-- Check if a prediction was made that matches this new address
if v.pre_read_valid = '1' then
v.use_read_buffer := v.pre_read_buffer;
v.readcounter := 0;
v.blockburstlength := csi_synced.burstlength;
-- Read from Syncram
v.sync_write := '0';
v.doRead := '1';
v.pre_read_valid := '0';
-- Make new read prediction if buffer not full
if (v.pre_read_buffer+1) /= csi_synced.rw_cmd_done and csi_synced.r_predict = '1' then
v.pre_read_adr := v.rwadrbuffer + csi_synced.burstlength;
v.pre_read_buffer := v.pre_read_buffer +1;
v.pre_read_valid := '1';
v.sync2_write := '1';
v.sync2_wdata := '0' & v.pre_read_adr;
v.sync2_adr := v.pre_read_buffer;
v.rw_cmd_valid := v.pre_read_buffer;
v.w_data_valid := v.pre_read_buffer;
end if;
-- No prediction was made, treat as non sequencial
else
v.new_burst := '1';
end if;
else
v.new_burst := '1';
end if;
end if;
-- Write (seq)
elsif csi.ahbsi.hwrite = '1' and csi.ahbsi.htrans = HTRANS_SEQ then
v.pre_read_valid := '0';
-- Check that new command can be part of current burst
if v.offset /= "000" then
v.doWrite := '1';
v.hresp := HRESP_OKAY;
v.hready := '1';
elsif v.writecounter+1 /= v.blockburstlength and csi_synced.locked = '0' then
v.writecounter := v.writecounter +1;
v.doWrite := '1';
v.hresp := HRESP_OKAY;
v.hready := '1';
-- Command has to start new burst
else
v.w_data_valid := v.rw_cmd_valid;
v.rw_cmd_valid := v.use_write_buffer;
v.new_burst := '1';
end if;
end if;
-------------------------------------------------------------------------------
-- NON SEQUENCIAL, start of new burst
if (csi.ahbsi.htrans = HTRANS_NONSEQ or v.new_burst = '1') then
v.pre_read_valid := '0';
-- Determine how many words that is valid until DRRMEM
-- will wrap within block
case csi_synced.burstlength is
when 2 => v.blockburstlength := csi_synced.burstlength - conv_integer(v.rwadrbuffer(0));
when 4 => v.blockburstlength := csi_synced.burstlength - conv_integer(v.rwadrbuffer(1 downto 0));
when 8 => v.blockburstlength := csi_synced.burstlength - conv_integer(v.rwadrbuffer(2 downto 0));
when others => null;
end case;
-- Commandbuffer full or AHB interface locked
if next_rw_cmd_valid = csi_synced.rw_cmd_done or csi_synced.locked = '1' then
v.hresp := HRESP_RETRY;
v.hready := '0';
v.prev_retry := '1';
-- Put new command into command buffer
else
v.sync2_adr := next_rw_cmd_valid;
-------------------------------------------------------------------------------
-- Read (non-seq)
if csi.ahbsi.hwrite = '0' then
v.hready := '0';
v.readcounter := 0;
v.use_read_buffer := next_rw_cmd_valid;
v.rw_cmd_valid := next_rw_cmd_valid;
v.w_data_valid := next_rw_cmd_valid; -- keep in phase for read
v.sync2_wdata := '0' & v.rwadrbuffer;
v.sync2_write := '1';
-- Wait one cycle (maybe write before)
v.sync_busy_adr := next_rw_cmd_valid & "00";
v.sync_busy := '1';
v.doRead := '0';
-- Predict (if space in buffer and option choosen) next read
next_rw_cmd_valid := next_rw_cmd_valid +1;
if next_rw_cmd_valid /= csi_synced.rw_cmd_done and csi_synced.r_predict = '1' then
v.pre_read_buffer := next_rw_cmd_valid;
v.pre_read_adr := v.rwadrbuffer + v.blockburstlength;
v.pre_read_valid := '1';
v.rw_cmd_valid := next_rw_cmd_valid;
v.w_data_valid := next_rw_cmd_valid; -- keep in phase
-- Address cannot be saved due to syncram busy, write in
-- next cycle
v.sync2_busy := '1';
end if;
-------------------------------------------------------------------------------
-- Write (non-seq)
elsif csi_synced.w_prot = '0' then
v.pre_read_valid := '0';
v.w_data_valid := v.rw_cmd_valid;
v.rw_cmd_valid := next_rw_cmd_valid;
v.writecounter := 0;
v.use_write_buffer := next_rw_cmd_valid;
v.sync2_wdata := '1' & v.rwadrbuffer;
v.sync2_write := '1';
v.doWrite := '1';
v.hresp := HRESP_OKAY;
v.hready := '1';
-- Write protection error
else
assert false report "Write when write protection enabled" severity warning;
v.hresp := HRESP_ERROR;
v.hready := '0';
v.prev_error := '1';
end if; -- write
end if; -- cmdbuffer not full
end if; -- non seq transfer
end if; -- seq or non seq
-- Slave not selected
else
v.w_data_valid := v.rw_cmd_valid;
v.hready := '1';
v.hresp := HRESP_OKAY;
end if;
-- Always set HRDATA (to improve timing)
if conv_std_logic_vector(v.readcounter,4)(0) = '0' then -- Even word
v.read_data((dqsize-1) downto 0) := DSRAM_o.dataout1((dqsize-1) downto 0);
else -- Odd word
v.read_data((dqsize-1) downto 0) := DSRAM_o.dataout1((2*dqsize)-1 downto dqsize);
end if;
--Read data from syncram
for i in 0 to ahbdata-1 loop
if i >= v.ahbstartp*8 and i < (v.ahbstartp+v.burst_hsize)*8 then
v.cur_hrdata(i) := v.read_data(i+(v.startp-v.ahbstartp)*8);
end if;
end loop;
-- Calculate for next clk cycle
-- If read cmd, dont try to read from syncram since maybe write before
if v.sync_busy = '1' then
v.cur_hready := '0';
v.cur_hresp := HRESP_OKAY;
-- Read data is avalible
elsif (csi_synced.rw_cmd_done = v.use_read_buffer or
(csi_synced.rw_cmd_done = v.pre_read_buffer and
v.pre_read_valid = '1')) and v.doRead = '1' then
-- Set address for next read
v.readcounter := v.readcounter +1;
if v.readcounter = v.blockburstlength then
v.sync_adr := (v.use_read_buffer+1) & "00";
else
v.sync_adr := v.use_read_buffer & conv_std_logic_vector(v.readcounter,3)(2 downto 1);
end if;
v.doRead := '0';
v.cur_hready := '1';
v.cur_hresp := HRESP_OKAY;
-- Waiting for read data
elsif v.doRead = '1' then
v.cur_hready := '0';
v.cur_hresp := HRESP_OKAY;
else
v.cur_hready := v.hready;
v.cur_hresp := v.hresp;
end if;
-------------------------------------------------------------------------------
-- Reset
if rst = '0' then
v.readcounter := 0;
v.writecounter := 0;
v.blockburstlength:= 0;
v.hready := '1';
v.hresp := HRESP_OKAY;
v.rwadrbuffer := (others => '0');
v.use_read_buffer := (others => '1');
v.pre_read_buffer := (others => '1');
v.pre_read_adr := (others => '0');
v.pre_read_valid := '0';
v.use_write_buffer:= (others => '1');
v.rw_cmd_valid := (others => '1');
v.w_data_valid := (others => '1');
v.sync_adr := (others => '0');
v.sync_wdata := (others => '0');
v.sync_write := '0';
v.sync_busy := '0';
v.sync_busy_adr := (others => '0');
v.sync2_adr := (others => '0');
v.sync2_wdata := (others => '0');
v.sync2_write := '0';
v.sync2_busy := '0';
v.doRead := '0';
v.doWrite := '0';
v.new_burst := '0';
v.startp := 0;
v.ahbstartp := 0;
v.even_odd_write := 0;
v.burst_hsize := 1;
v.offset := "000";
v.ahboffset := "000";
v.read_data := (others => '0');
v.cur_hready := '0';
v.cur_hresp := HRESP_OKAY;
v.prev_retry := '0';
v.prev_error := '0';
end if;
-------------------------------------------------------------------------------
-- Set output signals
ahbri <= v;
cso.ahbso.hsplit <= (others => '0');
cso.ahbso.hcache <= '1';
cso.ahbso.hirq <= (others => '0');
cso.ahbso.hindex <= hindex;
DSRAM_i.address1 <= v.sync_adr;
DSRAM_i.datain1 <= v.sync_wdata;
DSRAM_i.write1 <= v.sync_write;
ASRAM_i.waddress <= v.sync2_adr;
ASRAM_i.datain <= v.sync2_wdata;
ASRAM_i.write <= v.sync2_write;
end process;
-------------------------------------------------------------------------------
-- Purely combinatorial (no process)
cso.ahbso.hconfig <= HCONFIG;
DSRAM_i.address2 <= csi.dsramsi.address2;
DSRAM_i.datain2 <= csi.dsramsi.datain2;
DSRAM_i.write2 <= csi.dsramsi.write2;
ASRAM_i.raddress <= csi.asramsi.raddress;
cso.asramso <= ASRAM_o;
cso.dsramso <= DSRAM_o;
-------------------------------------------------------------------------------
-- AMBA AHB control clocked register
ahbclk : process(hclk)
begin
if rising_edge(hclk) then
ahbr <= ahbri;
-- Registred outputs
cso.rw_cmd_valid <= ahbri.rw_cmd_valid;
cso.w_data_valid <= ahbri.w_data_valid;
cso.burst_dm <= ahbri.burst_dm;
cso.ahbso.hrdata <= ahbri.cur_hrdata;
cso.ahbso.hresp <= ahbri.cur_hresp;
cso.ahbso.hready <= ahbri.cur_hready;
end if;
end process;
-- Register for incoming signals if separete clock domains
sept : if sepclk = 1 generate
sepp : process(hclk)
begin
if rising_edge(hclk) then
csi_synced.burstlength <= csi.burstlength;
csi_synced.r_predict <= csi.r_predict;
csi_synced.w_prot <= csi.w_prot;
csi_synced.locked <= csi.locked;
csi_synced.rw_cmd_done <= csi.rw_cmd_done;
end if;
end process;
end generate;
sepf : if sepclk = 0 generate
csi_synced.burstlength <= csi.burstlength;
csi_synced.r_predict <= csi.r_predict;
csi_synced.w_prot <= csi.w_prot;
csi_synced.locked <= csi.locked;
-- This sync below required since the current used syncram cannot write
-- and read from the same location in the same cycle
sepp : process(hclk)
begin
if rising_edge(hclk) then
csi_synced.rw_cmd_done <= csi.rw_cmd_done;
end if;
end process;
end generate;
-------------------------------------------------------------------------------
-- SyncRAM
-- Data syncram
S0: syncram_dp
generic map(
tech => tech,
abits => bufferadr,
dbits => 2*(dqsize+dmsize))
port map(
clk1 => hclk,
address1 => DSRAM_i.address1,
datain1 => DSRAM_i.datain1(2*(dqsize+dmsize)-1 downto 0),
dataout1 => DSRAM_o.dataout1(2*(dqsize+dmsize)-1 downto 0),
enable1 => vcc,
write1 => DSRAM_i.write1,
clk2 => clk0,
address2 => DSRAM_i.address2,
datain2 => DSRAM_i.datain2(2*(dqsize+dmsize)-1 downto 0),
dataout2 => DSRAM_o.dataout2(2*(dqsize+dmsize)-1 downto 0),
enable2 => vcc,
write2 => DSRAM_i.write2);
-- Address syncram
S1: syncram_2p
generic map(
tech => tech*0,
abits => log2(buffersize),
dbits => ahbadr+1,
sepclk => sepclk,
wrfst => syncram_2p_write_through(tech))
port map(
rclk => clk0,
renable => vcc,
raddress => ASRAM_i.raddress,
dataout => ASRAM_o.dataout,
wclk => hclk,
write => ASRAM_i.write,
waddress => ASRAM_i.waddress,
datain => ASRAM_i.datain);
-- End of AHB controller
-------------------------------------------------------------------------------
end rtl;
| mit | 2cf3002a248cb70fb02ee4f1d8ba9eba | 0.484041 | 3.670158 | false | false | false | false |
SteffenReith/J1Sc | src/main/vhdl/arch/Nexys4/PLL.vhd | 1 | 6,106 | --------------------------------------------------------------------------------
-- Author: Steffen Reith ([email protected])
--
-- Creation Date: Tue Jan 17 19:29:25 GMT+1 2017
-- Creator: Steffen Reith
-- Module Name: PLL - Structural
-- Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity PLL is
port (clkIn : in std_logic;
clkOut : out std_logic;
isLocked : out std_logic);
end PLL;
architecture Structural of PLL is
-- Control signals
signal locked : std_logic; -- The MMCM has achieved phase alignment
signal psDone_unused : std_logic; -- Dummy signal for phase shift done
signal clkinstopped_unused : std_logic; -- Input clock has stopped (not used)
signal clkfbstopped_unused : std_logic; -- Feedback clock has stopped (not used)
signal drdy_unused : std_logic; -- Reconfiguration ready signal
signal do_unused : std_logic_vector(15 downto 0); -- Reconfiguration data out
-- Internal clock signals
signal clkInI : std_logic; -- Internal buffered input clock
signal clkI1 : std_logic; -- Internal output clock 1
signal clkOutI1 : std_logic; -- Internal already buffered output clock 1
signal clkDI_unused : std_logic; -- Internal delayed output clock
-- Feedback clock signals
signal clkfbI : std_logic; -- Internal unbuffered feedback clock
signal clkfbIBuf : std_logic; -- Internal buffered feedback clock
-- Unused clock ports
signal clkfbb_unused : std_logic;
signal clk0b_unused : std_logic;
signal clk1b_unused : std_logic;
signal clk2_unused : std_logic;
signal clk2b_unused : std_logic;
signal clk3_unused : std_logic;
signal clk3b_unused : std_logic;
signal clk4_unused : std_logic;
signal clk5_unused : std_logic;
signal clk6_unused : std_logic;
begin
-- Instantiate a input clock buffer
clkInBuffer : IBUFG
port map (O => clkInI,
I => clkIn);
-- Instantiate a clock buffer for the internal feedback signal
feedbackBuffer : BUFG
port map (O => clkfbIBuf,
I => clkfbI);
-- Instantiate a clock manager
clkgen : MMCME2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- MMCM programming affecting jitter
CLKOUT4_CASCADE => false, -- don't divide output more than 128
COMPENSATION => "ZHOLD", -- Clk input compensation for feedback
STARTUP_WAIT => false, -- not supported yet (set to default)
DIVCLK_DIVIDE => 1, -- Division ratio for output clocks
CLKFBOUT_MULT_F => 10.000, -- set feedback base
CLKFBOUT_PHASE => 0.000, -- phase of feedback output
CLKFBOUT_USE_FINE_PS => false, -- Don't enable fine shift
--CLKOUT0_DIVIDE_F => 12.500, -- Scale clock to 80Mhz
CLKOUT0_DIVIDE_F => 10.000, -- Scale to 100Mhz
CLKOUT0_PHASE => 0.000, -- Phase of clock 0 (no shift)
CLKOUT0_DUTY_CYCLE => 0.500, -- Duty cycle of clock 0
CLKOUT0_USE_FINE_PS => false, -- No fine shift for clock 0
CLKOUT1_DIVIDE => 10, -- Scale clock 1 to 1.0
CLKOUT1_PHASE => 270.000, -- Phase of clock 1 (delayed)
CLKOUT1_DUTY_CYCLE => 0.500, -- Duty cycle of clock 1
CLKOUT1_USE_FINE_PS => false, -- No fine shift for clock 1
CLKIN1_PERIOD => 10.000, -- 10ns input clock period -> 100Mhz
REF_JITTER1 => 0.010) -- Set expected jitter to default
port map (
CLKFBOUT => clkfbI,
CLKFBOUTB => clkfbb_unused, -- Unused inverted feedback
-- Output clocks (delayed and non inverted)
CLKOUT0 => clkI1,
CLKOUT0B => clk0b_unused,
CLKOUT1 => clkDI_unused,
CLKOUT1B => clk1b_unused,
-- Unused clocks
CLKOUT2 => clk2_unused,
CLKOUT2B => clk2b_unused,
CLKOUT3 => clk3_unused,
CLKOUT3B => clk3b_unused,
CLKOUT4 => clk4_unused,
CLKOUT5 => clk5_unused,
CLKOUT6 => clk6_unused,
-- Input clock control
CLKFBIN => clkfbIBuf, -- Buffered feedback signal
CLKIN1 => clkInI, -- Input clock
CLKIN2 => '0', -- Second input clock is not used
CLKINSEL => '1', -- Select primary input clock
-- Disable dynamic reconfiguration
DADDR => (others => '0'), -- set all address bits to 0
DCLK => '0', -- No clock for the reconfig port
DEN => '0', -- Disable to reconfiguration port
DI => (others => '0'), -- set reconfiguration data to 0
DO => do_unused, -- Ignore MMCM reconfig data output
DRDY => drdy_unused, -- Ignore the ready signal
DWE => '0', -- Disable the write enable
-- Don't implement dynamic phase shift
PSCLK => '0', -- No phase shift clock
PSEN => '0', -- Disable phase shift
PSINCDEC => '0', -- No inc / dec of phase shift
PSDONE => psDone_unused, -- Dummy signal for phase shift done
-- Other control and status signals
LOCKED => locked, -- MMCE clock is stable
CLKINSTOPPED => clkinstopped_unused, -- Input clock has stopped (not used)
CLKFBSTOPPED => clkfbstopped_unused, -- Feedback clock has stopped (not used)
PWRDWN => '0', -- Don't power down MMCE
RST => '0'); -- No reset after startup
-- Scaled clock
clk1Buf : BUFGCE
port map (O => clkOutI1,
CE => locked,
I => clkI1);
clkOut <= clkOutI1;
-- Provide the locked signal to the outside world
isLocked <= locked;
end architecture;
| bsd-3-clause | 923a6ff584d5aa6288689eb1797fcb9a | 0.565182 | 4.148098 | false | false | false | false |
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