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markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/nios_dut_rst_controller.vhd | 1 | 9,070 | -- nios_dut_rst_controller.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_dut_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity nios_dut_rst_controller;
architecture rtl of nios_dut_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of nios_dut_rst_controller
| gpl-3.0 | 6e7fb7a1650849a81f96f3a73ed5729d | 0.546196 | 2.72782 | false | false | false | false |
nussbrot/AdvPT | wb_test/src/vhdl/wbi_m2s4.vhd | 2 | 11,667 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2017 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used AND/OR copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
--*
--* @short INTERCON
--* Generated by TCL script gen_intercon.tcl. Do not edit this file.
--* @author wrupprecht
--*
-------------------------------------------------------------------------------
-- for defines see wbi_m2s4.sxl
--
-- Generated Wed Jun 21 07:50:50 CEST 2017
--
-- Wishbone masters:
-- wbm_1
-- wbm_2
--
-- Wishbone slaves:
-- wbs_1
-- baseaddr 0x00000000 - size 0x00000100
-- wbs_2
-- baseaddr 0x00000200 - size 0x00000010
-- wbs_3
-- baseaddr 0x00100000 - size 0x00001000
-- wbs_4
-- baseaddr 0x00101000 - size 0x00000100
--
-- Intercon type: SharedBus
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY rtl_lib;
ENTITY wbi_m2s4 IS
PORT (
-- wishbone master port(s)
-- wbm_1
i_wbm_1_o_cyc : IN STD_LOGIC;
i_wbm_1_o_stb : IN STD_LOGIC;
i_wbm_1_o_we : IN STD_LOGIC;
i_wbm_1_o_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wbm_1_o_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbm_1_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_1_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_1_i_ack : OUT STD_LOGIC;
o_wbm_1_i_rty : OUT STD_LOGIC;
o_wbm_1_i_err : OUT STD_LOGIC;
-- wbm_2
i_wbm_2_o_cyc : IN STD_LOGIC;
i_wbm_2_o_stb : IN STD_LOGIC;
i_wbm_2_o_we : IN STD_LOGIC;
i_wbm_2_o_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wbm_2_o_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbm_2_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_2_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_2_i_ack : OUT STD_LOGIC;
o_wbm_2_i_rty : OUT STD_LOGIC;
o_wbm_2_i_err : OUT STD_LOGIC;
-- wishbone slave port(s)
-- wbs_1
o_wbs_1_i_cyc : OUT STD_LOGIC;
o_wbs_1_i_stb : OUT STD_LOGIC;
o_wbs_1_i_we : OUT STD_LOGIC;
o_wbs_1_i_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
o_wbs_1_i_addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_wbs_1_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_1_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_1_o_ack : IN STD_LOGIC;
i_wbs_1_o_rty : IN STD_LOGIC;
i_wbs_1_o_err : IN STD_LOGIC;
-- wbs_2
o_wbs_2_i_cyc : OUT STD_LOGIC;
o_wbs_2_i_stb : OUT STD_LOGIC;
o_wbs_2_i_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
o_wbs_2_i_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wbs_2_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_2_o_ack : IN STD_LOGIC;
i_wbs_2_o_rty : IN STD_LOGIC;
i_wbs_2_o_err : IN STD_LOGIC;
-- wbs_3
o_wbs_3_i_cyc : OUT STD_LOGIC;
o_wbs_3_i_stb : OUT STD_LOGIC;
o_wbs_3_i_we : OUT STD_LOGIC;
o_wbs_3_i_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
o_wbs_3_i_addr : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
o_wbs_3_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_3_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_3_o_ack : IN STD_LOGIC;
i_wbs_3_o_rty : IN STD_LOGIC;
i_wbs_3_o_err : IN STD_LOGIC;
-- wbs_4
o_wbs_4_i_cyc : OUT STD_LOGIC;
o_wbs_4_i_stb : OUT STD_LOGIC;
o_wbs_4_i_we : OUT STD_LOGIC;
o_wbs_4_i_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
o_wbs_4_i_addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_wbs_4_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_4_o_ack : IN STD_LOGIC;
i_wbs_4_o_rty : IN STD_LOGIC;
i_wbs_4_o_err : IN STD_LOGIC;
-- clock and reset
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC := '1');
END ENTITY wbi_m2s4;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF wbi_m2s4 IS
FUNCTION "AND" (
le : STD_LOGIC_VECTOR;
ri : STD_LOGIC)
RETURN STD_LOGIC_VECTOR IS
VARIABLE v_result : STD_LOGIC_VECTOR(le'RANGE);
BEGIN
FOR i IN le'RANGE LOOP
v_result(i) := le(i) AND ri;
END LOOP;
RETURN v_result;
END FUNCTION "AND";
SIGNAL s_wbm_1_bg : STD_LOGIC; -- bus grant
SIGNAL s_wbm_2_bg : STD_LOGIC; -- bus grant
SIGNAL s_wbs_1_ss : STD_LOGIC; -- slave select
SIGNAL s_wbs_2_ss : STD_LOGIC; -- slave select
SIGNAL s_wbs_3_ss : STD_LOGIC; -- slave select
SIGNAL s_wbs_4_ss : STD_LOGIC; -- slave select
BEGIN -- rtl
arbiter_sharedbus : BLOCK
SIGNAL s_wbm_1_bg_1 : STD_LOGIC;
SIGNAL s_wbm_1_bb_1 : STD_LOGIC;
SIGNAL s_wbm_1_bg_2 : STD_LOGIC;
SIGNAL s_wbm_1_bb_2 : STD_LOGIC;
SIGNAL s_wbm_1_bg_q : STD_LOGIC;
SIGNAL s_wbm_2_bg_1 : STD_LOGIC;
SIGNAL s_wbm_2_bb_1 : STD_LOGIC;
SIGNAL s_wbm_2_bg_2 : STD_LOGIC;
SIGNAL s_wbm_2_bb_2 : STD_LOGIC;
SIGNAL s_wbm_2_bg_q : STD_LOGIC;
SIGNAL s_wbm_1_traffic_ctrl_limit : STD_LOGIC;
SIGNAL s_wbm_2_traffic_ctrl_limit : STD_LOGIC;
SIGNAL s_ack : STD_LOGIC;
SIGNAL s_ce : STD_LOGIC;
SIGNAL s_idle : STD_LOGIC;
BEGIN -- arbiter
s_ack <= i_wbs_1_o_ack OR i_wbs_2_o_ack OR i_wbs_3_o_ack OR i_wbs_4_o_ack;
wb_traffic_supervision_1 : ENTITY rtl_lib.wb_traffic_supervision
GENERIC MAP (
g_priority => 1,
g_tot_priority => 2)
PORT MAP (
i_bg => s_wbm_1_bg,
i_ce => s_ce,
o_traffic_limit => s_wbm_1_traffic_ctrl_limit,
clk => clk,
rst_n => rst_n);
wb_traffic_supervision_2 : ENTITY rtl_lib.wb_traffic_supervision
GENERIC MAP (
g_priority => 1,
g_tot_priority => 2)
PORT MAP (
i_bg => s_wbm_2_bg,
i_ce => s_ce,
o_traffic_limit => s_wbm_2_traffic_ctrl_limit,
clk => clk,
rst_n => rst_n);
PROCESS (clk, rst_n)
BEGIN
IF (rst_n = '0') THEN
s_wbm_1_bg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (s_wbm_1_bg_q = '0') THEN
s_wbm_1_bg_q <= s_wbm_1_bg;
ELSIF (s_ack = '1') THEN
s_wbm_1_bg_q <= '0';
ELSIF (i_wbm_1_o_cyc = '0') THEN
s_wbm_1_bg_q <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst_n)
BEGIN
IF (rst_n = '0') THEN
s_wbm_2_bg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (s_wbm_2_bg_q = '0') THEN
s_wbm_2_bg_q <= s_wbm_2_bg;
ELSIF (s_ack = '1') THEN
s_wbm_2_bg_q <= '0';
ELSIF (i_wbm_2_o_cyc = '0') THEN
s_wbm_2_bg_q <= '0';
END IF;
END IF;
END PROCESS;
s_idle <= '1' WHEN (s_wbm_1_bg_q = '0' AND s_wbm_2_bg_q = '0') ELSE '0';
s_wbm_1_bg_1 <= '1' WHEN (s_idle = '1' AND i_wbm_1_o_cyc = '1' AND s_wbm_1_traffic_ctrl_limit = '0') ELSE '0';
s_wbm_1_bb_1 <= '1' WHEN (s_wbm_1_bg_1 = '1') ELSE '0';
s_wbm_2_bg_1 <= '1' WHEN (s_idle = '1' AND i_wbm_2_o_cyc = '1' AND s_wbm_2_traffic_ctrl_limit = '0' AND s_wbm_1_bb_1 = '0') ELSE '0';
s_wbm_2_bb_1 <= '1' WHEN (s_wbm_2_bg_1 = '1' OR s_wbm_1_bb_1 = '1') ELSE '0';
s_wbm_1_bg_2 <= '1' WHEN (s_idle = '1' AND s_wbm_2_bb_1 = '0' AND i_wbm_1_o_cyc = '1') ELSE '0';
s_wbm_1_bb_2 <= '1' WHEN (s_wbm_1_bg_2 = '1' OR s_wbm_2_bb_1 = '1') ELSE '0';
s_wbm_2_bg_2 <= '1' WHEN (s_idle = '1' AND s_wbm_1_bb_2 = '0' AND i_wbm_2_o_cyc = '1') ELSE '0';
s_wbm_2_bb_2 <= '1' WHEN (s_wbm_2_bg_2 = '1' OR s_wbm_1_bb_2 = '1') ELSE '0';
s_wbm_1_bg <= s_wbm_1_bg_q OR s_wbm_1_bg_1 OR s_wbm_1_bg_2;
s_wbm_2_bg <= s_wbm_2_bg_q OR s_wbm_2_bg_1 OR s_wbm_2_bg_2;
s_ce <= i_wbm_1_o_cyc OR i_wbm_2_o_cyc WHEN (s_idle = '1') ELSE '0';
END BLOCK arbiter_sharedbus;
decoder : BLOCK
SIGNAL s_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
s_addr <= (i_wbm_1_o_addr AND s_wbm_1_bg) OR (i_wbm_2_o_addr AND s_wbm_2_bg);
s_wbs_1_ss <=
'1' WHEN (s_addr(31 DOWNTO 8) = "000000000000000000000000") ELSE '0';
s_wbs_2_ss <=
'1' WHEN (s_addr(31 DOWNTO 4) = "0000000000000000000000100000") ELSE '0';
s_wbs_3_ss <=
'1' WHEN (s_addr(31 DOWNTO 12) = "00000000000100000000") ELSE '0';
s_wbs_4_ss <=
'1' WHEN (s_addr(31 DOWNTO 8) = "000000000001000000010000") ELSE '0';
o_wbs_1_i_addr <= s_addr(7 DOWNTO 0);
o_wbs_2_i_addr <= s_addr(3 DOWNTO 0);
o_wbs_3_i_addr <= s_addr(11 DOWNTO 0);
o_wbs_4_i_addr <= s_addr(7 DOWNTO 0);
END BLOCK decoder;
mux : BLOCK
SIGNAL s_cyc : STD_LOGIC;
SIGNAL s_stb : STD_LOGIC;
SIGNAL s_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL s_we : STD_LOGIC;
SIGNAL s_data_m2s : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_data_s2m : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_ack : STD_LOGIC;
SIGNAL s_rty : STD_LOGIC;
SIGNAL s_err : STD_LOGIC;
BEGIN
-- cyc
s_cyc <= (i_wbm_1_o_cyc AND s_wbm_1_bg) OR (i_wbm_2_o_cyc AND s_wbm_2_bg);
o_wbs_1_i_cyc <= s_cyc AND s_wbs_1_ss;
o_wbs_2_i_cyc <= s_cyc AND s_wbs_2_ss;
o_wbs_3_i_cyc <= s_cyc AND s_wbs_3_ss;
o_wbs_4_i_cyc <= s_cyc AND s_wbs_4_ss;
-- stb
s_stb <= (i_wbm_1_o_stb AND s_wbm_1_bg) OR (i_wbm_2_o_stb AND s_wbm_2_bg);
o_wbs_1_i_stb <= s_stb AND s_wbs_1_ss;
o_wbs_2_i_stb <= s_stb AND s_wbs_2_ss;
o_wbs_3_i_stb <= s_stb AND s_wbs_3_ss;
o_wbs_4_i_stb <= s_stb AND s_wbs_4_ss;
-- sel
s_sel <= (i_wbm_1_o_sel AND s_wbm_1_bg) OR (i_wbm_2_o_sel AND s_wbm_2_bg);
o_wbs_1_i_sel <= s_sel;
o_wbs_2_i_sel <= s_sel;
o_wbs_3_i_sel <= s_sel;
o_wbs_4_i_sel <= s_sel;
-- we
s_we <= (i_wbm_1_o_we AND s_wbm_1_bg) OR (i_wbm_2_o_we AND s_wbm_2_bg);
o_wbs_1_i_we <= s_we;
o_wbs_3_i_we <= s_we;
o_wbs_4_i_we <= s_we;
-- data m2s
s_data_m2s <= (i_wbm_1_o_data AND s_wbm_1_bg) OR (i_wbm_2_o_data AND s_wbm_2_bg);
o_wbs_1_i_data <= s_data_m2s;
o_wbs_3_i_data <= s_data_m2s;
o_wbs_4_i_data <= s_data_m2s;
-- data s2m
s_data_s2m <= (i_wbs_1_o_data AND s_wbs_1_ss) OR (i_wbs_2_o_data AND s_wbs_2_ss) OR (i_wbs_3_o_data AND s_wbs_3_ss) OR (i_wbs_4_o_data AND s_wbs_4_ss);
o_wbm_1_i_data <= s_data_s2m;
o_wbm_2_i_data <= s_data_s2m;
-- ack
s_ack <= i_wbs_1_o_ack OR i_wbs_2_o_ack OR i_wbs_3_o_ack OR i_wbs_4_o_ack;
o_wbm_1_i_ack <= s_ack AND s_wbm_1_bg;
o_wbm_2_i_ack <= s_ack AND s_wbm_2_bg;
-- rty
s_rty <= i_wbs_1_o_rty OR i_wbs_2_o_rty OR i_wbs_3_o_rty OR i_wbs_4_o_rty;
o_wbm_1_i_rty <= s_rty AND s_wbm_1_bg;
o_wbm_2_i_rty <= s_rty AND s_wbm_2_bg;
-- err
s_err <= i_wbs_1_o_err OR i_wbs_2_o_err OR i_wbs_3_o_err OR i_wbs_4_o_err;
o_wbm_1_i_err <= s_err AND s_wbm_1_bg;
o_wbm_2_i_err <= s_err AND s_wbm_2_bg;
END BLOCK mux;
END ARCHITECTURE rtl;
| mit | 8ba506275eabe2d2eaa1b79429b28e0b | 0.5075 | 2.543492 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_memory_ctrl.vhd | 1 | 9,278 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
--use work.tl_sctb_pkg.all;
--use work.tl_string_util_pkg.all;
-- This module performs the memory operations that are instructed
-- by the nano_cpu. This controller copies data to or from a
-- designated BRAM, and notifies the nano_cpu that the transfer
-- is complete.
entity usb_memory_ctrl is
generic (
g_big_endian : boolean;
g_tag : std_logic_vector(7 downto 0) := X"55" );
port (
clock : in std_logic;
reset : in std_logic;
-- cmd interface
cmd_addr : in std_logic_vector(3 downto 0);
cmd_valid : in std_logic;
cmd_write : in std_logic;
cmd_wdata : in std_logic_vector(15 downto 0);
cmd_ack : out std_logic;
cmd_done : out std_logic;
cmd_ready : out std_logic;
-- BRAM interface
ram_addr : out std_logic_vector(10 downto 2);
ram_en : out std_logic;
ram_we : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(31 downto 0);
ram_rdata : in std_logic_vector(31 downto 0);
-- memory interface
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32 );
end entity;
architecture gideon of usb_memory_ctrl is
type t_state is (idle, reading, writing, data_wait, prefetch, init);
signal state : t_state;
signal mem_addr_r : unsigned(25 downto 0) := (others => '0');
signal mem_addr_i : unsigned(25 downto 2) := (others => '0');
signal ram_addr_i : unsigned(8 downto 2) := (others => '0');
signal size_r : unsigned(1 downto 0) := "00";
signal mreq : std_logic := '0';
signal rwn : std_logic := '1';
signal addr_do_load : std_logic := '0';
signal new_addr : std_logic := '0';
signal addr_do_inc : std_logic := '0';
signal rem_do_load : std_logic;
signal rem_do_dec : std_logic;
signal remain_is_0 : std_logic;
signal remain_is_1 : std_logic;
signal buffer_idx : std_logic_vector(10 downto 9) := "00";
signal ram_we_i : std_logic_vector(3 downto 0);
signal ram_wnext : std_logic;
signal rdata_valid : std_logic;
signal first_req : std_logic;
signal last_req : std_logic;
signal mem_rdata_le : std_logic_vector(31 downto 0);
begin
mem_req.tag(7) <= last_req;
mem_req.tag(6) <= first_req;
mem_req.tag(5 downto 0) <= g_tag(5 downto 0);
mem_req.request <= mreq;
mem_req.address <= mem_addr_i & mem_addr_r(1 downto 0);
mem_req.read_writen <= rwn;
mem_req.data <= ram_rdata;
mem_req.byte_en <= "1111";
-- pop from fifo when we process the access
cmd_ack <= '1' when (state = idle) and (cmd_valid='1') else '0';
process(buffer_idx, state, mreq, mem_resp, ram_addr_i, ram_we_i)
begin
ram_addr <= buffer_idx & std_logic_vector(ram_addr_i);
ram_en <= '0';
-- for writing to memory, we enable the BRAM only when we are going to set
-- the request, such that the data and the request comes at the same time
case state is
when prefetch =>
ram_en <= '1';
when writing =>
if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) then
ram_en <= '1';
end if;
when others =>
null;
end case;
rem_do_dec <= '0';
if mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0) then
rem_do_dec <= '1';
end if;
-- for reading from memory, it doesn't matter in which state we are:
if ram_we_i /= "0000" then
ram_en <= '1';
end if;
end process;
ram_we <= ram_we_i;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
rwn <= '1';
if cmd_valid='1' then
if cmd_write='1' then
cmd_done <= '0';
case cmd_addr is
when X"0" =>
mem_addr_r(15 downto 0) <= unsigned(cmd_wdata(15 downto 0));
new_addr <= '1';
when X"1" =>
mem_addr_r(25 downto 16) <= unsigned(cmd_wdata(9 downto 0));
new_addr <= '1';
when X"2" =>
rwn <= '0';
size_r <= unsigned(cmd_wdata(1 downto 0));
state <= init;
when X"3" =>
size_r <= unsigned(cmd_wdata(1 downto 0));
state <= init;
when X"4" =>
buffer_idx <= cmd_wdata(15 downto 14);
when others =>
null;
end case;
end if;
end if;
when init =>
new_addr <= '0';
ram_addr_i <= (others => '0');
first_req <= '1';
if rwn='1' then
mreq <= '1';
state <= reading;
-- sctb_trace("Reading buffer " & hstr(buffer_idx) & " from memory address " & hstr(mem_addr_r));
else
state <= prefetch;
-- sctb_trace("Writing buffer " & hstr(buffer_idx) & " to memory address " & hstr(mem_addr_r));
end if;
when reading =>
if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) then
first_req <= '0';
if last_req = '1' then
state <= data_wait;
cmd_done <= '1';
mreq <= '0';
end if;
end if;
when data_wait =>
-- just wait until we get a tag on data valid that indicates the last dataword of the transfer
if rdata_valid = '1' and mem_resp.dack_tag(7) = '1' then
state <= idle;
end if;
when prefetch =>
mreq <= '1';
ram_addr_i <= ram_addr_i + 1;
state <= writing;
when writing =>
if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) then
first_req <= '0';
ram_addr_i <= ram_addr_i + 1;
if remain_is_1 = '1' then
state <= idle;
cmd_done <= '1';
mreq <= '0';
end if;
end if;
when others =>
null;
end case;
if ram_wnext = '1' then
ram_addr_i <= ram_addr_i + 1;
end if;
if reset='1' then
state <= idle;
mreq <= '0';
cmd_done <= '0';
new_addr <= '0';
first_req <= '0';
end if;
end if;
end process;
cmd_ready <= '1' when (state = idle) else '0';
addr_do_load <= new_addr when (state = init) else '0';
addr_do_inc <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) else '0';
i_addr: entity work.mem_addr_counter
port map (
clock => clock,
load_value => mem_addr_r(25 downto 2),
do_load => addr_do_load,
do_inc => addr_do_inc,
address => mem_addr_i );
rem_do_load <= '1' when cmd_valid='1' and cmd_write='1' and cmd_addr(3 downto 1)="001" else '0';
i_rem: entity work.mem_remain_counter
port map (
clock => clock,
load_value => unsigned(cmd_wdata(9 downto 2)),
do_load => rem_do_load,
do_dec => rem_do_dec,
remain => open,
remain_is_1 => remain_is_1,
remain_is_0 => remain_is_0 );
last_req <= remain_is_1;
rdata_valid <= '1' when mem_resp.dack_tag(5 downto 0) = g_tag(5 downto 0) else '0';
mem_rdata_le <= byte_swap(mem_resp.data, g_big_endian);
i_align: entity work.align_read_to_bram
port map (
clock => clock,
reset => reset,
rdata => mem_rdata_le,
rdata_valid => rdata_valid,
first_word => mem_resp.dack_tag(6),
last_word => mem_resp.dack_tag(7),
offset => mem_addr_r(1 downto 0),
last_bytes => size_r,
wdata => ram_wdata,
wmask => ram_we_i,
wnext => ram_wnext );
end architecture;
| gpl-3.0 | e120566830db911ea94717211bcee7ce | 0.448804 | 3.765422 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/synchroniser/vhdl_source/synchronizer_gzw.vhd | 1 | 4,950 | -------------------------------------------------------------------------------
-- Title : Vector Synchronizer block
-- Author : Gideon Zweijtzer ([email protected])
-------------------------------------------------------------------------------
-- Description: Synchroniser block implementing a better synchronizer.
--
-- TIMING CONSTRAINTS
--
-- For Altera users:
-- Add the following lines to your SDC file to add false path constraints to
-- the required paths:
--
-- set_false_path \
-- -from [get_registers *\|synchronizer_gzw:*\|*_tig_src] \
-- -to [get_registers *\|synchronizer_gzw:*\|*_tig_dst]
--
-- For Xilinx users:
-- Add the following lines to your UCF file to add timing ignore attributes to
-- the required paths:
--
-- INST "*_tig_src*" TNM = "tnm_sync_src";
-- INST "*_tig_dst*" TNM = "tnm_sync_dst";
-- TIMESPEC "ts_sync_tig" = FROM "tnm_sync_src" TO "tnm_sync_dst" TIG;
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer_gzw is
generic (
g_width : natural := 16;
g_fast : boolean := false );
port (
tx_clock : in std_logic;
tx_push : in std_logic;
tx_data : in std_logic_vector(g_width - 1 downto 0) := (others => '0');
tx_done : out std_logic;
rx_clock : in std_logic;
rx_new_data : out std_logic;
rx_data : out std_logic_vector(g_width - 1 downto 0) := (others => '0')
);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of synchronizer_gzw : entity is "no";
attribute register_balancing : string;
attribute register_balancing of synchronizer_gzw : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of synchronizer_gzw : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of synchronizer_gzw : entity is true;
-----------------------------------------------------------------------------
end entity;
architecture rtl of synchronizer_gzw is
signal tx_inhibit : std_logic := '0';
signal tx_enable : std_logic := '0';
signal tx_done_i : std_logic := '0';
signal tx_tig_src : std_logic := '0';
signal rx_tig_dst : std_logic := '0';
signal rx_tig_src : std_logic := '0';
signal rx_stable : std_logic := '0';
signal rx_done : std_logic := '0';
signal tx_tig_dst : std_logic := '0';
signal tx_stable : std_logic := '0';
signal tx_stable_d : std_logic := '0';
signal tx_data_tig_src : std_logic_vector(tx_data'range) := (others => '0');
signal rx_data_tig_dst : std_logic_vector(tx_data'range) := (others => '0');
begin
tx_enable <= tx_push and not tx_inhibit;
tx_inhibit <= tx_tig_src xor tx_stable;
p_tx: process(tx_clock)
begin
if rising_edge(tx_clock) then
-- path to receive side
tx_tig_src <= tx_tig_src xor tx_enable; -- toggle flipfop
if tx_enable = '1' then
tx_data_tig_src <= tx_data;
end if;
-- path from receive side
tx_stable <= tx_tig_dst;
tx_stable_d <= tx_stable;
if not g_fast then
tx_tig_dst <= rx_tig_src;
end if;
end if;
if falling_edge(tx_clock) then
if g_fast then
tx_tig_dst <= rx_tig_src;
end if;
end if;
end process;
tx_done_i <= tx_stable xor tx_stable_d;
tx_done <= tx_done_i;
p_rx: process(rx_clock)
begin
if rising_edge(rx_clock) then
-- path from transmit side
if not g_fast then
rx_tig_dst <= tx_tig_src;
end if;
rx_stable <= rx_tig_dst;
rx_tig_src <= rx_stable; -- rx_tig_src = stable_d
if rx_done = '1' then
rx_data_tig_dst <= tx_data_tig_src;
end if;
rx_new_data <= rx_done;
end if;
if falling_edge(rx_clock) then
if g_fast then
rx_tig_dst <= tx_tig_src;
end if;
end if;
end process;
rx_done <= rx_tig_src xor rx_stable;
rx_data <= rx_data_tig_dst;
end rtl;
| gpl-3.0 | c9c5a4c67b16907a0cddc8fe02e28b89 | 0.468485 | 3.944223 | false | false | false | false |
markusC64/1541ultimate2 | target/fpga/u2p_memtest/memphy_alt_mem_phy_pll.vhd | 1 | 23,757 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: memphy_alt_mem_phy_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY memphy_alt_mem_phy_pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
phasecounterselect : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
phasestep : IN STD_LOGIC := '0';
phaseupdown : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC
);
END memphy_alt_mem_phy_pll;
ARCHITECTURE SYN OF memphy_alt_mem_phy_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire10_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire10 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
vco_frequency_control : STRING;
vco_phase_shift_step : NATURAL;
width_clock : NATURAL;
width_phasecounterselect : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
scanclk : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire10_bv(0 DOWNTO 0) <= "0";
sub_wire10 <= To_stdlogicvector(sub_wire10_bv);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
c4 <= sub_wire5;
locked <= sub_wire6;
phasedone <= sub_wire7;
sub_wire8 <= inclk0;
sub_wire9 <= sub_wire10(0 DOWNTO 0) & sub_wire8;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 10,
clk0_duty_cycle => 50,
clk0_multiply_by => 13,
clk0_phase_shift => "0",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
clk1_multiply_by => 13,
clk1_phase_shift => "0",
clk2_divide_by => 5,
clk2_duty_cycle => 50,
clk2_multiply_by => 13,
clk2_phase_shift => "-1923",
clk3_divide_by => 5,
clk3_duty_cycle => 50,
clk3_multiply_by => 13,
clk3_phase_shift => "0",
clk4_divide_by => 5,
clk4_duty_cycle => 50,
clk4_multiply_by => 13,
clk4_phase_shift => "0",
compensate_clock => "CLK1",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_USED",
port_phasedone => "PORT_USED",
port_phasestep => "PORT_USED",
port_phaseupdown => "PORT_USED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
vco_frequency_control => "MANUAL_PHASE",
vco_phase_shift_step => 96,
width_clock => 5,
width_phasecounterselect => 3
)
PORT MAP (
areset => areset,
inclk => sub_wire9,
phasecounterselect => phasecounterselect,
phasestep => phasestep,
phaseupdown => phaseupdown,
scanclk => scanclk,
clk => sub_wire0,
locked => sub_wire6,
phasedone => sub_wire7
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "65.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "130.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "130.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "130.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "130.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
-- Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "96.00000000"
-- Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "65.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "130.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "130.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "130.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "130.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-90.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "13"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "13"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "13"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1923"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "13"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "13"
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
-- Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "96"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_PHASECOUNTERSELECT NUMERIC "3"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: USED_PORT: phasecounterselect 0 0 3 0 INPUT GND "phasecounterselect[2..0]"
-- Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
-- Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
-- Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: @phasecounterselect 0 0 3 0 phasecounterselect 0 0 3 0
-- Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
-- Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.v TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_inst.v FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_bb.v FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_wave*.jpg FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memphy_alt_mem_phy_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memphy_alt_mem_phy_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memphy_alt_mem_phy_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memphy_alt_mem_phy_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memphy_alt_mem_phy_pll_inst.vhd FALSE
| gpl-3.0 | 4fd9d0a5b44cb091b00fde05bc43cb4e | 0.702235 | 3.243276 | false | false | false | false |
chiggs/nvc | test/parse/expr.vhd | 4 | 402 | architecture a of e is
begin
process is
begin
x := not y;
x := abs y;
x := y ** z;
x := f(4).z;
x := y sll 1;
x := y srl 1;
x := y sla 1;
x := y sra 1;
x := y rol 1;
x := y ror 1;
x := work.foo."and"(1, 2);
x(y'range) := y;
x := (1 => 1, x'range => 2);
end process;
end architecture;
| gpl-3.0 | 29a322f773096bb76483a39672b122be | 0.363184 | 3.116279 | false | false | false | false |
ringof/radiofist_audio | ipcore_dir/dcm_6/simulation/dcm_6_tb.vhd | 1 | 6,432 | -- file: dcm_6_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity dcm_6_tb is
end dcm_6_tb;
architecture test of dcm_6_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component dcm_6_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : dcm_6_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET);
-- Freq Check
end test;
| mit | 9c1729e09a4bc77837eda09fa2253d2f | 0.631374 | 4.251157 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/c1541_timing.vhd | 1 | 3,201 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity c1541_timing is
port (
clock : in std_logic;
reset : in std_logic;
two_MHz_mode : in std_logic := '0';
tick_4MHz : in std_logic;
mem_busy : in std_logic := '0';
use_c64_reset : in std_logic;
c64_reset_n : in std_logic;
iec_reset_n : in std_logic;
iec_reset_o : out std_logic;
power : in std_logic;
drive_stop : in std_logic;
cia_rising : out std_logic;
cpu_clock_en : out std_logic );
end c1541_timing;
architecture Gideon of c1541_timing is
signal pre_cnt : unsigned(1 downto 0) := "00";
signal cpu_clock_en_i : std_logic := '0';
signal iec_reset_sh : std_logic_vector(0 to 2) := "000";
signal c64_reset_sh : std_logic_vector(0 to 2) := "000";
signal behind : unsigned(3 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
cpu_clock_en_i <= '0';
cia_rising <= '0';
if drive_stop='0' and power='1' then
if tick_4MHz = '1' then
case pre_cnt is
when "00" =>
pre_cnt <= "01";
when "01" =>
cia_rising <= '1';
if behind = 0 then
if two_MHz_mode = '1' then
pre_cnt <= "11";
else
pre_cnt <= "10";
end if;
else
behind <= behind - 1;
pre_cnt <= "11";
end if;
when "10" =>
pre_cnt <= "11";
when others => -- 11
if mem_busy = '0' then
cpu_clock_en_i <= '1';
if two_MHz_mode = '1' then
pre_cnt <= "01";
else
pre_cnt <= "00";
end if;
elsif signed(behind) /= -1 then
behind <= behind + 1;
end if;
end case;
end if;
end if;
if cpu_clock_en_i = '1' then
iec_reset_sh(0) <= not iec_reset_n;
iec_reset_sh(1 to 2) <= iec_reset_sh(0 to 1);
c64_reset_sh(0) <= use_c64_reset and not c64_reset_n;
c64_reset_sh(1 to 2) <= c64_reset_sh(0 to 1);
end if;
if reset='1' then
pre_cnt <= (others => '0');
behind <= (others => '0');
end if;
end if;
end process;
cpu_clock_en <= cpu_clock_en_i;
iec_reset_o <= '1' when (iec_reset_sh="111") or (c64_reset_sh="111") else '0';
end Gideon;
| gpl-3.0 | a57d96b73ed743facf99bd4d13e56ee5 | 0.368322 | 3.996255 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/cart_slot_pkg.vhd | 1 | 3,128 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cart_slot_pkg is
constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
constant c_cart_cartridge_active : unsigned(3 downto 0) := X"6";
constant c_cart_kernal_enable : unsigned(3 downto 0) := X"7";
constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
constant c_cart_timing : unsigned(3 downto 0) := X"B";
constant c_cart_phi2_recover : unsigned(3 downto 0) := X"C";
constant c_cart_serve_control : unsigned(3 downto 0) := X"D";
constant c_cart_sampler_enable : unsigned(3 downto 0) := X"E";
constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
type t_cart_control is record
c64_reset : std_logic;
c64_nmi : std_logic;
c64_ultimax : std_logic;
c64_stop : std_logic;
c64_stop_mode : std_logic_vector(1 downto 0);
cartridge_type : std_logic_vector(4 downto 0);
cartridge_variant : std_logic_vector(2 downto 0);
cartridge_kill : std_logic;
cartridge_force : std_logic;
kernal_enable : std_logic;
kernal_16k : std_logic;
reu_enable : std_logic;
reu_size : std_logic_vector(2 downto 0);
sampler_enable : std_logic;
swap_buttons : std_logic;
timing_addr_valid : unsigned(2 downto 0);
phi2_edge_recover : std_logic;
serve_while_stopped : std_logic;
end record;
type t_cart_status is record
c64_stopped : std_logic;
clock_detect : std_logic;
cart_active : std_logic;
c64_vcc : std_logic;
exrom : std_logic;
game : std_logic;
nmi : std_logic;
reset_in : std_logic;
end record;
constant c_cart_control_init : t_cart_control := (
c64_nmi => '0',
c64_reset => '0',
c64_ultimax => '0',
c64_stop => '0',
c64_stop_mode => "00",
cartridge_type => "00000",
cartridge_variant => "000",
cartridge_kill => '0',
cartridge_force=> '0',
kernal_enable => '0',
kernal_16k => '0',
reu_enable => '0',
reu_size => "111",
sampler_enable => '0',
timing_addr_valid => "100",
phi2_edge_recover => '1',
swap_buttons => '1',
serve_while_stopped => '0' );
end cart_slot_pkg;
| gpl-3.0 | 63b27d117cb7b140b76c92e6214aa072 | 0.52046 | 3.231405 | false | false | false | false |
xiadz/oscilloscope | src/vga_controller_1280_1024.vhd | 1 | 5,061 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
--
-- Description:
-- o Entity generates impulses required for managing
-- vga port in 1280x1024@60hz mode
--
-- o It requires 108 Mhz input clock
--
-- o It generates vblank signal. Whenever it's active,
-- vga color output should be set to "00000000" (all black).
-- It indicates an off-the-screen position.
--
-- o Sync pulses schema:
--
-- timing diagram for the horizontal synch signal (HS)
-- 0 1328 1440 1680 (pixels)
-- -------------------------|______|-------------------
-- timing diagram for the vertical synch signal (VS)
-- 0 1025 1028 1066 (lines)
-- -----------------------------------|______|---------
--
--
--
-- o For "next entities" (video signal generators), it generates signals line_change
-- and page_change. They are set to '1' for one clock cycle just before
-- there's a change in (appropriately) current line or current page.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga_controller_1280_1024 is
port (
nrst : in std_logic;
clk108 : in std_logic;
hsync : out std_logic;
vsync : out std_logic;
vblank : out std_logic;
line_change : out std_logic;
page_change : out std_logic;
column : out integer range 0 to 1279;
column_change : out std_logic
);
end vga_controller_1280_1024;
architecture behavioral of vga_controller_1280_1024 is
constant HFrontPorch : integer := 1280;
constant HSyncPulse : integer := 1328;
constant HBackPorch : integer := 1440;
constant HTotal : integer := 1688;
constant VFrontPorch : integer := 1024;
constant VSyncPulse : integer := 1025;
constant VBackPorch : integer := 1028;
constant VTotal : integer := 1066;
signal hcount: integer range 0 to 1687 := 0;
signal vcount: integer range 0 to 1065 := 0;
signal next_hcount: integer range 0 to 1687;
signal next_vcount: integer range 0 to 1065;
signal internal_column : integer range 0 to 1279;
signal next_column : integer range 0 to 1279;
signal next_column_change : std_logic;
begin
-- Generating next_hcount.
next_hcount <= hcount + 1 when hcount < (HTotal - 1) else 0;
-- Generating next_vcount.
process (vcount, next_hcount) is
begin
if next_hcount = 0 then
if vcount < (VTotal - 1) then
next_vcount <= vcount + 1;
else
next_vcount <= 0;
end if;
else
next_vcount <= vcount;
end if;
end process;
-- Generating next_column and next_column_change.
process (next_hcount, internal_column, next_column) is
begin
if (next_hcount >= 1280) then
next_column <= 1279;
else
next_column <= next_hcount;
end if;
if next_column /= internal_column then
next_column_change <= '1';
else
next_column_change <= '0';
end if;
end process;
column <= internal_column;
-- Generating sync pulses and line_change, page_change signals.
process (nrst, clk108) is
begin
if nrst = '0' then
line_change <= '0';
page_change <= '0';
hsync <= '0';
vsync <= '0';
vblank <= '0';
internal_column <= 0;
column_change <= '0';
elsif rising_edge (clk108) then
if vcount /= next_vcount then
line_change <= '1';
else
line_change <= '0';
end if;
if vcount /= next_vcount and next_vcount = 0 then
page_change <= '1';
else
page_change <= '0';
end if;
hcount <= next_hcount;
if (next_hcount >= 1280) then
internal_column <= 1279;
else
internal_column <= next_hcount;
end if;
column_change <= next_column_change;
vcount <= next_vcount;
if next_hcount < HFrontPorch and next_vcount < VFrontPorch then
vblank <= '0';
else
vblank <= '1';
end if;
if next_hcount >= HSyncPulse and next_hcount < HBackPorch then
hsync <= '1';
else
hsync <= '0';
end if;
if next_vcount >= VSyncPulse and next_vcount < VBackPorch then
vsync <= '1';
else
vsync <= '0';
end if;
end if;
end process;
end architecture behavioral;
| mit | 5f9bff8fa4cc5ab01127eebec03a142e | 0.495159 | 4.51875 | false | false | false | false |
chiggs/nvc | test/sem/scope.vhd | 1 | 6,484 | package pack1 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
package pack2 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
use work.pack1;
use work.pack2;
entity no_use_clause is
port (
a : in pack1.my_int1;
b : out pack2.my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of no_use_clause is
type my_int1 is range 10 to 50;
begin
process is
begin
-- Should fail as types have same name but from different packages
b <= a;
end process;
process is
variable v : pack2.my_int1;
begin
b <= v; -- OK
end process;
process is
variable v : my_int1;
begin
-- Should fail as local my_int1 distinct from pack1.my_int1
v := a;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack1.all;
entity foo is
generic ( g : my_int1 );
port ( p : in my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of foo is
-- Architecture decls exist in same scope as entity so this should
-- generate an error
signal g : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture b of foo is
-- Should also generate an error
signal p : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture c of foo is
begin
-- This is OK as processes define a new scope
process is
variable p : my_int1;
variable g : my_int1;
begin
g := 6;
p := 2;
wait for 1 ns;
end process;
end architecture;
-------------------------------------------------------------------------------
entity overload is
port (
SI: in bit;
SO: out bit
);
end ;
architecture behave of overload is
begin
foo_inst:
SO <= SI;
end behave;
-------------------------------------------------------------------------------
use work.all;
entity no_use_clause is
port (
a : in pack1.my_int1; -- OK
b : out my_int1 ); -- Error
end entity;
-------------------------------------------------------------------------------
package pack3 is
type my_enum is (E1, E2, E3);
end package;
-------------------------------------------------------------------------------
use work.pack3.all;
package pack4 is
type my_enum_array is array (integer range <>) of my_enum;
end package;
-------------------------------------------------------------------------------
use work.pack4.all;
architecture a of foo is
signal x : my_enum_array(1 to 3); -- OK
signal y : my_enum_array(1 to 3) := (others => E1);
-- Error: E1 not visible
begin
end architecture;
-------------------------------------------------------------------------------
package pack5 is
function func1(x : integer) return boolean;
function func2(x : integer) return boolean;
function "and"(x, y : integer) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack5.func1;
architecture a2 of foo is
begin
process is
begin
assert func1(4); -- OK
assert func2(5); -- Error
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack5.not_here; -- Error
architecture a3 of foo is
begin
end architecture;
-------------------------------------------------------------------------------
entity bar is
end entity;
architecture a4 of bar is
begin
process is
use work.pack1.all;
variable x : my_int1; -- OK
begin
x := 5;
end process;
process is
variable x : my_int1; -- Error
begin
end process;
b: block is
use work.pack1;
signal x : pack1.my_int1; -- OK
begin
end block;
end architecture;
-------------------------------------------------------------------------------
use work.pack5."and";
architecture a5 of bar is
begin
process is
begin
assert 1 and 2; -- OK
assert work.pack5."and"(1, 2); -- OK
assert pack5."and"(1, 2); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
package pack6 is
component bar is
end component;
end package;
-------------------------------------------------------------------------------
use work.pack6.all;
architecture a6 of bar is
begin
process is
begin
report bar'path_name; -- OK (references entity)
end process;
end architecture;
-------------------------------------------------------------------------------
use foo.bar.all; -- Error
architecture a7 of bar is
begin
end architecture;
-------------------------------------------------------------------------------
package pack7 is
function foo(x : in integer) return boolean;
function foo(y : in real) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack7.foo;
architecture issue62 of bar is
begin
process is
begin
assert foo(integer'(1)); -- OK
assert foo(real'(1.6)); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
use work.all;
use work.pack1.all;
architecture issue63 of bar is
signal x : my_int1; -- OK
begin
end architecture;
-------------------------------------------------------------------------------
package pack8 is
function min(x, y : in integer) return integer;
end package;
-------------------------------------------------------------------------------
use work.pack8.all; -- OK
architecture unit_decl_crash of bar is
begin
process is
variable x : integer := min(1, 2); -- OK
begin
end process;
end architecture;
| gpl-3.0 | e6c2994e97c173d25be5e481060480f4 | 0.404997 | 4.849663 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_sim/tb_ulpi_bus.vhd | 2 | 3,047 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_bus is
end entity;
architecture tb of tb_ulpi_bus is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.usb1_ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_bfm: entity work.usb1_ulpi_phy_bfm
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
p_test: process
procedure tx_packet(invec : t_std_logic_8_vector; last : boolean) is
begin
wait until clock='1';
tx_start <= '1';
for i in invec'range loop
tx_data <= invec(i);
tx_valid <= '1';
if i = invec'right and last then
tx_last <= '1';
else
tx_last <= '0';
end if;
wait until clock='1';
tx_start <= '0';
while tx_next = '0' loop
wait until clock='1';
end loop;
end loop;
tx_valid <= '0';
end procedure;
begin
wait for 500 ns;
tx_packet((X"40", X"01", X"02", X"03", X"04"), true);
wait for 300 ns;
tx_packet((X"81", X"15"), true);
wait for 300 ns;
tx_packet((0 => X"C2"), false);
wait;
end process;
end tb;
| gpl-3.0 | 087231aff8ce25555b457dd11e9c9063 | 0.460125 | 3.675513 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/mem_remain_counter.vhd | 2 | 1,120 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_remain_counter is
port (
clock : in std_logic;
load_value : in unsigned(7 downto 0);
do_load : in std_logic;
do_dec : in std_logic;
remain : out unsigned(7 downto 0);
remain_is_1 : out std_logic;
remain_is_0 : out std_logic );
end mem_remain_counter;
architecture test of mem_remain_counter is
signal rem_i : unsigned(remain'range) := (others => '0');
signal small : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if do_load='1' then
rem_i <= load_value;
elsif do_dec='1' then
rem_i <= rem_i - 1;
end if;
end if;
end process;
remain <= rem_i;
small <= '1' when (rem_i(rem_i'high downto 2) = 0) else '0';
remain_is_0 <= small when (rem_i(1 downto 0) = 0) else '0';
remain_is_1 <= small when (rem_i(1 downto 0) = 1) else '0';
-- remain_less4 <= small;
end architecture;
| gpl-3.0 | 38eaf60c5212ad9c09d944c532c77727 | 0.526786 | 3.236994 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_source/mblite_wrapper.vhd | 1 | 3,682 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: mblite_sdram
-- Date:2015-01-02
-- Author: Gideon
-- Description: mblite processor with sdram interface - test module
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
library mblite;
use mblite.core_Pkg.all;
entity mblite_wrapper is
generic (
g_icache : boolean := true;
g_dcache : boolean := true;
g_tag_i : std_logic_vector(7 downto 0) := X"20";
g_tag_d : std_logic_vector(7 downto 0) := X"21" );
port (
clock : in std_logic;
reset : in std_logic;
mb_reset : in std_logic;
irq_i : in std_logic := '0';
irq_o : out std_logic;
disable_i : in std_logic := '0';
disable_d : in std_logic := '0';
invalidate : in std_logic := '0';
inv_addr : in std_logic_vector(31 downto 0);
io_req : out t_io_req;
io_resp : in t_io_resp;
io_busy : out std_logic;
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32 );
end entity;
architecture arch of mblite_wrapper is
signal reset_i : std_logic;
signal dmem_o : dmem_out_type;
signal dmem_i : dmem_in_type;
signal imem_o : dmem_out_type;
signal imem_i : dmem_in_type;
signal dmem_req : t_mem_req_32;
signal dmem_resp : t_mem_resp_32;
signal imem_req : t_mem_req_32;
signal imem_resp : t_mem_resp_32;
begin
reset_i <= mb_reset or reset when rising_edge(clock);
i_proc: entity mblite.cached_mblite
generic map (
g_icache => g_icache,
g_dcache => g_dcache )
port map (
clock => clock,
reset => reset_i,
disable_i => disable_i,
disable_d => disable_d,
invalidate => invalidate,
inv_addr => inv_addr,
dmem_o => dmem_o,
dmem_i => dmem_i,
imem_o => imem_o,
imem_i => imem_i,
irq_i => irq_i,
irq_o => irq_o );
i_imem: entity work.dmem_splitter
generic map (
g_tag => g_tag_i,
g_support_io => false )
port map (
clock => clock,
reset => reset_i,
dmem_i => imem_i,
dmem_o => imem_o,
mem_req => imem_req,
mem_resp => imem_resp,
io_req => open,
io_resp => c_io_resp_init );
i_dmem: entity work.dmem_splitter
generic map (
g_tag => g_tag_d,
g_support_io => true )
port map (
clock => clock,
reset => reset_i,
dmem_i => dmem_i,
dmem_o => dmem_o,
mem_req => dmem_req,
mem_resp => dmem_resp,
io_busy => io_busy,
io_req => io_req,
io_resp => io_resp );
i_arb: entity work.mem_bus_arbiter_pri_32
generic map (
g_registered => false,
g_ports => 2 )
port map (
clock => clock,
reset => reset,
reqs(0) => imem_req,
reqs(1) => dmem_req,
resps(0) => imem_resp,
resps(1) => dmem_resp,
req => mem_req,
resp => mem_resp );
end arch;
| gpl-3.0 | 76785d559dd4457ff2b975c7cfc11a95 | 0.448126 | 3.480151 | false | false | false | false |
xiadz/oscilloscope | src/tests/test_clock_divider.vhd | 1 | 2,371 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:15:48 05/28/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_clock_divider.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: divider
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_clock_divider IS
END test_clock_divider;
ARCHITECTURE behavior OF test_clock_divider IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT divider
GENERIC (n: natural range 1 to 2147483647 := 5);
PORT(
clk_in : IN std_logic;
nrst : IN std_logic;
clk_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_in : std_logic := '0';
signal nrst : std_logic := '0';
--Output
signal clk_out : std_logic;
-- Clock period definitions
constant clk_in_period : time := 10 ns;
constant c : character := character'val(0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: divider PORT MAP (
clk_in => clk_in,
nrst => nrst,
clk_out => clk_out
);
-- Clock process definitions
clk_in_process :process
begin
clk_in <= '0';
wait for clk_in_period/2;
clk_in <= '1';
wait for clk_in_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
nrst <= '0';
wait for 100 ns;
nrst <= '1';
wait for clk_in_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | 30710e89225ed00ffed2aa4cc5b1a6aa | 0.585407 | 3.958264 | false | true | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/tb_floppy_stream.vhd | 1 | 5,533 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : tb_floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_flat_memory_model_pkg.all;
entity tb_floppy_stream is
end tb_floppy_stream;
architecture tb of tb_floppy_stream is
signal clock : std_logic := '0';
signal reset : std_logic;
signal mem_rdata : std_logic_vector(7 downto 0) := X"01";
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic;
signal step : unsigned(1 downto 0) := "00";
signal bit_time : unsigned(9 downto 0) := to_unsigned(399, 10); -- 335 for fastest
--signal bit_time : unsigned(9 downto 0) := to_unsigned(335, 10);
signal track : unsigned(6 downto 0);
--signal rate_ctrl : std_logic_vector(1 downto 0) := "11"; -- fastest
signal rate_ctrl : std_logic_vector(1 downto 0) := "00"; -- slowest
signal byte_ready : std_logic;
signal sync : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal write_data : std_logic_vector(7 downto 0) := X"55";
signal read_latched : std_logic_vector(7 downto 0) := (others => '-');
signal do_read : std_logic;
signal do_write : std_logic;
signal do_advance : std_logic;
signal tick_16MHz : std_logic_vector(24 downto 0) := "0010010010010010010010010";
type t_buffer_array is array (natural range <>) of std_logic_vector(7 downto 0);
shared variable my_buffer : t_buffer_array(0 to 15) := (others => X"FF");
begin
clock <= not clock after 10 ns; -- 50 MHz
reset <= '1', '0' after 400 ns;
tick_16MHz <= tick_16MHz(0) & tick_16MHz(tick_16MHz'high downto 1) when rising_edge(clock);
mut: entity work.floppy_stream
port map (
clock => clock,
reset => reset,
tick_16MHz => tick_16MHz(0),
mem_rdata => mem_rdata,
floppy_inserted => '1',
do_read => do_read,
do_write => do_write,
do_advance => do_advance,
track => track,
motor_on => motor_on,
stepper_en => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => std_logic_vector(step),
byte_ready => byte_ready,
bit_time => bit_time,
rate_ctrl => rate_ctrl,
read_data => read_data );
test: process
begin
motor_on <= '1';
mode <= '1';
write_prot_n <= '1';
wait for 600 us;
mode <= '0'; -- switch to write
wait;
end process;
process(byte_ready)
begin
if falling_edge(byte_ready) then
read_latched <= read_data;
end if;
end process;
memory: process(clock)
variable h : h_mem_object;
variable h_initialized : boolean := false;
variable address : unsigned(31 downto 0) := X"000002AE";
begin
if rising_edge(clock) then
if not h_initialized then
register_mem_model("my_memory", "my memory", h);
load_memory("../data/720_s0.g64", 1, X"00000000");
h_initialized := true;
write_memory_32(h, X"00000400", X"00000000");
write_memory_32(h, X"00000404", X"00000000");
write_memory_32(h, X"00000408", X"00000000");
write_memory_32(h, X"0000040C", X"00000000");
write_memory_32(h, X"00000410", X"00000000");
write_memory_32(h, X"00000414", X"00000000");
write_memory_32(h, X"00000418", X"00000000");
write_memory_32(h, X"0000041C", X"00000000");
write_memory_32(h, X"00000420", X"00000000");
end if;
if do_write = '1' then
write_memory_8(h, std_logic_vector(address), write_data);
address := address + 1;
elsif do_read = '1' then
mem_rdata <= read_memory_8(h, std_logic_vector(address));
address := address + 1;
elsif do_advance = '1' then
address := address + 1;
end if;
end if;
end process;
move: process
begin
wait for 2 us;
for i in 0 to 100 loop
step <= step + 1;
wait for 2 us;
end loop;
wait for 2 us;
for i in 0 to 100 loop
step <= step - 1;
wait for 2 us;
end loop;
end process;
end tb;
| gpl-3.0 | 8eae84763d7d5708a9d5a5b494e42e6f | 0.464667 | 4.089431 | false | false | false | false |
chiggs/nvc | test/parse/based.vhd | 3 | 326 | package p is
constant a : integer := 2#1101#;
constant b : integer := 3#20#;
constant c : integer := 8#7#;
constant d : integer := 10#1234#;
constant e : integer := 16#beef01#;
constant f : integer := 2#1_0#;
constant g : integer := 2:1_0:;
constant h : integer := 16#abababab#;
end package;
| gpl-3.0 | 52fb85bced6467716a2612af7b38b9ff | 0.576687 | 3.431579 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/cart_slot_registers.vhd | 1 | 6,073 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.cart_slot_pkg.all;
entity cart_slot_registers is
generic (
g_cartreset_init: std_logic := '0';
g_boot_stop : boolean := false;
g_kernal_repl : boolean := true;
g_ram_expansion : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_cart_control;
status : in t_cart_status );
end entity;
architecture rtl of cart_slot_registers is
signal control_i : t_cart_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
control_i.cartridge_kill <= '0';
control_i.cartridge_force <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
if io_req.data(2)='1' then
control_i.c64_reset <= '1';
elsif io_req.data(3)='1' then
control_i.c64_reset <= '0';
else
control_i.c64_ultimax <= io_req.data(1);
control_i.c64_nmi <= io_req.data(4);
end if;
when c_cart_c64_stop =>
control_i.c64_stop <= io_req.data(0);
when c_cart_c64_stop_mode =>
control_i.c64_stop_mode <= io_req.data(1 downto 0);
when c_cart_cartridge_type =>
control_i.cartridge_type <= io_req.data(4 downto 0);
control_i.cartridge_variant <= io_req.data(7 downto 5);
when c_cart_cartridge_kill =>
control_i.cartridge_kill <= io_req.data(0);
control_i.cartridge_force <= io_req.data(1);
when c_cart_kernal_enable =>
if g_kernal_repl then
control_i.kernal_enable <= io_req.data(0);
control_i.kernal_16k <= io_req.data(1);
end if;
when c_cart_reu_enable =>
control_i.reu_enable <= io_req.data(0);
when c_cart_reu_size =>
control_i.reu_size <= io_req.data(2 downto 0);
when c_cart_serve_control =>
control_i.serve_while_stopped <= io_req.data(0);
when c_cart_timing =>
control_i.timing_addr_valid <= unsigned(io_req.data(2 downto 0));
when c_cart_phi2_recover =>
control_i.phi2_edge_recover <= io_req.data(0);
when c_cart_swap_buttons =>
control_i.swap_buttons <= io_req.data(0);
when c_cart_sampler_enable =>
control_i.sampler_enable <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
io_resp.data(1) <= control_i.c64_ultimax;
io_resp.data(2) <= control_i.c64_reset;
io_resp.data(4) <= control_i.c64_nmi;
when c_cart_c64_stop =>
io_resp.data(0) <= control_i.c64_stop;
io_resp.data(1) <= status.c64_stopped;
when c_cart_c64_stop_mode =>
io_resp.data(1 downto 0) <= control_i.c64_stop_mode;
when c_cart_c64_clock_detect =>
io_resp.data(0) <= status.clock_detect;
io_resp.data(1) <= status.c64_vcc;
io_resp.data(2) <= status.exrom;
io_resp.data(3) <= status.game;
io_resp.data(4) <= status.reset_in;
io_resp.data(5) <= status.nmi;
when c_cart_cartridge_type =>
io_resp.data(4 downto 0) <= control_i.cartridge_type;
io_resp.data(7 downto 5) <= control_i.cartridge_variant;
when c_cart_cartridge_active =>
io_resp.data(0) <= status.cart_active;
when c_cart_kernal_enable =>
io_resp.data(0) <= control_i.kernal_enable;
io_resp.data(1) <= control_i.kernal_16k;
when c_cart_reu_enable =>
io_resp.data(0) <= control_i.reu_enable;
when c_cart_reu_size =>
io_resp.data(2 downto 0) <= control_i.reu_size;
when c_cart_serve_control =>
io_resp.data(0) <= control_i.serve_while_stopped;
when c_cart_sampler_enable =>
io_resp.data(0) <= control_i.sampler_enable;
when c_cart_timing =>
io_resp.data(2 downto 0) <= std_logic_vector(control_i.timing_addr_valid);
when c_cart_phi2_recover =>
io_resp.data(0) <= control_i.phi2_edge_recover;
when c_cart_swap_buttons =>
io_resp.data(0) <= control_i.swap_buttons;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_cart_control_init;
control_i.c64_reset <= g_cartreset_init;
if g_boot_stop then
control_i.c64_stop <= '1';
control_i.c64_stop_mode <= "10";
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 623dbc669697b38302acc7d1340615bb | 0.450025 | 3.632177 | false | false | false | false |
trondd/mkjpeg | design/huffman/DoubleFifo.vhd | 2 | 6,246 | -------------------------------------------------------------------------------
-- File Name : DoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : DoubleFifo
--
-- Content : DoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(7 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity DoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(7 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(7 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(7 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(7 downto 0);
signal fifo_data_in : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
data_out <= (others => '0');
fifo1_rd <= '0';
fifo2_rd <= '0';
fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
data_out <= fifo1_q;
fifo1_rd <= rd_req;
fifo_empty <= fifo1_empty;
else
data_out <= fifo2_q;
fifo2_rd <= rd_req;
fifo_empty <= fifo2_empty;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | 0d91b5501590d2d99fbe05af571ab719 | 0.263689 | 5.688525 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/memory/vhdl_source/dpram_sc.vhd | 2 | 3,164 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram_sc is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_global_init : std_logic_vector := X"0000";
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0');
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram_sc : entity is "yes";
end entity;
architecture xilinx of dpram_sc is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => g_global_init);
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
-----------------------------------------------------------------------
-- PORT A
-----------------------------------------------------------------------
p_port_a: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
if g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
if a_we = '1' then
ram(to_integer(a_address)) := a_wdata;
end if;
if not g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- PORT B
-----------------------------------------------------------------------
p_port_b: process(clock)
begin
if rising_edge(clock) then
if b_en = '1' then
if g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
end if;
if not g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 2c46e036e9472722ef6552b5313fc206 | 0.417509 | 4.109091 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/debug/vhdl_source/logic_analyzer_32.vhd | 1 | 6,075 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
entity logic_analyzer_32 is
generic (
g_big_endian : boolean;
g_timer_div : positive := 50 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(7 downto 0);
task : out std_logic_vector(3 downto 0);
---
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer_32;
architecture gideon of logic_analyzer_32 is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(15 downto 0);
signal ev_data_d : std_logic_vector(15 downto 0);
signal ev_wdata : std_logic_vector(31 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
type t_state is (idle, writing);
signal state : t_state;
signal sub, task_i : std_logic_vector(3 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= sub & task_i & ev_data;
case state is
when idle =>
if ev_dav='1' or ev_tick='1' then
if (ev_data_c /= ev_data_d) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
ev_data_d <= ev_data_c;
stamp <= (others => '0');
if enable_log = '1' then
state <= writing;
end if;
end if;
end if;
when writing =>
mem_req.data <= byte_swap(ev_wdata, g_big_endian);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 4;
mem_req.request <= '0';
state <= idle;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
if g_big_endian then
case io_req.address(2 downto 0) is
when "011" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "000" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= X"0" & sub;
when "101" =>
io_resp.data <= X"0" & task_i;
when others =>
null;
end case;
else
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= X"0" & sub;
when "101" =>
io_resp.data <= X"0" & task_i;
when others =>
null;
end case;
end if;
elsif io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "111" =>
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
when "110" =>
enable_log <= '0';
when "101" =>
task_i <= io_req.data(3 downto 0);
when "100" =>
sub <= io_req.data(3 downto 0);
when others =>
null;
end case;
end if;
if reset='1' then
state <= idle;
sub <= X"0";
task_i <= X"0";
enable_log <= '0';
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.byte_en <= "1111";
task <= task_i;
end gideon;
| gpl-3.0 | e50f615a4f91621d84dc9097e0c90b37 | 0.382716 | 4.068989 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/debug/vhdl_source/usb_trace_adapter.vhd | 1 | 1,866 | --------------------------------------------------------------------------------
-- Entity: usb_trace_adapter
-- Date:2018-07-15
-- Author: Gideon
--
-- Description: Encodes USB data into 1480A compatible data format
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_trace_adapter is
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_cmd : in std_logic;
rx_ourdata : in std_logic;
rx_store : in std_logic;
tx_first : in std_logic;
usb_data : out std_logic_vector(7 downto 0);
usb_valid : out std_logic;
usb_rxcmd : out std_logic );
end entity;
architecture arch of usb_trace_adapter is
signal tx_latch : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if tx_first = '1' and tx_latch = '0' then
tx_latch <= '1';
elsif rx_ourdata = '1' then
tx_latch <= '0';
end if;
-- What is what?
-- Case 1: We are sending: first byte is PID, we need to translate it
usb_rxcmd <= '0';
usb_data <= rx_data;
if rx_ourdata = '1' then
usb_valid <= '1';
if tx_latch = '1' then
usb_data <= not(rx_data(3 downto 0)) & rx_data(3 downto 0);
end if;
elsif rx_cmd = '1' then
usb_rxcmd <= '1';
usb_valid <= '1';
elsif rx_store = '1' then
usb_valid <= '1';
end if;
if reset = '1' then
tx_latch <= '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 59b38e3a9da75ae640b6d481e8f7dbe2 | 0.446409 | 3.871369 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/harness_mm.vhd | 1 | 4,545 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_mm is
port (
io_irq : out std_logic );
end entity;
architecture harness of harness_mm is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal iec_atn : std_logic;
signal iec_atn_o : std_logic;
signal iec_atn_i : std_logic;
signal iec_data : std_logic;
signal iec_data_o : std_logic;
signal iec_data_i : std_logic;
signal iec_clk : std_logic;
signal iec_clk_o : std_logic;
signal iec_clk_i : std_logic;
signal iec_fclk_o : std_logic;
signal iec_fclk_i : std_logic;
signal iec_fclk : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal act_led_n : std_logic;
signal audio_sample : signed(12 downto 0);
signal tick_1kHz : std_logic := '0';
signal tick_4MHz : std_logic := '0';
signal tick_16MHz : std_logic := '0';
begin
clock <= not clock after 16 ns;
reset <= '1', '0' after 1000 ns;
process
begin
wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '1';
end process;
process
begin
tick_1kHz <= '0';
wait for 1 ms;
wait until clock = '1';
tick_1kHz <= '1';
wait until clock = '1';
end process;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_drive: entity work.mm_drive
generic map (
g_big_endian => false,
g_audio => false,
g_audio_base => X"0010000",
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
-- timing
tick_1kHz => tick_1kHz,
tick_4MHz => tick_4MHz,
tick_16MHz => tick_16MHz,
-- slave port on io bus
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq,
-- master port on memory bus
mem_req => mem_req,
mem_resp => mem_resp,
-- serial bus pins
atn_o => iec_atn_o, -- open drain
atn_i => iec_atn_i,
clk_o => iec_clk_o, -- open drain
clk_i => iec_clk_i,
data_o => iec_data_o, -- open drain
data_i => iec_data_i,
fast_clk_o => iec_fclk_o, -- open drain
fast_clk_i => iec_fclk_i,
-- LED
act_led_n => act_led_n,
-- audio out
audio_sample => audio_sample );
iec_atn <= '0' when iec_atn_o='0' else 'Z';
iec_atn_i <= '0' when iec_atn='0' else '1';
iec_clk <= '0' when iec_clk_o='0' else 'Z';
iec_clk_i <= '0' when iec_clk='0' else '1';
iec_data <= '0' when iec_data_o='0' else 'Z';
iec_data_i <= '0' when iec_data='0' else '1';
iec_fclk <= '0' when iec_fclk_o='0' else 'Z';
iec_fclk_i <= '0' when iec_fclk='0' else '1';
i_memory: entity work.mem_bus_32_slave_bfm
generic map(
g_name => "dram",
g_latency => 2
)
port map(
clock => clock,
req => mem_req,
resp => mem_resp
);
iec_bfm: entity work.iec_bus_bfm
generic map ("iec_bfm")
port map (
iec_clock => iec_clk,
iec_data => iec_data,
iec_atn => iec_atn,
iec_srq => iec_fclk );
end harness;
| gpl-3.0 | 742f6e9ecf73f17ca2417d1d6e59b57c | 0.463366 | 3.274496 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/command_interface/vhdl_source/command_interface.vhd | 1 | 3,435 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
entity command_interface is
port (
clock : in std_logic;
reset : in std_logic;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
write_ff00 : in std_logic := '0';
-- io interface for local cpu
io_req : in t_io_req; -- we get an 8K range
io_resp : out t_io_resp;
io_irq : out std_logic );
end entity;
architecture gideon of command_interface is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_ram : t_io_req;
signal io_resp_ram : t_io_resp;
signal io_ram_en : std_logic;
signal io_ram_rdata : std_logic_vector(7 downto 0);
signal io_ram_ack : std_logic;
signal b_address : unsigned(10 downto 0);
signal b_rdata : std_logic_vector(7 downto 0);
signal b_wdata : std_logic_vector(7 downto 0);
signal b_en : std_logic;
signal b_we : std_logic;
begin
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_ram,
resps(0) => io_resp_regs,
resps(1) => io_resp_ram );
process(clock)
begin
if rising_edge(clock) then
io_ram_ack <= io_ram_en;
end if;
end process;
io_ram_en <= io_req_ram.read or io_req_ram.write;
io_resp_ram.data <= X"00" when io_ram_ack='0' else io_ram_rdata;
io_resp_ram.ack <= io_ram_ack;
i_ram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => 11,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => io_req_ram.address(10 downto 0),
a_rdata => io_ram_rdata,
a_wdata => io_req_ram.data,
a_en => io_ram_en,
a_we => io_req_ram.write,
b_clock => clock,
b_address => b_address,
b_rdata => b_rdata,
b_wdata => b_wdata,
b_en => b_en,
b_we => b_we );
i_protocol: entity work.command_protocol
port map (
clock => clock,
reset => reset,
-- Local CPU side
io_req => io_req_regs,
io_resp => io_resp_regs,
io_irq => io_irq,
-- slot
slot_req => slot_req,
slot_resp => slot_resp,
freeze => freeze,
write_ff00 => write_ff00,
-- memory
address => b_address,
rdata => b_rdata,
wdata => b_wdata,
en => b_en,
we => b_we );
end architecture;
| gpl-3.0 | 070c989b9b1d7ba181e57bffb1c87e5a | 0.454731 | 3.441884 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/ultimate_fpga/vhdl_source/s3a_clockgen.vhd | 2 | 4,953 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3a_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
soft_reset : in std_logic := '0';
sys_clock : out std_logic; -- 50 MHz
sys_reset : out std_logic;
sys_clock_2x : out std_logic;
drive_stop : in std_logic := '0';
drv_clock_en : out std_logic; -- 1/12.5 (4 MHz)
cpu_clock_en : out std_logic; -- 1/50 (1 MHz)
iec_reset_n : in std_logic := '1';
iec_reset_o : out std_logic );
end s3a_clockgen;
architecture Gideon of s3a_clockgen is
signal clk_in_buf : std_logic;
signal sys_clk_buf : std_logic;
signal reset_dcm : std_logic;
signal reset_cnt : integer range 0 to 63 := 0;
signal dcm1_locked : std_logic := '1';
signal sys_clk_i : std_logic := '0';
signal sys_reset_i : std_logic := '1';
signal sys_reset_p : std_logic := '1';
signal div_cnt : std_logic_vector(3 downto 0) := "0000";
signal pre_cnt : std_logic_vector(1 downto 0) := "00";
signal cpu_cke_i : std_logic := '0';
signal toggle : std_logic := '0';
signal reset_c : std_logic;
signal soft_reset_r : std_logic := '0';
signal reset_out : std_logic := '1';
constant c_sys_reset_ticks : integer := 63;
signal sysrst_cnt : integer range 0 to c_sys_reset_ticks;
signal iec_reset_sh : std_logic_vector(0 to 2) := "000";
-- signal reset_sample_cnt : integer range 0 to 127 := 0;
-- signal reset_float : std_logic := '1';
attribute register_duplication : string;
attribute register_duplication of sys_reset_i : signal is "no";
attribute register_duplication of soft_reset_r : signal is "no";
signal clk_0_pre : std_logic;
signal clk_2x_pre : std_logic;
begin
dcm_lock <= dcm1_locked;
bufg_in : BUFG port map (I => clk_50, O => clk_in_buf);
process(clk_in_buf)
begin
if rising_edge(clk_in_buf) then
if reset_cnt = 63 then
reset_dcm <= '0';
else
reset_cnt <= reset_cnt + 1;
reset_dcm <= '1';
end if;
end if;
if reset_in='1' then
reset_dcm <= '1';
reset_cnt <= 0;
end if;
end process;
dcm_shft: DCM
generic map
(
CLKIN_PERIOD => 20.0,
-- CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
-- PHASE_SHIFT => -20,
STARTUP_WAIT => true
)
port map
(
CLKIN => clk_in_buf,
CLKFB => sys_clk_buf,
CLK0 => clk_0_pre,
CLK2X => clk_2x_pre,
LOCKED => dcm1_locked,
RST => reset_dcm
);
bufg_sys: BUFG port map (I => clk_0_pre, O => sys_clk_buf);
bufg_sys2x: BUFG port map (I => clk_2x_pre, O => sys_clock_2x);
sys_clk_i <= sys_clk_buf;
sys_clock <= sys_clk_buf;
process(sys_clk_i, dcm1_locked)
begin
if rising_edge(sys_clk_i) then
soft_reset_r <= soft_reset;
sys_reset_p <= sys_reset_i;
if soft_reset_r = '1' then
sysrst_cnt <= 0;
sys_reset_i <= '1';
elsif sysrst_cnt = c_sys_reset_ticks then
sys_reset_i <= '0';
else
sysrst_cnt <= sysrst_cnt + 1;
end if;
drv_clock_en <= '0';
cpu_cke_i <= '0';
if drive_stop='0' then
if (div_cnt = X"B" and toggle='0') or
(div_cnt = X"C" and toggle='1') then
div_cnt <= X"0";
drv_clock_en <= '1';
toggle <= not toggle;
pre_cnt <= pre_cnt + 1;
if pre_cnt = "11" then
cpu_cke_i <= '1';
else
cpu_cke_i <= '0';
end if;
else
div_cnt <= div_cnt + 1;
end if;
end if;
if cpu_cke_i = '1' then
iec_reset_sh(0) <= not iec_reset_n;
iec_reset_sh(1 to 2) <= iec_reset_sh(0 to 1);
end if;
if sys_reset_p='1' then
toggle <= '0';
pre_cnt <= (others => '0');
div_cnt <= (others => '0');
end if;
end if;
if dcm1_locked='0' then
sysrst_cnt <= 0;
sys_reset_i <= '1';
sys_reset_p <= '1';
end if;
end process;
sys_reset <= sys_reset_p;
cpu_clock_en <= cpu_cke_i;
iec_reset_o <= '1' when iec_reset_sh="111" else '0';
end Gideon;
| gpl-3.0 | ac786edcbe70c05843a3f499489ad2b3 | 0.469009 | 3.197547 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_source/usb1_pkg.vhd | 2 | 10,575 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package usb1_pkg is
type t_transaction_type is ( control, bulk, interrupt, isochronous );
type t_transaction_state is ( none, busy, done, error );
type t_pipe_state is ( invalid, initialized, stalled, aborted );
type t_direction is ( dir_in, dir_out );
type t_transfer_mode is ( direct, use_preamble, use_split );
type t_pipe is record
state : t_pipe_state;
direction : t_direction;
device_address : std_logic_vector(6 downto 0);
device_endpoint : std_logic_vector(3 downto 0);
max_transfer : unsigned(10 downto 0); -- could be encoded in less (3) bits (only 2^x)
data_toggle : std_logic;
control : std_logic; -- '1' if this pipe is treated as a control pipe
timeout : std_logic;
--transfer_mode : t_transfer_mode;
end record; -- 18 bits now with encoded max transfer, otherwise 26
type t_transaction is record
transaction_type : t_transaction_type;
state : t_transaction_state;
pipe_pointer : unsigned(4 downto 0); -- 32 pipes enough?
transfer_length : unsigned(10 downto 0); -- max 2K
buffer_address : unsigned(10 downto 0); -- 2K buffer
link_to_next : std_logic; -- when '1', no other events will take place (such as sof)
end record; -- 32 bits now
function data_to_t_pipe(i: std_logic_vector(31 downto 0)) return t_pipe;
function t_pipe_to_data(i: t_pipe) return std_logic_vector;
function data_to_t_transaction(i: std_logic_vector(31 downto 0)) return t_transaction;
function t_transaction_to_data(i: t_transaction) return std_logic_vector;
constant c_pid_out : std_logic_vector(3 downto 0) := X"1"; -- token
constant c_pid_in : std_logic_vector(3 downto 0) := X"9"; -- token
constant c_pid_sof : std_logic_vector(3 downto 0) := X"5"; -- token
constant c_pid_setup : std_logic_vector(3 downto 0) := X"D"; -- token
constant c_pid_data0 : std_logic_vector(3 downto 0) := X"3"; -- data
constant c_pid_data1 : std_logic_vector(3 downto 0) := X"B"; -- data
constant c_pid_data2 : std_logic_vector(3 downto 0) := X"7"; -- data
constant c_pid_mdata : std_logic_vector(3 downto 0) := X"F"; -- data
constant c_pid_ack : std_logic_vector(3 downto 0) := X"2"; -- handshake
constant c_pid_nak : std_logic_vector(3 downto 0) := X"A"; -- handshake
constant c_pid_stall : std_logic_vector(3 downto 0) := X"E"; -- handshake
constant c_pid_nyet : std_logic_vector(3 downto 0) := X"6"; -- handshake
constant c_pid_pre : std_logic_vector(3 downto 0) := X"C"; -- token
constant c_pid_err : std_logic_vector(3 downto 0) := X"C"; -- handshake
constant c_pid_split : std_logic_vector(3 downto 0) := X"8"; -- token
constant c_pid_ping : std_logic_vector(3 downto 0) := X"4"; -- token
constant c_pid_reserved : std_logic_vector(3 downto 0) := X"0";
function is_token(i : std_logic_vector(3 downto 0)) return boolean;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean;
constant c_cmd_get_status : std_logic_vector(3 downto 0) := X"1";
constant c_cmd_get_speed : std_logic_vector(3 downto 0) := X"2";
constant c_cmd_get_done : std_logic_vector(3 downto 0) := X"3";
constant c_cmd_do_reset_hs : std_logic_vector(3 downto 0) := X"4";
constant c_cmd_do_reset_fs : std_logic_vector(3 downto 0) := X"5";
constant c_cmd_disable_host : std_logic_vector(3 downto 0) := X"6";
constant c_cmd_abort : std_logic_vector(3 downto 0) := X"7";
constant c_cmd_sof_enable : std_logic_vector(3 downto 0) := X"8";
constant c_cmd_sof_disable : std_logic_vector(3 downto 0) := X"9";
constant c_cmd_set_gap : std_logic_vector(3 downto 0) := X"A";
constant c_cmd_set_busy : std_logic_vector(3 downto 0) := X"B";
constant c_cmd_clear_busy : std_logic_vector(3 downto 0) := X"C";
constant c_cmd_set_debug : std_logic_vector(3 downto 0) := X"D";
constant c_cmd_disable_scan : std_logic_vector(3 downto 0) := X"E";
constant c_cmd_enable_scan : std_logic_vector(3 downto 0) := X"F";
function map_speed(i : std_logic_vector(1 downto 0)) return std_logic_vector;
end package;
package body usb1_pkg is
function data_to_t_pipe(i: std_logic_vector(31 downto 0)) return t_pipe is
variable ret : t_pipe;
begin
case i(1 downto 0) is
when "01" =>
ret.state := initialized;
when "10" =>
ret.state := stalled;
when "11" =>
ret.state := aborted;
when others =>
ret.state := invalid;
end case;
if i(2) = '1' then
ret.direction := dir_out;
else
ret.direction := dir_in;
end if;
ret.device_address := i(9 downto 3);
ret.device_endpoint := i(13 downto 10);
ret.max_transfer := unsigned(i(24 downto 14));
-- max_transfer(3 + to_integer(unsigned(i(16 downto 14)))) <= '1'; -- set one bit
ret.data_toggle := i(25);
ret.control := i(26);
ret.timeout := i(31);
-- case i(28 downto 27) is
-- when "00" =>
-- ret.transfer_mode := direct;
-- when "01" =>
-- ret.transfer_mode := use_preamble;
-- when "10" =>
-- ret.transfer_mode := use_split;
-- when others =>
-- ret.transfer_mode := direct;
-- end case;
return ret;
end function;
function t_pipe_to_data(i: t_pipe) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0);
begin
ret := (others => '0');
case i.state is
when initialized => ret(1 downto 0) := "01";
when stalled => ret(1 downto 0) := "10";
when aborted => ret(1 downto 0) := "11";
when others => ret(1 downto 0) := "00";
end case;
if i.direction = dir_out then
ret(2) := '1';
else
ret(2) := '0';
end if;
ret(9 downto 3) := i.device_address;
ret(13 downto 10) := i.device_endpoint;
ret(24 downto 14) := std_logic_vector(i.max_transfer);
ret(25) := i.data_toggle;
ret(26) := i.control;
ret(31) := i.timeout;
-- case i.transfer_mode is
-- when direct => ret(28 downto 27) := "00";
-- when use_preamble => ret(28 downto 27) := "01";
-- when use_split => ret(28 downto 27) := "10";
-- when others => ret(28 downto 27) := "00";
-- end case;
return ret;
end function;
function data_to_t_transaction(i: std_logic_vector(31 downto 0)) return t_transaction is
variable ret : t_transaction;
begin
case i(1 downto 0) is
when "00" => ret.state := none;
when "01" => ret.state := busy;
when "10" => ret.state := done;
when others => ret.state := error;
end case;
case i(3 downto 2) is
when "00" => ret.transaction_type := control;
when "01" => ret.transaction_type := bulk;
when "10" => ret.transaction_type := interrupt;
when others => ret.transaction_type := isochronous;
end case;
ret.pipe_pointer := unsigned(i(8 downto 4));
ret.transfer_length := unsigned(i(19 downto 9));
ret.buffer_address := unsigned(i(30 downto 20));
ret.link_to_next := i(31);
return ret;
end function;
function t_transaction_to_data(i: t_transaction) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0);
begin
ret := (others => '0');
case i.state is
when none => ret(1 downto 0) := "00";
when busy => ret(1 downto 0) := "01";
when done => ret(1 downto 0) := "10";
when error => ret(1 downto 0) := "11";
when others => ret(1 downto 0) := "11";
end case;
case i.transaction_type is
when control => ret(3 downto 2) := "00";
when bulk => ret(3 downto 2) := "01";
when interrupt => ret(3 downto 2) := "10";
when isochronous => ret(3 downto 2) := "11";
when others => ret(3 downto 2) := "11";
end case;
ret(8 downto 4) := std_logic_vector(i.pipe_pointer);
ret(19 downto 9) := std_logic_vector(i.transfer_length);
ret(30 downto 20):= std_logic_vector(i.buffer_address);
ret(31) := i.link_to_next;
return ret;
end function;
function is_token(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_out => return true;
when c_pid_in => return true;
when c_pid_sof => return true;
when c_pid_setup => return true;
when c_pid_pre => return true;
when c_pid_split => return true;
when c_pid_ping => return true;
when others => return false;
end case;
return false;
end function;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_ack => return true;
when c_pid_nak => return true;
when c_pid_nyet => return true;
when c_pid_stall => return true;
when c_pid_err => return true; -- reused!
when others => return false;
end case;
return false;
end function;
function map_speed(i : std_logic_vector(1 downto 0)) return std_logic_vector is
begin
case i is
when "00" =>
return X"46"; -- LS mode
when "01" =>
return X"45"; -- FS mode
when "10" =>
return X"40"; -- HS mode
when others =>
return X"50"; -- stay in chirp mode
end case;
return X"00";
end function;
end;
| gpl-3.0 | 2266a1b9f261a0f848411644ffb2e52a | 0.530591 | 3.541527 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/c1571_startup_tc.vhd | 1 | 11,222 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_bfm_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.c1541_pkg.all;
use work.tl_string_util_pkg.all;
use work.iec_bus_bfm_pkg.all;
entity c1571_startup_tc is
end;
architecture tc of c1571_startup_tc is
signal irq : std_logic;
constant c_wd177x_command : unsigned(15 downto 0) := X"1800";
constant c_wd177x_track : unsigned(15 downto 0) := X"1801";
constant c_wd177x_sector : unsigned(15 downto 0) := X"1802";
constant c_wd177x_datareg : unsigned(15 downto 0) := X"1803";
constant c_wd177x_status_clear : unsigned(15 downto 0) := X"1804";
constant c_wd177x_status_set : unsigned(15 downto 0) := X"1805";
constant c_wd177x_irq_ack : unsigned(15 downto 0) := X"1806";
constant c_wd177x_dma_mode : unsigned(15 downto 0) := X"1807";
constant c_wd177x_dma_addr : unsigned(15 downto 0) := X"1808"; -- DWORD
constant c_wd177x_dma_len : unsigned(15 downto 0) := X"180C"; -- WORD
constant c_param_ram : unsigned(15 downto 0) := X"1000";
begin
i_harness: entity work.harness_c1571
port map (
io_irq => irq
);
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
variable value : unsigned(31 downto 0);
variable params : std_logic_vector(31 downto 0);
variable rotation_speed : natural;
variable bit_time : natural;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
bind_iec_bus_bfm("iec_bfm", bfm);
load_memory("../../../roms/1571-rom.310654-05.bin", dram, X"00008000");
-- load_memory("../../../roms/sounds.bin", dram, X"00000000");
load_memory("../../../disks/cpm.g71", dram, X"00100000" ); -- 1 MB offset
wait for 20 us;
io_write(io, c_drvreg_power, X"01");
wait for 20 us;
io_write(io, c_drvreg_reset, X"00");
rotation_speed := (31250000 / 20);
for i in 0 to 34 loop
value := unsigned(read_memory_32(dram, std_logic_vector(to_unsigned(16#100000# + 12 + i*8, 32))));
value := value + X"00100000";
params(15 downto 0) := read_memory_16(dram, std_logic_vector(value));
value := value + 2;
bit_time := rotation_speed / to_integer(unsigned(params(15 downto 0)));
params(31 downto 16) := std_logic_vector(to_unsigned(bit_time, 16));
report "Track " & integer'image(i+1) & ": " & hstr(value) & " - " & hstr(params);
io_write_32(io, c_param_ram + 16*i, std_logic_vector(value) );
io_write_32(io, c_param_ram + 16*i + 4, params );
io_write_32(io, c_param_ram + 16*i + 12, params );
end loop;
wait for 800 ms;
io_write(io, c_drvreg_inserted, X"01");
-- iec_drf(bfm);
-- iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
-- iec_send_atn(bfm, X"6F"); -- Open channel 15
-- iec_turnaround(bfm); -- start to listen
-- iec_get_message(bfm, msg);
-- iec_print_message(msg);
iec_send_atn(bfm, X"28"); -- Drive 8, Listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_send_message(bfm, "U0>M1"); -- 1571 Mode!
wait for 10 ms;
iec_send_atn(bfm, X"3F", true); -- UnListen
-- wait for 20 ms;
-- iec_drf(bfm);
-- iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
-- iec_send_atn(bfm, X"6F"); -- Open channel 15
-- iec_turnaround(bfm); -- start to listen
-- iec_get_message(bfm, msg);
-- iec_print_message(msg);
--
-- io_write(io, c_drvreg_inserted, X"01");
-- io_write(io, c_drvreg_diskchng, X"01");
wait for 1000 ms;
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
-- Type Command 7 6 5 4 3 2 1 0
-- -------------------------------------------------------
-- I Restore 0 0 0 0 h v r1 r0
-- I Seek 0 0 0 1 h v r1 r0
-- I Step 0 0 1 u h v r1 r0
-- I Step in 0 1 0 u h v r1 r0
-- I Step out 0 1 1 u h v r1 r0
-- II Read sector 1 0 0 m h/s e 0/c 0
-- II Write sector 1 0 1 m h/s e p/c a
-- III Read address 1 1 0 0 h/0 e 0 0
-- III Read track 1 1 1 0 h/0 e 0 0
-- III Write track 1 1 1 1 h/0 e p/0 0
-- IV Force interrupt 1 1 0 1 i3 i2 i1 i0
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable cmd : std_logic_vector(7 downto 0);
variable byte : std_logic_vector(7 downto 0);
variable track : natural := 0;
variable sector : natural := 0;
variable dir : std_logic := '1';
variable side : std_logic := '0';
procedure do_step(update : std_logic) is
begin
if dir = '0' then
if track < 80 then
track := track + 1;
end if;
else
if track > 0 then
track := track - 1;
end if;
end if;
if update = '1' then
io_read(io, c_wd177x_track, byte);
if dir = '0' then
byte := std_logic_vector(unsigned(byte) + 1);
else
byte := std_logic_vector(unsigned(byte) - 1);
end if;
io_write(io, c_wd177x_track, byte);
end if;
end procedure;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
while true loop
wait until irq = '1';
io_read(io, c_wd177x_command, cmd);
report "Command: " & hstr(cmd);
wait for 50 us;
if cmd(7 downto 4) = "0000" then
report "WD1770 Command: Restore";
io_write(io, c_wd177x_track, X"00"); -- set track to zero
track := 0;
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 4) = "0001" then
io_read(io, c_wd177x_datareg, byte);
report "WD1770 Command: Seek: Track = " & integer'image(to_integer(unsigned(byte)));
io_write(io, c_wd177x_track, byte);
track := to_integer(unsigned(byte));
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "001" then
report "WD1770 Command: Step.";
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "010" then
report "WD1770 Command: Step In.";
dir := '1';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "011" then
report "WD1770 Command: Step Out.";
dir := '0';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "100" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Read Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"0000C000" ); -- read a piece of the ROM for now
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"01"); -- read
-- data transfer, so we are not yet done
elsif cmd(7 downto 5) = "101" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Write Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"02"); -- write
-- data transfer, so we are not yet done
elsif cmd(7 downto 4) = "1100" then
report "WD1770 Command: Read Address.";
write_memory_8(dram, X"00020000", std_logic_vector(to_unsigned(track, 8)) );
write_memory_8(dram, X"00020001", X"00" ); -- side (!!)
write_memory_8(dram, X"00020002", std_logic_vector(to_unsigned(sector, 8)) );
write_memory_8(dram, X"00020003", X"02" ); -- sector length = 512
write_memory_8(dram, X"00020004", X"F9" ); -- CRC1
write_memory_8(dram, X"00020005", X"5E" ); -- CRC2
io_write_32(io, c_wd177x_dma_addr, X"00020000" );
io_write(io, c_wd177x_dma_len, X"06");
io_write(io, c_wd177x_dma_len+1, X"00"); -- transfer 6 bytes
io_write(io, c_wd177x_dma_mode, X"01"); -- read
elsif cmd(7 downto 4) = "1110" then
report "WD1770 Command: Read Track (not implemented).";
elsif cmd(7 downto 4) = "1111" then
report "WD1770 Command: Write Track.";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"6A");
io_write(io, c_wd177x_dma_len+1, X"18"); -- 6250 bytes
io_write(io, c_wd177x_dma_mode, X"02"); -- write
elsif cmd(7 downto 4) = "1101" then
io_write(io, c_wd177x_dma_mode, X"00"); -- stop
io_write(io, c_wd177x_status_clear, X"01");
end if;
io_write(io, c_wd177x_irq_ack, X"00");
end loop;
end process;
end architecture;
| gpl-3.0 | b298e429c6c730b2a4c077d57c185052 | 0.487346 | 3.32997 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/std/std_Pkg.vhd | 2 | 9,284 | ----------------------------------------------------------------------------------------------
--
-- Input file : std_Pkg.vhd
-- Design name : std_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with several standard components.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
PACKAGE std_Pkg IS
----------------------------------------------------------------------------------------------
-- STANDARD COMPONENTS IN STD_PKG
----------------------------------------------------------------------------------------------
component sram generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component sram_4en generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(3 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component dsram generic
(
WIDTH : positive;
SIZE : positive
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
ena_i : in std_logic;
dat_w_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_w_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
clk_i : in std_logic
);
end component;
----------------------------------------------------------------------------------------------
-- FUNCTIONS IN STD_PKG
----------------------------------------------------------------------------------------------
function v_or(d : std_logic_vector) return std_logic;
function is_zero(d : std_logic_vector) return std_logic;
function is_not_zero(d : std_logic_vector) return std_logic;
function my_conv_integer(a: std_logic_vector) return integer;
function notx(d : std_logic_vector) return boolean;
function compare(a, b : std_logic_vector) return std_logic;
function multiply(a, b : std_logic_vector) return std_logic_vector;
function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector;
function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector;
function increment(a : std_logic_vector) return std_logic_vector;
function shift(value : std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector;
function shift_left(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0)) return std_logic_vector;
function shift_right(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector;
end std_Pkg;
PACKAGE BODY std_Pkg IS
-- Unary OR reduction
function v_or(d : std_logic_vector) return std_logic is
variable z : std_logic;
begin
z := '0';
if notx (d) then
for i in d'range loop
z := z or d(i);
end loop;
end if;
return z;
end;
-- Check for ones in the vector
function is_not_zero(d : std_logic_vector) return std_logic is
variable z : std_logic_vector(d'range);
begin
z := (others => '0');
if notx(d) then
if d = z then
return '0';
else
return '1';
end if;
else
return '0';
end if;
end;
-- Check for ones in the vector
function is_zero(d : std_logic_vector) return std_logic is
begin
return not is_not_zero(d);
end;
-- rewrite conv_integer to avoid modelsim warnings
function my_conv_integer(a : std_logic_vector) return integer is
variable res : integer range 0 to 2**a'length-1;
begin
res := 0;
if (notx(a)) then
res := to_integer(unsigned(a));
end if;
return res;
end;
function compare(a, b : std_logic_vector) return std_logic is
variable z : std_logic;
begin
if notx(a & b) and a = b then
return '1';
else
return '0';
end if;
end;
-- Unary NOT X test
function notx(d : std_logic_vector) return boolean is
variable res : boolean;
begin
res := true;
-- pragma translate_off
res := not is_x(d);
-- pragma translate_on
return (res);
end;
-- -- 32 bit shifter
-- -- SYNOPSIS:
-- -- value: value to be shifted
-- -- shamt: shift amount
-- -- s 0 / 1: shift right / left
-- -- t 0 / 1: shift logical / arithmetic
-- -- PSEUDOCODE (from microblaze reference guide)
-- -- if S = 1 then
-- -- (rD) = (rA) << (rB)[27:31]
-- -- else
-- -- if T = 1 then
-- -- if ((rB)[27:31]) != 0 then
-- -- (rD)[0:(rB)[27:31]-1] = (rA)[0]
-- -- (rD)[(rB)[27:31]:31] = (rA) >> (rB)[27:31]
-- -- else
-- -- (rD) = (rA)
-- -- else
-- -- (rD) = (rA) >> (rB)[27:31]
function shift(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector is
begin
if s = '1' then
-- left arithmetic or logical shift
return shift_left(value, shamt);
else
if t = '1' then
-- right arithmetic shift
return shift_right(value, shamt, value(31));
else
-- right logical shift
return shift_right(value, shamt, '0');
end if;
end if;
end;
function shift_left(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0)) return std_logic_vector is
variable result: std_logic_vector(31 downto 0);
variable paddings: std_logic_vector(15 downto 0);
begin
paddings := (others => '0');
result := value;
if (shamt(4) = '1') then result := result(15 downto 0) & paddings(15 downto 0); end if;
if (shamt(3) = '1') then result := result(23 downto 0) & paddings( 7 downto 0); end if;
if (shamt(2) = '1') then result := result(27 downto 0) & paddings( 3 downto 0); end if;
if (shamt(1) = '1') then result := result(29 downto 0) & paddings( 1 downto 0); end if;
if (shamt(0) = '1') then result := result(30 downto 0) & paddings( 0 ); end if;
return result;
end;
function shift_right(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector is
variable result: std_logic_vector(31 downto 0);
variable paddings: std_logic_vector(15 downto 0);
begin
paddings := (others => padding);
result := value;
if (shamt(4) = '1') then result := paddings(15 downto 0) & result(31 downto 16); end if;
if (shamt(3) = '1') then result := paddings( 7 downto 0) & result(31 downto 8); end if;
if (shamt(2) = '1') then result := paddings( 3 downto 0) & result(31 downto 4); end if;
if (shamt(1) = '1') then result := paddings( 1 downto 0) & result(31 downto 2); end if;
if (shamt(0) = '1') then result := paddings( 0 ) & result(31 downto 1); end if;
return result;
end;
function multiply(a, b: std_logic_vector) return std_logic_vector is
variable x: std_logic_vector (a'length + b'length - 1 downto 0);
begin
x := std_logic_vector(signed(a) * signed(b));
return x(31 downto 0);
end;
function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector is
variable a: std_logic_vector (size - 1 downto 0);
begin
a(size - 1 downto value'length) := (others => fill);
a(value'length - 1 downto 0) := value;
return a;
end;
function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector is
variable x : std_logic_vector(a'length + 1 downto 0);
begin
x := (others => '0');
if notx (a & b & ci) then
x := std_logic_vector(signed('0' & a & '1') + signed('0' & b & ci));
end if;
return x(a'length + 1 downto 1);
end;
function increment(a : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
begin
x := (others => '0');
if notx (a) then
x := std_logic_vector(signed(a) + 1);
end if;
return x;
end;
end std_Pkg; | gpl-3.0 | 677d88dc95432cf05fcb4854094afc92 | 0.523266 | 3.727017 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/acia/vhdl_source/acia6551_pkg.vhd | 1 | 1,454 | --------------------------------------------------------------------------------
-- Entity: acia6551
-- Date:2018-11-13
-- Author: gideon
--
-- Description: Definitions of 6551.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package acia6551_pkg is
constant c_addr_data_register : unsigned(1 downto 0) := "00";
constant c_addr_status_register : unsigned(1 downto 0) := "01"; -- writing causes reset
constant c_addr_command_register : unsigned(1 downto 0) := "10";
constant c_addr_control_register : unsigned(1 downto 0) := "11";
constant c_reg_rx_head : unsigned(3 downto 0) := X"0";
constant c_reg_rx_tail : unsigned(3 downto 0) := X"1";
constant c_reg_tx_head : unsigned(3 downto 0) := X"2";
constant c_reg_tx_tail : unsigned(3 downto 0) := X"3";
constant c_reg_control : unsigned(3 downto 0) := X"4";
constant c_reg_command : unsigned(3 downto 0) := X"5";
constant c_reg_status : unsigned(3 downto 0) := X"6";
constant c_reg_enable : unsigned(3 downto 0) := X"7";
constant c_reg_handsh : unsigned(3 downto 0) := X"8";
constant c_reg_irq_source : unsigned(3 downto 0) := X"9";
constant c_reg_slot_base : unsigned(3 downto 0) := X"A";
constant c_reg_rx_rate : unsigned(3 downto 0) := X"B";
end package;
| gpl-3.0 | 62b5cd7be627e4bfd8fc1cae1894629e | 0.540578 | 3.453682 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/command_interface/vhdl_source/command_if_pkg.vhd | 1 | 3,029 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package command_if_pkg is
constant c_cif_io_slot_base : unsigned(3 downto 0) := X"0";
constant c_cif_io_slot_enable : unsigned(3 downto 0) := X"1";
constant c_cif_io_handshake_out : unsigned(3 downto 0) := X"2"; -- write will also cause pointers to be reset
constant c_cif_io_handshake_in : unsigned(3 downto 0) := X"3";
constant c_cif_io_command_start : unsigned(3 downto 0) := X"4"; -- read only; tells software where the buffers are.
constant c_cif_io_command_end : unsigned(3 downto 0) := X"5";
constant c_cif_io_response_start : unsigned(3 downto 0) := X"6"; -- read only; tells software where the buffers are.
constant c_cif_io_response_end : unsigned(3 downto 0) := X"7";
constant c_cif_io_status_start : unsigned(3 downto 0) := X"8"; -- read only; tells software where the buffers are.
constant c_cif_io_status_end : unsigned(3 downto 0) := X"9";
constant c_cif_io_status_length : unsigned(3 downto 0) := X"A"; -- write will reset status readout
constant c_cif_io_irq_mask : unsigned(3 downto 0) := X"B"; -- read/write
constant c_cif_io_response_len_l : unsigned(3 downto 0) := X"C"; -- write will reset response readout
constant c_cif_io_response_len_h : unsigned(3 downto 0) := X"D"; -- read will return the current pointer
constant c_cif_io_command_len_l : unsigned(3 downto 0) := X"E"; -- read only
constant c_cif_io_command_len_h : unsigned(3 downto 0) := X"F";
constant c_cif_io_irq_mask_set : unsigned(3 downto 0) := X"4"; -- write only
constant c_cif_io_irq_mask_clear : unsigned(3 downto 0) := X"5"; -- write only
constant c_cif_bus_id : unsigned(2 downto 0) := "011"; -- RO
constant c_cif_slot_control : unsigned(2 downto 0) := "100"; -- R/W
constant c_cif_slot_command : unsigned(2 downto 0) := "101"; -- WO
constant c_cif_slot_response : unsigned(2 downto 0) := "110"; -- RO
constant c_cif_slot_status : unsigned(2 downto 0) := "111"; -- RO
constant c_cmd_if_command_buffer_addr : unsigned(10 downto 0) := to_unsigned( 0, 11);
constant c_cmd_if_response_buffer_addr : unsigned(10 downto 0) := to_unsigned( 896, 11);
constant c_cmd_if_status_buffer_addr : unsigned(10 downto 0) := to_unsigned(1792, 11);
constant c_cmd_if_command_buffer_size : integer := 896;
constant c_cmd_if_response_buffer_size : integer := 896;
constant c_cmd_if_status_buffer_size : integer := 256;
constant c_cmd_if_command_buffer_end : unsigned(10 downto 0) := to_unsigned( 0 + c_cmd_if_command_buffer_size-1, 11);
constant c_cmd_if_response_buffer_end : unsigned(10 downto 0) := to_unsigned( 896 + c_cmd_if_response_buffer_size-1, 11);
constant c_cmd_if_status_buffer_end : unsigned(10 downto 0) := to_unsigned(1792 + c_cmd_if_status_buffer_size-1, 11);
end package;
| gpl-3.0 | 025707474e3ca79d688f458654d879fd | 0.630571 | 3.175052 | false | false | false | false |
armandas/Arcade | sounds.vhd | 2 | 1,082 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sounds is
port(
clk, not_reset: in std_logic;
enable: in std_logic;
period: in std_logic_vector(18 downto 0);
volume: in std_logic_vector(2 downto 0);
buzzer: out std_logic
);
end sounds;
architecture generator of sounds is
signal counter, counter_next: std_logic_vector(18 downto 0);
signal pulse_width: std_logic_vector(18 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
counter <= (others => '0');
elsif clk'event and clk = '0' then
counter <= counter_next;
end if;
end process;
-- duty cycle:
-- max: 50% (18 downto 1)
-- min: 0.78% (18 downto 7)
-- off when given 0 (18 downto 0)!
pulse_width <= period(18 downto conv_integer(volume));
counter_next <= (others => '0') when counter = period else
counter + 1;
buzzer <= '1' when (enable = '1' and counter < pulse_width) else '0';
end generator; | bsd-2-clause | b5606d01a61071bb03c00aa61f545249 | 0.586876 | 3.52443 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/floppy_sound.vhd | 1 | 7,444 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy_sound is
generic (
g_tag : std_logic_vector(7 downto 0) := X"04";
sound_base : unsigned(27 downto 16) := X"103";
motor_hum_addr : unsigned(15 downto 0) := X"0000";
flop_slip_addr : unsigned(15 downto 0) := X"1200";
track_in_addr : unsigned(15 downto 0) := X"2400";
track_out_addr : unsigned(15 downto 0) := X"2E00";
head_bang_addr : unsigned(15 downto 0) := X"3800";
insert_addr : unsigned(15 downto 0) := X"4000";
remove_addr : unsigned(15 downto 0) := X"6000";
motor_len : integer := 4410;
track_in_len : unsigned(15 downto 0) := X"089D"; -- 100 ms
track_out_len : unsigned(15 downto 0) := X"089D"; -- 100 ms
head_bang_len : unsigned(15 downto 0) := X"089D"; -- 100 ms
insert_len : unsigned(15 downto 0) := X"2000"; -- 400 ms
remove_len : unsigned(15 downto 0) := X"2000" ); -- 400 ms
port (
clock : in std_logic;
reset : in std_logic;
tick_4MHz : in std_logic;
do_trk_out : in std_logic;
do_trk_in : in std_logic;
do_head_bang : in std_logic;
do_insert : in std_logic := '0';
do_remove : in std_logic := '0';
en_hum : in std_logic;
en_slip : in std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- audio
sample_out : out signed(12 downto 0) := (others => '0'));
end floppy_sound;
architecture gideon of floppy_sound is
constant c_rate_div : integer := 4000000 / 22050;
signal rate_count : integer range 0 to c_rate_div;
signal motor_sample : signed(7 downto 0);
signal head_sample : signed(7 downto 0);
signal sample_tick : std_logic;
type t_voice_state is (idle, play);
type t_serve_state is (idle, wait_voice1, serve_voice2, wait_voice2);
signal voice1 : t_voice_state;
signal serve_state : t_serve_state;
signal voice1_cnt : unsigned(13 downto 0); -- max 16K
signal voice1_addr : unsigned(15 downto 0);
signal voice2_cnt : unsigned(13 downto 0); -- max 16K
signal mem_addr_i : unsigned(15 downto 0);
signal mem_rack : std_logic;
signal mem_dack : std_logic;
begin
mem_req.tag <= g_tag;
mem_req.read_writen <= '1'; -- always read
mem_req.address <= sound_base(25 downto 16) & mem_addr_i;
mem_req.data <= X"00";
mem_req.size <= "00"; -- 1 byte at a time
mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0';
process(clock)
variable signed_sum : signed(12 downto 0);
begin
if rising_edge(clock) then
sample_tick <= '0';
if tick_4MHz = '1' then
if rate_count = 0 then
signed_sum := motor_sample + (head_sample(head_sample'high) & head_sample & "0000");
sample_out <= signed_sum;
rate_count <= c_rate_div;
sample_tick <= '1';
else
rate_count <= rate_count - 1;
end if;
end if;
case serve_state is
when idle =>
if sample_tick='1' then
case voice1 is
when play =>
if voice1_cnt = 0 then
voice1 <= idle;
else
mem_req.request <= '1';
mem_addr_i <= voice1_addr;
serve_state <= wait_voice1;
end if;
when others =>
head_sample <= X"00";
serve_state <= serve_voice2;
end case;
end if;
when wait_voice1 =>
if mem_rack='1' then
mem_req.request <= '0';
end if;
if mem_dack='1' then
head_sample <= signed(mem_resp.data);
voice1_cnt <= voice1_cnt - 1;
voice1_addr <= voice1_addr + 1;
serve_state <= serve_voice2;
end if;
when serve_voice2 =>
if en_hum = '1' then
mem_req.request <= '1';
mem_addr_i <= motor_hum_addr(15 downto 0) + ("00" & voice2_cnt);
serve_state <= wait_voice2;
elsif en_slip = '1' then
mem_req.request <= '1';
mem_addr_i <= flop_slip_addr(15 downto 0) + ("00" & voice2_cnt);
serve_state <= wait_voice2;
else
motor_sample <= X"00";
serve_state <= idle;
end if;
when wait_voice2 =>
if mem_rack='1' then
mem_req.request <= '0';
end if;
if mem_dack='1' then
motor_sample <= signed(mem_resp.data);
if voice2_cnt = motor_len-1 then
voice2_cnt <= (others => '0');
else
voice2_cnt <= voice2_cnt + 1;
end if;
serve_state <= idle;
end if;
when others =>
null;
end case;
if do_trk_out = '1' then
voice1 <= play;
voice1_cnt <= track_out_len(voice1_cnt'range);
voice1_addr <= track_out_addr(voice1_addr'range);
end if;
if do_trk_in = '1' then
voice1 <= play;
voice1_cnt <= track_in_len(voice1_cnt'range);
voice1_addr <= track_in_addr(voice1_addr'range);
end if;
if do_head_bang = '1' then
voice1 <= play;
voice1_cnt <= head_bang_len(voice1_cnt'range);
voice1_addr <= head_bang_addr(voice1_addr'range);
end if;
if do_insert = '1' then
voice1 <= play;
voice1_cnt <= insert_len(voice1_cnt'range);
voice1_addr <= insert_addr(voice1_addr'range);
end if;
if do_remove = '1' then
voice1 <= play;
voice1_cnt <= remove_len(voice1_cnt'range);
voice1_addr <= remove_addr(voice1_addr'range);
end if;
if reset='1' then
mem_req.request <= '0';
serve_state <= idle;
voice1 <= idle;
voice1_cnt <= (others => '0');
voice2_cnt <= (others => '0');
voice1_addr <= (others => '0');
sample_out <= (others => '0');
motor_sample <= (others => '0');
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 659aa6033087d1e49c82d7c9932cc382 | 0.438608 | 3.853002 | false | false | false | false |
keyru/hdl-make | tests/counter/top/proasic3_sk/vhdl/proasic3_top.vhd | 2 | 1,357 | -----------------------------------------------------------------------
-- Design : Counter VHDL top module, Microsemi ProASIC3 Starter Kit
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity proasic3_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(7 downto 0)
);
end proasic3_top;
-----------------------------------------------------------------------
architecture structure of proasic3_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= clear_i;
s_count <= count_i;
led_o <= s_Q;
end architecture structure;
----------------------------------------------------------------
| gpl-3.0 | 9634809cf6085b0f12c41711651e6374 | 0.467207 | 3.910663 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/cyclone4_test/vhdl_source/u2p_nios_ddr2.vhd | 1 | 16,985 | -------------------------------------------------------------------------------
-- Title : u2p_nios_ddr2
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel with just the alt-mem phy. Testing and experimenting
-- with memory latency.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity u2p_nios_ddr2 is
port (
-- slot side
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : inout std_logic;
SLOT_BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : out std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : inout std_logic;
SLOT_ROMLn : inout std_logic;
SLOT_IO1n : inout std_logic;
SLOT_IO2n : inout std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DM : inout std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_nios_ddr2 is
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
component nios_solo is
port (
clk_clk : in std_logic := 'X'; -- clk
-- dram_waitrequest : in std_logic := 'X'; -- waitrequest
-- dram_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
-- dram_readdatavalid : in std_logic := 'X'; -- readdatavalid
-- dram_burstcount : out std_logic_vector(0 downto 0); -- burstcount
-- dram_writedata : out std_logic_vector(31 downto 0); -- writedata
-- dram_address : out std_logic_vector(25 downto 0); -- address
-- dram_write : out std_logic; -- write
-- dram_read : out std_logic; -- read
-- dram_byteenable : out std_logic_vector(3 downto 0); -- byteenable
-- dram_debugaccess : out std_logic; -- debugaccess
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component nios_solo;
signal por_n : std_logic;
signal por_count : unsigned(23 downto 0) := (others => '0');
signal led_n : std_logic_vector(0 to 3);
signal ref_reset : std_logic;
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_reset_n : std_logic;
signal eth_reset : std_logic;
signal button_i : std_logic_vector(2 downto 0);
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_u2p_req : t_io_req;
signal io_u2p_resp : t_io_resp;
signal io_req_new_io : t_io_req;
signal io_resp_new_io : t_io_resp;
signal io_req_remote : t_io_req;
signal io_resp_remote : t_io_resp;
signal io_req_ddr2 : t_io_req;
signal io_resp_ddr2 : t_io_resp;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal dram_waitrequest : std_logic := 'X'; -- waitrequest
signal dram_readdata : std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
signal dram_readdatavalid : std_logic := 'X'; -- readdatavalid
signal dram_writedata : std_logic_vector(31 downto 0); -- writedata
signal dram_address : std_logic_vector(25 downto 0); -- address
signal dram_write : std_logic; -- write
signal dram_read : std_logic; -- read
signal dram_byteenable : std_logic_vector(3 downto 0); -- byteenable
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
signal reset_request_n : std_logic := '1';
signal is_idle : std_logic;
begin
process(RMII_REFCLK, reset_request_n)
begin
if reset_request_n = '0' then
por_count <= (others => '0');
elsif rising_edge(RMII_REFCLK) then
if por_count = X"FFFFFF" then
por_n <= '1';
else
por_n <= '0';
por_count <= por_count + 1;
end if;
end if;
end process;
ref_reset <= not por_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => open );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => not sys_reset_n,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => sys_reset,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
sys_reset_n <= not sys_reset;
i_nios: nios_solo
port map (
clk_clk => sys_clock,
reset_reset_n => sys_reset_n,
-- dram_waitrequest => dram_waitrequest,
-- dram_readdata => dram_readdata,
-- dram_readdatavalid => dram_readdatavalid,
-- dram_burstcount => open,
-- dram_writedata => dram_writedata,
-- dram_address => dram_address,
-- dram_write => dram_write,
-- dram_read => dram_read,
-- dram_byteenable => dram_byteenable,
-- dram_debugaccess => open,
io_ack => io_resp.ack,
io_rdata => io_resp.data,
io_read => io_req.read,
io_wdata => io_req.data,
io_write => io_req.write,
unsigned(io_address) => io_req.address,
io_irq => '0',
io_u2p_ack => io_u2p_resp.ack,
io_u2p_rdata => io_u2p_resp.data,
io_u2p_read => io_u2p_req.read,
io_u2p_wdata => io_u2p_req.data,
io_u2p_write => io_u2p_req.write,
unsigned(io_u2p_address) => io_u2p_req.address,
io_u2p_irq => '0',
unsigned(mem_mem_req_address) => mem_req.address,
mem_mem_req_byte_en => mem_req.byte_en,
mem_mem_req_read_writen => mem_req.read_writen,
mem_mem_req_request => mem_req.request,
mem_mem_req_tag => mem_req.tag,
mem_mem_req_wdata => mem_req.data,
mem_mem_resp_dack_tag => mem_resp.dack_tag,
mem_mem_resp_data => mem_resp.data,
mem_mem_resp_rack_tag => mem_resp.rack_tag
);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 9,
g_ports => 3
)
port map (
clock => sys_clock,
req => io_u2p_req,
resp => io_u2p_resp,
reqs(0) => io_req_new_io,
reqs(1) => io_req_ddr2,
reqs(2) => io_req_remote,
resps(0) => io_resp_new_io,
resps(1) => io_resp_ddr2,
resps(2) => io_resp_remote
);
-- i_dram_bridge: entity work.avalon_to_mem32_bridge
-- port map (
-- clock => sys_clock,
-- reset => sys_reset,
--
-- avs_read => dram_read,
-- avs_write => dram_write,
-- avs_address => dram_address,
-- avs_writedata => dram_writedata,
-- avs_byteenable => dram_byteenable,
-- avs_waitrequest => dram_waitrequest,
-- avs_readdata => dram_readdata,
-- avs_readdatavalid => dram_readdatavalid,
--
-- mem_req => mem_req,
-- mem_resp => mem_resp );
i_memphy: entity work.ddr2_ctrl
port map (
ref_clock => RMII_REFCLK,
ref_reset => ref_reset,
sys_clock_o => sys_clock,
sys_reset_o => sys_reset,
clock => sys_clock,
reset => sys_reset,
io_req => io_req_ddr2,
io_resp => io_resp_ddr2,
inhibit => '0',
is_idle => is_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_ODT => SDRAM_ODT,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA(1 downto 0),
SDRAM_DM => SDRAM_DM,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS
);
i_remote: entity work.update_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_remote,
io_resp => io_resp_remote,
flash_selck => FLASH_SELCK,
flash_sel => FLASH_SEL
);
i_u2p_io: entity work.u2p_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_new_io,
io_resp => io_resp_new_io,
mdc => MDIO_CLK,
mdio => MDIO_DATA,
i2c_scl => I2C_SCL,
i2c_sda => I2C_SDA,
speaker_en => SPEAKER_ENABLE,
hub_reset_n=> HUB_RESETn
);
ETH_RESETn <= '1';
SLOT_ADDR <= (others => 'Z');
SLOT_DATA <= (others => 'Z');
-- top
SLOT_DMAn <= 'Z';
SLOT_ROMLn <= 'Z';
SLOT_IO2n <= 'Z';
SLOT_EXROMn <= 'Z';
SLOT_GAMEn <= 'Z';
SLOT_IO1n <= 'Z';
SLOT_RWn <= 'Z';
SLOT_IRQn <= 'Z';
SLOT_NMIn <= 'Z';
SLOT_RSTn <= 'Z';
SLOT_ROMHn <= 'Z';
-- Cassette Interface
CAS_SENSE <= '0';
CAS_READ <= '0';
CAS_WRITE <= '0';
LED_MOTORn <= sys_reset;
LED_DISKn <= is_idle;
LED_CARTn <= button_i(0) xor button_i(1) xor button_i(2);
LED_SDACTn <= SLOT_BA xor SLOT_DOTCLK xor SLOT_PHI2 xor CAS_MOTOR xor SLOT_VCC;
button_i <= not BUTTON;
SLOT_BUFFER_ENn <= '1'; -- we don't connect to a C64
-- Flash Interface
FLASH_CSn <= '1';
FLASH_SCK <= '1';
FLASH_MOSI <= '1';
-- USB Interface (ULPI)
ULPI_RESET <= por_n;
ULPI_STP <= '0';
ULPI_DATA <= (others => 'Z');
end architecture;
| gpl-3.0 | c581a028aed94c1c88ed3431c21bcd57 | 0.458934 | 3.532654 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/vhdl_bfm/dram_model_8.vhd | 5 | 6,461 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
-------------------------------------------------------------------------------
-- File : dram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple DRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_string_util_pkg.all;
entity dram_model_8 is
generic (
g_given_name : string;
g_cas_latency : positive := 2;
g_burst_len_r : positive := 1;
g_burst_len_w : positive := 1;
g_column_bits : positive := 10;
g_row_bits : positive := 13;
g_bank_bits : positive := 2 );
port (
CLK : in std_logic;
CKE : in std_logic;
A : in std_logic_vector(g_row_bits-1 downto 0);
BA : in std_logic_vector(g_bank_bits-1 downto 0);
CSn : in std_logic;
RASn : in std_logic;
CASn : in std_logic;
WEn : in std_logic;
DQM : in std_logic;
DQ : inout std_logic_vector(7 downto 0) );
end dram_model_8;
architecture bfm of dram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
signal command : std_logic_vector(2 downto 0);
constant c_banks : integer := 2 ** g_bank_bits;
type t_row_array is array(0 to c_banks-1) of std_logic_vector(g_row_bits-1 downto 0);
signal bank_rows : t_row_array;
signal bank : integer;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal r_queue : t_byte_array(0 to g_cas_latency + g_burst_len_r) := (others => (others => 'Z'));
-- constant c_col : integer := 0;
-- constant c_bank : integer := g_column_bits;
-- constant c_row : integer := g_column_bits + g_bank_bits;
begin
bind: process
begin
register_mem_model(dram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
command <= WEn & CASn & RASn;
bank <= to_integer(unsigned(BA));
DQ <= transport r_queue(0) after 6 ns;
process(CLK)
variable raddr : std_logic_vector(31 downto 0) := (others => '0');
variable waddr : std_logic_vector(31 downto 0) := (others => '0');
variable more_writes : integer := 0;
function map_address(bank_bits : std_logic_vector(g_bank_bits-1 downto 0);
row_bits : std_logic_vector(g_row_bits-1 downto 0);
col_bits : std_logic_vector(g_column_bits-1 downto 0) ) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
-- mapping used in v5_sdr
--addr_bank <= address_fifo(3 downto 2);
--addr_row <= address_fifo(24 downto 12);
--addr_column <= address_fifo(11 downto 4) & address_fifo(1 downto 0);
ret(g_bank_bits+1 downto 2) := bank_bits;
ret(1 downto 0) := col_bits(1 downto 0);
ret(g_column_bits+g_bank_bits-1 downto g_bank_bits+2) := col_bits(g_column_bits-1 downto 2);
ret(g_bank_bits+g_column_bits+g_row_bits-1 downto g_bank_bits+g_column_bits) := row_bits;
return ret;
end function;
begin
if rising_edge(CLK) then
if bound and CKE='1' then
r_queue <= r_queue(1 to r_queue'high) & ("ZZZZZZZZ");
if more_writes > 0 then
waddr := std_logic_vector(unsigned(waddr) + 1);
if to_integer(unsigned(waddr)) mod g_burst_len_w = 0 then
waddr := std_logic_vector(unsigned(waddr) - g_burst_len_w);
end if;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
more_writes := more_writes - 1;
end if;
if CSn='0' then
case command is
when "110" => -- RAS, register bank address
bank_rows(bank) <= A(g_row_bits-1 downto 0);
when "101" => -- CAS, start read burst
raddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--raddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--raddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--raddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
--report hstr(BA) & " " & hstr(bank_rows(bank)) & " " & hstr(A) & ": " & hstr(raddr);
for i in 0 to g_burst_len_r-1 loop
r_queue(g_cas_latency-1 + i) <= read_memory_8(this, raddr);
raddr := std_logic_vector(unsigned(raddr) + 1);
if to_integer(unsigned(raddr)) mod g_burst_len_r = 0 then
raddr := std_logic_vector(unsigned(raddr) - g_burst_len_r);
end if;
end loop;
when "001" => -- CAS & WE, start write burst
waddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
--waddr(c_bank+g_bank_bits-1 downto c_bank) := BA;
--waddr(c_row+g_row_bits-1 downto c_row) := bank_rows(bank);
--waddr(c_col+g_column_bits-1 downto c_col) := A(g_column_bits-1 downto 0);
more_writes := g_burst_len_w - 1;
if DQM='0' then
write_memory_8(this, waddr, DQ);
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end bfm;
| gpl-3.0 | f6dba9409da9341a634c0c48155d09d7 | 0.46742 | 3.704702 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/cpu6502.vhd | 1 | 1,393 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu6502 is
port (
cpu_clk : in std_logic;
cpu_clk_en : in std_logic;
cpu_reset : in std_logic;
cpu_write : out std_logic;
cpu_wdata : out std_logic_vector(7 downto 0);
cpu_rdata : in std_logic_vector(7 downto 0);
cpu_addr : out std_logic_vector(16 downto 0);
cpu_pc : out std_logic_vector(15 downto 0);
carry : out std_logic;
IRQn : in std_logic; -- IRQ interrupt (level sensitive)
NMIn : in std_logic; -- NMI interrupt (edge sensitive)
SOn : in std_logic -- set Overflow flag
);
end cpu6502;
architecture cycle_exact of cpu6502 is
signal read_write_n : std_logic;
begin
core: entity work.proc_core
generic map (
support_bcd => true )
port map(
clock => cpu_clk,
clock_en => cpu_clk_en,
reset => cpu_reset,
irq_n => IRQn,
nmi_n => NMIn,
so_n => SOn,
carry => carry,
pc_out => cpu_pc,
addr_out => cpu_addr,
data_in => cpu_rdata,
data_out => cpu_wdata,
read_write_n => read_write_n );
cpu_write <= not read_write_n;
end cycle_exact;
| gpl-3.0 | 94493fa3fa9a7c523607cec4cf2b2bf8 | 0.505384 | 3.405868 | false | false | false | false |
asicguy/crash | fpga/src/usrp_ddr_intf/usrp_ddr_intf_axis.vhd | 2 | 35,904 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: usrp_ddr_intf_axis.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Wraps AXI Stream interfaces around usrp_ddr_intf.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity usrp_ddr_intf_axis is
generic (
DDR_CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface
BAUD : integer := 1e6); -- UART baud rate
port (
-- USRP Interface
UART_TX : out std_logic; -- UART
RX_DATA_CLK_N : in std_logic; -- Receive data clock (N)
RX_DATA_CLK_P : in std_logic; -- Receive data clock (P)
RX_DATA_N : in std_logic_vector(4 downto 0); -- Receive data (N)
RX_DATA_P : in std_logic_vector(4 downto 0); -- Receive data (P)
RX_DATA_STB_N : in std_logic; -- Receive data strobe (N)
RX_DATA_STB_P : in std_logic; -- Receive data strobe (P)
TX_DATA_N : out std_logic_vector(5 downto 0); -- Transmit data (N)
TX_DATA_P : out std_logic_vector(5 downto 0); -- Transmit data (P)
TX_DATA_STB_N : out std_logic; -- Transmit data strobe (N)
TX_DATA_STB_P : out std_logic; -- Transmit data strobe (P)
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (DAC / TX Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (ADC / RX Data)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
rx_enable_aux : in std_logic;
tx_enable_aux : in std_logic);
end entity;
architecture RTL of usrp_ddr_intf_axis is
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component usrp_ddr_intf is
generic (
DDR_CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface
BAUD : integer := 115200); -- UART baud rate
port (
reset : in std_logic; -- Asynchronous reset
-- Control registers (internally synchronized to clk_rx clock domain)
usrp_mode_ctrl : in std_logic_vector(7 downto 0); -- USRP Mode
usrp_mode_ctrl_en : in std_logic; -- USRP Mode data valid, hold until acknowledge
usrp_mode_ctrl_ack : out std_logic; -- USRP Mode register acknowledge
rx_enable : in std_logic; -- Enable RX processing chain (clears resets)
rx_gain : in std_logic_vector(31 downto 0); -- Scales decimating CIC filter output
rx_cic_decim : in std_logic_vector(10 downto 0); -- Receive CIC decimation rate
rx_cic_decim_en : in std_logic; -- Set receive CIC decimation rate
rx_cic_decim_ack : out std_logic; -- Set receive CIC decimation rate acknowledge
rx_fix2float_bypass : in std_logic; -- Bypass RX fixed to floating point conversion
rx_cic_bypass : in std_logic; -- Bypass RX CIC filter
rx_hb_bypass : in std_logic; -- Bypass RX half band filter
tx_enable : in std_logic; -- Enable TX processing chain (clears resets)
tx_gain : in std_logic_vector(31 downto 0); -- Scales interpolating CIC filter output
tx_cic_interp : in std_logic_vector(10 downto 0); -- Transmit CIC interpolation rate
tx_cic_interp_en : in std_logic; -- Set transmit CIC interpolation rate
tx_cic_interp_ack : out std_logic; -- Set transmit CIC interpolation rate acknowledge
tx_float2fix_bypass : in std_logic; -- Bypass TX floating to fixed point conversion
tx_cic_bypass : in std_logic; -- Bypass TX CIC filter
tx_hb_bypass : in std_logic; -- Bypass TX half band filter
-- UART output signals
uart_busy : out std_logic; -- UART busy
UART_TX : out std_logic; -- UART
-- Physical Transmit / Receive data interface
RX_DATA_CLK_N : in std_logic; -- Receive data clock (N)
RX_DATA_CLK_P : in std_logic; -- Receive data clock (P)
RX_DATA_N : in std_logic_vector(4 downto 0); -- Receive data (N)
RX_DATA_P : in std_logic_vector(4 downto 0); -- Receive data (P)
RX_DATA_STB_N : in std_logic; -- Receive data strobe (N)
RX_DATA_STB_P : in std_logic; -- Receive data strobe (P)
TX_DATA_N : out std_logic_vector(5 downto 0); -- Transmit data (N)
TX_DATA_P : out std_logic_vector(5 downto 0); -- Transmit data (P)
TX_DATA_STB_N : out std_logic; -- Transmit data strobe (N)
TX_DATA_STB_P : out std_logic; -- Transmit data strobe (P)
clk_rx_locked : out std_logic; -- RX data MMCM clock locked
clk_rx_phase : out std_logic_vector(9 downto 0); -- RX data MMCM phase offset, 0 - 559
rx_phase_init : in std_logic_vector(9 downto 0); -- RX data MMCM phase offset initialization, 0 - 559
rx_phase_incdec : in std_logic; -- '1' = Increment, '0' = Decrement
rx_phase_en : in std_logic; -- Increment / decrements RX data MMCM phase (Rising edge)
rx_phase_busy : out std_logic; -- RX data MMCM phase adjustment in process
rx_restart_cal : in std_logic; -- Restart RX data MMCM phase calibration
rx_cal_complete : out std_logic; -- RX data MMCM phase calibration complete
clk_tx_locked : out std_logic; -- TX data MMCM clock locked
clk_tx_phase : out std_logic_vector(9 downto 0); -- TX data MMCM phase offset, 0 - 559
tx_phase_init : in std_logic_vector(9 downto 0); -- TX data MMCM phase offset initialization, 0 - 559
tx_phase_incdec : in std_logic; -- '1' = Increment, '0' = Decrement
tx_phase_en : in std_logic; -- Increment / decrements TX data MMCM phase (Rising edge)
tx_phase_busy : out std_logic; -- TX data MMCM phase adjustment in process
tx_restart_cal : in std_logic; -- Restart TX data MMCM phase calibration
tx_cal_complete : out std_logic; -- TX data MMCM phase calibration complete
-- Receive data FIFO interface (all signals on clk_rx_fifo clock domain)
clk_rx_fifo : in std_logic; -- Receive data FIFO clock
rx_fifo_reset : in std_logic; -- Receive data FIFO reset
rx_fifo_data_i : out std_logic_vector(31 downto 0); -- Receive data FIFO output
rx_fifo_data_q : out std_logic_vector(31 downto 0); -- Receive data FIFO output
rx_fifo_rd_en : in std_logic; -- Receive data FIFO read enable
rx_fifo_underflow : out std_logic; -- Receive data FIFO underflow
rx_fifo_empty : out std_logic; -- Receive data FIFO empty
rx_fifo_almost_empty : out std_logic; -- Receive data FIFO almost empty
rx_fifo_overflow_latch : out std_logic; -- Receive data FIFO overflow (clears on reset)
rx_fifo_overflow_clr : in std_logic; -- Receive data FIFO clears overflow latch
-- Receive data FIFO interface (all signals on clk_tx_fifo clock domain)
clk_tx_fifo : in std_logic; -- Transmit data FIFO clock
tx_fifo_reset : in std_logic; -- Transmit data FIFO reset
tx_fifo_data_i : in std_logic_vector(31 downto 0); -- Transmit data FIFO output
tx_fifo_data_q : in std_logic_vector(31 downto 0); -- Transmit data FIFO output
tx_fifo_wr_en : in std_logic; -- Transmit data FIFO write enable
tx_fifo_overflow : out std_logic; -- Transmit data FIFO overflow
tx_fifo_full : out std_logic; -- Transmit data FIFO full
tx_fifo_almost_full : out std_logic; -- Transmit data FIFO almost full
tx_fifo_underflow_latch : out std_logic; -- Transmit data FIFO underflow (clears on reset)
tx_fifo_underflow_clr : in std_logic); -- Transmit data FIFO clears underflow latch
end component;
component synchronizer is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic := '0');
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic; -- Asynchronous input
sync : out std_logic); -- Synchronized output
end component;
component synchronizer_slv is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic_vector := "0");
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic_vector; -- Asynchronous input
sync : out std_logic_vector); -- Synchronized output
end component;
-----------------------------------------------------------------------------
-- Constants Declaration
-----------------------------------------------------------------------------
constant REG_USRP_MODE : std_logic_vector(31 downto 0) := x"00000001";
constant REG_RX_PKT_SIZE : std_logic_vector(31 downto 0) := x"00000002";
constant REG_RX_DECIM : std_logic_vector(31 downto 0) := x"00000003";
constant REG_RX_GAIN : std_logic_vector(31 downto 0) := x"00000004";
constant REG_TXRX_RESET : std_logic_vector(31 downto 0) := x"00000005";
constant REG_TX_INTERP : std_logic_vector(31 downto 0) := x"00000006";
constant REG_TX_GAIN : std_logic_vector(31 downto 0) := x"00000007";
constant REG_TXRX_MMCM_PHASE_INIT : std_logic_vector(31 downto 0) := x"00000008";
constant REG_TXRX_MMCM_PHASE_ADJ : std_logic_vector(31 downto 0) := x"00000009";
constant REG_MISC : std_logic_vector(31 downto 0) := x"0000000A";
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
type slv_32x256 is array(0 to 255) of std_logic_vector(31 downto 0);
signal ctrl_reg : slv_32x256 := (others=>(others=>'0'));
signal status_reg : slv_32x256 := (others=>(others=>'0'));
signal axis_master_tdest_hold : std_logic_vector(2 downto 0);
signal axis_master_tdest_safe : std_logic_vector(2 downto 0);
signal rst : std_logic;
signal usrp_mode_ctrl : std_logic_vector(7 downto 0);
signal usrp_mode_ctrl_en : std_logic;
signal usrp_mode_ctrl_ack : std_logic;
signal rx_enable : std_logic;
signal rx_gain : std_logic_vector(31 downto 0);
signal rx_cic_decim : std_logic_vector(10 downto 0);
signal rx_cic_decim_en : std_logic;
signal rx_cic_decim_ack : std_logic;
signal rx_fix2float_bypass : std_logic;
signal rx_cic_bypass : std_logic;
signal rx_hb_bypass : std_logic;
signal tx_enable : std_logic;
signal tx_gain : std_logic_vector(31 downto 0);
signal tx_cic_interp : std_logic_vector(10 downto 0);
signal tx_cic_interp_en : std_logic;
signal tx_cic_interp_ack : std_logic;
signal tx_float2fix_bypass : std_logic;
signal tx_cic_bypass : std_logic;
signal tx_hb_bypass : std_logic;
signal uart_busy : std_logic;
signal clk_rx_locked : std_logic;
signal clk_rx_phase : std_logic_vector(9 downto 0);
signal rx_phase_init : std_logic_vector(9 downto 0);
signal rx_phase_incdec : std_logic;
signal rx_phase_en : std_logic;
signal rx_phase_busy : std_logic;
signal rx_restart_cal : std_logic;
signal rx_cal_complete : std_logic;
signal clk_tx_locked : std_logic;
signal clk_tx_phase : std_logic_vector(9 downto 0);
signal tx_phase_init : std_logic_vector(9 downto 0);
signal tx_phase_incdec : std_logic;
signal tx_phase_en : std_logic;
signal tx_phase_busy : std_logic;
signal tx_restart_cal : std_logic;
signal tx_cal_complete : std_logic;
signal clk_rx_fifo : std_logic;
signal rx_fifo_reset : std_logic;
signal rx_fifo_data_i : std_logic_vector(31 downto 0);
signal rx_fifo_data_q : std_logic_vector(31 downto 0);
signal rx_fifo_rd_en : std_logic;
signal rx_fifo_underflow : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_fifo_empty_n : std_logic;
signal rx_fifo_almost_empty : std_logic;
signal rx_fifo_overflow_latch : std_logic;
signal rx_fifo_overflow_clr : std_logic;
signal clk_tx_fifo : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_fifo_data_i : std_logic_vector(31 downto 0);
signal tx_fifo_data_q : std_logic_vector(31 downto 0);
signal tx_fifo_wr_en : std_logic;
signal tx_fifo_overflow : std_logic;
signal tx_fifo_full : std_logic;
signal tx_fifo_almost_full : std_logic;
signal tx_fifo_underflow_latch : std_logic;
signal tx_fifo_underflow_clr : std_logic;
signal clk_ddr_locked : std_logic;
signal cal_complete : std_logic;
signal async : std_logic_vector(30 downto 0);
signal sync : std_logic_vector(30 downto 0);
signal usrp_mode_ctrl_ack_sync : std_logic;
signal rx_cic_decim_ack_sync : std_logic;
signal tx_cic_interp_ack_sync : std_logic;
signal rx_fifo_overflow_latch_sync : std_logic;
signal tx_fifo_underflow_latch_sync : std_logic;
signal clk_ddr_locked_sync : std_logic;
signal clk_rx_phase_sync : std_logic_vector(9 downto 0);
signal clk_tx_phase_sync : std_logic_vector(9 downto 0);
signal rx_cal_complete_sync : std_logic;
signal tx_cal_complete_sync : std_logic;
signal rx_phase_busy_sync : std_logic;
signal tx_phase_busy_sync : std_logic;
signal uart_busy_sync : std_logic;
signal rx_fifo_bypass : std_logic;
signal rx_enable_sideband : std_logic;
signal tx_enable_sideband : std_logic;
signal rx_enable_aux_reg : std_logic;
signal tx_enable_aux_reg : std_logic;
signal rx_packet_size : std_logic_vector(23 downto 0);
signal rx_fifo_cnt : integer;
begin
rst <= NOT(rst_n);
axis_master_irq <= '0';
axis_slave_irq <= '0';
-- Sychronizers to cross clock domains
inst_synchronizer_slv : synchronizer_slv
port map (
clk => clk,
reset => rst,
async => async,
sync => sync);
async(0) <= rx_cic_decim_ack;
async(1) <= tx_cic_interp_ack;
async(2) <= usrp_mode_ctrl_ack;
async(12 downto 3) <= clk_rx_phase;
async(22 downto 13) <= clk_tx_phase;
async(23) <= rx_phase_busy;
async(24) <= tx_phase_busy;
async(25) <= uart_busy;
async(26) <= clk_ddr_locked;
async(27) <= rx_cal_complete;
async(28) <= tx_cal_complete;
rx_cic_decim_ack_sync <= sync(0);
tx_cic_interp_ack_sync <= sync(1);
usrp_mode_ctrl_ack_sync <= sync(2);
clk_rx_phase_sync <= sync(12 downto 3);
clk_tx_phase_sync <= sync(22 downto 13);
rx_phase_busy_sync <= sync(23);
tx_phase_busy_sync <= sync(24);
uart_busy_sync <= sync(25);
clk_ddr_locked_sync <= sync(26);
rx_cal_complete_sync <= sync(27);
tx_cal_complete_sync <= sync(28);
clk_ddr_locked <= clk_rx_locked AND clk_tx_locked;
-------------------------------------------------------------------------------
-- Enable and Acknowledge Signals
-------------------------------------------------------------------------------
proc_enable_and_ack : process(clk,rst)
begin
if (rst = '1') then
usrp_mode_ctrl_en <= '0';
rx_cic_decim_en <= '0';
tx_cic_interp_en <= '0';
else
if rising_edge(clk) then
-- Set the required enables to update the registers.
-- Deassert enables only after acknowledgement.
-- Bank 3 is Decimation & Interpolation Rate
if (ctrl_stb = '1' AND ctrl_addr = x"03") then
rx_cic_decim_en <= '1';
end if;
if (rx_cic_decim_ack_sync = '1') then
rx_cic_decim_en <= '0';
end if;
-- Bank 3 is Decimation & Interpolation Rate
if (ctrl_stb = '1' AND ctrl_addr = x"03") then
tx_cic_interp_en <= '1';
end if;
if (tx_cic_interp_ack_sync = '1') then
tx_cic_interp_en <= '0';
end if;
-- Bank 1 is USRP mode
if (ctrl_stb = '1' AND ctrl_addr = x"01") then
usrp_mode_ctrl_en <= '1';
end if;
if (usrp_mode_ctrl_ack_sync = '1') then
usrp_mode_ctrl_en <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- AXIS Stream to TX Data
-------------------------------------------------------------------------------
clk_tx_fifo <= clk;
tx_fifo_data_q <= axis_slave_tdata(63 downto 32);
tx_fifo_data_i <= axis_slave_tdata(31 downto 0);
tx_fifo_wr_en <= axis_slave_tvalid;
axis_slave_tready <= NOT(tx_fifo_full);
-------------------------------------------------------------------------------
-- RX Data to AXIS Stream
-------------------------------------------------------------------------------
-- This counter below is used to assert the tlast signal at the end of the transfer.
proc_gen_axis_stream : process(clk,rst)
begin
if (rst = '1') then
rx_fifo_cnt <= 0;
else
if rising_edge(clk) then
if (rx_enable = '0') then
rx_fifo_cnt <= to_integer(unsigned(rx_packet_size));
else
-- Decrement only on successful reads from the FIFO
if (axis_master_tready = '1' AND rx_fifo_empty = '0') then
rx_fifo_cnt <= rx_fifo_cnt - 1;
if (rx_fifo_cnt = 1) then
rx_fifo_cnt <= to_integer(unsigned(rx_packet_size));
end if;
end if;
end if;
end if;
end if;
end process;
rx_fifo_rd_en <= (axis_master_tready OR rx_fifo_bypass) AND NOT(rx_fifo_empty) AND rx_enable;
axis_master_tdata <= rx_fifo_data_q & rx_fifo_data_i;
axis_master_tvalid <= (NOT(rx_fifo_empty) AND rx_enable);
axis_master_tlast <= '1' when rx_fifo_cnt = 1 AND rx_enable = '1' else '0';
axis_master_tdest <= axis_master_tdest_safe;
-------------------------------------------------------------------------------
-- USRP DDR Interface Instance
-------------------------------------------------------------------------------
inst_usrp_ddr_intf : usrp_ddr_intf
generic map (
DDR_CLOCK_FREQ => DDR_CLOCK_FREQ,
BAUD => BAUD)
port map (
reset => rst,
usrp_mode_ctrl => usrp_mode_ctrl,
usrp_mode_ctrl_en => usrp_mode_ctrl_en,
usrp_mode_ctrl_ack => usrp_mode_ctrl_ack,
rx_enable => rx_enable,
rx_gain => rx_gain,
rx_cic_decim => rx_cic_decim,
rx_cic_decim_en => rx_cic_decim_en,
rx_cic_decim_ack => rx_cic_decim_ack,
rx_fix2float_bypass => rx_fix2float_bypass,
rx_cic_bypass => rx_cic_bypass,
rx_hb_bypass => rx_hb_bypass,
tx_enable => tx_enable,
tx_gain => tx_gain,
tx_cic_interp => tx_cic_interp,
tx_cic_interp_en => tx_cic_interp_en,
tx_cic_interp_ack => tx_cic_interp_ack,
tx_float2fix_bypass => tx_float2fix_bypass,
tx_cic_bypass => tx_cic_bypass,
tx_hb_bypass => tx_hb_bypass,
uart_busy => uart_busy,
UART_TX => UART_TX,
RX_DATA_CLK_N => RX_DATA_CLK_N,
RX_DATA_CLK_P => RX_DATA_CLK_P,
RX_DATA_N => RX_DATA_N,
RX_DATA_P => RX_DATA_P,
RX_DATA_STB_N => RX_DATA_STB_N,
RX_DATA_STB_P => RX_DATA_STB_P,
TX_DATA_N => TX_DATA_N,
TX_DATA_P => TX_DATA_P,
TX_DATA_STB_N => TX_DATA_STB_N,
TX_DATA_STB_P => TX_DATA_STB_P,
clk_rx_locked => clk_rx_locked,
clk_rx_phase => clk_rx_phase,
rx_phase_init => rx_phase_init,
rx_phase_incdec => rx_phase_incdec,
rx_phase_en => rx_phase_en,
rx_phase_busy => rx_phase_busy,
rx_restart_cal => rx_restart_cal,
rx_cal_complete => rx_cal_complete,
clk_tx_locked => clk_tx_locked,
clk_tx_phase => clk_tx_phase,
tx_phase_init => tx_phase_init,
tx_phase_incdec => tx_phase_incdec,
tx_phase_en => tx_phase_en,
tx_phase_busy => tx_phase_busy,
tx_restart_cal => tx_restart_cal,
tx_cal_complete => tx_cal_complete,
clk_rx_fifo => clk,
rx_fifo_reset => rx_fifo_reset,
rx_fifo_data_i => rx_fifo_data_i,
rx_fifo_data_q => rx_fifo_data_q,
rx_fifo_rd_en => rx_fifo_rd_en,
rx_fifo_underflow => rx_fifo_underflow,
rx_fifo_empty => rx_fifo_empty,
rx_fifo_almost_empty => rx_fifo_almost_empty,
rx_fifo_overflow_latch => rx_fifo_overflow_latch,
rx_fifo_overflow_clr => rx_fifo_overflow_clr,
clk_tx_fifo => clk,
tx_fifo_reset => tx_fifo_reset,
tx_fifo_data_i => tx_fifo_data_i,
tx_fifo_data_q => tx_fifo_data_q,
tx_fifo_wr_en => tx_fifo_wr_en,
tx_fifo_overflow => tx_fifo_overflow,
tx_fifo_full => tx_fifo_full,
tx_fifo_almost_full => tx_fifo_almost_full,
tx_fifo_underflow_latch => tx_fifo_underflow_latch,
tx_fifo_underflow_clr => tx_fifo_underflow_clr);
-------------------------------------------------------------------------------
-- Control and status registers.
-------------------------------------------------------------------------------
proc_ctrl_status_reg : process(clk,rst)
begin
if (rst = '1') then
ctrl_reg <= (others=>(others=>'0'));
axis_master_tdest_safe <= (others=>'0');
rx_enable_aux_reg <= '0';
tx_enable_aux_reg <= '0';
else
if rising_edge(clk) then
-- Update control registers only when accessed
if (ctrl_stb = '1') then
ctrl_reg(to_integer(unsigned(ctrl_addr(7 downto 0)))) <= ctrl_data;
end if;
-- Output status register
if (status_stb = '1') then
status_data <= status_reg(to_integer(unsigned(status_addr(7 downto 0))));
end if;
-- The destination can only update when no data is being transmitted, i.e. RX disabled
if (rx_enable = '0') then
axis_master_tdest_safe <= axis_master_tdest_hold;
end if;
-- Register sideband signals
if (rx_enable_sideband = '1') then
rx_enable_aux_reg <= rx_enable_aux;
else
rx_enable_aux_reg <= '0';
end if;
if (tx_enable_sideband = '1') then
tx_enable_aux_reg <= tx_enable_aux;
else
tx_enable_aux_reg <= '0';
end if;
end if;
end if;
end process;
-- Control Registers
-- Bank 0 (RX & TX Enable, and output destination)
rx_enable <= ctrl_reg(0)(0) OR rx_enable_aux_reg;
tx_enable <= ctrl_reg(0)(1) OR tx_enable_aux_reg;
rx_enable_sideband <= ctrl_reg(0)(2);
tx_enable_sideband <= ctrl_reg(0)(3);
rx_fifo_reset <= ctrl_reg(0)(4);
tx_fifo_reset <= ctrl_reg(0)(5);
rx_fifo_bypass <= ctrl_reg(0)(6);
rx_fifo_overflow_clr <= ctrl_reg(0)(7);
tx_fifo_underflow_clr <= ctrl_reg(0)(8);
axis_master_tdest_hold <= ctrl_reg(0)(31 downto 29);
-- Bank 1 (USRP Mode)
usrp_mode_ctrl <= ctrl_reg(1)(7 downto 0);
-- Bank 2 (RX & TX Floating Point Bypass, RX Packet Size)
rx_packet_size <= ctrl_reg(2)(23 downto 0);
rx_fix2float_bypass <= ctrl_reg(2)(24);
rx_cic_bypass <= ctrl_reg(2)(25);
rx_hb_bypass <= ctrl_reg(2)(26);
tx_float2fix_bypass <= ctrl_reg(2)(27);
tx_cic_bypass <= ctrl_reg(2)(28);
tx_hb_bypass <= ctrl_reg(2)(29);
-- Bank 3 (Decimation and Interpolation Rate)
rx_cic_decim <= ctrl_reg(3)(10 downto 0);
tx_cic_interp <= ctrl_reg(3)(26 downto 16);
-- Bank 4 (RX Gain)
rx_gain <= ctrl_reg(4);
-- Bank 5 (TX Gain)
tx_gain <= ctrl_reg(5);
-- Bank 6 (MMCM Phase Setting & Manual Adjustment)
rx_restart_cal <= ctrl_reg(6)(0);
rx_phase_init <= ctrl_reg(6)(10 downto 1);
tx_restart_cal <= ctrl_reg(6)(16);
tx_phase_init <= ctrl_reg(6)(26 downto 17);
rx_phase_en <= ctrl_reg(6)(28);
rx_phase_incdec <= ctrl_reg(6)(29);
tx_phase_en <= ctrl_reg(6)(30);
tx_phase_incdec <= ctrl_reg(6)(31);
-- Status Registers
-- Bank 0 (RX & TX Enable, and output destination Readback)
status_reg(0)(0) <= rx_enable;
status_reg(0)(1) <= tx_enable;
status_reg(0)(2) <= rx_enable_sideband;
status_reg(0)(3) <= tx_enable_sideband;
status_reg(0)(4) <= rx_fifo_reset;
status_reg(0)(5) <= tx_fifo_reset;
status_reg(0)(6) <= rx_fifo_bypass;
status_reg(0)(7) <= rx_fifo_overflow_clr;
status_reg(0)(8) <= tx_fifo_underflow_clr;
status_reg(0)(31 downto 29) <= axis_master_tdest_safe;
-- Bank 1 (USRP Mode Readback)
status_reg(1)(7 downto 0) <= usrp_mode_ctrl;
-- Bank 2 (RX & TX Floating Point Bypass, RX Packet Size Readback)
status_reg(2)(23 downto 0) <= rx_packet_size;
status_reg(2)(24) <= rx_fix2float_bypass;
status_reg(2)(25) <= rx_cic_bypass;
status_reg(2)(26) <= rx_hb_bypass;
status_reg(2)(27) <= tx_float2fix_bypass;
status_reg(2)(28) <= tx_cic_bypass;
status_reg(2)(29) <= tx_hb_bypass;
-- Bank 3 (Decimation and Interpolation Rate Readback)
status_reg(3)(10 downto 0) <= rx_cic_decim;
status_reg(3)(26 downto 16) <= tx_cic_interp;
-- Bank 4 (RX Gain Readback)
status_reg(4) <= rx_gain;
-- Bank 5 (TX Gain Readback)
status_reg(5) <= tx_gain;
-- Bank 6 (MMCM Phase Setting & Manual Adjustment Readback)
status_reg(6)(0) <= rx_restart_cal;
status_reg(6)(10 downto 1) <= rx_phase_init;
status_reg(6)(16) <= tx_restart_cal;
status_reg(6)(26 downto 17) <= tx_phase_init;
status_reg(6)(28) <= rx_phase_en;
status_reg(6)(29) <= rx_phase_incdec;
status_reg(6)(30) <= tx_phase_en;
status_reg(6)(31) <= tx_phase_incdec;
-- Bank 7
status_reg(7)(0) <= clk_ddr_locked_sync;
status_reg(7)(1) <= rx_fifo_overflow_latch;
status_reg(7)(2) <= tx_fifo_underflow_latch;
status_reg(7)(3) <= rx_cal_complete_sync;
status_reg(7)(4) <= tx_cal_complete_sync;
status_reg(7)(5) <= rx_phase_busy_sync;
status_reg(7)(6) <= tx_phase_busy_sync;
status_reg(7)(7) <= uart_busy_sync;
status_reg(7)(19 downto 10) <= clk_rx_phase_sync;
status_reg(7)(29 downto 20) <= clk_tx_phase_sync;
end architecture; | gpl-3.0 | f2c7975377e01c33d4fe9222fb4879b3 | 0.446858 | 4.166164 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20_info_device_0_avalon_slave_translator.vhd | 1 | 14,655 | -- cb20_info_device_0_avalon_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 5;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(4 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_info_device_0_avalon_slave_translator;
architecture rtl of cb20_info_device_0_avalon_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
info_device_0_avalon_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_info_device_0_avalon_slave_translator
| apache-2.0 | 292c854a28891d3c8a4b8c2bc277ed35 | 0.429887 | 4.348665 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/free_queue/vhdl_source/block_bus_pkg.vhd | 1 | 1,312 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : free_queue
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: A simple source of free memory blocks. Software provides, hardware uses.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package block_bus_pkg is
type t_alloc_resp is record
done : std_logic;
error : std_logic;
id : unsigned(7 downto 0);
address : unsigned(25 downto 0);
end record;
type t_used_req is record
request : std_logic;
id : unsigned(7 downto 0);
bytes : unsigned(11 downto 0);
end record;
constant c_alloc_resp_init : t_alloc_resp := (
done => '0',
error => '0',
id => X"00",
address => (others => '0') );
constant c_used_req_init : t_used_req := (
request => '0',
id => X"00",
bytes => X"000" );
end package;
| gpl-3.0 | 5f1dec1161ff5bdc5a8a82cb00cd75e8 | 0.411585 | 4.652482 | false | false | false | false |
armandas/Arcade | menu.vhd | 1 | 6,318 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity menu is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
nes_up, nes_down: in std_logic;
selection: out std_logic;
rgb_pixel: out std_logic_vector(2 downto 0)
);
end menu;
architecture behaviour of menu is
type rom_type is array(0 to 32) of std_logic_vector(8 downto 0);
constant CREDITS: rom_type :=
(
"000000000",
"100001000",
"110010000",
"101101000",
"100001000",
"101110000",
"100100000",
"100001000",
"110011000",
"000000000",
"101010000",
"100001000",
"110010000",
"110101000",
"110011000",
"100001000",
"110101000",
"110011000",
"101011000",
"100001000",
"110011000",
"001100000",
"000000000",
"010010000",
"010000000",
"010001000",
"010000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000"
);
signal credits_addr: std_logic_vector(6 downto 0);
signal font_addr: std_logic_vector(8 downto 0);
signal font_data: std_logic_vector(0 to 7);
signal font_pixel: std_logic;
-- logo pixel is separate because of scaling
signal logo_pixel: std_logic;
signal arrow_pos, arrow_pos_next: std_logic;
signal logo_on,
plong_text_on,
fpgalaxy_text_on,
arrow_on,
credits_on,
hr_on: std_logic;
signal logo_font_addr,
plong_text_font_addr,
fpgalaxy_text_font_addr,
arrow_font_addr: std_logic_vector(8 downto 0);
signal logo_rgb, font_rgb: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
arrow_pos <= '0';
elsif falling_edge(clk) then
arrow_pos <= arrow_pos_next;
end if;
end process;
logo_on <= '1' when (px_x >= 128 and
px_x < 512 and
px_y >= 64 and
px_y < 128) else
'0';
plong_text_on <= '1' when (px_x >= 280 and
px_x < 320 and
px_y >= 272 and
px_y < 280) else
'0';
fpgalaxy_text_on <= '1' when (px_x >= 280 and
px_x < 344 and
px_y >= 288 and
px_y < 296) else
'0';
arrow_pos_next <= '1' when nes_down = '1' else
'0' when nes_up = '1' else
arrow_pos;
arrow_on <= '1' when (arrow_pos = '0' and
px_x >= 264 and
px_x < 272 and
px_y >= 272 and
px_y < 280) or
(arrow_pos = '1' and
px_x >= 264 and
px_x < 272 and
px_y >= 288 and
px_y < 296) else
'0';
credits_on <= '1' when (px_x >= 0 and
px_x < 256 and
px_y >= 472 and
px_y < 480) else
'0';
-- horizontal rule
hr_on <= '1' when px_y > 470 else '0';
with px_x(9 downto 6) select
logo_font_addr <= "010010000" when "0010", -- 2
"101001000" when "0100", -- I
"101110000" when "0101", -- N
"010001000" when "0111", -- 1
"000000000" when others; -- spaces
with px_x(9 downto 3) select
plong_text_font_addr <= "110000000" when "0100011", -- P
"101100000" when "0100100", -- L
"101111000" when "0100101", -- O
"101110000" when "0100110", -- N
"100111000" when "0100111", -- G
"000000000" when others;
with px_x(9 downto 3) select
fpgalaxy_text_font_addr <= "100110000" when "0100011", -- F
"110000000" when "0100100", -- P
"100111000" when "0100101", -- G
"100001000" when "0100110", -- A
"101100000" when "0100111", -- L
"100001000" when "0101000", -- A
"111000000" when "0101001", -- X
"111001000" when "0101010", -- Y
"000000000" when others;
-- single symbol
arrow_font_addr <= "111100000";
credits_addr <= px_x(9 downto 3) when px_x(9 downto 3) < 33 else
(others => '0');
font_addr <= px_y(5 downto 3) + logo_font_addr when logo_on = '1' else
px_y(2 downto 0) + plong_text_font_addr when plong_text_on = '1' else
px_y(2 downto 0) + fpgalaxy_text_font_addr when fpgalaxy_text_on = '1' else
px_y(2 downto 0) + arrow_font_addr when arrow_on = '1' else
px_y(2 downto 0) + CREDITS(conv_integer(credits_addr)) when credits_on = '1' else
(others => '0');
logo_pixel <= font_data(conv_integer(px_x(5 downto 3)));
logo_rgb <= "111" when logo_pixel = '1' else "000";
font_pixel <= font_data(conv_integer(px_x(2 downto 0)));
font_rgb <= "111" when font_pixel = '1' else "000";
rgb_pixel <= logo_rgb when logo_on = '1' else
font_rgb when (plong_text_on = '1' or
fpgalaxy_text_on = '1' or
arrow_on = '1') else
not font_rgb when credits_on = '1' else
"111" when hr_on = '1' else
(others => '0');
selection <= arrow_pos;
codepage:
entity work.codepage_rom(content)
port map(addr => font_addr, data => font_data);
end behaviour; | bsd-2-clause | 96f8ef3654b4588d6d02c0ad9fed734c | 0.43748 | 4.113281 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/uart_lite/vhdl_source/uart_peripheral_io.vhd | 1 | 5,531 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity uart_peripheral_io is
generic (
g_impl_irq : boolean := false;
g_impl_rx : boolean := true;
g_tx_fifo : boolean := true;
g_divisor : natural := 35 );
port (
clock : in std_logic;
reset : in std_logic;
tick : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
irq : out std_logic;
txd : out std_logic;
rxd : in std_logic := '1';
rts : out std_logic;
cts : in std_logic := '1' );
end uart_peripheral_io;
architecture gideon of uart_peripheral_io is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic := '0';
signal rxfifo_get : std_logic := '0';
signal rxfifo_dout : std_logic_vector(7 downto 0) := X"00";
signal rxfifo_full : std_logic := '0';
signal rxfifo_dav : std_logic := '0';
signal overflow : std_logic := '0';
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(1 downto 0) := "00";
signal rdata_mux : std_logic_vector(7 downto 0);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
constant c_uart_data : unsigned(1 downto 0) := "00";
constant c_uart_get : unsigned(1 downto 0) := "01";
constant c_uart_flags : unsigned(1 downto 0) := "10";
constant c_uart_imask : unsigned(1 downto 0) := "11";
begin
my_tx: entity work.tx
generic map (g_divisor)
port map (
clk => clock,
reset => reset,
tick => tick,
dotx => dotx,
txchar => txchar,
cts => cts,
txd => txd,
done => done );
r_rx: if g_impl_rx generate
my_rx: entity work.rx
generic map (g_divisor)
port map (
clk => clock,
reset => reset,
tick => tick,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
end generate;
gentx: if g_tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => io_req.data,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
io_resp <= c_io_resp_init;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
txfifo_put <= '0';
if g_tx_fifo then
dotx <= txfifo_dav and done and not dotx;
txchar <= txfifo_dout;
else
dotx <= '0'; -- default, overridden with write
end if;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(1 downto 0) is
when c_uart_data => -- dout
if not g_tx_fifo then
txchar <= io_req.data;
dotx <= '1';
else -- there is a fifo
txfifo_put <= '1';
end if;
when c_uart_get => -- din
rxfifo_get <= '1';
when c_uart_flags => -- clear flags
overflow <= overflow and not io_req.data(0);
when c_uart_imask => -- interrupt control
if g_impl_irq then
imask <= io_req.data(1 downto 0);
end if;
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
io_resp.data <= rdata_mux;
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
irq <= (flags(6) and imask(1)) or (flags(7) and imask(0));
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
rts <= not rxfifo_full;
with io_req.address(1 downto 0) select rdata_mux <=
rxfifo_dout when c_uart_data,
flags when c_uart_flags,
"000000" & imask when c_uart_imask,
X"00" when others;
end gideon;
| gpl-3.0 | 8150f33b60903e5d02496f0322fd5594 | 0.480745 | 3.431141 | false | false | false | false |
trondd/mkjpeg | design/rle/RleDoubleFifo.vhd | 2 | 6,535 | -------------------------------------------------------------------------------
-- File Name : RleDoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : RleDoubleFifo
--
-- Content : RleDoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity RleDoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(19 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(19 downto 0)
);
end entity RleDoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of RleDoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(19 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(6 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(19 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(6 downto 0);
signal fifo_data_in : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 20,
ADDR_WIDTH => 6
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
--data_out <= (others => '0');
--fifo1_rd <= '0';
--fifo2_rd <= '0';
--fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
--data_out <= fifo1_q;
--fifo1_rd <= rd_req;
--fifo_empty <= fifo1_empty;
else
--data_out <= fifo2_q;
--fifo2_rd <= rd_req;
--fifo_empty <= fifo2_empty;
end if;
end if;
end process;
fifo1_rd <= rd_req when buf_sel = '1' else '0';
fifo2_rd <= rd_req when buf_sel = '0' else '0';
data_out <= fifo1_q when buf_sel = '1' else fifo2_q;
fifo_empty <= fifo1_empty when buf_sel = '1' else fifo2_empty;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | 46070b5c788e30d38b028164e4dc130a | 0.276358 | 5.360952 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/mem_ctrl/vhdl_source/fpga_mem_test_v5.vhd | 2 | 2,988 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v5 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
DISK_ACTn : out std_logic );
end fpga_mem_test_v5;
architecture tb of fpga_mem_test_v5 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_req_32 := c_mem_req_32_init;
signal resp : t_mem_resp_32;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_v5
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
inhibit => inhibit,
run => MOTOR_LEDn,
okay => okay );
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
DISK_ACTn <= not okay;
end;
| gpl-3.0 | 66b567060fe929d7d79fb24aa7e08068 | 0.435074 | 3.716418 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_sim/tb_ulpi_host.vhd | 2 | 9,982 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
use work.tl_vector_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity tb_ulpi_host is
end ;
architecture tb of tb_ulpi_host is
signal clock : std_logic := '0';
signal reset : std_logic;
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(11 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_valid : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
begin
i_mut: entity work.usb1_ulpi_host
port map (
clock => clock,
reset => reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
do_reset => open,
power_en => open,
reset_done => '1',
speed => "10",
reset_pkt => '0',
reset_data => X"00",
reset_last => '0',
reset_valid => '0',
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_descr_ram: entity work.bram_model_32sp
generic map("descriptors", 9)
port map (
CLK => clock,
SSR => reset,
EN => descr_en,
WE => descr_we,
ADDR => descr_addr,
DI => descr_wdata,
DO => descr_rdata );
i_buf_ram: entity work.bram_model_8sp
generic map("buffer", 12)
port map (
CLK => clock,
SSR => reset,
EN => buf_en,
WE => buf_we,
ADDR => buf_addr,
DI => buf_wdata,
DO => buf_rdata );
b_tx_bfm: block
signal tx_delay : integer range 0 to 31 := 0;
begin
process(clock)
begin
if rising_edge(clock) then
tx_ack <= '0';
user_next <= '0';
if tx_delay = 28 then -- transmit packet
user_next <= '1';
if user_last='1' and user_valid='1' then
tx_delay <= 0; -- done;
user_next <= '0';
end if;
elsif tx_delay = 0 then
if send_token='1' then
tx_delay <= 6;
tx_ack <= '1';
elsif send_handsh='1' then
tx_delay <= 4;
tx_ack <= '1';
elsif send_data='1' then
tx_ack <= '1';
if no_data='1' then
tx_delay <= 5;
else
tx_delay <= 31;
end if;
end if;
else
tx_delay <= tx_delay - 1;
end if;
end if;
end process;
tx_busy <= '0' when tx_delay = 0 else '1';
end block;
p_test: process
variable desc : h_mem_object;
variable buf : h_mem_object;
procedure packet(pkt : t_std_logic_8_vector) is
begin
for i in pkt'range loop
wait until clock='1';
data_out <= pkt(i);
data_valid <= '1';
if i = pkt'left then
data_start <= '1';
else
data_start <= '0';
end if;
end loop;
wait until clock='1';
data_valid <= '0';
data_start <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
end procedure packet;
begin
bind_mem_model("descriptors", desc);
bind_mem_model("buffer", buf);
wait until reset='0';
write_memory_32(desc, X"0000_0100", t_transaction_to_data((
transaction_type => control,
state => busy, -- activate
pipe_pointer => "00000",
transfer_length => to_unsigned(8, 11),
buffer_address => to_unsigned(100, 12) )));
write_memory_32(desc, X"0000_0104", t_transaction_to_data((
transaction_type => bulk,
state => busy, -- activate
pipe_pointer => "00001",
transfer_length => to_unsigned(60, 11),
buffer_address => to_unsigned(256, 12) )));
write_memory_32(desc, X"0000_0000", t_pipe_to_data((
state => initialized,
direction => dir_out,
device_address => (others => '0'),
device_endpoint => (others => '0'),
max_transfer => to_unsigned(64, 11),
data_toggle => '0' ) ));
write_memory_32(desc, X"0000_0004", t_pipe_to_data((
state => initialized,
direction => dir_out,
device_address => (others => '0'),
device_endpoint => (others => '0'),
max_transfer => to_unsigned(8, 11),
data_toggle => '0' ) ));
for i in 0 to 7 loop
write_memory_8(buf, std_logic_vector(to_unsigned(100+i,32)),
std_logic_vector(to_unsigned(33+i,8)));
end loop;
wait until tx_busy='0'; -- first sof token
wait until tx_busy='0'; -- setup token
wait until tx_busy='0'; -- setup data
wait until tx_busy='0'; -- retried setup token
wait until tx_busy='0'; -- retried setup data
wait until clock='1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
valid_handsh <= '1';
rx_pid <= c_pid_ack;
wait until clock='1';
valid_handsh <= '0';
-- control out
for i in 0 to 7 loop
wait until tx_busy='0'; -- out token
wait until tx_busy='0'; -- out data
wait until clock='1';
wait until clock='1';
wait until clock='1';
valid_handsh <= '1';
rx_pid <= c_pid_ack;
wait until clock='1';
valid_handsh <= '0';
end loop;
wait until tx_busy='0'; -- in token
assert tx_pid = c_pid_in
report "Expected in token! (pid = " & hstr(tx_pid) & ")"
severity error;
wait until clock='1';
wait until clock='1';
wait until clock='1';
valid_packet <= '1';
wait until clock='1';
valid_packet <= '0';
-- -- control in..
-- wait until send_token='1';
-- wait until tx_busy='0'; -- in token done
-- wait until clock='1';
-- wait until clock='1';
-- wait until clock='1';
-- packet((X"01", X"02", X"03", X"04", X"05", X"06"));
-- valid_packet <= '1';
-- wait until clock='1';
-- valid_packet <= '0';
wait;
end process;
end tb;
| gpl-3.0 | 3953d903d408f953192abbb33e068e34 | 0.443098 | 3.942338 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20_altpll_0_pll_slave_translator.vhd | 1 | 14,475 | -- cb20_altpll_0_pll_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.11.08:07:37
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_altpll_0_pll_slave_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(1 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(3 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_altpll_0_pll_slave_translator;
architecture rtl of cb20_altpll_0_pll_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
altpll_0_pll_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_altpll_0_pll_slave_translator
| apache-2.0 | 3bb107056230b04c85909d0238632ec1 | 0.42943 | 4.324768 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/nios_rst_controller_002.vhd | 1 | 9,037 | -- nios_rst_controller_002.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_rst_controller_002 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity nios_rst_controller_002;
architecture rtl of nios_rst_controller_002 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_002 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of nios_rst_controller_002
| gpl-3.0 | 01205cc1140b5d46e3b1293cd6e9d271 | 0.547416 | 2.72445 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/all_carts_v5.vhd | 1 | 32,834 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
use work.io_bus_pkg.all;
entity all_carts_v5 is
generic (
g_eeprom : boolean := true;
g_kernal_base : std_logic_vector(27 downto 0) := X"0EC8000"; -- multiple of 32K
g_rom_base : std_logic_vector(27 downto 0) := X"0F00000"; -- multiple of 1M
g_georam_base : std_logic_vector(27 downto 0) := X"1000000"; -- Shared with reu
g_ram_base : std_logic_vector(27 downto 0) := X"0EF0000" ); -- multiple of 64K
port (
clock : in std_logic;
reset : in std_logic;
io_req_eeprom : in t_io_req;
io_resp_eeprom : out t_io_resp := c_io_resp_init;
RST_in : in std_logic;
c64_reset : in std_logic;
kernal_enable : in std_logic;
kernal_area : in std_logic;
freeze_trig : in std_logic; -- goes '1' when the button has been pressed and we're waiting to enter the freezer
freeze_act : in std_logic; -- goes '1' when we need to switch in the cartridge for freeze mode
unfreeze : out std_logic; -- indicates the freeze logic to switch back to non-freeze mode.
cart_active : out std_logic; -- indicates that the cartridge is active
cart_kill : in std_logic;
cart_logic : in std_logic_vector(4 downto 0); -- 1 out of 32 logic emulations
cart_variant : in std_logic_vector(2 downto 0); -- max 8 variants for one emulation class
cart_force : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp := c_slot_resp_init;
epyx_timeout : in std_logic;
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_128 : out std_logic; -- 8000-FFFF
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
mem_addr : out unsigned(25 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic;
size_ctrl : in std_logic_vector(2 downto 0) := "001" );
end all_carts_v5;
architecture gideon of all_carts_v5 is
signal reset_in : std_logic;
signal rom_mode : std_logic_vector(14 downto 13) := "11";
signal bank_bits : std_logic_vector(19 downto 13);
signal ram_bank : std_logic_vector(15 downto 13) := "000";
signal mode_bits : std_logic_vector(2 downto 0);
signal ef_write : std_logic := '0';
signal georam_bank : std_logic_vector(15 downto 0);
signal freeze_act_d : std_logic;
signal cart_en : std_logic;
signal do_io2 : std_logic;
signal allow_bank : std_logic;
signal hold_nmi : std_logic;
signal mem_addr_i : std_logic_vector(27 downto 0);
signal rom_addr : std_logic_vector(27 downto 0);
signal ram_addr : std_logic_vector(27 downto 0);
signal cart_logic_d : std_logic_vector(cart_logic'range) := (others => '0');
signal variant : std_logic_vector(cart_variant'range) := (others => '0');
signal ee_clk, ee_sel : std_logic;
signal ee_rdata, ee_wdata : std_logic;
-- Ultra Simple
constant c_none : std_logic_vector(4 downto 0) := "00000";
constant c_normal : std_logic_vector(4 downto 0) := "00001";
constant c_epyx : std_logic_vector(4 downto 0) := "00010";
constant c_128 : std_logic_vector(4 downto 0) := "00011";
constant c_westermann : std_logic_vector(4 downto 0) := "00100"; -- also blackbox v4 with variant
constant c_sbasic : std_logic_vector(4 downto 0) := "00101";
constant c_bbasic : std_logic_vector(4 downto 0) := "00110";
constant c_blackbox_v3 : std_logic_vector(4 downto 0) := "00111";
-- Simple banking
constant c_ocean_8K : std_logic_vector(4 downto 0) := "01000";
constant c_ocean_16K : std_logic_vector(4 downto 0) := "01001";
constant c_system3 : std_logic_vector(4 downto 0) := "01010";
constant c_supergames : std_logic_vector(4 downto 0) := "01011";
constant c_blackbox_v8 : std_logic_vector(4 downto 0) := "01100";
constant c_zaxxon : std_logic_vector(4 downto 0) := "01101";
-- Simple bankers with RAM
constant c_pagefox : std_logic_vector(4 downto 0) := "10000";
constant c_easy_flash : std_logic_vector(4 downto 0) := "10001";
-- Freezers
constant c_fc : std_logic_vector(4 downto 0) := "11000";
constant c_fc3 : std_logic_vector(4 downto 0) := "11001";
constant c_ss5 : std_logic_vector(4 downto 0) := "11010";
constant c_action : std_logic_vector(4 downto 0) := "11011";
constant c_kcs : std_logic_vector(4 downto 0) := "11100";
-- Exotics
constant c_georam : std_logic_vector(4 downto 0) := "11111";
constant c_serve_rom_rr : std_logic_vector(0 to 7) := "11011111";
constant c_serve_io_rr : std_logic_vector(0 to 7) := "10101111";
type t_address_select is ( ROM, RAM, GEO );
signal addr_map : t_address_select;
-- alias
signal slot_addr : std_logic_vector(15 downto 0);
signal slot_rwn : std_logic;
signal io_read : std_logic;
signal io_write : std_logic;
signal io_addr : std_logic_vector(8 downto 0);
signal io_wdata : std_logic_vector(7 downto 0);
signal georam_mask : std_logic_vector(15 downto 0);
begin
with size_ctrl select georam_mask <=
"0000000111111111" when "000",
"0000001111111111" when "001",
"0000011111111111" when "010",
"0000111111111111" when "011",
"0001111111111111" when "100",
"0011111111111111" when "101",
"0111111111111111" when "110",
"1111111111111111" when others;
serve_enable <= cart_en or kernal_enable;
cart_active <= cart_en;
slot_addr <= std_logic_vector(slot_req.bus_address);
slot_rwn <= slot_req.bus_rwn;
io_write <= slot_req.io_write;
io_read <= slot_req.io_read;
io_addr <= std_logic_vector(slot_req.io_address(8 downto 0));
io_wdata <= slot_req.data;
process(clock)
variable v_addr4 : std_logic_vector(3 downto 0);
begin
if rising_edge(clock) then
reset_in <= reset or RST_in or c64_reset;
freeze_act_d <= freeze_act;
unfreeze <= '0';
-- control register
if freeze_act='1' and freeze_act_d='0' then
bank_bits <= (others => '0');
ram_bank <= (others => '0');
mode_bits <= (others => '0');
cart_en <= '1';
hold_nmi <= '1';
-- activate change of mode, when:
elsif reset_in='1' or cart_force = '1' then
cart_logic_d <= cart_logic;
variant <= cart_variant;
mode_bits <= (others => '0');
bank_bits <= (others => '0');
ram_bank <= (others => '0');
georam_bank <= (others => '0');
ef_write <= '0';
allow_bank <= '0';
do_io2 <= '1';
cart_en <= '1';
hold_nmi <= '0';
ee_clk <= '0';
ee_sel <= '0';
ee_wdata <= '0';
end if;
-- Default, everything is off.
serve_128 <= '0';
serve_rom <= '0';
serve_io1 <= '0';
serve_io2 <= '0';
serve_vic <= '0';
irq_n <= '1';
nmi_n <= '1';
game_n <= '1';
exrom_n <= '1';
rom_mode <= "01"; -- No banking, All within 16K
case cart_logic_d is
-- ULTRA SIMPLE CARTS, NO BANKING, NO RAM
when c_normal =>
if io_write='1' and io_addr(8 downto 0) = "111111111" then -- DFFF
if cart_en='1' and io_wdata(7 downto 6) = "01" then
cart_en <= '0'; -- permanent off
end if;
end if;
game_n <= variant(1);
exrom_n <= variant(0);
serve_rom <= '1';
serve_vic <= variant(2);
when c_128 =>
serve_128 <= '1'; -- 8000-FFFF
serve_vic <= '1';
serve_io1 <= variant(0);
serve_io2 <= variant(1);
rom_mode <= "11"; -- Banking here is 32K!
if variant(2)='1' then
if io_write='1' and io_addr(8 downto 0)="101111111" then -- DF7F
bank_bits(19 downto 15) <= io_wdata(4 downto 0);
end if;
if io_write='1' and io_addr(8 downto 0)="101111110" then -- DF7E
ram_bank <= io_wdata(2 downto 0);
end if;
end if;
when c_epyx =>
game_n <= '1';
exrom_n <= epyx_timeout;
serve_rom <= '1';
serve_io2 <= '1'; -- rom visible df00-dfff
when c_westermann => -- 16K
-- Variant bit 0: enable turning on by reading DExx
-- Variant bit 1: enable keeping 8000-9FFF always enabled
--
-- Variant 0: Westermann. Complete off when reading DFxx
-- Variant 1: Blackbox V4 (16K or off). Reading DFxx = off, Reading DExx = on
-- Variant 2: Westermann. Only upper cartridge half turned off when reading from DFxx
if io_read='1' and io_addr(8)='1' then
mode_bits(0) <= '1';
elsif io_read='1' and io_addr(8)='0' and variant(0)='1' then -- read IO1
mode_bits(0) <= '0';
end if;
game_n <= mode_bits(0);
if variant(1)='1' then
exrom_n <= '0';
else
exrom_n <= mode_bits(0);
end if;
serve_rom <= '1';
when c_sbasic => -- 16K, upper 8k enabled by writing to DExx
-- and disabled by reading
if io_write='1' and io_addr(8)='0' then
mode_bits(0) <= '1';
elsif io_read='1' and io_addr(8)='0' then
mode_bits(0) <= '0';
end if;
game_n <= not mode_bits(0);
exrom_n <= '0';
serve_rom <= '1';
when c_bbasic => -- Write IO1 = off, Read IO1 = ON
if io_write='1' and io_addr(8)='0' then
mode_bits(0) <= '0';
elsif io_read='1' and io_addr(8)='0' then
mode_bits(0) <= '1';
end if;
if mode_bits(0)='1' then
game_n <= '0';
exrom_n <= '0';
-- Dynamic mode, Ultimax in ranges 8000, A000 and E000. How about writes?
elsif slot_addr(15)='1' and not(slot_addr(14 downto 13) = "10") then -- 100x 101x 111x => 8000, A000, E000
game_n <= '0';
exrom_n <= '1';
else -- Off
game_n <= '1';
exrom_n <= '1';
end if;
serve_rom <= '1';
serve_io1 <= '1';
rom_mode <= "11"; -- 32K! The ROMs shall be placed in memory at the right location by the software.
-- Note that the CRT files are usually wrong; they list 3 banks of 8K, all at $8000, which is incorrect.
when c_blackbox_v3 =>
if io_write='1' and io_addr(8)='0' then -- write IO1 => disable
mode_bits(0) <= '1';
elsif io_write='1' and io_addr(8)='1' then -- write IO2 => enable
mode_bits(0) <= '0';
end if;
exrom_n <= mode_bits(0);
serve_rom <= '1';
-- SIMPLE ROM BANKERS
when c_ocean_8K =>
-- variant 0: always enabled
-- variant 1: can be disabled by setting bit 7 to 1 (domark)
-- variant 2: can be disabled by setting bit 6 to 1 (gmod2)
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits(19 downto 14) <= io_wdata(5 downto 0); -- 64 banks of 8K
case variant is
when "000"|"100" =>
null; -- Always enabled
when "001"|"101" =>
mode_bits(0) <= io_wdata(7); -- DOMARK ROM disable
when "010"|"110" =>
mode_bits(1) <= io_wdata(7); -- gmod2 EEPROM write enable
mode_bits(0) <= io_wdata(6); -- gmod2 ROM disable
ee_sel <= io_wdata(6);
ee_clk <= io_wdata(5);
ee_wdata <= io_wdata(4);
when others =>
null;
end case;
end if;
game_n <= '1';
exrom_n <= mode_bits(0);
serve_rom <= '1';
cart_en <= not mode_bits(0);
rom_mode <= "00"; -- 8K banks
when c_ocean_16K =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
-- variant sets max number of banks, 000 = 4, 001 = 8, 011 = 16, 111 = 32
bank_bits(18 downto 14) <= io_wdata(4 downto 0) and (variant & "11"); -- max 32 banks of 16K
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
rom_mode <= "01"; -- 16K banks
when c_system3 => -- 16K, only 8K used?
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits(19 downto 14) <= io_addr(5 downto 0); -- max 64 banks of 8K
-- turn on
mode_bits(0) <= '0';
elsif io_read='1' and io_addr(8)='0' then
-- turn off
mode_bits(0) <= '1';
end if;
game_n <= '1';
exrom_n <= mode_bits(0);
serve_rom <= '1';
rom_mode <= "00"; -- 8K banks
when c_supergames =>
if io_write='1' and io_addr(8)='1' and mode_bits(1) = '0' then -- DF00-DFFF
bank_bits(15 downto 14) <= io_wdata(1 downto 0); -- 4 banks of 16K
mode_bits(1 downto 0) <= io_wdata(3 downto 2);
end if;
if mode_bits(1 downto 0) = "11" then -- Mostly to visualize
cart_en <= '0';
end if;
game_n <= mode_bits(0);
exrom_n <= mode_bits(0); -- hmm?!
serve_rom <= '1';
rom_mode <= "01"; -- 16K banks
when c_blackbox_v8 =>
if io_write='1' and io_addr(8)='1' then -- write to DFxx
bank_bits(15 downto 14) <= io_wdata(3 downto 2); -- 4 banks of 16K
mode_bits(1 downto 0) <= io_wdata(1 downto 0);
end if;
game_n <= mode_bits(1);
exrom_n <= mode_bits(0);
serve_rom <= '1';
rom_mode <= "01"; -- 16K banks
when c_zaxxon =>
-- a read from 8000-8FFF selects bank 0, a read from 9000-9FFF selects bank 1.
if slot_req.sample_io = '1' and slot_addr(15 downto 13) = "100" and slot_rwn = '1' then
bank_bits(14) <= slot_addr(12);
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
rom_mode <= "01"; -- 16K banks
-- (SIMPLE) BANKERS WITH RAM
when c_pagefox => -- 16K mode on/off, 4 banks
if io_write='1' and io_addr(8 downto 7) = "01" then -- DE80-DEFF
mode_bits <= io_wdata(4 downto 2); -- if mode_bits are 10X then map ram
bank_bits(15 downto 14) <= io_wdata(2 downto 1);
ram_bank(14) <= io_wdata(1);
end if;
ram_bank(13) <= slot_addr(13); -- :-)
game_n <= mode_bits(0);
exrom_n <= mode_bits(0);
serve_rom <= '1';
rom_mode <= "01"; -- 16K banks
when c_easy_flash =>
if io_write='1' and io_addr(8)='0' and cart_en='1' then -- DExx
ef_write <= '0';
v_addr4 := io_addr(3 downto 0);
case v_addr4 is
when X"0" =>
bank_bits(19 downto 14) <= io_wdata(5 downto 0); -- max 64 banks of 16K
when X"2" =>
mode_bits <= io_wdata(2 downto 0); -- LED not implemented
when X"9" =>
if io_wdata = X"65" then
ef_write <= '1';
end if;
when others =>
null;
end case;
end if;
game_n <= not (mode_bits(0) or not mode_bits(2));
exrom_n <= not mode_bits(1);
serve_rom <= '1';
serve_io1 <= '0'; -- write registers only, no reads
serve_io2 <= '1'; -- RAM
rom_mode <= "01"; -- 16K banks
-- COMMON FREEZERS
when c_fc3 =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
bank_bits(15 downto 14) <= io_wdata(1 downto 0);
if variant(0)='1' then -- 256K version
bank_bits(17 downto 16) <= io_wdata(3 downto 2);
end if;
mode_bits <= '0' & io_wdata(4) & io_wdata(5);
unfreeze <= '1';
cart_en <= not io_wdata(7);
hold_nmi <= not io_wdata(6);
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
else
game_n <= mode_bits(0);
exrom_n <= mode_bits(1);
end if;
if mode_bits(1 downto 0)="10" then
serve_vic <= '1';
end if;
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
nmi_n <= not(freeze_trig or freeze_act or hold_nmi);
rom_mode <= "01"; -- 16K banks
when c_action =>
-- variant bit 0: Retro Extension (0 = All of DExx / 1 = Only DE00/01, and REU compatible mapping / extra RAM)
-- variant bit 1: Nordic extension (1 = special mode "110" that selects ultimax in A000-BFFF range)
if io_write='1' and io_addr(8) = '0' and cart_en='1' and (io_addr(8 downto 1) = X"00" or variant(0)='0') then
if io_addr(0)='0' or variant(0)='0' then
bank_bits(16 downto 14) <= io_wdata(7) & io_wdata(4 downto 3);
mode_bits <= io_wdata(5) & io_wdata(1 downto 0);
unfreeze <= io_wdata(6);
cart_en <= not io_wdata(2);
elsif io_addr(0)='1' and variant(0)='1' then -- extended register for Retro Replay
if io_wdata(6)='1' then
do_io2 <= '0';
end if;
if io_wdata(1)='1' then
allow_bank <= '1';
end if;
end if;
end if;
if allow_bank = '1' then
ram_bank <= bank_bits(16 downto 14);
else
ram_bank <= "000";
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
else
serve_io1 <= c_serve_io_rr(to_integer(unsigned(mode_bits)));
serve_io2 <= c_serve_io_rr(to_integer(unsigned(mode_bits))) and do_io2;
serve_rom <= c_serve_rom_rr(to_integer(unsigned(mode_bits)));
if mode_bits(2 downto 0)="110" and variant(1)='1' then
game_n <= '0';
-- Switch to Ultimax mode for writes to address A000-BFFF (disable C64 RAM write)
exrom_n <= slot_addr(15) and not slot_addr(14) and slot_addr(13) and not slot_rwn;
else
game_n <= not mode_bits(0);
exrom_n <= mode_bits(1);
end if;
end if;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
rom_mode <= "00"; -- 8K banks
when c_ss5 =>
if io_write='1' and io_addr(8) = '0' and cart_en='1' then -- DE00-DEFF
bank_bits(15 downto 14) <= io_wdata(4) & io_wdata(2); -- 4 banks of 16K
mode_bits <= io_wdata(3) & io_wdata(1) & io_wdata(0);
unfreeze <= not io_wdata(0);
cart_en <= not io_wdata(3);
end if;
game_n <= mode_bits(0);
exrom_n <= not mode_bits(1);
serve_io1 <= cart_en;
serve_io2 <= '0';
serve_rom <= cart_en;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
rom_mode <= "01"; -- 16K banks
when c_kcs =>
-- mode_bit(0) -> ULTIMAX
-- mode_bit(1) -> 16K Mode
-- io1 read
if io_read='1' and io_addr(8) = '0' then -- DE00-DEFF
mode_bits(0) <= '1'; -- When read and addr bit 1=0 : 8k GAME mode
mode_bits(1) <= io_addr(1); -- When read and addr bit 1=1 : Cartridge disabled mode
mode_bits(2) <= '0';
end if;
-- io1 write
if io_write='1' and io_addr(8 downto 7) = "01" then -- DE80-DEFF
mode_bits <= "000"; -- 16K mode
end if;
if io_write='1' and io_addr(8 downto 7) = "00" then -- DE00-DE7F
-- if in 16K 000 / UmaxS 110 / Off2 111
if mode_bits = "000" then -- 16K
mode_bits <= "110";
elsif mode_bits = "010" or mode_bits = "111" then -- Freeze of Off2
mode_bits <= "000"; -- When addr bit 1=0 : 16k GAME mode
mode_bits(0) <= io_addr(1); -- When addr bit 1=1 : 8k GAME mode
end if;
end if;
-- io2 read
if io_read='1' and io_addr(8 downto 7) = "11" then -- DF80-DFFF
unfreeze <= '1'; -- When read : release freeze
end if;
-- on freeze
if freeze_act='1' then
mode_bits <= "010";
end if;
game_n <= mode_bits(0);
exrom_n <= mode_bits(1);
serve_io1 <= '1';
serve_io2 <= '1';
serve_rom <= '1';
serve_vic <= mode_bits(1);
nmi_n <= not(freeze_trig or freeze_act);
when c_fc =>
-- io1 access
if (io_read='1' or io_write='1') and io_addr(8) = '0' then -- DE00-DEFF
mode_bits(0) <= '1';
unfreeze <= '1';
end if;
-- io2 access
if (io_read='1' or io_write='1') and io_addr(8) = '1' then -- DF00-DFFF
mode_bits(0) <= '0';
unfreeze <= '1';
end if;
-- Freezer runs in Ultimax mode
if freeze_act='1' then
game_n <= '0'; -- ULTIMAX mode
exrom_n <= '1';
else
game_n <= mode_bits(0); -- 16K mode or off
exrom_n <= mode_bits(0);
end if;
serve_io1 <= '1';
serve_io2 <= '1';
serve_rom <= '1';
nmi_n <= not(freeze_trig or freeze_act);
-- EXOTICS
when c_georam =>
if io_write='1' and io_addr(8 downto 7) = "11" then
if io_addr(0) = '0' then
georam_bank(5 downto 0) <= io_wdata(5 downto 0) and georam_mask(5 downto 0);
georam_bank(15 downto 14) <= io_wdata(7 downto 6) and georam_mask(15 downto 14);
else
georam_bank(13 downto 6) <= io_wdata(7 downto 0) and georam_mask(13 downto 6);
end if;
end if;
serve_io1 <= '1';
when others =>
null;
end case;
if cart_kill='1' then
cart_en <= '0';
hold_nmi <= '0';
end if;
end if;
end process;
CART_LEDn <= not cart_en;
-- determine ROM address
process(slot_addr, bank_bits, rom_mode) -- Rom mode 00 = 8K banks, 01 = 16K banks, 11 = 32K banks
begin
rom_addr <= g_rom_base;
rom_addr(12 downto 0) <= slot_addr(12 downto 0);
rom_addr(19 downto 13) <= bank_bits;
if rom_mode(13)='1' then
rom_addr(13) <= slot_addr(13);
end if;
if rom_mode(14)='1' then
rom_addr(14) <= slot_addr(14);
end if;
end process;
-- Determine if RAM is mapped, and its address (max 64K)
process(cart_logic_d, variant, mode_bits, ram_bank, slot_addr, do_io2, allow_bank, ef_write)
begin
-- Default
ram_addr <= g_ram_base;
ram_addr(15 downto 0) <= ram_bank & slot_addr(12 downto 0);
allow_write <= '0';
addr_map <= ROM;
case cart_logic_d is
when c_action =>
if mode_bits(2)='1' then
if slot_addr(13)='0' then -- True for 8000-9FFF, as well as IO1/IO2.
addr_map <= RAM;
end if;
if slot_addr(15 downto 13)="100" then -- 8000-9FFF
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" and variant(0)='1' then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
if mode_bits(1 downto 0)="10" and variant(1)='1' then
if slot_addr(15 downto 13)="100" then
addr_map <= ROM;
allow_write <= '0';
elsif slot_addr(15 downto 13)="101" then
addr_map <= RAM;
allow_write <= '1';
end if;
end if;
end if;
when c_easy_flash =>
-- Little RAM
if slot_addr(15 downto 8)=X"DF" then
addr_map <= RAM;
allow_write <= '1';
elsif ef_write='1' and mode_bits="101" and (slot_addr(15 downto 13)="111" or slot_addr(15 downto 13)="100") then -- Ultimax mode, 8000-9FFF and
allow_write <= '1';
end if;
when c_ss5 =>
if mode_bits(1 downto 0)="00" then
if slot_addr(15 downto 13)="100" then
addr_map <= RAM;
allow_write <= '1';
end if;
end if;
when c_kcs =>
-- io2 ram access
if slot_addr(15 downto 8) = X"DF" then
ram_addr(7) <= '0';
addr_map <= RAM;
allow_write <= '1';
end if;
when c_georam =>
if slot_addr(15 downto 8)=X"DE" then
allow_write <= '1';
addr_map <= GEO;
end if;
when c_128 =>
if slot_addr(15 downto 8)=X"DF" and slot_addr(7)='1' and variant(2)='1' then
allow_write <= '1';
addr_map <= RAM;
end if;
when c_pagefox =>
if ram_bank(15 downto 14)="10" then
addr_map <= RAM;
end if;
if slot_addr(15 downto 14)="10" then
allow_write <= '1';
end if;
when others =>
null;
end case;
end process;
-- Calculate the final memory address
process(addr_map, rom_addr, ram_addr, kernal_area, georam_bank, slot_addr)
begin
case addr_map is
when RAM =>
mem_addr_i <= ram_addr;
when GEO =>
mem_addr_i <= g_georam_base(27 downto 24) & georam_bank & slot_addr(7 downto 0);
when others =>
mem_addr_i <= rom_addr;
end case;
if kernal_area='1' then -- This bit-order reduces the number of multiplexers
mem_addr_i <= g_kernal_base(27 downto 15) & slot_addr(1 downto 0) & slot_addr(12 downto 2) & "00";
end if;
end process;
mem_addr <= unsigned(mem_addr_i(mem_addr'range));
-- slot_resp.data(7) <= bank_bits(16);
-- slot_resp.data(6) <= '1';
-- slot_resp.data(5) <= '0';
-- slot_resp.data(4) <= bank_bits(15);
-- slot_resp.data(3) <= bank_bits(14);
-- slot_resp.data(2) <= '0'; -- freeze button pressed
-- slot_resp.data(1) <= allow_bank;
-- slot_resp.data(0) <= '0';
--
-- slot_resp.reg_output <= '1' when (slot_addr(8 downto 1)="00000000") and (cart_logic_d = c_action) and (variant(0)='1') else '0';
process(bank_bits, mode_bits, allow_bank, cart_logic_d, variant, slot_addr, ee_rdata)
begin
slot_resp <= c_slot_resp_init;
case cart_logic_d is
when c_action =>
slot_resp.data(7) <= bank_bits(16);
slot_resp.data(6) <= '1';
slot_resp.data(5) <= '0';
slot_resp.data(4) <= bank_bits(15);
slot_resp.data(3) <= bank_bits(14);
slot_resp.data(2) <= '0'; -- freeze button pressed
slot_resp.data(1) <= allow_bank;
slot_resp.data(0) <= '0';
if slot_addr(8 downto 1) = X"00" and variant(1)='1' then
slot_resp.reg_output <= '1';
end if;
when c_ocean_8K =>
if g_eeprom then
slot_resp.data(7) <= ee_rdata;
if slot_addr(8) = '0' and variant(1 downto 0) = "10" then -- gmod2 variant, reading from DExx
slot_resp.reg_output <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
r_ee: if g_eeprom generate
i_ee: entity work.microwire_eeprom
port map(
clock => clock,
reset => reset,
io_req => io_req_eeprom,
io_resp => io_resp_eeprom,
sel_in => ee_sel,
clk_in => ee_clk,
data_in => ee_wdata,
data_out => ee_rdata
);
end generate;
r_no_ee: if not g_eeprom generate
i_ee_dummy: entity work.io_dummy
port map(
clock => clock,
io_req => io_req_eeprom,
io_resp => io_resp_eeprom
);
end generate;
end architecture;
| gpl-3.0 | 273771aef29932ab1fbf5014ac2a8592 | 0.439971 | 3.709637 | false | false | false | false |
chiggs/nvc | test/regress/issue90.vhd | 5 | 510 | entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
x := x + 1;
end procedure;
begin
process is
variable v : integer := 0;
begin
proc(v);
assert v = 3;
wait;
end process;
end architecture;
| gpl-3.0 | 4ea06c1392085e5df7650220f3d04f8a | 0.55098 | 3.541667 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_sim/usb_test_nano2.vhd | 1 | 6,245 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 2 for USB host
-- This testcase initializes a repeated IN transfer in Circular Mem Buffer mode
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
use work.tl_string_util_pkg.all;
use work.nano_addresses_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity usb_test_nano2 is
generic (
g_report_file_name : string := "work/usb_test_nano2.rpt"
);
end entity;
architecture arch of usb_test_nano2 is
signal clocks_stopped : boolean := false;
signal interrupt : std_logic;
constant Attr_Fifo_Base : unsigned(19 downto 0) := X"00700"; -- 380 * 2
constant Attr_Fifo_Tail_Address : unsigned(19 downto 0) := X"007F0"; -- 3f8 * 2
constant Attr_Fifo_Head_Address : unsigned(19 downto 0) := X"007F2"; -- 3f9 * 2
begin
i_harness: entity work.usb_harness_nano
port map (
interrupt => interrupt,
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable res : std_logic_vector(7 downto 0);
variable attr_fifo_tail : integer := 0;
variable attr_fifo_head : integer := 0;
variable data : std_logic_vector(15 downto 0);
procedure io_write_word(addr : unsigned(19 downto 0); word : std_logic_vector(15 downto 0)) is
begin
io_write(io => io, addr => (addr + 0), data => word(7 downto 0));
io_write(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure io_read_word(addr : unsigned(19 downto 0); word : out std_logic_vector(15 downto 0)) is
begin
io_read(io => io, addr => (addr + 0), data => word(7 downto 0));
io_read(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure read_attr_fifo(result : out std_logic_vector(15 downto 0)) is
variable data : std_logic_vector(15 downto 0);
begin
wait until interrupt = '1';
-- io_read_word(addr => Attr_Fifo_Head_Address, word => data);
-- attr_fifo_head := to_integer(unsigned(data));
-- L1: while true loop
-- io_read_word(addr => Attr_Fifo_Head_Address, word => data);
-- attr_fifo_head := to_integer(unsigned(data));
-- if (attr_fifo_head /= attr_fifo_tail) then
-- exit L1;
-- end if;
-- end loop;
io_read_word(addr => (Attr_Fifo_Base + attr_fifo_tail*2), word => data);
attr_fifo_tail := attr_fifo_tail + 1;
if attr_fifo_tail = 16 then
attr_fifo_tail := 0;
end if;
io_write_word(addr => Attr_Fifo_Tail_Address, word => std_logic_vector(to_unsigned(attr_fifo_tail, 16)));
sctb_trace("Fifo read: " & hstr(data));
result := data;
end procedure;
procedure check_result(expected : std_logic_vector(7 downto 0); exp_result : std_logic_vector(15 downto 0)) is
variable data : std_logic_vector(15 downto 0);
variable byte : std_logic_vector(7 downto 0);
begin
io_read_word(Command_Length, data);
sctb_trace("Command length: " & hstr(data));
io_read_word(Command_Result, data);
sctb_trace("Command result: " & hstr(data));
sctb_check(data, exp_result, "Unexpected response");
byte := read_memory_8(mem, X"00550000");
sctb_check(byte, expected, "Erroneous byte");
write_memory_8(mem, X"00550000", X"00");
end procedure;
-- procedure wait_command_done is
-- begin
-- L1: while true loop
-- io_read(io => io, addr => Command, data => res);
-- if res(1) = '1' then -- check if paused bit has been set
-- exit L1;
-- end if;
-- end loop;
-- end procedure;
begin
bind_io_bus_bfm("io", io);
bind_mem_model("memory", mem);
sctb_open_simulation("path::path", g_report_file_name);
sctb_open_region("Testing Setup request", 0);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write_word(c_nano_simulation, X"0001" ); -- set nano to simulation mode
io_write_word(c_nano_busspeed, X"0002" ); -- set bus speed to HS
io_write(io, c_nano_enable, X"01" ); -- enable nano
wait for 4 us;
io_write_word(Command_DevEP, X"0007"); -- EP7: NAK NAK DATA0 NAK NAK DATA1 NAK STALL
io_write_word(Command_MemHi, X"0055");
io_write_word(Command_MemLo, X"0000");
io_write_word(Command_MaxTrans, X"0010");
io_write_word(Command_Interval, X"0002"); -- every other microframe
io_write_word(Command_Length, X"0010");
-- arm
io_write_word(Command_MemLo, X"0000");
io_write_word(Command, X"5042"); -- in with mem write, using cercular buffer
read_attr_fifo(data);
check_result(X"44", X"8001");
-- arm
io_write_word(Command_MemLo, X"0000");
io_write_word(Command, X"5842"); -- in with mem write, using cercular buffer
read_attr_fifo(data);
check_result(X"6B", X"8801");
-- arm
io_write_word(Command_MemLo, X"0000");
io_write_word(Command, X"5042"); -- in with mem write, using cercular buffer
read_attr_fifo(data);
check_result(X"00", X"C400");
sctb_close_region;
sctb_close_simulation;
clocks_stopped <= true;
wait;
end process;
end arch;
--restart; mem load -infile nano_code.hex -format hex /usb_test_nano2/i_harness/i_host/i_nano/i_buf_ram/mem; run 2000 us
| gpl-3.0 | cc7cf04ec0d9cf4d2012df272ae1dadf | 0.549239 | 3.552332 | false | true | false | false |
markusC64/1541ultimate2 | fpga/nios_tester/nios_tester/synthesis/submodules/jtag_host.vhd | 2 | 6,456 | --------------------------------------------------------------------------------
-- Entity: jtag_host
-- Date:2016-11-03
-- Author: Gideon
--
-- Description: AvalonMM based JTAG host, enhanced PIO.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity jtag_host is
generic (
g_clock_divider : natural := 6 ); -- results in 6 low, 6 high cycles, or 5.2 MHz at 62.5 MHz
port (
clock : in std_logic;
reset : in std_logic;
-- 32 bits Avalon bus interface
-- We do up to 32 bits per transfer. The address determines the state of TMS and the length of the transfer
-- All accesses are queued in a fifo. Read accesses result in a readdatavalid (eventually), and write
-- accesses are simply queued. The host software can easily step through the JTAG states by
-- issuing a couple of write commands. I.e. reset: issue a write command at address 9A (5*4) + 0x80 for TMS.
-- 32*4 = 128. So the address mapping is as follows
-- A7 A6..A2 A1..0
-- TMS <length> <X>
-- The data bits written are those that appear on TDI.
avs_read : in std_logic;
avs_write : in std_logic;
avs_address : in std_logic_vector(7 downto 0);
avs_writedata : in std_logic_vector(31 downto 0);
avs_ready : out std_logic;
avs_readdata : out std_logic_vector(31 downto 0);
avs_readdatavalid : out std_logic;
jtag_tck : out std_logic;
jtag_tms : out std_logic;
jtag_tdi : out std_logic;
jtag_tdo : in std_logic );
end entity;
architecture arch of jtag_host is
signal presc : integer range 0 to g_clock_divider-1;
type t_state is (idle, shifting_L, shifting_H, wait_state);
signal state : t_state;
signal sample : std_logic;
signal wr_en : std_logic;
signal rd_en : std_logic;
signal din : std_logic_vector(33 downto 0);
signal dout : std_logic_vector(33 downto 0);
signal full : std_logic;
signal valid : std_logic;
signal tms_select : std_logic;
signal tms_last : std_logic;
signal data : std_logic_vector(31 downto 0);
signal length : integer range 0 to 16383;
signal position : integer range 0 to 16383;
begin
i_fifo: entity work.sync_fifo
generic map (
g_depth => 255,
g_data_width => 34,
g_threshold => 100,
g_storage => "auto",
g_fall_through => true
)
port map(
clock => clock,
reset => reset,
rd_en => rd_en,
wr_en => wr_en,
din => din,
dout => dout,
flush => '0',
full => full,
almost_full => open,
empty => open,
valid => valid,
count => open
);
din <= avs_read & avs_address(2) & avs_writedata;
wr_en <= avs_read or avs_write;
process(clock)
variable v_bit : std_logic;
begin
if rising_edge(clock) then
avs_readdatavalid <= '0';
rd_en <= '0';
sample <= '0';
if position < 32 then
if sample = '1' then
data(position) <= jtag_tdo;
end if;
v_bit := data(position);
else
v_bit := '0';
end if;
case state is
when idle =>
presc <= g_clock_divider-1;
jtag_tms <= '0';
jtag_tck <= '0';
jtag_tdi <= '0';
if valid = '1' then
rd_en <= '1';
if dout(33) = '1' then
avs_readdatavalid <= '1';
state <= wait_state;
elsif dout(32) = '1' then
tms_select <= '0';
tms_last <= '0';
length <= 31;
data <= dout(31 downto 0);
position <= 0;
state <= shifting_L;
else
tms_select <= dout(31);
tms_last <= dout(30);
length <= to_integer(unsigned(dout(29 downto 16)));
position <= 0;
data <= X"0000" & dout(15 downto 0);
state <= shifting_L;
end if;
end if;
when shifting_L =>
jtag_tck <= '0';
if tms_select = '0' then
jtag_tdi <= v_bit;
if position = length then
jtag_tms <= tms_last;
else
jtag_tms <= '0';
end if;
else
jtag_tdi <= '0';
jtag_tms <= v_bit;
end if;
if presc = 0 then
sample <= '1';
presc <= g_clock_divider-1;
state <= shifting_H;
else
presc <= presc - 1;
end if;
when shifting_H =>
jtag_tck <= '1';
if presc = 0 then
presc <= g_clock_divider-1;
if position = length then
state <= idle;
else
position <= position + 1;
state <= shifting_L;
end if;
else
presc <= presc - 1;
end if;
when wait_state =>
state <= idle;
when others =>
null;
end case;
if reset = '1' then
presc <= 0;
length <= 0;
position <= 0;
state <= idle;
end if;
end if;
end process;
avs_readdata <= data;
avs_ready <= not full;
end architecture;
| gpl-3.0 | 8330aa4de820df08bfecc961c6cd3491 | 0.414343 | 4.492693 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_source/usb1_ulpi_host.vhd | 2 | 27,641 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
entity usb1_ulpi_host is
port (
clock : in std_logic;
reset : in std_logic;
-- Descriptor RAM interface
descr_addr : out std_logic_vector(8 downto 0);
descr_rdata : in std_logic_vector(31 downto 0);
descr_wdata : out std_logic_vector(31 downto 0);
descr_en : out std_logic;
descr_we : out std_logic;
-- Buffer RAM interface
buf_addr : out std_logic_vector(10 downto 0);
buf_rdata : in std_logic_vector(7 downto 0);
buf_wdata : out std_logic_vector(7 downto 0);
buf_en : out std_logic;
buf_we : out std_logic;
-- Transmit Path Interface
tx_busy : in std_logic;
tx_ack : in std_logic;
-- Interface to send tokens and handshakes
send_token : out std_logic;
send_handsh : out std_logic;
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
-- Interface to send data packets
send_data : out std_logic;
no_data : out std_logic;
user_data : out std_logic_vector(7 downto 0);
user_last : out std_logic;
user_valid : out std_logic;
user_next : in std_logic;
-- Interface to bus initialization unit
reset_done : in std_logic;
sof_enable : in std_logic;
scan_enable : in std_logic := '1';
speed : in std_logic_vector(1 downto 0);
abort : in std_logic;
-- Receive Path Interface
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
valid_token : in std_logic;
valid_handsh : in std_logic;
valid_packet : in std_logic;
data_valid : in std_logic;
data_start : in std_logic;
data_out : in std_logic_vector(7 downto 0);
rx_error : in std_logic );
end usb1_ulpi_host;
architecture functional of usb1_ulpi_host is
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal do_sof : std_logic;
constant c_max_transaction : integer := 31;
constant c_max_pipe : integer := 31;
constant c_timeout_val : integer := 7167;
constant c_transaction_offset : unsigned(8 downto 6) := "001";
signal transaction_pntr : integer range 0 to c_max_transaction;
signal descr_addr_i : unsigned(8 downto 0); -- could be temporarily pipe addr
type t_state is (startup, idle, wait4start, scan_transactions, get_pipe,
handle_trans, setup_token, bulk_token, send_data_packet, get_status,
wait_for_ack, receive_data, send_ack, update_pipe, update_trans, do_ping );
signal state : t_state;
signal substate : integer range 0 to 7;
signal trans_in : t_transaction;
signal pipe_in : t_pipe;
signal trans_cnt : unsigned(10 downto 0);
signal trans_len : unsigned(10 downto 0);
signal buf_addr_i : unsigned(10 downto 0);
-- signal speed : std_logic_vector(1 downto 0) := "11";
signal no_data_i : boolean;
signal abort_reg : std_logic;
signal tx_put : std_logic;
signal tx_last : std_logic;
signal need_ping : std_logic;
signal fifo_data_in : std_logic_vector(7 downto 0);
signal tx_almost_full : std_logic;
signal link_busy : std_logic;
signal timeout : boolean;
signal timeout_cnt : integer range 0 to c_timeout_val;
signal first_transfer : boolean;
signal terminate : std_logic;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "sequential";
-- attribute keep : string;
-- attribute keep of timeout : signal is "true";
signal debug_count : integer range 0 to 1023 := 0;
signal debug_error : std_logic := '0';
begin
descr_addr <= std_logic_vector(descr_addr_i);
buf_addr <= std_logic_vector(buf_addr_i);
no_data <= '1' when no_data_i else '0';
buf_wdata <= data_out; -- should be rx_data
buf_we <= '1' when (state = receive_data) and (data_valid = '1') else '0';
p_protocol: process(clock)
procedure next_transaction is
begin
if terminate='1' then
terminate <= '0';
state <= idle;
elsif transaction_pntr = c_max_transaction then
transaction_pntr <= 0;
state <= idle; -- wait for next sof before rescan
else
transaction_pntr <= transaction_pntr + 1;
substate <= 0;
state <= scan_transactions;
end if;
end procedure;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
variable trans_temp : t_transaction;
variable len : unsigned(trans_temp.transfer_length'range);
begin
if rising_edge(clock) then
descr_en <= '0';
descr_we <= '0';
tx_put <= '0';
if abort='1' then
abort_reg <= '1';
end if;
-- default counter
if substate /= 3 then
substate <= substate + 1;
end if;
if timeout_cnt /= 0 then
timeout_cnt <= timeout_cnt - 1;
if timeout_cnt = 1 then
timeout <= false;--true;
end if;
end if;
case state is
when startup =>
tx_pid <= c_pid_reserved;
do_sof <= '0';
frame_div <= 7499;
if reset_done='1' then
state <= idle;
if speed = "10" then
need_ping <= '1';
end if;
end if;
when idle =>
abort_reg <= '0';
if do_sof='1' then
do_sof <= '0';
tx_token <= std_logic_vector(frame_cnt(13 downto 3));
tx_pid <= c_pid_sof;
if speed = "00" then
send_handsh <= '1';
else
send_token <= '1';
end if;
if speed(1)='1' then
frame_cnt <= frame_cnt + 1;
else
frame_cnt <= frame_cnt + 8;
end if;
state <= wait4start;
end if;
when wait4start =>
if tx_ack='1' then
send_token <= '0';
send_handsh <= '0';
send_data <= '0'; -- redundant - will not come here
substate <= 0;
if scan_enable='1' then
state <= scan_transactions;
else
state <= idle;
end if;
end if;
when scan_transactions =>
case substate is
when 0 =>
descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr,
descr_addr_i'length-c_transaction_offset'length);
descr_en <= '1';
when 2 =>
trans_temp := data_to_t_transaction(descr_rdata);
trans_in <= trans_temp;
substate <= 0;
if trans_temp.state = busy then
state <= get_pipe;
else -- go for next, unless we are at the end of the list
next_transaction;
end if;
when others =>
null;
end case;
when get_pipe =>
case substate is
when 0 =>
descr_addr_i <= (others => '0');
descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer;
descr_en <= '1';
when 2 =>
pipe_in <= data_to_t_pipe(descr_rdata);
first_transfer <= true;
state <= handle_trans; ---
when others =>
null;
end case;
when handle_trans => -- both pipe and transaction records are now valid
abort_reg <= '0';
substate <= 0;
if do_sof='1' and link_busy='0' then
state <= idle;
elsif pipe_in.state /= initialized then -- can we use the pipe?
trans_in.state <= error;
state <= update_trans;
else -- yes we can
timeout <= false;
timeout_cnt <= c_timeout_val;
link_busy <= trans_in.link_to_next;
case trans_in.transaction_type is
when control =>
-- a control out sequence exists of a setup token
-- and then a data0 packet, which should be followed by
-- an ack from the device. The next phase of the transaction
-- could be either in or out, and defines whether it is a
-- control read or a control write.
-- By choice, control transfers are implemented using
-- two transactions, which are executed in guaranteed
-- sequence.
-- In this way, each stage has its own buffer.
-- Note, the first pipe should be of type OUT, although it is not
-- checked.
tx_pid <= c_pid_setup;
tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
send_token <= '1';
state <= setup_token;
when bulk | interrupt =>
tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
state <= bulk_token;
send_token <= '1';
timeout <= false;
timeout_cnt <= c_timeout_val;
if pipe_in.direction = dir_in then
tx_pid <= c_pid_in;
else
-- if need_ping='1' then
-- tx_pid <= c_pid_ping;
-- state <= do_ping;
-- else
tx_pid <= c_pid_out;
-- end if;
end if;
if pipe_in.control='1' and first_transfer then
pipe_in.data_toggle <= '1'; -- start with data 1
end if;
first_transfer <= false;
when others => -- not yet supported
trans_in.state <= error;
state <= update_trans;
end case;
end if;
when setup_token =>
if tx_ack='1' then
send_token <= '0';
tx_pid <= c_pid_data0; -- send setup data immediately
send_data <= '1';
buf_en <= '1';
substate <= 0;
state <= send_data_packet;
end if;
-- prepare buffer
buf_addr_i <= trans_in.buffer_address;
trans_len <= trans_in.transfer_length; -- not cut up
trans_cnt <= trans_in.transfer_length; -- not cut up
no_data_i <= (trans_in.transfer_length = 0);
when do_ping =>
if tx_ack='1' then
send_token <= '0';
end if;
-- wait for ack/nack or nyet.
if rx_error='1' then
trans_in.state <= error;
state <= update_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_handsh='1' then -- maybe an ack?
if rx_pid = c_pid_ack then
tx_pid <= c_pid_out;
send_token <= '1';
state <= bulk_token;
elsif rx_pid = c_pid_stall then
pipe_in.state <= stalled;
trans_in.state <= error;
state <= update_pipe;
elsif (rx_pid = c_pid_nak) or (rx_pid = c_pid_nyet) then
state <= handle_trans;
end if; -- all other pids are just ignored
elsif timeout then
state <= handle_trans;
end if;
when bulk_token =>
if tx_ack='1' then
send_token <= '0';
if pipe_in.direction = dir_out then
if pipe_in.data_toggle = '0' then
tx_pid <= c_pid_data0;
else
tx_pid <= c_pid_data1;
end if;
send_data <= '1';
buf_en <= '1';
substate <= 0;
state <= send_data_packet;
else -- input
timeout <= false;
timeout_cnt <= c_timeout_val;
state <= receive_data;
buf_en <= '1';
end if;
end if;
-- prepare buffer
buf_addr_i <= trans_in.buffer_address;
if pipe_in.direction = dir_out then
len := min(trans_in.transfer_length, pipe_in.max_transfer);
trans_len <= len; -- possibly cut up
trans_cnt <= len;
no_data_i <= (trans_in.transfer_length = 0);
else
trans_len <= (others => '0');
end if;
when send_data_packet =>
case substate is
when 0 =>
if tx_ack='1' then
send_data <= '0';
if no_data_i then
substate <= 2;
end if;
else
substate <= 0;
end if;
when 1 =>
substate <= 1; -- stay!
if tx_almost_full='0' then
tx_put <= '1';
buf_addr_i <= buf_addr_i + 1;
trans_cnt <= trans_cnt - 1;
if trans_cnt = 1 then
tx_last <= '1';
substate <= 2;
buf_en <= '0';
else
tx_last <= '0';
end if;
end if;
when 2 =>
if tx_busy='1' then
substate <= 2;
else
state <= wait_for_ack;
timeout <= false;
timeout_cnt <= c_timeout_val;
end if;
when others =>
null;
end case;
when wait_for_ack =>
if rx_error='1' then
trans_in.state <= error;
state <= update_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_handsh='1' then -- maybe an ack?
if (rx_pid = c_pid_ack) or (rx_pid = c_pid_nyet) then
if rx_pid = c_pid_nyet then
need_ping <= '1';
else
need_ping <= '0';
end if;
if trans_in.transfer_length = trans_len then
trans_in.state <= done;
if pipe_in.control='1' and trans_in.transaction_type = bulk then
state <= get_status;
substate <= 0;
else
state <= update_pipe;
end if;
else
trans_in.state <= busy;
state <= handle_trans;
end if;
trans_in.buffer_address <= buf_addr_i; -- store back
trans_in.transfer_length <= trans_in.transfer_length - trans_len;
pipe_in.data_toggle <= not pipe_in.data_toggle;
elsif rx_pid = c_pid_stall then
pipe_in.state <= stalled;
trans_in.state <= error;
state <= update_pipe;
elsif rx_pid = c_pid_nak then
terminate <= '0'; --link_busy; -- if control packet, then don't continue with next transaction!
state <= update_trans;
-- state <= handle_trans; -- just retry and retry, no matter what kind of packet it is, don't send SOF!
end if; -- all other pids are just ignored
-- elsif do_sof='1' then
-- state <= idle; -- test
elsif timeout then
pipe_in.timeout <= '1';
trans_in.state <= error;
state <= update_pipe;
-- state <= handle_trans; -- try again
end if;
when get_status =>
case substate is
when 0 =>
send_token <= '1';
tx_pid <= c_pid_in;
when 1 =>
if tx_ack='1' then
send_token <= '0';
timeout_cnt <= c_timeout_val;
timeout <= false;
else
substate <= 1; -- wait
end if;
when 2 =>
if valid_packet='1' or valid_handsh='1' then
state <= update_pipe; -- end transaction
elsif rx_error='1' or timeout then
trans_in.state <= error;
state <= update_pipe; -- end transaction
else
substate <= 2; -- wait
end if;
when others =>
null;
end case;
when receive_data =>
if data_valid = '1' then
timeout <= false;
timeout_cnt <= 0; -- does not occur anymore
buf_addr_i <= buf_addr_i + 1;
trans_len <= trans_len + 1;
end if;
--------------------------------------------------------------------
if rx_error = '1' or debug_error='1' then
-- go back to send the in token again
buf_en <= '0';
state <= handle_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_packet='1' then
buf_en <= '0';
trans_in.buffer_address <= buf_addr_i - 2; -- cut off CRC
trans_in.transfer_length <= trans_in.transfer_length - (trans_len - 2);
if ((trans_len - 2) >= trans_in.transfer_length) or
((trans_len - 2) < pipe_in.max_transfer) then
trans_in.state <= done;
else
trans_in.state <= busy;
end if;
state <= send_ack;
substate <= 0;
elsif valid_handsh='1' then
buf_en <= '0';
if rx_pid = c_pid_nak then
if pipe_in.control='1' then
state <= idle; -- retry on next sof, do not go to the next transaction
else
state <= update_trans; -- is not updated, but is the standard path to go to the next transact.
end if;
elsif rx_pid = c_pid_stall then
trans_in.state <= error;
pipe_in.state <= stalled;
state <= update_pipe;
end if;
elsif timeout then -- device doesn't answer, could it have missed my in token?
buf_en <= '0';
state <= handle_trans;
end if;
when send_ack =>
case substate is
when 0 =>
send_handsh <= '1';
tx_pid <= c_pid_ack;
when 1 =>
if tx_ack='0' then
substate <= 1; -- stay here.
else
send_handsh <= '0';
state <= update_trans;
-- if (pipe_in.control='0') and (trans_in.state = done) then
-- state <= update_trans;
-- elsif (pipe_in.control='1') and (trans_len = 2) then -- no data, thus status already received
-- state <= update_trans;
-- else
-- null;
-- -- substate <= 2;
-- end if;
end if;
-- when 2 => -- send status back (no data packet)
-- tx_pid <= c_pid_out;
-- tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
-- send_token <= '1';
-- when 3 => -- wait until token was sent
-- if tx_ack='0' then
-- substate <= 3;
-- else
-- send_token <= '0';
-- no_data_i <= true;
-- send_data <= '1';
-- tx_pid <= c_pid_data1;
-- end if;
-- when 4 => -- wait until no data packet was processed
-- if tx_ack='0' then
-- substate <= 4;
-- else
-- send_data <= '0';
-- state <= update_trans;
-- end if;
when others =>
null;
end case;
when update_pipe =>
descr_addr_i <= (others => '0');
descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer;
descr_en <= '1';
descr_we <= '1';
descr_wdata <= t_pipe_to_data(pipe_in);
state <= update_trans;
when update_trans =>
descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr,
descr_addr_i'length-c_transaction_offset'length);
descr_wdata <= t_transaction_to_data(trans_in);
descr_en <= '1';
descr_we <= '1';
next_transaction;
when others =>
null;
end case;
---------------------------------------------------
-- DEBUG
---------------------------------------------------
-- if state /= receive_data then
-- debug_count <= 0;
-- debug_error <= '0';
-- elsif debug_count = 1023 then
-- debug_error <= '1';
-- else
-- debug_count <= debug_count + 1;
-- end if;
---------------------------------------------------
if frame_div = 0 then
do_sof <= sof_enable;
if speed(1)='1' then
frame_div <= 7499; -- microframes
else
frame_div <= 59999; -- 1 ms frames
end if;
else
frame_div <= frame_div - 1;
end if;
if reset_done='0' then
state <= startup;
end if;
if speed /= "10" then -- If not high speed, then we force no ping
need_ping <= '0';
end if;
if reset = '1' then
abort_reg <= '0';
buf_en <= '0';
buf_addr_i <= (others => '0');
trans_len <= (others => '0');
trans_cnt <= (others => '0');
link_busy <= '0';
state <= startup;
do_sof <= '0';
frame_div <= 7499;
frame_cnt <= (others => '0');
send_token <= '0';
send_data <= '0';
send_handsh <= '0';
need_ping <= '0';
terminate <= '0';
end if;
end if;
end process;
-- Decoupling of ulpi tx bus and our generation of data
-- to meet timing of "next" signal
-- fifo_data_in <= reset_data when (state = startup) else buf_rdata;
fifo_data_in <= buf_rdata;
i_srl_tx: entity work.srl_fifo
generic map (
Width => 9,
Depth => 15,
Threshold => 10 )
port map (
clock => clock,
reset => reset,
GetElement => user_next,
PutElement => tx_put,
FlushFifo => '0',
DataIn(7 downto 0) => fifo_data_in,
DataIn(8) => tx_last,
DataOut(7 downto 0) => user_data,
DataOut(8) => user_last,
SpaceInFifo => open,
AlmostFull => tx_almost_full,
DataInFifo => user_valid );
end functional;
| gpl-3.0 | e933727dfe91a81ce8b23fa90b0ce464 | 0.389566 | 4.695261 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/alu.vhd | 1 | 5,047 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
generic (
support_bcd : boolean := true );
port (
operation : in std_logic_vector(2 downto 0);
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
d_in : in std_logic;
data_a : in std_logic_vector(7 downto 0);
data_b : in std_logic_vector(7 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
half_carry : out std_logic;
full_carry : out std_logic;
data_out : out std_logic_vector(7 downto 0));
end alu;
architecture gideon of alu is
signal data_out_i : std_logic_vector(7 downto 0) := X"FF";
signal zero : std_logic;
signal sum_c : std_logic;
signal sum_n : std_logic;
signal sum_z : std_logic;
signal sum_v : std_logic;
signal sum_result : unsigned(7 downto 0) := X"FF";
constant c_ora : std_logic_vector(2 downto 0) := "000";
constant c_and : std_logic_vector(2 downto 0) := "001";
constant c_eor : std_logic_vector(2 downto 0) := "010";
constant c_adc : std_logic_vector(2 downto 0) := "011";
constant c_lda : std_logic_vector(2 downto 0) := "101";
constant c_cmp : std_logic_vector(2 downto 0) := "110";
constant c_sbc : std_logic_vector(2 downto 0) := "111";
begin
-- ORA $nn AND $nn EOR $nn ADC $nn STA $nn LDA $nn CMP $nn SBC $nn
sum: process(data_a, data_b, c_in, operation, d_in)
variable a : unsigned(7 downto 0);
variable b : unsigned(7 downto 0);
variable c : unsigned(0 downto 0);
variable hc : unsigned(0 downto 0);
variable fc : unsigned(0 downto 0);
variable sum_l : unsigned(4 downto 0);
variable sum_h : unsigned(4 downto 0);
begin
a := unsigned(data_a);
-- for subtraction invert second operand
if operation(2)='1' then -- invert b
b := unsigned(not data_b);
else
b := unsigned(data_b);
end if;
-- carry in is masked to '1' for CMP
c(0) := c_in or not operation(0);
-- First add the lower nibble
sum_l := ('0' & a(3 downto 0)) + ('0' & b(3 downto 0)) + c;
-- Determine HalfCarry for ADC only
if support_bcd and d_in='1' and operation(0)='1' and operation(2) = '0' then
if sum_l(4) = '1' or sum_l(3 downto 2)="11" or sum_l(3 downto 1)="101" then -- >9 (10-11, 12-15)
hc := "1";
else
hc := "0";
end if;
else
hc(0) := sum_l(4); -- Standard carry
end if;
half_carry <= hc(0);
-- Then, determine the upper nipple
sum_h := ('0' & a(7 downto 4)) + ('0' & b(7 downto 4)) + hc;
-- Again, determine the carry of the upper nibble
if support_bcd and d_in='1' and operation(0)='1' and operation(2) = '0' then
if sum_h(4) = '1' or sum_h(3 downto 2)="11" or sum_h(3 downto 1)="101" then -- >9 (10-11, 12-15)
fc := "1";
else
fc := "0";
end if;
else
fc(0) := sum_h(4);
end if;
full_carry <= fc(0);
-- Determine Z flag
if sum_l(3 downto 0)="0000" and sum_h(3 downto 0)="0000" then
sum_z <= '1';
else
sum_z <= '0';
end if;
sum_n <= sum_h(3);
sum_c <= fc(0);
sum_v <= (sum_h(3) xor data_a(7)) and (sum_h(3) xor data_b(7) xor operation(2));
sum_result <= sum_h(3 downto 0) & sum_l(3 downto 0);
end process;
with operation select data_out_i <=
data_a or data_b when c_ora,
data_a and data_b when c_and,
data_a xor data_b when c_eor,
std_logic_vector(sum_result) when c_adc | c_cmp | c_sbc,
data_b when others;
zero <= '1' when data_out_i = X"00" else '0';
with operation select c_out <=
sum_c when c_adc | c_sbc | c_cmp,
c_in when others;
with operation select z_out <=
sum_z when c_adc | c_sbc | c_cmp,
zero when c_ora | c_and | c_eor | c_lda,
z_in when others;
with operation select n_out <=
sum_n when c_adc | c_sbc | c_cmp,
data_out_i(7) when c_ora | c_and | c_eor | c_lda,
n_in when others;
with operation select v_out <=
sum_v when c_adc | c_sbc,
v_in when others;
data_out <= data_out_i;
end gideon;
| gpl-3.0 | affac98fddc298e32316b25e688549b5 | 0.472162 | 3.360186 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/packages/vhdl_source/tl_flat_memory_model_pkg.vhd | 1 | 25,654 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
-- Title : Flat Memory Model package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package implements a memory model that can be used
-- as or in bus functional models. It implements different
-- banks, such that only one package is needed for all memories
-- in the whole project. These banks are dynamic, just like
-- the contents of the memories. Internally, this memory model
-- is 32-bit, but can be accessed by means of functions and
-- procedures that exist in various widths.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
use work.tl_string_util_pkg.all;
package tl_flat_memory_model_pkg is
constant c_fm_max_bank : integer := 255;
constant c_fm_max_sector : integer := 65535;
constant c_fm_sector_size : integer := 16384;
subtype t_byte is std_logic_vector(7 downto 0);
type flat_mem_sector_t is array(0 to c_fm_sector_size-1) of integer; -- each sector is 64kB
type flat_mem_sector_p is access flat_mem_sector_t;
type flat_mem_bank_t is array(0 to c_fm_max_sector) of flat_mem_sector_p; -- there are 64k sectors (4 GB)
type flat_mem_bank_p is access flat_mem_bank_t;
-- we need to use a handle rather than a pointer, because we can't pass pointers in function calls
-- Hence, we don't use a linked list, but an array.
type flat_mem_object_t is record
path : string(1 to 256);
name : string(1 to 128);
bank : flat_mem_bank_p;
end record;
type flat_mem_object_p is access flat_mem_object_t;
type flat_mem_array_t is array(1 to c_fm_max_bank) of flat_mem_object_p;
subtype h_mem_object is integer range 0 to c_fm_max_bank;
---------------------------------------------------------------------------
shared variable flat_memories : flat_mem_array_t := (others => null);
---------------------------------------------------------------------------
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object);
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object);
---------------------------------------------------------------------------
-- Low level calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer)
return integer;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer);
procedure clear_memory(
bank : integer);
procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0));
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0));
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0));
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0));
-- integer direct access calls
impure function read_memory_int(
bank : integer;
address : integer )
return integer;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer );
-- File Access Procedures
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0));
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
procedure load_memory_hex(
filename : string;
bank : integer);
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
end package;
package body tl_flat_memory_model_pkg is
-- Memory model module registration into array
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
L1 : for i in flat_memories'range loop
if flat_memories(i) = null then
-- report "my name is "& named;
handle := i;
flat_memories(i) := new flat_mem_object_t;
flat_memories(i).path(path'range) := path;
flat_memories(i).name(named'range) := named;
flat_memories(i).bank := new flat_mem_bank_t;
exit L1;
end if;
end loop;
end procedure register_mem_model;
-- Memory model module binding
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
wait for 1 ns;
L1 : for i in flat_memories'range loop
if flat_memories(i) /= null then
if flat_memories(i).name(named'range) = named or
flat_memories(i).path(named'range) = named then
handle := i;
return;
end if;
end if;
end loop;
report "Can't find memory model '"&named&"'."
severity failure;
end procedure bind_mem_model;
-- Base calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer) return integer is
begin
if flat_memories(bank) = null then
return 0;
end if;
if flat_memories(bank).bank(sector) = null then
return 0;
end if;
return flat_memories(bank).bank(sector).all(entry);
end function read_memory;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer) is
begin
if flat_memories(bank) = null then
flat_memories(bank) := new flat_mem_object_t;
flat_memories(bank).bank(0 to c_fm_max_sector) := (others => null);
end if;
if flat_memories(bank).bank(sector) = null then
flat_memories(bank).bank(sector) := new flat_mem_sector_t;
flat_memories(bank).bank(sector).all(0 to c_fm_sector_size-1) := (others => 0);
end if;
flat_memories(bank).bank(sector).all(entry) := data;
end procedure write_memory;
procedure clear_memory(bank : integer) is
begin
if flat_memories(bank) /= null then
for i in flat_memories(bank).bank'range loop
if flat_memories(bank).bank(i) /= null then
deallocate(flat_memories(bank).bank(i));
end if;
end loop;
deallocate(flat_memories(bank));
flat_memories(bank) := null;
end if;
end procedure clear_memory;
procedure clean_up is
begin
for i in flat_memories'range loop
clear_memory(i);
end loop;
end procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
return std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
end function read_memory_32;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
write_memory(bank, sector_idx, entry_idx, to_integer(signed(data)));
end procedure write_memory_32;
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
--write_s(L, "Writing " & vec_to_hex(data, 8) & " to location " & vec_to_hex(address, 8));
--writeline(output, L);
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
for i in be'range loop
if to_x01(be(i)) = '1' then
read_data(7+8*i downto 8*i) := data(7+8*i downto 8*i);
end if;
end loop;
write_memory(bank, sector_idx, entry_idx, to_integer(signed(read_data)));
end procedure write_memory_be;
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
if address(1) = '0' then
return read_data(15 downto 0);
else
return read_data(31 downto 16);
end if;
end function read_memory_16;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0);
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data;
be_temp := address(1) & address(1) & not address(1) & not address(1);
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_16;
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
case address(1 downto 0) is
when "11" =>
return read_data(31 downto 24);
when "01" =>
return read_data(15 downto 8);
when "10" =>
return read_data(23 downto 16);
when others =>
return read_data(7 downto 0);
end case;
end function read_memory_8;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0) := (others => '0');
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data & data & data;
be_temp(to_integer(unsigned(address(1 downto 0)))) := '1';
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_8;
-- Integer direct procedures
impure function read_memory_int(
bank : integer;
address : integer )
return integer is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
return read_memory(bank, sect, index);
end function read_memory_int;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer ) is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
write_memory(bank, sect, index, data);
end procedure write_memory_int;
-- File access procedures
-- not a public procedure.
procedure read_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
aligned : while true loop
if EndFile(myfile) then
exit aligned;
end if;
read(myfile, i);
write_memory(bank, sector_idx, entry_idx, i);
if entry_idx = c_fm_sector_size-1 then
entry_idx := 0;
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
unaligned : while true loop
if EndFile(myfile) and myrec.Offset = 0 then
exit unaligned;
end if;
read_byte(myfile, data, myrec);
write_memory_8(bank, std_logic_vector(addr), data);
--report "Writing " & hstr(data) & " to " & hstr(addr);
addr := addr + 1;
end loop;
end if;
end read_binary_file;
-- not a public procedure
procedure read_hex_file (
file myfile : text;
bank : integer)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : t_byte;
variable sum : unsigned(7 downto 0);
variable rectype : t_byte;
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
return;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
when X"01" => -- end of file record
return;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
return;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
end read_hex_file;
-- public procedure:
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0))
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
init_record(myrec);
read_binary_file (myfile, bank, address, myrec);
file_close(myfile);
end load_memory;
-- public procedure:
procedure load_memory_hex(
filename : string;
bank : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file (myfile, bank);
file_close(myfile);
end load_memory_hex;
-- not a public procedure.
procedure write_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer;
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
remaining := (length + 3) / 4;
aligned : while remaining > 0 loop
i := read_memory(bank, sector_idx, entry_idx);
write(myfile, i);
remaining := remaining - 1;
if entry_idx = c_fm_sector_size-1 then
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
remaining := length;
unaligned : while remaining > 0 loop
data := read_memory_8(bank, std_logic_vector(addr));
write_byte(myfile, data, myrec);
addr := addr + 1;
remaining := remaining - 1;
end loop;
purge(myfile, myrec);
end if;
end write_binary_file;
-- not a public procedure.
procedure write_hex_file(
file myfile : text;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer)
is
variable addr : std_logic_vector(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable remaining : integer;
variable maxlen : integer;
variable sum : unsigned(7 downto 0);
variable L : line;
variable prev_hi : std_logic_vector(31 downto 16) := (others => '-');
begin
addr := startaddr;
remaining := length;
unaligned : while remaining > 0 loop
-- check if we need to write a new extended address record
if addr(31 downto 16) /= prev_hi then
write_string(L, ":02000004");
write(L, vec_to_hex(addr(31 downto 16), 4));
write(L, vec_to_hex(std_logic_vector(X"FA" - unsigned(addr(31 downto 24)) - unsigned(addr(23 downto 16))), 2));
writeline(myfile, L);
prev_hi := addr(31 downto 16);
end if;
-- check for maximum length (until 64k boundary)
maxlen := 65536 - to_integer(unsigned(addr(15 downto 0)));
if maxlen > 16 then maxlen := 16; end if;
-- create data record
sum := X"00";
write(L, ':');
write(L, vec_to_hex(std_logic_vector(to_unsigned(maxlen, 8)), 2));
write(L, vec_to_hex(addr(15 downto 0), 4));
write_string(L, "00");
sum := sum - maxlen;
sum := sum - unsigned(addr(15 downto 8));
sum := sum - unsigned(addr(7 downto 0));
for i in 1 to maxlen loop
data := read_memory_8(bank, addr);
sum := sum - unsigned(data);
write(L, vec_to_hex(data, 2));
addr := std_logic_vector(unsigned(addr) + 1);
end loop;
remaining := remaining - maxlen;
write(L, vec_to_hex(std_logic_vector(sum), 2));
writeline(myfile, L);
end loop;
write_string(L, ":00000001");
writeline(myfile, L);
end write_hex_file;
-- public procedure:
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
init_record(myrec);
write_binary_file (myfile, bank, address, length, myrec);
file_close(myfile);
end save_memory;
-- public procedure:
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
write_hex_file (myfile, bank, address, length);
file_close(myfile);
end save_memory_hex;
end;
| gpl-3.0 | cfd6ea74d6a6a75a8f0d4b9d04a20492 | 0.520387 | 4.190461 | false | false | false | false |
trondd/mkjpeg | design/JFIFGen/HeaderRAM.vhd | 2 | 1,490 | LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
ENTITY HeaderRam IS
GENERIC
(
ADDRESS_WIDTH : integer := 10;
DATA_WIDTH : integer := 8
);
PORT
(
clk : IN std_logic;
d : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
waddr : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
raddr : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
we : IN std_logic;
q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)
);
END HeaderRam;
ARCHITECTURE rtl OF HeaderRam IS
TYPE RamType IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
impure function InitRamFromFile(RamFileName : in string) return RamType is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for l in RamType'range loop
readline(RamFile, RamFileLine);
hread(RamFileLine, RAM(l));
end loop;
return RAM;
end function;
--SIGNAL ram_block : RamType := InitRamFromFile("../design/jfifgen/header.hex");
SIGNAL ram_block : RamType;
attribute ram_init_file : string;
attribute ram_init_file of ram_block :
signal is "./src/jpg/JFIFGen/header.mif";
BEGIN
PROCESS (clk)
BEGIN
IF (clk'event AND clk = '1') THEN
IF (we = '1') THEN
ram_block(to_integer(unsigned(waddr))) <= d;
END IF;
q <= ram_block(to_integer(unsigned(raddr)));
END IF;
END PROCESS;
END rtl;
| lgpl-3.0 | f8e79daceb4c94502eaa8e1bb8542d47 | 0.65906 | 2.985972 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/submodules/spi_master.m.vhd | 1 | 10,801 | -------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE spi_master_pkg IS
COMPONENT spi_master IS
GENERIC(
BASE_CLK : INTEGER := 33000000; -- frequency of the isl_clk signal
SCLK_FREQUENCY : INTEGER := 10000; -- frequency of the osl_sclk signal can not be bigger than BASE_CLK/2;
CS_SETUP_CYLES : INTEGER := 10; -- number of isl_clk cycles till the first osl_sclk edge is coming out after oslv_Ss is asserted.
TRANSFER_WIDTH : INTEGER := 32; -- number of bits per transfer
NR_OF_SS : INTEGER := 1; -- number of slave selects
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
MSBFIRST: STD_LOGIC := '1'; -- msb first = 0 Data is shifted out with the lsb first, msb first = 1 data is shifted out with the msb first.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
isl_tx_start : IN STD_LOGIC;
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
osl_rx_done : OUT STD_LOGIC;
islv_ss_activ : IN STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END COMPONENT spi_master;
END PACKAGE spi_master_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY spi_master IS
GENERIC(
BASE_CLK : INTEGER := 33000000; -- frequency of the isl_clk signal
SCLK_FREQUENCY : INTEGER := 10000; -- frequency of the osl_sclk signal can not be bigger than BASE_CLK/2;
CS_SETUP_CYLES : INTEGER := 10; -- number of isl_clk cycles till the first osl_sclk edge is coming out after oslv_Ss is asserted.
TRANSFER_WIDTH : INTEGER := 32; -- number of bits per transfer
NR_OF_SS : INTEGER := 1; -- number of slave selects
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
MSBFIRST: STD_LOGIC := '1'; -- msb first = 0 Data is shifted out with the lsb first, msb first = 1 data is shifted out with the msb first.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0); -- data to transmit, should not be changed after tx_start is asserted till rx_done is received
isl_tx_start : IN STD_LOGIC; --if this signal is set to one the transmission starts
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0); --received data only valid if rx_done is high
osl_rx_done : OUT STD_LOGIC; --if this signal goes high the receiving of data is finished
islv_ss_activ : IN STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0); -- decides which ss line should be active always write a logic high to set the ss active. the block itselve handles the logic level of the ss depending on the sspol value
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END ENTITY spi_master;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF spi_master IS
CONSTANT NR_OF_TICKS_PER_SCLK_EDGE : INTEGER := BASE_CLK/SCLK_FREQUENCY/2;
CONSTANT CYCLE_COUNTHER_WIDTH : INTEGER := integer(ceil(log2(real(SCLK_FREQUENCY))))+1;
TYPE t_states IS (idle,wait_ss_enable_setup,process_data,wait_ss_disable_setup);
TYPE t_internal_register IS RECORD
state :t_states;
-- synchronize signals
sync_miso_1 : STD_LOGIC;
sync_miso_2 : STD_LOGIC;
clk_count : UNSIGNED(CYCLE_COUNTHER_WIDTH-1 DOWNTO 0);
sclk : STD_LOGIC;
ss : STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
bit_count : INTEGER;
mosi : STD_LOGIC;
leading_edge : STD_LOGIC;
rx_data_buf : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
rx_done : STD_LOGIC;
END RECORD;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,isl_tx_start,islv_ss_activ,islv_tx_data,isl_miso)
VARIABLE vi: t_internal_register;
PROCEDURE change_bitcount IS
BEGIN
IF MSBFIRST = '0' THEN
IF vi.bit_count >= TRANSFER_WIDTH-1 THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := wait_ss_disable_setup;
vi.bit_count := 0;
ELSE
vi.bit_count := vi.bit_count + 1;
END IF;
ELSE
IF vi.bit_count <= 0 THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := wait_ss_disable_setup;
vi.bit_count := TRANSFER_WIDTH-1;
ELSE
vi.bit_count := vi.bit_count - 1;
END IF;
END IF;
END change_bitcount;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.rx_done := '0';
--synchronisation
vi.sync_miso_2 := vi.sync_miso_1;
vi.sync_miso_1 := isl_miso;
CASE vi.state IS
WHEN idle =>
vi.mosi := '0';
vi.ss := (OTHERS => NOT SSPOL);
vi.sclk := CPOL;
IF isl_tx_start = '1' THEN
vi.state := wait_ss_enable_setup;
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
FOR i IN 0 TO NR_OF_SS-1 LOOP
IF islv_ss_activ(i) = '1' THEN
vi.ss(i) := SSPOL;
END IF;
END LOOP;
END IF;
WHEN wait_ss_enable_setup =>
vi.clk_count := vi.clk_count + 1;
IF vi.clk_count >= CS_SETUP_CYLES THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.leading_edge := '1';
vi.rx_data_buf := (OTHERS => '0');
vi.state := process_data;
END IF;
WHEN process_data =>
--toggle sclk
IF vi.clk_count = to_unsigned(0,CYCLE_COUNTHER_WIDTH) THEN
vi.sclk := NOT vi.sclk;
vi.clk_count := to_unsigned(NR_OF_TICKS_PER_SCLK_EDGE,CYCLE_COUNTHER_WIDTH);
IF CPHA = '0' THEN -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK.
IF vi.leading_edge = '1' THEN
vi.rx_data_buf(vi.bit_count) := vi.sync_miso_2;
ELSE --trailing edge
vi.mosi := islv_tx_data(vi.bit_count);
change_bitcount;
END IF;
ELSE -- clock phase 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
IF vi.leading_edge = '1' THEN
vi.mosi := islv_tx_data(vi.bit_count);
ELSE --trailing edge
vi.rx_data_buf(vi.bit_count) := vi.sync_miso_2;
change_bitcount;
END IF;
END IF;
vi.leading_edge := NOT vi.leading_edge;
ELSE
vi.clk_count := vi.clk_count - 1;
END IF;
WHEN wait_ss_disable_setup =>
IF vi.clk_count >= CS_SETUP_CYLES THEN
vi.ss := (OTHERS => NOT SSPOL);
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := idle;
vi.rx_done := '1';
ELSE
vi.clk_count := vi.clk_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := idle;
vi.sclk := CPOL;
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.ss := (OTHERS => NOT SSPOL);
IF MSBFIRST = '0' THEN
vi.bit_count := 0;
ELSE
vi.bit_count := TRANSFER_WIDTH-1;
END IF;
vi.mosi := '0';
vi.leading_edge := '0';
vi.rx_data_buf := (OTHERS => '0');
vi.rx_done := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
--output assignement
osl_sclk <= ri.sclk;
oslv_Ss <= ri.ss;
osl_mosi <= ri.mosi;
osl_rx_done <= ri.rx_done;
oslv_rx_data <= ri.rx_data_buf;
END ARCHITECTURE rtl;
| apache-2.0 | b803aa761f667cea3b21fd8e91052fd8 | 0.559948 | 3.407256 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_source/mem_to_mem32.vhd | 1 | 7,380 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: mem_to_mem32
-- Date:2015-01-05
-- Author: Gideon
-- Description: Adapter to attach an 8 bit memory slave to a 32 bit memory controller port.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity mem_to_mem32 is
generic (
g_big_endian : boolean );
port (
clock : in std_logic;
reset : in std_logic;
mem_req_8 : in t_mem_req;
mem_resp_8 : out t_mem_resp;
mem_req_32 : out t_mem_req_32;
mem_resp_32 : in t_mem_resp_32 );
end entity;
architecture route_through of mem_to_mem32 is
begin
-- this adapter is the most simple variant; it just routes through the data and address
-- no support for count and burst.
mem_resp_8.data <= mem_resp_32.data(31 downto 24) when g_big_endian else mem_resp_32.data(7 downto 0);
mem_resp_8.rack <= mem_resp_32.rack;
mem_resp_8.rack_tag <= mem_resp_32.rack_tag;
mem_resp_8.dack_tag <= mem_resp_32.dack_tag;
mem_resp_8.count <= "00";
mem_req_32.tag <= mem_req_8.tag;
mem_req_32.request <= mem_req_8.request;
mem_req_32.read_writen <= mem_req_8.read_writen;
mem_req_32.address <= mem_req_8.address;
mem_req_32.data <= (mem_req_8.data & X"000000") when g_big_endian else (X"000000" & mem_req_8.data);
mem_req_32.byte_en <= "1000" when g_big_endian else "0001";
end architecture;
-- The buffered variant of the 8-to-32 bit bus conversion performs reads in 32-bit mode
-- and compares the address of consequetive accesses to read from the buffer instead of
-- issuing a new access. The buffer is therefore just 32 bits and could potentially reduce
-- the number of accesses by a factor of 4. Writes fall through, in order to make sure
-- that a read never requires a pending write to be flushed first. Of course, writes also
-- update the buffered data.
--
architecture buffered of mem_to_mem32 is
type t_state is (idle, reading, read_req);
type t_vars is record
state : t_state;
last_address : unsigned(mem_req_32.address'range);
address_valid : std_logic;
buffered_data : std_logic_vector(31 downto 0);
end record;
constant c_vars_init : t_vars := (state => idle, address_valid => '0', buffered_data => (others => '0'), last_address => (others => '0'));
signal cur, nxt : t_vars := c_vars_init;
function slice(a : std_logic_vector; len : natural; sel : unsigned) return std_logic_vector is
alias aa : std_logic_vector(a'length-1 downto 0) is a;
variable si : natural;
begin
si := to_integer(sel);
return aa(len-1+si*len downto si*len);
end function;
begin
process(cur, mem_req_8, mem_resp_32)
variable alow : unsigned(1 downto 0);
begin
nxt <= cur;
mem_resp_8.data <= X"00";
mem_resp_8.rack <= '0';
mem_resp_8.rack_tag <= X"00";
mem_resp_8.dack_tag <= X"00";
mem_resp_8.count <= "00";
mem_req_32.tag <= mem_req_8.tag;
mem_req_32.request <= '0';
mem_req_32.read_writen <= mem_req_8.read_writen;
mem_req_32.address <= mem_req_8.address;
if g_big_endian then
mem_req_32.data <= mem_req_8.data & X"000000";
mem_req_32.byte_en <= "1000";
else
mem_req_32.data <= X"000000" & mem_req_8.data;
mem_req_32.byte_en <= "0001";
end if;
case cur.state is
when idle =>
if mem_req_8.request = '1' then
if mem_req_8.read_writen = '0' then
mem_resp_8.rack <= mem_resp_32.rack;
mem_resp_8.rack_tag <= mem_resp_32.rack_tag;
mem_req_32.request <= '1';
if cur.address_valid = '1' and mem_req_8.address(mem_req_8.address'high downto 2) = cur.last_address(mem_req_8.address'high downto 2) then
alow := mem_req_8.address(1 downto 0);
if g_big_endian then alow := not alow; end if;
case alow is
when "00" =>
nxt.buffered_data(7 downto 0) <= mem_req_8.data;
when "01" =>
nxt.buffered_data(15 downto 8) <= mem_req_8.data;
when "10" =>
nxt.buffered_data(23 downto 16) <= mem_req_8.data;
when "11" =>
nxt.buffered_data(31 downto 24) <= mem_req_8.data;
when others =>
null;
end case;
end if;
else -- read
if cur.address_valid = '1' and mem_req_8.address(mem_req_8.address'high downto 2) = cur.last_address(mem_req_8.address'high downto 2) then
-- Ok.. easy, we're done.
mem_resp_8.rack <= '1';
mem_resp_8.rack_tag <= mem_req_8.tag;
mem_resp_8.dack_tag <= mem_req_8.tag;
mem_resp_8.data <= slice(cur.buffered_data, 8, mem_req_8.address(1 downto 0));
else
-- Not so easy, a request should be made to the memory, which may be acked immediately, or not
mem_req_32.request <= '1';
mem_req_32.address(1 downto 0) <= "00"; -- only aligned access
nxt.last_address <= mem_req_8.address;
nxt.address_valid <= '1';
if mem_resp_32.rack_tag /= mem_req_8.tag then
nxt.state <= read_req;
else
nxt.state <= reading;
end if;
end if;
end if;
end if;
when read_req => -- we need to read, read has not been acknowledged yet.
mem_req_32.request <= '1';
mem_req_32.address(1 downto 0) <= "00"; -- only aligned access
if mem_resp_32.rack_tag = mem_req_8.tag then
-- does data come in the same cycle?
if mem_resp_32.dack_tag = mem_req_8.tag then
nxt.buffered_data <= mem_resp_32.data;
nxt.state <= idle;
else
nxt.state <= reading;
end if;
end if;
when reading =>
if mem_resp_32.dack_tag = mem_req_8.tag then
nxt.buffered_data <= mem_resp_32.data;
nxt.state <= idle;
end if;
when others =>
null;
end case;
end process;
process(clock)
begin
if rising_edge(clock) then
cur <= nxt;
if reset = '1' then
cur.address_valid <= '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 2feb48a7f3b13ff99d7e2cf857ad69a0 | 0.496883 | 3.717884 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/bridge_to_mem_ctrl.vhd | 1 | 1,833 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bridge_to_mem_ctrl is
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
nano_addr : in unsigned(7 downto 0);
nano_write : in std_logic;
nano_wdata : in std_logic_vector(15 downto 0);
-- cmd interface
sys_clock : in std_logic;
sys_reset : in std_logic;
cmd_addr : out std_logic_vector(3 downto 0);
cmd_valid : out std_logic;
cmd_write : out std_logic;
cmd_wdata : out std_logic_vector(15 downto 0);
cmd_ack : in std_logic );
end entity;
architecture gideon of bridge_to_mem_ctrl is
signal fifo_data_in : std_logic_vector(19 downto 0);
signal fifo_write : std_logic;
signal cmd_data_out : std_logic_vector(19 downto 0);
begin
fifo_data_in <= std_logic_vector(nano_addr(3 downto 0)) & nano_wdata;
fifo_write <= '1' when (nano_addr(7 downto 4)=X"7" and nano_write='1') else '0';
i_cmd_fifo: entity work.async_fifo_ft
generic map (
g_data_width => 20,
g_depth_bits => 3 )
port map (
-- write port signals (synchronized to write clock)
wr_clock => ulpi_clock,
wr_reset => ulpi_reset,
wr_en => fifo_write,
wr_din => fifo_data_in,
wr_full => open,
-- read port signals (synchronized to read clock)
rd_clock => sys_clock,
rd_reset => sys_reset,
rd_next => cmd_ack,
rd_dout => cmd_data_out,
rd_valid => cmd_valid );
cmd_addr <= cmd_data_out(19 downto 16);
cmd_wdata <= cmd_data_out(15 downto 0);
cmd_write <= '1'; -- we don't support reads yet
end architecture;
| gpl-3.0 | cd330ded6f82cdcf2628569a73f33d72 | 0.548282 | 3.284946 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_sim/tb_ulpi_tx.vhd | 2 | 5,776 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity tb_ulpi_tx is
end entity;
architecture tb of tb_ulpi_tx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := X"40";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '1';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_command : std_logic;
signal rx_register : std_logic;
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal status : std_logic_vector(7 downto 0);
signal busy : std_logic;
-- Interface to send tokens
signal send_handsh : std_logic := '0';
signal send_token : std_logic := '0';
signal pid : std_logic_vector(3 downto 0) := X"0";
signal token : std_logic_vector(10 downto 0) := (others => '0');
-- Interface to send data packets
signal send_data : std_logic := '0';
signal user_data : std_logic_vector(7 downto 0) := X"00";
signal user_last : std_logic := '0';
signal user_valid : std_logic := '0';
signal user_next : std_logic := '0';
-- Interface to read/write registers
signal read_reg : std_logic := '0';
signal write_reg : std_logic := '0';
signal address : std_logic_vector(5 downto 0) := (others => '0');
signal write_data : std_logic_vector(7 downto 0) := (others => '0');
signal read_data : std_logic_vector(7 downto 0) := (others => '0');
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
signal set : std_logic_vector(7 downto 0) := X"00";
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_tx: entity work.usb1_ulpi_tx
port map (
clock => clock,
reset => reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_register => rx_register,
rx_data => rx_data,
-- Status
busy => busy,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => pid,
token => token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to read/write registers
read_reg => read_reg,
write_reg => write_reg,
address => address,
write_data => write_data,
read_data => read_data );
i_bus: entity work.usb1_ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_register => rx_register,
rx_last => rx_last,
rx_valid => rx_valid );
i_bfm: entity work.usb1_ulpi_phy_bfm
generic map (
g_rx_interval => 500 )
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
P_data: process(clock)
begin
if rising_edge(clock) then
if set /= X"00" then
user_data <= set;
elsif user_next='1' then
user_data <= std_logic_vector(unsigned(tx_data) + 1);
end if;
end if;
end process;
p_test: process
begin
wait until reset='0';
wait until clock='1';
write_data <= X"21";
address <= "010101";
write_reg <= '1';
wait until clock='1';
write_reg <= '0';
wait until busy='0';
wait until clock='1';
address <= "101010";
read_reg <= '1';
wait until clock='1';
read_reg <= '0';
wait until busy='0';
wait until clock='1';
pid <= c_pid_sof;
token <= "00101100011";
send_token <= '1';
wait until clock='1';
send_token <= '0';
wait until busy='0';
wait until clock='1';
send_data <= '1';
pid <= c_pid_data0;
wait until clock='1';
send_data <= '0';
wait until user_data = X"10";
user_last <= '1';
wait until clock = '1';
user_last <= '0';
wait until busy='0';
wait until clock='1';
pid <= c_pid_ack;
token <= "00101100011";
send_handsh <= '1';
wait until clock='1';
send_handsh <= '0';
wait;
end process;
end tb;
| gpl-3.0 | 737e555a8489b88f9be9168589981152 | 0.470914 | 3.726452 | false | false | false | false |
trondd/mkjpeg | design/common/SingleSM.vhd | 2 | 4,013 | -------------------------------------------------------------------------------
-- File Name : SingleSM.vhd
--
-- Project :
--
-- Module :
--
-- Content :
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
-------------------------------------------------------------------------------
-- History :
-- 20080301: (MK): Initial Creation.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity SingleSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- from/to SM(m)
start_i : in std_logic;
idle_o : out std_logic;
-- from/to SM(m+1)
idle_i : in std_logic;
start_o : out std_logic;
-- from/to processing block
pb_rdy_i : in std_logic;
pb_start_o : out std_logic;
-- state debug
fsm_o : out std_logic_vector(1 downto 0)
);
end entity SingleSM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture SingleSM_rtl of SingleSM is
-------------------------------------------------------------------------------
-- Architecture: Signal definition.
-------------------------------------------------------------------------------
type T_STATE is (IDLE, WAIT_FOR_BLK_RDY, WAIT_FOR_BLK_IDLE);
signal state : T_STATE;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fsm_o <= "00" when state = IDLE else
"01" when state = WAIT_FOR_BLK_RDY else
"10" when state = WAIT_FOR_BLK_IDLE else
"11";
------------------------------------------------------------------------------
-- FSM
------------------------------------------------------------------------------
p_fsm : process(CLK, RST)
begin
if RST = '1' then
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
state <= IDLE;
elsif CLK'event and CLK = '1' then
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
case state is
when IDLE =>
idle_o <= '1';
-- this fsm is started
if start_i = '1' then
state <= WAIT_FOR_BLK_RDY;
-- start processing block associated with this FSM
pb_start_o <= '1';
idle_o <= '0';
end if;
when WAIT_FOR_BLK_RDY =>
-- wait until processing block completes
if pb_rdy_i = '1' then
-- wait until next FSM is idle before starting it
if idle_i = '1' then
state <= IDLE;
start_o <= '1';
else
state <= WAIT_FOR_BLK_IDLE;
end if;
end if;
when WAIT_FOR_BLK_IDLE =>
if idle_i = '1' then
state <= IDLE;
start_o <= '1';
end if;
when others =>
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
state <= IDLE;
end case;
end if;
end process;
end architecture SingleSM_rtl;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
| lgpl-3.0 | 21949d51cd6b02d346f5fd72f66eeda7 | 0.293546 | 5.151476 | false | false | false | false |
trondd/mkjpeg | tb/vhdl/GPL_V2_Image_pkg.vhd | 2 | 10,277 | -----------------------------------------------------------------
-- Copyright (c) 1997 Ben Cohen. All rights reserved.
-- email: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published
-- by the Free Software Foundation; either version 2 of the License,
-- or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
-- UPDATE: 8/22/02
-- Add to HexImage the supply of hex 'Z'
-- in the case statement when a binary set of 4 bits = "ZZZZ"
---------------------------------------------------------------
-- Note: 2006.08.11: (FB): modified package name to fit the structure of the
-- project and to highlight the license.
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_TextIO.all;
use ieee.numeric_std.all;
-- use IEEE.Std_Logic_Arith.all;
library Std;
use STD.TextIO.all;
--package Image_Pkg is
package GPL_V2_Image_Pkg is
function Image(In_Image : Time) return String;
function Image(In_Image : Bit) return String;
function Image(In_Image : Bit_Vector) return String;
function Image(In_Image : Integer) return String;
function Image(In_Image : Real) return String;
function Image(In_Image : Std_uLogic) return String;
function Image(In_Image : Std_uLogic_Vector) return String;
function Image(In_Image : Std_Logic_Vector) return String;
function Image(In_Image : Signed) return String;
function Image(In_Image : UnSigned) return String;
function HexImage(InStrg : String) return String;
function HexImage(In_Image : Bit_Vector) return String;
function HexImage(In_Image : Std_uLogic_Vector) return String;
function HexImage(In_Image : Std_Logic_Vector) return String;
function HexImage(In_Image : Signed) return String;
function HexImage(In_Image : UnSigned) return String;
function DecImage(In_Image : Bit_Vector) return String;
function DecImage(In_Image : Std_uLogic_Vector) return String;
function DecImage(In_Image : Std_Logic_Vector) return String;
function DecImage(In_Image : Signed) return String;
function DecImage(In_Image : UnSigned) return String;
end GPL_V2_Image_Pkg;
--end Image_Pkg;
--package body Image_Pkg is
package body GPL_V2_Image_Pkg is
function Image(In_Image : Time) return String is
variable L : Line; -- access type
variable W : String(1 to 14) := (others => ' ');
-- Long enough to hold a time string
begin
-- the WRITE procedure creates an object with "NEW".
-- L is passed as an output of the procedure.
Std.TextIO.WRITE(L, in_image);
-- Copy L.all onto W
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Bit) return String is
variable L : Line; -- access type
variable W : String(1 to 3) := (others => ' ');
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Bit_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Integer) return String is
variable L : Line; -- access type
variable W : String(1 to 32) := (others => ' ');
-- Long enough to hold a time string
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Real) return String is
variable L : Line; -- access type
variable W : String(1 to 32) := (others => ' ');
-- Long enough to hold a time string
begin
Std.TextIO.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Std_uLogic) return String is
variable L : Line; -- access type
variable W : String(1 to 3) := (others => ' ');
begin
IEEE.Std_Logic_Textio.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Std_uLogic_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
IEEE.Std_Logic_Textio.WRITE(L, in_image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Std_Logic_Vector) return String is
variable L : Line; -- access type
variable W : String(1 to In_Image'length) := (others => ' ');
begin
IEEE.Std_Logic_TextIO.WRITE(L, In_Image);
W(L.all'range) := L.all;
Deallocate(L);
return W;
end Image;
function Image(In_Image : Signed) return String is
begin
return Image(Std_Logic_Vector(In_Image));
end Image;
function Image(In_Image : UnSigned) return String is
begin
return Image(Std_Logic_Vector(In_Image));
end Image;
function HexImage(InStrg : String) return String is
subtype Int03_Typ is Integer range 0 to 3;
variable Result : string(1 to ((InStrg'length - 1)/4)+1) :=
(others => '0');
variable StrTo4 : string(1 to Result'length * 4) :=
(others => '0');
variable MTspace : Int03_Typ; -- Empty space to fill in
variable Str4 : String(1 to 4);
variable Group_v : Natural := 0;
begin
MTspace := Result'length * 4 - InStrg'length;
StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0'
Cnvrt_Lbl : for I in Result'range loop
Group_v := Group_v + 4; -- identifies end of bit # in a group of 4
Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters
case Str4 is
when "0000" => Result(I) := '0';
when "0001" => Result(I) := '1';
when "0010" => Result(I) := '2';
when "0011" => Result(I) := '3';
when "0100" => Result(I) := '4';
when "0101" => Result(I) := '5';
when "0110" => Result(I) := '6';
when "0111" => Result(I) := '7';
when "1000" => Result(I) := '8';
when "1001" => Result(I) := '9';
when "1010" => Result(I) := 'A';
when "1011" => Result(I) := 'B';
when "1100" => Result(I) := 'C';
when "1101" => Result(I) := 'D';
when "1110" => Result(I) := 'E';
when "1111" => Result(I) := 'F';
when "ZZZZ" => Result(I) := 'Z'; -- added 8/23/02
when others => Result(I) := 'X';
end case; -- Str4
end loop Cnvrt_Lbl;
return Result;
end HexImage;
function HexImage(In_Image : Bit_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Std_uLogic_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Std_Logic_Vector) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : Signed) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function HexImage(In_Image : UnSigned) return String is
begin
return HexImage(Image(In_Image));
end HexImage;
function DecImage(In_Image : Bit_Vector) return String is
variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer
(Unsigned(To_StdLogicVector
(In_Image_v(31 downto 1)))));
else
return Image(To_integer(Unsigned(To_StdLogicVector(In_Image))));
end if;
end DecImage;
function DecImage(In_Image : Std_uLogic_Vector) return String is
variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1)
:= In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(Unsigned(In_Image_v(31 downto 1))));
else
return Image(To_integer(Unsigned(In_Image)));
end if;
end DecImage;
function DecImage(In_Image : Std_Logic_Vector) return String is
variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1)
:= In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(Unsigned(In_Image_v(31 downto 1))));
else
return Image(To_integer(Unsigned(In_Image)));
end if;
end DecImage;
function DecImage(In_Image : Signed) return String is
variable In_Image_v : Signed(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(In_Image_v(31 downto 1)));
else
return Image(To_integer(In_Image));
end if;
end DecImage;
function DecImage(In_Image : UnSigned) return String is
variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image;
begin
if In_Image'length > 31 then
assert False
report "Number too large for Integer, clipping to 31 bits"
severity Warning;
return Image(To_integer(In_Image_v(31 downto 1)));
else
return Image(To_integer(In_Image));
end if;
end DecImage;
end GPL_V2_Image_Pkg;
--end Image_Pkg;
| lgpl-3.0 | d6f6484ffd387b8cc644c064d4335230 | 0.600662 | 3.634017 | false | false | false | false |
nussbrot/AdvPT | tpl/wb_reg_no_rst.tpl.vhd | 2 | 5,995 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, %TPL_YEAR% All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project : %TPL_PROJECT%
-- File : %TPL_VHDLFILE%
-- Created : %TPL_DATE%
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--*
--* @short Wishbone register module
--* Auto-generated by '%TPL_SCRIPT%' based on '%TPL_TPLFILE%'
--*
--* Needed Libraries and Packages:
--* @li ieee.std_logic_1164 standard multi-value logic package
--* @li ieee.numeric_std
--*
--* @author %TPL_USER%
--* @date %TPL_DATE%
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- %TPL_DATE% %TPL_USER%: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
%TPL_LIBRARY%
-------------------------------------------------------------------------------
ENTITY %TPL_MODULE% IS
GENERIC (
g_addr_bits : INTEGER := %TPL_WBSIZE%);
PORT (
-- Wishbone interface
clk : IN STD_LOGIC;
i_wb_cyc : IN STD_LOGIC;
i_wb_stb : IN STD_LOGIC;
i_wb_we : IN STD_LOGIC;
i_wb_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wb_addr : IN STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
i_wb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_ack : OUT STD_LOGIC;
o_wb_rty : OUT STD_LOGIC;
o_wb_err : OUT STD_LOGIC;
-- Custom ports
%TPL_PORTS%
);
END ENTITY %TPL_MODULE%;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF %TPL_MODULE% IS
-----------------------------------------------------------------------------
-- Procedures
-----------------------------------------------------------------------------
%TPL_PROCEDURES%
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
%TPL_CONSTANTS%
-----------------------------------------------------------------------------
-- WB interface signals
-----------------------------------------------------------------------------
SIGNAL s_wb_ack : STD_LOGIC;
SIGNAL s_wb_err : STD_LOGIC;
SIGNAL s_wb_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_data : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_int_we : STD_LOGIC_VECTOR(i_wb_sel'RANGE);
SIGNAL s_int_trd : STD_LOGIC;
SIGNAL s_int_twr : STD_LOGIC;
SIGNAL s_int_addr_valid : STD_LOGIC;
SIGNAL s_int_data_rb : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_wb_data : STD_LOGIC_VECTOR(o_wb_data'RANGE);
-----------------------------------------------------------------------------
-- Custom registers
-----------------------------------------------------------------------------
%TPL_REGISTERS%
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
--* purpose : Wishbone Bus Control
--* type : sequential, rising edge, no reset
wb_ctrl : PROCESS (clk)
BEGIN -- PROCESS wb_ctrl
IF rising_edge(clk) THEN
s_wb_ack <= '0';
s_wb_err <= '0';
s_int_data <= i_wb_data;
s_int_addr <= s_wb_addr;
s_int_we <= (OTHERS => '0');
s_int_trd <= '0';
s_int_twr <= '0';
-- check if anyone requests access
IF (s_wb_ack = '0' AND s_wb_err = '0' AND i_wb_cyc = '1' AND i_wb_stb = '1') THEN
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
IF (i_wb_we = '1') THEN
s_int_we <= i_wb_sel;
s_int_twr <= '1';
ELSE
s_int_trd <= '1';
END IF;
END IF;
s_wb_data <= s_int_data_rb;
END IF;
END PROCESS wb_ctrl;
s_wb_addr <= UNSIGNED(i_wb_addr);
o_wb_data <= s_wb_data;
o_wb_ack <= s_wb_ack;
o_wb_err <= s_wb_err;
o_wb_rty <= '0';
-----------------------------------------------------------------------------
-- WB address validation
WITH to_integer(s_wb_addr) SELECT
s_int_addr_valid <=
%TPL_ADDR_VALIDATION%
'0' WHEN OTHERS;
-----------------------------------------------------------------------------
--* purpose : register access
--* type : sequential, rising edge, high active synchronous reset
reg_access : PROCESS (clk)
BEGIN -- PROCESS reg_access
IF rising_edge(clk) THEN
-- default values / clear trigger signals
%TPL_REG_DEFAULT%
-- WRITE registers
CASE to_integer(s_int_addr) IS
%TPL_REG_WR%
WHEN OTHERS => NULL;
END CASE;
-- READ-ONLY registers (override WRITE registers)
%TPL_REG_RD%
END IF;
END PROCESS reg_access;
-----------------------------------------------------------------------------
-- WB output data multiplexer
WITH to_integer(s_wb_addr) SELECT
s_int_data_rb <=
%TPL_REG_DATA_OUT%
(OTHERS => '0') WHEN OTHERS;
-----------------------------------------------------------------------------
-- output mappings
%TPL_PORT_REG_OUT%
END ARCHITECTURE rtl;
| mit | 2bf6e4d32823448ac1ec659dc992eb71 | 0.415847 | 4.198179 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_cmd_io.vhd | 2 | 4,001 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_cmd_io
-- Date:2015-01-18
-- Author: Gideon
-- Description: I/O registers for controlling commands directly
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.usb_cmd_pkg.all;
entity usb_cmd_io is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
connected : in std_logic;
operational : in std_logic;
speed : in std_logic_vector(1 downto 0);
cmd_req : out t_usb_cmd_req;
cmd_resp : in t_usb_cmd_resp );
end entity;
architecture arch of usb_cmd_io is
signal done_latch : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if cmd_resp.done = '1' then
cmd_req.request <= '0';
done_latch <= '1';
end if;
io_resp <= c_io_resp_init;
if io_req.write = '1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when X"1" =>
cmd_req.request <= '1';
done_latch <= '0';
cmd_req.do_split <= io_req.data(7);
cmd_req.do_data <= io_req.data(6);
cmd_req.command <= c_usb_commands_decoded(to_integer(unsigned(io_req.data(2 downto 0))));
when X"6" => -- high of data buffer control
cmd_req.buffer_index <= unsigned(io_req.data(7 downto 6));
cmd_req.no_data <= io_req.data(5);
cmd_req.togglebit <= io_req.data(4);
cmd_req.data_length(9 downto 8) <= unsigned(io_req.data(1 downto 0));
when X"7" =>
cmd_req.data_length(7 downto 0) <= unsigned(io_req.data);
when X"A" =>
cmd_req.device_addr <= unsigned(io_req.data(6 downto 0));
when X"B" =>
cmd_req.endp_addr <= unsigned(io_req.data(3 downto 0));
when X"E" =>
cmd_req.split_hub_addr <= unsigned(io_req.data(6 downto 0));
when X"F" =>
cmd_req.split_port_addr <= unsigned(io_req.data(3 downto 0));
cmd_req.split_sc <= io_req.data(7);
cmd_req.split_sp <= io_req.data(6);
cmd_req.split_et <= io_req.data(5 downto 4);
when others =>
null;
end case;
elsif io_req.read = '1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when X"0" =>
io_resp.data(7) <= done_latch;
io_resp.data(6 downto 4) <= std_logic_vector(to_unsigned(t_usb_result'pos(cmd_resp.result), 3));
io_resp.data(2) <= cmd_resp.no_data;
io_resp.data(3) <= cmd_resp.togglebit;
io_resp.data(1 downto 0) <= std_logic_vector(cmd_resp.data_length(9 downto 8));
when X"1" =>
io_resp.data <= std_logic_vector(cmd_resp.data_length(7 downto 0));
when X"2" =>
io_resp.data(0) <= connected;
io_resp.data(1) <= operational;
io_resp.data(5 downto 4) <= speed;
when others =>
null;
end case;
end if;
if reset='1' then
done_latch <= '0';
cmd_req.request <= '0';
end if;
end if;
end process;
end arch;
| gpl-3.0 | 8e24caee9940250cf71a3bc4a5e124da | 0.435141 | 3.832375 | false | false | false | false |
trondd/mkjpeg | design/common/FIFO.vhd | 2 | 6,756 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity RAMF is
generic (
RAMD_W : INTEGER := 12;
RAMA_W : INTEGER := 6
);
port (
d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
);
end RAMF;
architecture RTL of RAMF is
type mem_type is array ((2**RAMA_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
signal mem : mem_type;
signal read_addr : STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library WORK;
entity FIFO is
generic (
DATA_WIDTH : INTEGER := 12;
ADDR_WIDTH : INTEGER := 2
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
rinc : in STD_LOGIC;
winc : in STD_LOGIC;
datai : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
datao : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
fullo : out STD_LOGIC;
emptyo : out STD_LOGIC;
count : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0)
);
end FIFO;
architecture RTL of FIFO is
signal raddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
signal waddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
signal count_reg : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal rd_en_reg : STD_LOGIC;
signal wr_en_reg : STD_LOGIC;
signal empty_reg : STD_LOGIC;
signal full_reg : STD_LOGIC;
signal ramq : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal ramd : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal ramwaddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
signal ramenw : STD_LOGIC;
signal ramraddr : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
signal ramenr : STD_LOGIC;
constant ZEROS_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0');
constant ONES_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
component RAMF
generic (
RAMD_W : INTEGER := 12;
RAMA_W : INTEGER := 6
);
port (
d : in STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
);
end component;
begin
U_RAMF : RAMF
generic map (
RAMD_W => DATA_WIDTH,
RAMA_W => ADDR_WIDTH
)
port map (
d => ramd,
waddr => ramwaddr,
raddr => ramraddr,
we => ramenw,
clk => clk,
q => ramq
);
ramd <= datai;
ramwaddr <= waddr_reg;
ramenw <= wr_en_reg;
ramraddr <= raddr_reg;
ramenr <= '1';
datao <= ramq;
emptyo <= empty_reg;
fullo <= full_reg;
rd_en_reg <= (rinc and not empty_reg);
wr_en_reg <= (winc and not full_reg);
count <= count_reg;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
empty_reg <= '1';
else
if count_reg = ZEROS_C or
(count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then
empty_reg <= '1';
else
empty_reg <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
full_reg <= '0';
else
if count_reg = 2**ADDR_WIDTH or
(count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then
full_reg <= '1';
else
full_reg <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
raddr_reg <= (others => '0');
else
if rd_en_reg = '1' then
raddr_reg <= raddr_reg + '1';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
waddr_reg <= (others => '0');
else
if wr_en_reg = '1' then
waddr_reg <= waddr_reg + '1';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
count_reg <= (others => '0');
else
if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then
if rd_en_reg = '1' then
count_reg <= count_reg - '1';
else
count_reg <= count_reg + '1';
end if;
end if;
end if;
end if;
end process;
end RTL;
| lgpl-3.0 | 3165bd2c6ccf6987318bde194864d5b2 | 0.413854 | 3.939359 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/u2p_cia_io.vhd | 1 | 6,320 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.io_bus_pkg.all;
entity u2p_cia_io is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
addr : out std_logic_vector(3 downto 0);
cs_n : out std_logic;
cs2 : out std_logic;
reset_n : out std_logic;
rw_n : out std_logic;
phi2 : out std_logic;
irq_n : in std_logic;
rising : out std_logic;
falling : out std_logic;
db_from_my_cia : in std_logic_vector(7 downto 0);
pb_from_my_cia : in std_logic_vector(7 downto 0);
hs_from_my_cia : in std_logic_vector(4 downto 0);
irq_from_my_cia : in std_logic;
db_to_cia : out std_logic_vector(7 downto 0);
db_from_cia : in std_logic_vector(7 downto 0);
db_drive : out std_logic;
pa_to_cia : out std_logic_vector(7 downto 0);
pa_from_cia : in std_logic_vector(7 downto 0);
pa_drive : out std_logic_vector(7 downto 0);
pb_to_cia : out std_logic_vector(7 downto 0);
pb_from_cia : in std_logic_vector(7 downto 0);
pb_drive : out std_logic_vector(7 downto 0);
hs_to_cia : out std_logic_vector(4 downto 0);
hs_from_cia : in std_logic_vector(4 downto 0);
hs_drive : out std_logic_vector(4 downto 0) );
end entity;
architecture rtl of u2p_cia_io is
signal reg_addr : std_logic_vector(3 downto 0);
signal reg_cs_n : std_logic;
signal reg_cs2 : std_logic;
signal reg_reset_n : std_logic;
signal reg_rw_n : std_logic;
signal reg_phi2 : std_logic;
signal reg_hs_to_cia : std_logic_vector(4 downto 0);
begin
process(clock, reset)
variable local : unsigned(3 downto 0);
begin
if reset = '1' then -- switched to asynchronous reset
reg_addr <= X"0";
reg_cs_n <= '1';
reg_cs2 <= '0';
reg_reset_n <= '1';
reg_rw_n <= '1';
reg_phi2 <= '0';
db_to_cia <= (others => '0');
pa_to_cia <= (others => '0');
pa_drive <= (others => '0');
pb_to_cia <= (others => '0');
pb_drive <= (others => '0');
reg_hs_to_cia <= (others => '0');
hs_drive <= (others => '0');
elsif rising_edge(clock) then
local := io_req.address(3 downto 0);
io_resp <= c_io_resp_init;
if io_req.read = '1' then
io_resp.ack <= '1';
case local is
when X"0" =>
io_resp.data(3 downto 0) <= reg_addr;
when X"1" =>
io_resp.data <= db_from_cia;
when X"2" | X"3" =>
io_resp.data(0) <= reg_cs_n;
io_resp.data(1) <= reg_cs2;
io_resp.data(2) <= reg_reset_n;
io_resp.data(3) <= reg_rw_n;
io_resp.data(4) <= reg_phi2;
when X"4" | X"5" =>
io_resp.data <= pa_from_cia;
when X"6" | X"7" =>
io_resp.data <= pb_from_cia;
when X"8" | X"9" =>
io_resp.data(4 downto 0) <= hs_from_cia;
io_resp.data(5) <= irq_n;
when X"B" =>
io_resp.data <= db_from_my_cia;
when X"C" =>
io_resp.data <= pb_from_my_cia;
when X"D" =>
io_resp.data(4 downto 0) <= hs_from_my_cia;
io_resp.data(5) <= not irq_from_my_cia;
when others =>
null;
end case;
end if;
rising <= '0';
falling <= '0';
if io_req.write = '1' then
io_resp.ack <= '1';
case local is
when X"0" =>
reg_addr <= io_req.data(3 downto 0);
when X"1" =>
db_to_cia <= io_req.data;
when X"2" =>
reg_cs_n <= reg_cs_n or io_req.data(0);
reg_cs2 <= reg_cs2 or io_req.data(1);
reg_reset_n <= reg_reset_n or io_req.data(2);
reg_rw_n <= reg_rw_n or io_req.data(3);
reg_phi2 <= reg_phi2 or io_req.data(4);
rising <= not reg_phi2 and io_req.data(4); -- pulse if it was zero.
when X"3" =>
reg_cs_n <= reg_cs_n and not io_req.data(0);
reg_cs2 <= reg_cs2 and not io_req.data(1);
reg_reset_n <= reg_reset_n and not io_req.data(2);
reg_rw_n <= reg_rw_n and not io_req.data(3);
reg_phi2 <= reg_phi2 and not io_req.data(4);
falling <= reg_phi2 and io_req.data(4); -- pulse if it was one.
when X"4" =>
pa_to_cia <= io_req.data;
when X"5" =>
pa_drive <= io_req.data;
when X"6" =>
pb_to_cia <= io_req.data;
when X"7" =>
pb_drive <= io_req.data;
when X"8" =>
reg_hs_to_cia <= reg_hs_to_cia or io_req.data(4 downto 0);
when X"9" =>
reg_hs_to_cia <= reg_hs_to_cia and not io_req.data(4 downto 0);
when X"A" =>
hs_drive <= io_req.data(4 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
addr <= reg_addr;
cs_n <= reg_cs_n;
cs2 <= reg_cs2;
reset_n <= reg_reset_n;
rw_n <= reg_rw_n;
phi2 <= reg_phi2;
hs_to_cia <= reg_hs_to_cia;
db_drive <= '1' when reg_rw_n = '0' and reg_cs_n = '0' and reg_cs2 = '1' else '0';
end architecture;
| gpl-3.0 | 039f571e9d759990307fb4c475e5cdcd | 0.416772 | 3.347458 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/nano_cpu/vhdl_source/nano_cpu.vhd | 1 | 7,370 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu is
port (
clock : in std_logic;
reset : in std_logic;
-- instruction/data ram
ram_addr : out std_logic_vector(9 downto 0);
ram_en : out std_logic;
ram_we : out std_logic;
ram_wdata : out std_logic_vector(15 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic := '0';
io_read : out std_logic := '0';
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic );
end entity;
architecture gideon of nano_cpu is
signal accu : unsigned(15 downto 0);
signal branch_taken : boolean;
signal n, z, c : boolean;
signal push : std_logic;
signal pop : std_logic;
type t_state is (fetch_inst, decode_inst, indirect, external);
type t_state_vector is record
state : t_state;
i_addr : unsigned(9 downto 0);
offset : unsigned(7 downto 0);
update_accu : std_logic;
update_flags : std_logic;
alu_oper : std_logic_vector(14 downto 12);
end record;
constant c_default : t_state_vector := (
state => fetch_inst,
i_addr => (others => '0'),
offset => X"00",
update_accu => '0',
update_flags => '0',
alu_oper => "000" );
signal cur, nxt : t_state_vector;
signal stack_top : std_logic_vector(cur.i_addr'range);
signal ram_en_i : std_logic;
begin
with ram_rdata(c_br_eq'range) select branch_taken <=
z when c_br_eq,
not z when c_br_neq,
n when c_br_mi,
not n when c_br_pl,
c when c_br_c,
not c when c_br_nc,
true when c_br_always,
true when c_br_call,
false when others;
io_wdata <= std_logic_vector(accu);
ram_wdata <= std_logic_vector(accu);
io_addr <= unsigned(ram_rdata(io_addr'range));
process(ram_rdata, cur, stack_top, branch_taken, stall)
variable v_inst : std_logic_vector(15 downto 11);
begin
ram_we <= '0';
ram_en_i <= '0';
io_write <= '0';
io_read <= '0';
push <= '0';
pop <= '0';
nxt <= cur;
v_inst := ram_rdata(v_inst'range);
case cur.state is
when fetch_inst =>
ram_addr <= std_logic_vector(cur.i_addr);
ram_en_i <= '1';
nxt.i_addr <= cur.i_addr + 1;
nxt.state <= decode_inst;
nxt.update_accu <= '0';
nxt.update_flags <= '0';
nxt.offset <= X"00";
when decode_inst =>
nxt.alu_oper <= ram_rdata(cur.alu_oper'range);
nxt.state <= fetch_inst;
ram_addr <= std_logic_vector(unsigned(ram_rdata(ram_addr'range)) + cur.offset);
-- IN instruction
if v_inst = c_in then
if ram_rdata(7) = '1' then -- optimization: for ulpi access only
nxt.state <= external;
end if;
io_read <= '1';
nxt.update_accu <= '1';
nxt.update_flags <= '1';
-- ALU instruction
elsif ram_rdata(15) = '0' then
ram_en_i <= '1';
nxt.update_accu <= ram_rdata(11);
nxt.update_flags <= '1';
-- BRANCH
elsif ram_rdata(c_branch'range) = c_branch then
if branch_taken then
nxt.i_addr <= unsigned(ram_rdata(cur.i_addr'range));
end if;
if ram_rdata(c_br_call'range) = c_br_call then
push <= '1';
end if;
-- SPECIALS
else
case v_inst is
when c_store =>
ram_we <= '1';
ram_en_i <= '1';
when c_load_ind | c_store_ind =>
ram_addr(ram_addr'high downto 3) <= (others => '1');
ram_en_i <= '1';
nxt.offset <= unsigned(ram_rdata(10 downto 3));
nxt.state <= indirect;
when c_out =>
io_write <= '1';
if ram_rdata(7) = '1' then -- optimization: for ulpi access only
nxt.state <= external;
end if;
when c_return =>
nxt.i_addr <= unsigned(stack_top);
pop <= '1';
when others =>
null;
end case;
end if;
when indirect =>
ram_addr <= std_logic_vector(unsigned(ram_rdata(ram_addr'range)) + cur.offset);
ram_en_i <= '1';
nxt.state <= fetch_inst;
-- differentiate between load and store
if cur.alu_oper = c_alu_load then
nxt.update_accu <= '1';
nxt.update_flags <= '1';
else
ram_we <= '1';
end if;
when external =>
ram_addr <= std_logic_vector(unsigned(ram_rdata(ram_addr'range)) + cur.offset);
-- differentiate between load and store (read and write)
if cur.alu_oper = c_alu_ext then
io_read <= stall;
nxt.update_accu <= '1';
nxt.update_flags <= '1';
else
io_write <= '1';
end if;
nxt.state <= fetch_inst;
when others =>
nxt.state <= fetch_inst;
end case;
end process;
ram_en <= ram_en_i and not stall;
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
cur <= c_default;
elsif stall='0' then
cur <= nxt;
end if;
end if;
end process;
i_alu: entity work.nano_alu
port map (
clock => clock,
reset => reset,
value_in => unsigned(ram_rdata),
ext_in => unsigned(io_rdata),
alu_oper => cur.alu_oper,
update_accu => cur.update_accu,
update_flag => cur.update_flags,
accu => accu,
z => z,
n => n,
c => c );
i_stack : entity work.distributed_stack
generic map (
width => stack_top'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => '0',
data_in => std_logic_vector(cur.i_addr),
data_out => stack_top,
full => open,
data_valid => open );
end architecture;
| gpl-3.0 | 2be646f2a5ee6c16e8b2ed214f19c922 | 0.43555 | 3.949625 | false | false | false | false |
ringof/radiofist_audio | ipcore_dir/fir_filter.vhd | 1 | 6,554 | --------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:fir_compiler:5.0
-- You must compile the wrapper file fir_filter.vhd when simulating
-- the core, fir_filter. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fir_filter IS
port (
sclr: in std_logic;
clk: in std_logic;
nd: in std_logic;
rfd: out std_logic;
rdy: out std_logic;
data_valid: out std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(40 downto 0));
END fir_filter;
ARCHITECTURE fir_filter_a OF fir_filter IS
-- synthesis translate_off
component wrapped_fir_filter
port (
sclr: in std_logic;
clk: in std_logic;
nd: in std_logic;
rfd: out std_logic;
rdy: out std_logic;
data_valid: out std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(40 downto 0));
end component;
-- Configuration specification
for all : wrapped_fir_filter use entity XilinxCoreLib.fir_compiler_v5_0(behavioral)
generic map(
coef_width => 16,
c_has_sclr => 1,
datapath_memtype => 0,
c_component_name => "fir_filter",
c_family => "spartan6",
round_mode => 0,
output_width => 41,
sclr_deterministic => 1,
col_config => "1",
coef_memtype => 0,
clock_freq => 6000000,
symmetry => 1,
col_pipe_len => 4,
c_latency => 20,
chan_sel_width => 1,
c_xdevicefamily => "spartan6",
c_has_nd => 1,
allow_approx => 0,
num_channels => 1,
data_width => 25,
filter_sel_width => 1,
sample_freq => 150000,
coef_reload => 0,
neg_symmetry => 0,
filter_type => 1,
data_type => 0,
accum_width => 41,
rate_change_type => 0,
ipbuff_memtype => 0,
c_optimization => 1,
output_reg => 1,
data_memtype => 0,
c_has_data_valid => 1,
decim_rate => 2,
coef_type => 0,
filter_arch => 1,
interp_rate => 1,
num_taps => 37,
c_mem_init_file => "fir_filter.mif",
zero_packing_factor => 1,
num_paths => 1,
num_filts => 1,
col_mode => 0,
c_has_ce => 0,
chan_in_adv => 0,
opbuff_memtype => 0,
odd_symmetry => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fir_filter
port map (
sclr => sclr,
clk => clk,
nd => nd,
rfd => rfd,
rdy => rdy,
data_valid => data_valid,
din => din,
dout => dout);
-- synthesis translate_on
END fir_filter_a;
| mit | d7097add0870c1e762ef395a531faeaf | 0.530668 | 4.244819 | false | false | false | false |
xiadz/oscilloscope | ipcore_dir/char_rom_memory.vhd | 1 | 5,368 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file char_rom_memory.vhd when simulating
-- the core, char_rom_memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY char_rom_memory IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END char_rom_memory;
ARCHITECTURE char_rom_memory_a OF char_rom_memory IS
-- synthesis translate_off
COMPONENT wrapped_char_rom_memory
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_char_rom_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v6_1(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "char_rom_memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 1,
c_read_width_b => 1,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 1,
c_write_width_b => 1,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_char_rom_memory
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END char_rom_memory_a;
| mit | e1e2efcc45a40292a3979d6e865f80a2 | 0.533159 | 3.988113 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_sim/usb_harness_nano.vhd | 1 | 3,091 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_harness
-- Date:2015-02-14
-- Author: Gideon
-- Description: Harness for USB Host Controller with memory controller
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity usb_harness_nano is
port (
nyet_count : in natural := 2;
ack_on_ping : in boolean := true;
transfer_size : in natural := 256;
packet_size : in natural := 256;
interrupt : out std_logic;
clocks_stopped : in boolean := false );
end entity;
architecture arch of usb_harness_nano is
signal sys_clock : std_logic := '1';
signal sys_reset : std_logic;
signal clock : std_logic := '0';
signal reset : std_logic;
signal sys_io_req : t_io_req;
signal sys_io_resp : t_io_resp;
signal sys_mem_req : t_mem_req_32;
signal sys_mem_resp : t_mem_resp_32;
signal ulpi_nxt : std_logic;
signal ulpi_stp : std_logic;
signal ulpi_dir : std_logic;
signal ulpi_data : std_logic_vector(7 downto 0);
begin
sys_clock <= not sys_clock after 10 ns when not clocks_stopped;
sys_reset <= '1', '0' after 50 ns;
clock <= not clock after 8.333 ns when not clocks_stopped;
reset <= '1', '0' after 250 ns;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io" )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp );
i_host: entity work.usb_host_nano
generic map (
g_big_endian => false,
g_simulation => true )
port map (
clock => clock,
reset => reset,
ulpi_nxt => ulpi_nxt,
ulpi_dir => ulpi_dir,
ulpi_stp => ulpi_stp,
ulpi_data => ulpi_data,
sys_irq => interrupt,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_mem_req => sys_mem_req,
sys_mem_resp=> sys_mem_resp,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
i_ulpi_phy: entity work.ulpi_master_bfm
generic map (
g_given_name => "device" )
port map (
clock => clock,
reset => reset,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_dir => ulpi_dir,
ulpi_data => ulpi_data );
i_device: entity work.usb_device_model
port map (
transfer_size => transfer_size,
packet_size => packet_size,
nyet_count => nyet_count,
ack_on_ping => ack_on_ping
);
i_memory: entity work.mem_bus_32_slave_bfm
generic map (
g_name => "memory",
g_latency => 3
)
port map (
clock => sys_clock,
req => sys_mem_req,
resp => sys_mem_resp
);
end arch;
| gpl-3.0 | 14f3d60303352964314c9d2a30f279e4 | 0.50825 | 3.524515 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_source/dm_simple.vhd | 1 | 13,318 | --------------------------------------------------------------------------------
-- Entity: dm_simple
-- Date: 2014-12-08
-- Author: Gideon
--
-- Description: Simple direct mapped cache controller, compatible with the
-- I/D buses of the mblite
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.core_Pkg.all;
-- type dmem_in_type is record
-- dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- ena_i : std_logic;
-- end record;
--
-- type dmem_out_type is record
-- dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
-- sel_o : std_logic_vector(3 downto 0);
-- we_o : std_logic;
-- ena_o : std_logic;
-- end record;
-- type imem_in_type is record
-- dat_i : std_logic_vector(CFG_dmem_WIDTH - 1 downto 0);
-- ena_i : std_logic;
-- end record;
--
-- type imem_out_type is record
-- adr_o : std_logic_vector(CFG_dmem_SIZE - 1 downto 0);
-- ena_o : std_logic;
-- end record;
entity dm_simple is
generic (
g_address_swap : std_logic_vector(31 downto 0) := X"00000000";
g_registered_out: boolean := false;
g_data_register : boolean := true;
g_mem_direct : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
disable : in std_logic := '0';
dmem_i : in dmem_out_type;
dmem_o : out dmem_in_type;
mem_o : out dmem_out_type;
mem_i : in dmem_in_type );
end entity;
architecture arch of dm_simple is
constant c_cachable_area_bits : natural := 25;
constant c_cache_size_bits : natural := 11; -- 2**11 bytes = 2KB
-- constant c_tag_compare_width : natural := c_cachable_area_bits - c_cache_size_bits;
constant c_tag_size_bits : natural := c_cache_size_bits - 2; -- 4 bytes per cache entry
type t_tag is record
addr_high : std_logic_vector(c_cachable_area_bits-1 downto c_cache_size_bits);
valid : std_logic;
end record;
constant c_valid_zero_tag : t_tag := ( addr_high => (others => '0'), valid => '1' );
function extend32(a : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
ret(a'length-1 downto 0) := a;
return ret;
end function;
function address_to_tag (addr : std_logic_vector;
valid : std_logic) return t_tag is
variable v_addr : std_logic_vector(31 downto 0);
variable ret : t_tag;
begin
v_addr := extend32(addr);
ret.addr_high := v_addr(c_cachable_area_bits-1 downto c_cache_size_bits);
ret.valid := valid;
return ret;
end function;
constant c_tag_width : natural := c_cachable_area_bits - c_cache_size_bits + 1;
function tag_to_vector(i: t_tag) return std_logic_vector is
begin
return i.valid & i.addr_high;
end function;
constant c_valid_zero_tag_vector : std_logic_vector(c_tag_width-1 downto 0) := tag_to_vector(c_valid_zero_tag);
function vector_to_tag(i : std_logic_vector(c_tag_width-1 downto 0)) return t_tag is
variable ret : t_tag;
begin
ret.valid := i(c_tag_width-1);
ret.addr_high := i(c_tag_width-2 downto 0);
return ret;
end function;
function get_tag_index (addr : std_logic_vector) return unsigned is
begin
return unsigned(addr(c_tag_size_bits+1 downto 2));
end function;
function is_cacheable (addr : std_logic_vector) return boolean is
variable v_addr : std_logic_vector(31 downto 0);
begin
v_addr := extend32(addr);
return unsigned(v_addr(31 downto c_cachable_area_bits)) = 0;
end function;
-- type t_tag_ram is record
--
-- end record;
signal tag_ram_a_address : unsigned(c_tag_size_bits-1 downto 0);
signal tag_ram_a_rdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_wdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_en : std_logic;
signal tag_ram_a_we : std_logic;
signal tag_ram_b_address : unsigned(c_tag_size_bits-1 downto 0) := (others => '0');
signal tag_ram_b_rdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_wdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_en : std_logic := '0';
signal tag_ram_b_we : std_logic := '0';
signal cache_ram_a_address : unsigned(c_cache_size_bits-1 downto 2);
signal cache_ram_a_rdata : std_logic_vector(31 downto 0);
signal cache_ram_a_wdata : std_logic_vector(31 downto 0);
signal cache_ram_a_en : std_logic;
signal cache_ram_a_we : std_logic;
signal cache_ram_b_address : unsigned(c_cache_size_bits-1 downto 2) := (others => '0');
signal cache_ram_b_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_en : std_logic := '0';
signal cache_ram_b_we : std_logic := '0';
signal d_tag_ram_out : t_tag;
signal d_miss : std_logic;
signal data_reg : std_logic_vector(31 downto 0);
signal dmem_r : dmem_out_type;
signal dmem_o_comb : dmem_in_type;
signal dmem_o_reg : dmem_in_type;
type t_state is (idle, fill, reg);
signal state : t_state;
begin
i_tag_ram: entity work.dpram_sc
generic map (
g_width_bits => c_tag_width,
g_depth_bits => c_tag_size_bits,
g_global_init => c_valid_zero_tag_vector,
g_read_first_a => false, --true,
g_read_first_b => false, --true,
g_storage => "block" )
port map (
clock => clock,
a_address => tag_ram_a_address,
a_rdata => tag_ram_a_rdata,
a_wdata => tag_ram_a_wdata,
a_en => tag_ram_a_en,
a_we => tag_ram_a_we,
b_address => tag_ram_b_address,
b_rdata => tag_ram_b_rdata,
b_wdata => tag_ram_b_wdata,
b_en => tag_ram_b_en,
b_we => tag_ram_b_we );
i_cache_ram: entity work.dpram_sc
generic map (
g_width_bits => 32,
g_depth_bits => c_cache_size_bits-2,
g_global_init => X"FFFFFFFF",
g_read_first_a => false, --true,
g_read_first_b => false, --true,
g_storage => "block" )
port map (
clock => clock,
a_address => cache_ram_a_address,
a_rdata => cache_ram_a_rdata,
a_wdata => cache_ram_a_wdata,
a_en => cache_ram_a_en,
a_we => cache_ram_a_we,
b_address => cache_ram_b_address,
b_rdata => cache_ram_b_rdata,
b_wdata => cache_ram_b_wdata,
b_en => cache_ram_b_en,
b_we => cache_ram_b_we );
d_tag_ram_out <= vector_to_tag(tag_ram_a_rdata);
-- handle the dmem address request here; split it up
process(state, dmem_i, dmem_r, mem_i, d_tag_ram_out, cache_ram_a_rdata, data_reg, disable)
begin
if g_registered_out then
dmem_o_comb.ena_i <= '0'; -- registered out, use this signal as register load enable
else
dmem_o_comb.ena_i <= '1'; -- direct out, use this signal as enable output
end if;
dmem_o_comb.dat_i <= (others => 'X');
d_miss <= '0';
tag_ram_a_address <= get_tag_index(dmem_i.adr_o);
tag_ram_a_wdata <= (others => 'X');
tag_ram_a_we <= '0';
tag_ram_a_en <= '0';
cache_ram_a_address <= unsigned(dmem_i.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_a_wdata <= dmem_i.dat_o;
cache_ram_a_we <= '0';
cache_ram_a_en <= '0';
tag_ram_b_address <= get_tag_index(dmem_r.adr_o);
tag_ram_b_wdata <= tag_to_vector(address_to_tag(dmem_r.adr_o, '1'));
tag_ram_b_we <= '0';
tag_ram_b_en <= '0';
cache_ram_b_address <= unsigned(dmem_r.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_b_wdata <= mem_i.dat_i;
cache_ram_b_we <= '0';
cache_ram_b_en <= '0';
if dmem_i.ena_o = '1' then -- processor address is valid, let's do our thing
if dmem_i.we_o = '0' then -- read
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
else -- write
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
tag_ram_a_we <= '1';
cache_ram_a_we <= '1';
if dmem_i.sel_o = "1111" then -- full word results in a valid cache line
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '1')); -- valid
else
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '0')); -- invalid
end if;
end if;
end if;
-- response to processor
case state is
when idle =>
if dmem_r.ena_o = '1' then -- registered (=delayed request valid)
if (address_to_tag(dmem_r.adr_o, '1') = d_tag_ram_out) and (dmem_r.we_o='0') and is_cacheable(dmem_r.adr_o) and disable = '0' then -- read hit!
dmem_o_comb.dat_i <= cache_ram_a_rdata;
dmem_o_comb.ena_i <= '1';
else -- miss or write
dmem_o_comb.ena_i <= '0';
d_miss <= '1';
end if;
end if; -- else use default values, hence X
when fill =>
dmem_o_comb.ena_i <= '0';
if mem_i.ena_i = '1' then
if g_mem_direct then
dmem_o_comb.dat_i <= mem_i.dat_i; -- ouch, 32-bit multiplexer!
dmem_o_comb.ena_i <= '1';
end if;
if dmem_r.we_o='0' then -- was a read
tag_ram_b_en <= '1';
cache_ram_b_en <= '1';
tag_ram_b_we <= '1';
cache_ram_b_we <= '1';
end if;
end if;
when reg =>
dmem_o_comb.dat_i <= data_reg; -- ouch, 3rd input to 32-bit multiplexer!
dmem_o_comb.ena_i <= '1';
end case;
end process;
-- type dmem_out_type is record
-- dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
-- sel_o : std_logic_vector(3 downto 0);
-- we_o : std_logic;
-- ena_o : std_logic;
-- end record;
r_comb: if not g_registered_out generate
dmem_o <= dmem_o_comb;
end generate;
r_reg: if g_registered_out generate
dmem_o <= dmem_o_reg;
end generate;
process(state, dmem_r, d_miss)
begin
mem_o <= dmem_r;
mem_o.adr_o <= dmem_r.adr_o xor g_address_swap(dmem_r.adr_o'range);
mem_o.ena_o <= d_miss;
end process;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
if d_miss = '1' then
state <= fill;
end if;
when fill =>
if mem_i.ena_i = '1' then
data_reg <= mem_i.dat_i; -- ouch, 32-bit register
dmem_r.ena_o <= '0';
if g_registered_out then
state <= idle;
elsif dmem_i.ena_o = '0' then
if g_data_register then
state <= reg;
else
report "No data register support, but it seems to be needed!"
severity error;
end if;
else
state <= idle;
end if;
end if;
when reg =>
if dmem_i.ena_o = '1' then
if d_miss = '1' then
state <= fill;
else
state <= idle;
end if;
end if;
end case;
if dmem_i.ena_o = '1' then
dmem_o_reg.ena_i <= '0';
elsif dmem_o_comb.ena_i = '1' then
dmem_o_reg.dat_i <= dmem_o_comb.dat_i;
dmem_o_reg.ena_i <= '1';
end if;
if dmem_i.ena_o = '1' then
dmem_r <= dmem_i;
end if;
if reset='1' then
state <= idle;
dmem_o_reg.ena_i <= '1';
end if;
end if;
end process;
end arch;
| gpl-3.0 | 91e8e052f75f44264cadbd942b18b766 | 0.485809 | 3.351283 | false | false | false | false |
mkreider/cocotb2 | tests/designs/viterbi_decoder_axi4s/src/recursion.vhd | 2 | 2,907 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Recursion unit for recursive code.
--! @author Markus Fehrenz
--! @date 2011/01/12
--!
--! @details The recusion handling buffers the reorder ouput and
--! calculates the correct output depending on the feedback polynomial.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
entity recursion is
port(
clk : in std_logic;
rst : in std_logic;
--
-- Decoded bits input from the reordering units in std_logic
--
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic;
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
--
-- Output decoded bits convolved with the feedback polynomial
--
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic;
m_axis_output_tlast : out std_logic;
m_axis_output_tready : in std_logic
);
end entity recursion;
architecture rtl of recursion is
signal recursion_sreg : unsigned(ENCODER_MEMORY_DEPTH downto 0);
signal s_axis_input_tready_int : std_logic;
signal m_axis_output_tvalid_int : std_logic;
begin
s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' or m_axis_output_tvalid_int = '0' else
'0';
s_axis_input_tready <= s_axis_input_tready_int;
m_axis_output_tvalid <= m_axis_output_tvalid_int;
-- Use the feedback polynomial to convolve the global path.
pr_recursion : process(clk) is
variable v_bit : std_logic := '0';
variable v_recursion_state : unsigned(ENCODER_MEMORY_DEPTH downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
recursion_sreg <= (others => '0');
m_axis_output_tdata <= '0';
m_axis_output_tlast <= '0';
else
m_axis_output_tvalid_int <= s_axis_input_tvalid;
if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
-- move current decoded output bits into shift register and reset if last flag is valid
if s_axis_input_tlast = '1' then
recursion_sreg <= (others => '0');
else
recursion_sreg <= s_axis_input_tdata & recursion_sreg(ENCODER_MEMORY_DEPTH downto 1);
end if;
-- convolve with feedback polynomial with the output register.
v_bit := '0';
v_recursion_state := (s_axis_input_tdata & recursion_sreg(ENCODER_MEMORY_DEPTH downto 1)) and
('1' & to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH));
for i in ENCODER_MEMORY_DEPTH downto 0 loop
v_bit := v_bit xor v_recursion_state(i);
end loop;
m_axis_output_tdata <= v_bit;
m_axis_output_tlast <= s_axis_input_tlast;
end if;
end if;
end if;
end process pr_recursion;
end architecture rtl;
| bsd-3-clause | c91fd04842ad4571d257f14cb429cbb1 | 0.675955 | 3.102455 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/gprf.vhd | 2 | 2,456 | ----------------------------------------------------------------------------------------------
--
-- Input file : gprf.vhd
-- Design name : gprf
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The general purpose register infers memory blocks to implement
-- the register file. All outputs are registered, possibly by using
-- registered memory elements.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity gprf is port
(
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end gprf;
-- This architecture is the default implementation. It
-- consists of three dual port memories. Other
-- architectures can be added while configurations can
-- control the implemented architecture.
architecture arch of gprf is
signal write : std_logic;
begin
write <= '1' when (gprf_i.wre_i = '1') and (unsigned(gprf_i.adr_w_i) /= 0) else '0';
a : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_a_o,
adr_i => gprf_i.adr_a_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => write,
clk_i => clk_i
);
b : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_b_o,
adr_i => gprf_i.adr_b_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => write,
clk_i => clk_i
);
d : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_d_o,
adr_i => gprf_i.adr_d_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => write,
clk_i => clk_i
);
end arch;
| gpl-3.0 | 88add9b6b21649b62887966ea623b748 | 0.47272 | 3.473833 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/c2n_playback/vhdl_source/tape_speed_control.vhd | 1 | 2,842 | --------------------------------------------------------------------------------
-- Entity: tape_speed_control
-- Date:2016-04-17
-- Author: Gideon
--
-- Description: This module controls the tape speed, based on the motor pin.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tape_speed_control is
generic (
g_clock_freq : natural := 50_000_000 );
port (
clock : in std_logic;
reset : in std_logic;
speed_sel : in std_logic; -- '1' for NTSC
motor_en : in std_logic;
tick_out : out std_logic );
end entity;
architecture arch of tape_speed_control is
constant c_pdm_target_pal : natural := ( 985250 * 512) / (g_clock_freq / 128);
constant c_pdm_target_avg : natural := (1000000 * 512) / (g_clock_freq / 128);
constant c_pdm_target_ntsc : natural := (1022727 * 512) / (g_clock_freq / 128);
constant c_slowdown_ticks : natural := 300 * (g_clock_freq / 1000);
constant c_speedup_ticks : natural := 120 * (g_clock_freq / 1000);
constant c_slowdown_divider : natural := c_slowdown_ticks / c_pdm_target_avg;
constant c_speedup_divider : natural := c_speedup_ticks / c_pdm_target_avg;
signal divider : natural range 0 to c_slowdown_divider - 1;
signal pdm_value : unsigned(10 downto 0);
signal pdm_accu : unsigned(15 downto 0);
signal pdm_target : unsigned(10 downto 0);
begin
pdm_target <= to_unsigned(c_pdm_target_pal, 11) when speed_sel = '0' else
to_unsigned(c_pdm_target_ntsc, 11);
process(clock)
variable v_sum : unsigned(16 downto 0);
begin
if rising_edge(clock) then
if divider = 0 then
if motor_en = '1' and pdm_value < pdm_target then
pdm_value <= pdm_value + 1;
divider <= c_speedup_divider - 1;
elsif motor_en = '1' and pdm_value > pdm_target then
pdm_value <= pdm_value - 1;
divider <= c_slowdown_divider - 1;
elsif motor_en = '0' and pdm_value /= 0 then
pdm_value <= pdm_value - 1;
divider <= c_slowdown_divider - 1;
end if;
else
divider <= divider - 1;
end if;
v_sum := ('0' & pdm_accu) + ('0' & pdm_value);
tick_out <= v_sum(v_sum'high);
pdm_accu <= v_sum(pdm_accu'range);
if reset='1' then
divider <= 0;
pdm_value <= (others => '0');
pdm_accu <= (others => '0');
end if;
end if;
end process;
end arch;
| gpl-3.0 | d99b37127194f26969dd7896c03ab687 | 0.493666 | 3.779255 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20_gpio_block_1.vhd | 1 | 3,970 | -- cb20_gpio_block_1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_1 is
generic (
number_of_gpios : integer := 8;
unique_id : std_logic_vector(31 downto 0) := "00010010011100000101000000000010"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- avalon_slave_0.readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => '0'); -- .address
isl_avs_read : in std_logic := '0'; -- .read
isl_avs_write : in std_logic := '0'; -- .write
osl_avs_waitrequest : out std_logic; -- .waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
isl_clk : in std_logic := '0'; -- clock_sink.clk
isl_reset_n : in std_logic := '0'; -- reset_sink.reset_n
oslv_gpios : inout std_logic_vector(7 downto 0) := (others => '0') -- conduit_end.export
);
end entity cb20_gpio_block_1;
architecture rtl of cb20_gpio_block_1 is
component avalon_gpio_interface is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component avalon_gpio_interface;
begin
number_of_gpios_check : if number_of_gpios /= 8 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
unique_id_check : if unique_id /= "00010010011100000101000000000010" generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
gpio_block_1 : component avalon_gpio_interface
generic map (
number_of_gpios => 8,
unique_id => "00010010011100000101000000000010"
)
port map (
oslv_avs_read_data => oslv_avs_read_data, -- avalon_slave_0.readdata
islv_avs_address => islv_avs_address, -- .address
isl_avs_read => isl_avs_read, -- .read
isl_avs_write => isl_avs_write, -- .write
osl_avs_waitrequest => osl_avs_waitrequest, -- .waitrequest
islv_avs_write_data => islv_avs_write_data, -- .writedata
islv_avs_byteenable => islv_avs_byteenable, -- .byteenable
isl_clk => isl_clk, -- clock_sink.clk
isl_reset_n => isl_reset_n, -- reset_sink.reset_n
oslv_gpios => oslv_gpios -- conduit_end.export
);
end architecture rtl; -- of cb20_gpio_block_1
| apache-2.0 | a2e03a8e373b4d19203df741b2f341fc | 0.522166 | 3.538324 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/packages/vhdl_source/tl_vector_pkg.vhd | 2 | 27,538 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2007 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : tl_vector_pkg
-- Author : Edwin Hakkennes <[email protected]>
-------------------------------------------------------------------------------
-- Description: tl vector package, types and functions on vectors (of vectors)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tl_vector_pkg is
-- type to define vector ranges. Use left and right instead of high and low, to
-- make it possible to encode both 'to' and 'downto' vectors.
type t_vector_range is
record
left : integer;
right : integer;
end record;
-------------------------------------------------------------------------------
-- arrays of vectors
-------------------------------------------------------------------------------
type t_std_logic_1_vector is array (integer range <>) of std_logic_vector(0 downto 0);
type t_std_logic_2_vector is array (integer range <>) of std_logic_vector(1 downto 0);
type t_std_logic_3_vector is array (integer range <>) of std_logic_vector(2 downto 0);
type t_std_logic_4_vector is array (integer range <>) of std_logic_vector(3 downto 0);
type t_std_logic_5_vector is array (integer range <>) of std_logic_vector(4 downto 0);
type t_std_logic_6_vector is array (integer range <>) of std_logic_vector(5 downto 0);
type t_std_logic_7_vector is array (integer range <>) of std_logic_vector(6 downto 0);
type t_std_logic_8_vector is array (integer range <>) of std_logic_vector(7 downto 0);
type t_std_logic_9_vector is array (integer range <>) of std_logic_vector(8 downto 0);
type t_std_logic_10_vector is array (integer range <>) of std_logic_vector(9 downto 0);
type t_std_logic_11_vector is array (integer range <>) of std_logic_vector(10 downto 0);
type t_std_logic_12_vector is array (integer range <>) of std_logic_vector(11 downto 0);
type t_std_logic_13_vector is array (integer range <>) of std_logic_vector(12 downto 0);
type t_std_logic_14_vector is array (integer range <>) of std_logic_vector(13 downto 0);
type t_std_logic_15_vector is array (integer range <>) of std_logic_vector(14 downto 0);
type t_std_logic_16_vector is array (integer range <>) of std_logic_vector(15 downto 0);
type t_std_logic_17_vector is array (integer range <>) of std_logic_vector(16 downto 0);
type t_std_logic_18_vector is array (integer range <>) of std_logic_vector(17 downto 0);
type t_std_logic_19_vector is array (integer range <>) of std_logic_vector(18 downto 0);
type t_std_logic_20_vector is array (integer range <>) of std_logic_vector(19 downto 0);
type t_std_logic_21_vector is array (integer range <>) of std_logic_vector(20 downto 0);
type t_std_logic_22_vector is array (integer range <>) of std_logic_vector(21 downto 0);
type t_std_logic_23_vector is array (integer range <>) of std_logic_vector(22 downto 0);
type t_std_logic_24_vector is array (integer range <>) of std_logic_vector(23 downto 0);
type t_std_logic_25_vector is array (integer range <>) of std_logic_vector(24 downto 0);
type t_std_logic_26_vector is array (integer range <>) of std_logic_vector(25 downto 0);
type t_std_logic_27_vector is array (integer range <>) of std_logic_vector(26 downto 0);
type t_std_logic_28_vector is array (integer range <>) of std_logic_vector(27 downto 0);
type t_std_logic_29_vector is array (integer range <>) of std_logic_vector(28 downto 0);
type t_std_logic_30_vector is array (integer range <>) of std_logic_vector(29 downto 0);
type t_std_logic_31_vector is array (integer range <>) of std_logic_vector(30 downto 0);
type t_std_logic_32_vector is array (integer range <>) of std_logic_vector(31 downto 0);
type t_std_logic_36_vector is array (integer range <>) of std_logic_vector(35 downto 0);
type t_std_logic_48_vector is array (integer range <>) of std_logic_vector(47 downto 0);
type t_std_logic_56_vector is array (integer range <>) of std_logic_vector(55 downto 0);
type t_std_logic_64_vector is array (integer range <>) of std_logic_vector(63 downto 0);
type t_std_logic_128_vector is array (integer range <>) of std_logic_vector(127 downto 0);
type t_std_logic_256_vector is array (integer range <>) of std_logic_vector(255 downto 0);
type t_std_logic_512_vector is array (integer range <>) of std_logic_vector(511 downto 0);
type t_signed_1_vector is array (integer range <>) of signed(0 downto 0);
type t_signed_2_vector is array (integer range <>) of signed(1 downto 0);
type t_signed_3_vector is array (integer range <>) of signed(2 downto 0);
type t_signed_4_vector is array (integer range <>) of signed(3 downto 0);
type t_signed_5_vector is array (integer range <>) of signed(4 downto 0);
type t_signed_6_vector is array (integer range <>) of signed(5 downto 0);
type t_signed_7_vector is array (integer range <>) of signed(6 downto 0);
type t_signed_8_vector is array (integer range <>) of signed(7 downto 0);
type t_signed_9_vector is array (integer range <>) of signed(8 downto 0);
type t_signed_10_vector is array (integer range <>) of signed(9 downto 0);
type t_signed_11_vector is array (integer range <>) of signed(10 downto 0);
type t_signed_12_vector is array (integer range <>) of signed(11 downto 0);
type t_signed_13_vector is array (integer range <>) of signed(12 downto 0);
type t_signed_14_vector is array (integer range <>) of signed(13 downto 0);
type t_signed_15_vector is array (integer range <>) of signed(14 downto 0);
type t_signed_16_vector is array (integer range <>) of signed(15 downto 0);
type t_signed_17_vector is array (integer range <>) of signed(16 downto 0);
type t_signed_18_vector is array (integer range <>) of signed(17 downto 0);
type t_signed_19_vector is array (integer range <>) of signed(18 downto 0);
type t_signed_20_vector is array (integer range <>) of signed(19 downto 0);
type t_signed_21_vector is array (integer range <>) of signed(20 downto 0);
type t_signed_22_vector is array (integer range <>) of signed(21 downto 0);
type t_signed_23_vector is array (integer range <>) of signed(22 downto 0);
type t_signed_24_vector is array (integer range <>) of signed(23 downto 0);
type t_signed_25_vector is array (integer range <>) of signed(24 downto 0);
type t_signed_26_vector is array (integer range <>) of signed(25 downto 0);
type t_signed_27_vector is array (integer range <>) of signed(26 downto 0);
type t_signed_28_vector is array (integer range <>) of signed(27 downto 0);
type t_signed_29_vector is array (integer range <>) of signed(28 downto 0);
type t_signed_30_vector is array (integer range <>) of signed(29 downto 0);
type t_signed_31_vector is array (integer range <>) of signed(30 downto 0);
type t_signed_32_vector is array (integer range <>) of signed(31 downto 0);
type t_signed_36_vector is array (integer range <>) of signed(35 downto 0);
type t_signed_64_vector is array (integer range <>) of signed(63 downto 0);
type t_signed_128_vector is array (integer range <>) of signed(127 downto 0);
type t_signed_256_vector is array (integer range <>) of signed(255 downto 0);
type t_signed_512_vector is array (integer range <>) of signed(511 downto 0);
type t_unsigned_1_vector is array (integer range <>) of unsigned(0 downto 0);
type t_unsigned_2_vector is array (integer range <>) of unsigned(1 downto 0);
type t_unsigned_3_vector is array (integer range <>) of unsigned(2 downto 0);
type t_unsigned_4_vector is array (integer range <>) of unsigned(3 downto 0);
type t_unsigned_5_vector is array (integer range <>) of unsigned(4 downto 0);
type t_unsigned_6_vector is array (integer range <>) of unsigned(5 downto 0);
type t_unsigned_7_vector is array (integer range <>) of unsigned(6 downto 0);
type t_unsigned_8_vector is array (integer range <>) of unsigned(7 downto 0);
type t_unsigned_9_vector is array (integer range <>) of unsigned(8 downto 0);
type t_unsigned_10_vector is array (integer range <>) of unsigned(9 downto 0);
type t_unsigned_11_vector is array (integer range <>) of unsigned(10 downto 0);
type t_unsigned_12_vector is array (integer range <>) of unsigned(11 downto 0);
type t_unsigned_13_vector is array (integer range <>) of unsigned(12 downto 0);
type t_unsigned_14_vector is array (integer range <>) of unsigned(13 downto 0);
type t_unsigned_15_vector is array (integer range <>) of unsigned(14 downto 0);
type t_unsigned_16_vector is array (integer range <>) of unsigned(15 downto 0);
type t_unsigned_17_vector is array (integer range <>) of unsigned(16 downto 0);
type t_unsigned_18_vector is array (integer range <>) of unsigned(17 downto 0);
type t_unsigned_19_vector is array (integer range <>) of unsigned(18 downto 0);
type t_unsigned_20_vector is array (integer range <>) of unsigned(19 downto 0);
type t_unsigned_21_vector is array (integer range <>) of unsigned(20 downto 0);
type t_unsigned_22_vector is array (integer range <>) of unsigned(21 downto 0);
type t_unsigned_23_vector is array (integer range <>) of unsigned(22 downto 0);
type t_unsigned_24_vector is array (integer range <>) of unsigned(23 downto 0);
type t_unsigned_25_vector is array (integer range <>) of unsigned(24 downto 0);
type t_unsigned_26_vector is array (integer range <>) of unsigned(25 downto 0);
type t_unsigned_27_vector is array (integer range <>) of unsigned(26 downto 0);
type t_unsigned_28_vector is array (integer range <>) of unsigned(27 downto 0);
type t_unsigned_29_vector is array (integer range <>) of unsigned(28 downto 0);
type t_unsigned_30_vector is array (integer range <>) of unsigned(29 downto 0);
type t_unsigned_31_vector is array (integer range <>) of unsigned(30 downto 0);
type t_unsigned_32_vector is array (integer range <>) of unsigned(31 downto 0);
type t_unsigned_36_vector is array (integer range <>) of unsigned(35 downto 0);
type t_unsigned_64_vector is array (integer range <>) of unsigned(63 downto 0);
type t_unsigned_128_vector is array (integer range <>) of unsigned(127 downto 0);
type t_unsigned_256_vector is array (integer range <>) of unsigned(255 downto 0);
type t_unsigned_512_vector is array (integer range <>) of unsigned(511 downto 0);
type t_integer_vector is array (integer range <>) of integer;
type t_character_vector is array (integer range <>) of character;
type t_boolean_vector is array (integer range <>) of boolean;
type t_real_vector is array (integer range <>) of real;
-------------------------------------------------------------------------------
-- or-reduce functions on arrays of vectors.
-------------------------------------------------------------------------------
-- Desrcription: or_reduce is intended for busses where each unit drives the
-- with zero's unless it is addressed.
-------------------------------------------------------------------------------
function or_reduce (data_in : std_logic_vector) return std_logic;
function or_reduce (data_in : t_std_logic_2_vector) return std_logic_vector;
function or_reduce (data_in : t_std_logic_3_vector) return std_logic_vector;
function or_reduce (data_in : t_std_logic_4_vector) return std_logic_vector;
function or_reduce (data_in : t_std_logic_8_vector) return std_logic_vector;
function or_reduce (data_in : t_std_logic_16_vector) return std_logic_vector;
function or_reduce (data_in : t_std_logic_32_vector) return std_logic_vector;
function or_reduce (data_in : t_std_logic_64_vector) return std_logic_vector;
function or_reduce (data_in : t_std_logic_128_vector) return std_logic_vector;
function or_reduce (data_in : t_unsigned_6_vector) return unsigned;
-------------------------------------------------------------------------------
-- xor-reduce functions
-------------------------------------------------------------------------------
function xor_reduce(data_in: std_logic_vector) return std_logic;
-------------------------------------------------------------------------------
-- and-reduce functions
-------------------------------------------------------------------------------
function and_reduce(data_in: std_logic_vector) return std_logic;
-------------------------------------------------------------------------------
-- std_logic_vector manipulation functions
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- lowest_bit
---------------------------------------------------------------------------
-- Description: Returns the lowest bit position in a vector that is '1'
---------------------------------------------------------------------------
function lowest_bit(arg : std_logic_vector) return integer;
function lowest_bit(arg : signed) return integer;
function lowest_bit(arg : unsigned) return integer;
---------------------------------------------------------------------------
-- highest_bit
---------------------------------------------------------------------------
-- Description: Returns the highest bit position in a vector that is '1'
---------------------------------------------------------------------------
function highest_bit(arg : std_logic_vector) return integer;
function highest_bit(arg : signed) return integer;
function highest_bit(arg : unsigned) return integer;
---------------------------------------------------------------------------
-- ones
---------------------------------------------------------------------------
-- Description: Returns the number of '1' in a vector
---------------------------------------------------------------------------
function ones(arg : std_logic_vector) return natural;
function ones(arg : signed) return natural;
function ones(arg : unsigned) return natural;
-------------------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- onehot2int
---------------------------------------------------------------------------
-- Description: This function returns the bit position of the one in a
-- one-hot encoded signal
---------------------------------------------------------------------------
function onehot2int(arg : std_logic_vector) return natural;
function onehot2bin(arg : std_logic_vector; size : natural) return std_logic_vector;
---------------------------------------------------------------------------
-- int2onehot
---------------------------------------------------------------------------
-- Description: This function returns a onehot encoded std_logic_vector
-- with the one at the position given as argument
---------------------------------------------------------------------------
function int2onehot(arg : natural; size : natural) return std_logic_vector;
function bin2onehot(arg : std_logic_vector; size : natural) return std_logic_vector;
-------------------------------------------------------------------------------
-- std_logic_vector range functions
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- reverse_order
---------------------------------------------------------------------------
-- Description: Reverses the order of the vector. So 'downto' is converted
-- to 'to' and vica versa.
---------------------------------------------------------------------------
function reverse_order(v : std_logic_vector) return std_logic_vector;
function reverse_bits(v: std_logic_vector) return std_logic_vector;
function reverse_bits(v: unsigned) return unsigned;
---------------------------------------------------------------------------
-- slice
---------------------------------------------------------------------------
-- Description: Return a fraction of the given input vector, depending on
-- requeste slice width and index. Note: in case the requested
-- slice lies (partially) outside the input vector range, the
-- return data is padded with zeroes.
---------------------------------------------------------------------------
function slice(data: std_logic_vector; size, index : integer)
return std_logic_vector;
end tl_vector_pkg;
package body tl_vector_pkg is
-------------------------------------------------------------------------------
-- std_logic_vector manipulation functions
-------------------------------------------------------------------------------
function lowest_bit(arg : std_logic_vector) return integer is
variable v_result : integer range arg'low to arg'high;
begin
v_result := arg'high;
for i in arg'low to arg'high loop
if arg(i) = '1' then
v_result := i;
exit;
end if;
end loop;
return v_result;
end;
function lowest_bit(arg : signed) return integer is
begin
return lowest_bit(std_logic_vector(arg));
end;
function lowest_bit(arg : unsigned) return integer is
begin
return lowest_bit(std_logic_vector(arg));
end;
function highest_bit(arg : std_logic_vector) return integer is
variable v_result : integer range arg'low to arg'high;
begin
v_result := arg'low;
for i in arg'high downto arg'low loop
if arg(i) = '1' then
v_result := i;
exit;
end if;
end loop;
return v_result;
end;
function highest_bit(arg : signed) return integer is
begin
return highest_bit(std_logic_vector(arg));
end;
function highest_bit(arg : unsigned) return integer is
begin
return highest_bit(std_logic_vector(arg));
end;
function ones(arg : std_logic_vector) return natural is
variable v_result : natural range 0 to arg'length;
begin
v_result := 0;
for i in arg'range loop
if arg(i) = '1' then
v_result := v_result + 1;
end if;
end loop;
return v_result;
end function;
function ones(arg : signed) return natural is
begin
return ones(std_logic_vector(arg));
end function;
function ones(arg : unsigned) return natural is
begin
return ones(std_logic_vector(arg));
end function;
-------------------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------------------
function onehot2int(arg : std_logic_vector) return natural is
begin
return lowest_bit(arg);
end function;
function int2onehot(arg : natural; size : natural) return std_logic_vector is
variable v_result : std_logic_vector(size - 1 downto 0);
begin
v_result := (others => '0');
if arg < size then
v_result(arg) := '1';
end if;
return v_result;
end function;
function onehot2bin(arg : std_logic_vector; size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(onehot2int(arg), size));
end function;
function bin2onehot(arg : std_logic_vector; size : natural) return std_logic_vector is
begin
return int2onehot(to_integer(unsigned(arg)), size);
end function;
-------------------------------------------------------------------------------
-- std_logic_vector range functions
-------------------------------------------------------------------------------
function reverse_order(v : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(v'reverse_range);
begin
for i in v'low to v'high loop
result(i) := v(v'high - i + v'low);
end loop;
return result;
end function;
function reverse_bits(v: std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(v'range);
begin
for i in v'low to v'high loop
result(i) := v(v'high - i + v'low);
end loop;
return result;
end function;
function reverse_bits(v: unsigned) return unsigned is
variable result : unsigned(v'range);
begin
for i in v'low to v'high loop
result(i) := v(v'high - i + v'low);
end loop;
return result;
end function;
function slice(data: std_logic_vector; size, index : integer) return std_logic_vector is
variable v_result : std_logic_vector(size - 1 downto 0);
variable v_data_pad : std_logic_vector(((index + 1) * size) - 1 downto 0);
begin
v_data_pad := std_logic_vector(resize(unsigned(data), v_data_pad'length));
v_result := v_data_pad(((index + 1) * size) - 1 downto (index * size));
return v_result;
end function;
-------------------------------------------------------------------------------
-- or_reduce functions
-------------------------------------------------------------------------------
function or_reduce (data_in : std_logic_vector) return std_logic is
variable temp : std_logic := '0';
begin -- or_reduce
for i in data_in'range loop
temp := temp or data_in(i);
end loop; -- i
return temp;
end or_reduce;
function or_reduce (data_in : t_std_logic_2_vector) return std_logic_vector is
variable temp : std_logic_vector(1 downto 0) := (others => '0');
begin -- or_reduce
for i in data_in'range loop
temp := temp or data_in(i);
end loop; -- i
return temp;
end or_reduce;
function or_reduce (data_in : t_std_logic_3_vector) return std_logic_vector is
variable temp : std_logic_vector(2 downto 0) := (others => '0');
begin -- or_reduce
for i in data_in'range loop
temp := temp or data_in(i);
end loop; -- i
return temp;
end or_reduce;
function or_reduce (data_in : t_std_logic_4_vector) return std_logic_vector is
variable temp : std_logic_vector(3 downto 0) := (others => '0');
begin -- or_reduce
for i in data_in'range loop
temp := temp or data_in(i);
end loop; -- i
return temp;
end or_reduce;
function or_reduce (data_in : t_std_logic_8_vector) return std_logic_vector is
variable temp : std_logic_vector(7 downto 0) := (others => '0');
begin -- or_reduce
for i in data_in'range loop
temp := temp or data_in(i);
end loop; -- i
return temp;
end or_reduce;
function or_reduce (data_in : t_std_logic_16_vector) return std_logic_vector is
variable temp : std_logic_vector(15 downto 0) := (others => '0');
begin -- or_reduce
for i in data_in'range loop
temp := temp or data_in(i);
end loop; -- i
return temp;
end or_reduce;
function or_reduce (data_in : t_std_logic_32_vector) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin -- or_reduce
for i in data_in'range loop
temp := temp or data_in(i);
end loop; -- i
return temp;
end or_reduce;
function or_reduce (data_in : t_std_logic_64_vector) return std_logic_vector is
variable temp : std_logic_vector(63 downto 0) := (others => '0');
begin -- or_reduce
for i in data_in'range loop
temp := temp or data_in(i);
end loop; -- i
return temp;
end or_reduce;
function or_reduce (data_in : t_std_logic_128_vector) return std_logic_vector is
variable temp : std_logic_vector(127 downto 0) := (others => '0');
begin -- or_reduce
for i in data_in'range loop
temp := temp or data_in(i);
end loop; -- i
return temp;
end or_reduce;
function or_reduce (data_in : t_unsigned_6_vector) return unsigned is
variable temp : unsigned(5 downto 0) := (others => '0');
begin -- or_reduce
for i in data_in'range loop
temp := temp or data_in(i);
end loop; -- i
return temp;
end or_reduce;
-------------------------------------------------------------------------------
-- xor_reduce functions
-------------------------------------------------------------------------------
function xor_reduce(data_in : std_logic_vector) return std_logic is
variable temp : std_logic := '0';
begin
for i in data_in'range loop
temp := temp xor data_in(i);
end loop;
return temp;
end function;
-------------------------------------------------------------------------------
-- and_reduce functions
-------------------------------------------------------------------------------
function and_reduce(data_in : std_logic_vector) return std_logic is
variable temp : std_logic := '1';
begin
for i in data_in'range loop
temp := temp and data_in(i);
end loop;
return temp;
end function;
end tl_vector_pkg;
| gpl-3.0 | 1fcdcf85bafe9f7f941db9535b46cb77 | 0.521062 | 4.28874 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_sim/usb_test_nano7.vhd | 1 | 9,704 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 7 for USB host
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
use work.tl_string_util_pkg.all;
use work.nano_addresses_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity usb_test_nano7 is
generic (
g_report_file_name : string := "work/usb_test_nano7.rpt"
);
end entity;
architecture arch of usb_test_nano7 is
signal clocks_stopped : boolean := false;
signal interrupt : std_logic;
signal nyet_count : natural := 2;
signal ack_on_ping : boolean := true;
constant Attr_Fifo_Base : unsigned(19 downto 0) := X"00700"; -- 380 * 2
constant Attr_Fifo_Tail_Address : unsigned(19 downto 0) := X"007F0"; -- 3f8 * 2
constant Attr_Fifo_Head_Address : unsigned(19 downto 0) := X"007F2"; -- 3f9 * 2
begin
i_harness: entity work.usb_harness_nano
port map (
ack_on_ping => ack_on_ping,
nyet_count => nyet_count,
interrupt => interrupt,
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable data : std_logic_vector(15 downto 0);
variable res : std_logic_vector(7 downto 0);
variable pipe : integer;
variable attr_fifo_tail : integer := 0;
variable attr_fifo_head : integer := 0;
procedure io_write_word(addr : unsigned(19 downto 0); word : std_logic_vector(15 downto 0)) is
begin
io_write(io => io, addr => (addr + 0), data => word(7 downto 0));
io_write(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure io_read_word(addr : unsigned(19 downto 0); word : out std_logic_vector(15 downto 0)) is
begin
io_read(io => io, addr => (addr + 0), data => word(7 downto 0));
io_read(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure read_attr_fifo(result : out std_logic_vector(15 downto 0); timeout : time) is
variable data : std_logic_vector(15 downto 0);
variable cmd : std_logic_vector(15 downto 0);
variable res : std_logic_vector(15 downto 0);
begin
wait until interrupt = '1' for timeout;
if interrupt = '0' then
sctb_trace("Timeout waiting for interrupt.");
result := X"FFFF";
return;
end if;
io_read_word(addr => (Attr_Fifo_Base + attr_fifo_tail*2), word => data);
attr_fifo_tail := attr_fifo_tail + 1;
if attr_fifo_tail = 16 then
attr_fifo_tail := 0;
end if;
io_write_word(addr => Attr_Fifo_Tail_Address, word => std_logic_vector(to_unsigned(attr_fifo_tail, 16)));
io_read_word(addr => Command, word => cmd);
io_read_word(addr => Command_Result, word => res);
sctb_trace("Fifo read: " & hstr(data) & ", Command: " & hstr(cmd) & ", Result: " & hstr(res));
result := res;
end procedure;
begin
bind_io_bus_bfm("io", io);
bind_mem_model("memory", mem);
sctb_open_simulation("path:path", g_report_file_name);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write_word(c_nano_simulation, X"0001" ); -- set nano to simulation mode
io_write_word(c_nano_busspeed, X"0002" ); -- set bus speed to HS
io_write(io, c_nano_enable, X"01" ); -- enable nano
wait for 4 us;
sctb_open_region("Testing an out packet that NAKs, without SPLIT, using a timeout of 10 frames.", 0);
--io_write_word(Command_SplitCtl, X"8130"); -- Hub Address 1, Port 2, Speed = FS, EP = control
io_write_word(Command_SplitCtl, X"0000"); -- High speed
io_write_word(Command_DevEP, X"0002");
io_write_word(Command_MaxTrans, X"0010");
io_write_word(Command_Length, X"0010");
io_write_word(Command_MemHi, X"0005");
io_write_word(Command_MemLo, X"0000");
io_write_word(Command_Interval, X"0000");
io_write_word(Command_Timeout, X"000A");
io_write_word(c_nano_numpipes, X"0001" ); -- Set active pipes to 1
io_write_word(Command, X"8041"); -- 8000 = read from memory, 40 = Do Data, 01 = OUT
-- There should be NO report until the timeout has occurred.
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"AC00", "Result should be AC00, namely: NAK + Timeout");
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_open_region("Testing an out packet that NAKs, with SPLIT, using a timeout of 10 frames.", 0);
-- Enable split, and try the same thing
io_write_word(Command_SplitCtl, X"8130"); -- Hub Address 1, Port 2, Speed = FS, EP = control
-- re-enable the command, but we do need to clear the start flag too
io_write_word(Command_Started, X"0000");
io_write_word(Command, X"8041"); -- 8000 = read from memory, 40 = Do Data, 01 = OUT
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"AC00", "Result should be AC00, namely: NAK + Timeout");
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_open_region("Testing an in packet that NAKs, without SPLIT, using a timeout of 10 frames.", 0);
io_write_word(Command_SplitCtl, X"0000"); -- High speed
io_write_word(Command_Started, X"0000");
io_write_word(Command, X"4042"); -- 4000 = write to memory, 40 = Do Data, 2 = IN
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"AC00", "Result should be AC00, namely: NAK + Timeout");
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_open_region("Testing an in packet that NAKs, with SPLIT, using a timeout of 10 frames.", 0);
io_write_word(Command_SplitCtl, X"8130"); -- Hub Address 1, Port 2, Speed = FS, EP = control
io_write_word(Command_Started, X"0000");
io_write_word(Command, X"4042"); -- 4000 = write to memory, 40 = Do Data, 2 = IN
read_attr_fifo(data, 2.0 ms);
sctb_check(data, X"AC00", "Result should be AC00, namely: NAK + Timeout");
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_open_region("Testing an out packet that NYETs too often, with SPLIT, using a timeout of 10 frames.", 0);
nyet_count <= 12;
io_write_word(Command_SplitCtl, X"8130"); -- Hub Address 1, Port 2, Speed = FS, EP = control
-- re-enable the command, but we do need to clear the start flag too
io_write_word(Command_Started, X"0000");
io_write_word(Command, X"8041"); -- 8000 = read from memory, 40 = Do Data, 01 = OUT
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"B400", "Result should be B400, namely: NYET");
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_open_region("Testing an out packet that always NAKs on PING in HS mode, using a timeout of 10 frames.", 0);
io_write_word(Command_SplitCtl, X"0000"); -- High speed
io_write_word(Command_Started, X"0000");
ack_on_ping <= false; -- !!
io_write_word(Command, X"8041"); -- 8000 = read from memory, 40 = Do Data, 01 = OUT
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"AC00", "Result should be AC00, namely: NAK + Timeout");
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_open_region("Testing an out packet that always NAKs in HS mode, no timeout, but manual abort.", 0);
io_write_word(Command_SplitCtl, X"0000"); -- High speed
io_write_word(Command_Started, X"0000");
io_write_word(Command_Timeout, X"0000");
ack_on_ping <= true;
io_write_word(Command, X"8041"); -- 8000 = read from memory, 40 = Do Data, 01 = OUT
wait for 0.5 ms;
io_write_word(Command, X"8141"); -- Abort current command
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"6400", "Result should be 6400, namely: Aborted!");
read_attr_fifo(data, 1.5 ms);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_close_simulation;
clocks_stopped <= true;
wait;
end process;
end arch;
-- restart; mem load -infile nano_code.hex -format hex /usb_test_nano7/i_harness/i_host/i_nano/i_buf_ram/mem; run 20 ms | gpl-3.0 | 893051fe18af69944fd037566ac3b5c1 | 0.59089 | 3.499459 | false | true | false | false |
chiggs/nvc | test/regress/issue69.vhd | 5 | 529 | entity issue69 is
end entity;
architecture test of issue69 is
function flip(x : bit_vector) return bit_vector is
variable r : bit_vector(x'reverse_range);
begin
for i in x'reverse_range loop
r(i) := x(i);
end loop;
return r;
end function;
begin
process is
variable v : bit_vector(1 to 4);
begin
v := "1100";
assert flip(v) = "0011";
v := "0101";
assert flip(v) = "1010";
wait;
end process;
end architecture;
| gpl-3.0 | 773bf02c69eec547791b368d19c5be4d | 0.544423 | 3.673611 | false | false | false | false |
ringof/radiofist_audio | ipcore_dir/dcm_6/example_design/dcm_6_exdes.vhd | 1 | 6,677 | -- file: dcm_6_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm_6_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic
);
end dcm_6_exdes;
architecture xilinx of dcm_6_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal clk_n : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component dcm_6 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_ADC : out std_logic;
DEC_CLK : out std_logic;
-- Status and control signals
RESET : in std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= RESET or COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : dcm_6
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_ADC => clk_int(1),
DEC_CLK => clk_int(2),
-- Status and control signals
RESET => RESET);
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clk_n(clk_out_pins) <= not clk(clk_out_pins);
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(clk_out_pins),
C0 => clk(clk_out_pins),
C1 => clk_n(clk_out_pins),
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| mit | 1d0ba14c6911b187a00267dc7a8b050d | 0.620338 | 3.850634 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/standard/cb20/synthesis/cb20.vhd | 1 | 386,068 | -- cb20.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20 is
port (
clk_clk : in std_logic := '0'; -- clk.clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
eim_slave_to_avalon_master_0_conduit_end_ioslv_data : inout std_logic_vector(15 downto 0) := (others => '0'); -- eim_slave_to_avalon_master_0_conduit_end.ioslv_data
eim_slave_to_avalon_master_0_conduit_end_isl_cs_n : in std_logic := '0'; -- .isl_cs_n
eim_slave_to_avalon_master_0_conduit_end_isl_oe_n : in std_logic := '0'; -- .isl_oe_n
eim_slave_to_avalon_master_0_conduit_end_isl_we_n : in std_logic := '0'; -- .isl_we_n
eim_slave_to_avalon_master_0_conduit_end_osl_data_ack : out std_logic; -- .osl_data_ack
eim_slave_to_avalon_master_0_conduit_end_islv_address : in std_logic_vector(15 downto 0) := (others => '0'); -- .islv_address
dacad5668_0_conduit_end_osl_sclk : out std_logic; -- dacad5668_0_conduit_end.osl_sclk
dacad5668_0_conduit_end_oslv_Ss : out std_logic; -- .oslv_Ss
dacad5668_0_conduit_end_osl_mosi : out std_logic; -- .osl_mosi
dacad5668_0_conduit_end_osl_LDAC_n : out std_logic; -- .osl_LDAC_n
dacad5668_0_conduit_end_osl_CLR_n : out std_logic; -- .osl_CLR_n
fqd_interface_0_conduit_end_B : in std_logic_vector(7 downto 0) := (others => '0'); -- fqd_interface_0_conduit_end.B
fqd_interface_0_conduit_end_A : in std_logic_vector(7 downto 0) := (others => '0'); -- .A
gpio_block_0_conduit_end_export : inout std_logic_vector(8 downto 0) := (others => '0'); -- gpio_block_0_conduit_end.export
pwm_interface_0_conduit_end_export : out std_logic_vector(7 downto 0); -- pwm_interface_0_conduit_end.export
gpio_block_1_conduit_end_export : inout std_logic_vector(7 downto 0) := (others => '0') -- gpio_block_1_conduit_end.export
);
end entity cb20;
architecture rtl of cb20 is
component cb20_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component cb20_altpll_0;
component info_device is
generic (
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
description : std_logic_vector(223 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
dev_size : integer := 0
);
port (
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
);
end component info_device;
component eim_slave_to_avalon_master is
generic (
TRANSFER_WIDTH : integer := 16
);
port (
ioslv_data : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
isl_cs_n : in std_logic := 'X'; -- export
isl_oe_n : in std_logic := 'X'; -- export
isl_we_n : in std_logic := 'X'; -- export
osl_data_ack : out std_logic; -- export
islv_address : in std_logic_vector(15 downto 0) := (others => 'X'); -- export
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
islv_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
islv_waitrequest : in std_logic := 'X'; -- waitrequest
oslv_address : out std_logic_vector(15 downto 0); -- address
oslv_read : out std_logic; -- read
oslv_write : out std_logic; -- write
oslv_writedata : out std_logic_vector(15 downto 0) -- writedata
);
end component eim_slave_to_avalon_master;
component avalon_dacad5668_interface is
generic (
BASE_CLK : integer := 33000000;
SCLK_FREQUENCY : integer := 10000000;
INTERNAL_REFERENCE : std_logic := '0';
UNIQUE_ID : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
osl_sclk : out std_logic; -- export
oslv_Ss : out std_logic; -- export
osl_mosi : out std_logic; -- export
osl_LDAC_n : out std_logic; -- export
osl_CLR_n : out std_logic; -- export
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
);
end component avalon_dacad5668_interface;
component avalon_fqd_counter_interface is
generic (
number_of_fqds : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
islv_enc_B : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
islv_enc_A : in std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component avalon_fqd_counter_interface;
component avalon_pwm_interface is
generic (
number_of_pwms : integer := 1;
base_clk : integer := 125000000;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(5 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_pwm : out std_logic_vector(7 downto 0) -- export
);
end component avalon_pwm_interface;
component altera_merlin_master_translator is
generic (
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W : integer := 10;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 1;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 0;
AV_REGISTERINCOMINGSIGNALS : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(16 downto 0); -- address
uav_burstcount : out std_logic_vector(1 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(1 downto 0); -- byteenable
uav_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(15 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
av_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
av_begintransfer : in std_logic := 'X'; -- begintransfer
av_chipselect : in std_logic := 'X'; -- chipselect
av_readdatavalid : out std_logic; -- readdatavalid
av_lock : in std_logic := 'X'; -- lock
av_debugaccess : in std_logic := 'X'; -- debugaccess
uav_clken : out std_logic; -- clken
av_clken : in std_logic := 'X'; -- clken
uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
av_response : out std_logic_vector(1 downto 0); -- response
uav_writeresponserequest : out std_logic; -- writeresponserequest
uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component altera_merlin_master_translator;
component altera_merlin_master_agent is
generic (
PKT_PROTECTION_H : integer := 80;
PKT_PROTECTION_L : integer := 80;
PKT_BEGIN_BURST : integer := 81;
PKT_BURSTWRAP_H : integer := 79;
PKT_BURSTWRAP_L : integer := 77;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 94;
PKT_BURST_TYPE_L : integer := 93;
PKT_BYTE_CNT_H : integer := 76;
PKT_BYTE_CNT_L : integer := 74;
PKT_ADDR_H : integer := 73;
PKT_ADDR_L : integer := 42;
PKT_TRANS_COMPRESSED_READ : integer := 41;
PKT_TRANS_POSTED : integer := 40;
PKT_TRANS_WRITE : integer := 39;
PKT_TRANS_READ : integer := 38;
PKT_TRANS_LOCK : integer := 82;
PKT_TRANS_EXCLUSIVE : integer := 83;
PKT_DATA_H : integer := 37;
PKT_DATA_L : integer := 6;
PKT_BYTEEN_H : integer := 5;
PKT_BYTEEN_L : integer := 2;
PKT_SRC_ID_H : integer := 1;
PKT_SRC_ID_L : integer := 1;
PKT_DEST_ID_H : integer := 0;
PKT_DEST_ID_L : integer := 0;
PKT_THREAD_ID_H : integer := 88;
PKT_THREAD_ID_L : integer := 87;
PKT_CACHE_H : integer := 92;
PKT_CACHE_L : integer := 89;
PKT_DATA_SIDEBAND_H : integer := 105;
PKT_DATA_SIDEBAND_L : integer := 98;
PKT_QOS_H : integer := 109;
PKT_QOS_L : integer := 106;
PKT_ADDR_SIDEBAND_H : integer := 97;
PKT_ADDR_SIDEBAND_L : integer := 93;
PKT_RESPONSE_STATUS_H : integer := 111;
PKT_RESPONSE_STATUS_L : integer := 110;
ST_DATA_W : integer := 112;
ST_CHANNEL_W : integer := 1;
AV_BURSTCOUNT_W : integer := 3;
SUPPRESS_0_BYTEEN_RSP : integer := 1;
ID : integer := 1;
BURSTWRAP_VALUE : integer := 4;
CACHE_VALUE : integer := 0;
SECURE_ACCESS_BIT : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(69 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic; -- ready
av_response : out std_logic_vector(1 downto 0); -- response
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component altera_merlin_master_agent;
component altera_merlin_slave_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(16 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(87 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(88 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(88 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(33 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_agent;
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(88 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(88 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
component cb20_addr_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(69 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component cb20_addr_router;
component cb20_id_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(87 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component cb20_id_router;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_in2 : in std_logic := 'X'; -- reset
reset_in3 : in std_logic := 'X'; -- reset
reset_in4 : in std_logic := 'X'; -- reset
reset_in5 : in std_logic := 'X'; -- reset
reset_in6 : in std_logic := 'X'; -- reset
reset_in7 : in std_logic := 'X'; -- reset
reset_in8 : in std_logic := 'X'; -- reset
reset_in9 : in std_logic := 'X'; -- reset
reset_in10 : in std_logic := 'X'; -- reset
reset_in11 : in std_logic := 'X'; -- reset
reset_in12 : in std_logic := 'X'; -- reset
reset_in13 : in std_logic := 'X'; -- reset
reset_in14 : in std_logic := 'X'; -- reset
reset_in15 : in std_logic := 'X' -- reset
);
end component altera_reset_controller;
component cb20_cmd_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(69 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(69 downto 0); -- data
src1_channel : out std_logic_vector(5 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(69 downto 0); -- data
src2_channel : out std_logic_vector(5 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(69 downto 0); -- data
src3_channel : out std_logic_vector(5 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(69 downto 0); -- data
src4_channel : out std_logic_vector(5 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic; -- endofpacket
src5_ready : in std_logic := 'X'; -- ready
src5_valid : out std_logic; -- valid
src5_data : out std_logic_vector(69 downto 0); -- data
src5_channel : out std_logic_vector(5 downto 0); -- channel
src5_startofpacket : out std_logic; -- startofpacket
src5_endofpacket : out std_logic -- endofpacket
);
end component cb20_cmd_xbar_demux;
component cb20_rsp_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(69 downto 0); -- data
src0_channel : out std_logic_vector(5 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component cb20_rsp_xbar_demux;
component cb20_rsp_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(69 downto 0); -- data
src_channel : out std_logic_vector(5 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X'; -- endofpacket
sink5_ready : out std_logic; -- ready
sink5_valid : in std_logic := 'X'; -- valid
sink5_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
sink5_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink5_startofpacket : in std_logic := 'X'; -- startofpacket
sink5_endofpacket : in std_logic := 'X' -- endofpacket
);
end component cb20_rsp_xbar_mux;
component cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component cb20_info_device_0_avalon_slave_translator;
component cb20_gpio_block_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(3 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component cb20_gpio_block_0_avalon_slave_0_translator;
component cb20_pwm_interface_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(5 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component cb20_pwm_interface_0_avalon_slave_0_translator;
component cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_channel : out std_logic_vector(5 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component cb20_width_adapter;
component cb20_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(69 downto 0); -- data
out_channel : out std_logic_vector(5 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component cb20_width_adapter_001;
component cb20_gpio_block_0 is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => 'X') -- export
);
end component cb20_gpio_block_0;
component cb20_gpio_block_1 is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component cb20_gpio_block_1;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [EIM_Slave_to_Avalon_Master_0:isl_clk, EIM_Slave_to_Avalon_Master_0_avalon_master_translator:clk, EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:clk, addr_router:clk, cmd_xbar_demux:clk, dacad5668_0:isl_clk, dacad5668_0_avalon_slave_translator:clk, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:clk, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, fqd_interface_0:isl_clk, fqd_interface_0_avalon_slave_0_translator:clk, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, gpio_block_0:isl_clk, gpio_block_0_avalon_slave_0_translator:clk, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, gpio_block_1:isl_clk, gpio_block_1_avalon_slave_0_translator:clk, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, info_device_0:isl_clk, info_device_0_avalon_slave_translator:clk, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:clk, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, pwm_interface_0:isl_clk, pwm_interface_0_avalon_slave_0_translator:clk, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_mux:clk, rst_controller_001:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk, width_adapter_006:clk, width_adapter_007:clk, width_adapter_008:clk, width_adapter_009:clk, width_adapter_010:clk, width_adapter_011:clk]
signal eim_slave_to_avalon_master_0_avalon_master_waitrequest : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_waitrequest -> EIM_Slave_to_Avalon_Master_0:islv_waitrequest
signal eim_slave_to_avalon_master_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0:oslv_writedata -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_writedata
signal eim_slave_to_avalon_master_0_avalon_master_address : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0:oslv_address -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_address
signal eim_slave_to_avalon_master_0_avalon_master_write : std_logic; -- EIM_Slave_to_Avalon_Master_0:oslv_write -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_write
signal eim_slave_to_avalon_master_0_avalon_master_read : std_logic; -- EIM_Slave_to_Avalon_Master_0:oslv_read -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_read
signal eim_slave_to_avalon_master_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_readdata -> EIM_Slave_to_Avalon_Master_0:islv_readdata
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- info_device_0:osl_avs_waitrequest -> info_device_0_avalon_slave_translator:av_waitrequest
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- info_device_0_avalon_slave_translator:av_writedata -> info_device_0:islv_avs_write_data
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- info_device_0_avalon_slave_translator:av_address -> info_device_0:islv_avs_address
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_write : std_logic; -- info_device_0_avalon_slave_translator:av_write -> info_device_0:isl_avs_write
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_read : std_logic; -- info_device_0_avalon_slave_translator:av_read -> info_device_0:isl_avs_read
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- info_device_0:oslv_avs_read_data -> info_device_0_avalon_slave_translator:av_readdata
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- info_device_0_avalon_slave_translator:av_byteenable -> info_device_0:islv_avs_byteenable
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- dacad5668_0:osl_avs_waitrequest -> dacad5668_0_avalon_slave_translator:av_waitrequest
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- dacad5668_0_avalon_slave_translator:av_writedata -> dacad5668_0:islv_avs_write_data
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- dacad5668_0_avalon_slave_translator:av_address -> dacad5668_0:islv_avs_address
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_write : std_logic; -- dacad5668_0_avalon_slave_translator:av_write -> dacad5668_0:isl_avs_write
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_read : std_logic; -- dacad5668_0_avalon_slave_translator:av_read -> dacad5668_0:isl_avs_read
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- dacad5668_0:oslv_avs_read_data -> dacad5668_0_avalon_slave_translator:av_readdata
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- dacad5668_0_avalon_slave_translator:av_byteenable -> dacad5668_0:islv_avs_byteenable
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- fqd_interface_0:osl_avs_waitrequest -> fqd_interface_0_avalon_slave_0_translator:av_waitrequest
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- fqd_interface_0_avalon_slave_0_translator:av_writedata -> fqd_interface_0:islv_avs_write_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- fqd_interface_0_avalon_slave_0_translator:av_address -> fqd_interface_0:islv_avs_address
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- fqd_interface_0_avalon_slave_0_translator:av_write -> fqd_interface_0:isl_avs_write
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- fqd_interface_0_avalon_slave_0_translator:av_read -> fqd_interface_0:isl_avs_read
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- fqd_interface_0:oslv_avs_read_data -> fqd_interface_0_avalon_slave_0_translator:av_readdata
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- fqd_interface_0_avalon_slave_0_translator:av_byteenable -> fqd_interface_0:islv_avs_byteenable
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- gpio_block_0:osl_avs_waitrequest -> gpio_block_0_avalon_slave_0_translator:av_waitrequest
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- gpio_block_0_avalon_slave_0_translator:av_writedata -> gpio_block_0:islv_avs_write_data
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(3 downto 0); -- gpio_block_0_avalon_slave_0_translator:av_address -> gpio_block_0:islv_avs_address
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- gpio_block_0_avalon_slave_0_translator:av_write -> gpio_block_0:isl_avs_write
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- gpio_block_0_avalon_slave_0_translator:av_read -> gpio_block_0:isl_avs_read
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- gpio_block_0:oslv_avs_read_data -> gpio_block_0_avalon_slave_0_translator:av_readdata
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_0_avalon_slave_0_translator:av_byteenable -> gpio_block_0:islv_avs_byteenable
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- pwm_interface_0:osl_avs_waitrequest -> pwm_interface_0_avalon_slave_0_translator:av_waitrequest
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- pwm_interface_0_avalon_slave_0_translator:av_writedata -> pwm_interface_0:islv_avs_write_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(5 downto 0); -- pwm_interface_0_avalon_slave_0_translator:av_address -> pwm_interface_0:islv_avs_address
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- pwm_interface_0_avalon_slave_0_translator:av_write -> pwm_interface_0:isl_avs_write
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- pwm_interface_0_avalon_slave_0_translator:av_read -> pwm_interface_0:isl_avs_read
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- pwm_interface_0:oslv_avs_read_data -> pwm_interface_0_avalon_slave_0_translator:av_readdata
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- pwm_interface_0_avalon_slave_0_translator:av_byteenable -> pwm_interface_0:islv_avs_byteenable
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- gpio_block_1:osl_avs_waitrequest -> gpio_block_1_avalon_slave_0_translator:av_waitrequest
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- gpio_block_1_avalon_slave_0_translator:av_writedata -> gpio_block_1:islv_avs_write_data
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(3 downto 0); -- gpio_block_1_avalon_slave_0_translator:av_address -> gpio_block_1:islv_avs_address
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- gpio_block_1_avalon_slave_0_translator:av_write -> gpio_block_1:isl_avs_write
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- gpio_block_1_avalon_slave_0_translator:av_read -> gpio_block_1:isl_avs_read
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- gpio_block_1:oslv_avs_read_data -> gpio_block_1_avalon_slave_0_translator:av_readdata
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_1_avalon_slave_0_translator:av_byteenable -> gpio_block_1:islv_avs_byteenable
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_waitrequest -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_waitrequest
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(1 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_burstcount -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_burstcount
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_writedata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_writedata -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_writedata
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_address : std_logic_vector(16 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_address -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_address
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_lock : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_lock -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_lock
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_write : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_write -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_write
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_read : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_read -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_read
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdata -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_readdata
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_debugaccess -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(1 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_byteenable -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_byteenable
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_readdatavalid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- info_device_0_avalon_slave_translator:uav_waitrequest -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> info_device_0_avalon_slave_translator:uav_burstcount
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> info_device_0_avalon_slave_translator:uav_writedata
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_address -> info_device_0_avalon_slave_translator:uav_address
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_write -> info_device_0_avalon_slave_translator:uav_write
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_lock -> info_device_0_avalon_slave_translator:uav_lock
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_read -> info_device_0_avalon_slave_translator:uav_read
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- info_device_0_avalon_slave_translator:uav_readdata -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- info_device_0_avalon_slave_translator:uav_readdatavalid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> info_device_0_avalon_slave_translator:uav_debugaccess
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> info_device_0_avalon_slave_translator:uav_byteenable
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- dacad5668_0_avalon_slave_translator:uav_waitrequest -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> dacad5668_0_avalon_slave_translator:uav_burstcount
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> dacad5668_0_avalon_slave_translator:uav_writedata
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_address -> dacad5668_0_avalon_slave_translator:uav_address
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_write -> dacad5668_0_avalon_slave_translator:uav_write
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_lock -> dacad5668_0_avalon_slave_translator:uav_lock
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_read -> dacad5668_0_avalon_slave_translator:uav_read
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- dacad5668_0_avalon_slave_translator:uav_readdata -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- dacad5668_0_avalon_slave_translator:uav_readdatavalid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> dacad5668_0_avalon_slave_translator:uav_debugaccess
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> dacad5668_0_avalon_slave_translator:uav_byteenable
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- fqd_interface_0_avalon_slave_0_translator:uav_waitrequest -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> fqd_interface_0_avalon_slave_0_translator:uav_burstcount
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> fqd_interface_0_avalon_slave_0_translator:uav_writedata
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> fqd_interface_0_avalon_slave_0_translator:uav_address
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> fqd_interface_0_avalon_slave_0_translator:uav_write
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> fqd_interface_0_avalon_slave_0_translator:uav_lock
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> fqd_interface_0_avalon_slave_0_translator:uav_read
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- fqd_interface_0_avalon_slave_0_translator:uav_readdata -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- fqd_interface_0_avalon_slave_0_translator:uav_readdatavalid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> fqd_interface_0_avalon_slave_0_translator:uav_debugaccess
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> fqd_interface_0_avalon_slave_0_translator:uav_byteenable
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- gpio_block_0_avalon_slave_0_translator:uav_waitrequest -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> gpio_block_0_avalon_slave_0_translator:uav_burstcount
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> gpio_block_0_avalon_slave_0_translator:uav_writedata
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> gpio_block_0_avalon_slave_0_translator:uav_address
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> gpio_block_0_avalon_slave_0_translator:uav_write
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> gpio_block_0_avalon_slave_0_translator:uav_lock
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> gpio_block_0_avalon_slave_0_translator:uav_read
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- gpio_block_0_avalon_slave_0_translator:uav_readdata -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- gpio_block_0_avalon_slave_0_translator:uav_readdatavalid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> gpio_block_0_avalon_slave_0_translator:uav_debugaccess
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> gpio_block_0_avalon_slave_0_translator:uav_byteenable
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- pwm_interface_0_avalon_slave_0_translator:uav_waitrequest -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> pwm_interface_0_avalon_slave_0_translator:uav_burstcount
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> pwm_interface_0_avalon_slave_0_translator:uav_writedata
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> pwm_interface_0_avalon_slave_0_translator:uav_address
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> pwm_interface_0_avalon_slave_0_translator:uav_write
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> pwm_interface_0_avalon_slave_0_translator:uav_lock
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> pwm_interface_0_avalon_slave_0_translator:uav_read
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- pwm_interface_0_avalon_slave_0_translator:uav_readdata -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- pwm_interface_0_avalon_slave_0_translator:uav_readdatavalid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pwm_interface_0_avalon_slave_0_translator:uav_debugaccess
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> pwm_interface_0_avalon_slave_0_translator:uav_byteenable
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- gpio_block_1_avalon_slave_0_translator:uav_waitrequest -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> gpio_block_1_avalon_slave_0_translator:uav_burstcount
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> gpio_block_1_avalon_slave_0_translator:uav_writedata
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> gpio_block_1_avalon_slave_0_translator:uav_address
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> gpio_block_1_avalon_slave_0_translator:uav_write
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> gpio_block_1_avalon_slave_0_translator:uav_lock
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> gpio_block_1_avalon_slave_0_translator:uav_read
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- gpio_block_1_avalon_slave_0_translator:uav_readdata -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- gpio_block_1_avalon_slave_0_translator:uav_readdatavalid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> gpio_block_1_avalon_slave_0_translator:uav_debugaccess
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> gpio_block_1_avalon_slave_0_translator:uav_byteenable
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(69 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_ready
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> altpll_0:reset
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [EIM_Slave_to_Avalon_Master_0_avalon_master_translator:reset, EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:reset, addr_router:reset, cmd_xbar_demux:reset, dacad5668_0_avalon_slave_translator:reset, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:reset, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, fqd_interface_0_avalon_slave_0_translator:reset, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, gpio_block_0_avalon_slave_0_translator:reset, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, gpio_block_1_avalon_slave_0_translator:reset, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, info_device_0_avalon_slave_translator:reset, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:reset, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, pwm_interface_0_avalon_slave_0_translator:reset, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_mux:reset, rst_controller_001_reset_out_reset:in, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_004:reset, width_adapter_005:reset, width_adapter_006:reset, width_adapter_007:reset, width_adapter_008:reset, width_adapter_009:reset, width_adapter_010:reset, width_adapter_011:reset]
signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> width_adapter:in_endofpacket
signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> width_adapter:in_valid
signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> width_adapter:in_startofpacket
signal cmd_xbar_demux_src0_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src0_data -> width_adapter:in_data
signal cmd_xbar_demux_src0_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux:src0_channel -> width_adapter:in_channel
signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> width_adapter_002:in_endofpacket
signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> width_adapter_002:in_valid
signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> width_adapter_002:in_startofpacket
signal cmd_xbar_demux_src1_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src1_data -> width_adapter_002:in_data
signal cmd_xbar_demux_src1_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux:src1_channel -> width_adapter_002:in_channel
signal cmd_xbar_demux_src2_endofpacket : std_logic; -- cmd_xbar_demux:src2_endofpacket -> width_adapter_004:in_endofpacket
signal cmd_xbar_demux_src2_valid : std_logic; -- cmd_xbar_demux:src2_valid -> width_adapter_004:in_valid
signal cmd_xbar_demux_src2_startofpacket : std_logic; -- cmd_xbar_demux:src2_startofpacket -> width_adapter_004:in_startofpacket
signal cmd_xbar_demux_src2_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src2_data -> width_adapter_004:in_data
signal cmd_xbar_demux_src2_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux:src2_channel -> width_adapter_004:in_channel
signal cmd_xbar_demux_src3_endofpacket : std_logic; -- cmd_xbar_demux:src3_endofpacket -> width_adapter_006:in_endofpacket
signal cmd_xbar_demux_src3_valid : std_logic; -- cmd_xbar_demux:src3_valid -> width_adapter_006:in_valid
signal cmd_xbar_demux_src3_startofpacket : std_logic; -- cmd_xbar_demux:src3_startofpacket -> width_adapter_006:in_startofpacket
signal cmd_xbar_demux_src3_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src3_data -> width_adapter_006:in_data
signal cmd_xbar_demux_src3_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux:src3_channel -> width_adapter_006:in_channel
signal cmd_xbar_demux_src4_endofpacket : std_logic; -- cmd_xbar_demux:src4_endofpacket -> width_adapter_008:in_endofpacket
signal cmd_xbar_demux_src4_valid : std_logic; -- cmd_xbar_demux:src4_valid -> width_adapter_008:in_valid
signal cmd_xbar_demux_src4_startofpacket : std_logic; -- cmd_xbar_demux:src4_startofpacket -> width_adapter_008:in_startofpacket
signal cmd_xbar_demux_src4_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src4_data -> width_adapter_008:in_data
signal cmd_xbar_demux_src4_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux:src4_channel -> width_adapter_008:in_channel
signal cmd_xbar_demux_src5_endofpacket : std_logic; -- cmd_xbar_demux:src5_endofpacket -> width_adapter_010:in_endofpacket
signal cmd_xbar_demux_src5_valid : std_logic; -- cmd_xbar_demux:src5_valid -> width_adapter_010:in_valid
signal cmd_xbar_demux_src5_startofpacket : std_logic; -- cmd_xbar_demux:src5_startofpacket -> width_adapter_010:in_startofpacket
signal cmd_xbar_demux_src5_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src5_data -> width_adapter_010:in_data
signal cmd_xbar_demux_src5_channel : std_logic_vector(5 downto 0); -- cmd_xbar_demux:src5_channel -> width_adapter_010:in_channel
signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
signal rsp_xbar_demux_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
signal rsp_xbar_demux_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
signal rsp_xbar_demux_src0_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
signal rsp_xbar_demux_001_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
signal rsp_xbar_demux_001_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
signal rsp_xbar_demux_001_src0_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
signal rsp_xbar_demux_002_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
signal rsp_xbar_demux_002_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
signal rsp_xbar_demux_002_src0_ready : std_logic; -- rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
signal rsp_xbar_demux_003_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
signal rsp_xbar_demux_003_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
signal rsp_xbar_demux_004_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
signal rsp_xbar_demux_004_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
signal rsp_xbar_demux_004_src0_ready : std_logic; -- rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux:sink5_endofpacket
signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux:sink5_valid
signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux:sink5_startofpacket
signal rsp_xbar_demux_005_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux:sink5_data
signal rsp_xbar_demux_005_src0_channel : std_logic_vector(5 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux:sink5_channel
signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux:sink5_ready -> rsp_xbar_demux_005:src0_ready
signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> cmd_xbar_demux:sink_valid
signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
signal addr_router_src_data : std_logic_vector(69 downto 0); -- addr_router:src_data -> cmd_xbar_demux:sink_data
signal addr_router_src_channel : std_logic_vector(5 downto 0); -- addr_router:src_channel -> cmd_xbar_demux:sink_channel
signal addr_router_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> addr_router:src_ready
signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_src_data : std_logic_vector(69 downto 0); -- rsp_xbar_mux:src_data -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_src_channel : std_logic_vector(5 downto 0); -- rsp_xbar_mux:src_channel -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_src_ready : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
signal cmd_xbar_demux_src0_ready : std_logic; -- width_adapter:in_ready -> cmd_xbar_demux:src0_ready
signal width_adapter_src_endofpacket : std_logic; -- width_adapter:out_endofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_src_valid : std_logic; -- width_adapter:out_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_src_startofpacket : std_logic; -- width_adapter:out_startofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_src_data : std_logic_vector(87 downto 0); -- width_adapter:out_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_src_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter:out_ready
signal width_adapter_src_channel : std_logic_vector(5 downto 0); -- width_adapter:out_channel -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> width_adapter_001:in_endofpacket
signal id_router_src_valid : std_logic; -- id_router:src_valid -> width_adapter_001:in_valid
signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> width_adapter_001:in_startofpacket
signal id_router_src_data : std_logic_vector(87 downto 0); -- id_router:src_data -> width_adapter_001:in_data
signal id_router_src_channel : std_logic_vector(5 downto 0); -- id_router:src_channel -> width_adapter_001:in_channel
signal id_router_src_ready : std_logic; -- width_adapter_001:in_ready -> id_router:src_ready
signal width_adapter_001_src_endofpacket : std_logic; -- width_adapter_001:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
signal width_adapter_001_src_valid : std_logic; -- width_adapter_001:out_valid -> rsp_xbar_demux:sink_valid
signal width_adapter_001_src_startofpacket : std_logic; -- width_adapter_001:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
signal width_adapter_001_src_data : std_logic_vector(69 downto 0); -- width_adapter_001:out_data -> rsp_xbar_demux:sink_data
signal width_adapter_001_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> width_adapter_001:out_ready
signal width_adapter_001_src_channel : std_logic_vector(5 downto 0); -- width_adapter_001:out_channel -> rsp_xbar_demux:sink_channel
signal cmd_xbar_demux_src1_ready : std_logic; -- width_adapter_002:in_ready -> cmd_xbar_demux:src1_ready
signal width_adapter_002_src_endofpacket : std_logic; -- width_adapter_002:out_endofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_002_src_valid : std_logic; -- width_adapter_002:out_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_002_src_startofpacket : std_logic; -- width_adapter_002:out_startofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_002_src_data : std_logic_vector(87 downto 0); -- width_adapter_002:out_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_002_src_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_002:out_ready
signal width_adapter_002_src_channel : std_logic_vector(5 downto 0); -- width_adapter_002:out_channel -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> width_adapter_003:in_endofpacket
signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> width_adapter_003:in_valid
signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> width_adapter_003:in_startofpacket
signal id_router_001_src_data : std_logic_vector(87 downto 0); -- id_router_001:src_data -> width_adapter_003:in_data
signal id_router_001_src_channel : std_logic_vector(5 downto 0); -- id_router_001:src_channel -> width_adapter_003:in_channel
signal id_router_001_src_ready : std_logic; -- width_adapter_003:in_ready -> id_router_001:src_ready
signal width_adapter_003_src_endofpacket : std_logic; -- width_adapter_003:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
signal width_adapter_003_src_valid : std_logic; -- width_adapter_003:out_valid -> rsp_xbar_demux_001:sink_valid
signal width_adapter_003_src_startofpacket : std_logic; -- width_adapter_003:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
signal width_adapter_003_src_data : std_logic_vector(69 downto 0); -- width_adapter_003:out_data -> rsp_xbar_demux_001:sink_data
signal width_adapter_003_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> width_adapter_003:out_ready
signal width_adapter_003_src_channel : std_logic_vector(5 downto 0); -- width_adapter_003:out_channel -> rsp_xbar_demux_001:sink_channel
signal cmd_xbar_demux_src2_ready : std_logic; -- width_adapter_004:in_ready -> cmd_xbar_demux:src2_ready
signal width_adapter_004_src_endofpacket : std_logic; -- width_adapter_004:out_endofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_004_src_valid : std_logic; -- width_adapter_004:out_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_004_src_startofpacket : std_logic; -- width_adapter_004:out_startofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_004_src_data : std_logic_vector(87 downto 0); -- width_adapter_004:out_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_004_src_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_004:out_ready
signal width_adapter_004_src_channel : std_logic_vector(5 downto 0); -- width_adapter_004:out_channel -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> width_adapter_005:in_endofpacket
signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> width_adapter_005:in_valid
signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> width_adapter_005:in_startofpacket
signal id_router_002_src_data : std_logic_vector(87 downto 0); -- id_router_002:src_data -> width_adapter_005:in_data
signal id_router_002_src_channel : std_logic_vector(5 downto 0); -- id_router_002:src_channel -> width_adapter_005:in_channel
signal id_router_002_src_ready : std_logic; -- width_adapter_005:in_ready -> id_router_002:src_ready
signal width_adapter_005_src_endofpacket : std_logic; -- width_adapter_005:out_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
signal width_adapter_005_src_valid : std_logic; -- width_adapter_005:out_valid -> rsp_xbar_demux_002:sink_valid
signal width_adapter_005_src_startofpacket : std_logic; -- width_adapter_005:out_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
signal width_adapter_005_src_data : std_logic_vector(69 downto 0); -- width_adapter_005:out_data -> rsp_xbar_demux_002:sink_data
signal width_adapter_005_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> width_adapter_005:out_ready
signal width_adapter_005_src_channel : std_logic_vector(5 downto 0); -- width_adapter_005:out_channel -> rsp_xbar_demux_002:sink_channel
signal cmd_xbar_demux_src3_ready : std_logic; -- width_adapter_006:in_ready -> cmd_xbar_demux:src3_ready
signal width_adapter_006_src_endofpacket : std_logic; -- width_adapter_006:out_endofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_006_src_valid : std_logic; -- width_adapter_006:out_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_006_src_startofpacket : std_logic; -- width_adapter_006:out_startofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_006_src_data : std_logic_vector(87 downto 0); -- width_adapter_006:out_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_006_src_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_006:out_ready
signal width_adapter_006_src_channel : std_logic_vector(5 downto 0); -- width_adapter_006:out_channel -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> width_adapter_007:in_endofpacket
signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> width_adapter_007:in_valid
signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> width_adapter_007:in_startofpacket
signal id_router_003_src_data : std_logic_vector(87 downto 0); -- id_router_003:src_data -> width_adapter_007:in_data
signal id_router_003_src_channel : std_logic_vector(5 downto 0); -- id_router_003:src_channel -> width_adapter_007:in_channel
signal id_router_003_src_ready : std_logic; -- width_adapter_007:in_ready -> id_router_003:src_ready
signal width_adapter_007_src_endofpacket : std_logic; -- width_adapter_007:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
signal width_adapter_007_src_valid : std_logic; -- width_adapter_007:out_valid -> rsp_xbar_demux_003:sink_valid
signal width_adapter_007_src_startofpacket : std_logic; -- width_adapter_007:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
signal width_adapter_007_src_data : std_logic_vector(69 downto 0); -- width_adapter_007:out_data -> rsp_xbar_demux_003:sink_data
signal width_adapter_007_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> width_adapter_007:out_ready
signal width_adapter_007_src_channel : std_logic_vector(5 downto 0); -- width_adapter_007:out_channel -> rsp_xbar_demux_003:sink_channel
signal cmd_xbar_demux_src4_ready : std_logic; -- width_adapter_008:in_ready -> cmd_xbar_demux:src4_ready
signal width_adapter_008_src_endofpacket : std_logic; -- width_adapter_008:out_endofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_008_src_valid : std_logic; -- width_adapter_008:out_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_008_src_startofpacket : std_logic; -- width_adapter_008:out_startofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_008_src_data : std_logic_vector(87 downto 0); -- width_adapter_008:out_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_008_src_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_008:out_ready
signal width_adapter_008_src_channel : std_logic_vector(5 downto 0); -- width_adapter_008:out_channel -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> width_adapter_009:in_endofpacket
signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> width_adapter_009:in_valid
signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> width_adapter_009:in_startofpacket
signal id_router_004_src_data : std_logic_vector(87 downto 0); -- id_router_004:src_data -> width_adapter_009:in_data
signal id_router_004_src_channel : std_logic_vector(5 downto 0); -- id_router_004:src_channel -> width_adapter_009:in_channel
signal id_router_004_src_ready : std_logic; -- width_adapter_009:in_ready -> id_router_004:src_ready
signal width_adapter_009_src_endofpacket : std_logic; -- width_adapter_009:out_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
signal width_adapter_009_src_valid : std_logic; -- width_adapter_009:out_valid -> rsp_xbar_demux_004:sink_valid
signal width_adapter_009_src_startofpacket : std_logic; -- width_adapter_009:out_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
signal width_adapter_009_src_data : std_logic_vector(69 downto 0); -- width_adapter_009:out_data -> rsp_xbar_demux_004:sink_data
signal width_adapter_009_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> width_adapter_009:out_ready
signal width_adapter_009_src_channel : std_logic_vector(5 downto 0); -- width_adapter_009:out_channel -> rsp_xbar_demux_004:sink_channel
signal cmd_xbar_demux_src5_ready : std_logic; -- width_adapter_010:in_ready -> cmd_xbar_demux:src5_ready
signal width_adapter_010_src_endofpacket : std_logic; -- width_adapter_010:out_endofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_010_src_valid : std_logic; -- width_adapter_010:out_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_010_src_startofpacket : std_logic; -- width_adapter_010:out_startofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_010_src_data : std_logic_vector(87 downto 0); -- width_adapter_010:out_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_010_src_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_010:out_ready
signal width_adapter_010_src_channel : std_logic_vector(5 downto 0); -- width_adapter_010:out_channel -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> width_adapter_011:in_endofpacket
signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> width_adapter_011:in_valid
signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> width_adapter_011:in_startofpacket
signal id_router_005_src_data : std_logic_vector(87 downto 0); -- id_router_005:src_data -> width_adapter_011:in_data
signal id_router_005_src_channel : std_logic_vector(5 downto 0); -- id_router_005:src_channel -> width_adapter_011:in_channel
signal id_router_005_src_ready : std_logic; -- width_adapter_011:in_ready -> id_router_005:src_ready
signal width_adapter_011_src_endofpacket : std_logic; -- width_adapter_011:out_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
signal width_adapter_011_src_valid : std_logic; -- width_adapter_011:out_valid -> rsp_xbar_demux_005:sink_valid
signal width_adapter_011_src_startofpacket : std_logic; -- width_adapter_011:out_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
signal width_adapter_011_src_data : std_logic_vector(69 downto 0); -- width_adapter_011:out_data -> rsp_xbar_demux_005:sink_data
signal width_adapter_011_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> width_adapter_011:out_ready
signal width_adapter_011_src_channel : std_logic_vector(5 downto 0); -- width_adapter_011:out_channel -> rsp_xbar_demux_005:sink_channel
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [EIM_Slave_to_Avalon_Master_0:isl_reset_n, dacad5668_0:isl_reset_n, fqd_interface_0:isl_reset_n, gpio_block_0:isl_reset_n, gpio_block_1:isl_reset_n, info_device_0:isl_reset_n, pwm_interface_0:isl_reset_n]
begin
altpll_0 : component cb20_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset
read => open, -- pll_slave.read
write => open, -- .write
address => open, -- .address
readdata => open, -- .readdata
writedata => open, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
info_device_0 : component info_device
generic map (
unique_id => "00010010011100000000000000000001",
description => "01100011011000100011001000110000001000000111001101110100011000010110111001100100011000010111001001100100001011000010000000110010001110000010111000110101001011100011001000110000001100100011000000000000000000000000000000000000",
dev_size => 768
)
port map (
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
islv_avs_address => info_device_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_slave.address
isl_avs_read => info_device_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => info_device_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => info_device_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
oslv_avs_read_data => info_device_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
osl_avs_waitrequest => info_device_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => info_device_0_avalon_slave_translator_avalon_anti_slave_0_byteenable -- .byteenable
);
eim_slave_to_avalon_master_0 : component eim_slave_to_avalon_master
generic map (
TRANSFER_WIDTH => 16
)
port map (
ioslv_data => eim_slave_to_avalon_master_0_conduit_end_ioslv_data, -- conduit_end.export
isl_cs_n => eim_slave_to_avalon_master_0_conduit_end_isl_cs_n, -- .export
isl_oe_n => eim_slave_to_avalon_master_0_conduit_end_isl_oe_n, -- .export
isl_we_n => eim_slave_to_avalon_master_0_conduit_end_isl_we_n, -- .export
osl_data_ack => eim_slave_to_avalon_master_0_conduit_end_osl_data_ack, -- .export
islv_address => eim_slave_to_avalon_master_0_conduit_end_islv_address, -- .export
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
islv_readdata => eim_slave_to_avalon_master_0_avalon_master_readdata, -- avalon_master.readdata
islv_waitrequest => eim_slave_to_avalon_master_0_avalon_master_waitrequest, -- .waitrequest
oslv_address => eim_slave_to_avalon_master_0_avalon_master_address, -- .address
oslv_read => eim_slave_to_avalon_master_0_avalon_master_read, -- .read
oslv_write => eim_slave_to_avalon_master_0_avalon_master_write, -- .write
oslv_writedata => eim_slave_to_avalon_master_0_avalon_master_writedata -- .writedata
);
dacad5668_0 : component avalon_dacad5668_interface
generic map (
BASE_CLK => 33000000,
SCLK_FREQUENCY => 10000000,
INTERNAL_REFERENCE => '0',
UNIQUE_ID => "00010010011100000010000000000001"
)
port map (
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
osl_sclk => dacad5668_0_conduit_end_osl_sclk, -- conduit_end.export
oslv_Ss => dacad5668_0_conduit_end_oslv_Ss, -- .export
osl_mosi => dacad5668_0_conduit_end_osl_mosi, -- .export
osl_LDAC_n => dacad5668_0_conduit_end_osl_LDAC_n, -- .export
osl_CLR_n => dacad5668_0_conduit_end_osl_CLR_n, -- .export
islv_avs_address => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_slave.address
isl_avs_read => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
oslv_avs_read_data => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
osl_avs_waitrequest => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_byteenable -- .byteenable
);
fqd_interface_0 : component avalon_fqd_counter_interface
generic map (
number_of_fqds => 8,
unique_id => "00010010011100000110000000000001"
)
port map (
oslv_avs_read_data => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
isl_avs_read => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
islv_avs_address => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
osl_avs_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
islv_enc_B => fqd_interface_0_conduit_end_B, -- conduit_end.export
islv_enc_A => fqd_interface_0_conduit_end_A -- .export
);
gpio_block_0 : component cb20_gpio_block_0
generic map (
number_of_gpios => 9,
unique_id => "00010010011100000101000000000001"
)
port map (
oslv_avs_read_data => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
islv_avs_address => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
isl_avs_read => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
osl_avs_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_write_data => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
islv_avs_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
oslv_gpios => gpio_block_0_conduit_end_export -- conduit_end.export
);
pwm_interface_0 : component avalon_pwm_interface
generic map (
number_of_pwms => 8,
base_clk => 200000000,
unique_id => "00010010011100001100000000000001"
)
port map (
oslv_avs_read_data => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
islv_avs_address => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
isl_avs_read => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
osl_avs_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
oslv_pwm => pwm_interface_0_conduit_end_export -- conduit_end.export
);
gpio_block_1 : component cb20_gpio_block_1
generic map (
number_of_gpios => 8,
unique_id => "00010010011100000101000000000010"
)
port map (
oslv_avs_read_data => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
islv_avs_address => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
isl_avs_read => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
osl_avs_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_write_data => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
islv_avs_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
oslv_gpios => gpio_block_1_conduit_end_export -- conduit_end.export
);
eim_slave_to_avalon_master_0_avalon_master_translator : component altera_merlin_master_translator
generic map (
AV_ADDRESS_W => 16,
AV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 2,
USE_READ => 1,
USE_WRITE => 1,
USE_BEGINBURSTTRANSFER => 0,
USE_BEGINTRANSFER => 0,
USE_CHIPSELECT => 0,
USE_BURSTCOUNT => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_LINEWRAPBURSTS => 0,
AV_REGISTERINCOMINGSIGNALS => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_read, -- .read
uav_write => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => eim_slave_to_avalon_master_0_avalon_master_address, -- avalon_anti_master_0.address
av_waitrequest => eim_slave_to_avalon_master_0_avalon_master_waitrequest, -- .waitrequest
av_read => eim_slave_to_avalon_master_0_avalon_master_read, -- .read
av_readdata => eim_slave_to_avalon_master_0_avalon_master_readdata, -- .readdata
av_write => eim_slave_to_avalon_master_0_avalon_master_write, -- .write
av_writedata => eim_slave_to_avalon_master_0_avalon_master_writedata, -- .writedata
av_burstcount => "1", -- (terminated)
av_byteenable => "11", -- (terminated)
av_beginbursttransfer => '0', -- (terminated)
av_begintransfer => '0', -- (terminated)
av_chipselect => '0', -- (terminated)
av_readdatavalid => open, -- (terminated)
av_lock => '0', -- (terminated)
av_debugaccess => '0', -- (terminated)
uav_clken => open, -- (terminated)
av_clken => '1', -- (terminated)
uav_response => "00", -- (terminated)
av_response => open, -- (terminated)
uav_writeresponserequest => open, -- (terminated)
uav_writeresponsevalid => '0', -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
info_device_0_avalon_slave_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => info_device_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => info_device_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => info_device_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => info_device_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => info_device_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => info_device_0_avalon_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => info_device_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
dacad5668_0_avalon_slave_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
fqd_interface_0_avalon_slave_0_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
gpio_block_0_avalon_slave_0_translator : component cb20_gpio_block_0_avalon_slave_0_translator
generic map (
AV_ADDRESS_W => 4,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
pwm_interface_0_avalon_slave_0_translator : component cb20_pwm_interface_0_avalon_slave_0_translator
generic map (
AV_ADDRESS_W => 6,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
gpio_block_1_avalon_slave_0_translator : component cb20_gpio_block_0_avalon_slave_0_translator
generic map (
AV_ADDRESS_W => 4,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent
generic map (
PKT_PROTECTION_H => 63,
PKT_PROTECTION_L => 61,
PKT_BEGIN_BURST => 52,
PKT_BURSTWRAP_H => 44,
PKT_BURSTWRAP_L => 44,
PKT_BURST_SIZE_H => 47,
PKT_BURST_SIZE_L => 45,
PKT_BURST_TYPE_H => 49,
PKT_BURST_TYPE_L => 48,
PKT_BYTE_CNT_H => 43,
PKT_BYTE_CNT_L => 41,
PKT_ADDR_H => 34,
PKT_ADDR_L => 18,
PKT_TRANS_COMPRESSED_READ => 35,
PKT_TRANS_POSTED => 36,
PKT_TRANS_WRITE => 37,
PKT_TRANS_READ => 38,
PKT_TRANS_LOCK => 39,
PKT_TRANS_EXCLUSIVE => 40,
PKT_DATA_H => 15,
PKT_DATA_L => 0,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_SRC_ID_H => 56,
PKT_SRC_ID_L => 54,
PKT_DEST_ID_H => 59,
PKT_DEST_ID_L => 57,
PKT_THREAD_ID_H => 60,
PKT_THREAD_ID_L => 60,
PKT_CACHE_H => 67,
PKT_CACHE_L => 64,
PKT_DATA_SIDEBAND_H => 51,
PKT_DATA_SIDEBAND_L => 51,
PKT_QOS_H => 53,
PKT_QOS_L => 53,
PKT_ADDR_SIDEBAND_H => 50,
PKT_ADDR_SIDEBAND_L => 50,
PKT_RESPONSE_STATUS_H => 69,
PKT_RESPONSE_STATUS_L => 68,
ST_DATA_W => 70,
ST_CHANNEL_W => 6,
AV_BURSTCOUNT_W => 2,
SUPPRESS_0_BYTEEN_RSP => 1,
ID => 0,
BURSTWRAP_VALUE => 1,
CACHE_VALUE => 0,
SECURE_ACCESS_BIT => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
av_address => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_address, -- av.address
av_write => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_write, -- .write
av_read => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_src_data, -- .data
rp_channel => rsp_xbar_mux_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_src_ready, -- .ready
av_response => open, -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 6,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_src_ready, -- cp.ready
cp_valid => width_adapter_src_valid, -- .valid
cp_data => width_adapter_src_data, -- .data
cp_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_src_channel, -- .channel
rf_sink_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 6,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_002_src_ready, -- cp.ready
cp_valid => width_adapter_002_src_valid, -- .valid
cp_data => width_adapter_002_src_data, -- .data
cp_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_002_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_002_src_channel, -- .channel
rf_sink_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 6,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_004_src_ready, -- cp.ready
cp_valid => width_adapter_004_src_valid, -- .valid
cp_data => width_adapter_004_src_data, -- .data
cp_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_004_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_004_src_channel, -- .channel
rf_sink_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 6,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_006_src_ready, -- cp.ready
cp_valid => width_adapter_006_src_valid, -- .valid
cp_data => width_adapter_006_src_data, -- .data
cp_startofpacket => width_adapter_006_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_006_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_006_src_channel, -- .channel
rf_sink_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 6,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_008_src_ready, -- cp.ready
cp_valid => width_adapter_008_src_valid, -- .valid
cp_data => width_adapter_008_src_data, -- .data
cp_startofpacket => width_adapter_008_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_008_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_008_src_channel, -- .channel
rf_sink_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 6,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_010_src_ready, -- cp.ready
cp_valid => width_adapter_010_src_valid, -- .valid
cp_data => width_adapter_010_src_data, -- .data
cp_startofpacket => width_adapter_010_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_010_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_010_src_channel, -- .channel
rf_sink_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
addr_router : component cb20_addr_router
port map (
sink_ready => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_src_ready, -- src.ready
src_valid => addr_router_src_valid, -- .valid
src_data => addr_router_src_data, -- .data
src_channel => addr_router_src_channel, -- .channel
src_startofpacket => addr_router_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_src_endofpacket -- .endofpacket
);
id_router : component cb20_id_router
port map (
sink_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_src_ready, -- src.ready
src_valid => id_router_src_valid, -- .valid
src_data => id_router_src_data, -- .data
src_channel => id_router_src_channel, -- .channel
src_startofpacket => id_router_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_src_endofpacket -- .endofpacket
);
id_router_001 : component cb20_id_router
port map (
sink_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_001_src_ready, -- src.ready
src_valid => id_router_001_src_valid, -- .valid
src_data => id_router_001_src_data, -- .data
src_channel => id_router_001_src_channel, -- .channel
src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_001_src_endofpacket -- .endofpacket
);
id_router_002 : component cb20_id_router
port map (
sink_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_002_src_ready, -- src.ready
src_valid => id_router_002_src_valid, -- .valid
src_data => id_router_002_src_data, -- .data
src_channel => id_router_002_src_channel, -- .channel
src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_002_src_endofpacket -- .endofpacket
);
id_router_003 : component cb20_id_router
port map (
sink_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_003_src_ready, -- src.ready
src_valid => id_router_003_src_valid, -- .valid
src_data => id_router_003_src_data, -- .data
src_channel => id_router_003_src_channel, -- .channel
src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_003_src_endofpacket -- .endofpacket
);
id_router_004 : component cb20_id_router
port map (
sink_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_004_src_ready, -- src.ready
src_valid => id_router_004_src_valid, -- .valid
src_data => id_router_004_src_data, -- .data
src_channel => id_router_004_src_channel, -- .channel
src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_004_src_endofpacket -- .endofpacket
);
id_router_005 : component cb20_id_router
port map (
sink_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_005_src_ready, -- src.ready
src_valid => id_router_005_src_valid, -- .valid
src_data => id_router_005_src_data, -- .data
src_channel => id_router_005_src_channel, -- .channel
src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_005_src_endofpacket -- .endofpacket
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
cmd_xbar_demux : component cb20_cmd_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_src_ready, -- sink.ready
sink_channel => addr_router_src_channel, -- .channel
sink_data => addr_router_src_data, -- .data
sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_src_valid, -- .valid
src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_src0_valid, -- .valid
src0_data => cmd_xbar_demux_src0_data, -- .data
src0_channel => cmd_xbar_demux_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_src1_valid, -- .valid
src1_data => cmd_xbar_demux_src1_data, -- .data
src1_channel => cmd_xbar_demux_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_src2_valid, -- .valid
src2_data => cmd_xbar_demux_src2_data, -- .data
src2_channel => cmd_xbar_demux_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_src3_valid, -- .valid
src3_data => cmd_xbar_demux_src3_data, -- .data
src3_channel => cmd_xbar_demux_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_src4_valid, -- .valid
src4_data => cmd_xbar_demux_src4_data, -- .data
src4_channel => cmd_xbar_demux_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_src4_endofpacket, -- .endofpacket
src5_ready => cmd_xbar_demux_src5_ready, -- src5.ready
src5_valid => cmd_xbar_demux_src5_valid, -- .valid
src5_data => cmd_xbar_demux_src5_data, -- .data
src5_channel => cmd_xbar_demux_src5_channel, -- .channel
src5_startofpacket => cmd_xbar_demux_src5_startofpacket, -- .startofpacket
src5_endofpacket => cmd_xbar_demux_src5_endofpacket -- .endofpacket
);
rsp_xbar_demux : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_001_src_ready, -- sink.ready
sink_channel => width_adapter_001_src_channel, -- .channel
sink_data => width_adapter_001_src_data, -- .data
sink_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_001_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_src0_valid, -- .valid
src0_data => rsp_xbar_demux_src0_data, -- .data
src0_channel => rsp_xbar_demux_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_001 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_003_src_ready, -- sink.ready
sink_channel => width_adapter_003_src_channel, -- .channel
sink_data => width_adapter_003_src_data, -- .data
sink_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_003_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_003_src_valid, -- .valid
src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid
src0_data => rsp_xbar_demux_001_src0_data, -- .data
src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_002 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_005_src_ready, -- sink.ready
sink_channel => width_adapter_005_src_channel, -- .channel
sink_data => width_adapter_005_src_data, -- .data
sink_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_005_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
src0_data => rsp_xbar_demux_002_src0_data, -- .data
src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_003 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_007_src_ready, -- sink.ready
sink_channel => width_adapter_007_src_channel, -- .channel
sink_data => width_adapter_007_src_data, -- .data
sink_startofpacket => width_adapter_007_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_007_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_007_src_valid, -- .valid
src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid
src0_data => rsp_xbar_demux_003_src0_data, -- .data
src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_004 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_009_src_ready, -- sink.ready
sink_channel => width_adapter_009_src_channel, -- .channel
sink_data => width_adapter_009_src_data, -- .data
sink_startofpacket => width_adapter_009_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_009_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_009_src_valid, -- .valid
src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid
src0_data => rsp_xbar_demux_004_src0_data, -- .data
src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_005 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_011_src_ready, -- sink.ready
sink_channel => width_adapter_011_src_channel, -- .channel
sink_data => width_adapter_011_src_data, -- .data
sink_startofpacket => width_adapter_011_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_011_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_011_src_valid, -- .valid
src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid
src0_data => rsp_xbar_demux_005_src0_data, -- .data
src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux : component cb20_rsp_xbar_mux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_src_ready, -- src.ready
src_valid => rsp_xbar_mux_src_valid, -- .valid
src_data => rsp_xbar_mux_src_data, -- .data
src_channel => rsp_xbar_mux_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src0_valid, -- .valid
sink0_channel => rsp_xbar_demux_src0_channel, -- .channel
sink0_data => rsp_xbar_demux_src0_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src0_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src0_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src0_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src0_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src0_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src0_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src0_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src0_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src0_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src0_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
sink4_ready => rsp_xbar_demux_004_src0_ready, -- sink4.ready
sink4_valid => rsp_xbar_demux_004_src0_valid, -- .valid
sink4_channel => rsp_xbar_demux_004_src0_channel, -- .channel
sink4_data => rsp_xbar_demux_004_src0_data, -- .data
sink4_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
sink4_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket
sink5_ready => rsp_xbar_demux_005_src0_ready, -- sink5.ready
sink5_valid => rsp_xbar_demux_005_src0_valid, -- .valid
sink5_channel => rsp_xbar_demux_005_src0_channel, -- .channel
sink5_data => rsp_xbar_demux_005_src0_data, -- .data
sink5_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
sink5_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
width_adapter : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src0_valid, -- sink.valid
in_channel => cmd_xbar_demux_src0_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src0_ready, -- .ready
in_data => cmd_xbar_demux_src0_data, -- .data
out_endofpacket => width_adapter_src_endofpacket, -- src.endofpacket
out_data => width_adapter_src_data, -- .data
out_channel => width_adapter_src_channel, -- .channel
out_valid => width_adapter_src_valid, -- .valid
out_ready => width_adapter_src_ready, -- .ready
out_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_001 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_src_valid, -- sink.valid
in_channel => id_router_src_channel, -- .channel
in_startofpacket => id_router_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_src_endofpacket, -- .endofpacket
in_ready => id_router_src_ready, -- .ready
in_data => id_router_src_data, -- .data
out_endofpacket => width_adapter_001_src_endofpacket, -- src.endofpacket
out_data => width_adapter_001_src_data, -- .data
out_channel => width_adapter_001_src_channel, -- .channel
out_valid => width_adapter_001_src_valid, -- .valid
out_ready => width_adapter_001_src_ready, -- .ready
out_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_002 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src1_valid, -- sink.valid
in_channel => cmd_xbar_demux_src1_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src1_ready, -- .ready
in_data => cmd_xbar_demux_src1_data, -- .data
out_endofpacket => width_adapter_002_src_endofpacket, -- src.endofpacket
out_data => width_adapter_002_src_data, -- .data
out_channel => width_adapter_002_src_channel, -- .channel
out_valid => width_adapter_002_src_valid, -- .valid
out_ready => width_adapter_002_src_ready, -- .ready
out_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_003 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_001_src_valid, -- sink.valid
in_channel => id_router_001_src_channel, -- .channel
in_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_001_src_endofpacket, -- .endofpacket
in_ready => id_router_001_src_ready, -- .ready
in_data => id_router_001_src_data, -- .data
out_endofpacket => width_adapter_003_src_endofpacket, -- src.endofpacket
out_data => width_adapter_003_src_data, -- .data
out_channel => width_adapter_003_src_channel, -- .channel
out_valid => width_adapter_003_src_valid, -- .valid
out_ready => width_adapter_003_src_ready, -- .ready
out_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_004 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src2_valid, -- sink.valid
in_channel => cmd_xbar_demux_src2_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src2_ready, -- .ready
in_data => cmd_xbar_demux_src2_data, -- .data
out_endofpacket => width_adapter_004_src_endofpacket, -- src.endofpacket
out_data => width_adapter_004_src_data, -- .data
out_channel => width_adapter_004_src_channel, -- .channel
out_valid => width_adapter_004_src_valid, -- .valid
out_ready => width_adapter_004_src_ready, -- .ready
out_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_005 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_002_src_valid, -- sink.valid
in_channel => id_router_002_src_channel, -- .channel
in_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_002_src_endofpacket, -- .endofpacket
in_ready => id_router_002_src_ready, -- .ready
in_data => id_router_002_src_data, -- .data
out_endofpacket => width_adapter_005_src_endofpacket, -- src.endofpacket
out_data => width_adapter_005_src_data, -- .data
out_channel => width_adapter_005_src_channel, -- .channel
out_valid => width_adapter_005_src_valid, -- .valid
out_ready => width_adapter_005_src_ready, -- .ready
out_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_006 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src3_valid, -- sink.valid
in_channel => cmd_xbar_demux_src3_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src3_ready, -- .ready
in_data => cmd_xbar_demux_src3_data, -- .data
out_endofpacket => width_adapter_006_src_endofpacket, -- src.endofpacket
out_data => width_adapter_006_src_data, -- .data
out_channel => width_adapter_006_src_channel, -- .channel
out_valid => width_adapter_006_src_valid, -- .valid
out_ready => width_adapter_006_src_ready, -- .ready
out_startofpacket => width_adapter_006_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_007 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_003_src_valid, -- sink.valid
in_channel => id_router_003_src_channel, -- .channel
in_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_003_src_endofpacket, -- .endofpacket
in_ready => id_router_003_src_ready, -- .ready
in_data => id_router_003_src_data, -- .data
out_endofpacket => width_adapter_007_src_endofpacket, -- src.endofpacket
out_data => width_adapter_007_src_data, -- .data
out_channel => width_adapter_007_src_channel, -- .channel
out_valid => width_adapter_007_src_valid, -- .valid
out_ready => width_adapter_007_src_ready, -- .ready
out_startofpacket => width_adapter_007_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_008 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src4_valid, -- sink.valid
in_channel => cmd_xbar_demux_src4_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src4_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src4_ready, -- .ready
in_data => cmd_xbar_demux_src4_data, -- .data
out_endofpacket => width_adapter_008_src_endofpacket, -- src.endofpacket
out_data => width_adapter_008_src_data, -- .data
out_channel => width_adapter_008_src_channel, -- .channel
out_valid => width_adapter_008_src_valid, -- .valid
out_ready => width_adapter_008_src_ready, -- .ready
out_startofpacket => width_adapter_008_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_009 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_004_src_valid, -- sink.valid
in_channel => id_router_004_src_channel, -- .channel
in_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_004_src_endofpacket, -- .endofpacket
in_ready => id_router_004_src_ready, -- .ready
in_data => id_router_004_src_data, -- .data
out_endofpacket => width_adapter_009_src_endofpacket, -- src.endofpacket
out_data => width_adapter_009_src_data, -- .data
out_channel => width_adapter_009_src_channel, -- .channel
out_valid => width_adapter_009_src_valid, -- .valid
out_ready => width_adapter_009_src_ready, -- .ready
out_startofpacket => width_adapter_009_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_010 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src5_valid, -- sink.valid
in_channel => cmd_xbar_demux_src5_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src5_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src5_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src5_ready, -- .ready
in_data => cmd_xbar_demux_src5_data, -- .data
out_endofpacket => width_adapter_010_src_endofpacket, -- src.endofpacket
out_data => width_adapter_010_src_data, -- .data
out_channel => width_adapter_010_src_channel, -- .channel
out_valid => width_adapter_010_src_valid, -- .valid
out_ready => width_adapter_010_src_ready, -- .ready
out_startofpacket => width_adapter_010_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_011 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 6,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_005_src_valid, -- sink.valid
in_channel => id_router_005_src_channel, -- .channel
in_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_005_src_endofpacket, -- .endofpacket
in_ready => id_router_005_src_ready, -- .ready
in_data => id_router_005_src_data, -- .data
out_endofpacket => width_adapter_011_src_endofpacket, -- src.endofpacket
out_data => width_adapter_011_src_data, -- .data
out_channel => width_adapter_011_src_channel, -- .channel
out_valid => width_adapter_011_src_valid, -- .valid
out_ready => width_adapter_011_src_ready, -- .ready
out_startofpacket => width_adapter_011_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
end architecture rtl; -- of cb20
| apache-2.0 | 56f6ddd55718a9c4b83419b84d05bdba | 0.494268 | 3.968545 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_sim/mblite_simu.vhd | 1 | 4,719 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu is
end entity;
architecture test of mblite_simu is
signal clock : std_logic := '0';
signal reset : std_logic;
signal imem_o : imem_out_type;
signal imem_i : imem_in_type;
signal dmem_o : dmem_out_type;
signal dmem_i : dmem_in_type;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 1048575) := (others => (others => '0')); -- 4MB
signal last_char : std_logic_vector(7 downto 0);
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
core0 : core
port map (
imem_o => imem_o,
imem_i => imem_i,
dmem_o => dmem_o,
dmem_i => dmem_i,
int_i => irq_i,
int_o => irq_o,
rst_i => reset,
clk_i => clock );
-- IRQ generation @ 100 kHz (every 10 us)
process
begin
wait for 600 us;
while true loop
wait for 10 us;
wait until clock='1';
irq_i <= '1';
wait until clock='1';
irq_i <= '0';
end loop;
end process;
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
if imem_o.ena_o = '1' then
imem_i.dat_i <= memory(to_integer(unsigned(imem_o.adr_o(21 downto 2))));
-- if (imem_i.dat_i(31 downto 26) = "000101") and (imem_i.dat_i(1 downto 0) = "01") then
-- report "Suspicious CMPS" severity warning;
-- end if;
end if;
if dmem_o.ena_o = '1' then
if dmem_o.adr_o(31 downto 25) = "0000000" then
if dmem_o.we_o = '1' then
for i in 0 to 3 loop
if dmem_o.sel_o(i) = '1' then
memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))))(i*8+7 downto i*8) := dmem_o.dat_o(i*8+7 downto i*8);
end if;
end loop;
else -- read
dmem_i.dat_i <= memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))));
end if;
else -- I/O
if dmem_o.we_o = '1' then -- write
case dmem_o.adr_o(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := dmem_o.dat_o(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
last_char <= byte;
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(dmem_o.adr_o) & " dropped";
end case;
else -- read
case dmem_o.adr_o(19 downto 0) is
when X"0000C" => -- Capabilities
dmem_i.dat_i <= X"00000002";
when X"00012" => -- UART_FLAGS
dmem_i.dat_i <= X"40404040";
when X"2000A" => -- 1541_A memmap
dmem_i.dat_i <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
dmem_i.dat_i <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(dmem_o.adr_o) & " dropped";
dmem_i.dat_i <= X"00000000";
end case;
end if;
end if;
end if;
if reset = '1' then
imem_i.ena_i <= '1';
dmem_i.ena_i <= '1';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | b1b1a0f8eec8e07636bbabb88233c5c0 | 0.427845 | 3.903226 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502/vhdl_source/cpu6502.vhd | 1 | 1,431 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu6502 is
port (
cpu_clk : in std_logic;
cpu_clk_en : in std_logic;
cpu_reset : in std_logic;
cpu_write : out std_logic;
cpu_wdata : out std_logic_vector(7 downto 0);
cpu_rdata : in std_logic_vector(7 downto 0);
cpu_addr : out std_logic_vector(16 downto 0);
cpu_pc : out std_logic_vector(15 downto 0);
IRQn : in std_logic; -- IRQ interrupt (level sensitive)
NMIn : in std_logic; -- NMI interrupt (edge sensitive)
SOn : in std_logic -- set Overflow flag
);
attribute optimize : string;
attribute optimize of cpu6502 : entity is "SPEED";
end cpu6502;
architecture cycle_exact of cpu6502 is
signal read_write_n : std_logic;
begin
core: entity work.proc_core
generic map (
support_bcd => true )
port map(
clock => cpu_clk,
clock_en => cpu_clk_en,
reset => cpu_reset,
irq_n => IRQn,
nmi_n => NMIn,
so_n => SOn,
pc_out => cpu_pc,
addr_out => cpu_addr,
data_in => cpu_rdata,
data_out => cpu_wdata,
read_write_n => read_write_n );
cpu_write <= not read_write_n;
end cycle_exact;
| gpl-3.0 | 962a68c4873571761bd9052180fa7306 | 0.517121 | 3.473301 | false | false | false | false |
nussbrot/AdvPT | log/log.vhd | 2 | 1,754 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity log is
port(
inp : in unsigned;
outp : out unsigned
);
end;
architecture rtl of log is
constant c_val_bits : integer := 5;
type t_lut is array(natural range <>) of unsigned(c_val_bits-1 downto 0);
function map_log2(addr_bits, value_bits : integer) return t_lut is
variable step : real := 1.0/real(2**addr_bits);
variable tmp : real;
variable result : t_lut(0 to 2**addr_bits-1);
begin
for idx in result'range loop
tmp := 1.0 + real(idx)*step;
result(idx) := to_unsigned(integer(tmp), value_bits);
end loop;
return result;
end function;
constant lut : t_lut := map_log2(5, c_val_bits);
function find_msb(inp : unsigned) return integer is
variable result : integer := 0;
begin
for idx in inp'left downto inp'right loop
if inp(idx) = '1' then
result := idx;
exit;
end if;
end loop;
return result;
end;
begin
p_comb : process(inp)
variable msb : integer;
variable lsb : integer;
variable idx : unsigned(c_val_bits-1 downto 0);
begin
if inp = 0 then
outp <= (others => '0');
else
msb := find_msb(inp);
lsb := msb - c_val_bits;
if lsb >= 0 then
idx := inp(msb-1 downto lsb);
else
idx := shift_left(inp, abs(lsb))(c_val_bits-1 downto 0);
end if;
outp <= to_unsigned(2**c_val_bits * msb) +
lut(to_integer(idx));
end if;
end process;
end; | mit | 35aea7675c5e044cbe8cae45c758b5d3 | 0.526226 | 3.708245 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/vhdl_bfm/bram_model_32sp.vhd | 5 | 2,062 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : BRAM model
-------------------------------------------------------------------------------
-- File : bram_model_32sp.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple BRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity bram_model_32sp is
generic (
g_given_name : string;
g_depth : positive := 18 );
port (
CLK : in std_logic;
SSR : in std_logic;
EN : in std_logic;
WE : in std_logic;
ADDR : in std_logic_vector(g_depth-1 downto 0);
DI : in std_logic_vector(31 downto 0);
DO : out std_logic_vector(31 downto 0) );
end bram_model_32sp;
architecture bfm of bram_model_32sp is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(bram_model_32sp'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(CLK)
variable vaddr : std_logic_vector(31 downto 0) := (others => '0');
begin
if rising_edge(CLK) then
vaddr(g_depth+1 downto 2) := ADDR;
if EN='1' then
if bound then
DO <= read_memory_32(this, vaddr);
if WE='1' then
write_memory_32(this, vaddr, DI);
end if;
end if;
end if;
if SSR='1' then
DO <= (others => '0');
end if;
end if;
end process;
end bfm;
| gpl-3.0 | b3df2a89d99641f80092999f0d137c15 | 0.428225 | 4.199593 | false | false | false | false |
xiadz/oscilloscope | src/char_rom_mux.vhd | 1 | 1,948 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 17:46:36 05/28/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity char_rom_mux is
port (
-- Inputs
nrst : in std_logic;
clk108 : in std_logic;
active_pixgen_source : in PIXGEN_SOURCE_T;
char_pos_x : in integer range 0 to 7;
char_pos_y : in integer range 0 to 15;
time_base_char : in short_character;
settings_char : in short_character;
char_pixel : out std_logic
);
end char_rom_mux;
architecture behavioral of char_rom_mux is
signal addra : std_logic_vector (13 downto 0);
signal douta : std_logic;
signal char_int : integer range 0 to 127;
signal char_lv : std_logic_vector (6 downto 0);
signal pos_x_lv : std_logic_vector (2 downto 0);
signal pos_y_lv : std_logic_vector (3 downto 0);
begin
char_rom_memory: entity work.char_rom_memory
port map (
clka => clk108,
addra => addra,
douta(0) => douta
);
char_pixel <= '0' when nrst = '0' else douta;
with active_pixgen_source select
char_int <=
short_character'pos (time_base_char) when TIME_BASE_PIXGEN_T,
short_character'pos (settings_char) when SETTINGS_PIXGEN_T,
0 when others;
char_lv <= std_logic_vector (to_unsigned (char_int, 7));
pos_x_lv <= std_logic_vector (to_unsigned (char_pos_x, 3));
pos_y_lv <= std_logic_vector (to_unsigned (char_pos_y, 4));
addra <= char_lv (6 downto 4) & pos_y_lv & char_lv (3 downto 0) & pos_x_lv;
end behavioral;
| mit | 01368b326c0386691e1646d4d4686cd0 | 0.5077 | 3.738964 | false | false | false | false |
chiggs/nvc | test/regress/proc2.vhd | 5 | 693 | entity proc2 is
end entity;
architecture test of proc2 is
type int_array is array (integer range <>) of integer;
procedure fill(a : out int_array) is
begin
for i in a'range loop
a(i) := a'length;
end loop;
end procedure;
procedure fill2(a : out int_array; v : in integer) is
begin
a := (6, 6, 6);
end procedure;
begin
process is
variable x : int_array(1 to 3);
variable y : int_array(5 to 6);
begin
fill(x);
assert x = (3, 3, 3);
fill(y);
assert y = (2, 2);
fill2(x, 6);
assert x = (6, 6, 6);
wait;
end process;
end architecture;
| gpl-3.0 | f1b02f76b2ddd273cc7de1b5194ed776 | 0.516595 | 3.5 | false | false | false | false |
mkreider/cocotb2 | examples/wb/hdl/cocotb_wb_loopback.vhd | 1 | 2,571 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
entity cocotb_wb_loopback is
port (
clk: in std_logic;
reset_n : in std_logic;
clk2 : in std_logic;
reset_n2 : in std_logic;
wbm_cyc : in std_logic;
wbm_stb : in std_logic;
wbm_we : in std_logic;
wbm_sel : in std_logic_vector(3 downto 0);
wbm_adr : in std_logic_vector(31 downto 0);
wbm_datrd : out std_logic_vector(31 downto 0);
wbm_datwr : in std_logic_vector(31 downto 0);
wbm_stall: out std_logic;
wbm_ack: out std_logic;
wbm_err: out std_logic;
wbmo_cyc : out std_logic;
wbmo_stb : out std_logic;
wbmo_we : out std_logic;
wbmo_sel : out std_logic_vector(3 downto 0);
wbmo_adr : out std_logic_vector(31 downto 0);
wbmo_datrd : in std_logic_vector(31 downto 0);
wbmo_datwr : out std_logic_vector(31 downto 0);
wbmo_err: in std_logic;
wbmo_stall: in std_logic;
wbmo_ack: in std_logic
);
end entity;
architecture rtl of cocotb_wb_loopback is
signal s_master_in : t_wishbone_master_in;
signal s_master_out : t_wishbone_master_out;
signal reg : std_logic_vector(31 downto 0);
begin
s_master_out.we <= wbm_we;
s_master_out.stb <= wbm_stb;
s_master_out.dat <= wbm_datwr;
s_master_out.adr <= wbm_adr;
s_master_out.sel <= x"f";
s_master_out.cyc <= wbm_cyc;
-- s_master_in.dat <= reg;
wbm_datrd <= s_master_in.dat;
wbm_ack <= s_master_in.ack;
wbm_stall <= s_master_in.stall;
wbm_err <= s_master_in.err;
wbmo_we <= s_master_out.we;
wbmo_stb <= s_master_out.stb;
wbmo_datwr <= s_master_out.dat;
wbmo_adr <= s_master_out.adr;
wbmo_sel <= s_master_out.sel;
wbmo_cyc <= s_master_out.cyc;
s_master_in.dat <= wbmo_datrd;
s_master_in.ack <= wbmo_ack;
s_master_in.err <= wbmo_err;
s_master_in.stall <= wbmo_stall;
-- main : process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(reset_n = '0') then
-- s_master_in.stall <= '0';
-- s_master_in.ack <= '0';
-- s_master_in.err <= '0';
-- reg <= (others => '0');
-- else
-- s_master_in.ack <= '0';
-- if((s_master_out.cyc and s_master_out.stb and not s_master_in.stall) = '1') then
-- if(s_master_out.we = '1') then
-- reg <= s_master_out.dat;
-- end if;
-- s_master_in.ack <= '1';
-- end if;
-- end if;
-- end if;
-- end process;
end architecture;
| bsd-3-clause | 42e0a6d76c356ea17db3022653c2350f | 0.571373 | 2.658738 | false | false | false | false |
asicguy/crash | fpga/src/uart/uart.vhd | 2 | 14,356 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: uart.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Universal asynchronous receiver transmitter. Transmits and
-- receives serial data and includes parity checking.
-- TX and RX interfaces are independent.
-- Transmit data tx_data is registered and transmission begins
-- when tx_data_load_stb is strobed. While the component is busy
-- (busy = '1'), further tx_data_load_stb strobes are ignored.
-- Receive data strobe rx_data_vld_stb toggles to indicate
-- serial data was received and rx_data is valid.
-- Parity bit is always transmitted / received. If UART does not
-- use a parity bit, set PARITY to either MARK ('1') or
-- SPACE ('0') and STOP_BITS to 1.
--
-- Note: For 1 stop bit, use PARITY "NONE"
-- For 2 stop bits, use PARITY "MARK"
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
generic (
CLOCK_FREQ : integer := 100e6; -- Input clock frequency (Hz)
BAUD : integer := 115200; -- Baud rate (bits/sec)
DATA_BITS : integer := 8; -- Number of data bits
PARITY : string := "MARK"; -- EVEN, ODD, MARK (always = '1'), SPACE (always = '0'), NONE
NO_STROBE_ON_ERR : string := "TRUE"); -- No rx_data_stb if error in received data.
port (
clk : in std_logic; -- Clock
reset : in std_logic; -- Active high reset
tx_busy : out std_logic; -- Transmitting data
tx_data_stb : in std_logic; -- Transmit buffer load and begin transmission strobe
tx_data : in std_logic_vector(DATA_BITS-1 downto 0);
rx_busy : out std_logic; -- Receiving data
rx_data_stb : out std_logic; -- Receive buffer data valid strobe
rx_data : out std_logic_vector(DATA_BITS-1 downto 0);
rx_error : out std_logic; -- '1' = Invalid parity bit, start bit, or stop bit(s)
tx : out std_logic; -- TX output
rx : in std_logic); -- RX input
end entity;
architecture RTL of uart is
-----------------------------------------------------------------------------
-- Constants Declaration
-----------------------------------------------------------------------------
constant BIT_PERIOD : integer := (CLOCK_FREQ/BAUD);
constant HALF_BIT_PERIOD : integer := (CLOCK_FREQ/BAUD)/2;
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
type rx_state_type is (RX_IDLE_S,RX_START_BIT_S,RX_DATA_S,RX_PARITY_S,RX_STOP_BIT_S,RX_VERIFY_S);
signal rx_state : rx_state_type;
type tx_state_type is (TX_IDLE_S,TX_START_BIT_S,TX_DATA_S,TX_PARITY_S,TX_STOP_BIT_S);
signal tx_state : tx_state_type;
signal rx_meta : std_logic;
signal rx_sync : std_logic;
signal rx_sync_dly1 : std_logic;
-- 1 Start bit + STOP_BITS + 1 parity bit + DATA_BITS
signal rx_start_bit : std_logic;
signal rx_stop_bit : std_logic;
signal rx_parity : std_logic;
signal rx_parity_calc : std_logic_vector(DATA_BITS-1 downto 0);
signal rx_parity_local : std_logic;
signal rx_data_int : std_logic_vector(DATA_BITS-1 downto 0);
signal rx_bit_cnt : integer range 0 to DATA_BITS;
signal rx_bit_period_cnt : integer range 0 to BIT_PERIOD-1;
signal tx_int : std_logic;
signal tx_data_int : std_logic_vector(DATA_BITS-1 downto 0);
signal tx_parity : std_logic;
signal tx_parity_mux : std_logic;
signal tx_parity_calc : std_logic_vector(DATA_BITS-1 downto 0);
signal tx_bit_cnt : integer range 0 to DATA_BITS;
signal tx_bit_period_cnt : integer range 0 to BIT_PERIOD-1;
begin
proc_receiver : process(clk,reset)
begin
if rising_edge(clk) then
if (reset = '1') then
rx_meta <= '0';
rx_sync <= '0';
rx_busy <= '0';
rx_state <= RX_IDLE_S;
rx_data_int <= (others=>'0');
rx_data <= (others=>'0');
rx_data_stb <= '0';
rx_error <= '0';
rx_start_bit <= '0';
rx_stop_bit <= '0';
rx_parity <= '0';
rx_bit_cnt <= 0;
rx_bit_period_cnt <= 0;
else
-- Sychronizer
rx_meta <= rx;
rx_sync <= rx_meta;
rx_sync_dly1 <= rx_sync;
case rx_state is
when RX_IDLE_S =>
-- Initial conditions
rx_bit_period_cnt <= 0;
rx_bit_cnt <= 0;
rx_data_stb <= '0';
rx_busy <= '0';
-- Start bit detected
if (rx_sync_dly1 = '1' AND rx_sync = '0') then
rx_busy <= '1';
rx_state <= RX_START_BIT_S;
end if;
-- Wait for half a bit period to align to the middle of the bit
when RX_START_BIT_S =>
if (rx_bit_period_cnt = HALF_BIT_PERIOD-1) then
rx_start_bit <= rx_sync;
rx_bit_period_cnt <= 0;
rx_state <= RX_DATA_S;
else
rx_bit_period_cnt <= rx_bit_period_cnt + 1;
end if;
-- Wait a full bit period then sample each bit.
when RX_DATA_S =>
if (rx_bit_period_cnt = BIT_PERIOD-1) then
rx_bit_cnt <= rx_bit_cnt + 1;
-- Shift register, UART is LSB first
rx_data_int(DATA_BITS-1) <= rx_sync;
for i in DATA_BITS-1 downto 1 loop
rx_data_int(i-1) <= rx_data_int(i);
end loop;
rx_bit_period_cnt <= 0;
else
rx_bit_period_cnt <= rx_bit_period_cnt + 1;
end if;
-- Need to use DATA_BITS instead of DATA_BITS-1 due to
-- rx_bit_cnt = 0 is not counted.
if (rx_bit_cnt = DATA_BITS) then
rx_bit_cnt <= 0;
if (PARITY(PARITY'left) = 'N') then
rx_state <= RX_STOP_BIT_S;
else
rx_state <= RX_PARITY_S;
end if;
end if;
-- Sample parity bit
when RX_PARITY_S =>
if (rx_bit_period_cnt = BIT_PERIOD-1) then
rx_bit_period_cnt <= 0;
rx_parity <= rx_sync;
rx_state <= RX_STOP_BIT_S;
else
rx_bit_period_cnt <= rx_bit_period_cnt + 1;
end if;
-- Wait for stop bit
-- Note: The statemachine will return to RX_IDLE while still
-- aligned to the middle of the received bits. This
-- alignment is intentional and corrected with the
-- next start bit.
when RX_STOP_BIT_S =>
if (rx_bit_period_cnt = BIT_PERIOD-1) then
rx_bit_period_cnt <= 0;
rx_stop_bit <= rx_sync;
rx_state <= RX_VERIFY_S;
else
rx_bit_period_cnt <= rx_bit_period_cnt + 1;
end if;
when RX_VERIFY_S =>
rx_data <= rx_data_int;
-- Even if an error occurs, output the data strobe
if (NO_STROBE_ON_ERR(NO_STROBE_ON_ERR'left) = 'F') then
rx_data_stb <= '1';
end if;
if (rx_parity = rx_parity_local AND rx_stop_bit = '1' AND rx_start_bit = '0') then
-- Only output the data strobe if no errors have occured
if (NO_STROBE_ON_ERR(NO_STROBE_ON_ERR'left) = 'T') then
rx_data_stb <= '1';
end if;
rx_error <= '0';
else
rx_error <= '1';
end if;
rx_state <= RX_IDLE_S;
when others =>
rx_state <= RX_IDLE_S;
end case;
end if;
end if;
end process;
-- Calculate expected parity bit
rx_parity_local <= '1' when PARITY(PARITY'left) = 'M' else -- Mark
'0' when PARITY(PARITY'left) = 'S' else -- Space
rx_parity_calc(DATA_BITS-1) when PARITY(PARITY'left) = 'E' else -- Even
NOT(rx_parity_calc(DATA_BITS-1)) when PARITY(PARITY'left) = 'O'; -- Odd
rx_parity_calc(0) <= rx_data_int(0);
rx_calc_parity_bit : for i in 1 to DATA_BITS-1 generate
rx_parity_calc(i) <= rx_data_int(i) XOR rx_parity_calc(i-1);
end generate;
proc_transmitter : process(clk,reset)
begin
if rising_edge(clk) then
if (reset = '1') then
tx <= '1';
tx_int <= '1';
tx_state <= TX_IDLE_S;
tx_bit_cnt <= 0;
tx_bit_period_cnt <= 0;
tx_data_int <= (others=>'0');
tx_parity <= '0';
tx_busy <= '0';
else
tx <= tx_int;
case tx_state is
when TX_IDLE_S =>
tx_busy <= '0';
if (tx_data_stb = '1') then
tx_busy <= '1';
tx_data_int <= tx_data;
tx_state <= TX_START_BIT_S;
end if;
when TX_START_BIT_S =>
tx_int <= '0';
if (tx_bit_period_cnt = BIT_PERIOD-1) then
-- Send out first bit
tx_int <= tx_data_int(0);
for i in 1 to DATA_BITS-1 loop
tx_data_int(i-1) <= tx_data_int(i);
end loop;
-- Register TX parity
tx_parity <= tx_parity_mux;
tx_bit_period_cnt <= 0;
tx_state <= TX_DATA_S;
else
tx_bit_period_cnt <= tx_bit_period_cnt + 1;
end if;
when TX_DATA_S =>
if (tx_bit_period_cnt = BIT_PERIOD-1) then
-- Shift register, UART is LSB first
tx_int <= tx_data_int(0);
for i in 1 to DATA_BITS-1 loop
tx_data_int(i-1) <= tx_data_int(i);
end loop;
tx_bit_period_cnt <= 0;
tx_bit_cnt <= tx_bit_cnt + 1;
else
tx_bit_period_cnt <= tx_bit_period_cnt + 1;
end if;
if (tx_bit_cnt = DATA_BITS) then
tx_bit_cnt <= 0;
if (PARITY(PARITY'left) = 'N') then
tx_state <= TX_STOP_BIT_S;
else
tx_state <= TX_PARITY_S;
end if;
end if;
when TX_PARITY_S =>
tx_int <= tx_parity;
if (tx_bit_period_cnt = BIT_PERIOD-1) then
tx_bit_period_cnt <= 0;
tx_state <= TX_STOP_BIT_S;
else
tx_bit_period_cnt <= tx_bit_period_cnt + 1;
end if;
when TX_STOP_BIT_S =>
tx_int <= '1';
if (tx_bit_period_cnt = BIT_PERIOD-1) then
tx_bit_period_cnt <= 0;
tx_state <= TX_IDLE_S;
else
tx_bit_period_cnt <= tx_bit_period_cnt + 1;
end if;
when others =>
tx_state <= TX_IDLE_S;
end case;
end if;
end if;
end process;
-- Generate parity bit
tx_parity_mux <= '1' when PARITY(PARITY'left) = 'M' else -- Mark
'0' when PARITY(PARITY'left) = 'S' else -- Space
tx_parity_calc(DATA_BITS-1) when PARITY(PARITY'left) = 'E' else -- Even
NOT(tx_parity_calc(DATA_BITS-1)) when PARITY(PARITY'left) = 'O'; -- Odd
tx_parity_calc(0) <= tx_data_int(0);
tx_calc_parity_bit : for i in 1 to DATA_BITS-1 generate
tx_parity_calc(i) <= tx_data_int(i) XOR tx_parity_calc(i-1);
end generate;
end architecture; | gpl-3.0 | 6e566abc3a322f6bcb1411a381271ea3 | 0.43083 | 4.065704 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/timer.vhd | 2 | 1,477 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: timer
-- Date:2015-02-19
-- Author: Gideon
-- Description: Generic timeout timer
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer is
generic (
g_reset : std_logic := '0';
g_width : natural := 10 );
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
start_value : in unsigned(g_width-1 downto 0);
timeout : out std_logic );
end entity;
architecture arch of timer is
signal running : std_logic;
signal count : unsigned(g_width-1 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if start = '1' then
count <= start_value;
running <= '1';
timeout <= '0';
elsif running = '1' then
count <= count - 1;
end if;
if count = 1 then
timeout <= '1';
running <= '0';
end if;
if reset='1' then
count <= (others => '0');
running <= '0';
timeout <= g_reset;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 5425f766ad6ab404ab8b11fee854c9b1 | 0.419093 | 4.530675 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/async_fifo/vhdl_source/gray_code_pkg.vhd | 1 | 2,520 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : gray_code_pkg
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: gray code package, only the functions needed for the
-- asynchronous fifo
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package gray_code_pkg is
---------------------------------------------------------------------------
-- type
---------------------------------------------------------------------------
type t_gray is array (natural range <>) of std_logic;
---------------------------------------------------------------------------
-- conversion functions
---------------------------------------------------------------------------
function to_unsigned (arg : t_gray) return unsigned;
function to_gray (arg : unsigned) return t_gray;
end gray_code_pkg;
-------------------------------------------------------------------------------
-- package body
-------------------------------------------------------------------------------
package body gray_code_pkg is
function to_unsigned (arg : t_gray) return unsigned is
alias myarg : t_gray(1 to arg'length) is arg; -- force direction
variable mybin : unsigned(myarg'range);
variable result: unsigned(arg'range);
begin
for i in myarg'range loop
if i = 1 then
mybin(i) := myarg(i);
else
mybin(i) := myarg(i) xor mybin(i-1);
end if;
end loop;
result := mybin;
return result;
end function;
function to_gray (arg : unsigned) return t_gray is
alias myarg : unsigned(1 to arg'length) is arg; -- force direction
variable mygray : t_gray(myarg'range);
variable result : t_gray(arg'range);
begin
for i in myarg'range loop
if i = 1 then
mygray(i) := myarg(i);
else
mygray(i) := myarg(i) xor myarg(i-1);
end if;
end loop;
result := mygray;
return result;
end function;
end;
| gpl-3.0 | e44879cdb4eea7399448028dde69de82 | 0.380952 | 5.283019 | false | false | false | false |
xiadz/oscilloscope | src/time_base_pixgen.vhd | 1 | 2,522 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 20:16:43 05/22/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity time_base_pixgen is
port (
nrst : in std_logic;
clk108 : in std_logic;
segment : in integer range 0 to 15;
segment_change : in std_logic;
subsegment : in integer range 0 to 3;
subsegment_change : in std_logic;
line : in integer range 0 to 15;
line_change : in std_logic;
column : in integer range 0 to 1279;
column_change : in std_logic;
page_change : in std_logic;
active_pixgen_source : in PIXGEN_SOURCE_T;
char : out short_character;
char_pixel : in std_logic;
vout : out std_logic_vector (7 downto 0)
);
end time_base_pixgen;
architecture behavioral of time_base_pixgen is
signal output : std_logic;
begin
char <= to_short_character (NUL);
process (clk108, nrst) is
begin
if nrst = '0' then
output <= '0';
elsif rising_edge (clk108) then
if line = 2 or line = 3 or line = 4 or line = 11 or line = 12 or line = 13 then
if column mod 128 = 127 then
output <= '1';
else
output <= '0';
end if;
elsif line = 5 or line = 10 then
if column mod 64 = 63 then
output <= '1';
else
output <= '0';
end if;
elsif line = 6 or line = 7 or line = 8 or line = 9 then
if column mod 16 = 15 then
output <= '1';
else
output <= '0';
end if;
else
output <= '1';
end if;
end if;
end process;
process (clk108, nrst) is
begin
if nrst = '0' then
vout <= "00000000";
elsif rising_edge (clk108) then
if output = '1' then
vout <= "11111111";
else
vout <= "00000000";
end if;
end if;
end process;
end behavioral;
| mit | 17e2faa27b786f81a4e18835853d00c9 | 0.423077 | 4.552347 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v5.vhd | 2 | 16,327 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (single beat), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5 is
generic (
g_simulation : boolean := false;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_2x : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req_32;
resp : out t_mem_resp_32;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v5;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v5 is
constant c_cmd_inactive : std_logic_vector(3 downto 0) := "1111";
constant c_cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant c_cmd_active : std_logic_vector(3 downto 0) := "0011";
constant c_cmd_read : std_logic_vector(3 downto 0) := "0101";
constant c_cmd_write : std_logic_vector(3 downto 0) := "0100";
constant c_cmd_bterm : std_logic_vector(3 downto 0) := "0110";
constant c_cmd_precharge : std_logic_vector(3 downto 0) := "0010";
constant c_cmd_refresh : std_logic_vector(3 downto 0) := "0001";
constant c_cmd_mode_reg : std_logic_vector(3 downto 0) := "0000";
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(3 downto 0);
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", c_cmd_precharge ),
( X"0032", c_cmd_mode_reg ), -- mode register, burstlen=4, writelen=4, CAS lat = 3
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ) );
signal not_clock_2x : std_logic;
signal not_clock : std_logic;
type t_state is (boot, init, idle, sd_read, sd_read_2, sd_read_3, sd_write, sd_write_2, sd_write_3);
signal sdram_d_o : std_logic_vector(7 downto 0);
signal sdram_t_o : std_logic_vector(7 downto 0);
signal rdata : std_logic_vector(15 downto 0);
signal rdata_lo : std_logic_vector(7 downto 0);
signal rdata_hi : std_logic_vector(7 downto 0);
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_RASn : signal is "true";
attribute iob of SDRAM_CASn : signal is "true";
attribute iob of SDRAM_WEn : signal is "true";
attribute iob of SDRAM_BA : signal is "true";
attribute iob of SDRAM_A : signal is "true";
attribute iob of SDRAM_CKE : signal is "false";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of SDRAM_DQ : signal is "1";
type t_output is record
sdram_cmd : std_logic_vector(3 downto 0);
sdram_cke : std_logic;
sdram_a : std_logic_vector(12 downto 0);
sdram_ba : std_logic_vector(1 downto 0);
tri : std_logic_vector(1 downto 0);
wmask_16 : std_logic_vector(1 downto 0);
wdata_16 : std_logic_vector(15 downto 0);
end record;
type t_internal_state is record
state : t_state;
enable_sdram : std_logic;
col_addr : std_logic_vector(9 downto 0);
bank_addr : std_logic_vector(1 downto 0);
refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
refr_delay : integer range 0 to 3;
delay : integer range 0 to 7;
do_refresh : std_logic;
refresh_inhibit : std_logic;
tag : std_logic_vector(req.tag'range);
rack : std_logic;
rack_tag : std_logic_vector(req.tag'range);
dack : std_logic;
dack_tag : std_logic_vector(req.tag'range);
dack_pre : std_logic;
dack_tag_pre : std_logic_vector(req.tag'range);
boot_cnt : integer range 0 to SDRAM_WakeupTime-1;
init_cnt : integer range 0 to c_init_array'high;
wdata : std_logic_vector(31 downto 0);
wmask : std_logic_vector(3 downto 0);
end record;
constant c_internal_state_init : t_internal_state := (
state => boot,
enable_sdram => '0',
col_addr => (others => '0'),
bank_addr => (others => '0'),
refresh_cnt => SDRAM_Refr_period-1,
refr_delay => 3,
delay => 7,
do_refresh => '0',
refresh_inhibit => '0',
tag => (others => '0'),
rack => '0',
rack_tag => (others => '0'),
dack => '0',
dack_tag => (others => '0'),
dack_pre => '0',
dack_tag_pre => (others => '0'),
boot_cnt => SDRAM_WakeupTime-1,
init_cnt => c_init_array'high,
wdata => (others => '0'),
wmask => (others => '0')
);
signal outp : t_output;
signal cur : t_internal_state := c_internal_state_init;
signal nxt : t_internal_state;
begin
is_idle <= '1' when cur.state = idle else '0';
resp.data <= rdata & rdata_hi & rdata_lo;
resp.rack <= cur.rack;
resp.rack_tag <= cur.rack_tag;
resp.dack_tag <= cur.dack_tag;
process(req, inhibit, cur)
procedure send_refresh_cmd is
begin
outp.sdram_cmd <= c_cmd_refresh;
nxt.do_refresh <= '0';
nxt.refr_delay <= 3;
end procedure;
procedure accept_req is
begin
nxt.rack <= '1';
nxt.rack_tag <= req.tag;
nxt.tag <= req.tag;
nxt.wdata <= req.data;
nxt.wmask <= not req.byte_en;
nxt.col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
nxt.bank_addr <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
outp.sdram_ba <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
outp.sdram_a <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
outp.sdram_cmd <= c_cmd_active;
end procedure;
begin
nxt <= cur; -- default no change
nxt.rack <= '0';
nxt.rack_tag <= (others => '0');
nxt.dack_pre <= '0';
nxt.dack_tag_pre <= (others => '0');
nxt.dack <= cur.dack_pre;
nxt.dack_tag <= cur.dack_tag_pre;
outp.sdram_cmd <= c_cmd_inactive;
outp.sdram_cke <= cur.enable_sdram;
outp.sdram_ba <= (others => 'X');
outp.sdram_a <= (others => 'X');
outp.tri <= "11";
outp.wmask_16 <= "00";
outp.wdata_16 <= (others => 'X');
if cur.refr_delay /= 0 then
nxt.refr_delay <= cur.refr_delay - 1;
end if;
if cur.delay /= 0 then
nxt.delay <= cur.delay - 1;
end if;
if inhibit='1' then
nxt.refresh_inhibit <= '1';
end if;
case cur.state is
when boot =>
nxt.refresh_inhibit <= '0';
nxt.enable_sdram <= '1';
if cur.refresh_cnt = 0 then
nxt.boot_cnt <= cur.boot_cnt - 1;
if cur.boot_cnt = 1 then
nxt.state <= init;
end if;
elsif g_simulation then
nxt.state <= idle;
end if;
when init =>
nxt.do_refresh <= '0';
outp.sdram_a <= c_init_array(cur.init_cnt).addr(12 downto 0);
outp.sdram_ba <= c_init_array(cur.init_cnt).addr(14 downto 13);
outp.sdram_cmd(3) <= '1';
outp.sdram_cmd(2 downto 0) <= c_init_array(cur.init_cnt).cmd(2 downto 0);
if cur.delay = 0 then
nxt.delay <= 7;
if cur.init_cnt = c_init_array'high then
nxt.state <= idle;
else
outp.sdram_cmd(3) <= '0';
nxt.init_cnt <= cur.init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 1, should not be a refresh
-- this enables putting cartridge images in sdram, because we guarantee the first access after inhibit to be a cart cycle
if cur.do_refresh='1' and cur.refresh_inhibit='0' then
send_refresh_cmd;
elsif inhibit='0' then -- make sure we are allowed to start a new cycle
if req.request='1' and cur.refr_delay = 0 then
accept_req;
nxt.refresh_inhibit <= '0';
if req.read_writen = '1' then
nxt.state <= sd_read;
else
nxt.state <= sd_write;
end if;
end if;
end if;
when sd_read =>
outp.sdram_ba <= cur.bank_addr;
outp.sdram_a(12 downto 11) <= "00";
outp.sdram_a(10) <= '1'; -- auto precharge
outp.sdram_a(9 downto 0) <= cur.col_addr;
outp.sdram_cmd <= c_cmd_read;
nxt.state <= sd_read_2;
when sd_read_2 =>
nxt.state <= sd_read_3;
when sd_read_3 =>
nxt.dack_pre <= '1';
nxt.dack_tag_pre <= cur.tag;
nxt.state <= idle;
when sd_write =>
outp.sdram_ba <= cur.bank_addr;
outp.sdram_a(12 downto 11) <= "00";
outp.sdram_a(10) <= '1'; -- auto precharge
outp.sdram_a(9 downto 0) <= cur.col_addr;
outp.sdram_cmd <= c_cmd_write;
outp.wdata_16 <= cur.wdata(31 downto 24) & "XXXXXXXX";
outp.wmask_16 <= cur.wmask(3) & "0";
outp.tri <= "01";
nxt.state <= sd_write_2;
when sd_write_2 =>
outp.tri <= "00";
outp.wdata_16 <= cur.wdata(15 downto 8) & cur.wdata(23 downto 16);
outp.wmask_16 <= cur.wmask(1) & cur.wmask(2);
nxt.state <= sd_write_3;
when sd_write_3 =>
outp.tri <= "10";
outp.wdata_16 <= "XXXXXXXX" & cur.wdata(7 downto 0);
outp.wmask_16 <= "0" & cur.wmask(0);
nxt.state <= idle;
when others =>
null;
end case;
if cur.refresh_cnt = SDRAM_Refr_period-1 then
nxt.do_refresh <= '1';
nxt.refresh_cnt <= 0;
else
nxt.refresh_cnt <= cur.refresh_cnt + 1;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
cur <= nxt;
SDRAM_A <= outp.sdram_a;
SDRAM_BA <= outp.sdram_ba;
SDRAM_RASn <= outp.sdram_cmd(2);
SDRAM_CASn <= outp.sdram_cmd(1);
SDRAM_WEn <= outp.sdram_cmd(0);
SDRAM_CKE <= cur.enable_sdram;
rdata <= rdata_hi & rdata_lo;
if reset='1' then
cur.state <= boot;
cur.delay <= 0;
cur.tag <= (others => '0');
cur.do_refresh <= '0';
cur.boot_cnt <= SDRAM_WakeupTime-1;
cur.init_cnt <= 0;
cur.enable_sdram <= '1';
cur.refresh_inhibit <= '0';
end if;
end if;
end process;
not_clock_2x <= not clk_2x;
not_clock <= not clock;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_2x,
C1 => not_clock_2x,
D0 => '0',
D1 => cur.enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
select_out: FDDRRSE
port map (
CE => '1',
C0 => clock,
C1 => not_clock,
D0 => outp.sdram_cmd(3),
D1 => '1',
Q => SDRAM_CSn,
R => '0',
S => '0' );
r_data: for i in 0 to 7 generate
i_in: IDDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q0 => rdata_hi(i),
Q1 => rdata_lo(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D => SDRAM_DQ(i),
R => reset,
S => '0');
i_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => sdram_d_o(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => outp.wdata_16(8+i),
D1 => outp.wdata_16(i),
R => reset,
S => '0' );
i_out_t: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => sdram_t_o(i),
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => outp.tri(1),
D1 => outp.tri(0),
R => reset,
S => '0' );
SDRAM_DQ(i) <= sdram_d_o(i) when sdram_t_o(i)='0' else 'Z';
end generate;
mask_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => SDRAM_DQM,
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => outp.wmask_16(1),
D1 => outp.wmask_16(0),
R => reset,
S => '0' );
end Gideon;
-- 100 MHz
-- ACT to READ: tRCD = 20 ns ( = 2 CLKs)
-- ACT to PRCH: tRAS = 44 ns ( = 5 CLKs)
-- ACT to ACT: tRC = 66 ns ( = 7 CLKs)
-- ACT to ACTb: tRRD = 15 ns ( = 2 CLKs)
-- PRCH time; tRP = 20 ns ( = 2 CLKs)
-- wr. recov. tWR=8ns+1clk ( = 2 CLKs) (starting from last data word)
-- CL=2
-- 0 1 2 3 4 5 6 7 8 9
-- BL1 A - R - - P + - precharge on odd clock
-- - - - - D d d -
-- +: ONLY if same bank, a new ACT command can be given here. Otherwise we don't meet tRC.
-- BL4 A - r - - - p -
-- - - - - D D D D
-- BL1W A - W - - P + - (precharge on odd clock)
-- - - D - - - - -
-- BL4W A - W - - - p -
-- - - D D D D - -
-- Conclusion: In order to meet tRC, without checking for the bank, we always need 80 ns.
-- In order to optimize to 60 ns (using 20 ns logic ticks), we need to add both bank
-- number checking, as well as differentiate between 1 byte and 4 bytes. I think that
-- it is not worthwhile at this point to implement this, so we will use a very rigid
-- 4-tick schedule: one fits all
| gpl-3.0 | d415d0353881afc4ac57e0a218602ab5 | 0.466283 | 3.512694 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/bit_cpx_cpy.vhd | 1 | 2,143 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bit_cpx_cpy is
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic := '1'; -- instruction(1 downto 0)="00"
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
a_reg : in std_logic_vector(7 downto 0);
x_reg : in std_logic_vector(7 downto 0);
y_reg : in std_logic_vector(7 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic );
end bit_cpx_cpy;
architecture gideon of bit_cpx_cpy is
signal reg : std_logic_vector(7 downto 0) := (others => '0');
signal diff : unsigned(8 downto 0) := (others => '0');
signal zero_cmp : std_logic;
signal zero_ld : std_logic;
signal zero_bit : std_logic;
signal oper4 : std_logic_vector(3 downto 0);
begin
-- *** BIT *** *** STY LDY CPY CPX
reg <= x_reg when operation(0)='1' else y_reg;
diff <= unsigned('1' & reg) - unsigned('0' & data_in);
zero_cmp <= '1' when diff(7 downto 0)=X"00" else '0';
zero_ld <= '1' when data_in=X"00" else '0';
zero_bit <= '1' when (data_in and a_reg)=X"00" else '0';
oper4 <= enable & operation;
with oper4 select c_out <=
diff(8) when "1110" | "1111", -- CPX / CPY
c_in when others;
with oper4 select z_out <=
zero_cmp when "1110" | "1111", -- CPX / CPY
zero_ld when "1101",
zero_bit when "1001",
z_in when others;
with oper4 select n_out <=
diff(7) when "1110" | "1111", -- CPX / CPY
data_in(7) when "1101" | "1001", -- LDY / BIT
n_in when others;
with oper4 select v_out <=
data_in(6) when "1001", -- BIT
v_in when others;
end gideon;
| gpl-3.0 | 904c80d3c6bff48a3b645791cd6a9200 | 0.490434 | 3.208084 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/connector/vhdl_source/connector.vhd | 1 | 1,573 | --------------------------------------------------------------------------------
-- Entity: connector
-- Date:2018-08-05
-- Author: gideon
--
-- Description: This simple module connects two tristate "TTL" buffers
-- This module does not allow external drivers to the net.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity connector is
generic (
g_usedbus : boolean := true;
g_width : natural := 8 );
port (
a_o : in std_logic_vector(g_width-1 downto 0);
a_t : in std_logic_vector(g_width-1 downto 0);
a_i : out std_logic_vector(g_width-1 downto 0);
dbus : in std_logic_vector(g_width-1 downto 0) := (others => '1');
b_o : in std_logic_vector(g_width-1 downto 0);
b_t : in std_logic_vector(g_width-1 downto 0);
b_i : out std_logic_vector(g_width-1 downto 0);
connect : in std_logic );
end entity;
architecture arch of connector is
begin
process(a_o, a_t, b_o, b_t, connect, dbus)
begin
if connect = '0' then
if g_usedbus then
a_i <= dbus;
else
a_i <= a_o or not a_t;
end if;
b_i <= b_o or not b_t;
else -- connected
-- '0' when a_o = '0' and a_t = '1', or b_o = '0' and b_t = '1'
a_i <= not ((not a_o and a_t) or (not b_o and b_t));
b_i <= not ((not a_o and a_t) or (not b_o and b_t));
end if;
end process;
end architecture;
| gpl-3.0 | 1eea80e4a9c80d396ba108506b746b61 | 0.474889 | 3.339703 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_source/crc32.vhd | 1 | 2,826 | -------------------------------------------------------------------------------
-- Title : CRC32 calculator
-------------------------------------------------------------------------------
-- File : crc32.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module calculates a 32-bit CRC over the incoming data-
-- stream (N-bits at a time). Note that the last bit of the
-- polynom needs to be set to '0', due to the way the code
-- is constructed.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity crc32 is
generic (
g_data_width : natural := 8 );
port (
clock : in std_logic;
clock_en : in std_logic;
sync : in std_logic;
data : in std_logic_vector(g_data_width-1 downto 0);
data_valid : in std_logic;
crc : out std_logic_vector(31 downto 0) );
end crc32;
architecture behavioral of crc32 is
signal crc_reg : std_logic_vector(31 downto 0) := (others => '0');
constant polynom : std_logic_vector(31 downto 0) := X"04C11DB6";
-- CRC-32 = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 (used in Ethernet)
-- 3322 2222 2222 1111 1111 1100 0000 0000
-- 1098 7654 3210 9876 5432 1098 7654 3210
-- 0000 0100 1100 0001 0001 1101 1011 0111
begin
process(clock)
function new_crc(i, p: std_logic_vector; data : std_logic) return std_logic_vector is
variable sh : std_logic_vector(i'range);
variable d : std_logic;
begin
d := data xor i(i'high);
sh := i(i'high-1 downto 0) & d; --'0';
if d = '1' then
sh := sh xor p;
end if;
return sh;
end new_crc;
variable tmp : std_logic_vector(crc_reg'range);
begin
if rising_edge(clock) then
if clock_en='1' then
if data_valid='1' then
if sync='1' then
tmp := (others => '1');
else
tmp := crc_reg;
end if;
for i in data'reverse_range loop -- LSB first!
tmp := new_crc(tmp, polynom, data(i));
end loop;
crc_reg <= tmp;
elsif sync='1' then
crc_reg <= (others => '1');
end if;
end if;
end if;
end process;
process(crc_reg)
begin
for i in 0 to 31 loop
crc(i) <= not crc_reg(31-i);
end loop;
end process;
end behavioral;
| gpl-3.0 | 4e0a8c216694e138071efedea6c36260 | 0.443737 | 4.066187 | false | false | false | false |
armandas/Arcade | spaceship.vhd | 2 | 2,398 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spaceship is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
nes_left, nes_right: std_logic;
spaceship_x, spaceship_y: out std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end spaceship;
architecture behaviour of spaceship is
constant SCREEN_W: integer := 640;
constant SCREEN_H: integer := 480;
-- how far down the spaceship will be
constant OFFSET: integer := 416;
-- size of the spaceship frame (32x32)
constant SIZE: integer := 32;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal output_enable: std_logic;
signal spaceship_rgb: std_logic_vector(2 downto 0);
-- x-coordinate of the spaceship
signal position, position_next: std_logic_vector(9 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
position <= conv_std_logic_vector(304, 10);
elsif falling_edge(clk) then
position <= position_next;
end if;
end process;
position_next <= position + 1 when (nes_right = '1' and
position + SIZE < SCREEN_W) else
position - 1 when (nes_left = '1' and
position > 0) else
position;
row_address <= px_y(4 downto 0) - OFFSET;
col_address <= px_x(4 downto 0) - position(4 downto 0);
addr <= row_address & col_address;
output_enable <= '1' when (px_x >= position and
px_x < position + SIZE and
px_y >= OFFSET and
px_y < OFFSET + SIZE) else
'0';
rgb_pixel <= spaceship_rgb when output_enable = '1' else
(others => '0');
-- +13 gives the center coordinate
-- this is used in missile.vhd
spaceship_x <= position + 13;
spaceship_y <= conv_std_logic_vector(OFFSET, 10);
spaceship_rom:
entity work.spaceship_rom(content)
port map(addr => addr, data => spaceship_rgb);
end behaviour;
| bsd-2-clause | d6b96275278568e45b4fa94a3ee4037b | 0.569641 | 3.892857 | false | false | false | false |
ringof/radiofist_audio | sigma_delta_dac.vhd | 1 | 1,326 | -- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See LICENCE.txt for details
--
-- an implementation of a 2nd order sigma-delta DAC
-- see Texas Instruments App Note
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity sigma_delta_dac is
generic (
MSBI : integer := 7
); --Most significant bit of DAC input
port (
din : in STD_LOGIC_VECTOR (MSBI downto 0);
dout : out STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end sigma_delta_dac;
architecture RTL of sigma_delta_dac is
signal delta_adder : STD_LOGIC_VECTOR ((MSBI + 2) downto 0);
signal sigma_adder : STD_LOGIC_VECTOR ((MSBI + 2) downto 0);
signal sigma_latch : STD_LOGIC_VECTOR ((MSBI + 2) downto 0);
signal delta_B : STD_LOGIC_VECTOR ((MSBI + 2) downto 0);
begin
-- process to move data through the sigma-delta loop and output
dac : process (reset, clk)
begin
if rising_edge(clk) then
if reset = '1' then
sigma_latch <= '1' & (others => '0');
dout <= '0';
else
sigma_latch <= sigma_adder;
dout <= sigma_latch(MSBI + 2);
end if;
end if;
end process;
-- Sigma-Delta DAC feedback functions
delta_adder <= din + delta_B;
sigma_adder <= delta_adder + sigma_latch;
delta_B <= sigma_adder(MSBI + 2) & sigma_adder(MSBI + 2) & (others => '0');
end RTL;
| mit | f60cd6aafe35393fb8f309a8f66052a4 | 0.662896 | 2.920705 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/nios_solo_inst.vhd | 1 | 4,856 | component nios_solo is
port (
clk_clk : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
reset_reset_n : in std_logic := 'X'; -- reset_n
dummy_export : in std_logic := 'X' -- export
);
end component nios_solo;
u0 : component nios_solo
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
io_ack => CONNECTED_TO_io_ack, -- io.ack
io_rdata => CONNECTED_TO_io_rdata, -- .rdata
io_read => CONNECTED_TO_io_read, -- .read
io_wdata => CONNECTED_TO_io_wdata, -- .wdata
io_write => CONNECTED_TO_io_write, -- .write
io_address => CONNECTED_TO_io_address, -- .address
io_irq => CONNECTED_TO_io_irq, -- .irq
io_u2p_ack => CONNECTED_TO_io_u2p_ack, -- io_u2p.ack
io_u2p_rdata => CONNECTED_TO_io_u2p_rdata, -- .rdata
io_u2p_read => CONNECTED_TO_io_u2p_read, -- .read
io_u2p_wdata => CONNECTED_TO_io_u2p_wdata, -- .wdata
io_u2p_write => CONNECTED_TO_io_u2p_write, -- .write
io_u2p_address => CONNECTED_TO_io_u2p_address, -- .address
io_u2p_irq => CONNECTED_TO_io_u2p_irq, -- .irq
mem_mem_req_address => CONNECTED_TO_mem_mem_req_address, -- mem.mem_req_address
mem_mem_req_byte_en => CONNECTED_TO_mem_mem_req_byte_en, -- .mem_req_byte_en
mem_mem_req_read_writen => CONNECTED_TO_mem_mem_req_read_writen, -- .mem_req_read_writen
mem_mem_req_request => CONNECTED_TO_mem_mem_req_request, -- .mem_req_request
mem_mem_req_tag => CONNECTED_TO_mem_mem_req_tag, -- .mem_req_tag
mem_mem_req_wdata => CONNECTED_TO_mem_mem_req_wdata, -- .mem_req_wdata
mem_mem_resp_dack_tag => CONNECTED_TO_mem_mem_resp_dack_tag, -- .mem_resp_dack_tag
mem_mem_resp_data => CONNECTED_TO_mem_mem_resp_data, -- .mem_resp_data
mem_mem_resp_rack_tag => CONNECTED_TO_mem_mem_resp_rack_tag, -- .mem_resp_rack_tag
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
dummy_export => CONNECTED_TO_dummy_export -- dummy.export
);
| gpl-3.0 | 80afbe281622da12805ee9811a79b5a2 | 0.434102 | 3.419718 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/standard/cb20/synthesis/cb20_gpio_block_0.vhd | 1 | 3,970 | -- cb20_gpio_block_0.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_0 is
generic (
number_of_gpios : integer := 9;
unique_id : std_logic_vector(31 downto 0) := "00010010011100000101000000000001"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- avalon_slave_0.readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => '0'); -- .address
isl_avs_read : in std_logic := '0'; -- .read
isl_avs_write : in std_logic := '0'; -- .write
osl_avs_waitrequest : out std_logic; -- .waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
isl_clk : in std_logic := '0'; -- clock_sink.clk
isl_reset_n : in std_logic := '0'; -- reset_sink.reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => '0') -- conduit_end.export
);
end entity cb20_gpio_block_0;
architecture rtl of cb20_gpio_block_0 is
component avalon_gpio_interface is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => 'X') -- export
);
end component avalon_gpio_interface;
begin
number_of_gpios_check : if number_of_gpios /= 9 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
unique_id_check : if unique_id /= "00010010011100000101000000000001" generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
gpio_block_0 : component avalon_gpio_interface
generic map (
number_of_gpios => 9,
unique_id => "00010010011100000101000000000001"
)
port map (
oslv_avs_read_data => oslv_avs_read_data, -- avalon_slave_0.readdata
islv_avs_address => islv_avs_address, -- .address
isl_avs_read => isl_avs_read, -- .read
isl_avs_write => isl_avs_write, -- .write
osl_avs_waitrequest => osl_avs_waitrequest, -- .waitrequest
islv_avs_write_data => islv_avs_write_data, -- .writedata
islv_avs_byteenable => islv_avs_byteenable, -- .byteenable
isl_clk => isl_clk, -- clock_sink.clk
isl_reset_n => isl_reset_n, -- reset_sink.reset_n
oslv_gpios => oslv_gpios -- conduit_end.export
);
end architecture rtl; -- of cb20_gpio_block_0
| apache-2.0 | 0e303f8058b8763ccae9c354b9f0d127 | 0.522166 | 3.538324 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20_width_adapter.vhd | 1 | 10,430 | -- cb20_width_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 34;
IN_PKT_ADDR_L : integer := 18;
IN_PKT_DATA_H : integer := 15;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 17;
IN_PKT_BYTEEN_L : integer := 16;
IN_PKT_BYTE_CNT_H : integer := 43;
IN_PKT_BYTE_CNT_L : integer := 41;
IN_PKT_TRANS_COMPRESSED_READ : integer := 35;
IN_PKT_BURSTWRAP_H : integer := 44;
IN_PKT_BURSTWRAP_L : integer := 44;
IN_PKT_BURST_SIZE_H : integer := 47;
IN_PKT_BURST_SIZE_L : integer := 45;
IN_PKT_RESPONSE_STATUS_H : integer := 69;
IN_PKT_RESPONSE_STATUS_L : integer := 68;
IN_PKT_TRANS_EXCLUSIVE : integer := 40;
IN_PKT_BURST_TYPE_H : integer := 49;
IN_PKT_BURST_TYPE_L : integer := 48;
IN_ST_DATA_W : integer := 70;
OUT_PKT_ADDR_H : integer := 52;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 61;
OUT_PKT_BYTE_CNT_L : integer := 59;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 53;
OUT_PKT_BURST_SIZE_H : integer := 65;
OUT_PKT_BURST_SIZE_L : integer := 63;
OUT_PKT_RESPONSE_STATUS_H : integer := 87;
OUT_PKT_RESPONSE_STATUS_L : integer := 86;
OUT_PKT_TRANS_EXCLUSIVE : integer := 58;
OUT_PKT_BURST_TYPE_H : integer := 67;
OUT_PKT_BURST_TYPE_L : integer := 66;
OUT_ST_DATA_W : integer := 88;
ST_CHANNEL_W : integer := 7;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(6 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(69 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(87 downto 0); -- .data
out_channel : out std_logic_vector(6 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter;
architecture rtl of cb20_width_adapter is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_channel : out std_logic_vector(6 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter
| apache-2.0 | d7b87af12a534b3ccfa3b013dce4e236 | 0.458581 | 3.372131 | false | false | false | false |
fpgaddicted/5bit-shift-register-structural- | shifregister_5bit.vhd | 1 | 4,552 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:50:37 04/01/2017
-- Design Name:
-- Module Name: shifregister_5bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shiftregister_5bit is
Port ( sel : in STD_LOGIC_VECTOR (2 downto 0);
A : out STD_LOGIC_VECTOR (4 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
C : out STD_LOGIC;
I : in STD_LOGIC_VECTOR (4 downto 0));
end shiftregister_5bit;
architecture Behavioral of shiftregister_5bit is
COMPONENT dff
PORT(
d : IN std_logic;
clk : IN std_logic;
clear : IN std_logic;
q : OUT std_logic
);
END COMPONENT;
COMPONENT mux8to1
PORT(
Y : OUT STD_LOGIC;
sel : IN STD_LOGIC_VECTOR (2 downto 0);
I : IN STD_LOGIC_VECTOR (7 downto 0)
);
END COMPONENT;
COMPONENT HA
PORT(
AI : in STD_LOGIC;
BI : in STD_LOGIC;
CO : out STD_LOGIC;
SUM : out STD_LOGIC);
END COMPONENT;
----bus
signal data_Q, mux_o : std_logic_vector(4 downto 0);
signal sI0,sI1,sI2,SI3,sI4 : std_logic_vector (7 downto 0);
signal comp1, comp2, carry : std_logic_vector (4 downto 0);
----single signal
signal nclear: std_logic;
begin
--------------------------------- 1st bit
mux0 : mux8to1 PORT MAP (
Y => mux_o(0),
sel => sel,
I => sI0
);
dff0: dff PORT MAP (
d => mux_o(0),
clk => clk,
clear => nclear,
q => data_Q(0)
);
ha_0 : HA PORT MAP (
AI => '1' ,
BI => comp1(0) ,
CO => carry(0) ,
SUM => comp2(0)
);
---------------------------------- 2nd bit
mux1 : mux8to1 PORT MAP (
Y => mux_o(1),
sel => sel,
I => sI1
);
dff1: dff PORT MAP (
d => mux_o(1),
clk => clk,
clear => nclear,
q => data_Q(1)
);
ha_1 : HA PORT MAP (
AI => carry(0),
BI => comp1(1),
CO => carry(1) ,
SUM => comp2(1)
);
----------------------------------- 3rd bit
mux2 : mux8to1 PORT MAP (
Y => mux_o(2),
sel => sel,
I => sI2
);
dff2: dff PORT MAP (
d => mux_o(2),
clk => clk,
clear => nclear,
q => data_Q(2)
);
ha_2 : HA PORT MAP (
AI => carry(1),
BI => comp1(2),
CO => carry(2),
SUM => comp2(2)
);
----------------------------------- 4th bit
mux3 : mux8to1 PORT MAP (
Y => mux_o(3),
sel => sel,
I => sI3
);
dff3: dff PORT MAP (
d => mux_o(3),
clk => clk,
clear => nclear,
q => data_Q(3)
);
ha_3 : HA PORT MAP (
AI => carry(2),
BI => comp1(3),
CO => carry(3),
SUM => comp2(3)
);
----------------------------------- 5th bit
mux4 : mux8to1 PORT MAP (
Y => mux_o(4),
sel => sel,
I => sI4
);
dff4: dff PORT MAP (
d => mux_o(4),
clk => clk,
clear => nclear,
q => data_Q(4)
);
ha_4 : HA PORT MAP (
AI => carry(3),
BI => comp1(4),
CO => carry(4),
SUM => comp2(4)
);
-----------------------------------
---------- SIGNAL MAPPING ---------
sI0 <= (data_Q(0),comp2(0),comp1(0),data_Q(4),data_Q(1),'0',data_Q(1),I(0));
sI1 <= (data_Q(1),comp2(1),comp1(1),data_Q(0),data_Q(2),data_Q(0),data_Q(2),I(1));
sI2 <= (data_Q(2),comp2(2),comp1(2),data_Q(1),data_Q(3),data_Q(1),data_Q(3),I(2));
sI3 <= (data_Q(3),comp2(3),comp1(3),data_Q(2),data_Q(4),data_Q(2),data_Q(4),I(3));
sI4 <= (data_Q(4),comp2(4),comp1(4),data_Q(3),data_Q(0),data_Q(3),'0',I(4));
--- 1's complementary signal mapping----
comp1(0) <= not data_Q(0);
comp1(1) <= not data_Q(1);
comp1(2) <= not data_Q(2);
comp1(3) <= not data_Q(3);
comp1(4) <= not data_Q(4);
----------------------------------------
A <= data_Q;
nclear <= not reset;
C <= carry(4);
end Behavioral;
| gpl-3.0 | 738e663998a576807937ad6ca257be69 | 0.411248 | 3.130674 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/cyclone4_test/vhdl_source/u2p_cia_test.vhd | 1 | 32,571 | -------------------------------------------------------------------------------
-- Title : u2p_cia_test
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel for u2p_cia_test.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity u2p_cia_test is
port (
-- slot side
SLOT_BUFFER_ENn : out std_logic;
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_BA : in std_logic;
SLOT_RSTn : inout std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_DMAn : inout std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : inout std_logic;
SLOT_ROMLn : inout std_logic;
SLOT_IO1n : inout std_logic;
SLOT_IO2n : inout std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_DM : inout std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : in std_logic;
IEC_DATA : in std_logic;
IEC_CLOCK : in std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : in std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Misc
BOARD_REVn : in std_logic_vector(4 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : in std_logic := 'Z';
CAS_READ : in std_logic := 'Z';
CAS_WRITE : in std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_cia_test is
component nios_dut is
port (
audio_in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
audio_in_valid : in std_logic := 'X'; -- valid
audio_in_ready : out std_logic; -- ready
audio_out_data : out std_logic_vector(31 downto 0); -- data
audio_out_valid : out std_logic; -- valid
audio_out_ready : in std_logic := 'X'; -- ready
dummy_export : in std_logic := 'X'; -- export
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
jtag_io_input_vector : in std_logic_vector(47 downto 0) := (others => 'X'); -- input_vector
jtag_io_output_vector : out std_logic_vector(7 downto 0); -- output_vector
jtag_test_clocks_clock_1 : in std_logic := 'X'; -- clock_1
jtag_test_clocks_clock_2 : in std_logic := 'X'; -- clock_2
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
pio1_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
pio2_export : in std_logic_vector(19 downto 0) := (others => 'X'); -- export
pio3_export : out std_logic_vector(7 downto 0); -- export
sys_clock_clk : in std_logic := 'X'; -- clk
sys_reset_reset_n : in std_logic := 'X'; -- reset_n
uart_rxd : in std_logic := 'X'; -- rxd
uart_txd : out std_logic; -- txd
uart_cts_n : in std_logic := 'X'; -- cts_n
uart_rts_n : out std_logic -- rts_n
);
end component nios_dut;
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
signal por_n : std_logic;
signal ref_reset : std_logic;
signal por_count : unsigned(19 downto 0) := (others => '0');
signal sys_count : unsigned(23 downto 0) := (others => '0');
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal eth_reset : std_logic;
signal ulpi_reset_req : std_logic;
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal is_idle : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal cpu_mem_req : t_mem_req_32;
signal cpu_mem_resp : t_mem_resp_32;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_scl_i : std_logic;
signal i2c_scl_o : std_logic;
signal mdio_o : std_logic;
-- io buses
signal io_irq : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_u2p_req : t_io_req;
signal io_u2p_resp : t_io_resp;
signal io_req_new_io : t_io_req;
signal io_resp_new_io : t_io_resp;
signal io_req_cia : t_io_req;
signal io_resp_cia : t_io_resp;
signal io_req_remote : t_io_req;
signal io_resp_remote : t_io_resp;
signal io_req_ddr2 : t_io_req;
signal io_resp_ddr2 : t_io_resp;
-- misc io
signal audio_in_data : std_logic_vector(31 downto 0) := (others => '0'); -- data
signal audio_in_valid : std_logic := '0'; -- valid
signal audio_in_ready : std_logic; -- ready
signal audio_out_data : std_logic_vector(31 downto 0) := (others => '0'); -- data
signal audio_out_valid : std_logic; -- valid
signal audio_out_ready : std_logic := '0'; -- ready
signal audio_speaker : signed(15 downto 0);
signal pll_locked : std_logic;
signal pio1_export : std_logic_vector(31 downto 0) := (others => '0'); -- in_port
signal pio2_export : std_logic_vector(19 downto 0) := (others => '0'); -- in_port
signal pio3_export : std_logic_vector(7 downto 0); -- out_port
signal prim_uart_rxd : std_logic := '1';
signal prim_uart_txd : std_logic := '1';
signal prim_uart_cts_n : std_logic := '1';
signal prim_uart_rts_n : std_logic := '1';
signal io_uart_rxd : std_logic := '1';
signal io_uart_txd : std_logic := '1';
signal slot_test_vector : std_logic_vector(47 downto 0);
signal jtag_write_vector : std_logic_vector(7 downto 0);
signal rising, falling : std_logic;
signal cia_write : std_logic;
signal cia_read : std_logic;
signal cia_addr : std_logic_vector(3 downto 0);
signal cia_cs_n : std_logic;
signal cia_cs2 : std_logic;
signal cia_reset_n : std_logic;
signal cia_rw_n : std_logic;
signal cia_phi2 : std_logic;
signal cia_irq_n : std_logic;
signal db_to_cia : std_logic_vector(7 downto 0);
signal db_from_cia : std_logic_vector(7 downto 0);
signal db_drive : std_logic;
signal pa_to_cia : std_logic_vector(7 downto 0);
signal pa_from_cia : std_logic_vector(7 downto 0);
signal pa_drive : std_logic_vector(7 downto 0);
signal pb_to_cia : std_logic_vector(7 downto 0);
signal pb_from_cia : std_logic_vector(7 downto 0);
signal pb_drive : std_logic_vector(7 downto 0);
signal hs_to_cia : std_logic_vector(4 downto 0);
signal hs_from_cia : std_logic_vector(4 downto 0);
signal hs_drive : std_logic_vector(4 downto 0);
signal pa_from_my_cia : std_logic_vector(7 downto 0);
signal pb_from_my_cia : std_logic_vector(7 downto 0);
signal db_from_my_cia : std_logic_vector(7 downto 0);
signal hs_from_my_cia : std_logic_vector(4 downto 0);
signal irq_from_my_cia : std_logic;
signal cia2_sp_o : std_logic;
signal cia2_sp_i : std_logic;
signal cia2_sp_t : std_logic;
signal cia2_cnt_o : std_logic;
signal cia2_cnt_i : std_logic;
signal cia2_cnt_t : std_logic;
signal cia2_pc_o : std_logic;
signal cia2_port_a_o : std_logic_vector(7 downto 0);
signal cia2_port_a_t : std_logic_vector(7 downto 0);
signal cia2_port_b_o : std_logic_vector(7 downto 0);
signal cia2_port_b_t : std_logic_vector(7 downto 0);
signal spi_c, spi_d : std_logic_vector(0 to 3);
begin
process(RMII_REFCLK)
begin
if rising_edge(RMII_REFCLK) then
if jtag_write_vector(7) = '1' then
por_count <= (others => '0');
por_n <= '0';
elsif por_count = X"FFFFF" then
por_n <= '1';
else
por_count <= por_count + 1;
por_n <= '0';
end if;
end if;
end process;
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_count <= sys_count + 1;
end if;
end process;
ref_reset <= not por_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => pll_locked );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => sys_reset,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => ulpi_reset_req,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
i_nios: nios_dut
port map (
audio_in_data => audio_in_data,
audio_in_valid => audio_in_valid,
audio_in_ready => audio_in_ready,
audio_out_data => audio_out_data,
audio_out_valid => audio_out_valid,
audio_out_ready => audio_out_ready,
dummy_export => '0',
io_ack => io_resp.ack,
io_rdata => io_resp.data,
io_read => io_req.read,
io_wdata => io_req.data,
io_write => io_req.write,
unsigned(io_address) => io_req.address,
io_irq => io_irq,
io_u2p_ack => io_u2p_resp.ack,
io_u2p_rdata => io_u2p_resp.data,
io_u2p_read => io_u2p_req.read,
io_u2p_wdata => io_u2p_req.data,
io_u2p_write => io_u2p_req.write,
unsigned(io_u2p_address) => io_u2p_req.address,
io_u2p_irq => '0',
jtag_io_input_vector => slot_test_vector,
jtag_io_output_vector => jtag_write_vector,
jtag_test_clocks_clock_1 => RMII_REFCLK,
jtag_test_clocks_clock_2 => ULPI_CLOCK,
unsigned(mem_mem_req_address) => cpu_mem_req.address,
mem_mem_req_byte_en => cpu_mem_req.byte_en,
mem_mem_req_read_writen => cpu_mem_req.read_writen,
mem_mem_req_request => cpu_mem_req.request,
mem_mem_req_tag => cpu_mem_req.tag,
mem_mem_req_wdata => cpu_mem_req.data,
mem_mem_resp_dack_tag => cpu_mem_resp.dack_tag,
mem_mem_resp_data => cpu_mem_resp.data,
mem_mem_resp_rack_tag => cpu_mem_resp.rack_tag,
pio1_export => pio1_export,
pio2_export => pio2_export,
pio3_export => pio3_export,
sys_clock_clk => sys_clock,
sys_reset_reset_n => not sys_reset,
uart_rxd => prim_uart_rxd,
uart_txd => prim_uart_txd,
uart_cts_n => prim_uart_cts_n,
uart_rts_n => prim_uart_rts_n
);
UART_TXD <= prim_uart_txd and io_uart_txd;
prim_uart_rxd <= UART_RXD;
io_uart_rxd <= UART_RXD;
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 10,
g_ports => 4
)
port map (
clock => sys_clock,
req => io_u2p_req,
resp => io_u2p_resp,
reqs(0) => io_req_new_io,
reqs(1) => io_req_ddr2,
reqs(2) => io_req_remote,
reqs(3) => io_req_cia,
resps(0) => io_resp_new_io,
resps(1) => io_resp_ddr2,
resps(2) => io_resp_remote,
resps(3) => io_resp_cia
);
i_memphy: entity work.ddr2_ctrl
port map (
ref_clock => RMII_REFCLK,
ref_reset => ref_reset,
sys_clock_o => sys_clock,
sys_reset_o => sys_reset,
clock => sys_clock,
reset => sys_reset,
io_req => io_req_ddr2,
io_resp => io_resp_ddr2,
inhibit => '0', --memctrl_inhibit,
is_idle => is_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_ODT => SDRAM_ODT,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA(1 downto 0),
SDRAM_DM => SDRAM_DM,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS
);
i_remote: entity work.update_io
port map (
clock => sys_clock,
reset => sys_reset,
slow_clock => audio_clock,
slow_reset => audio_reset,
io_req => io_req_remote,
io_resp => io_resp_remote,
flash_selck => FLASH_SELCK,
flash_sel => FLASH_SEL
);
i_u2p_io: entity work.u2p_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_new_io,
io_resp => io_resp_new_io,
mdc => MDIO_CLK,
mdio_i => MDIO_DATA,
mdio_o => mdio_o,
i2c_scl_i => i2c_scl_i,
i2c_scl_o => i2c_scl_o,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
iec_i => "1111",
board_rev => not BOARD_REVn,
iec_o => open,
eth_irq_i => ETH_IRQn,
speaker_en => SPEAKER_ENABLE,
hub_reset_n=> HUB_RESETn,
ulpi_reset => ulpi_reset_req
);
i_cia_test: entity work.u2p_cia_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_cia,
io_resp => io_resp_cia,
addr => cia_addr,
cs_n => cia_cs_n,
cs2 => cia_cs2,
reset_n => cia_reset_n,
rw_n => cia_rw_n,
phi2 => cia_phi2,
irq_n => cia_irq_n,
rising => rising,
falling => falling,
db_to_cia => db_to_cia,
db_from_cia => db_from_cia,
db_drive => db_drive,
pa_to_cia => pa_to_cia,
pa_from_cia => pa_from_cia,
pa_drive => pa_drive,
pb_to_cia => pb_to_cia,
pb_from_cia => pb_from_cia,
pb_drive => pb_drive,
hs_to_cia => hs_to_cia,
hs_from_cia => hs_from_cia,
hs_drive => hs_drive,
pb_from_my_cia => pb_from_my_cia,
db_from_my_cia => db_from_my_cia,
hs_from_my_cia => hs_from_my_cia,
irq_from_my_cia => irq_from_my_cia
);
i2c_scl_i <= I2C_SCL and I2C_SCL_18;
i2c_sda_i <= I2C_SDA and I2C_SDA_18;
I2C_SCL <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA <= '0' when i2c_sda_o = '0' else 'Z';
I2C_SCL_18 <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA_18 <= '0' when i2c_sda_o = '0' else 'Z';
MDIO_DATA <= '0' when mdio_o = '0' else 'Z';
i_logic: entity work.ultimate_logic_32
generic map (
g_version => X"7F",
g_simulation => false,
g_ultimate2plus => true,
g_clock_freq => 62_500_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_microblaze => false,
g_big_endian => false,
g_icap => false,
g_uart => true,
g_drive_1541 => false,
g_drive_1541_2 => false,
g_hardware_gcr => false,
g_ram_expansion => false,
g_extended_reu => false,
g_stereo_sid => false,
g_hardware_iec => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_cartridge => false,
g_command_intf => false,
g_drive_sound => false,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => false,
g_analyzer => false,
g_profiler => true,
g_rmii => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
ext_io_req => io_req,
ext_io_resp => io_resp,
ext_mem_req => cpu_mem_req,
ext_mem_resp=> cpu_mem_resp,
cpu_irq => io_irq,
-- local bus side
mem_req => mem_req,
mem_resp => mem_resp,
-- Debug UART
UART_TXD => io_uart_txd,
UART_RXD => io_uart_rxd,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Ethernet Interface (RMII)
eth_clock => RMII_REFCLK,
eth_reset => eth_reset,
rmii_crs_dv => RMII_CRS_DV,
rmii_rxd => RMII_RX_DATA,
rmii_tx_en => RMII_TX_EN,
rmii_txd => RMII_TX_DATA,
-- Buttons
BUTTON => not BUTTON );
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_divider => 10,
g_left_shift => 0,
g_width => audio_speaker'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => audio_speaker,
dac_out => SPEAKER_DATA );
audio_speaker(15 downto 8) <= signed(audio_out_data(15 downto 8));
audio_speaker( 7 downto 0) <= signed(audio_out_data(23 downto 16));
process(jtag_write_vector, pio3_export, sys_count, pll_locked, por_n)
begin
case jtag_write_vector(6 downto 5) is
when "00" =>
LED_MOTORn <= sys_count(sys_count'high);
LED_DISKn <= pll_locked; -- if pll_locked = 0, led is on
LED_CARTn <= por_n; -- if por_n is 0, led is on
LED_SDACTn <= '0';
when "01" =>
LED_MOTORn <= not jtag_write_vector(0);
LED_DISKn <= not jtag_write_vector(1);
LED_CARTn <= not jtag_write_vector(2);
LED_SDACTn <= not jtag_write_vector(3);
when "10" =>
LED_MOTORn <= not pio3_export(0);
LED_DISKn <= not pio3_export(1);
LED_CARTn <= not pio3_export(2);
LED_SDACTn <= not pio3_export(3);
when others =>
LED_MOTORn <= '1';
LED_DISKn <= '1';
LED_CARTn <= '1';
LED_SDACTn <= '1';
end case;
end process;
ULPI_RESET <= por_n;
AUDIO_MCLK <= audio_clock;
SLOT_BUFFER_ENn <= '0'; -- once configured, we can connect
pio1_export(31 downto 0) <= slot_test_vector(31 downto 0);
pio2_export(15 downto 0) <= slot_test_vector(47 downto 32);
pio2_export(18 downto 16) <= not BUTTON;
pio2_export(19) <= '1' when spi_d = "0000" else '0';
process(sys_clock)
begin
if rising_edge(sys_clock) then
spi_c <= CAS_MOTOR & CAS_SENSE & CAS_READ & CAS_WRITE;
spi_d <= spi_c;
end if;
end process;
slot_test_vector <= CAS_MOTOR &
CAS_SENSE &
CAS_READ &
CAS_WRITE &
IEC_ATN &
IEC_DATA &
IEC_CLOCK &
IEC_RESET &
IEC_SRQ_IN &
SLOT_PHI2 &
SLOT_DOTCLK &
SLOT_RSTn &
SLOT_RWn &
SLOT_BA &
SLOT_DMAn &
SLOT_EXROMn &
SLOT_GAMEn &
SLOT_ROMHn &
SLOT_ROMLn &
SLOT_IO1n &
SLOT_IO2n &
SLOT_IRQn &
SLOT_NMIn &
SLOT_VCC &
SLOT_DATA &
SLOT_ADDR;
SLOT_ADDR(5 downto 2) <= cia_addr;
SLOT_RSTn <= cia_cs_n;
-- cia_cs2
SLOT_ADDR(6) <= cia_reset_n;
SLOT_ROMHn <= cia_rw_n;
SLOT_ADDR(15) <= cia_phi2;
cia_irq_n <= SLOT_PHI2;
SLOT_ADDR(14 downto 7) <= db_to_cia when db_drive = '1' else "ZZZZZZZZ";
db_from_cia <= SLOT_ADDR(14 downto 7);
r_pa: for i in 0 to 7 generate
SLOT_DATA(i) <= pa_to_cia(i) when pa_drive(i) = '1' else 'Z';
pa_from_cia(i) <= SLOT_DATA(i);
end generate;
SLOT_DMAn <= pb_to_cia(0) when pb_drive(0) = '1' else 'Z';
-- SLOT_BA <= pb_to_cia(1) when pb_drive(1) = '1' else 'Z';
SLOT_ROMLn <= pb_to_cia(2) when pb_drive(2) = '1' else 'Z';
SLOT_IO2n <= pb_to_cia(3) when pb_drive(3) = '1' else 'Z';
SLOT_EXROMn <= pb_to_cia(4) when pb_drive(4) = '1' else 'Z';
SLOT_GAMEn <= pb_to_cia(5) when pb_drive(5) = '1' else 'Z';
SLOT_IO1n <= pb_to_cia(6) when pb_drive(6) = '1' else 'Z';
-- SLOT_DOTCLK <= pb_to_cia(7) when pb_drive(7) = '1' else 'Z';
pb_from_cia(0) <= SLOT_DMAn;
pb_from_cia(1) <= SLOT_BA;
pb_from_cia(2) <= SLOT_ROMLn;
pb_from_cia(3) <= SLOT_IO2n;
pb_from_cia(4) <= SLOT_EXROMn;
pb_from_cia(5) <= SLOT_GAMEn;
pb_from_cia(6) <= SLOT_IO1n;
pb_from_cia(7) <= SLOT_DOTCLK;
SLOT_RWn <= hs_to_cia(0) when hs_drive(0) = '1' else 'Z'; -- pin 18 (PC#)
SLOT_IRQn <= hs_to_cia(1) when hs_drive(1) = '1' else 'Z'; -- pin 19 (TOD)
SLOT_ADDR(0) <= hs_to_cia(2) when hs_drive(2) = '1' else 'Z'; -- pin 40 (CNT)
SLOT_ADDR(1) <= hs_to_cia(3) when hs_drive(3) = '1' else 'Z'; -- pin 39 (SP)
SLOT_NMIn <= hs_to_cia(4) when hs_drive(4) = '1' else 'Z'; -- pin 24 (FLAG#)
-- for 6526, hs_drive should be 10010
hs_from_cia(0) <= SLOT_RWn;
hs_from_cia(1) <= SLOT_IRQn;
hs_from_cia(2) <= SLOT_ADDR(0);
hs_from_cia(3) <= SLOT_ADDR(1);
hs_from_cia(4) <= SLOT_NMIn;
-- Wire mapping:
-- 21 SLOT_DATA[0] CIA 2 PA[0]
-- 20 SLOT_DATA[1] CIA 3 PA[1]
-- 19 SLOT_DATA[2] CIA 4 PA[2]
-- 18 SLOT_DATA[3] CIA 5 PA[3]
-- 17 SLOT_DATA[4] CIA 6 PA[4]
-- 16 SLOT_DATA[5] CIA 7 PA[5]
-- 15 SLOT_DATA[6] CIA 8 PA[6]
-- 14 SLOT_DATA[7] CIA 9 PA[7]
-- 13 SLOT_DMA CIA 10 PB[0]
-- 12 SLOT_BA CIA 11 PB[1]
-- 11 SLOT_ROMLn CIA 12 PB[2]
-- 10 SLOT_IO2n CIA 13 PB[3]
-- 9 SLOT_EXROMn CIA 14 PB[4]
-- 8 SLOT_GAMEn CIA 15 PB[5]
-- 7 SLOT_IO1n CIA 16 PB[6]
-- 6 SLOT_DOTCLK CIA 17 PB[7]
-- 5 SLOT_RWn CIA 18 PC#
-- 4 SLOT_IRQn CIA 19 TOD
-- E SLOT_PHI2 CIA 21 IRQ#
-- B SLOT_ROMHn CIA 22 R/W#
-- C SLOT_RSTn CIA 23 CS#
-- D SLOT_NMIn CIA 24 FLAG#
-- F SLOT_ADDR[15] CIA 25 PHI2
-- H SLOT_ADDR[14] CIA 26 DB[7]
-- J SLOT_ADDR[13] CIA 27 DB[6]
-- K SLOT_ADDR[12] CIA 28 DB[5]
-- L SLOT_ADDR[11] CIA 29 DB[4]
-- M SLOT_ADDR[10] CIA 30 DB[3]
-- N SLOT_ADDR[9] CIA 31 DB[2]
-- P SLOT_ADDR[8] CIA 32 DB[1]
-- R SLOT_ADDR[7] CIA 33 DB[0]
-- S SLOT_ADDR[6] CIA 34 RESET#
-- T SLOT_ADDR[5] CIA 35 RS[3]
-- U SLOT_ADDR[4] CIA 36 RS[2]
-- V SLOT_ADDR[3] CIA 37 RS[1]
-- W SLOT_ADDR[2] CIA 38 RS[0]
-- X SLOT_ADDR[1] CIA 39 SP
-- Y SLOT_ADDR[0] CIA 40 CNT
--
cia_write <= not cia_cs_n and not cia_rw_n;
cia_read <= not cia_cs_n and cia_rw_n;
i_my_cia: entity work.cia_registers
generic map (
g_unit_name => "CIA_2" )
port map (
clock => sys_clock,
rising => rising,
falling => falling,
reset => not cia_reset_n,
addr => unsigned(cia_addr),
wen => cia_write,
ren => cia_read,
data_out => db_from_my_cia,
data_in => db_to_cia,
-- pio --
port_a_o => cia2_port_a_o,
port_a_t => cia2_port_a_t,
port_a_i => pa_from_my_cia,
port_b_o => cia2_port_b_o,
port_b_t => cia2_port_b_t,
port_b_i => pb_from_my_cia,
-- serial pin
sp_o => cia2_sp_o,
sp_i => cia2_sp_i,
sp_t => cia2_sp_t,
cnt_i => cia2_cnt_i,
cnt_o => cia2_cnt_o,
cnt_t => cia2_cnt_t,
tod_pin => SLOT_IRQn,
pc_o => cia2_pc_o,
flag_i => SLOT_NMIn,
irq => irq_from_my_cia );
hs_from_my_cia(0) <= cia2_pc_o;
hs_from_my_cia(1) <= SLOT_IRQn;
hs_from_my_cia(2) <= cia2_cnt_i;
hs_from_my_cia(3) <= cia2_sp_i;
hs_from_my_cia(4) <= SLOT_NMIn;
pa_from_my_cia <= cia2_port_a_o or not cia2_port_a_t;
pb_from_my_cia <= cia2_port_b_o or not cia2_port_b_t;
cia2_cnt_i <= (cia2_cnt_o or not cia2_cnt_t) and (hs_to_cia(2) or not hs_drive(2));
cia2_sp_i <= (cia2_sp_o or not cia2_sp_t) and (hs_to_cia(3) or not hs_drive(3));
end architecture;
| gpl-3.0 | 3c7161aebe9cc9f2c60404661b006283 | 0.457892 | 3.260034 | false | false | false | false |
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