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asicguy/crash | fpga/src/common/trunc_unbiased.vhd | 2 | 1,986 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: trunc_unbiased.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Truncates input without negative bias.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity trunc_unbiased is
generic (
WIDTH_IN : integer; -- Input bit width
TRUNCATE : integer); -- Number of bits to truncate
port (
i : in std_logic_vector(WIDTH_IN-1 downto 0); -- Signed Input
o : out std_logic_vector(WIDTH_IN-TRUNCATE-1 downto 0)); -- Truncated Signed Output
end entity;
architecture RTL of trunc_unbiased is
begin
proc_trunc_unbiased : process(i)
variable or_reduce : std_logic := '0';
begin
for k in 0 to TRUNCATE-1 loop
if (k = 0) then
or_reduce := i(k);
else
or_reduce := or_reduce OR i(k);
end if;
end loop;
o <= std_logic_vector(unsigned(i(WIDTH_IN-1 downto TRUNCATE)) + ('0' & (i(WIDTH_IN-1) AND or_reduce)));
end process;
end RTL; | gpl-3.0 | 710dbcf00bb4e2a3f3d7296ff900907d | 0.564451 | 4.189873 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_sim/usb_test_nano8.vhd | 1 | 8,703 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2019-01-27
-- Author: Gideon
-- Description: Testcase 8 for USB host
-- This testcase verfies the correct behavior of the short packets
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
use work.tl_string_util_pkg.all;
use work.nano_addresses_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity usb_test_nano8 is
generic (
g_report_file_name : string := "work/usb_test_nano8.rpt"
);
end entity;
architecture arch of usb_test_nano8 is
signal clocks_stopped : boolean := false;
signal interrupt : std_logic;
signal nyet_count : natural := 2;
signal ack_on_ping : boolean := true;
signal transfer_size : natural := 256;
signal packet_size : natural := 256;
constant Attr_Fifo_Base : unsigned(19 downto 0) := X"00700"; -- 380 * 2
constant Attr_Fifo_Tail_Address : unsigned(19 downto 0) := X"007F0"; -- 3f8 * 2
constant Attr_Fifo_Head_Address : unsigned(19 downto 0) := X"007F2"; -- 3f9 * 2
begin
i_harness: entity work.usb_harness_nano
port map (
ack_on_ping => ack_on_ping,
nyet_count => nyet_count,
interrupt => interrupt,
transfer_size => transfer_size,
packet_size => packet_size,
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable data, remain, newcmd : std_logic_vector(15 downto 0);
variable res : std_logic_vector(7 downto 0);
variable pipe : integer;
variable attr_fifo_tail : integer := 0;
variable attr_fifo_head : integer := 0;
procedure io_write_word(addr : unsigned(19 downto 0); word : std_logic_vector(15 downto 0)) is
begin
io_write(io => io, addr => (addr + 0), data => word(7 downto 0));
io_write(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure io_read_word(addr : unsigned(19 downto 0); word : out std_logic_vector(15 downto 0)) is
begin
io_read(io => io, addr => (addr + 0), data => word(7 downto 0));
io_read(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure read_attr_fifo(result : out std_logic_vector(15 downto 0); timeout : time; new_cmd, remain : out std_logic_vector(15 downto 0)) is
variable data : std_logic_vector(15 downto 0);
variable cmd : std_logic_vector(15 downto 0);
variable res : std_logic_vector(15 downto 0);
variable len : std_logic_vector(15 downto 0);
begin
wait until interrupt = '1' for timeout;
if interrupt = '0' then
sctb_trace("Timeout waiting for interrupt.");
result := X"FFFF";
return;
end if;
io_read_word(addr => (Attr_Fifo_Base + attr_fifo_tail*2), word => data);
attr_fifo_tail := attr_fifo_tail + 1;
if attr_fifo_tail = 16 then
attr_fifo_tail := 0;
end if;
io_write_word(addr => Attr_Fifo_Tail_Address, word => std_logic_vector(to_unsigned(attr_fifo_tail, 16)));
io_read_word(addr => Command, word => cmd);
io_read_word(addr => Command_Result, word => res);
io_read_word(addr => Command_Length, word => len);
sctb_trace("Fifo read: " & hstr(data) & ", Command: " & hstr(cmd) & ", Result: " & hstr(res) & ", Remaining: " & hstr(len));
result := res;
new_cmd := cmd;
remain := len;
end procedure;
begin
bind_io_bus_bfm("io", io);
bind_mem_model("memory", mem);
sctb_open_simulation("path:path", g_report_file_name);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write_word(c_nano_simulation, X"0001" ); -- set nano to simulation mode
io_write_word(c_nano_busspeed, X"0002" ); -- set bus speed to HS
io_write(io, c_nano_enable, X"01" ); -- enable nano
wait for 4 us;
sctb_open_region("Testing an in packet in high speed, transfer size = packet_size", 0);
transfer_size <= 16;
packet_size <= 16;
write_memory_8(mem, X"00050000", X"11");
write_memory_8(mem, X"00050001", X"22");
write_memory_8(mem, X"00050002", X"33");
write_memory_8(mem, X"00050003", X"44");
write_memory_8(mem, X"00050004", X"55");
write_memory_8(mem, X"00050005", X"66");
write_memory_8(mem, X"00050006", X"77");
write_memory_8(mem, X"00050007", X"88");
io_write_word(Command_SplitCtl, X"8131"); -- Hub Address 1, Port 2, Speed = FS, EP = control
--io_write_word(Command_SplitCtl, X"0000"); -- High speed
io_write_word(Command_DevEP, X"0004");
io_write_word(Command_MaxTrans, X"0010");
io_write_word(Command_Length, X"0010");
io_write_word(Command_MemHi, X"0005");
io_write_word(Command_MemLo, X"0000");
io_write_word(Command_Interval, X"0000");
io_write_word(Command_Timeout, X"001A");
io_write_word(c_nano_numpipes, X"0001" ); -- Set active pipes to 1
--io_write_word(Command, X"8041"); -- output
io_write_word(Command, X"4042"); -- 4000 = write to memory, 40 = Do Data, 02 = IN
read_attr_fifo(data, 1.5 ms, newcmd, remain);
sctb_check(data, X"8010", "Unexpected result. Expected data packet of 16 bytes.");
sctb_check(remain, X"0000", "Expected all data to be transferred.");
sctb_check(newcmd, X"4A42", "Expected toggle bit to be set.");
read_attr_fifo(data, 1.5 ms, newcmd, remain);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_open_region("Testing an in packet in high speed, transfer size < packet_size. Note, we start with DATA 1!", 0);
--io_write_word(Command_SplitCtl, X"8130"); -- Hub Address 1, Port 2, Speed = FS, EP = control
transfer_size <= 8;
packet_size <= 16;
io_write_word(Command_MaxTrans, X"0008");
io_write_word(Command_Length, X"0011");
io_write_word(Command_Started, X"0000");
io_write_word(Command, X"4842"); -- 4000 = write to memory, 40 = Do Data, 02 = IN, 800 = toggle is 1
read_attr_fifo(data, 2.5 ms, newcmd, remain);
sctb_check(data and X"F7FF", X"8400", "Unexpected result. Expected data packet of 0 bytes in the last transfer.");
sctb_check(remain, X"0001", "Expected one data byte to be left.");
sctb_check(newcmd, X"4242", "Expected toggle bit to be cleared.");
read_attr_fifo(data, 1.5 ms, newcmd, remain);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_open_region("Testing an in packet in high speed, transfer size > packet_size. Note, we start with DATA 0!", 0);
--io_write_word(Command_SplitCtl, X"8130"); -- Hub Address 1, Port 2, Speed = FS, EP = control
transfer_size <= 32;
packet_size <= 22;
io_write_word(Command_MaxTrans, X"0020");
io_write_word(Command_Length, X"0020");
io_write_word(Command_Started, X"0000");
io_write_word(Command, X"4042"); -- 4000 = write to memory, 40 = Do Data, 02 = IN,
read_attr_fifo(data, 1.5 ms, newcmd, remain);
sctb_check(data and X"F7FF", X"8016", "Unexpected result. Expected data packet of 16 bytes in the last transfer.");
sctb_check(remain, X"000A", "Expected 10 bytes to be left.");
sctb_check(newcmd, X"4A42", "Expected toggle bit to be set.");
read_attr_fifo(data, 1.5 ms, newcmd, remain);
sctb_check(data, X"FFFF", "Result should be TIMEOUT, as the core should have stopped trying after the last attempt");
sctb_close_region;
sctb_close_simulation;
clocks_stopped <= true;
wait;
end process;
end arch;
-- restart; mem load -infile nano_code.hex -format hex /usb_test_nano7/i_harness/i_host/i_nano/i_buf_ram/mem; run 20 ms | gpl-3.0 | 25a9aeb39a724248585f3ad5696d3eeb | 0.576123 | 3.516364 | false | true | false | false |
ringof/radiofist_audio | sigma_delta_adc.vhd | 1 | 948 | -- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See LICENCE.txt for details
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sigma_delta_adc is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC;
feedback : out STD_LOGIC
);
end sigma_delta_adc;
architecture RTL of sigma_delta_adc is
signal clk_i : STD_LOGIC;
signal dout_i : STD_LOGIC;
signal feedback_i : STD_LOGIC;
begin
--Sample the output of the LVDS comparator
adc_sampler : process(reset, clk, din, dout_i)
begin
if reset = '1' then
dout <= '0';
elsif rising_edge(clk) then
dout <= din;
dout_i <= din;
end if;
end process adc_sampler;
--Sample the output of the one_bit ADC for input feedback loop
dac_output : process(reset, clk, dout_i)
begin
if reset = '1' then
feedback <= '0';
elsif rising_edge(clk) then
feedback <= dout_i;
end if;
end process dac_output;
end RTL;
| mit | 9eee9817f7ce515df80bd2c775388d05 | 0.675105 | 2.829851 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio/sys_to_aud.vhd | 1 | 1,468 | --------------------------------------------------------------------------------
-- Entity: sys_to_aud
-- Date:2018-08-02
-- Author: gideon
--
-- Description: Audio sample data in sysclock domain to audio domain filter and synchronizer
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sys_to_aud is
port (
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_tick : in std_logic;
sys_data : in signed(17 downto 0);
audio_clock : in std_logic;
audio_data : out signed(17 downto 0)
);
end entity;
architecture arch of sys_to_aud is
signal sys_filtered : signed(17 downto 0);
signal audio_data_i : std_logic_vector(17 downto 0);
begin
i_filt: entity work.lp_filter
port map (
clock => sys_clock,
reset => sys_reset,
signal_in => sys_data,
low_pass => sys_filtered );
i_sync: entity work.synchronizer_gzw
generic map (
g_width => 18,
g_fast => false
)
port map(
tx_clock => sys_clock,
tx_push => sys_tick,
tx_data => std_logic_vector(sys_filtered),
tx_done => open,
rx_clock => audio_clock,
rx_new_data => open,
rx_data => audio_data_i
);
audio_data <= signed(audio_data_i);
end architecture;
| gpl-3.0 | 6d9685f95b63e69e6d6363177a6f85bf | 0.499319 | 3.764103 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/std/dsram.vhd | 2 | 1,759 | ----------------------------------------------------------------------------------------------
--
-- Input file : dsram.vhd
-- Design name : dsram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Dual Port Synchronous 'read after write' Ram. 1 Read Port and 1
-- Write Port.
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.std_Pkg.all;
entity dsram is generic
(
WIDTH : positive := 32;
SIZE : positive := 8
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
ena_i : in std_logic;
dat_w_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_w_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
clk_i : in std_logic
);
end dsram;
architecture arch of dsram is
type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
signal ram : ram_type := (others => (others => '0'));
attribute ram_style : string;
attribute ram_style of ram : signal is "auto";
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if ena_i = '1' then
if wre_i = '1' then
ram(my_conv_integer(adr_w_i)) <= dat_w_i;
end if;
dat_o <= ram(my_conv_integer(adr_i));
end if;
end if;
end process;
end arch;
| gpl-3.0 | 0808c4be7e819a5e4067e9acfd55fae4 | 0.477544 | 3.857456 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/mm_drive.vhd | 1 | 14,919 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity mm_drive is
generic (
g_big_endian : boolean;
g_audio_tag : std_logic_vector(7 downto 0) := X"01";
g_floppy_tag : std_logic_vector(7 downto 0) := X"02";
g_disk_tag : std_logic_vector(7 downto 0) := X"03";
g_cpu_tag : std_logic_vector(7 downto 0) := X"04";
g_audio : boolean := true;
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
drive_stop : in std_logic := '0';
-- timing
tick_16MHz : in std_logic;
tick_4MHz : in std_logic;
tick_1kHz : in std_logic;
-- slave port on io bus
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic;
-- master port on memory bus
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
fast_clk_o : out std_logic; -- open drain
fast_clk_i : in std_logic;
iec_reset_n : in std_logic := '1';
c64_reset_n : in std_logic := '1';
-- parallel bus pins
via1_port_a_o : out std_logic_vector(7 downto 0);
via1_port_a_i : in std_logic_vector(7 downto 0) := X"55";
via1_port_a_t : out std_logic_vector(7 downto 0);
via1_ca2_o : out std_logic;
via1_ca2_i : in std_logic := '1';
via1_ca2_t : out std_logic;
via1_cb1_o : out std_logic;
via1_cb1_i : in std_logic := '1';
via1_cb1_t : out std_logic;
-- Debug port
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
-- LED
act_led_n : out std_logic;
motor_led_n : out std_logic;
dirty_led_n : out std_logic;
-- audio out
audio_sample : out signed(12 downto 0) );
end entity;
architecture structural of mm_drive is
signal tick_16M_i : std_logic;
signal cia_rising : std_logic;
signal cpu_clock_en : std_logic;
signal iec_reset_o : std_logic;
signal do_track_out : std_logic;
signal do_track_in : std_logic;
signal do_head_bang : std_logic;
signal do_snd_insert : std_logic;
signal do_snd_remove : std_logic;
signal en_hum : std_logic;
signal en_slip : std_logic;
signal use_c64_reset : std_logic;
signal floppy_inserted : std_logic := '0';
signal force_ready : std_logic;
signal bank_is_ram : std_logic_vector(7 downto 1);
signal two_MHz : std_logic;
signal power : std_logic;
signal motor_sound_on : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal side : std_logic;
signal stepper_en : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal track : unsigned(6 downto 0);
signal drive_address : std_logic_vector(1 downto 0) := "00";
signal write_prot_n : std_logic := '1';
signal disk_change_n : std_logic := '1';
signal rdy_n : std_logic := '1';
signal track_0 : std_logic := '0';
signal drv_reset : std_logic := '1';
signal disk_rdata : std_logic_vector(7 downto 0);
signal disk_wdata : std_logic_vector(7 downto 0);
signal drive_stop_i : std_logic;
signal stop_on_freeze : std_logic;
signal drive_type : natural range 0 to 2;
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_param : t_io_req;
signal io_resp_param : t_io_resp;
signal io_req_dirty : t_io_req;
signal io_resp_dirty : t_io_resp;
signal io_req_wd : t_io_req;
signal io_resp_wd : t_io_resp;
signal mem_req_cpu : t_mem_req;
signal mem_resp_cpu : t_mem_resp;
signal mem_req_flop : t_mem_req;
signal mem_resp_flop : t_mem_resp;
signal mem_req_snd : t_mem_req := c_mem_req_init;
signal mem_resp_snd : t_mem_resp;
signal mem_req_disk : t_mem_req;
signal mem_resp_disk : t_mem_resp;
signal mem_req_8 : t_mem_req := c_mem_req_init;
signal mem_resp_8 : t_mem_resp;
signal mem_busy : std_logic;
signal count : unsigned(7 downto 0) := X"00";
signal led_intensity : unsigned(1 downto 0);
begin
i_splitter: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 4
)
port map(
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_dirty,
reqs(2) => io_req_param,
reqs(3) => io_req_wd,
resps(0) => io_resp_regs,
resps(1) => io_resp_dirty,
resps(2) => io_resp_param,
resps(3) => io_resp_wd
);
i_timing: entity work.c1541_timing
port map (
clock => clock,
reset => reset,
tick_4MHz => tick_4MHz,
two_MHz_mode => two_MHz,
mem_busy => mem_busy,
use_c64_reset=> use_c64_reset,
c64_reset_n => c64_reset_n,
iec_reset_n => iec_reset_n,
iec_reset_o => iec_reset_o,
power => power,
drive_stop => drive_stop_i,
cia_rising => cia_rising,
cpu_clock_en => cpu_clock_en ); -- 1 MHz or 2 MHz
drive_stop_i <= drive_stop and stop_on_freeze;
tick_16M_i <= tick_16MHz and not drive_stop_i;
i_cpu: entity work.mm_drive_cpu
generic map (
g_cpu_tag => g_cpu_tag,
g_disk_tag => g_disk_tag,
g_ram_base => g_ram_base )
port map (
clock => clock,
falling => cpu_clock_en,
rising => cia_rising,
reset => drv_reset,
tick_1kHz => tick_1kHz,
tick_4MHz => tick_4MHz,
-- Drive type!!
drive_type => drive_type,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
fast_clk_o => fast_clk_o, -- open drain
fast_clk_i => fast_clk_i,
-- parallel bus pins
par_data_o => via1_port_a_o,
par_data_i => via1_port_a_i,
par_data_t => via1_port_a_t,
par_hsout_o => via1_ca2_o,
par_hsout_i => via1_ca2_i,
par_hsout_t => via1_ca2_t,
par_hsin_o => via1_cb1_o,
par_hsin_i => via1_cb1_i,
par_hsin_t => via1_cb1_t,
-- trace data
debug_data => debug_data,
debug_valid => debug_valid,
-- configuration
extra_ram => bank_is_ram(7), -- FIXME: signal name
-- memory interface
mem_req_cpu => mem_req_cpu,
mem_resp_cpu => mem_resp_cpu,
mem_req_disk => mem_req_disk,
mem_resp_disk => mem_resp_disk,
mem_busy => mem_busy,
-- i/o interface to wd177x
io_req => io_req_wd,
io_resp => io_resp_wd,
io_irq => io_irq,
-- drive pins
power => power,
drive_address => drive_address,
write_prot_n => write_prot_n,
motor_sound_on => motor_sound_on,
motor_on => motor_on,
stepper_en => stepper_en,
mode => mode,
step => step,
side => side,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
two_MHz => two_MHz,
rdy_n => rdy_n,
disk_change_n => disk_change_n,
track_0 => track_0,
track => track,
drv_rdata => disk_rdata,
drv_wdata => disk_wdata,
-- other
power_led => open, -- FIXME
act_led => act_led_n );
-- This may look odd; but 'motor on' is always 0 for the 1581, to shut off the GCR module
-- MotorSound, however, is enabled for 1581, and has the same function as motor_on.
rdy_n <= not (motor_sound_on and floppy_inserted) and not force_ready; -- should have a delay
i_flop: entity work.floppy
generic map (
g_big_endian => g_big_endian,
g_tag => g_floppy_tag )
port map (
clock => clock,
reset => drv_reset,
tick_16MHz => tick_16M_i,
-- signals from MOS 6522 VIA
stepper_en => stepper_en,
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
side => side,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
read_data => disk_rdata,
write_data => disk_wdata,
track => track,
track_is_0 => track_0,
---
io_req_param => io_req_param,
io_resp_param => io_resp_param,
io_req_dirty => io_req_dirty,
io_resp_dirty => io_resp_dirty,
---
floppy_inserted => floppy_inserted,
do_track_out => do_track_out,
do_track_in => do_track_in,
do_head_bang => do_head_bang,
dirty_led_n => dirty_led_n,
---
mem_req => mem_req_flop,
mem_resp => mem_resp_flop );
en_hum <= motor_sound_on and not floppy_inserted;
en_slip <= motor_sound_on and floppy_inserted;
r_snd: if g_audio generate
i_snd: entity work.floppy_sound
generic map (
g_tag => g_audio_tag,
sound_base => g_audio_base(27 downto 16),
motor_hum_addr => X"0000",
flop_slip_addr => X"1200",
track_in_addr => X"2400",
track_out_addr => X"2C00",
head_bang_addr => X"3480",
insert_addr => X"3D00",
remove_addr => X"7D00",
motor_len => 4410,
track_in_len => X"0800", -- ~100 ms
track_out_len => X"0880", -- ~100 ms
head_bang_len => X"0880", -- ~100 ms
insert_len => X"3F80", -- ~740 ms
remove_len => X"3800" ) -- ~650 ms
port map (
clock => clock,
reset => drv_reset,
tick_4MHz => tick_4MHz,
do_trk_out => do_track_out,
do_trk_in => do_track_in,
do_head_bang => do_head_bang,
do_insert => do_snd_insert,
do_remove => do_snd_remove,
en_hum => en_hum,
en_slip => en_slip,
-- memory interface
mem_req => mem_req_snd,
mem_resp => mem_resp_snd,
-- audio
sample_out => audio_sample );
end generate;
i_regs: entity work.drive_registers
generic map (
g_multi_mode => true )
port map (
clock => clock,
reset => reset,
tick_1kHz => tick_1kHz,
io_req => io_req_regs,
io_resp => io_resp_regs,
iec_reset_o => iec_reset_o,
use_c64_reset => use_c64_reset,
power => power,
drv_reset => drv_reset,
drive_address => drive_address,
floppy_inserted => floppy_inserted,
disk_change_n => disk_change_n,
force_ready => force_ready,
write_prot_n => write_prot_n,
bank_is_ram => bank_is_ram,
stop_on_freeze => stop_on_freeze,
drive_type => drive_type,
do_snd_insert => do_snd_insert,
do_snd_remove => do_snd_remove,
track => track,
side => side,
mode => mode,
motor_on => motor_sound_on );
-- memory arbitration
i_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 4,
g_registered => false )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_flop,
reqs(1) => mem_req_cpu,
reqs(2) => mem_req_snd,
reqs(3) => mem_req_disk,
resps(0) => mem_resp_flop,
resps(1) => mem_resp_cpu,
resps(2) => mem_resp_snd,
resps(3) => mem_resp_disk,
req => mem_req_8,
resp => mem_resp_8 );
i_conv32: entity work.mem_to_mem32(route_through)
generic map (
g_big_endian => g_big_endian )
port map(
clock => clock,
reset => reset,
mem_req_8 => mem_req_8,
mem_resp_8 => mem_resp_8,
mem_req_32 => mem_req,
mem_resp_32 => mem_resp );
process(clock)
variable led_int : unsigned(7 downto 0);
begin
if rising_edge(clock) then
count <= count + 1;
if count=X"00" then
motor_led_n <= '0'; -- on
end if;
led_int := led_intensity & led_intensity & led_intensity & led_intensity;
if count=led_int then
motor_led_n <= '1'; -- off
end if;
end if;
end process;
led_intensity <= "00" when power='0' else
"01" when floppy_inserted='0' else
"10" when motor_on='0' else
"11";
end architecture;
| gpl-3.0 | eb383ef88175ed6f004f7d9a055510bf | 0.461224 | 3.373813 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/vhdl_sim/mblite_simu.vhd | 1 | 4,396 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu is
end entity;
architecture test of mblite_simu is
signal clock : std_logic := '0';
signal reset : std_logic;
signal imem_o : imem_out_type;
signal imem_i : imem_in_type;
signal dmem_o : dmem_out_type;
signal dmem_i : dmem_in_type;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 1048575) := (others => (others => '0')); -- 4MB
signal last_char : std_logic_vector(7 downto 0);
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
core0 : core
port map (
imem_o => imem_o,
imem_i => imem_i,
dmem_o => dmem_o,
dmem_i => dmem_i,
int_i => irq_i,
int_o => irq_o,
rst_i => reset,
clk_i => clock );
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
if imem_o.ena_o = '1' then
imem_i.dat_i <= memory(to_integer(unsigned(imem_o.adr_o(21 downto 2))));
-- if (imem_i.dat_i(31 downto 26) = "000101") and (imem_i.dat_i(1 downto 0) = "01") then
-- report "Suspicious CMPS" severity warning;
-- end if;
end if;
if dmem_o.ena_o = '1' then
if dmem_o.adr_o(31 downto 25) = "0000000" then
if dmem_o.we_o = '1' then
for i in 0 to 3 loop
if dmem_o.sel_o(i) = '1' then
memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))))(i*8+7 downto i*8) := dmem_o.dat_o(i*8+7 downto i*8);
end if;
end loop;
else -- read
dmem_i.dat_i <= memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))));
end if;
else -- I/O
if dmem_o.we_o = '1' then -- write
case dmem_o.adr_o(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := dmem_o.dat_o(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
last_char <= char;
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(dmem_o.adr_o) & " dropped";
end case;
else -- read
case dmem_o.adr_o(19 downto 0) is
when X"0000C" => -- Capabilities
dmem_i.dat_i <= X"00000002";
when X"00012" => -- UART_FLAGS
dmem_i.dat_i <= X"40404040";
when X"2000A" => -- 1541_A memmap
dmem_i.dat_i <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
dmem_i.dat_i <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(dmem_o.adr_o) & " dropped";
dmem_i.dat_i <= X"00000000";
end case;
end if;
end if;
end if;
if reset = '1' then
imem_i.ena_i <= '1';
dmem_i.ena_i <= '1';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | bd33995829af1e5f7bad6e691a6ed86d | 0.429026 | 3.852761 | false | false | false | false |
keyru/hdl-make | tests/counter/top/brevia2_dk/vhdl/brevia2_top.vhd | 2 | 1,360 | ----------------------------------------------------------
-- Design : Counter VHDL top module, Lattice Brevia2
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity brevia2_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
clken_o: out std_logic;
led_o: out std_logic_vector(7 downto 0)
);
end brevia2_top;
----------------------------------------------------------
architecture structure of brevia2_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
clken_o <= '1';
s_clear <= not clear_i;
s_count <= not count_i;
led_o <= not s_Q;
end architecture structure;
----------------------------------------------------------------
| gpl-3.0 | f1e290bea3dfc693fcdc1546fc28c56b | 0.478676 | 3.685637 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/xilinx_primitives/RAMB16BWE_S36_S9.vhd | 1 | 12,647 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : RAMB16BWE_S36_S9
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Altera wrapper
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity RAMB16BWE_S36_S9 is
generic (
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000";
INIT_B : bit_vector := X"000000000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "READ_FIRST";
WRITE_MODE_B : string := "READ_FIRST"
);
port (
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(7 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(0 downto 0);
ADDRA : in std_logic_vector(8 downto 0);
ADDRB : in std_logic_vector(10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(7 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(3 downto 0);
WEB : in std_ulogic
);
end entity;
architecture wrapper of RAMB16BWE_S36_S9 is
signal wren_a : std_logic_vector(3 downto 0);
signal wren_b : std_logic_vector(3 downto 0);
signal q_b : std_logic_vector(31 downto 0);
signal b_mux : std_logic_vector(1 downto 0);
signal address_a : std_logic_vector(8 downto 0);
signal address_b : std_logic_vector(10 downto 2);
begin
address_a <= ADDRA(address_a'range);
address_b <= ADDRB(address_b'range);
r: for i in 0 to 3 generate
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 512,
numwords_b => 512,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 9,
widthad_b => 9,
width_a => 8,
width_b => 8,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => address_a,
address_b => address_b,
clock0 => CLKA,
clock1 => CLKB,
data_a => DIA(8*i + 7 downto 8*i),
data_b => DIB,
rden_a => ENA,
rden_b => ENB,
wren_a => wren_a(i),
wren_b => wren_b(i),
q_a => DOA(8*i + 7 downto 8*i),
q_b => q_b(8*i + 7 downto 8*i)
);
end generate;
process(CLKB)
begin
if rising_edge(CLKB) then
if ENB = '1' then
b_mux <= ADDRB(1 downto 0);
end if;
end if;
end process;
with b_mux select DOB <=
q_b(7 downto 0) when "00",
q_b(15 downto 8) when "01",
q_b(23 downto 16) when "10",
q_b(31 downto 24) when "11",
"XXXXXXXX" when others;
wren_a <= WEA when ENA = '1' else "0000";
wren_b(0) <= '1' when WEB = '1' and ENB = '1' and ADDRB(1 downto 0) = "00" else '0';
wren_b(1) <= '1' when WEB = '1' and ENB = '1' and ADDRB(1 downto 0) = "01" else '0';
wren_b(2) <= '1' when WEB = '1' and ENB = '1' and ADDRB(1 downto 0) = "10" else '0';
wren_b(3) <= '1' when WEB = '1' and ENB = '1' and ADDRB(1 downto 0) = "11" else '0';
end architecture;
| gpl-3.0 | f9558c1fb9da3c566e00cabf866ebce0 | 0.642366 | 4.944097 | false | false | false | false |
trondd/mkjpeg | design/BufFifo/BUF_FIFO.vhd | 1 | 11,786 | -------------------------------------------------------------------------------
-- File Name : BUF_FIFO.vhd
--
-- Project : JPEG_ENC
--
-- Module : BUF_FIFO
--
-- Content : Input FIFO Buffer
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090311: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity BUF_FIFO is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HOST PROG
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
sof : in std_logic;
-- HOST DATA
iram_wren : in std_logic;
iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
fifo_almost_full : out std_logic;
-- FDCT
fdct_fifo_rd : in std_logic;
fdct_fifo_q : out std_logic_vector(23 downto 0);
fdct_fifo_hf_full : out std_logic
);
end entity BUF_FIFO;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of BUF_FIFO is
constant C_NUM_LINES : integer := 8 + C_EXTRA_LINES;
signal pixel_cnt : unsigned(15 downto 0);
signal line_cnt : unsigned(15 downto 0);
signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
signal ramwaddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
signal ramenw : STD_LOGIC;
signal ramraddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
signal pix_inblk_cnt : unsigned(3 downto 0);
signal pix_inblk_cnt_d1 : unsigned(3 downto 0);
signal line_inblk_cnt : unsigned(2 downto 0);
signal read_block_cnt : unsigned(12 downto 0);
signal read_block_cnt_d1 : unsigned(12 downto 0);
signal write_block_cnt : unsigned(12 downto 0);
signal ramraddr_int : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
signal raddr_base_line : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
signal raddr_tmp : unsigned(15 downto 0);
signal ramwaddr_d1 : unsigned(ramwaddr'range);
signal line_lock : unsigned(log2(C_NUM_LINES)-1 downto 0);
signal memwr_line_cnt : unsigned(log2(C_NUM_LINES)-1 downto 0);
signal memrd_offs_cnt : unsigned(log2(C_NUM_LINES)-1+1 downto 0);
signal memrd_line : unsigned(log2(C_NUM_LINES)-1 downto 0);
signal wr_line_idx : unsigned(15 downto 0);
signal rd_line_idx : unsigned(15 downto 0);
signal image_write_end : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- RAM for SUB_FIFOs
-------------------------------------------------------------------
U_SUB_RAMZ : entity work.SUB_RAMZ
generic map
(
RAMADDR_W => log2( C_MAX_LINE_WIDTH*C_NUM_LINES ),
RAMDATA_W => C_PIXEL_BITS
)
port map
(
d => ramd,
waddr => std_logic_vector(ramwaddr_d1),
raddr => std_logic_vector(ramraddr),
we => ramenw,
clk => clk,
q => ramq
);
-------------------------------------------------------------------
-- register RAM data input
-------------------------------------------------------------------
p_mux1 : process(CLK, RST)
begin
if RST = '1' then
ramenw <= '0';
ramd <= (others => '0');
elsif CLK'event and CLK = '1' then
ramd <= iram_wdata;
ramenw <= iram_wren;
end if;
end process;
-------------------------------------------------------------------
-- resolve RAM write address
-------------------------------------------------------------------
p_pixel_cnt : process(CLK, RST)
begin
if RST = '1' then
pixel_cnt <= (others => '0');
memwr_line_cnt <= (others => '0');
wr_line_idx <= (others => '0');
ramwaddr <= (others => '0');
ramwaddr_d1 <= (others => '0');
image_write_end <= '0';
elsif CLK'event and CLK = '1' then
ramwaddr_d1 <= ramwaddr;
if iram_wren = '1' then
-- end of line
if pixel_cnt = unsigned(img_size_x)-1 then
pixel_cnt <= (others => '0');
-- absolute write line index
wr_line_idx <= wr_line_idx + 1;
if wr_line_idx = unsigned(img_size_y)-1 then
image_write_end <= '1';
end if;
-- memory line index
if memwr_line_cnt = C_NUM_LINES-1 then
memwr_line_cnt <= (others => '0');
ramwaddr <= (others => '0');
else
memwr_line_cnt <= memwr_line_cnt + 1;
ramwaddr <= ramwaddr + 1;
end if;
else
pixel_cnt <= pixel_cnt + 1;
ramwaddr <= ramwaddr + 1;
end if;
end if;
if sof = '1' then
pixel_cnt <= (others => '0');
ramwaddr <= (others => '0');
memwr_line_cnt <= (others => '0');
wr_line_idx <= (others => '0');
image_write_end <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- FIFO half full / almost full flag generation
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
fdct_fifo_hf_full <= '0';
fifo_almost_full <= '0';
elsif CLK'event and CLK = '1' then
if rd_line_idx + 8 <= wr_line_idx then
fdct_fifo_hf_full <= '1';
else
fdct_fifo_hf_full <= '0';
end if;
fifo_almost_full <= '0';
if wr_line_idx = rd_line_idx + C_NUM_LINES-1 then
if pixel_cnt >= unsigned(img_size_x)-1-1 then
fifo_almost_full <= '1';
end if;
elsif wr_line_idx > rd_line_idx + C_NUM_LINES-1 then
fifo_almost_full <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------
-- read side
-------------------------------------------------------------------
p_mux5 : process(CLK, RST)
begin
if RST = '1' then
memrd_offs_cnt <= (others => '0');
read_block_cnt <= (others => '0');
pix_inblk_cnt <= (others => '0');
line_inblk_cnt <= (others => '0');
rd_line_idx <= (others => '0');
pix_inblk_cnt_d1 <= (others => '0');
read_block_cnt_d1 <= (others => '0');
elsif CLK'event and CLK = '1' then
pix_inblk_cnt_d1 <= pix_inblk_cnt;
read_block_cnt_d1 <= read_block_cnt;
-- BUF FIFO read
if fdct_fifo_rd = '1' then
-- last pixel in block
if pix_inblk_cnt = 8-1 then
pix_inblk_cnt <= (others => '0');
-- last line in 8
if line_inblk_cnt = 8-1 then
line_inblk_cnt <= (others => '0');
-- last block in last line
if read_block_cnt = unsigned(img_size_x(15 downto 3))-1 then
read_block_cnt <= (others => '0');
rd_line_idx <= rd_line_idx + 8;
if memrd_offs_cnt + 8 > C_NUM_LINES-1 then
memrd_offs_cnt <= memrd_offs_cnt + 8 - C_NUM_LINES;
else
memrd_offs_cnt <= memrd_offs_cnt + 8;
end if;
else
read_block_cnt <= read_block_cnt + 1;
end if;
else
line_inblk_cnt <= line_inblk_cnt + 1;
end if;
else
pix_inblk_cnt <= pix_inblk_cnt + 1;
end if;
end if;
if memrd_offs_cnt + (line_inblk_cnt) > C_NUM_LINES-1 then
memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt) - (C_NUM_LINES);
else
memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt);
end if;
if sof = '1' then
memrd_line <= (others => '0');
memrd_offs_cnt <= (others => '0');
read_block_cnt <= (others => '0');
pix_inblk_cnt <= (others => '0');
line_inblk_cnt <= (others => '0');
rd_line_idx <= (others => '0');
end if;
end if;
end process;
-- generate RAM data output based on 16 or 24 bit mode selection
fdct_fifo_q <= (ramq(15 downto 11) & "000" &
ramq(10 downto 5) & "00" &
ramq(4 downto 0) & "000") when C_PIXEL_BITS = 16 else
std_logic_vector(resize(unsigned(ramq), 24));
ramraddr <= ramraddr_int(ramraddr'range);
-------------------------------------------------------------------
-- resolve RAM read address
-------------------------------------------------------------------
p_mux4 : process(CLK, RST)
begin
if RST = '1' then
ramraddr_int <= (others => '0');
elsif CLK'event and CLK = '1' then
raddr_base_line <= (memrd_line) * unsigned(img_size_x);
raddr_tmp <= (read_block_cnt_d1 & "000") + pix_inblk_cnt_d1;
ramraddr_int <= raddr_tmp + raddr_base_line;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | 8f021a31fb85807af644a1af4e8caf37 | 0.370609 | 4.40269 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_contoller.vhd | 2 | 12,032 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_controller is
generic (
g_tag : std_logic_vector(7 downto 0) := X"55" );
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- LED interface
usb_busy : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_mem_req : out t_mem_req;
sys_mem_resp: in t_mem_resp;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp );
end usb_controller;
architecture wrap of usb_controller is
signal nano_addr : unsigned(7 downto 0);
signal nano_write : std_logic;
signal nano_read : std_logic;
signal nano_wdata : std_logic_vector(15 downto 0);
signal nano_rdata : std_logic_vector(15 downto 0);
signal stall : std_logic := '0';
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal rx_valid_token : std_logic := '0';
signal rx_valid_handsh : std_logic := '0';
signal rx_valid_packet : std_logic := '0';
signal rx_error : std_logic := '0';
signal rx_user_valid : std_logic := '0';
signal rx_user_start : std_logic := '0';
signal rx_user_data : std_logic_vector(7 downto 0) := X"12";
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal tx_send_token : std_logic;
signal tx_send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal tx_send_data : std_logic;
signal tx_no_data : std_logic;
signal tx_user_data : std_logic_vector(7 downto 0);
signal tx_user_last : std_logic;
signal tx_user_next : std_logic;
signal tx_length : unsigned(10 downto 0);
signal transferred : unsigned(10 downto 0);
-- cmd interface
signal cmd_addr : std_logic_vector(3 downto 0);
signal cmd_valid : std_logic;
signal cmd_write : std_logic;
signal cmd_wdata : std_logic_vector(15 downto 0);
signal cmd_ack : std_logic;
signal cmd_ready : std_logic;
signal sys_buf_addr : std_logic_vector(10 downto 0);
signal sys_buf_en : std_logic;
signal sys_buf_we : std_logic;
signal sys_buf_wdata : std_logic_vector(7 downto 0);
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal ulpi_buf_addr : std_logic_vector(10 downto 0);
signal ulpi_buf_en : std_logic;
signal ulpi_buf_we : std_logic;
signal ulpi_buf_wdata : std_logic_vector(7 downto 0);
signal ulpi_buf_rdata : std_logic_vector(7 downto 0);
-- low level
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal tx_chirp_start : std_logic;
signal tx_chirp_level : std_logic;
signal tx_chirp_end : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal reg_read : std_logic := '0';
signal reg_write : std_logic := '0';
signal reg_ack : std_logic;
signal reg_addr : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
signal speed : std_logic_vector(1 downto 0) := "10";
begin
i_nano: entity work.nano
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- i/o interface
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => stall,
-- system interface (to write code into the nano)
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
i_regs: entity work.usb_io_bank
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- i/o interface
io_addr => nano_addr,
io_read => nano_read,
io_write => nano_write,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => stall,
-- memory controller
mem_ready => cmd_ready,
transferred => transferred,
-- Register access
reg_addr => reg_addr,
reg_read => reg_read,
reg_write => reg_write,
reg_ack => reg_ack,
reg_wdata => reg_wdata,
reg_rdata => rx_data,
status => status,
-- I/O pins from RX
rx_pid => rx_pid,
rx_token => rx_token,
rx_valid_token => rx_valid_token,
rx_valid_handsh => rx_valid_handsh,
rx_valid_packet => rx_valid_packet,
rx_error => rx_error,
-- I/O pins to TX
tx_pid => tx_pid,
tx_token => tx_token,
tx_send_token => tx_send_token,
tx_send_handsh => tx_send_handsh,
tx_send_data => tx_send_data,
tx_length => tx_length,
tx_no_data => tx_no_data,
tx_ack => tx_ack,
tx_chirp_start => tx_chirp_start,
tx_chirp_end => tx_chirp_end,
tx_chirp_level => tx_chirp_level );
i_bridge_to_mem_ctrl: entity work.bridge_to_mem_ctrl
port map (
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset,
nano_addr => nano_addr,
nano_write => nano_write,
nano_wdata => nano_wdata,
sys_clock => sys_clock,
sys_reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack );
i_memctrl: entity work.usb_memory_ctrl
generic map (
g_tag => g_tag )
port map (
clock => sys_clock,
reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack,
cmd_ready => cmd_ready,
-- BRAM interface
ram_addr => sys_buf_addr,
ram_en => sys_buf_en,
ram_we => sys_buf_we,
ram_wdata => sys_buf_wdata,
ram_rdata => sys_buf_rdata,
-- memory interface
mem_req => sys_mem_req,
mem_resp => sys_mem_resp );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_buf_we,
ADDRA => sys_buf_addr,
DIA => sys_buf_wdata,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => ulpi_buf_en,
WEB => ulpi_buf_we,
ADDRB => ulpi_buf_addr,
DIB => ulpi_buf_wdata,
DIPB => "0",
DOB => ulpi_buf_rdata );
i_buf_ctrl: entity work.rxtx_to_buf
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- transferred length
transferred => transferred,
-- bram interface
ram_addr => ulpi_buf_addr,
ram_wdata => ulpi_buf_wdata,
ram_rdata => ulpi_buf_rdata,
ram_we => ulpi_buf_we,
ram_en => ulpi_buf_en,
-- Interface from RX
user_rx_valid => rx_user_valid,
user_rx_start => rx_user_start,
user_rx_data => rx_user_data,
user_rx_last => rx_last,
-- Interface to TX
send_data => tx_send_data,
last_addr => tx_length,
no_data => tx_no_data,
user_tx_data => tx_user_data,
user_tx_last => tx_user_last,
user_tx_next => tx_user_next );
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
-- Status
speed => speed,
status => status,
busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens
send_token => tx_send_token,
send_handsh => tx_send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => tx_send_data,
no_data => tx_no_data,
user_data => tx_user_data,
user_last => tx_user_last,
user_next => tx_user_next,
-- Interface to read/write registers and reset packets
send_reset_data => tx_chirp_start,
reset_data => tx_chirp_level,
reset_last => tx_chirp_end );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => rx_valid_token,
valid_handsh => rx_valid_handsh,
valid_packet => rx_valid_packet,
data_out => rx_user_data,
data_valid => rx_user_valid,
data_start => rx_user_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_addr,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
end wrap;
| gpl-3.0 | 6808d12a583eb9f354b7971a785088e9 | 0.471493 | 3.584153 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/cia_timer.vhd | 1 | 3,481 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cia_pkg.all;
entity cia_timer is
port (
clock : in std_logic;
reset : in std_logic;
prescale_en : in std_logic;
timer_ctrl : in timer_t;
timer_set_t : in std_logic;
timer_in : in std_logic_vector(15 downto 0);
cnt : in std_logic;
othr_tmr_ev : in std_logic;
timer_out : out std_logic;
timer_event : out std_logic;
timer_stop : out std_logic;
timer_count : out std_logic_vector(15 downto 0) );
end cia_timer;
architecture Gideon of cia_timer is
signal mux_out : unsigned(15 downto 0);
signal count_next : unsigned(15 downto 0);
signal count_i : unsigned(15 downto 0);
signal timer_out_t : std_logic := '0';
signal cnt_d, cnt_c : std_logic := '0';
signal cnt_en : std_logic := '0';
signal cnt_en_d : std_logic := '0';
signal force_load : std_logic := '0';
signal event_i : std_logic;
signal event_d : std_logic := '0';
signal event_edge : std_logic;
signal load, carry : std_logic;
signal count_is_zero : std_logic;
signal run_mode_d : std_logic := '0';
begin
timer_out <= event_i when timer_ctrl.outmode = '0'
else timer_out_t xor event_edge;
timer_event <= event_i;
timer_stop <= event_i and (run_mode_d or timer_ctrl.runmode);
process(timer_ctrl.inmode, timer_ctrl.run, timer_ctrl.load, cnt_c, cnt_d, othr_tmr_ev)
begin
cnt_en <= '0';
case timer_ctrl.inmode is
when "00" => cnt_en <= timer_ctrl.run and '1';
when "01" => cnt_en <= timer_ctrl.run and cnt_c and not cnt_d;
when "10" => cnt_en <= timer_ctrl.run and othr_tmr_ev;
when "11" => cnt_en <= timer_ctrl.run and cnt_c and othr_tmr_ev;
when others => null;
end case;
end process;
timer_count <= std_logic_vector(mux_out);
mux_out <= unsigned(timer_in) when load = '1' else count_i;
count_next <= mux_out - 1 when carry = '1' else mux_out;
load <= force_load or event_i;
carry <= cnt_en_d and not load;
event_i <= count_is_zero and cnt_en_d;
event_edge <= event_i and not event_d;
count_is_zero <= '1' when count_i = X"0000" else '0';
process(clock)
begin
if rising_edge(clock) then
if prescale_en='1' then
run_mode_d <= timer_ctrl.runmode;
force_load <= timer_ctrl.load;
cnt_c <= cnt;
cnt_d <= cnt_c;
cnt_en_d <= cnt_en;
event_d <= event_i;
count_i <= count_next;
if timer_set_t = '1' then
timer_out_t <= '1';
elsif event_edge = '1' then
timer_out_t <= not timer_out_t; -- toggle
end if;
end if;
if reset='1' then
count_i <= (others => '1');
timer_out_t <= '0';
force_load <= '0';
end if;
end if;
end process;
end Gideon;
| gpl-3.0 | a36046beca772bcc5893e99b657ca4b7 | 0.477736 | 3.509073 | false | false | false | false |
chiggs/nvc | test/regress/protected2.vhd | 5 | 1,453 | package pack is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
end package;
package body pack is
type SharedCounter is protected body
constant INIT : integer := 5;
variable counter: Integer := INIT;
variable dummy: Integer;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity protected2 is
end entity;
use work.pack.all;
architecture test of protected2 is
shared variable x : SharedCounter;
begin
process is
begin
assert x.value = 5;
x.increment;
report "value is now " & integer'image(x.value);
x.increment(2);
assert x.value = 8;
wait;
end process;
process is
begin
wait for 1 ns;
assert x.value = 8;
x.decrement;
assert x.value = 7;
wait;
end process;
end architecture;
| gpl-3.0 | a22a4e83e3ec1fa19c2f434d5a4b8505 | 0.562285 | 4.875839 | false | false | false | false |
armandas/Arcade | main.vhd | 1 | 6,134 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity main is
port(
clk, not_reset: in std_logic;
nes_data_1: in std_logic;
nes_data_2: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(2 downto 0);
buzzer: out std_logic;
nes_clk_out: out std_logic;
nes_ps_control: out std_logic
);
end main;
architecture behaviour of main is
signal rgb_reg, rgb_next: std_logic_vector(2 downto 0);
signal px_x, px_y: std_logic_vector(9 downto 0);
signal video_on: std_logic;
signal menu_rgb, plong_rgb, fpgalaxy_rgb: std_logic_vector(2 downto 0);
signal plong_buzzer, fpgalaxy_buzzer: std_logic;
signal nes1_a, nes1_b, nes1_select, nes1_start,
nes1_up, nes1_down, nes1_left, nes1_right: std_logic;
signal nes2_a, nes2_b, nes2_select, nes2_start,
nes2_up, nes2_down, nes2_left, nes2_right: std_logic;
-- signals that go into graphics logic
signal f_nes1_a, f_nes1_b, f_nes1_left, f_nes1_right: std_logic;
signal p_nes1_up, p_nes1_down, p_nes1_start,
p_nes2_up, p_nes2_down, p_nes2_start: std_logic;
-- game selection: 0 - plong, 1 - fpgalaxy
signal selected_menu: std_logic;
-- which stream is enabled:
-- 00: menu
-- 01: fpgalaxy
-- 10: plong
-- 11: don't care
signal enable, enable_next: std_logic_vector(1 downto 0);
-- sound events
signal shot, destroyed,
ball_bounced, ball_missed: std_logic;
signal buzzer1, buzzer2: std_logic;
begin
process(clk, not_reset)
begin
if not_reset = '0' then
rgb_reg <= (others => '0');
enable <= (others => '0');
elsif falling_edge(clk) then
rgb_reg <= rgb_next;
enable <= enable_next;
end if;
end process;
rgb_next <= plong_rgb when enable = "01" else
fpgalaxy_rgb when enable = "10" else
menu_rgb;
enable_next <= "01" when (enable = "00" and
selected_menu = '0' and
nes1_select = '1') else
"10" when (enable = "00" and
selected_menu = '1' and
nes1_select = '1') else
enable;
f_nes1_a <= nes1_a when enable = "10" else '0';
f_nes1_b <= nes1_a when enable = "10" else '0';
f_nes1_left <= nes1_left when enable = "10" else '0';
f_nes1_right <= nes1_right when enable = "10" else '0';
p_nes1_up <= nes1_up when enable = "01" else '0';
p_nes1_down <= nes1_down when enable = "01" else '0';
p_nes1_start <= nes1_start when enable = "01" else '0';
p_nes2_up <= nes2_up when enable = "01" else '0';
p_nes2_down <= nes2_down when enable = "01" else '0';
p_nes2_start <= nes2_start when enable = "01" else '0';
vga:
entity work.vga(sync)
port map(
clk => clk, not_reset => not_reset,
hsync => hsync, vsync => vsync,
video_on => video_on, p_tick => open,
pixel_x => px_x, pixel_y => px_y
);
menu:
entity work.menu(behaviour)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
nes_up => nes1_up, nes_down => nes1_down,
selection => selected_menu,
rgb_pixel => menu_rgb
);
fpgalaxy:
entity work.fpgalaxy_graphics(dispatcher)
port map(
clk => clk, not_reset => not_reset,
px_x => px_x, px_y => px_y,
video_on => video_on,
nes_a => f_nes1_a, nes_b => f_nes1_b,
nes_left => f_nes1_left, nes_right => f_nes1_right,
rgb_stream => fpgalaxy_rgb,
shooting_sound => shot, destruction_sound => destroyed
);
plong:
entity work.plong_graphics(dispatcher)
port map(
clk => clk, not_reset => not_reset,
nes1_up => p_nes1_up, nes1_down => p_nes1_down,
nes2_up => p_nes2_up, nes2_down => p_nes2_down,
nes1_start => p_nes1_start,
nes2_start => p_nes2_start,
px_x => px_x, px_y => px_y,
video_on => video_on,
rgb_stream => plong_rgb,
ball_bounced => ball_bounced,
ball_missed => ball_missed
);
sound1:
entity work.player(behaviour)
port map(
clk => clk, not_reset => not_reset,
bump_sound => ball_bounced, miss_sound => ball_missed,
shooting_sound => shot, explosion_sound => '0',
buzzer => buzzer2
);
-- two units needed for fpgalaxy due to one sound canceling the other
buzzer <= buzzer1 or buzzer2;
sound2:
entity work.player(behaviour)
port map(
clk => clk, not_reset => not_reset,
bump_sound => ball_bounced, miss_sound => ball_missed,
shooting_sound => '0', explosion_sound => destroyed,
buzzer => buzzer1
);
NES_controller1:
entity work.controller(arch)
port map(
clk => clk, not_reset => not_reset,
data_in => nes_data_1,
clk_out => nes_clk_out,
ps_control => nes_ps_control,
gamepad(0) => nes1_a, gamepad(1) => nes1_b,
gamepad(2) => nes1_select, gamepad(3) => nes1_start,
gamepad(4) => nes1_up, gamepad(5) => nes1_down,
gamepad(6) => nes1_left, gamepad(7) => nes1_right
);
NES_controller2:
entity work.controller(arch)
port map(
clk => clk, not_reset => not_reset,
data_in => nes_data_2,
clk_out => open,
ps_control => open,
gamepad(0) => nes2_a, gamepad(1) => nes2_b,
gamepad(2) => nes2_select, gamepad(3) => nes2_start,
gamepad(4) => nes2_up, gamepad(5) => nes2_down,
gamepad(6) => nes2_left, gamepad(7) => nes2_right
);
rgb <= rgb_reg;
end behaviour; | bsd-2-clause | a73040eee2951d40a585681355f04574 | 0.521193 | 3.303177 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_source/usb1_data_crc.vhd | 2 | 1,827 | -------------------------------------------------------------------------------
-- Title : data_crc.vhd
-------------------------------------------------------------------------------
-- File : data_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB data
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity usb1_data_crc is
port (
clock : in std_logic;
sync : in std_logic;
valid : in std_logic;
data_in : in std_logic_vector(7 downto 0);
crc : out std_logic_vector(15 downto 0) );
end usb1_data_crc;
architecture Gideon of usb1_data_crc is
constant polynom : std_logic_vector(15 downto 0) := X"8004";
-- CRC-5 = x5 + x2 + 1
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
if sync = '1' then
tmp := (others => '1');
end if;
if valid = '1' then
for i in data_in'reverse_range loop -- LSB first!
d := data_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & d; --'0';
if d = '1' then
tmp := tmp xor polynom;
end if;
end loop;
end if;
for i in tmp'range loop -- reverse and invert
crc(crc'high-i) <= not(tmp(i));
end loop;
end if;
end process;
end Gideon;
| gpl-3.0 | 687ec5b8029c19f7e31dae7b0f7f5b65 | 0.394089 | 4.391827 | false | false | false | false |
asicguy/crash | fpga/src/spectrum_sense/spectrum_sense.vhd | 2 | 30,378 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: spectrum_sense.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Specturm sensing by implementing a FFT, magnitude calculation,
-- and threshold detection. The entire pipeline is single
-- precision floating point and based on Xilinx IP.
-- Maximum FFT size of 4096.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity spectrum_sense is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Time Domain / FFT Input)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (Frequency Domain / FFT Output)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Strobes when threshold exceeded
-- Sideband signals
threshold_not_exceeded : out std_logic;
threshold_not_exceeded_stb : out std_logic;
threshold_exceeded : out std_logic;
threshold_exceeded_stb : out std_logic);
end entity;
architecture RTL of spectrum_sense is
-------------------------------------------------------------------------------
-- Function / Procedure Declaration
-------------------------------------------------------------------------------
function float2real(fpin: std_logic_vector(31 downto 0)) return real is
constant xdiv : real := 2.0**23;
variable exp : integer;
variable mant : integer;
variable multexp : real;
variable mantdec : real;
variable res : real;
begin
exp := to_integer(unsigned(fpin(30 downto 23))) - 127;
multexp := 2.0**exp;
mant := to_integer(unsigned('1' & fpin(22 downto 0)));
mantdec := real(mant)/xdiv;
res := mantdec*multexp;
-- Check sign
if (fpin(31) = '1') then
res := -res;
end if;
return(res);
end function;
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component fft_axis
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_config_tdata : in std_logic_vector(23 downto 0);
s_axis_config_tvalid : in std_logic;
s_axis_config_tready : out std_logic;
s_axis_data_tdata : in std_logic_vector(63 downto 0);
s_axis_data_tvalid : in std_logic;
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
m_axis_data_tdata : out std_logic_vector(63 downto 0);
m_axis_data_tuser : out std_logic_vector(15 downto 0);
m_axis_data_tvalid : out std_logic;
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
event_frame_started : out std_logic;
event_tlast_unexpected : out std_logic;
event_tlast_missing : out std_logic;
event_status_channel_halt : out std_logic;
event_data_in_channel_halt : out std_logic;
event_data_out_channel_halt : out std_logic);
end component;
component add_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(15 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tready : out std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(15 downto 0));
end component;
component multiply_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(15 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tready : out std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(15 downto 0));
end component;
component sqrt_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(15 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(15 downto 0));
end component;
component gteq_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(47 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tready : out std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(47 downto 0));
end component;
component edge_detect is
generic (
EDGE : string := "R"); -- "R"ising, "F"alling, "B"oth, or "N"one.
port (
clk : in std_logic; -- Clock
reset : in std_logic; -- Active high reset
input_detect : in std_logic; -- Input data
edge_detect_stb : out std_logic); -- Edge detected strobe
end component;
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
type slv_256x32 is array(0 to 255) of std_logic_vector(31 downto 0);
signal ctrl_reg : slv_256x32 := (others=>(others=>'0'));
signal status_reg : slv_256x32 := (others=>(others=>'0'));
signal ctrl_stb_dly : std_logic;
signal axis_master_tdest_hold : std_logic_vector(2 downto 0);
signal axis_master_tdest_safe : std_logic_vector(2 downto 0);
signal rst : std_logic;
signal enable_fft : std_logic;
signal config_tvalid : std_logic;
signal config_tdata : std_logic_vector(23 downto 0);
signal output_mode : std_logic_vector(1 downto 0);
signal output_mode_safe : std_logic_vector(1 downto 0);
signal enable_threshold_irq : std_logic;
signal clear_threshold_latched : std_logic;
signal enable_thresh_sideband : std_logic;
signal enable_not_thresh_sideband : std_logic;
signal index_fft : std_logic_vector(15 downto 0);
signal axis_slave_tvalid_fft : std_logic;
signal axis_slave_tready_fft : std_logic;
signal axis_master_tdata_fft : std_logic_vector(63 downto 0);
signal axis_master_tvalid_fft : std_logic;
signal axis_master_tready_fft : std_logic;
signal axis_master_tlast_fft : std_logic;
signal axis_master_tlast_fft_dly : std_logic_vector(3 downto 0);
signal axis_config_tdata : std_logic_vector(23 downto 0);
signal axis_config_tvalid : std_logic;
signal axis_config_tready : std_logic;
signal event_frame_started : std_logic;
signal event_tlast_unexpected : std_logic;
signal event_tlast_missing : std_logic;
signal event_status_channel_halt : std_logic;
signal event_data_in_channel_halt : std_logic;
signal event_data_out_channel_halt : std_logic;
signal index_real_sqr : std_logic_vector(15 downto 0);
signal axis_real_tready : std_logic;
signal axis_real_sqr_tvalid : std_logic;
signal axis_real_sqr_tready : std_logic;
signal axis_real_sqr_tdata : std_logic_vector(31 downto 0);
signal axis_real_sqr_tlast : std_logic;
signal axis_imag_sqr_tvalid : std_logic;
signal axis_imag_sqr_tready : std_logic;
signal axis_imag_sqr_tdata : std_logic_vector(31 downto 0);
signal index_mag_sqr : std_logic_vector(15 downto 0);
signal axis_mag_sqr_tlast : std_logic;
signal axis_mag_sqr_tvalid : std_logic;
signal axis_mag_sqr_tready : std_logic;
signal axis_mag_sqr_tdata : std_logic_vector(31 downto 0);
signal index_mag : std_logic_vector(15 downto 0);
signal axis_mag_tlast : std_logic;
signal axis_mag_tvalid : std_logic;
signal axis_mag_tready : std_logic;
signal axis_mag_tdata : std_logic_vector(31 downto 0);
signal axis_mag_tuser : std_logic_vector(47 downto 0);
signal index_threshold : std_logic_vector(15 downto 0);
signal threshold_mag : std_logic_vector(31 downto 0);
signal axis_threshold_tlast : std_logic;
signal axis_threshold_tvalid : std_logic;
signal axis_threshold_tready : std_logic;
signal axis_threshold_tdata : std_logic_vector(7 downto 0);
signal axis_threshold_tuser : std_logic_vector(47 downto 0);
signal threshold_latched : std_logic;
signal threshold : std_logic_vector(31 downto 0);
signal threshold_exceeded_int : std_logic;
signal threshold_exceeded_reg : std_logic;
signal threshold_exceeded_index : std_logic_vector(15 downto 0);
signal threshold_exceeded_mag : std_logic_vector(31 downto 0);
signal update_threshold_stb : std_logic;
signal fft_load : std_logic;
-- Debug signals
-- signal fft_in_real : real;
-- signal fft_in_imag : real;
-- signal fft_out_real : real;
-- signal fft_out_imag : real;
begin
rst <= NOT(rst_n);
axis_slave_irq <= '0';
-- Output AXI-S Master Signals
axis_master_tvalid <= axis_master_tvalid_fft when output_mode_safe = "00" else
axis_threshold_tvalid when output_mode_safe = "01" else
'0';
axis_master_tlast <= axis_master_tlast_fft when output_mode_safe = "00" else
axis_threshold_tlast when output_mode_safe = "01" else
'0';
axis_master_tdata <= axis_master_tdata_fft when output_mode_safe = "00" else
axis_threshold_tdata(0) & (62 downto 48 => '0') & axis_threshold_tuser;
axis_master_tdest <= axis_master_tdest_safe;
inst_fft_axis : fft_axis
port map (
aclk => clk,
aresetn => rst_n,
s_axis_config_tdata => axis_config_tdata,
s_axis_config_tvalid => axis_config_tvalid,
s_axis_config_tready => axis_config_tready,
s_axis_data_tdata => axis_slave_tdata,
s_axis_data_tvalid => axis_slave_tvalid_fft,
s_axis_data_tready => axis_slave_tready_fft,
s_axis_data_tlast => axis_slave_tlast,
m_axis_data_tdata => axis_master_tdata_fft,
m_axis_data_tuser => index_fft,
m_axis_data_tvalid => axis_master_tvalid_fft,
m_axis_data_tready => axis_master_tready_fft,
m_axis_data_tlast => axis_master_tlast_fft,
event_frame_started => event_frame_started,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing,
event_status_channel_halt => event_status_channel_halt,
event_data_in_channel_halt => event_data_in_channel_halt,
event_data_out_channel_halt => event_data_out_channel_halt);
-- It is possible we may want to only detect a signal without saving the FFT output.
-- In the case that we have no destination for the FFT output, this logic overrides the
-- FFT output AXI-Stream handshaking signals tvalid and tready to make sure the FFT core
-- does not stall.
axis_slave_tvalid_fft <= axis_slave_tvalid when enable_fft = '1' AND fft_load = '1' else '0';
axis_slave_tready <= axis_slave_tready_fft AND fft_load;
axis_master_tready_fft <= axis_master_tready when output_mode_safe = "00" else
axis_real_tready when output_mode_safe = "01" else
'1';
-- Counteract Xilinx's annoying behavior to partially preload the FFT. This is not necesary
-- unless the sampling rate is high enough that FFT takes longer to execute than it takes
-- to buffer the samples.
proc_fft_load : process(clk,rst_n)
begin
if (rst_n = '0') then
fft_load <= '1';
else
if rising_edge(clk) then
if (enable_fft = '1') then
if (fft_load = '1' AND axis_slave_tlast = '1' AND axis_slave_tvalid = '1') then
fft_load <= '0';
end if;
if (fft_load = '0' AND axis_master_tlast_fft = '1' AND axis_master_tvalid_fft = '1') then
fft_load <= '1';
end if;
-- Reset on error
if (event_tlast_missing = '1' OR event_tlast_unexpected = '1') then
fft_load <= '1';
end if;
else
fft_load <= '1';
end if;
end if;
end if;
end process;
real_squared_multiply_floating_point : multiply_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_master_tvalid_fft,
s_axis_a_tready => axis_real_tready,
s_axis_a_tdata => axis_master_tdata_fft(31 downto 0),
s_axis_a_tlast => axis_master_tlast_fft,
s_axis_a_tuser => index_fft,
s_axis_b_tvalid => axis_master_tvalid_fft,
s_axis_b_tready => open,
s_axis_b_tdata => axis_master_tdata_fft(31 downto 0),
m_axis_result_tvalid => axis_real_sqr_tvalid,
m_axis_result_tready => axis_real_sqr_tready,
m_axis_result_tdata => axis_real_sqr_tdata,
m_axis_result_tlast => axis_real_sqr_tlast,
m_axis_result_tuser => index_real_sqr);
imag_squared_multiply_floating_point : multiply_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_master_tvalid_fft,
s_axis_a_tready => open,
s_axis_a_tdata => axis_master_tdata_fft(63 downto 32),
s_axis_a_tlast => '0',
s_axis_a_tuser => (others=>'0'),
s_axis_b_tvalid => axis_master_tvalid_fft,
s_axis_b_tready => open,
s_axis_b_tdata => axis_master_tdata_fft(63 downto 32),
m_axis_result_tvalid => axis_imag_sqr_tvalid,
m_axis_result_tready => axis_imag_sqr_tready,
m_axis_result_tdata => axis_imag_sqr_tdata,
m_axis_result_tlast => open,
m_axis_result_tuser => open);
magnitude_squared_add_floating_point : add_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_real_sqr_tvalid,
s_axis_a_tready => axis_real_sqr_tready,
s_axis_a_tdata => axis_real_sqr_tdata,
s_axis_a_tlast => axis_real_sqr_tlast,
s_axis_a_tuser => index_real_sqr,
s_axis_b_tvalid => axis_imag_sqr_tvalid,
s_axis_b_tready => axis_imag_sqr_tready,
s_axis_b_tdata => axis_imag_sqr_tdata,
m_axis_result_tvalid => axis_mag_sqr_tvalid,
m_axis_result_tready => axis_mag_sqr_tready,
m_axis_result_tdata => axis_mag_sqr_tdata,
m_axis_result_tlast => axis_mag_sqr_tlast,
m_axis_result_tuser => index_mag_sqr);
magnitude_sqrt_floating_point : sqrt_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_mag_sqr_tvalid,
s_axis_a_tready => axis_mag_sqr_tready,
s_axis_a_tdata => axis_mag_sqr_tdata,
s_axis_a_tlast => axis_mag_sqr_tlast,
s_axis_a_tuser => index_mag_sqr,
m_axis_result_tvalid => axis_mag_tvalid,
m_axis_result_tready => axis_mag_tready,
m_axis_result_tdata => axis_mag_tdata,
m_axis_result_tlast => axis_mag_tlast,
m_axis_result_tuser => index_mag);
threshold_gteq_floating_point : gteq_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_mag_tvalid,
s_axis_a_tready => axis_mag_tready,
s_axis_a_tdata => axis_mag_tdata,
s_axis_a_tlast => axis_mag_tlast,
s_axis_a_tuser => axis_mag_tuser,
s_axis_b_tvalid => axis_mag_tvalid,
s_axis_b_tready => open,
s_axis_b_tdata => threshold,
m_axis_result_tvalid => axis_threshold_tvalid,
m_axis_result_tready => axis_threshold_tready,
m_axis_result_tdata => axis_threshold_tdata,
m_axis_result_tlast => axis_threshold_tlast,
m_axis_result_tuser => axis_threshold_tuser);
axis_mag_tuser <= index_mag & axis_mag_tdata;
axis_threshold_tready <= axis_master_tready when output_mode_safe = "01" else
'1';
threshold_mag <= axis_threshold_tuser(31 downto 0);
index_threshold <= axis_threshold_tuser(47 downto 32);
-- TODO: Restructuring this code could give up to a 15% reduction in the latency of reporting threshold
-- exceeded. Right now threshold exceeded is updated at the end of a FFT cycle, mostly to
-- support the threshold not exceeded cases. Allowing it to update as soon as the threshold is
-- exceeded can provide a speed up. The threshold not exceeded logic will have to be changed
-- though.
proc_latch_threshold : process(clk,enable_fft)
begin
if (enable_fft = '0') then
threshold_latched <= '0';
threshold_exceeded_int <= '0';
threshold_exceeded_reg <= '0';
threshold_exceeded <= '0';
threshold_exceeded_stb <= '0';
threshold_not_exceeded <= '0';
threshold_not_exceeded_stb <= '0';
threshold_exceeded_index <= (others=>'0');
threshold_exceeded_mag <= (others=>'0');
axis_master_irq <= '0';
else
if rising_edge(clk) then
-- If the threshold is exceeded, latch the magnitude and index. This can be updated
if (axis_threshold_tvalid = '1' AND axis_threshold_tdata(0) = '1' AND threshold_latched = '0') then
threshold_latched <= '1';
threshold_exceeded_int <= '1';
threshold_exceeded_index <= index_threshold;
threshold_exceeded_mag <= threshold_mag;
end if;
-- Set sideband signals at the end of every frame based on the threshold exceeded state
if (update_threshold_stb = '1') then
-- Update threshold exceeded status register
threshold_exceeded_reg <= threshold_exceeded_int;
-- IRQ
if (enable_threshold_irq = '1') then
axis_master_irq <= threshold_exceeded_int;
end if;
-- Exceeds threshold
if (enable_thresh_sideband = '1') then
threshold_exceeded <= threshold_exceeded_int;
threshold_exceeded_stb <= threshold_exceeded_int;
end if;
-- Not Exceed Threshold
if (enable_not_thresh_sideband = '1') then
threshold_not_exceeded <= NOT(threshold_exceeded_int);
threshold_not_exceeded_stb <= NOT(threshold_exceeded_int);
end if;
else
axis_master_irq <= '0';
threshold_exceeded_stb <= '0';
threshold_not_exceeded_stb <= '0';
end if;
-- Reset threshold exceeded on start of a new frame
if (update_threshold_stb = '1' AND clear_threshold_latched = '1') then
threshold_latched <= '0';
threshold_exceeded_int <= '0';
end if;
end if;
end if;
end process;
update_threshold_edge_detect : edge_detect
generic map (
EDGE => "R")
port map (
clk => clk,
reset => rst,
input_detect => axis_threshold_tlast,
edge_detect_stb => update_threshold_stb);
-------------------------------------------------------------------------------
-- Control and status registers.
-------------------------------------------------------------------------------
proc_ctrl_status_reg : process(clk,rst_n)
begin
if (rst_n = '0') then
ctrl_stb_dly <= '0';
ctrl_reg <= (others=>(others=>'0'));
axis_master_tdest_safe <= (others=>'0');
output_mode_safe <= (others=>'0');
else
if rising_edge(clk) then
ctrl_stb_dly <= ctrl_stb;
-- Update control registers only when accelerator 0 is accessed
if (ctrl_stb = '1') then
ctrl_reg(to_integer(unsigned(ctrl_addr(7 downto 0)))) <= ctrl_data;
end if;
-- Output status register
if (status_stb = '1') then
status_data <= status_reg(to_integer(unsigned(status_addr(7 downto 0))));
end if;
-- The destination should only update when no data is being transmitted over the AXI bus.
if (enable_fft = '0') then
axis_master_tdest_safe <= axis_master_tdest_hold;
end if;
-- We can only update the mode when the FFT is complete or disabled. This prevents mode switches in the middle
-- of a AXI transfer which may corrupt it.
if (update_threshold_stb = '1' OR enable_fft = '0') then
output_mode_safe <= output_mode;
end if;
end if;
end if;
end process;
-- Control Registers
-- Bank 0 (Enable FFT and destination)
enable_fft <= ctrl_reg(0)(0);
axis_master_tdest_hold <= ctrl_reg(0)(31 downto 29);
-- Bank 1 (FFT Configuration)
axis_config_tdata <= "000" & "000000000000" & '1' & "000" & ctrl_reg(1)(4 downto 0);
axis_config_tvalid <= '1' when (ctrl_addr = std_logic_vector(to_unsigned(1,8)) AND
ctrl_reg(1)(5) = '1' AND ctrl_stb_dly = '1') else
'0';
-- output_mode: 00 - Normal FFT frequency output
-- 01 - Threshold result, Index, & Magnitude
-- 10,11 - Discard output. Useful for running the FFT when we only want to trigger on
-- the threshold being exceeded without having to send the FFT output somewhere.
output_mode <= ctrl_reg(1)(9 downto 8);
enable_threshold_irq <= ctrl_reg(1)(10);
enable_thresh_sideband <= ctrl_reg(1)(11);
enable_not_thresh_sideband <= ctrl_reg(1)(12);
clear_threshold_latched <= ctrl_reg(1)(13);
-- Bank 2 (Theshold value)
threshold <= ctrl_reg(2)(31 downto 0);
-- Status Registers
-- Bank 0 (Enable FFT and destination Readback)
status_reg(0)(0) <= enable_fft;
status_reg(0)(31 downto 29) <= axis_master_tdest_safe;
-- Bank 1 (FFT Configuration Readback)
status_reg(1)(4 downto 0) <= axis_config_tdata(4 downto 0);
status_reg(1)(5) <= axis_config_tvalid;
status_reg(1)(9 downto 8) <= output_mode_safe;
status_reg(1)(10) <= enable_threshold_irq;
status_reg(1)(11) <= enable_thresh_sideband;
status_reg(1)(12) <= enable_not_thresh_sideband;
status_reg(1)(13) <= clear_threshold_latched;
-- Bank 2 (Theshold comparison value)
status_reg(2)(31 downto 0) <= threshold;
-- Bank 3 (Threshold exceeded index and flag)
status_reg(3)(15 downto 0) <= threshold_exceeded_index;
status_reg(3)(31) <= threshold_exceeded_reg;
-- Bank 4 (Magnitude that exceeded the threshold)
status_reg(4)(31 downto 0) <= threshold_exceeded_mag;
-- Debug
-- fft_in_real <= float2real(axis_slave_tdata(63 downto 32));
-- fft_in_imag <= float2real(axis_slave_tdata(31 downto 0));
-- fft_out_real <= float2real(axis_master_tdata_fft(63 downto 32));
-- fft_out_imag <= float2real(axis_master_tdata_fft(31 downto 0));
end architecture; | gpl-3.0 | a474bc8aea8607d1d18a08fcb784511a | 0.505004 | 4.010297 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/slot_slave.vhd | 1 | 13,959 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity slot_slave is
generic (
g_big_endian : boolean );
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
VCC : in std_logic;
RSTn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
ROMLn : in std_logic;
ROMHn : in std_logic;
BA : in std_logic;
GAMEn : in std_logic;
EXROMn : in std_logic;
RWn : in std_logic;
ADDRESS : in unsigned(15 downto 0);
DATA_in : in std_logic_vector(7 downto 0);
DATA_out : out std_logic_vector(7 downto 0) := (others => '0');
DATA_tri : out std_logic;
-- interface with memory controller
mem_req : out std_logic; -- our memory request to serve slot
mem_rwn : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_rdata : in std_logic_vector(31 downto 0);
mem_wdata : out std_logic_vector(31 downto 0);
-- mem_addr comes from cartridge logic
reset_out : out std_logic;
-- timing inputs
phi2_tick : in std_logic;
do_sample_addr : in std_logic;
do_probe_end : in std_logic;
do_sample_io : in std_logic;
do_io_event : in std_logic;
dma_active_n : in std_logic := '1';
-- interface with freezer (cartridge) logic
allow_serve : in std_logic := '0'; -- from timing unit (modified version of serve_enable)
serve_128 : in std_logic := '0';
serve_rom : in std_logic := '0'; -- ROML or ROMH
serve_io1 : in std_logic := '0'; -- IO1n
serve_io2 : in std_logic := '0'; -- IO2n
allow_write : in std_logic := '0';
kernal_enable : in std_logic := '0';
kernal_probe : out std_logic := '0';
kernal_area : out std_logic := '0';
force_ultimax : out std_logic := '0';
epyx_timeout : out std_logic; -- '0' => epyx is on, '1' epyx is off
cpu_write : out std_logic; -- for freezer
slot_req : out t_slot_req;
slot_resp : in t_slot_resp;
-- interface with hardware
BUFFER_ENn : out std_logic );
end slot_slave;
architecture gideon of slot_slave is
signal address_c : unsigned(15 downto 0) := (others => '0');
signal data_c : std_logic_vector(7 downto 0) := X"FF";
signal io1n_c : std_logic := '1';
signal io2n_c : std_logic := '1';
signal rwn_c : std_logic := '1';
signal romhn_c : std_logic := '1';
signal romln_c : std_logic := '1';
signal ba_c : std_logic := '0';
signal dav : std_logic := '0';
signal addr_is_io : boolean;
signal addr_is_kernal : std_logic;
signal mem_req_ff : std_logic;
signal servicable : std_logic;
signal io_out : boolean := false;
signal io_read_cond : std_logic;
signal io_write_cond: std_logic;
signal late_write_cond : std_logic;
signal ultimax : std_logic;
signal ultimax_d : std_logic := '0';
signal ultimax_d2 : std_logic := '0';
signal last_rwn : std_logic;
signal mem_wdata_i : std_logic_vector(7 downto 0);
signal kernal_probe_i : std_logic;
signal kernal_area_i : std_logic;
signal mem_data_0 : std_logic_vector(7 downto 0) := X"00";
signal mem_data_1 : std_logic_vector(7 downto 0) := X"00";
signal data_mux : std_logic;
attribute register_duplication : string;
attribute register_duplication of rwn_c : signal is "no";
attribute register_duplication of io1n_c : signal is "no";
attribute register_duplication of io2n_c : signal is "no";
attribute register_duplication of romln_c : signal is "no";
attribute register_duplication of romhn_c : signal is "no";
attribute register_duplication of reset_out : signal is "no";
type t_state is (idle, mem_access, wait_end, reg_out);
attribute iob : string;
attribute iob of data_c : signal is "true";
signal state : t_state;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
signal epyx_timer : natural range 0 to 511;
signal epyx_reset : std_logic := '0';
begin
slot_req.io_write <= do_io_event and io_write_cond;
slot_req.io_read <= do_io_event and io_read_cond;
slot_req.late_write <= do_io_event and late_write_cond;
-- TODO: Do we still need io_read_early? If so, should we not check for PHI2 here? Or will we serve I/O data to the VIC?
slot_req.io_read_early <= '1' when (addr_is_io and rwn_c='1' and do_sample_addr='1') else '0';
slot_req.sample_io <= do_sample_io;
process(clock)
begin
if rising_edge(clock) then
-- synchronization
if mem_req_ff='0' then -- don't change while an access is taking place
rwn_c <= RWn;
address_c <= ADDRESS;
end if;
reset_out <= reset or (not RSTn and VCC);
ba_c <= BA;
io1n_c <= IO1n;
io2n_c <= IO2n;
romln_c <= ROMLn;
romhn_c <= ROMHn;
data_c <= DATA_in;
ultimax <= not GAMEn and EXROMn;
ultimax_d <= ultimax;
ultimax_d2 <= ultimax_d;
slot_req.rom_access <= not romln_c or not romhn_c;
-- 470 nF / 3.3K pup / Vih = 2V, but might be lower
-- Voh buffer = 0.3V, so let's take a threshold of 1.2V => 400 cycles
-- Now implemented: 512
if epyx_reset='1' then
epyx_timer <= 511;
epyx_timeout <= '0';
elsif phi2_tick='1' and dma_active_n = '1' then
if epyx_timer = 0 then
epyx_timeout <= '1';
else
epyx_timer <= epyx_timer - 1;
end if;
end if;
slot_req.bus_write <= '0';
if do_sample_io='1' then
cpu_write <= not RWn;
slot_req.bus_write <= not RWn;
slot_req.io_address <= address_c;
mem_wdata_i <= data_c;
late_write_cond <= not rwn_c;
io_write_cond <= not rwn_c and (not io2n_c or not io1n_c);
io_read_cond <= rwn_c and (not io2n_c or not io1n_c);
epyx_reset <= not io1n_c or not romln_c or not RSTn;
end if;
if do_probe_end='1' then
data_mux <= kernal_probe_i and not romhn_c;
force_ultimax <= kernal_probe_i;
kernal_probe_i <= '0';
elsif do_io_event='1' then
force_ultimax <= '0';
end if;
case state is
when idle =>
if do_sample_addr='1' then
-- register output
-- TODO: Should we not check for PHI2 here? Or will we serve I/O data to the VIC?
if slot_resp.reg_output='1' and addr_is_io and rwn_c='1' then -- read register
mem_data_0 <= slot_resp.data;
io_out <= true;
dav <= '1';
state <= reg_out;
elsif allow_serve='1' and servicable='1' and rwn_c='1' then
io_out <= false;
-- memory read
if kernal_enable='1' and ultimax='0' and addr_is_kernal='1' and ba_c='1' then
kernal_probe_i <= '1';
kernal_area_i <= '1';
end if;
if addr_is_io then
--if ba_c='1' then -- only serve IO when BA='1' (Fix for Ethernet)
mem_req_ff <= '1';
state <= mem_access;
--end if;
if address_c(8)='0' and serve_io1='1' then
io_out <= (rwn_c='1');
elsif address_c(8)='1' and serve_io2='1' then
io_out <= (rwn_c='1');
end if;
else -- non-IO, always serve
mem_req_ff <= '1';
state <= mem_access;
end if;
end if;
elsif do_sample_io='1' and rwn_c='0' then
if allow_write='1' then
-- memory write
if address_c(15 downto 12)=X"D" then -- IO range
if io2n_c='0' or io1n_c='0' then
mem_req_ff <= '1';
state <= mem_access;
end if;
else
mem_req_ff <= '1';
state <= mem_access;
end if;
elsif kernal_enable='1' and addr_is_kernal='1' then
-- do mirror to kernal write address
mem_req_ff <= '1';
state <= mem_access;
kernal_area_i <= '1';
end if;
end if;
when mem_access =>
if mem_rack='1' then
mem_req_ff <= '0'; -- clear request
if rwn_c='0' then -- if write, we're done.
kernal_area_i <= '0';
state <= idle;
else -- if read, then we need to wait for the data
state <= wait_end;
end if;
end if;
when wait_end =>
if mem_dack='1' then -- the data is available, put it on the bus!
if g_big_endian then
mem_data_0 <= mem_rdata(31 downto 24);
mem_data_1 <= mem_rdata(23 downto 16);
else
mem_data_0 <= mem_rdata(7 downto 0);
mem_data_1 <= mem_rdata(15 downto 8);
end if;
dav <= '1';
end if;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
kernal_area_i <= '0';
state <= idle;
io_out <= false;
dav <= '0';
end if;
when reg_out =>
mem_data_0 <= slot_resp.data;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
state <= idle;
io_out <= false;
dav <= '0';
end if;
when others =>
null;
end case;
if (kernal_area_i='1') then
DATA_tri <= not romhn_c and ultimax_d2 and rwn_c;
elsif (io_out and (io1n_c='0' or io2n_c='0')) or
((romln_c='0' or romhn_c='0') and (rwn_c='1')) then
DATA_tri <= mem_dack or dav;
else
DATA_tri <= '0';
end if;
if reset='1' then
data_mux <= '0';
last_rwn <= '1';
dav <= '0';
state <= idle;
mem_req_ff <= '0';
io_out <= false;
io_read_cond <= '0';
io_write_cond <= '0';
late_write_cond <= '0';
slot_req.io_address <= (others => '0');
cpu_write <= '0';
epyx_reset <= '1';
kernal_probe_i <= '0';
kernal_area_i <= '0';
force_ultimax <= '0';
end if;
end if;
end process;
-- combinatoric
addr_is_io <= (address_c(15 downto 9)="1101111"); -- DE/DF
addr_is_kernal <= '1' when (address_c(15 downto 13)="111") else '0';
process(rwn_c, address_c, addr_is_io, romln_c, romhn_c, serve_128, serve_rom, serve_io1, serve_io2, ultimax, kernal_enable, ba_c)
begin
servicable <= '0';
if rwn_c='1' then
if addr_is_io and (serve_io1='1' or serve_io2='1') then
servicable <= '1';
end if;
if address_c(15)='1' and serve_128='1' then -- 8000-FFFF
servicable <= '1';
end if;
if address_c(15 downto 14)="10" and (serve_rom='1') then -- 8000-BFFF
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (serve_rom='1') and (ultimax='1') then
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (kernal_enable='1') and (ba_c='1') then
servicable <= '1';
end if;
end if;
end process;
mem_req <= mem_req_ff;
mem_rwn <= rwn_c;
mem_wdata <= mem_wdata_i & X"0000" & mem_wdata_i; -- support both little endian as well as big endian
BUFFER_ENn <= '0';
DATA_out <= mem_data_0 when data_mux='0' else mem_data_1;
slot_req.data <= mem_wdata_i;
slot_req.bus_address <= unsigned(address_c(15 downto 0));
slot_req.bus_rwn <= rwn_c;
kernal_probe <= kernal_probe_i;
kernal_area <= kernal_area_i;
end gideon;
| gpl-3.0 | 5635564953b587dfdaca68c90cedb0dd | 0.448026 | 3.653232 | false | false | false | false |
trondd/mkjpeg | design/quantizer/QUANTIZER.vhd | 2 | 5,290 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : DCT QUANTIZER --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : QUANTIZER.VHD --
-- Created : Sun Aug 27 2006 --
-- --
--------------------------------------------------------------------------------
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity quantizer is
generic
(
SIZE_C : INTEGER := 12;
RAMQADDR_W : INTEGER := 7;
RAMQDATA_W : INTEGER := 8
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
divalid : in STD_LOGIC;
qdata : in std_logic_vector(7 downto 0);
qwaddr : in std_logic_vector(6 downto 0);
qwren : in std_logic;
cmp_idx : in unsigned(2 downto 0);
do : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
dovalid : out STD_LOGIC
);
end quantizer;
architecture rtl of quantizer is
constant INTERN_PIPE_C : INTEGER := 3;
signal romaddr_s : UNSIGNED(RAMQADDR_W-2 downto 0);
signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0);
signal romdatao_s : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0);
signal divisor_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal remainder_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal do_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal round_s : STD_LOGIC;
signal di_d1 : std_logic_vector(SIZE_C-1 downto 0);
signal pipeline_reg : STD_LOGIC_VECTOR(4 downto 0);
signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0);
signal do_rdiv : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal table_select : std_logic;
begin
----------------------------
-- RAMQ
----------------------------
U_RAMQ : entity work.RAMZ
generic map
(
RAMADDR_W => RAMQADDR_W,
RAMDATA_W => RAMQDATA_W
)
port map
(
d => qdata,
waddr => qwaddr,
raddr => slv_romaddr_s,
we => qwren,
clk => CLK,
q => romdatao_s
);
divisor_s(RAMQDATA_W-1 downto 0) <= romdatao_s;
divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0');
r_divider : entity work.r_divider
port map
(
rst => rst,
clk => clk,
a => di_d1,
d => romdatao_s,
q => do_s
) ;
do <= do_s;
slv_romaddr_s <= table_select & STD_LOGIC_VECTOR(romaddr_s);
------------------------------
-- Quantization sub table select
------------------------------
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
table_select <= '0';
else
-- luminance table select
if cmp_idx < 2 then
table_select <= '0';
-- chrominance table select
else
table_select <= '1';
end if;
end if;
end if;
end process;
----------------------------
-- address incrementer
----------------------------
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
romaddr_s <= (others => '0');
pipeline_reg <= (OTHERS => '0');
di_d1 <= (OTHERS => '0');
sign_bit_pipe <= (others => '0');
else
if divalid = '1' then
romaddr_s <= romaddr_s + TO_UNSIGNED(1,romaddr_s'length);
end if;
pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid;
di_d1 <= di;
sign_bit_pipe <= sign_bit_pipe(sign_bit_pipe'length-2 downto 0) & di(SIZE_C-1);
end if;
end if;
end process;
dovalid <= pipeline_reg(pipeline_reg'high);
end rtl;
-------------------------------------------------------------------------------- | lgpl-3.0 | 5e3864e2333be1500e54612cd96d0948 | 0.354064 | 4.608014 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/submodules/avalon_pwm_interface.m.vhd | 1 | 10,023 | -------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Avalon MM interface for PWM --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE avalon_pwm_interface_pkg IS
CONSTANT c_max_number_of_PWMs : INTEGER := 16; --Depens off the address with and the number of registers per pwm
CONSTANT c_pwm_interface_address_width : INTEGER := 6;
COMPONENT avalon_pwm_interface IS
GENERIC (
number_of_pwms: INTEGER RANGE 0 TO c_max_number_of_PWMs := 1;
base_clk: INTEGER := 125000000;
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_pwm_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_pwm : OUT STD_LOGIC_VECTOR(number_of_pwms-1 DOWNTO 0)
);
END COMPONENT;
CONSTANT c_pwm_subtype_id : INTEGER := 0;
CONSTANT c_pwm_interface_version : INTEGER := 0;
END PACKAGE avalon_pwm_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.adjustable_pwm_pkg.ALL;
USE work.avalon_pwm_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
ENTITY avalon_pwm_interface IS
GENERIC (
number_of_pwms: INTEGER RANGE 0 TO c_max_number_of_PWMs := 1;
base_clk: INTEGER := 125000000;
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_pwm_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_pwm : OUT STD_LOGIC_VECTOR(number_of_pwms-1 DOWNTO 0)
);
CONSTANT c_usig_base_clk_address : UNSIGNED(c_pwm_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers, c_pwm_interface_address_width);
CONSTANT c_usig_frequency_address : UNSIGNED(c_pwm_interface_address_width-1 DOWNTO 0) := c_usig_base_clk_address + 1;
CONSTANT c_usig_ratio_address : UNSIGNED(c_pwm_interface_address_width-1 DOWNTO 0) := c_usig_frequency_address + number_of_pwms;
CONSTANT c_usig_max_address : UNSIGNED(c_pwm_interface_address_width-1 DOWNTO 0) := c_usig_ratio_address + number_of_pwms;
END ENTITY avalon_pwm_interface;
ARCHITECTURE rtl OF avalon_pwm_interface IS
Type t_pwm_regs IS ARRAY(number_of_pwms-1 DOWNTO 0) OF UNSIGNED(c_fLink_avs_data_width-1 DOWNTO 0);
TYPE t_internal_register IS RECORD
frequency_regs : t_pwm_regs;
ratio_regs : t_pwm_regs;
conf_reg : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
END RECORD;
SIGNAL pwm_reset_n : STD_LOGIC;
SIGNAL ri,ri_next : t_internal_register;
BEGIN
gen_pwm:
FOR i IN 0 TO number_of_pwms-1 GENERATE
my_adjustable_pwm : adjustable_pwm
GENERIC MAP (frequency_resolution =>c_fLink_avs_data_width)
PORT MAP (isl_clk,pwm_reset_n,ri.frequency_regs(i),ri.ratio_regs(i),oslv_pwm(i));
END GENERATE gen_pwm;
-- combinatorial process
comb_proc : PROCESS (isl_reset_n,ri,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data,islv_avs_byteenable)
VARIABLE vi : t_internal_register;
BEGIN
-- keep variables stable
vi := ri;
--standard values
oslv_avs_read_data <= (OTHERS => '0');
pwm_reset_n <= '1';
--avalon slave interface write part
IF isl_avs_write = '1' THEN
IF UNSIGNED(islv_avs_address) = to_unsigned(c_fLink_configuration_address,c_pwm_interface_address_width) THEN
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.conf_reg((i + 1) * 8 - 1 DOWNTO i * 8) := islv_avs_write_data((i + 1) * 8 - 1 DOWNTO i * 8);
END IF;
END LOOP;
ELSIF UNSIGNED(islv_avs_address)>= c_usig_frequency_address AND UNSIGNED(islv_avs_address)< c_usig_ratio_address THEN
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.frequency_regs(to_integer(UNSIGNED(islv_avs_address)-c_usig_frequency_address))((i + 1) * 8 - 1 DOWNTO i * 8) := UNSIGNED(islv_avs_write_data((i + 1) * 8 - 1 DOWNTO i * 8));
END IF;
END LOOP;
ELSIF UNSIGNED(islv_avs_address)>= c_usig_ratio_address AND UNSIGNED(islv_avs_address)< c_usig_max_address THEN
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.ratio_regs(to_integer(UNSIGNED(islv_avs_address)-c_usig_ratio_address))((i + 1) * 8 - 1 DOWNTO i * 8) := UNSIGNED(islv_avs_write_data((i + 1) * 8 - 1 DOWNTO i * 8));
END IF;
END LOOP;
END IF;
END IF;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE UNSIGNED(islv_avs_address) IS
WHEN to_unsigned(c_fLink_typdef_address,c_pwm_interface_address_width) =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_pwm_out_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= STD_LOGIC_VECTOR(to_unsigned(c_pwm_subtype_id,c_fLink_subtype_length));
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(c_pwm_interface_version,c_fLink_interface_version_length));
WHEN to_unsigned(c_fLink_mem_size_address,c_pwm_interface_address_width) =>
oslv_avs_read_data(c_pwm_interface_address_width+2) <= '1';
WHEN to_unsigned(c_fLink_number_of_channels_address,c_pwm_interface_address_width) =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(number_of_pwms,c_fLink_avs_data_width));
WHEN to_unsigned(c_fLink_configuration_address,c_pwm_interface_address_width) =>
oslv_avs_read_data <= vi.conf_reg;
WHEN to_unsigned(c_fLink_unique_id_address,c_pwm_interface_address_width) =>
oslv_avs_read_data <= unique_id;
WHEN c_usig_base_clk_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(base_clk,c_fLink_avs_data_width));
WHEN OTHERS =>
IF UNSIGNED(islv_avs_address)>= c_usig_frequency_address AND UNSIGNED(islv_avs_address)< c_usig_ratio_address THEN
oslv_avs_read_data <= STD_LOGIC_VECTOR(vi.frequency_regs(to_integer(UNSIGNED(islv_avs_address)-c_usig_frequency_address)));
ELSIF UNSIGNED(islv_avs_address)>= c_usig_ratio_address AND UNSIGNED(islv_avs_address)< c_usig_max_address THEN
oslv_avs_read_data <= STD_LOGIC_VECTOR(vi.ratio_regs(to_integer(UNSIGNED(islv_avs_address)-c_usig_ratio_address)));
ELSE
oslv_avs_read_data <= (OTHERS => '0');
END IF;
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.conf_reg(c_fLink_reset_bit_num) = '1' THEN
vi.conf_reg := (OTHERS =>'0');
pwm_reset_n <= '0';
FOR i IN 0 TO number_of_pwms-1 LOOP
vi.frequency_regs(i) := (OTHERS => '0');
vi.ratio_regs(i) := (OTHERS => '1');
END LOOP;
END IF;
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
| apache-2.0 | 7634e3f459c0cbc082e474d2ddb523b4 | 0.583757 | 3.191022 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/dpram.vhd | 1 | 3,599 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := true;
g_read_first_b : boolean := true;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
a_clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_clock : in std_logic := '0';
b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0');
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
end entity;
architecture xilinx of dpram is
function string_select(a,b: string; s:boolean) return string is
begin
if s then
return a;
end if;
return b;
end function;
-- Error (14271): Illegal value NEW_DATA for port_a_read_during_write_mode parameter in WYSIWYG primitive "ram_block1a0" -- value must be new_data_no_nbe_read, new_data_with_nbe_read or old_data
constant a_new_data : string := string_select("OLD_DATA", "new_data_with_nbe_read", g_read_first_a);
constant b_new_data : string := string_select("OLD_DATA", "new_data_with_nbe_read", g_read_first_b);
signal wren_a : std_logic;
signal wren_b : std_logic;
begin
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 2 ** g_depth_bits,
numwords_b => 2 ** g_depth_bits,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => g_depth_bits,
widthad_b => g_depth_bits,
width_a => g_width_bits,
width_b => g_width_bits,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => std_logic_vector(a_address),
address_b => std_logic_vector(b_address),
clock0 => a_clock,
clock1 => b_clock,
data_a => a_wdata,
data_b => b_wdata,
rden_a => a_en,
rden_b => b_en,
wren_a => wren_a,
wren_b => wren_b,
q_a => a_rdata,
q_b => b_rdata );
wren_a <= a_we and a_en;
wren_b <= b_we and b_en;
end architecture;
| gpl-3.0 | ead9100fa13d110b26538b664a7c748a | 0.513754 | 3.357276 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/watchdog/cb20/synthesis/cb20_info_device_0_avalon_slave_translator.vhd | 1 | 14,655 | -- cb20_info_device_0_avalon_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 5;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(4 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_info_device_0_avalon_slave_translator;
architecture rtl of cb20_info_device_0_avalon_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
info_device_0_avalon_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_info_device_0_avalon_slave_translator
| apache-2.0 | 1d4491fa75edc0316fc70a9a203c53be | 0.429887 | 4.348665 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio_select/vhdl_source/audio_select.vhd | 1 | 1,725 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity audio_select is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
select_left : out std_logic_vector(3 downto 0);
select_right : out std_logic_vector(3 downto 0) );
end audio_select;
architecture gideon of audio_select is
signal left_select : std_logic_vector(3 downto 0);
signal right_select : std_logic_vector(3 downto 0);
begin
select_left <= left_select;
select_right <= right_select;
process(clock)
begin
if rising_edge(clock) then
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
left_select <= req.data(3 downto 0);
when X"1" =>
right_select <= req.data(3 downto 0);
when others =>
null;
end case;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data(3 downto 0) <= left_select;
when X"1" =>
resp.data(3 downto 0) <= right_select;
when others =>
null;
end case;
end if;
if reset='1' then
left_select <= "0000";
right_select <= "0000";
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 4d5f9aed88239b8feb4fb0808b8625ce | 0.467826 | 3.947368 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/debug/vhdl_source/usb_tracer.vhd | 1 | 5,115 | --------------------------------------------------------------------------------
-- Entity: usb_tracer
-- Date:2018-07-15
-- Author: Gideon
--
-- Description: Encodes USB data into 1480A compatible data format
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_tracer is
port (
clock : in std_logic;
reset : in std_logic;
usb_data : in std_logic_vector(7 downto 0);
usb_valid : in std_logic;
usb_rxcmd : in std_logic;
stream_out : out std_logic_vector(31 downto 0);
stream_valid: out std_logic );
end entity;
architecture arch of usb_tracer is
signal counter : unsigned(27 downto 0);
signal raw_rd : std_logic;
signal raw_wr : std_logic;
signal raw_valid : std_logic;
signal raw_in : std_logic_vector(37 downto 0);
signal raw_in : std_logic_vector(37 downto 0);
signal enc16 : std_logic_vector(15 downto 0);
signal enc16_push : std_logic;
type t_state is (idle, ext1, format1, format3a, format3b);
signal state, next_state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
raw_wr <= '0';
if usb_valid = '1' then
raw_in <= '0' & usb_rxcmd & usb_data & std_logic_vector(counter);
raw_wr <= '1';
counter <= to_unsigned(1, counter'length);
elsif counter = X"FFFFFFF" then
raw_in <= "10" & X"00" & std_logic_vector(counter);
raw_wr <= '1';
counter <= to_unsigned(1, counter'length);
else
counter <= counter + 1;
end if;
if reset = '1' then
counter <= (others => '0');
end if;
end if;
end process;
i_raw_fifo: entity work.sync_fifo
generic map(
g_depth => 15,
g_data_width => 38,
g_threshold => 8,
g_storage => "auto",
g_fall_through => true
)
port map(
clock => clock,
reset => reset,
rd_en => raw_rd,
wr_en => raw_wr,
din => raw_in,
dout => raw_out,
flush => '0',
valid => raw_valid
);
p_encode: process(raw_out, raw_valid, state)
begin
next_state <= state;
enc16 <= (others => 'X');
enc16_push <= '0';
raw_rd <= '0';
case state is
when idle =>
if raw_valid = '1' then
if raw_out(37 downto 36) = "10" then
enc16 <= X"3FFF";
enc16_push <= '1';
raw_rd <= '1';
next_state <= ext1;
elsif raw_out(27 downto 4) = X"000000" then -- Format 0 feasible
enc16 <= '1' & raw_out(36) & "00" & raw_out(3 downto 0) & raw_out(35 downto 28);
enc16_push <= '1';
raw_rd <= '1';
elsif raw_out(27 downto 20) = X"000" then -- Format 1 or 2 are feasible
enc16 <= '1' & raw_out(36) & "01" & raw_out(3 downto 0) & raw_out(11 downto 4);
enc16_push <= '1';
next_state <= format1;
else
enc16 <= '1' & raw_out(36) & "11" & raw_out(3 downto 0) & raw_out(11 downto 4);
enc16_push <= '1';
next_state <= format3a;
end if;
end if;
when ext1 =>
enc16 <= X"FFFF";
enc16_push <= '1';
next_state <= idle;
when format1 =>
enc16 <= raw_out(35 downto 28) & raw_out(19 downto 12);
enc16_push <= '1';
raw_rd <= '1';
next_state <= idle;
when format3a =>
enc16 <= raw_out(19 downto 12) & raw_out(27 downto 20);
enc16_push <= '1';
next_state <= format3b;
when format3b =>
enc16 <= X"00" & raw_out(35 downto 28);
enc16_push <= '1';
raw_rd <= '1';
next_state <= idle;
when others =>
null;
end case;
end process;
process(clock)
begin
if rising_edge(clock) then
state <= next_state;
stream_valid <= '0';
if enc16_push = '1' then
if toggle = '0' then
stream_out(15 downto 0) <= enc16;
toggle <= '1';
else
stream_out(31 downto 16) <= enc16;
stream_valid <= '1';
toggle <= '0';
end if;
end if;
if reset = '1' then
state <= idle;
toggle <= '0';
stream_out <= (others => '0');
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 18414ee39c333fb5338ec31a6a9d95bb | 0.42346 | 3.913542 | false | false | false | false |
chiggs/nvc | test/regress/logical2.vhd | 4 | 1,158 | entity logical2 is
end entity;
architecture test of logical2 is
signal x : bit;
signal one : bit := '1';
signal zero : bit := '0';
begin
process is
begin
x <= '0';
wait for 1 ns;
assert (x and zero) = zero;
assert (x and one) = zero;
assert (x or zero) = zero;
assert (x or one) = one;
assert (x xor zero) = zero;
assert (x xor one) = one;
assert (x xnor zero) = one;
assert (x xnor one) = zero;
assert (x nand zero) = one;
assert (x nand one) = one;
assert (x nor zero) = one;
assert (x nor one) = zero;
x <= '1';
wait for 1 ns;
assert (x and zero) = zero;
assert (x and one) = one;
assert (x or zero) = one;
assert (x or one) = one;
assert (x xor zero) = one;
assert (x xor one) = zero;
assert (x xnor zero) = zero;
assert (x xnor one) = one;
assert (x nand zero) = one;
assert (x nand one) = zero;
assert (x nor zero) = zero;
assert (x nor one) = zero;
wait;
end process;
end architecture;
| gpl-3.0 | d67e364cc0161201f9873d404537d971 | 0.495682 | 3.552147 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/submodules/adjustable_pwm.m.vhd | 1 | 4,099 | -------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Adjustable PWM Signal Generator --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
-- Based on the PWM block of Marco Tinner from the AirBotOne project
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE adjustable_pwm_pkg IS
COMPONENT adjustable_pwm IS
GENERIC(frequency_resolution : INTEGER := 32);
PORT (
sl_clk : IN STD_LOGIC;
sl_reset_n : IN STD_LOGIC;
slv_frequency_divider : IN UNSIGNED(frequency_resolution-1 DOWNTO 0);
slv_ratio : IN UNSIGNED(frequency_resolution-1 DOWNTO 0);
sl_pwm : OUT STD_LOGIC
);
END COMPONENT adjustable_pwm;
END PACKAGE adjustable_pwm_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.adjustable_pwm_pkg.ALL;
ENTITY adjustable_pwm IS
GENERIC(frequency_resolution : INTEGER := 32);
PORT (
sl_clk : IN STD_LOGIC;
sl_reset_n : IN STD_LOGIC;
slv_frequency_divider : IN UNSIGNED(frequency_resolution-1 DOWNTO 0); -- pwm frequency divider for example if this value is 2 the pwm output frequency is f_sl_clk/2
slv_ratio : IN UNSIGNED(frequency_resolution-1 DOWNTO 0); -- the high time part in clk cyles this value has alway to be smaller than the slv_frequency_divider
sl_pwm : OUT STD_LOGIC
);
END ENTITY adjustable_pwm;
ARCHITECTURE rtl OF adjustable_pwm IS
SIGNAL cycle_counter : UNSIGNED(frequency_resolution-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
proc : PROCESS (sl_reset_n,sl_clk)
BEGIN
IF sl_reset_n = '0' THEN
sl_pwm <= '0';
cycle_counter <= (OTHERS => '0');
ELSIF rising_edge(sl_clk) THEN
IF slv_ratio > slv_frequency_divider THEN
sl_pwm <= '0';
cycle_counter <= (OTHERS => '0');
ELSIF cycle_counter >= slv_frequency_divider THEN
sl_pwm <= '0';
cycle_counter <= (OTHERS => '0');
ELSIF cycle_counter < slv_ratio THEN
sl_pwm <= '1';
cycle_counter <= cycle_counter + 1;
ELSE
sl_pwm <= '0';
cycle_counter <= cycle_counter + 1;
END IF;
END IF;
END PROCESS proc;
END ARCHITECTURE rtl;
| apache-2.0 | 09582127e499770665c959bfc1359e73 | 0.441083 | 4.247668 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20_width_adapter_001.vhd | 1 | 10,454 | -- cb20_width_adapter_001.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 52;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 61;
IN_PKT_BYTE_CNT_L : integer := 59;
IN_PKT_TRANS_COMPRESSED_READ : integer := 53;
IN_PKT_BURSTWRAP_H : integer := 62;
IN_PKT_BURSTWRAP_L : integer := 62;
IN_PKT_BURST_SIZE_H : integer := 65;
IN_PKT_BURST_SIZE_L : integer := 63;
IN_PKT_RESPONSE_STATUS_H : integer := 87;
IN_PKT_RESPONSE_STATUS_L : integer := 86;
IN_PKT_TRANS_EXCLUSIVE : integer := 58;
IN_PKT_BURST_TYPE_H : integer := 67;
IN_PKT_BURST_TYPE_L : integer := 66;
IN_ST_DATA_W : integer := 88;
OUT_PKT_ADDR_H : integer := 34;
OUT_PKT_ADDR_L : integer := 18;
OUT_PKT_DATA_H : integer := 15;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 17;
OUT_PKT_BYTEEN_L : integer := 16;
OUT_PKT_BYTE_CNT_H : integer := 43;
OUT_PKT_BYTE_CNT_L : integer := 41;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 35;
OUT_PKT_BURST_SIZE_H : integer := 47;
OUT_PKT_BURST_SIZE_L : integer := 45;
OUT_PKT_RESPONSE_STATUS_H : integer := 69;
OUT_PKT_RESPONSE_STATUS_L : integer := 68;
OUT_PKT_TRANS_EXCLUSIVE : integer := 40;
OUT_PKT_BURST_TYPE_H : integer := 49;
OUT_PKT_BURST_TYPE_L : integer := 48;
OUT_ST_DATA_W : integer := 70;
ST_CHANNEL_W : integer := 7;
OPTIMIZE_FOR_RSP : integer := 1;
RESPONSE_PATH : integer := 1
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(6 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(87 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(69 downto 0); -- .data
out_channel : out std_logic_vector(6 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter_001;
architecture rtl of cb20_width_adapter_001 is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(69 downto 0); -- data
out_channel : out std_logic_vector(6 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter_001 : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter_001
| apache-2.0 | 1b8febc8f1cfc4f593c4228e22cbc05c | 0.45925 | 3.366828 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/cpu_part_1571.vhd | 1 | 20,041 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_part_1571 is
generic (
g_disk_tag : std_logic_vector(7 downto 0) := X"03";
g_cpu_tag : std_logic_vector(7 downto 0) := X"02";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
falling : in std_logic;
rising : in std_logic;
reset : in std_logic;
tick_1kHz : in std_logic;
tick_4MHz : in std_logic;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
fast_clk_o : out std_logic; -- open drain
fast_clk_i : in std_logic;
-- Debug port
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
-- memory interface
mem_req_cpu : out t_mem_req;
mem_resp_cpu : in t_mem_resp;
mem_req_disk : out t_mem_req;
mem_resp_disk : in t_mem_resp;
mem_busy : out std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic;
-- drive pins
power : in std_logic;
drive_address : in std_logic_vector(1 downto 0);
motor_on : out std_logic;
mode : out std_logic;
write_prot_n : in std_logic;
step : out std_logic_vector(1 downto 0);
rate_ctrl : out std_logic_vector(1 downto 0);
byte_ready : in std_logic;
sync : in std_logic;
rdy_n : in std_logic;
disk_change_n : in std_logic;
side : out std_logic;
two_MHz : out std_logic;
track_0 : in std_logic;
drv_rdata : in std_logic_vector(7 downto 0);
drv_wdata : out std_logic_vector(7 downto 0);
act_led : out std_logic );
end entity;
architecture structural of cpu_part_1571 is
signal motor_on_i : std_logic;
signal soe : std_logic;
signal so_n : std_logic;
signal cpu_write : std_logic;
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_addr : std_logic_vector(16 downto 0);
signal cpu_irqn : std_logic;
signal ext_rdata : std_logic_vector(7 downto 0) := X"00";
signal via1_data : std_logic_vector(7 downto 0);
signal via2_data : std_logic_vector(7 downto 0);
signal via1_wen : std_logic;
signal via1_ren : std_logic;
signal via2_wen : std_logic;
signal via2_ren : std_logic;
signal cia_data : std_logic_vector(7 downto 0);
signal cia_wen : std_logic;
signal cia_ren : std_logic;
signal wd_data : std_logic_vector(7 downto 0);
signal wd_wen : std_logic;
signal wd_ren : std_logic;
signal cia_port_a_o : std_logic_vector(7 downto 0);
signal cia_port_a_t : std_logic_vector(7 downto 0);
signal cia_port_a_i : std_logic_vector(7 downto 0);
signal cia_port_b_o : std_logic_vector(7 downto 0);
signal cia_port_b_t : std_logic_vector(7 downto 0);
signal cia_port_b_i : std_logic_vector(7 downto 0);
signal cia_sp_o : std_logic;
signal cia_sp_i : std_logic;
signal cia_sp_t : std_logic;
signal cia_cnt_o : std_logic;
signal cia_cnt_i : std_logic;
signal cia_cnt_t : std_logic;
signal cia_irq : std_logic;
signal via1_port_a_o : std_logic_vector(7 downto 0);
signal via1_port_a_t : std_logic_vector(7 downto 0);
signal via1_port_a_i : std_logic_vector(7 downto 0);
signal via1_ca2_o : std_logic;
signal via1_ca2_i : std_logic;
signal via1_ca2_t : std_logic;
signal via1_cb1_o : std_logic;
signal via1_cb1_i : std_logic;
signal via1_cb1_t : std_logic;
signal via1_port_b_o : std_logic_vector(7 downto 0);
signal via1_port_b_t : std_logic_vector(7 downto 0);
signal via1_port_b_i : std_logic_vector(7 downto 0);
signal via1_ca1 : std_logic;
signal via1_cb2_o : std_logic;
signal via1_cb2_i : std_logic;
signal via1_cb2_t : std_logic;
signal via1_irq : std_logic;
signal via2_port_b_o : std_logic_vector(7 downto 0);
signal via2_port_b_t : std_logic_vector(7 downto 0);
signal via2_port_b_i : std_logic_vector(7 downto 0);
signal via2_ca2_o : std_logic;
signal via2_ca2_i : std_logic;
signal via2_ca2_t : std_logic;
signal via2_cb1_o : std_logic;
signal via2_cb1_i : std_logic;
signal via2_cb1_t : std_logic;
signal via2_cb2_o : std_logic;
signal via2_cb2_i : std_logic;
signal via2_cb2_t : std_logic;
signal via2_irq : std_logic;
-- Local signals
signal fast_ser_dir : std_logic;
signal atn_ack : std_logic;
signal my_clk_out : std_logic;
signal my_data_out : std_logic;
signal my_fast_data_out : std_logic;
signal cpu_clk_en : std_logic;
signal cpu_rising : std_logic;
type t_mem_state is (idle, newcycle, extcycle);
signal mem_state : t_mem_state;
-- "old" style signals
signal mem_request : std_logic;
signal mem_addr : unsigned(25 downto 0);
signal mem_rwn : std_logic;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
signal mem_wdata : std_logic_vector(7 downto 0);
begin
mem_req_cpu.request <= mem_request;
mem_req_cpu.address <= mem_addr;
mem_req_cpu.read_writen <= mem_rwn;
mem_req_cpu.data <= mem_wdata;
mem_req_cpu.tag <= g_cpu_tag;
mem_req_cpu.size <= "00"; -- 1 byte at a time
mem_rack <= '1' when mem_resp_cpu.rack_tag = g_cpu_tag else '0';
mem_dack <= '1' when mem_resp_cpu.dack_tag = g_cpu_tag else '0';
cpu: entity work.cpu6502(cycle_exact)
port map (
cpu_clk => clock,
cpu_clk_en => cpu_clk_en,
cpu_reset => reset,
cpu_write => cpu_write,
cpu_wdata => cpu_wdata,
cpu_rdata => cpu_rdata,
cpu_addr => cpu_addr,
IRQn => cpu_irqn, -- IRQ interrupt (level sensitive)
NMIn => '1',
SOn => so_n );
-- Generate an output stream to debug internal operation of 1541 CPU
process(clock)
begin
if rising_edge(clock) then
debug_valid <= '0';
if cpu_clk_en = '1' then
debug_data <= '0' & atn_i & data_i & clk_i & sync & so_n & cpu_irqn & not cpu_write & cpu_rdata & cpu_addr(15 downto 0);
debug_valid <= '1';
if cpu_write = '1' then
debug_data(23 downto 16) <= cpu_wdata;
end if;
end if;
end if;
end process;
via1: entity work.via6522
port map (
clock => clock,
falling => cpu_clk_en,
rising => cpu_rising,
reset => reset,
addr => cpu_addr(3 downto 0),
wen => via1_wen,
ren => via1_ren,
data_in => cpu_wdata,
data_out => via1_data,
-- pio --
port_a_o => via1_port_a_o,
port_a_t => via1_port_a_t,
port_a_i => via1_port_a_i,
port_b_o => via1_port_b_o,
port_b_t => via1_port_b_t,
port_b_i => via1_port_b_i,
-- handshake pins
ca1_i => via1_ca1,
ca2_o => via1_ca2_o, -- ignore, driven from LS14
ca2_i => via1_ca2_i, -- connects to write protect pin
ca2_t => via1_ca2_t, -- ignore, driven from LS14
cb1_o => via1_cb1_o,
cb1_i => via1_cb1_i,
cb1_t => via1_cb1_t,
cb2_o => via1_cb2_o,
cb2_i => via1_cb2_i,
cb2_t => via1_cb2_t,
irq => via1_irq );
via2: entity work.via6522
port map (
clock => clock,
falling => cpu_clk_en,
rising => cpu_rising,
reset => reset,
addr => cpu_addr(3 downto 0),
wen => via2_wen,
ren => via2_ren,
data_in => cpu_wdata,
data_out => via2_data,
-- pio --
port_a_o => drv_wdata,
port_a_t => open,
port_a_i => drv_rdata,
port_b_o => via2_port_b_o,
port_b_t => via2_port_b_t,
port_b_i => via2_port_b_i,
-- handshake pins
ca1_i => so_n,
ca2_o => via2_ca2_o,
ca2_i => via2_ca2_i,
ca2_t => via2_ca2_t,
cb1_o => via2_cb1_o,
cb1_i => via2_cb1_i,
cb1_t => via2_cb1_t,
cb2_o => via2_cb2_o,
cb2_i => via2_cb2_i,
cb2_t => via2_cb2_t,
irq => via2_irq );
i_cia1: entity work.cia_registers
generic map (
g_report => false,
g_unit_name => "CIA_1581" )
port map (
clock => clock,
falling => falling,
reset => reset,
tod_pin => '1', -- depends on jumper
addr => unsigned(cpu_addr(3 downto 0)),
data_in => cpu_wdata,
wen => cia_wen,
ren => cia_ren,
data_out => cia_data,
-- pio --
port_a_o => cia_port_a_o, -- unused
port_a_t => cia_port_a_t,
port_a_i => cia_port_a_i,
port_b_o => cia_port_b_o, -- unused
port_b_t => cia_port_b_t,
port_b_i => cia_port_b_i,
-- serial pin
sp_o => cia_sp_o, -- Burst mode IEC data
sp_i => cia_sp_i,
sp_t => cia_sp_t,
cnt_i => cia_cnt_i, -- Burst mode IEC clock
cnt_o => cia_cnt_o,
cnt_t => cia_cnt_t,
pc_o => open,
flag_i => atn_i, -- active low ATN in
irq => cia_irq );
cpu_irqn <= not(via1_irq or via2_irq);
cpu_clk_en <= falling;
cpu_rising <= rising;
mem_busy <= '0' when mem_state = idle else '1';
-- Fetch ROM byte
process(clock)
begin
if rising_edge(clock) then
mem_addr(25 downto 16) <= g_ram_base(25 downto 16);
case mem_state is
when idle =>
if cpu_clk_en = '1' then
mem_state <= newcycle;
end if;
when newcycle => -- we have a new address now
mem_addr(15 downto 0) <= unsigned(cpu_addr(15 downto 0));
if cpu_addr(15) = '1' then -- ROM Area, which is not overridden as RAM
if cpu_write = '0' then
mem_request <= '1';
mem_state <= extcycle;
else -- writing to rom -> ignore
mem_state <= idle;
end if;
-- It's not extended RAM, not ROM, so it must be internal RAM or I/O.
elsif cpu_addr(14 downto 11) = "0000" then -- Internal RAM
mem_request <= '1';
mem_state <= extcycle;
else -- this applies to anything 0000-07FF, thus 0800-7FFF!
mem_state <= idle;
end if;
when extcycle =>
if mem_rack='1' then
mem_request <= '0';
if cpu_write='1' then
mem_state <= idle;
end if;
end if;
if mem_dack='1' and cpu_write='0' then -- only for reads
ext_rdata <= mem_resp_cpu.data;
mem_state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
mem_request <= '0';
mem_state <= idle;
end if;
end if;
end process;
mem_rwn <= not cpu_write;
mem_wdata <= cpu_wdata;
-- address decoding and data muxing
process(cpu_addr, ext_rdata, via1_data, via2_data, cia_data, wd_data)
begin
if cpu_addr(15) = '1' then -- 8000-FFFF
cpu_rdata <= ext_rdata;
elsif cpu_addr(14) = '1' then -- 4000-7FFF
cpu_rdata <= cia_data;
elsif cpu_addr(13) = '1' then -- 2000-3FFF
cpu_rdata <= wd_data;
elsif cpu_addr(12 downto 10) = "110" then -- 1800-1BFF
cpu_rdata <= via1_data;
elsif cpu_addr(12 downto 10) = "111" then -- 1C00-1FFF
cpu_rdata <= via2_data;
elsif cpu_addr(12 downto 11) = "00" then -- 0000-07FF
cpu_rdata <= ext_rdata;
else
cpu_rdata <= X"FF";
end if;
end process;
via1_wen <= '1' when cpu_write='1' and cpu_addr(15 downto 10)="000110" else '0';
via1_ren <= '1' when cpu_write='0' and cpu_addr(15 downto 10)="000110" else '0';
via2_wen <= '1' when cpu_write='1' and cpu_addr(15 downto 10)="000111" else '0';
via2_ren <= '1' when cpu_write='0' and cpu_addr(15 downto 10)="000111" else '0';
cia_wen <= '1' when cpu_write='1' and cpu_addr(15 downto 14)="01" else '0';
cia_ren <= '1' when cpu_write='0' and cpu_addr(15 downto 14)="01" else '0';
wd_wen <= '1' when cpu_write='1' and cpu_addr(15 downto 13)="001" else '0';
wd_ren <= '1' when cpu_write='0' and cpu_addr(15 downto 13)="001" else '0';
-- correctly attach the VIA pins to the outside world
via1_ca1 <= not atn_i;
via1_cb2_i <= via1_cb2_o or not via1_cb2_t;
-- Via Port A is used in the 1541 for the parallel interface (SpeedDos / DolphinDos), but in the 1571 some of the pins are connected internally
via1_port_a_i(7) <= (via1_port_a_o(7) or not via1_port_a_t(7)) and so_n; -- Byte ready in schematic. Our byte_ready signal is not yet masked with so_e
via1_port_a_i(6) <= (via1_port_a_o(6) or not via1_port_a_t(6)); -- ATN OUT (not connected)
via1_port_a_i(5) <= (via1_port_a_o(5) or not via1_port_a_t(5)); -- 2 MHz mode
via1_port_a_i(4) <= (via1_port_a_o(4) or not via1_port_a_t(4));
via1_port_a_i(3) <= (via1_port_a_o(3) or not via1_port_a_t(3));
via1_port_a_i(2) <= (via1_port_a_o(2) or not via1_port_a_t(2)); -- SIDE
via1_port_a_i(1) <= (via1_port_a_o(1) or not via1_port_a_t(1)); -- SER_DIR
via1_port_a_i(0) <= (via1_port_a_o(0) or not via1_port_a_t(0)) and not track_0;
side <= via1_port_a_i(2);
two_MHz <= via1_port_a_i(5);
fast_ser_dir <= via1_port_a_i(1);
-- Because Port B reads its own output when set to output, we do not need to consider the direction here
via1_port_b_i(7) <= not atn_i;
via1_port_b_i(6) <= drive_address(1); -- drive select
via1_port_b_i(5) <= drive_address(0); -- drive select;
via1_port_b_i(4) <= '1'; -- atn a - PUP
via1_port_b_i(3) <= '1'; -- clock out - PUP
via1_port_b_i(2) <= not (clk_i and not my_clk_out);
via1_port_b_i(1) <= '1'; -- data out - PUP
via1_port_b_i(0) <= not (data_i and not my_data_out and (not (atn_ack xor (not atn_i))));
via1_ca2_i <= write_prot_n;
via1_cb1_i <= via1_cb1_o or not via1_cb1_t;
atn_ack <= via1_port_b_o(4) or not via1_port_b_t(4);
my_data_out <= via1_port_b_o(1) or not via1_port_b_t(1);
my_clk_out <= via1_port_b_o(3) or not via1_port_b_t(3);
-- Do the same for VIA 2. Port A should read the pin, Port B reads the output internally, so for port B only actual input signals should be connected
via2_port_b_i(7) <= sync;
via2_port_b_i(6) <= '1'; --Density
via2_port_b_i(5) <= '1'; --Density
via2_port_b_i(4) <= write_prot_n;
via2_port_b_i(3) <= '1'; -- LED
via2_port_b_i(2) <= '1'; -- Motor
via2_port_b_i(1) <= '1'; -- Step
via2_port_b_i(0) <= '1'; -- Step
via2_cb1_i <= via2_cb1_o or not via2_cb1_t;
via2_cb2_i <= via2_cb2_o or not via2_cb2_t;
via2_ca2_i <= via2_ca2_o or not via2_ca2_t;
-- CIA ports are not used
cia_port_a_i <= cia_port_a_o or not cia_port_a_t;
cia_port_b_i <= cia_port_b_o or not cia_port_b_t;
act_led <= not (via2_port_b_o(3) or not via2_port_b_t(3)) or not power;
mode <= via2_cb2_i;
step(0) <= via2_port_b_o(0) or not via2_port_b_t(0);
step(1) <= via2_port_b_o(1) or not via2_port_b_t(1);
motor_on_i <= (via2_port_b_o(2) or not via2_port_b_t(2)) and power;
rate_ctrl(0) <= via2_port_b_o(5) or not via2_port_b_t(5);
rate_ctrl(1) <= via2_port_b_o(6) or not via2_port_b_t(6);
soe <= via2_ca2_i;
so_n <= byte_ready or not soe;
motor_on <= motor_on_i;
data_o <= not power or (not my_data_out and my_fast_data_out and (not (atn_ack xor (not atn_i))));
clk_o <= not power or not my_clk_out;
atn_o <= '1';
my_fast_data_out <= (cia_sp_o or not cia_sp_t) or not fast_ser_dir; -- active low!
cia_sp_i <= (cia_sp_o or not cia_sp_t) when fast_ser_dir = '1' else
data_i;
fast_clk_o <= (cia_cnt_o or not cia_cnt_t) or not fast_ser_dir; -- active low!
cia_cnt_i <= (cia_cnt_o or not cia_cnt_t) when fast_ser_dir = '1' else -- output
fast_clk_i; -- assume that 74LS241 wins
-- Floppy Controller
i_wd177x: entity work.wd177x
generic map (
g_tag => g_disk_tag
)
port map(
clock => clock,
clock_en => cpu_clk_en,
reset => reset,
addr => unsigned(cpu_addr(1 downto 0)),
wen => wd_wen,
ren => wd_ren,
wdata => cpu_wdata,
rdata => wd_data,
motor_en => motor_on_i,
tick_1kHz => tick_1kHz,
tick_4MHz => tick_4MHz,
stepper_en => '0',
mem_req => mem_req_disk,
mem_resp => mem_resp_disk,
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq
);
end architecture;
-- Original mapping:
-- 0000-07FF RAM
-- 0800-17FF open
-- 1800-1BFF VIA 1
-- 1C00-1FFF VIA 2
-- 2000-3FFF WD17xx
-- 4000-7FFF CIA 6526
-- 8000-FFFF ROM image
| gpl-3.0 | cf55019c1f5a7b1babac397ef4cd6cff | 0.471883 | 3.168037 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/testbench/mem_io_timing_tb.vhd | 1 | 3,300 | --------------------------------------------------------------------------------
-- Entity: mem_io_synth
-- Date:2016-07-17
-- Author: Gideon
--
-- Description: Testbench for altera io for ddr
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_io_timing_tb is
generic (
g_in_delay : time := 0.3 ns );
end entity;
architecture arch of mem_io_timing_tb is
signal ref_clock : std_logic := '0';
signal ref_reset : std_logic;
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic;
signal SDRAM_CLK : std_logic := 'Z';
signal SDRAM_CLKn : std_logic := 'Z';
signal SDRAM_A : std_logic_vector(7 downto 0);
signal SDRAM_DQ : std_logic_vector(3 downto 0) := (others => 'Z');
signal SDRAM_DQS : std_logic;
signal write_data : std_logic_vector(15 downto 0);
signal read_data : std_logic_vector(15 downto 0);
signal do_read : std_logic;
signal mode : std_logic_vector(1 downto 0) := "01";
signal correct : std_logic;
signal measurement : std_logic_vector(11 downto 0);
signal latency : integer := 0;
signal rdata_valid : std_logic;
begin
ref_clock <= not ref_clock after 10 ns; -- 20 ns cycle time
ref_reset <= '1', '0' after 100 ns;
i_mut: entity work.mem_io_synth
port map (
ref_clock => ref_clock,
ref_reset => ref_reset,
sys_clock => sys_clock,
sys_reset => sys_reset,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS,
write_data => write_data,
read_data => read_data,
do_read => do_read,
rdata_valid=> rdata_valid,
mode => mode,
measurement => measurement
);
process(SDRAM_CLK)
variable delay : integer := -10;
begin
if rising_edge(SDRAM_CLK) then
if SDRAM_A(7 downto 4) = "0110" then
delay := 7;
end if;
end if;
delay := delay - 1;
case delay is
when 0 =>
SDRAM_DQ <= transport X"2" after g_in_delay;
when -1 =>
SDRAM_DQ <= transport X"3" after g_in_delay;
when -2 =>
SDRAM_DQ <= transport X"4" after g_in_delay;
when -3 =>
SDRAM_DQ <= transport X"5" after g_in_delay;
when others =>
SDRAM_DQ <= transport "ZZZZ" after g_in_delay;
end case;
end process;
process(sys_clock)
variable timer : integer := 0;
begin
if falling_edge(sys_clock) then
if do_read = '1' then
timer := 0;
else
timer := timer + 1;
end if;
if read_data = X"5432" then
correct <= '1';
latency <= timer;
else
correct <= '0';
end if;
end if;
end process;
end arch;
| gpl-3.0 | a0ef7b5ed5b8a8aeb682de358d14066b | 0.464848 | 3.937947 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_sim/usb_test_nano3.vhd | 1 | 6,651 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 2 for USB host
-- This testcase initializes a repeated IN using split tokens
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
use work.tl_string_util_pkg.all;
use work.nano_addresses_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity usb_test_nano3 is
generic (
g_report_file_name : string := "work/usb_test_nano3.rpt"
);
end entity;
architecture arch of usb_test_nano3 is
signal clocks_stopped : boolean := false;
signal interrupt : std_logic;
constant Attr_Fifo_Base : unsigned(19 downto 0) := X"00700"; -- 380 * 2
constant Attr_Fifo_Tail_Address : unsigned(19 downto 0) := X"007F0"; -- 3f8 * 2
constant Attr_Fifo_Head_Address : unsigned(19 downto 0) := X"007F2"; -- 3f9 * 2
begin
i_harness: entity work.usb_harness_nano
port map (
interrupt => interrupt,
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable res : std_logic_vector(7 downto 0);
variable attr_fifo_tail : integer := 0;
variable attr_fifo_head : integer := 0;
variable data : std_logic_vector(15 downto 0);
procedure io_write_word(addr : unsigned(19 downto 0); word : std_logic_vector(15 downto 0)) is
begin
io_write(io => io, addr => (addr + 0), data => word(7 downto 0));
io_write(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure io_read_word(addr : unsigned(19 downto 0); word : out std_logic_vector(15 downto 0)) is
begin
io_read(io => io, addr => (addr + 0), data => word(7 downto 0));
io_read(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure read_attr_fifo(result : out std_logic_vector(15 downto 0)) is
variable data : std_logic_vector(15 downto 0);
begin
wait until interrupt = '1';
-- io_read_word(addr => Attr_Fifo_Head_Address, word => data);
-- attr_fifo_head := to_integer(unsigned(data));
-- L1: while true loop
-- io_read_word(addr => Attr_Fifo_Head_Address, word => data);
-- attr_fifo_head := to_integer(unsigned(data));
-- if (attr_fifo_head /= attr_fifo_tail) then
-- exit L1;
-- end if;
-- end loop;
io_read_word(addr => (Attr_Fifo_Base + attr_fifo_tail*2), word => data);
attr_fifo_tail := attr_fifo_tail + 1;
if attr_fifo_tail = 16 then
attr_fifo_tail := 0;
end if;
io_write_word(addr => Attr_Fifo_Tail_Address, word => std_logic_vector(to_unsigned(attr_fifo_tail, 16)));
sctb_trace("Fifo read: " & hstr(data));
result := data;
end procedure;
procedure check_result(expected : std_logic_vector(7 downto 0); exp_result : std_logic_vector(15 downto 0)) is
variable data : std_logic_vector(15 downto 0);
variable byte : std_logic_vector(7 downto 0);
begin
io_read_word(Command_Length, data);
sctb_trace("Command length: " & hstr(data));
io_read_word(Command_Result, data);
sctb_trace("Command result: " & hstr(data));
sctb_check(data, exp_result, "Unexpected response");
byte := read_memory_8(mem, X"00550000");
sctb_check(byte, expected, "Erroneous byte");
write_memory_8(mem, X"00550000", X"00");
end procedure;
-- procedure wait_command_done is
-- begin
-- L1: while true loop
-- io_read(io => io, addr => Command, data => res);
-- if res(1) = '1' then -- check if paused bit has been set
-- exit L1;
-- end if;
-- end loop;
-- end procedure;
begin
bind_io_bus_bfm("io", io);
bind_mem_model("memory", mem);
sctb_open_simulation("path::path", g_report_file_name);
sctb_open_region("Testing Setup request", 0);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write_word(c_nano_simulation, X"0001" ); -- set nano to simulation mode
io_write_word(c_nano_busspeed, X"0002" ); -- set bus speed to HS
io_write(io, c_nano_enable, X"01" ); -- enable nano
wait for 4 us;
--#define SPLIT_START 0x0000
--#define SPLIT_COMPLETE 0x0080
--#define SPLIT_SPEED 0x0040
--#define SPLIT_CONTROL 0x0000
--#define SPLIT_ISOCHRO 0x0010
--#define SPLIT_BULK 0x0020
--#define SPLIT_INTERRUPT 0x0030
--#define SPLIT_PORT_MSK 0x000F
--#define SPLIT_HUBAD_MSK 0x7F00
--#define SPLIT_DO_SPLIT 0x8000
io_write_word(Command_SplitCtl, X"8132"); -- Hub Address 1, Port 2, Speed = FS, EP = interrupt
io_write_word(Command_DevEP, X"0007"); -- EP7: NAK NAK DATA0 NAK NAK DATA1 NAK STALL
io_write_word(Command_MemHi, X"0055");
io_write_word(Command_MemLo, X"0000");
io_write_word(Command_MaxTrans, X"0010");
io_write_word(Command_Interval, X"0001"); -- every frame!
io_write_word(Command_Length, X"0010");
-- arm
io_write_word(Command_MemLo, X"0000");
io_write_word(Command, X"5042"); -- in with mem write, using cercular buffer
read_attr_fifo(data);
check_result(X"44", X"8001");
-- arm
io_write_word(Command_MemLo, X"0000");
io_write_word(Command, X"5842"); -- in with mem write, using cercular buffer
read_attr_fifo(data);
check_result(X"6B", X"8801");
-- arm
io_write_word(Command_MemLo, X"0000");
io_write_word(Command, X"5042"); -- in with mem write, using cercular buffer
read_attr_fifo(data);
check_result(X"00", X"C400");
sctb_close_region;
sctb_close_simulation;
clocks_stopped <= true;
wait;
end process;
end arch;
--restart; mem load -infile nano_code.hex -format hex /usb_test_nano3/i_harness/i_host/i_nano/i_buf_ram/mem; run 2000 us
| gpl-3.0 | df73909c04837aa0f090a524eabc9d2a | 0.55736 | 3.511616 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/stack/vhdl_source/distributed_stack.vhd | 2 | 4,080 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2012, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Stack Using Single Port Distributed RAM
-------------------------------------------------------------------------------
-- File : distributed_stack.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This implementation makes use of the RAMX1 properties,
-- implementing a 16-deep synchronous stack in only one LUT per
-- bit. The value to be popped is always visible.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity distributed_stack is
generic (
Width : integer := 32;
simultaneous_pushpop : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
pop : in std_logic;
push : in std_logic;
flush : in std_logic;
data_in : in std_logic_vector(Width-1 downto 0);
data_out : out std_logic_vector(Width-1 downto 0);
full : out std_logic;
data_valid : out std_logic );
end distributed_stack;
architecture Gideon of distributed_stack is
signal pointer : unsigned(3 downto 0);
signal address : unsigned(3 downto 0);
signal we : std_logic;
signal data_valid_i : std_logic;
signal full_i : std_logic;
signal filtered_pop : std_logic;
signal filtered_push : std_logic;
signal ram_data : std_logic_vector(Width-1 downto 0);
begin
filtered_pop <= data_valid_i and pop;
filtered_push <= not full_i and push;
full <= full_i;
process(filtered_push, pop, pointer, ram_data, data_in, data_valid_i)
begin
we <= filtered_push;
data_out <= ram_data;
data_valid <= data_valid_i;
if filtered_push='1' then
address <= pointer + 1;
else
address <= pointer;
end if;
if simultaneous_pushpop then
if filtered_push='1' and pop='1' then
data_out <= data_in;
we <= '0';
data_valid <= '1';
end if;
end if;
end process;
process(clock)
variable new_pointer : unsigned(3 downto 0);--integer range 0 to Depth;
begin
if rising_edge(clock) then
if flush='1' then
new_pointer := X"F";
elsif (filtered_pop='1') and (filtered_push='0') then
new_pointer := pointer - 1;
elsif (filtered_pop='0') and (filtered_push='1') then
new_pointer := pointer + 1;
else
new_pointer := pointer;
end if;
pointer <= new_pointer;
if (new_pointer = X"F") then
data_valid_i <= '0';
else
data_valid_i <= '1';
end if;
if (new_pointer /= X"E") then
full_i <= '0';
else
full_i <= '1';
end if;
if reset='1' then
pointer <= X"F";
full_i <= '0';
data_valid_i <= '0';
end if;
end if;
end process;
RAMs : for ram2 in 0 to Width-1 generate
i_ram : RAM16X1S
port map (
WCLK => clock,
WE => we,
D => data_in(ram2),
A3 => address(3),
A2 => address(2),
A1 => address(1),
A0 => address(0),
O => ram_data(ram2) );
end generate;
end Gideon;
| gpl-3.0 | 2f65df953ac97e1602fa8268b03ad71a | 0.441912 | 4.34968 | false | false | false | false |
keyru/hdl-make | tests/counter/top/spec_v4/vhdl/spec_top.vhd | 2 | 1,394 | -----------------------------------------------------------------------
-- Design : Counter VHDL top module, SPEC (Simple PCIe Carrier)
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(3 downto 0)
);
end spec_top;
-----------------------------------------------------------------------
architecture structure of spec_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= not clear_i;
s_count <= not count_i;
led_o(3 downto 0) <= not s_Q(7 downto 4);
end architecture structure;
-----------------------------------------------------------------------
| gpl-3.0 | ec599bf3d4993e4ee3676ff0d7a5c056 | 0.464849 | 3.949008 | false | false | false | false |
chiggs/nvc | test/regress/vecorder.vhd | 4 | 1,391 | entity vecorder is
end entity;
architecture test of vecorder is
type int_array is array (integer range <>) of integer;
signal s : int_array(0 to 1) := ( 0 => 0, 1 => 1 );
begin
process is
variable x : int_array(0 to 1) := ( 0 => 0, 1 => 1 );
variable y : int_array(1 downto 0) := ( 0 => 0, 1 => 1 );
begin
assert x(0) = 0 report "one";
assert x(1) = 1 report "two";
assert x = ( 0, 1 );
x := ( 2, 3 );
report integer'image(x(0));
report integer'image(x(1));
assert x(0) = 2 report "three";
assert x(1) = 3 report "four";
assert x = ( 2, 3 ) report "five";
assert ( 2, 3 ) = x report "six";
assert s(0) = 0 report "s one";
assert s(1) = 1 report "s two";
s <= ( 2, 3 );
wait for 0 ns;
report integer'image(s(0));
report integer'image(s(1));
assert s(0) = 2 report "s three";
assert s(1) = 3 report "s four";
assert y(0) = 0 report "y one";
assert y(1) = 1 report "y two";
assert y = ( 1, 0 );
y := ( 2, 3 );
report integer'image(y(0));
report integer'image(y(1));
assert y(0) = 3 report "y three";
assert y(1) = 2 report "y four";
assert y = ( 2, 3 ) report "y five";
wait;
end process;
end architecture;
| gpl-3.0 | da8e918540f1539930bb29ffa208969f | 0.478073 | 3.34375 | false | false | false | false |
trondd/mkjpeg | design/mdct/FDCT.vhd | 2 | 22,044 | -------------------------------------------------------------------------------
-- File Name : FDCT.vhd
--
-- Project : JPEG_ENC
--
-- Module : FDCT
--
-- Content : FDCT
--
-- Description : 2D Discrete Cosine Transform
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity FDCT is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
fdct_sm_settings : in T_SM_SETTINGS;
-- BUF_FIFO
bf_fifo_rd : out std_logic;
bf_fifo_q : in std_logic_vector(23 downto 0);
bf_fifo_hf_full : in std_logic;
-- ZIG ZAG
zz_buf_sel : in std_logic;
zz_rd_addr : in std_logic_vector(5 downto 0);
zz_data : out std_logic_vector(11 downto 0);
zz_rden : in std_logic;
-- HOST
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
sof : in std_logic
);
end entity FDCT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of FDCT is
constant C_Y_1 : signed(14 downto 0) := to_signed(4899, 15);
constant C_Y_2 : signed(14 downto 0) := to_signed(9617, 15);
constant C_Y_3 : signed(14 downto 0) := to_signed(1868, 15);
constant C_Cb_1 : signed(14 downto 0) := to_signed(-2764, 15);
constant C_Cb_2 : signed(14 downto 0) := to_signed(-5428, 15);
constant C_Cb_3 : signed(14 downto 0) := to_signed(8192, 15);
constant C_Cr_1 : signed(14 downto 0) := to_signed(8192, 15);
constant C_Cr_2 : signed(14 downto 0) := to_signed(-6860, 15);
constant C_Cr_3 : signed(14 downto 0) := to_signed(-1332, 15);
signal mdct_data_in : std_logic_vector(7 downto 0);
signal mdct_idval : std_logic;
signal mdct_odval : std_logic;
signal mdct_data_out : std_logic_vector(11 downto 0);
signal odv1 : std_logic;
signal dcto1 : std_logic_vector(11 downto 0);
signal x_pixel_cnt : unsigned(15 downto 0);
signal y_line_cnt : unsigned(15 downto 0);
signal rd_addr : std_logic_vector(31 downto 0);
signal input_rd_cnt : unsigned(6 downto 0);
signal rd_en : std_logic;
signal rd_en_d1 : std_logic;
signal rdaddr : unsigned(31 downto 0);
signal bf_dval : std_logic;
signal bf_dval_m1 : std_logic;
signal bf_dval_m2 : std_logic;
signal bf_dval_m3 : std_logic;
signal wr_cnt : unsigned(5 downto 0);
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
signal dbuf_we : std_logic;
signal dbuf_waddr : std_logic_vector(6 downto 0);
signal dbuf_raddr : std_logic_vector(6 downto 0);
signal xw_cnt : unsigned(2 downto 0);
signal yw_cnt : unsigned(2 downto 0);
signal dbuf_q_z1 : std_logic_vector(11 downto 0);
constant C_SIMA_ASZ : integer := 9;
signal sim_rd_addr : unsigned(C_SIMA_ASZ-1 downto 0);
signal Y_reg_1 : signed(23 downto 0);
signal Y_reg_2 : signed(23 downto 0);
signal Y_reg_3 : signed(23 downto 0);
signal Cb_reg_1 : signed(23 downto 0);
signal Cb_reg_2 : signed(23 downto 0);
signal Cb_reg_3 : signed(23 downto 0);
signal Cr_reg_1 : signed(23 downto 0);
signal Cr_reg_2 : signed(23 downto 0);
signal Cr_reg_3 : signed(23 downto 0);
signal Y_reg : signed(23 downto 0);
signal Cb_reg : signed(23 downto 0);
signal Cr_reg : signed(23 downto 0);
signal R_s : signed(8 downto 0);
signal G_s : signed(8 downto 0);
signal B_s : signed(8 downto 0);
signal Y_8bit : unsigned(7 downto 0);
signal Cb_8bit : unsigned(7 downto 0);
signal Cr_8bit : unsigned(7 downto 0);
signal cmp_idx : unsigned(2 downto 0);
signal cur_cmp_idx : unsigned(2 downto 0);
signal cur_cmp_idx_d1 : unsigned(2 downto 0);
signal cur_cmp_idx_d2 : unsigned(2 downto 0);
signal cur_cmp_idx_d3 : unsigned(2 downto 0);
signal cur_cmp_idx_d4 : unsigned(2 downto 0);
signal cur_cmp_idx_d5 : unsigned(2 downto 0);
signal cur_cmp_idx_d6 : unsigned(2 downto 0);
signal cur_cmp_idx_d7 : unsigned(2 downto 0);
signal cur_cmp_idx_d8 : unsigned(2 downto 0);
signal cur_cmp_idx_d9 : unsigned(2 downto 0);
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(11 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(9 downto 0);
signal fifo1_rd_cnt : unsigned(5 downto 0);
signal fifo1_q_dval : std_logic;
signal fifo_data_in : std_logic_vector(11 downto 0);
signal fifo_rd_arm : std_logic;
signal eoi_fdct : std_logic;
signal bf_fifo_rd_s : std_logic;
signal start_int : std_logic;
signal start_int_d : std_logic_vector(4 downto 0);
signal fram1_data : std_logic_vector(23 downto 0);
signal fram1_q : std_logic_vector(23 downto 0);
signal fram1_we : std_logic;
signal fram1_waddr : std_logic_vector(6 downto 0);
signal fram1_raddr : std_logic_vector(6 downto 0);
signal fram1_rd_d : std_logic_vector(8 downto 0);
signal fram1_rd : std_logic;
signal rd_started : std_logic;
signal writing_en : std_logic;
signal fram1_q_vld : std_logic;
signal fram1_line_cnt : unsigned(2 downto 0);
signal fram1_pix_cnt : unsigned(2 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
zz_data <= dbuf_q;
bf_fifo_rd <= bf_fifo_rd_s;
-------------------------------------------------------------------
-- FRAM1
-------------------------------------------------------------------
U_FRAM1 : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 24
)
port map
(
d => fram1_data,
waddr => fram1_waddr,
raddr => fram1_raddr,
we => fram1_we,
clk => CLK,
q => fram1_q
);
fram1_we <= bf_dval;
fram1_data <= bf_fifo_q;
fram1_q_vld <= fram1_rd_d(5);
-------------------------------------------------------------------
-- FRAM1 process
-------------------------------------------------------------------
p_fram1_acc : process(CLK, RST)
begin
if RST = '1' then
fram1_waddr <= (others => '0');
elsif CLK'event and CLK = '1' then
if fram1_we = '1' then
fram1_waddr <= std_logic_vector(unsigned(fram1_waddr) + 1);
end if;
end if;
end process;
-------------------------------------------------------------------
-- IRAM read process
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d1 <= '0';
x_pixel_cnt <= (others => '0');
y_line_cnt <= (others => '0');
input_rd_cnt <= (others => '0');
cmp_idx <= (others => '0');
cur_cmp_idx <= (others => '0');
cur_cmp_idx_d1 <= (others => '0');
cur_cmp_idx_d2 <= (others => '0');
cur_cmp_idx_d3 <= (others => '0');
cur_cmp_idx_d4 <= (others => '0');
cur_cmp_idx_d5 <= (others => '0');
cur_cmp_idx_d6 <= (others => '0');
cur_cmp_idx_d7 <= (others => '0');
cur_cmp_idx_d8 <= (others => '0');
cur_cmp_idx_d9 <= (others => '0');
eoi_fdct <= '0';
start_int <= '0';
bf_fifo_rd_s <= '0';
bf_dval <= '0';
bf_dval_m1 <= '0';
bf_dval_m2 <= '0';
fram1_rd <= '0';
fram1_rd_d <= (others => '0');
start_int_d <= (others => '0');
fram1_raddr <= (others => '0');
fram1_line_cnt <= (others => '0');
fram1_pix_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d1 <= rd_en;
cur_cmp_idx_d1 <= cur_cmp_idx;
cur_cmp_idx_d2 <= cur_cmp_idx_d1;
cur_cmp_idx_d3 <= cur_cmp_idx_d2;
cur_cmp_idx_d4 <= cur_cmp_idx_d3;
cur_cmp_idx_d5 <= cur_cmp_idx_d4;
cur_cmp_idx_d6 <= cur_cmp_idx_d5;
cur_cmp_idx_d7 <= cur_cmp_idx_d6;
cur_cmp_idx_d8 <= cur_cmp_idx_d7;
cur_cmp_idx_d9 <= cur_cmp_idx_d8;
start_int <= '0';
bf_dval_m3 <= bf_fifo_rd_s;
bf_dval_m2 <= bf_dval_m3;
bf_dval_m1 <= bf_dval_m2;
bf_dval <= bf_dval_m1;
fram1_rd_d <= fram1_rd_d(fram1_rd_d'length-2 downto 0) & fram1_rd;
start_int_d <= start_int_d(start_int_d'length-2 downto 0) & start_int;
-- SOF or internal self-start
if (sof = '1' or start_int = '1') then
input_rd_cnt <= (others => '0');
-- enable BUF_FIFO/FRAM1 reading
rd_started <= '1';
-- component index
if cmp_idx = 4-1 then
cmp_idx <= (others => '0');
-- horizontal block counter
if x_pixel_cnt = unsigned(img_size_x)-16 then
x_pixel_cnt <= (others => '0');
-- vertical block counter
if y_line_cnt = unsigned(img_size_y)-8 then
y_line_cnt <= (others => '0');
-- set end of image flag
eoi_fdct <= '1';
else
y_line_cnt <= y_line_cnt + 8;
end if;
else
x_pixel_cnt <= x_pixel_cnt + 16;
end if;
else
cmp_idx <=cmp_idx + 1;
end if;
cur_cmp_idx <= cmp_idx;
end if;
-- wait until FIFO becomes half full but only for component 0
-- as we read buf FIFO only during component 0
if rd_started = '1' and (bf_fifo_hf_full = '1' or cur_cmp_idx > 1) then
rd_en <= '1';
rd_started <= '0';
end if;
bf_fifo_rd_s <= '0';
fram1_rd <= '0';
-- stall reading from input FIFO and writing to output FIFO
-- when output FIFO is almost full
if rd_en = '1' and unsigned(fifo1_count) < 512-64 and
(bf_fifo_hf_full = '1' or cur_cmp_idx > 1) then
-- read request goes to BUF_FIFO only for component 0.
if cur_cmp_idx < 2 then
bf_fifo_rd_s <= '1';
end if;
-- count number of samples read from input in one run
if input_rd_cnt = 64-1 then
rd_en <= '0';
-- internal restart
start_int <= '1' and not eoi_fdct;
eoi_fdct <= '0';
else
input_rd_cnt <= input_rd_cnt + 1;
end if;
-- FRAM read enable
fram1_rd <= '1';
end if;
-- increment FRAM1 read address according to subsampling
-- idea is to extract 8x8 from 16x8 block
-- there are two luminance blocks left and right
-- there is 2:1 subsampled Cb block
-- there is 2:1 subsampled Cr block
-- subsampling done as simple decimation by 2 wo/ averaging
if sof = '1' then
fram1_raddr <= (others => '0');
fram1_line_cnt <= (others => '0');
fram1_pix_cnt <= (others => '0');
elsif start_int_d(4) = '1' then
fram1_line_cnt <= (others => '0');
fram1_pix_cnt <= (others => '0');
case cur_cmp_idx_d4 is
-- Y1, Cr, Cb
when "000" | "010" | "011" =>
fram1_raddr <= (others => '0');
-- Y2
when "001" =>
fram1_raddr <= std_logic_vector(to_unsigned(64, fram1_raddr'length));
when others =>
null;
end case;
elsif fram1_rd_d(4) = '1' then
if fram1_pix_cnt = 8-1 then
fram1_pix_cnt <= (others => '0');
if fram1_line_cnt = 8-1 then
fram1_line_cnt <= (others => '0');
else
fram1_line_cnt <= fram1_line_cnt + 1;
end if;
else
fram1_pix_cnt <= fram1_pix_cnt + 1;
end if;
case cur_cmp_idx_d6 is
when "000" | "001" =>
fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 1);
when "010" | "011" =>
if fram1_pix_cnt = 4-1 then
fram1_raddr <= std_logic_vector('1' & fram1_line_cnt & "000");
elsif fram1_pix_cnt = 8-1 then
if fram1_line_cnt = 8-1 then
fram1_raddr <= '0' & "000" & "000";
else
fram1_raddr <= std_logic_vector('0' & (fram1_line_cnt+1) & "000");
end if;
else
fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 2);
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------
-- FDCT with input level shift
-------------------------------------------------------------------
U_MDCT : entity work.MDCT
port map
(
clk => CLK,
rst => RST,
dcti => mdct_data_in,
idv => mdct_idval,
odv => mdct_odval,
dcto => mdct_data_out,
odv1 => odv1,
dcto1 => dcto1
);
mdct_idval <= fram1_rd_d(8);
R_s <= signed('0' & fram1_q(7 downto 0));
G_s <= signed('0' & fram1_q(15 downto 8));
B_s <= signed('0' & fram1_q(23 downto 16));
-------------------------------------------------------------------
-- Mux1
-------------------------------------------------------------------
p_mux1 : process(CLK, RST)
begin
if RST = '1' then
mdct_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
case cur_cmp_idx_d9 is
when "000" | "001" =>
mdct_data_in <= std_logic_vector(Y_8bit);
when "010" =>
mdct_data_in <= std_logic_vector(Cb_8bit);
when "011" =>
mdct_data_in <= std_logic_vector(Cr_8bit);
when others =>
null;
end case;
end if;
end process;
-------------------------------------------------------------------
-- FIFO1
-------------------------------------------------------------------
U_FIFO1 : entity work.FIFO
generic map
(
DATA_WIDTH => 12,
ADDR_WIDTH => 9
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
fifo1_wr <= mdct_odval;
fifo_data_in <= mdct_data_out;
-------------------------------------------------------------------
-- FIFO1 rd controller
-------------------------------------------------------------------
p_fifo_rd_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo1_rd <= '0';
fifo_rd_arm <= '0';
fifo1_rd_cnt <= (others => '0');
fifo1_q_dval <= '0';
elsif CLK'event and CLK = '1' then
fifo1_rd <= '0';
fifo1_q_dval <= fifo1_rd;
if start_pb = '1' then
fifo_rd_arm <= '1';
fifo1_rd_cnt <= (others => '0');
end if;
if fifo_rd_arm = '1' then
if fifo1_rd_cnt = 64-1 then
fifo_rd_arm <= '0';
fifo1_rd <= '1';
elsif fifo1_empty = '0' then
fifo1_rd <= '1';
fifo1_rd_cnt <= fifo1_rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- write counter
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
xw_cnt <= (others => '0');
yw_cnt <= (others => '0');
writing_en <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
xw_cnt <= (others => '0');
yw_cnt <= (others => '0');
writing_en <= '1';
end if;
if writing_en = '1' then
if fifo1_q_dval = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
ready_pb <= '1';
writing_en <= '0';
else
wr_cnt <= wr_cnt + 1;
end if;
if yw_cnt = 8-1 then
yw_cnt <= (others => '0');
xw_cnt <= xw_cnt+1;
else
yw_cnt <= yw_cnt+1;
end if;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- RGB to YCbCr conversion
-------------------------------------------------------------------
p_rgb2ycbcr : process(CLK, RST)
begin
if RST = '1' then
Y_Reg_1 <= (others => '0');
Y_Reg_2 <= (others => '0');
Y_Reg_3 <= (others => '0');
Cb_Reg_1 <= (others => '0');
Cb_Reg_2 <= (others => '0');
Cb_Reg_3 <= (others => '0');
Cr_Reg_1 <= (others => '0');
Cr_Reg_2 <= (others => '0');
Cr_Reg_3 <= (others => '0');
Y_Reg <= (others => '0');
Cb_Reg <= (others => '0');
Cr_Reg <= (others => '0');
elsif CLK'event and CLK = '1' then
-- RGB input
if C_YUV_INPUT = '0' then
Y_Reg_1 <= R_s*C_Y_1;
Y_Reg_2 <= G_s*C_Y_2;
Y_Reg_3 <= B_s*C_Y_3;
Cb_Reg_1 <= R_s*C_Cb_1;
Cb_Reg_2 <= G_s*C_Cb_2;
Cb_Reg_3 <= B_s*C_Cb_3;
Cr_Reg_1 <= R_s*C_Cr_1;
Cr_Reg_2 <= G_s*C_Cr_2;
Cr_Reg_3 <= B_s*C_Cr_3;
Y_Reg <= Y_Reg_1 + Y_Reg_2 + Y_Reg_3;
Cb_Reg <= Cb_Reg_1 + Cb_Reg_2 + Cb_Reg_3 + to_signed(128*16384,Cb_Reg'length);
Cr_Reg <= Cr_Reg_1 + Cr_Reg_2 + Cr_Reg_3 + to_signed(128*16384,Cr_Reg'length);
-- YCbCr input
-- R-G-B misused as Y-Cb-Cr
else
Y_Reg_1 <= '0' & R_s & "00000000000000";
Cb_Reg_1 <= '0' & G_s & "00000000000000";
Cr_Reg_1 <= '0' & B_s & "00000000000000";
Y_Reg <= Y_Reg_1;
Cb_Reg <= Cb_Reg_1;
Cr_Reg <= Cr_Reg_1;
end if;
end if;
end process;
Y_8bit <= unsigned(Y_Reg(21 downto 14));
Cb_8bit <= unsigned(Cb_Reg(21 downto 14));
Cr_8bit <= unsigned(Cr_Reg(21 downto 14));
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= fifo1_q;
dbuf_we <= fifo1_q_dval;
dbuf_waddr <= (not zz_buf_sel) & std_logic_vector(yw_cnt & xw_cnt);
dbuf_raddr <= zz_buf_sel & zz_rd_addr;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | ea8b513c0c810f6ed019b37c130530d5 | 0.404464 | 3.717369 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20_gpio_block_0_avalon_slave_0_translator.vhd | 1 | 14,661 | -- cb20_gpio_block_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 4;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(3 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_gpio_block_0_avalon_slave_0_translator;
architecture rtl of cb20_gpio_block_0_avalon_slave_0_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(3 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
gpio_block_0_avalon_slave_0_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_gpio_block_0_avalon_slave_0_translator
| apache-2.0 | 903b48b94d783b09f4f0a5283d465433 | 0.429711 | 4.335009 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/distributed_stack.vhd | 1 | 4,413 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2012, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Stack Using Single Port Distributed RAM
-------------------------------------------------------------------------------
-- File : distributed_stack.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This implementation makes use of the RAMX1 properties,
-- implementing a 16-deep synchronous stack in only one LUT per
-- bit. The value to be popped is always visible.
--
-- For building on altera, this block has been sub-optimized,
-- and the required cells are now inferred.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity distributed_stack is
generic (
width : integer := 32;
simultaneous_pushpop : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
pop : in std_logic;
push : in std_logic;
flush : in std_logic;
data_in : in std_logic_vector(width-1 downto 0);
data_out : out std_logic_vector(width-1 downto 0);
full : out std_logic;
data_valid : out std_logic );
end distributed_stack;
architecture Gideon of distributed_stack is
signal pointer : unsigned(3 downto 0) := X"0";
signal address : unsigned(3 downto 0) := X"0";
signal we : std_logic;
signal en : std_logic;
signal data_valid_i : std_logic;
signal full_i : std_logic;
signal filtered_pop : std_logic;
signal filtered_push : std_logic;
signal sel : std_logic;
signal ram_data : std_logic_vector(width-1 downto 0) := (others => '0');
signal last_written : std_logic_vector(width-1 downto 0) := (others => '0');
begin
filtered_pop <= data_valid_i and pop;
filtered_push <= not full_i and push;
full <= full_i;
data_valid <= data_valid_i;
en <= filtered_pop or filtered_push;
we <= filtered_push;
address <= (pointer - 2) when filtered_pop='1' else pointer;
process(clock)
variable new_pointer : unsigned(3 downto 0);
begin
if rising_edge(clock) then
new_pointer := pointer;
if flush='1' then
new_pointer := X"0";
elsif (filtered_pop='1') and (filtered_push='0') then
new_pointer := new_pointer - 1;
elsif (filtered_pop='0') and (filtered_push='1') then
new_pointer := new_pointer + 1;
end if;
pointer <= new_pointer;
if (new_pointer = X"0") then
data_valid_i <= '0';
else
data_valid_i <= '1';
end if;
if (new_pointer /= X"F") then
full_i <= '0';
else
full_i <= '1';
end if;
if reset='1' then
pointer <= X"0";
full_i <= '0';
data_valid_i <= '0';
end if;
end if;
end process;
data_out <= ram_data when sel = '0' else last_written;
b_ram: block
type t_ram is array(0 to 15) of std_logic_vector(width-1 downto 0);
signal ram : t_ram := (others => (others => '0'));
begin
process(clock)
begin
if rising_edge(clock) then
if en = '1' then
ram_data <= ram(to_integer(address));
sel <= '0';
if we = '1' then
ram(to_integer(address)) <= data_in;
last_written <= data_in;
sel <= '1';
end if;
end if;
if reset='1' then
sel <= '0';
end if;
end if;
end process;
end block;
end Gideon;
| gpl-3.0 | 2692e0550724363ebd37b95851c09196 | 0.440517 | 4.373637 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/mem.vhd | 2 | 3,960 | ----------------------------------------------------------------------------------------------
--
-- Input file : mem.vhd
-- Design name : mem
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Memory retrieves data words from a data memory. Memory file
-- access of byte, halfword and word sizes is supported. The sel_o
-- signal indicates which bytes should be read or written. The
-- responsibility for writing the right memory address is not within
-- this integer unit but should be handled by the external memory
-- device. This facilitates the addition of devices with different
-- bus sizes.
--
-- The dmem_i signals are directly connected to the decode and
-- execute components.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity mem is port
(
mem_o : out mem_out_type;
dmem_o : out dmem_out_type;
mem_i : in mem_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end mem;
architecture arch of mem is
signal r, rin : mem_out_type;
signal mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
-- connect pipline signals
mem_o.ctrl_wrb <= r.ctrl_wrb;
mem_o.ctrl_mem_wrb <= r.ctrl_mem_wrb;
mem_o.alu_result <= r.alu_result;
-- connect memory interface signals
dmem_o.dat_o <= mem_result;
dmem_o.sel_o <= decode_mem_store(mem_i.alu_result(1 downto 0), mem_i.ctrl_mem.transfer_size);
dmem_o.we_o <= mem_i.ctrl_mem.mem_write;
dmem_o.adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 downto 0);
dmem_o.ena_o <= (mem_i.ctrl_mem.mem_read or mem_i.ctrl_mem.mem_write) and ena_i;
mem_comb: process(mem_i, mem_i.ctrl_wrb, mem_i.ctrl_mem, r, r.ctrl_wrb, r.ctrl_mem_wrb)
variable v : mem_out_type;
variable intermediate : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v.ctrl_wrb := mem_i.ctrl_wrb;
if mem_i.branch = '1' then
-- set alu result for branch and load instructions
v.alu_result := sign_extend(mem_i.program_counter, '0', 32);
else
v.alu_result := mem_i.alu_result;
end if;
-- Forward memory result
if CFG_MEM_FWD_WRB = true and ( r.ctrl_mem_wrb.mem_read and compare(mem_i.ctrl_wrb.reg_d, r.ctrl_wrb.reg_d)) = '1' then
intermediate := align_mem_load(mem_i.mem_result, r.ctrl_mem_wrb.transfer_size, r.alu_result(1 downto 0));
mem_result <= align_mem_store(intermediate, mem_i.ctrl_mem.transfer_size);
else
mem_result <= mem_i.dat_d;
end if;
v.ctrl_mem_wrb.mem_read := mem_i.ctrl_mem.mem_read;
v.ctrl_mem_wrb.transfer_size := mem_i.ctrl_mem.transfer_size;
rin <= v;
end process;
mem_seq: process(clk_i)
procedure proc_mem_reset is
begin
r.alu_result <= (others => '0');
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
r.ctrl_mem_wrb.mem_read <= '0';
r.ctrl_mem_wrb.transfer_size <= WORD;
end procedure proc_mem_reset;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_mem_reset;
elsif ena_i = '1' then
r <= rin;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 2534c7335fbe37083374ca44aa163327 | 0.530303 | 3.570784 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502/vhdl_source/proc_control.vhd | 1 | 15,856 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
entity proc_control is
port (
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
interrupt : in std_logic;
i_reg : in std_logic_vector(7 downto 0);
index_carry : in std_logic;
pc_carry : in std_logic;
branch_taken : in boolean;
sync : out std_logic;
dummy_cycle : out std_logic;
latch_dreg : out std_logic;
copy_d2p : out std_logic;
reg_update : out std_logic;
rwn : out std_logic;
vect_bit : out std_logic := '0';
set_i_flag : out std_logic;
vectoring : out std_logic;
a16 : out std_logic;
a_mux : out t_amux := c_amux_pc;
dout_mux : out t_dout_mux;
pc_oper : out t_pc_oper;
s_oper : out t_sp_oper;
adl_oper : out t_adl_oper;
adh_oper : out t_adh_oper );
end proc_control;
architecture gideon of proc_control is
type t_state is (fetch, decode, absolute, abs_hi, abs_fix, branch, branch_fix,
indir1, indir2, jump_sub, jump, retrn, rmw1, rmw2, vector, startup,
zp, zp_idx, zp_indir, push1, push2, push3, pull1, pull2, pull3 );
signal state : t_state;
signal next_state : t_state;
signal next_cp_p : std_logic;
signal next_rwn : std_logic;
signal next_dreg : std_logic;
signal next_amux : t_amux;
signal next_dout : t_dout_mux;
signal next_dummy : std_logic;
signal vectoring_i : std_logic;
begin
-- combinatroial process
process(state, i_reg, index_carry, pc_carry, branch_taken, interrupt, vectoring_i)
variable v_stack_idx : std_logic_vector(1 downto 0);
begin
-- defaults
sync <= '0';
pc_oper <= increment;
next_amux <= c_amux_pc;
next_rwn <= '1';
next_state <= state;
adl_oper <= keep;
adh_oper <= keep;
s_oper <= keep;
next_dreg <= '1';
next_cp_p <= '0';
next_dout <= reg_d;
next_dummy <= '0';
v_stack_idx := stack_idx(i_reg);
case state is
when fetch =>
sync <= '1';
if interrupt='1' then
pc_oper <= keep;
next_rwn <= '0';
next_dout <= reg_pch;
next_state <= push1;
next_amux <= c_amux_stack;
else
next_state <= decode;
end if;
when decode =>
adl_oper <= load_bus;
adh_oper <= clear;
if is_absolute(i_reg) then
if is_abs_jump(i_reg) then
next_state <= jump;
else
next_state <= absolute;
end if;
elsif is_implied(i_reg) then
pc_oper <= keep;
if is_stack(i_reg) then -- PHP, PLP, PHA, PLA
next_amux <= c_amux_stack;
case v_stack_idx is
when "00" => -- PHP
next_state <= push3;
next_rwn <= '0';
next_dout <= reg_flags;
when "10" => -- PHA
next_state <= push3;
next_rwn <= '0';
next_dout <= reg_accu;
when others =>
next_state <= pull1;
end case;
else
next_state <= fetch;
end if;
elsif is_zeropage(i_reg) then
next_amux <= c_amux_addr;
if is_indirect(i_reg) then
if is_postindexed(i_reg) then
next_state <= zp_indir;
else
next_state <= zp;
next_dummy <= '1';
end if;
else
next_state <= zp;
if is_store(i_reg) and not is_postindexed(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
end if;
elsif is_relative(i_reg) then
next_state <= branch;
elsif is_stack(i_reg) then -- non-implied stack operations like BRK, JSR, RTI and RTS
next_amux <= c_amux_stack;
case v_stack_idx is
when c_stack_idx_brk =>
next_rwn <= '0';
next_dout <= reg_pch;
next_state <= push1;
when c_stack_idx_jsr =>
next_dreg <= '0';
next_dout <= reg_pch;
next_state <= jump_sub;
when c_stack_idx_rti =>
next_state <= pull1;
when c_stack_idx_rts =>
next_state <= pull2;
when others =>
null;
end case;
elsif is_immediate(i_reg) then
next_state <= fetch;
end if;
when absolute =>
next_state <= abs_hi;
next_amux <= c_amux_addr;
adh_oper <= load_bus;
if is_postindexed(i_reg) then
adl_oper <= add_idx;
elsif not is_zeropage(i_reg) then
if is_store(i_reg) then
next_rwn <='0';
next_dout <= reg_axy;
end if;
end if;
if is_zeropage(i_reg) then
pc_oper <= keep;
else
pc_oper <= increment;
end if;
when abs_hi =>
pc_oper <= keep;
if is_postindexed(i_reg) then
if is_load(i_reg) and index_carry='0' then
next_amux <= c_amux_pc;
next_state <= fetch;
else
next_amux <= c_amux_addr;
next_state <= abs_fix;
if index_carry='1' then
adh_oper <= increment;
end if;
end if;
if is_store(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
else -- not post-indexed
if is_jump(i_reg) then
next_amux <= c_amux_addr;
next_state <= jump;
adl_oper <= increment;
elsif is_rmw(i_reg) then
next_rwn <= '0';
next_dout <= reg_d;
next_dummy <= '1';
next_state <= rmw1;
next_amux <= c_amux_addr;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
end if;
when abs_fix =>
pc_oper <= keep;
if is_rmw(i_reg) then
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= reg_d;
next_dummy <= '1';
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when branch =>
next_amux <= c_amux_pc;
if branch_taken then
pc_oper <= from_alu; -- add offset
next_state <= branch_fix;
else
pc_oper <= increment;
next_state <= decode;
sync <= '1';
end if;
when branch_fix =>
next_amux <= c_amux_pc;
if pc_carry='1' then
next_state <= fetch;
pc_oper <= keep; -- this will fix the PCH, since the carry is set
else
sync <= '1';
next_state <= decode;
pc_oper <= increment;
end if;
when indir1 =>
pc_oper <= keep;
next_state <= indir2;
next_amux <= c_amux_addr;
adl_oper <= copy_dreg;
adh_oper <= load_bus;
if is_store(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
when indir2 =>
pc_oper <= keep;
if is_rmw(i_reg) then
next_dummy <= '1';
next_rwn <= '0';
next_dout <= reg_d;
next_state <= rmw1;
next_amux <= c_amux_addr;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when jump_sub =>
next_state <= push1;
pc_oper <= keep;
next_dout <= reg_pch;
next_rwn <= '0';
next_dreg <= '0';
next_amux <= c_amux_stack;
when jump =>
pc_oper <= copy;
next_amux <= c_amux_pc;
if is_stack(i_reg) and v_stack_idx=c_stack_idx_rts and vectoring_i='0' then
next_state <= retrn;
else
next_state <= fetch;
end if;
when retrn =>
pc_oper <= increment;
next_state <= fetch;
when pull1 =>
s_oper <= increment;
next_state <= pull2;
next_amux <= c_amux_stack;
pc_oper <= keep;
when pull2 =>
pc_oper <= keep;
if is_implied(i_reg) then
next_state <= fetch;
next_amux <= c_amux_pc;
next_cp_p <= not v_stack_idx(1); -- only for PLP
else -- it was a stack operation, but not implied (RTS/RTI)
s_oper <= increment;
next_state <= pull3;
next_amux <= c_amux_stack;
next_cp_p <= not v_stack_idx(0); -- only for RTI
end if;
when pull3 =>
pc_oper <= keep;
s_oper <= increment;
next_state <= jump;
next_amux <= c_amux_stack;
when push1 =>
pc_oper <= keep;
s_oper <= decrement;
next_state <= push2;
next_amux <= c_amux_stack;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_pcl;
when push2 =>
pc_oper <= keep;
s_oper <= decrement;
if (v_stack_idx=c_stack_idx_jsr) and vectoring_i='0' then
next_state <= jump;
next_amux <= c_amux_pc;
else
next_state <= push3;
next_rwn <= '0';
next_dout <= reg_flags;
next_amux <= c_amux_stack;
end if;
when push3 =>
pc_oper <= keep;
s_oper <= decrement;
if is_implied(i_reg) and vectoring_i='0' then -- PHP, PHA
next_amux <= c_amux_pc;
next_state <= fetch;
else
next_state <= vector;
next_amux <= c_amux_vector;
end if;
when rmw1 =>
pc_oper <= keep;
next_state <= rmw2;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= shift_res;
when rmw2 =>
pc_oper <= keep;
next_state <= fetch;
next_amux <= c_amux_pc;
when vector =>
next_state <= jump;
pc_oper <= keep;
next_amux <= c_amux_vector;
when startup =>
next_state <= vector;
pc_oper <= keep;
next_amux <= c_amux_vector;
when zp =>
pc_oper <= keep;
if is_postindexed(i_reg) or is_indirect(i_reg) then
adl_oper <= add_idx;
next_state <= zp_idx;
next_amux <= c_amux_addr;
if is_postindexed(i_reg) and is_store(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
elsif is_rmw(i_reg) then
next_dummy <= '1';
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= reg_d;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when zp_idx =>
pc_oper <= keep;
if is_indirect(i_reg) then
next_state <= indir1;
adl_oper <= increment;
next_amux <= c_amux_addr;
elsif is_rmw(i_reg) then
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= reg_d;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when zp_indir =>
pc_oper <= keep;
next_state <= absolute;
next_amux <= c_amux_addr;
adl_oper <= increment;
when others =>
null;
end case;
end process;
reg_update <= '1' when (state = fetch) and vectoring_i='0' and
not is_stack(i_reg) and not is_relative(i_reg) else '0';
set_i_flag <= '1' when state = vector else '0';
vect_bit <= '0' when state = vector else '1';
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
state <= next_state;
a_mux <= next_amux;
dout_mux <= next_dout;
rwn <= next_rwn;
latch_dreg <= next_dreg and next_rwn; -- disable dreg latch for writes
copy_d2p <= next_cp_p;
dummy_cycle <= next_dummy;
if next_amux = c_amux_vector or next_amux = c_amux_pc then
a16 <= '1';
else
a16 <= '0';
end if;
if state = fetch then
vectoring_i <= interrupt;
end if;
end if;
if reset='1' then
a16 <= '1';
state <= startup; --vector;
a_mux <= c_amux_vector;
rwn <= '1';
latch_dreg <= '1';
dout_mux <= reg_d;
copy_d2p <= '0';
vectoring_i <= '0';
dummy_cycle <= '0';
end if;
end if;
end process;
vectoring <= vectoring_i;
end architecture;
| gpl-3.0 | b941a6c72fa31a87f71990a0a9add70a | 0.377586 | 4.214779 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_cmd_nano.vhd | 1 | 3,236 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_cmd_nano
-- Date:2015-02-14
-- Author: Gideon
-- Description: I/O registers for controlling commands directly, 16 bits for
-- attachment to nano cpu.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_cmd_pkg.all;
entity usb_cmd_nano is
port (
clock : in std_logic;
reset : in std_logic;
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
cmd_req : out t_usb_cmd_req;
cmd_resp : in t_usb_cmd_resp );
end entity;
architecture arch of usb_cmd_nano is
signal done_latch : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if cmd_resp.done = '1' then
cmd_req.request <= '0';
done_latch <= '1';
end if;
if io_write = '1' then
case io_addr is
when X"60" => -- command request
cmd_req.request <= '1';
done_latch <= '0';
cmd_req.togglebit <= io_wdata(11);
--cmd_req.do_split <= io_wdata(7);
cmd_req.do_data <= io_wdata(6);
cmd_req.command <= c_usb_commands_decoded(to_integer(unsigned(io_wdata(2 downto 0))));
when X"61" => -- data buffer control
cmd_req.buffer_index <= unsigned(io_wdata(15 downto 14));
cmd_req.no_data <= io_wdata(13);
cmd_req.data_length(9 downto 0) <= unsigned(io_wdata(9 downto 0));
when X"62" => -- device/endpoint
cmd_req.device_addr <= unsigned(io_wdata(14 downto 8));
cmd_req.endp_addr <= unsigned(io_wdata(3 downto 0));
when X"63" => -- split info
cmd_req.do_split <= io_wdata(15);
cmd_req.split_hub_addr <= unsigned(io_wdata(14 downto 8));
cmd_req.split_port_addr <= unsigned(io_wdata(3 downto 0));
cmd_req.split_sc <= io_wdata(7);
cmd_req.split_sp <= io_wdata(6);
cmd_req.split_et <= io_wdata(5 downto 4);
when others =>
null;
end case;
end if;
if reset='1' then
done_latch <= '0';
cmd_req.request <= '0';
end if;
end if;
end process;
process(cmd_resp, done_latch)
begin
io_rdata(15) <= done_latch;
io_rdata(14 downto 12) <= std_logic_vector(to_unsigned(t_usb_result'pos(cmd_resp.result), 3));
io_rdata(11) <= cmd_resp.togglebit;
io_rdata(10) <= cmd_resp.no_data;
io_rdata(9 downto 0) <= std_logic_vector(cmd_resp.data_length(9 downto 0));
end process;
end arch;
| gpl-3.0 | f3e91e43df908a1a640fefebbeba8490 | 0.468789 | 3.852381 | false | false | false | false |
bgunebakan/toyrobot | counter.vhd | 1 | 1,400 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:30:59 12/18/2014
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Counter is
generic(n: POSITIVE := 10);
Port ( clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
Counter_output : out STD_LOGIC_VECTOR (n-1 downto 0));
end Counter;
architecture Behavioral of Counter is
signal count: STD_LOGIC_VECTOR(n-1 downto 0);
begin
process(clk,reset)
begin
if(reset='0') then
count <= (others => '0');
elsif(clk'event and clk='1') then
if(enable='1') then
count <= count+1;
end if;
end if;
end process;
Counter_output <= count;
end Behavioral;
| gpl-2.0 | 4fa2e87eb1b5949a63ae22a1172c2ff7 | 0.583571 | 3.743316 | false | false | false | false |
asicguy/crash | fpga/src/ps_pl_interface/ps_pl_interface.vhd | 2 | 80,812 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: ps_pl_interface.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Interfaces the Processing System (PS) with the
-- Programmable Logic (PL) via the AXI ACP bus and
-- an AXI Datamover IP core. Includes a AXI-Stream 8x8
-- interconnect.
--
-- The destination of each interface matches its enumeration,
-- i.e. slave 1's tdest = "001". The master transfers data to
-- a slave by setting tdest and then asserting tvalid. Each
-- slave port arbitrates when tlast is asserted.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ps_pl_interface is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff");
port (
-- AXIS Stream Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- AXI-Lite Slave bus for access to control & status registers
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI ACP Bus to interface with processor system
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
-- Interrupt on successfully completed AXI ACP writes
irq : out std_logic;
-- Global reset for all accelerators
rst_glb_n : out std_logic;
-- Accelerator interfaces
-- Note: Master & Slave 0 are not listed as the Datamover componeent
-- uses both.
-- Accelerator 1
axis_master_1_tvalid : in std_logic;
axis_master_1_tready : out std_logic;
axis_master_1_tdata : in std_logic_vector(63 downto 0);
axis_master_1_tdest : in std_logic_vector(2 downto 0);
axis_master_1_tlast : in std_logic;
axis_master_1_irq : in std_logic;
axis_slave_1_tvalid : out std_logic;
axis_slave_1_tready : in std_logic;
axis_slave_1_tdata : out std_logic_vector(63 downto 0);
axis_slave_1_tid : out std_logic_vector(2 downto 0);
axis_slave_1_tlast : out std_logic;
axis_slave_1_irq : in std_logic;
status_1_addr : out std_logic_vector(7 downto 0);
status_1_data : in std_logic_vector(31 downto 0);
status_1_stb : out std_logic;
ctrl_1_addr : out std_logic_vector(7 downto 0);
ctrl_1_data : out std_logic_vector(31 downto 0);
ctrl_1_stb : out std_logic;
-- Accelerator 2
axis_master_2_tvalid : in std_logic;
axis_master_2_tready : out std_logic;
axis_master_2_tdata : in std_logic_vector(63 downto 0);
axis_master_2_tdest : in std_logic_vector(2 downto 0);
axis_master_2_tlast : in std_logic;
axis_master_2_irq : in std_logic;
axis_slave_2_tvalid : out std_logic;
axis_slave_2_tready : in std_logic;
axis_slave_2_tdata : out std_logic_vector(63 downto 0);
axis_slave_2_tid : out std_logic_vector(2 downto 0);
axis_slave_2_tlast : out std_logic;
axis_slave_2_irq : in std_logic;
status_2_addr : out std_logic_vector(7 downto 0);
status_2_data : in std_logic_vector(31 downto 0);
status_2_stb : out std_logic;
ctrl_2_addr : out std_logic_vector(7 downto 0);
ctrl_2_data : out std_logic_vector(31 downto 0);
ctrl_2_stb : out std_logic;
-- Accelerator 3
axis_master_3_tvalid : in std_logic;
axis_master_3_tready : out std_logic;
axis_master_3_tdata : in std_logic_vector(63 downto 0);
axis_master_3_tdest : in std_logic_vector(2 downto 0);
axis_master_3_tlast : in std_logic;
axis_master_3_irq : in std_logic;
axis_slave_3_tvalid : out std_logic;
axis_slave_3_tready : in std_logic;
axis_slave_3_tdata : out std_logic_vector(63 downto 0);
axis_slave_3_tid : out std_logic_vector(2 downto 0);
axis_slave_3_tlast : out std_logic;
axis_slave_3_irq : in std_logic;
status_3_addr : out std_logic_vector(7 downto 0);
status_3_data : in std_logic_vector(31 downto 0);
status_3_stb : out std_logic;
ctrl_3_addr : out std_logic_vector(7 downto 0);
ctrl_3_data : out std_logic_vector(31 downto 0);
ctrl_3_stb : out std_logic;
-- Accelerator 4
axis_master_4_tvalid : in std_logic;
axis_master_4_tready : out std_logic;
axis_master_4_tdata : in std_logic_vector(63 downto 0);
axis_master_4_tdest : in std_logic_vector(2 downto 0);
axis_master_4_tlast : in std_logic;
axis_master_4_irq : in std_logic;
axis_slave_4_tvalid : out std_logic;
axis_slave_4_tready : in std_logic;
axis_slave_4_tdata : out std_logic_vector(63 downto 0);
axis_slave_4_tid : out std_logic_vector(2 downto 0);
axis_slave_4_tlast : out std_logic;
axis_slave_4_irq : in std_logic;
status_4_addr : out std_logic_vector(7 downto 0);
status_4_data : in std_logic_vector(31 downto 0);
status_4_stb : out std_logic;
ctrl_4_addr : out std_logic_vector(7 downto 0);
ctrl_4_data : out std_logic_vector(31 downto 0);
ctrl_4_stb : out std_logic;
-- Accelerator 5
axis_master_5_tvalid : in std_logic;
axis_master_5_tready : out std_logic;
axis_master_5_tdata : in std_logic_vector(63 downto 0);
axis_master_5_tdest : in std_logic_vector(2 downto 0);
axis_master_5_tlast : in std_logic;
axis_master_5_irq : in std_logic;
axis_slave_5_tvalid : out std_logic;
axis_slave_5_tready : in std_logic;
axis_slave_5_tdata : out std_logic_vector(63 downto 0);
axis_slave_5_tid : out std_logic_vector(2 downto 0);
axis_slave_5_tlast : out std_logic;
axis_slave_5_irq : in std_logic;
status_5_addr : out std_logic_vector(7 downto 0);
status_5_data : in std_logic_vector(31 downto 0);
status_5_stb : out std_logic;
ctrl_5_addr : out std_logic_vector(7 downto 0);
ctrl_5_data : out std_logic_vector(31 downto 0);
ctrl_5_stb : out std_logic;
-- Accelerator 6
axis_master_6_tvalid : in std_logic;
axis_master_6_tready : out std_logic;
axis_master_6_tdata : in std_logic_vector(63 downto 0);
axis_master_6_tdest : in std_logic_vector(2 downto 0);
axis_master_6_tlast : in std_logic;
axis_master_6_irq : in std_logic;
axis_slave_6_tvalid : out std_logic;
axis_slave_6_tready : in std_logic;
axis_slave_6_tdata : out std_logic_vector(63 downto 0);
axis_slave_6_tid : out std_logic_vector(2 downto 0);
axis_slave_6_tlast : out std_logic;
axis_slave_6_irq : in std_logic;
status_6_addr : out std_logic_vector(7 downto 0);
status_6_data : in std_logic_vector(31 downto 0);
status_6_stb : out std_logic;
ctrl_6_addr : out std_logic_vector(7 downto 0);
ctrl_6_data : out std_logic_vector(31 downto 0);
ctrl_6_stb : out std_logic;
-- Accelerator 7
axis_master_7_tvalid : in std_logic;
axis_master_7_tready : out std_logic;
axis_master_7_tdata : in std_logic_vector(63 downto 0);
axis_master_7_tdest : in std_logic_vector(2 downto 0);
axis_master_7_tlast : in std_logic;
axis_master_7_irq : in std_logic;
axis_slave_7_tvalid : out std_logic;
axis_slave_7_tready : in std_logic;
axis_slave_7_tdata : out std_logic_vector(63 downto 0);
axis_slave_7_tid : out std_logic_vector(2 downto 0);
axis_slave_7_tlast : out std_logic;
axis_slave_7_irq : in std_logic;
status_7_addr : out std_logic_vector(7 downto 0);
status_7_data : in std_logic_vector(31 downto 0);
status_7_stb : out std_logic;
ctrl_7_addr : out std_logic_vector(7 downto 0);
ctrl_7_data : out std_logic_vector(31 downto 0);
ctrl_7_stb : out std_logic);
end entity;
architecture RTL of ps_pl_interface is
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component axi_lite_to_parallel_bus is
generic (
-- 32K word address space
C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff");
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
read_addr : out std_logic_vector(14 downto 0);
read_data : in std_logic_vector(31 downto 0);
read_stb : out std_logic;
write_addr : out std_logic_vector(14 downto 0);
write_data : out std_logic_vector(31 downto 0);
write_stb : out std_logic);
end component;
component xlnx_axi_datamover is
port (
m_axi_mm2s_aclk : in std_logic;
m_axi_mm2s_aresetn : in std_logic;
mm2s_halt : in std_logic;
mm2s_halt_cmplt : out std_logic;
mm2s_err : out std_logic;
m_axis_mm2s_cmdsts_aclk : in std_logic;
m_axis_mm2s_cmdsts_aresetn : in std_logic;
s_axis_mm2s_cmd_tvalid : in std_logic;
s_axis_mm2s_cmd_tready : out std_logic;
s_axis_mm2s_cmd_tdata : in std_logic_vector(71 downto 0);
m_axis_mm2s_sts_tvalid : out std_logic;
m_axis_mm2s_sts_tready : in std_logic;
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0);
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0);
m_axis_mm2s_sts_tlast : out std_logic;
mm2s_allow_addr_req : in std_logic;
mm2s_addr_req_posted : out std_logic;
mm2s_rd_xfer_cmplt : out std_logic;
m_axi_mm2s_arid : out std_logic_vector(3 downto 0);
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(63 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(7 downto 0);
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
mm2s_dbg_sel : in std_logic_vector( 3 downto 0);
mm2s_dbg_data : out std_logic_vector(31 downto 0) ;
m_axi_s2mm_aclk : in std_logic;
m_axi_s2mm_aresetn : in std_logic;
s2mm_halt : in std_logic;
s2mm_halt_cmplt : out std_logic;
s2mm_err : out std_logic;
m_axis_s2mm_cmdsts_awclk : in std_logic;
m_axis_s2mm_cmdsts_aresetn : in std_logic;
s_axis_s2mm_cmd_tvalid : in std_logic;
s_axis_s2mm_cmd_tready : out std_logic;
s_axis_s2mm_cmd_tdata : in std_logic_vector(71 downto 0);
m_axis_s2mm_sts_tvalid : out std_logic;
m_axis_s2mm_sts_tready : in std_logic;
m_axis_s2mm_sts_tdata : out std_logic_vector(7 downto 0);
m_axis_s2mm_sts_tkeep : out std_logic_vector(0 downto 0);
m_axis_s2mm_sts_tlast : out std_logic;
s2mm_allow_addr_req : in std_logic;
s2mm_addr_req_posted : out std_logic;
s2mm_wr_xfer_cmplt : out std_logic;
s2mm_ld_nxt_len : out std_logic;
s2mm_wr_len : out std_logic_vector(7 downto 0);
m_axi_s2mm_awid : out std_logic_vector(3 downto 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(63 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(7 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(63 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(7 downto 0);
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s2mm_dbg_sel : in std_logic_vector( 3 downto 0);
s2mm_dbg_data : out std_logic_vector(31 downto 0));
end component;
component fifo_72x64
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(71 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(71 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
component fifo_8x64
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(7 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(7 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
component axis_interconnect_8x8
port (
aclk : in std_logic;
aresetn : in std_logic;
s00_axis_aclk : in std_logic;
s01_axis_aclk : in std_logic;
s02_axis_aclk : in std_logic;
s03_axis_aclk : in std_logic;
s04_axis_aclk : in std_logic;
s05_axis_aclk : in std_logic;
s06_axis_aclk : in std_logic;
s07_axis_aclk : in std_logic;
s00_axis_aresetn : in std_logic;
s01_axis_aresetn : in std_logic;
s02_axis_aresetn : in std_logic;
s03_axis_aresetn : in std_logic;
s04_axis_aresetn : in std_logic;
s05_axis_aresetn : in std_logic;
s06_axis_aresetn : in std_logic;
s07_axis_aresetn : in std_logic;
s00_axis_tvalid : in std_logic;
s01_axis_tvalid : in std_logic;
s02_axis_tvalid : in std_logic;
s03_axis_tvalid : in std_logic;
s04_axis_tvalid : in std_logic;
s05_axis_tvalid : in std_logic;
s06_axis_tvalid : in std_logic;
s07_axis_tvalid : in std_logic;
s00_axis_tready : out std_logic;
s01_axis_tready : out std_logic;
s02_axis_tready : out std_logic;
s03_axis_tready : out std_logic;
s04_axis_tready : out std_logic;
s05_axis_tready : out std_logic;
s06_axis_tready : out std_logic;
s07_axis_tready : out std_logic;
s00_axis_tdata : in std_logic_vector(63 downto 0);
s01_axis_tdata : in std_logic_vector(63 downto 0);
s02_axis_tdata : in std_logic_vector(63 downto 0);
s03_axis_tdata : in std_logic_vector(63 downto 0);
s04_axis_tdata : in std_logic_vector(63 downto 0);
s05_axis_tdata : in std_logic_vector(63 downto 0);
s06_axis_tdata : in std_logic_vector(63 downto 0);
s07_axis_tdata : in std_logic_vector(63 downto 0);
s00_axis_tlast : in std_logic;
s01_axis_tlast : in std_logic;
s02_axis_tlast : in std_logic;
s03_axis_tlast : in std_logic;
s04_axis_tlast : in std_logic;
s05_axis_tlast : in std_logic;
s06_axis_tlast : in std_logic;
s07_axis_tlast : in std_logic;
s00_axis_tdest : in std_logic_vector(2 downto 0);
s01_axis_tdest : in std_logic_vector(2 downto 0);
s02_axis_tdest : in std_logic_vector(2 downto 0);
s03_axis_tdest : in std_logic_vector(2 downto 0);
s04_axis_tdest : in std_logic_vector(2 downto 0);
s05_axis_tdest : in std_logic_vector(2 downto 0);
s06_axis_tdest : in std_logic_vector(2 downto 0);
s07_axis_tdest : in std_logic_vector(2 downto 0);
s00_axis_tid : in std_logic_vector(2 downto 0);
s01_axis_tid : in std_logic_vector(2 downto 0);
s02_axis_tid : in std_logic_vector(2 downto 0);
s03_axis_tid : in std_logic_vector(2 downto 0);
s04_axis_tid : in std_logic_vector(2 downto 0);
s05_axis_tid : in std_logic_vector(2 downto 0);
s06_axis_tid : in std_logic_vector(2 downto 0);
s07_axis_tid : in std_logic_vector(2 downto 0);
m00_axis_aclk : in std_logic;
m01_axis_aclk : in std_logic;
m02_axis_aclk : in std_logic;
m03_axis_aclk : in std_logic;
m04_axis_aclk : in std_logic;
m05_axis_aclk : in std_logic;
m06_axis_aclk : in std_logic;
m07_axis_aclk : in std_logic;
m00_axis_aresetn : in std_logic;
m01_axis_aresetn : in std_logic;
m02_axis_aresetn : in std_logic;
m03_axis_aresetn : in std_logic;
m04_axis_aresetn : in std_logic;
m05_axis_aresetn : in std_logic;
m06_axis_aresetn : in std_logic;
m07_axis_aresetn : in std_logic;
m00_axis_tvalid : out std_logic;
m01_axis_tvalid : out std_logic;
m02_axis_tvalid : out std_logic;
m03_axis_tvalid : out std_logic;
m04_axis_tvalid : out std_logic;
m05_axis_tvalid : out std_logic;
m06_axis_tvalid : out std_logic;
m07_axis_tvalid : out std_logic;
m00_axis_tready : in std_logic;
m01_axis_tready : in std_logic;
m02_axis_tready : in std_logic;
m03_axis_tready : in std_logic;
m04_axis_tready : in std_logic;
m05_axis_tready : in std_logic;
m06_axis_tready : in std_logic;
m07_axis_tready : in std_logic;
m00_axis_tdata : out std_logic_vector(63 downto 0);
m01_axis_tdata : out std_logic_vector(63 downto 0);
m02_axis_tdata : out std_logic_vector(63 downto 0);
m03_axis_tdata : out std_logic_vector(63 downto 0);
m04_axis_tdata : out std_logic_vector(63 downto 0);
m05_axis_tdata : out std_logic_vector(63 downto 0);
m06_axis_tdata : out std_logic_vector(63 downto 0);
m07_axis_tdata : out std_logic_vector(63 downto 0);
m00_axis_tlast : out std_logic;
m01_axis_tlast : out std_logic;
m02_axis_tlast : out std_logic;
m03_axis_tlast : out std_logic;
m04_axis_tlast : out std_logic;
m05_axis_tlast : out std_logic;
m06_axis_tlast : out std_logic;
m07_axis_tlast : out std_logic;
m00_axis_tdest : out std_logic_vector(2 downto 0);
m01_axis_tdest : out std_logic_vector(2 downto 0);
m02_axis_tdest : out std_logic_vector(2 downto 0);
m03_axis_tdest : out std_logic_vector(2 downto 0);
m04_axis_tdest : out std_logic_vector(2 downto 0);
m05_axis_tdest : out std_logic_vector(2 downto 0);
m06_axis_tdest : out std_logic_vector(2 downto 0);
m07_axis_tdest : out std_logic_vector(2 downto 0);
m00_axis_tid : out std_logic_vector(2 downto 0);
m01_axis_tid : out std_logic_vector(2 downto 0);
m02_axis_tid : out std_logic_vector(2 downto 0);
m03_axis_tid : out std_logic_vector(2 downto 0);
m04_axis_tid : out std_logic_vector(2 downto 0);
m05_axis_tid : out std_logic_vector(2 downto 0);
m06_axis_tid : out std_logic_vector(2 downto 0);
m07_axis_tid : out std_logic_vector(2 downto 0);
s00_decode_err : out std_logic;
s01_decode_err : out std_logic;
s02_decode_err : out std_logic;
s03_decode_err : out std_logic;
s04_decode_err : out std_logic;
s05_decode_err : out std_logic;
s06_decode_err : out std_logic;
s07_decode_err : out std_logic);
end component;
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
type slv_256x32 is array(0 to 255) of std_logic_vector(31 downto 0);
type slv_8x72 is array(0 to 7) of std_logic_vector(71 downto 0);
signal ctrl_0_reg : slv_256x32 := (others=>(others=>'0'));
signal status_0_reg : slv_256x32 := (others=>(others=>'0'));
signal ctrl_127_reg : slv_256x32 := (others=>(others=>'0'));
signal status_127_reg : slv_256x32 := (others=>(others=>'0'));
signal ctrl_0_stb_dly : std_logic;
signal status_0_addr : std_logic_vector(7 downto 0);
signal status_0_data : std_logic_vector(31 downto 0);
signal status_0_stb : std_logic;
signal ctrl_0_addr : std_logic_vector(7 downto 0);
signal ctrl_0_data : std_logic_vector(31 downto 0);
signal ctrl_0_stb : std_logic;
signal status_127_addr : std_logic_vector(7 downto 0);
signal status_127_data : std_logic_vector(31 downto 0);
signal status_127_stb : std_logic;
signal ctrl_127_addr : std_logic_vector(7 downto 0);
signal ctrl_127_data : std_logic_vector(31 downto 0);
signal ctrl_127_stb : std_logic;
signal status_id : std_logic_vector(6 downto 0);
signal ctrl_id : std_logic_vector(6 downto 0);
signal read_addr : std_logic_vector(14 downto 0);
signal read_data : std_logic_vector(31 downto 0);
signal read_stb : std_logic;
signal write_addr : std_logic_vector(14 downto 0);
signal write_data : std_logic_vector(31 downto 0);
signal write_stb : std_logic;
signal rst_global_n : std_logic;
signal rst_global : std_logic;
signal rst_mm2s_cmd_fifo : std_logic;
signal rst_s2mm_cmd_fifo : std_logic;
signal rst_sts_fifo : std_logic;
signal mm2s_cmd_fifo_loop : std_logic_vector(7 downto 0);
signal s2mm_cmd_fifo_loop : std_logic_vector(7 downto 0);
signal sts_fifo_auto_read : std_logic;
signal irq_s2mm_en : std_logic;
signal irq_mm2s_en : std_logic;
signal irq_axis_master_en : std_logic_vector(7 downto 0);
signal irq_axis_slave_en : std_logic_vector(7 downto 0);
signal mm2s_cmd_addr : std_logic_vector(31 downto 0);
signal mm2s_cmd_seq_num : std_logic_vector(11 downto 0);
signal mm2s_cmd_size : std_logic_vector(22 downto 0);
signal mm2s_cmd_cache : std_logic_vector(3 downto 0);
signal mm2s_cmd_tdest : std_logic_vector(2 downto 0);
signal mm2s_cmd_en : std_logic;
signal s2mm_cmd_addr : std_logic_vector(31 downto 0);
signal s2mm_cmd_seq_num : std_logic_vector(11 downto 0);
signal s2mm_cmd_size : std_logic_vector(22 downto 0);
signal s2mm_cmd_cache : std_logic_vector(3 downto 0);
signal s2mm_cmd_tid : std_logic_vector(2 downto 0);
signal s2mm_cmd_en : std_logic;
signal mm2s_err : std_logic;
signal axis_mm2s_cmd_tvalid : std_logic;
signal axis_mm2s_cmd_tready : std_logic;
signal axis_mm2s_cmd_tdata : std_logic_vector(71 downto 0);
signal axis_mm2s_sts_tvalid : std_logic;
signal axis_mm2s_sts_tdata : std_logic_vector(7 downto 0);
signal axis_mm2s_tdata : std_logic_vector(63 downto 0);
signal axis_mm2s_tkeep : std_logic_vector(7 downto 0);
signal axis_mm2s_tlast : std_logic;
signal axis_mm2s_tvalid : std_logic;
signal axis_mm2s_tready : std_logic;
signal axis_mm2s_tdest : std_logic_vector(2 downto 0);
signal mm2s_rd_xfer_cmplt : std_logic;
signal s2mm_err : std_logic;
signal axis_s2mm_cmd_tvalid : std_logic;
signal axis_s2mm_cmd_tready : std_logic;
signal axis_s2mm_cmd_tdata : std_logic_vector(71 downto 0);
signal axis_s2mm_sts_tvalid : std_logic;
signal axis_s2mm_sts_tdata : std_logic_vector(7 downto 0);
signal axis_s2mm_tdata : std_logic_vector(63 downto 0);
signal axis_s2mm_tkeep : std_logic_vector(7 downto 0);
signal axis_s2mm_tlast : std_logic;
signal axis_s2mm_tvalid : std_logic;
signal axis_s2mm_tready : std_logic;
signal axis_s2mm_tid : std_logic_vector(2 downto 0);
signal s2mm_wr_xfer_cmplt : std_logic;
signal m00_fifo_data_count : std_logic_vector(31 downto 0);
signal mm2s_cmd_fifo_din : slv_8x72;
signal mm2s_cmd_fifo_wr_en : std_logic_vector(7 downto 0);
signal mm2s_cmd_fifo_rd_en : std_logic_vector(7 downto 0);
signal mm2s_cmd_fifo_dout : slv_8x72;
signal mm2s_cmd_fifo_full : std_logic_vector(7 downto 0);
signal mm2s_cmd_fifo_empty : std_logic_vector(7 downto 0);
signal s2mm_cmd_fifo_din : slv_8x72;
signal s2mm_cmd_fifo_wr_en : std_logic_vector(7 downto 0);
signal s2mm_cmd_fifo_rd_en : std_logic_vector(7 downto 0);
signal s2mm_cmd_fifo_dout : slv_8x72;
signal s2mm_cmd_fifo_full : std_logic_vector(7 downto 0);
signal s2mm_cmd_fifo_empty : std_logic_vector(7 downto 0);
signal mm2s_sts_fifo_rd_en : std_logic;
signal mm2s_sts_fifo_dout : std_logic_vector(7 downto 0);
signal mm2s_sts_fifo_full : std_logic;
signal mm2s_sts_fifo_empty : std_logic;
signal s2mm_sts_fifo_rd_en : std_logic;
signal s2mm_sts_fifo_dout : std_logic_vector(7 downto 0);
signal s2mm_sts_fifo_full : std_logic;
signal s2mm_sts_fifo_empty : std_logic;
signal mm2s_tdest : integer range 0 to 7;
signal mm2s_xfer_in_progress : std_logic;
signal s2mm_xfer_in_progress : std_logic;
signal mm2s_xfer_en : std_logic;
signal s2mm_xfer_en : std_logic;
signal s2mm_xfer_cnt : integer;
signal clear_s2mm_xfer_cnt : std_logic;
signal mm2s_xfer_cnt : integer;
signal clear_mm2s_xfer_cnt : std_logic;
signal irq_long_cnt : integer range 0 to 15;
signal irq_queue_cnt : integer range 0 to 31;
signal irq_concat : std_logic_vector(15 downto 0);
signal irq_reduce : std_logic;
signal axis_master_0_irq : std_logic;
signal axis_slave_0_irq : std_logic;
signal debug_counter : integer;
attribute keep : string;
attribute keep of mm2s_err : signal is "true";
attribute keep of s2mm_err : signal is "true";
attribute keep of mm2s_rd_xfer_cmplt : signal is "true";
attribute keep of s2mm_wr_xfer_cmplt : signal is "true";
begin
rst_global_n <= NOT(rst_global);
rst_glb_n <= rst_global_n;
proc_debug_count : process(clk,rst_global_n)
begin
if (rst_global_n = '0') then
debug_counter <= 0;
elsif rising_edge(clk) then
if (debug_counter = 2**30-1) then
debug_counter <= 0;
else
debug_counter <= debug_counter + 1;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Processor Interrupt Controller is on a different clock, so stretch the
-- interrupts 8 clock cycles to ensure it does no miss the pulse. Also
-- includes logic to count interrupts so none are missed in case they
-- occur simultaneously.
-------------------------------------------------------------------------------
proc_irq_stretch : process(clk,rst_global_n)
begin
if (rst_global_n = '0') then
irq_long_cnt <= 0;
irq_queue_cnt <= 0;
irq <= '0';
else
if rising_edge(clk) then
if (irq_reduce = '1') then
irq_queue_cnt <= irq_queue_cnt + 1;
end if;
if (irq_long_cnt = 0 AND irq_queue_cnt > 0) then
-- Reduce queue count, except in the case when
-- another irq occurs which would case no net
-- change.
if (irq_reduce = '0') then
irq_queue_cnt <= irq_queue_cnt - 1;
end if;
irq_long_cnt <= 15;
irq <= '1';
end if;
if (irq_long_cnt = 7) then
irq <= '0';
end if;
if (irq_long_cnt > 0) then
irq_long_cnt <= irq_long_cnt - 1;
end if;
end if;
end if;
end process;
irq_concat <= axis_master_0_irq & axis_slave_0_irq &
axis_master_1_irq & axis_slave_1_irq &
axis_master_2_irq & axis_slave_2_irq &
axis_master_3_irq & axis_slave_3_irq &
axis_master_4_irq & axis_slave_4_irq &
axis_master_5_irq & axis_slave_5_irq &
axis_master_6_irq & axis_slave_6_irq &
axis_master_7_irq & axis_slave_7_irq;
axis_master_0_irq <= axis_mm2s_sts_tvalid AND irq_mm2s_en;
axis_slave_0_irq <= axis_s2mm_sts_tvalid AND irq_s2mm_en;
irq_reduce <= '1' when irq_concat /= (irq_concat'length-1 downto 0 => '0') else
'0';
-------------------------------------------------------------------------------
-- Converts AXI-4 Lite interface to a simple parallel bus.
-- This interfaces with the control / status register banks.
-------------------------------------------------------------------------------
inst_axi_lite_to_parallel_bus : axi_lite_to_parallel_bus
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR)
port map (
S_AXI_ACLK => clk,
S_AXI_ARESETN => rst_n,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
read_addr => read_addr,
read_data => read_data,
read_stb => read_stb,
write_addr => write_addr,
write_data => write_data,
write_stb => write_stb);
read_data <= status_0_data when status_id = std_logic_vector(to_unsigned( 0,7)) else
status_1_data when status_id = std_logic_vector(to_unsigned( 1,7)) else
status_2_data when status_id = std_logic_vector(to_unsigned( 2,7)) else
status_3_data when status_id = std_logic_vector(to_unsigned( 3,7)) else
status_4_data when status_id = std_logic_vector(to_unsigned( 4,7)) else
status_5_data when status_id = std_logic_vector(to_unsigned( 5,7)) else
status_6_data when status_id = std_logic_vector(to_unsigned( 6,7)) else
status_7_data when status_id = std_logic_vector(to_unsigned( 7,7)) else
status_127_data when status_id = std_logic_vector(to_unsigned(127,7)) else
(others=>'0');
status_0_addr <= read_addr(7 downto 0);
status_1_addr <= read_addr(7 downto 0);
status_2_addr <= read_addr(7 downto 0);
status_3_addr <= read_addr(7 downto 0);
status_4_addr <= read_addr(7 downto 0);
status_5_addr <= read_addr(7 downto 0);
status_6_addr <= read_addr(7 downto 0);
status_7_addr <= read_addr(7 downto 0);
status_127_addr <= read_addr(7 downto 0);
status_id <= read_addr(14 downto 8);
status_0_stb <= '1' when read_stb = '1' AND status_id = std_logic_vector(to_unsigned( 0,7)) else '0';
status_1_stb <= '1' when read_stb = '1' AND status_id = std_logic_vector(to_unsigned( 1,7)) else '0';
status_2_stb <= '1' when read_stb = '1' AND status_id = std_logic_vector(to_unsigned( 2,7)) else '0';
status_3_stb <= '1' when read_stb = '1' AND status_id = std_logic_vector(to_unsigned( 3,7)) else '0';
status_4_stb <= '1' when read_stb = '1' AND status_id = std_logic_vector(to_unsigned( 4,7)) else '0';
status_5_stb <= '1' when read_stb = '1' AND status_id = std_logic_vector(to_unsigned( 5,7)) else '0';
status_6_stb <= '1' when read_stb = '1' AND status_id = std_logic_vector(to_unsigned( 6,7)) else '0';
status_7_stb <= '1' when read_stb = '1' AND status_id = std_logic_vector(to_unsigned( 7,7)) else '0';
status_127_stb <= '1' when read_stb = '1' AND status_id = std_logic_vector(to_unsigned(127,7)) else '0';
ctrl_0_addr <= write_addr(7 downto 0);
ctrl_1_addr <= write_addr(7 downto 0);
ctrl_2_addr <= write_addr(7 downto 0);
ctrl_3_addr <= write_addr(7 downto 0);
ctrl_4_addr <= write_addr(7 downto 0);
ctrl_5_addr <= write_addr(7 downto 0);
ctrl_6_addr <= write_addr(7 downto 0);
ctrl_7_addr <= write_addr(7 downto 0);
ctrl_127_addr <= write_addr(7 downto 0);
ctrl_id <= write_addr(14 downto 8);
ctrl_0_stb <= '1' when write_stb = '1' AND ctrl_id = std_logic_vector(to_unsigned( 0,7)) else '0';
ctrl_1_stb <= '1' when write_stb = '1' AND ctrl_id = std_logic_vector(to_unsigned( 1,7)) else '0';
ctrl_2_stb <= '1' when write_stb = '1' AND ctrl_id = std_logic_vector(to_unsigned( 2,7)) else '0';
ctrl_3_stb <= '1' when write_stb = '1' AND ctrl_id = std_logic_vector(to_unsigned( 3,7)) else '0';
ctrl_4_stb <= '1' when write_stb = '1' AND ctrl_id = std_logic_vector(to_unsigned( 4,7)) else '0';
ctrl_5_stb <= '1' when write_stb = '1' AND ctrl_id = std_logic_vector(to_unsigned( 5,7)) else '0';
ctrl_6_stb <= '1' when write_stb = '1' AND ctrl_id = std_logic_vector(to_unsigned( 6,7)) else '0';
ctrl_7_stb <= '1' when write_stb = '1' AND ctrl_id = std_logic_vector(to_unsigned( 7,7)) else '0';
ctrl_127_stb <= '1' when write_stb = '1' AND ctrl_id = std_logic_vector(to_unsigned(127,7)) else '0';
ctrl_0_data <= write_data;
ctrl_1_data <= write_data;
ctrl_2_data <= write_data;
ctrl_3_data <= write_data;
ctrl_4_data <= write_data;
ctrl_5_data <= write_data;
ctrl_6_data <= write_data;
ctrl_7_data <= write_data;
ctrl_127_data <= write_data;
-------------------------------------------------------------------------------
-- Converts AXI-4 to AXI-Stream and vice versa. This component is how the FPGA
-- accelerators read/write RAM and/or processor cache via AXI ACP.
-------------------------------------------------------------------------------
inst_xlnx_axi_datamover : xlnx_axi_datamover
port map (
m_axi_mm2s_aclk => clk,
m_axi_mm2s_aresetn => rst_global_n,
mm2s_halt => '0',
mm2s_halt_cmplt => open,
mm2s_err => mm2s_err,
m_axis_mm2s_cmdsts_aclk => clk,
m_axis_mm2s_cmdsts_aresetn => rst_global_n,
s_axis_mm2s_cmd_tvalid => axis_mm2s_cmd_tvalid,
s_axis_mm2s_cmd_tready => axis_mm2s_cmd_tready,
s_axis_mm2s_cmd_tdata => axis_mm2s_cmd_tdata,
m_axis_mm2s_sts_tvalid => axis_mm2s_sts_tvalid,
m_axis_mm2s_sts_tready => '1', -- Always ready. If not ready, stalls core
m_axis_mm2s_sts_tdata => axis_mm2s_sts_tdata,
m_axis_mm2s_sts_tkeep => open,
m_axis_mm2s_sts_tlast => open,
mm2s_allow_addr_req => '1',
mm2s_addr_req_posted => open,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt,
m_axi_mm2s_arid => open,
m_axi_mm2s_araddr => M_AXI_ARADDR,
m_axi_mm2s_arlen => M_AXI_ARLEN,
m_axi_mm2s_arsize => M_AXI_ARSIZE,
m_axi_mm2s_arburst => M_AXI_ARBURST,
m_axi_mm2s_arprot => open,
m_axi_mm2s_arcache => open,
m_axi_mm2s_arvalid => M_AXI_ARVALID,
m_axi_mm2s_arready => M_AXI_ARREADY,
m_axi_mm2s_rdata => M_AXI_RDATA,
m_axi_mm2s_rresp => M_AXI_RRESP,
m_axi_mm2s_rlast => M_AXI_RLAST,
m_axi_mm2s_rvalid => M_AXI_RVALID,
m_axi_mm2s_rready => M_AXI_RREADY,
m_axis_mm2s_tdata => axis_mm2s_tdata,
m_axis_mm2s_tkeep => axis_mm2s_tkeep,
m_axis_mm2s_tlast => axis_mm2s_tlast,
m_axis_mm2s_tvalid => axis_mm2s_tvalid,
m_axis_mm2s_tready => axis_mm2s_tready,
mm2s_dbg_sel => "0000",
mm2s_dbg_data => open,
m_axi_s2mm_aclk => clk,
m_axi_s2mm_aresetn => rst_global_n,
s2mm_halt => '0',
s2mm_halt_cmplt => open,
s2mm_err => s2mm_err,
m_axis_s2mm_cmdsts_awclk => clk,
m_axis_s2mm_cmdsts_aresetn => rst_global_n,
s_axis_s2mm_cmd_tvalid => axis_s2mm_cmd_tvalid,
s_axis_s2mm_cmd_tready => axis_s2mm_cmd_tready,
s_axis_s2mm_cmd_tdata => axis_s2mm_cmd_tdata,
m_axis_s2mm_sts_tvalid => axis_s2mm_sts_tvalid,
m_axis_s2mm_sts_tready => '1', -- Always ready. If not ready, stalls core
m_axis_s2mm_sts_tdata => axis_s2mm_sts_tdata,
m_axis_s2mm_sts_tkeep => open,
m_axis_s2mm_sts_tlast => open,
s2mm_allow_addr_req => '1',
s2mm_addr_req_posted => open,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt,
s2mm_ld_nxt_len => open,
s2mm_wr_len => open,
m_axi_s2mm_awid => open,
m_axi_s2mm_awaddr => M_AXI_AWADDR,
m_axi_s2mm_awlen => M_AXI_AWLEN,
m_axi_s2mm_awsize => M_AXI_AWSIZE,
m_axi_s2mm_awburst => M_AXI_AWBURST,
m_axi_s2mm_awprot => open,
m_axi_s2mm_awcache => open,
m_axi_s2mm_awvalid => M_AXI_AWVALID,
m_axi_s2mm_awready => M_AXI_AWREADY,
m_axi_s2mm_wdata => M_AXI_WDATA,
m_axi_s2mm_wstrb => M_AXI_WSTRB,
m_axi_s2mm_wlast => M_AXI_WLAST,
m_axi_s2mm_wvalid => M_AXI_WVALID,
m_axi_s2mm_wready => M_AXI_WREADY,
m_axi_s2mm_bresp => M_AXI_BRESP,
m_axi_s2mm_bvalid => M_AXI_BVALID,
m_axi_s2mm_bready => M_AXI_BREADY,
s_axis_s2mm_tdata => axis_s2mm_tdata,
s_axis_s2mm_tkeep => x"FF", -- Keep all bytes
s_axis_s2mm_tlast => axis_s2mm_tlast,
s_axis_s2mm_tvalid => axis_s2mm_tvalid,
s_axis_s2mm_tready => axis_s2mm_tready,
s2mm_dbg_sel => "0000",
s2mm_dbg_data => open);
-------------------------------------------------------------------------------
-- AXI-Stream Interconnect 8x8
-- Note: This interconnect has 8 slaves and 8 masters with full connectivity.
-- M00 & S00 (Master & Slave 0) each have 4K FIFO buffers. These help
-- buffer the uneven read & write speeds over the AXI ACP interface.
-- Arbitrates on tlast or after 16383 cycles with tvalid low. 16383 was
-- chosen to accommodate the slow output rate of a decimation filter.
-------------------------------------------------------------------------------
inst_axis_interconnect_8x8 : axis_interconnect_8x8
port map (
aclk => clk,
aresetn => rst_global_n,
s00_axis_aclk => clk,
s01_axis_aclk => clk,
s02_axis_aclk => clk,
s03_axis_aclk => clk,
s04_axis_aclk => clk,
s05_axis_aclk => clk,
s06_axis_aclk => clk,
s07_axis_aclk => clk,
s00_axis_aresetn => rst_global_n,
s01_axis_aresetn => rst_global_n,
s02_axis_aresetn => rst_global_n,
s03_axis_aresetn => rst_global_n,
s04_axis_aresetn => rst_global_n,
s05_axis_aresetn => rst_global_n,
s06_axis_aresetn => rst_global_n,
s07_axis_aresetn => rst_global_n,
s00_axis_tvalid => axis_mm2s_tvalid,
s01_axis_tvalid => axis_master_1_tvalid,
s02_axis_tvalid => axis_master_2_tvalid,
s03_axis_tvalid => axis_master_3_tvalid,
s04_axis_tvalid => axis_master_4_tvalid,
s05_axis_tvalid => axis_master_5_tvalid,
s06_axis_tvalid => axis_master_6_tvalid,
s07_axis_tvalid => axis_master_7_tvalid,
s00_axis_tready => axis_mm2s_tready,
s01_axis_tready => axis_master_1_tready,
s02_axis_tready => axis_master_2_tready,
s03_axis_tready => axis_master_3_tready,
s04_axis_tready => axis_master_4_tready,
s05_axis_tready => axis_master_5_tready,
s06_axis_tready => axis_master_6_tready,
s07_axis_tready => axis_master_7_tready,
s00_axis_tdata => axis_mm2s_tdata,
s01_axis_tdata => axis_master_1_tdata(63 downto 0),
s02_axis_tdata => axis_master_2_tdata(63 downto 0),
s03_axis_tdata => axis_master_3_tdata(63 downto 0),
s04_axis_tdata => axis_master_4_tdata(63 downto 0),
s05_axis_tdata => axis_master_5_tdata(63 downto 0),
s06_axis_tdata => axis_master_6_tdata(63 downto 0),
s07_axis_tdata => axis_master_7_tdata(63 downto 0),
s00_axis_tlast => axis_mm2s_tlast,
s01_axis_tlast => axis_master_1_tlast,
s02_axis_tlast => axis_master_2_tlast,
s03_axis_tlast => axis_master_3_tlast,
s04_axis_tlast => axis_master_4_tlast,
s05_axis_tlast => axis_master_5_tlast,
s06_axis_tlast => axis_master_6_tlast,
s07_axis_tlast => axis_master_7_tlast,
s00_axis_tdest => axis_mm2s_tdest,
s01_axis_tdest => axis_master_1_tdest,
s02_axis_tdest => axis_master_2_tdest,
s03_axis_tdest => axis_master_3_tdest,
s04_axis_tdest => axis_master_4_tdest,
s05_axis_tdest => axis_master_5_tdest,
s06_axis_tdest => axis_master_6_tdest,
s07_axis_tdest => axis_master_7_tdest,
s00_axis_tid => "000",
s01_axis_tid => "001",
s02_axis_tid => "010",
s03_axis_tid => "011",
s04_axis_tid => "100",
s05_axis_tid => "101",
s06_axis_tid => "110",
s07_axis_tid => "111",
m00_axis_aclk => clk,
m01_axis_aclk => clk,
m02_axis_aclk => clk,
m03_axis_aclk => clk,
m04_axis_aclk => clk,
m05_axis_aclk => clk,
m06_axis_aclk => clk,
m07_axis_aclk => clk,
m00_axis_aresetn => rst_global_n,
m01_axis_aresetn => rst_global_n,
m02_axis_aresetn => rst_global_n,
m03_axis_aresetn => rst_global_n,
m04_axis_aresetn => rst_global_n,
m05_axis_aresetn => rst_global_n,
m06_axis_aresetn => rst_global_n,
m07_axis_aresetn => rst_global_n,
m00_axis_tvalid => axis_s2mm_tvalid,
m01_axis_tvalid => axis_slave_1_tvalid,
m02_axis_tvalid => axis_slave_2_tvalid,
m03_axis_tvalid => axis_slave_3_tvalid,
m04_axis_tvalid => axis_slave_4_tvalid,
m05_axis_tvalid => axis_slave_5_tvalid,
m06_axis_tvalid => axis_slave_6_tvalid,
m07_axis_tvalid => axis_slave_7_tvalid,
m00_axis_tready => axis_s2mm_tready,
m01_axis_tready => axis_slave_1_tready,
m02_axis_tready => axis_slave_2_tready,
m03_axis_tready => axis_slave_3_tready,
m04_axis_tready => axis_slave_4_tready,
m05_axis_tready => axis_slave_5_tready,
m06_axis_tready => axis_slave_6_tready,
m07_axis_tready => axis_slave_7_tready,
m00_axis_tdata => axis_s2mm_tdata,
m01_axis_tdata => axis_slave_1_tdata(63 downto 0),
m02_axis_tdata => axis_slave_2_tdata(63 downto 0),
m03_axis_tdata => axis_slave_3_tdata(63 downto 0),
m04_axis_tdata => axis_slave_4_tdata(63 downto 0),
m05_axis_tdata => axis_slave_5_tdata(63 downto 0),
m06_axis_tdata => axis_slave_6_tdata(63 downto 0),
m07_axis_tdata => axis_slave_7_tdata(63 downto 0),
m00_axis_tlast => axis_s2mm_tlast,
m01_axis_tlast => axis_slave_1_tlast,
m02_axis_tlast => axis_slave_2_tlast,
m03_axis_tlast => axis_slave_3_tlast,
m04_axis_tlast => axis_slave_4_tlast,
m05_axis_tlast => axis_slave_5_tlast,
m06_axis_tlast => axis_slave_6_tlast,
m07_axis_tlast => axis_slave_7_tlast,
m00_axis_tdest => open,
m01_axis_tdest => open,
m02_axis_tdest => open,
m03_axis_tdest => open,
m04_axis_tdest => open,
m05_axis_tdest => open,
m06_axis_tdest => open,
m07_axis_tdest => open,
m00_axis_tid => axis_s2mm_tid,
m01_axis_tid => axis_slave_1_tid,
m02_axis_tid => axis_slave_2_tid,
m03_axis_tid => axis_slave_3_tid,
m04_axis_tid => axis_slave_4_tid,
m05_axis_tid => axis_slave_5_tid,
m06_axis_tid => axis_slave_6_tid,
m07_axis_tid => axis_slave_7_tid,
s00_decode_err => open,
s01_decode_err => open,
s02_decode_err => open,
s03_decode_err => open,
s04_decode_err => open,
s05_decode_err => open,
s06_decode_err => open,
s07_decode_err => open);
-------------------------------------------------------------------------------
-- FIFOs for the Datamover MM2S and S2MM Command interfaces
-- One FIFO per destination which queues transfers solely for that tdest.
-- Note: The Datamover is configured to only queue one command at a time and
-- the FIFOs below can queue the remainder. This is necessary due to
-- the need to retain tdest signals which are used for routing
-- with the AXI-Stream interconnect.
-------------------------------------------------------------------------------
gen_mm2s_cmd_fifos : for i in 0 to 7 generate
mm2s_cmd_fifo_72x64 : fifo_72x64
port map (
clk => clk,
rst => rst_mm2s_cmd_fifo,
din => mm2s_cmd_fifo_din(i),
wr_en => mm2s_cmd_fifo_wr_en(i),
rd_en => mm2s_cmd_fifo_rd_en(i),
dout => mm2s_cmd_fifo_dout(i),
full => mm2s_cmd_fifo_full(i),
empty => mm2s_cmd_fifo_empty(i));
s2mm_cmd_fifo_72x64 : fifo_72x64
port map (
clk => clk,
rst => rst_s2mm_cmd_fifo,
din => s2mm_cmd_fifo_din(i),
wr_en => s2mm_cmd_fifo_wr_en(i),
rd_en => s2mm_cmd_fifo_rd_en(i),
dout => s2mm_cmd_fifo_dout(i),
full => s2mm_cmd_fifo_full(i),
empty => s2mm_cmd_fifo_empty(i));
mm2s_cmd_fifo_din(i) <= "0000" & -- Reserved
'0' & mm2s_cmd_tdest & -- Destination
mm2s_cmd_addr & -- Start Address
'0' & -- No DRE
'1' & -- Always EOF
"000000" & -- No DRE
'0' & -- Type Fixed Address
mm2s_cmd_size -- Number of bytes to read
when mm2s_cmd_fifo_loop(i) = '0' else
mm2s_cmd_fifo_dout(i); -- Loopback dout, useful for ring buffer
-- Push command to the FIFO based on tdest
mm2s_cmd_fifo_wr_en(i) <= '1' when (mm2s_cmd_en = '1' AND
ctrl_0_addr = x"03" AND
ctrl_0_stb_dly = '1' AND
mm2s_cmd_tdest = std_logic_vector(to_unsigned(i,3)))
OR
(mm2s_cmd_fifo_rd_en(i) = '1' AND mm2s_cmd_fifo_loop(i) = '1')
else '0';
s2mm_cmd_fifo_din(i) <= "0000" & -- Reserved
'0' & s2mm_cmd_tid & -- Destination
s2mm_cmd_addr & -- Start Address
'0' & -- No DRE
'1' & -- Always EOF
"000000" & -- No DRE
'0' & -- Type Fixed Address
s2mm_cmd_size -- Number of bytes to write
when s2mm_cmd_fifo_loop(i) = '0' else
s2mm_cmd_fifo_dout(i);
-- Push command to the FIFO based on tdest
s2mm_cmd_fifo_wr_en(i) <= '1' when (s2mm_cmd_en = '1' AND
ctrl_0_addr = x"05" AND
ctrl_0_stb_dly = '1' AND
s2mm_cmd_tid = std_logic_vector(to_unsigned(i,3)))
OR
(s2mm_cmd_fifo_rd_en(i) = '1' AND s2mm_cmd_fifo_loop(i) = '1')
else '0';
end generate;
-- Controls the MM2S interface with round robin selection for which AXI-Stream (via tdest)
-- to output data on.
proc_mm2s_cmd_intf : process(clk,rst_global_n)
begin
if (rst_global_n = '0') then
mm2s_cmd_fifo_rd_en <= (others=>'0');
axis_mm2s_cmd_tvalid <= '0';
axis_mm2s_cmd_tdata <= (others=>'0');
axis_mm2s_tdest <= (others=>'0');
mm2s_xfer_in_progress <= '0';
mm2s_tdest <= 0;
else
if rising_edge(clk) then
-- Check each command FIFO. If not empty, the Datamover is ready, and a transfer is currently not in
-- process, execute a new transfer.
if (mm2s_cmd_fifo_empty(mm2s_tdest) = '0' AND axis_mm2s_cmd_tready = '1' AND mm2s_xfer_in_progress = '0' AND mm2s_xfer_en = '1') then
mm2s_cmd_fifo_rd_en(mm2s_tdest) <= '1';
axis_mm2s_cmd_tvalid <= '1';
axis_mm2s_cmd_tdata <= mm2s_cmd_fifo_dout(mm2s_tdest);
axis_mm2s_tdest <= std_logic_vector(to_unsigned(mm2s_tdest,3));
mm2s_xfer_in_progress <= '1';
else
mm2s_cmd_fifo_rd_en <= (others=>'0');
axis_mm2s_cmd_tvalid <= '0';
end if;
-- While an xfer is not in progress, loop through the available destinations
if (mm2s_xfer_in_progress = '0') then
if (mm2s_tdest = 7) then
mm2s_tdest <= 0;
else
mm2s_tdest <= mm2s_tdest + 1;
end if;
end if;
-- Clear transfer in progress register when the write is complete
if (axis_mm2s_sts_tvalid = '1') then
mm2s_xfer_in_progress <= '0';
end if;
end if;
end if;
end process;
proc_s2mm_cmd_intf : process(clk,rst_global_n)
begin
if (rst_global_n = '0') then
s2mm_xfer_in_progress <= '0';
s2mm_cmd_fifo_rd_en <= (others=>'0');
axis_s2mm_cmd_tvalid <= '0';
axis_s2mm_cmd_tdata <= (others=>'0');
else
if rising_edge(clk) then
-- Wait until the Datamover is ready, the command FIFO is not empty, the AXI-Stream master
-- has valid data, and no other transfers are in progress.
if (axis_s2mm_cmd_tready = '1' AND s2mm_cmd_fifo_empty(to_integer(unsigned(axis_s2mm_tid))) = '0' AND
axis_s2mm_tvalid = '1' AND s2mm_xfer_in_progress = '0' AND s2mm_xfer_en = '1') then
s2mm_cmd_fifo_rd_en(to_integer(unsigned(axis_s2mm_tid))) <= '1';
axis_s2mm_cmd_tvalid <= '1';
axis_s2mm_cmd_tdata <= s2mm_cmd_fifo_dout(to_integer(unsigned(axis_s2mm_tid)));
s2mm_xfer_in_progress <= '1';
else
s2mm_cmd_fifo_rd_en <= (others=>'0');
axis_s2mm_cmd_tvalid <= '0';
end if;
if (axis_s2mm_sts_tvalid = '1') then
s2mm_xfer_in_progress <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- FIFOs for the Datamover MM2S and S2MM Status interfaces
-- Note: The sts_tready signals are always asserted on the Datamover as
-- deasserting the signal can cause it to stall. This means that these
-- FIFOs may overflow if not read, but ultimately that is not a serious
-- issue (especially if sts_fifo_auto_read is enabled).
-------------------------------------------------------------------------------
mm2s_sts_fifo_8x64 : fifo_8x64
port map (
clk => clk,
rst => rst_sts_fifo,
din => axis_mm2s_sts_tdata,
wr_en => axis_mm2s_sts_tvalid,
rd_en => mm2s_sts_fifo_rd_en,
dout => mm2s_sts_fifo_dout,
full => mm2s_sts_fifo_full,
empty => mm2s_sts_fifo_empty);
-- Pop FIFO when either Status Register Bank 6 is accessed or if auto-read is enabled and the FIFO is full (to avoid
-- overflow)
mm2s_sts_fifo_rd_en <= '1' when (status_0_addr = x"06" AND status_0_stb = '1') OR
(sts_fifo_auto_read = '1' AND mm2s_sts_fifo_full = '1') else '0';
s2mm_sts_fifo_8x64 : fifo_8x64
port map (
clk => clk,
rst => rst_sts_fifo,
din => axis_s2mm_sts_tdata,
wr_en => axis_s2mm_sts_tvalid,
rd_en => s2mm_sts_fifo_rd_en,
dout => s2mm_sts_fifo_dout,
full => s2mm_sts_fifo_full,
empty => s2mm_sts_fifo_empty);
-- Pop FIFO when either Status Register Bank 7 is accessed or if auto-read is enabled and the FIFO is full (to avoid
-- overflow)
s2mm_sts_fifo_rd_en <= '1' when (status_0_addr = x"07" AND status_0_stb = '1') OR
(sts_fifo_auto_read = '1' AND s2mm_sts_fifo_full = '1') else '0';
-- Count the number of transfers per plblock in each direction
proc_xfer_counters : process(clk,rst_global_n)
begin
if (rst_global_n = '0') then
s2mm_xfer_cnt <= 0;
mm2s_xfer_cnt <= 0;
else
if rising_edge(clk) then
for i in 0 to 7 loop
if (clear_s2mm_xfer_cnt = '1' AND status_0_addr = x"00" AND status_0_stb = '1') then
-- Xfer occured when we were commanded to clear the count
if (axis_s2mm_sts_tvalid = '1') then
s2mm_xfer_cnt <= 1;
else
s2mm_xfer_cnt <= 0;
end if;
elsif (axis_s2mm_sts_tvalid = '1') then
s2mm_xfer_cnt <= s2mm_xfer_cnt + 1;
end if;
if (clear_mm2s_xfer_cnt = '1' AND status_0_addr = x"00" AND status_0_stb = '1') then
if (axis_mm2s_sts_tvalid = '1') then
mm2s_xfer_cnt <= 1;
else
mm2s_xfer_cnt <= 0;
end if;
elsif (axis_s2mm_sts_tvalid = '1') then
mm2s_xfer_cnt <= mm2s_xfer_cnt + 1;
end if;
end loop;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Control and status registers.
-------------------------------------------------------------------------------
-- Global registers for all accelerators
proc_global_reg : process(clk,rst_n)
begin
if (rst_n = '0') then
ctrl_127_reg <= (others=>(others=>'0'));
status_127_data <= (others=>'0');
else
if rising_edge(clk) then
-- Update control registers only when the global registers are accessed
if (ctrl_127_stb = '1') then
ctrl_127_reg(to_integer(unsigned(ctrl_127_addr))) <= ctrl_127_data;
end if;
-- Always update status registers, regardless of which status regs
-- are accessed (see above)
if (status_127_stb = '1') then
status_127_data <= status_127_reg(to_integer(unsigned(status_127_addr)));
end if;
end if;
end if;
end process;
-- Control Registers Bank 0 (General)
rst_global <= ctrl_127_reg(0)(0) OR NOT(rst_n);
-- Control Registers Bank 1 (AXI Cache & User)
-- AxPROT(1): "0" = Secure, "1" = Non-secure. To access the ACP bus, we must be in secure mode.
-- AxCACHE: "1111" = Cacheable write-back, allocate on both read and write per ARM documenation
-- AxUSER(4:1): "1111" = Write-Back Write Allocate per ARM documentation
-- AxUSER(0): Enable transaction sharing. From ARM documentation: "AxUSER(0) is ANDed with
-- AxCACHE(1) to decide if it is a coherent shared request. Such requests can access
-- level-1 cache coherent data."
-- Recommended Values:
M_AXI_AWPROT <= ctrl_127_reg(1)(2 downto 0); -- "000"
M_AXI_AWCACHE <= ctrl_127_reg(1)(6 downto 3); -- "1111"
M_AXI_AWUSER <= ctrl_127_reg(1)(11 downto 7); -- "11111"
M_AXI_ARPROT <= ctrl_127_reg(1)(14 downto 12); -- "000"
M_AXI_ARCACHE <= ctrl_127_reg(1)(18 downto 15); -- "1111"
M_AXI_ARUSER <= ctrl_127_reg(1)(23 downto 19); -- "11111"
-- Status Registers Bank 0 (Readback)
status_127_reg(0)(0) <= rst_global;
-- Status Registers Bank 1 (Readback)
status_127_reg(1)(2 downto 0) <= ctrl_127_reg(1)(2 downto 0);
status_127_reg(1)(6 downto 3) <= ctrl_127_reg(1)(6 downto 3);
status_127_reg(1)(11 downto 7) <= ctrl_127_reg(1)(11 downto 7);
status_127_reg(1)(14 downto 12) <= ctrl_127_reg(1)(14 downto 12);
status_127_reg(1)(18 downto 15) <= ctrl_127_reg(1)(18 downto 15);
status_127_reg(1)(23 downto 19) <= ctrl_127_reg(1)(23 downto 19);
-- Registers for datamover and PS PL interface
proc_datamover_reg : process(clk,rst_global_n)
begin
if (rst_global_n = '0') then
ctrl_0_stb_dly <= '0';
ctrl_0_reg <= (others=>(others=>'0'));
status_0_data <= (others=>'0');
else
if rising_edge(clk) then
ctrl_0_stb_dly <= ctrl_0_stb;
-- Update control registers only when accelerator 0 is accessed
if (ctrl_0_stb = '1') then
ctrl_0_reg(to_integer(unsigned(ctrl_0_addr))) <= ctrl_0_data;
end if;
-- Always update status registers, regardless of which accelerator's status regs
-- are accessed (see above)
if (status_0_stb = '1') then
status_0_data <= status_0_reg(to_integer(unsigned(status_0_addr)));
end if;
end if;
end if;
end process;
-- Control Registers Bank 0 (General)
mm2s_xfer_en <= ctrl_0_reg(0)(0);
s2mm_xfer_en <= ctrl_0_reg(0)(1);
rst_mm2s_cmd_fifo <= ctrl_0_reg(0)(2) OR rst_global;
rst_s2mm_cmd_fifo <= ctrl_0_reg(0)(3) OR rst_global;
mm2s_cmd_fifo_loop <= ctrl_0_reg(0)(11 downto 4); -- Re-write command fifo output back to input
s2mm_cmd_fifo_loop <= ctrl_0_reg(0)(19 downto 12); -- Re-write command fifo output back to input
sts_fifo_auto_read <= ctrl_0_reg(0)(20); -- Automatically read FIFO if full to prevent overflow
rst_sts_fifo <= ctrl_0_reg(0)(21) OR rst_global;
clear_mm2s_xfer_cnt <= ctrl_0_reg(0)(22);
clear_s2mm_xfer_cnt <= ctrl_0_reg(0)(23);
-- Control Registers Bank 1 (Accelerator Interrupts)
irq_s2mm_en <= ctrl_0_reg(1)(0);
irq_mm2s_en <= ctrl_0_reg(1)(1);
irq_axis_master_en <= ctrl_0_reg(1)(15 downto 8);
irq_axis_slave_en <= ctrl_0_reg(1)(23 downto 16);
-- Control Registers Bank 2 (MM2S Command Interface Address)
mm2s_cmd_addr <= ctrl_0_reg(2);
-- Control Registers Bank 3 (MM2S Command Interface FIFO Write Enable, tdest, Cache, Size)
mm2s_cmd_size <= ctrl_0_reg(3)(22 downto 0);
mm2s_cmd_tdest <= ctrl_0_reg(3)(25 downto 23);
mm2s_cmd_en <= ctrl_0_reg(3)(31);
-- Control Registers Bank 4 (S2MM Command Interface Address)
s2mm_cmd_addr <= ctrl_0_reg(4);
-- Control Registers Bank 5 (S2MM Command Interface FIFO Write Enable, tid, Cache, Size)
s2mm_cmd_size <= ctrl_0_reg(5)(22 downto 0);
s2mm_cmd_tid <= ctrl_0_reg(5)(25 downto 23);
s2mm_cmd_en <= ctrl_0_reg(5)(31);
-- Status Registers Bank 0 (General Readback)
status_0_reg(0)(0) <= mm2s_xfer_en;
status_0_reg(0)(1) <= s2mm_xfer_en;
status_0_reg(0)(2) <= rst_mm2s_cmd_fifo;
status_0_reg(0)(3) <= rst_s2mm_cmd_fifo;
status_0_reg(0)(11 downto 4) <= mm2s_cmd_fifo_loop;
status_0_reg(0)(19 downto 12) <= s2mm_cmd_fifo_loop;
status_0_reg(0)(20) <= sts_fifo_auto_read;
status_0_reg(0)(21) <= rst_sts_fifo;
status_0_reg(0)(22) <= clear_mm2s_xfer_cnt;
status_0_reg(0)(23) <= clear_s2mm_xfer_cnt;
status_0_reg(0)(24) <= mm2s_xfer_in_progress;
status_0_reg(0)(25) <= s2mm_xfer_in_progress;
-- Status Registers Bank 1 (Interrupts Readback)
status_0_reg(1)(0) <= irq_s2mm_en;
status_0_reg(1)(1) <= irq_mm2s_en;
status_0_reg(1)(15 downto 8) <= irq_axis_master_en;
status_0_reg(1)(23 downto 16) <= irq_axis_slave_en;
-- Status Registers Bank 2 (MM2S Command Interface Address Readback)
status_0_reg(2) <= mm2s_cmd_addr;
-- Status Registers Bank 3 (MM2S Command Interface FIFO Write Enable, tdest, Cache, Size Readback)
status_0_reg(3)(22 downto 0) <= mm2s_cmd_size;
status_0_reg(3)(25 downto 23) <= mm2s_cmd_tdest;
status_0_reg(3)(31) <= mm2s_cmd_en;
-- Status Registers Bank 4 (S2MM Command Interface Address Readback)
status_0_reg(4) <= s2mm_cmd_addr;
-- Status Registers Bank 5 (S2MM Command Interface FIFO Write Enable, tid, Cache, Size Readback)
status_0_reg(5)(22 downto 0) <= s2mm_cmd_size;
status_0_reg(5)(25 downto 23) <= s2mm_cmd_tid;
status_0_reg(5)(31) <= s2mm_cmd_en;
-- Status Registers Bank 6 (MM2S Sts)
status_0_reg(6)(7 downto 0) <= mm2s_sts_fifo_dout;
-- Status Registers Bank 7 (S2MM Sts)
status_0_reg(7)(7 downto 0) <= s2mm_sts_fifo_dout;
-- Status Registers Bank 8 (Sts FIFO Status)
status_0_reg(8)(0) <= mm2s_sts_fifo_empty;
status_0_reg(8)(1) <= mm2s_sts_fifo_full;
status_0_reg(8)(2) <= s2mm_sts_fifo_empty;
status_0_reg(8)(3) <= s2mm_sts_fifo_full;
-- Status Registers Bank 9 (Command FIFO Status)
status_0_reg(9)(7 downto 0) <= mm2s_cmd_fifo_empty;
status_0_reg(9)(15 downto 8) <= mm2s_cmd_fifo_full;
status_0_reg(9)(23 downto 16) <= s2mm_cmd_fifo_empty;
status_0_reg(9)(31 downto 24) <= s2mm_cmd_fifo_full;
-- Status Register Bank 11 (MM2S Xfer count)
status_0_reg(10) <= std_logic_vector(to_unsigned(mm2s_xfer_cnt,32));
-- Status Register Bank 12 (S2MM Xfer count)
status_0_reg(11) <= std_logic_vector(to_unsigned(s2mm_xfer_cnt,32));
-- Status Registers Bank 20 (Test Word)
status_0_reg(12) <= x"CA11AB1E";
-- Status Registers Bank 21 (Debug Counter)
status_0_reg(13) <= std_logic_vector(to_unsigned(debug_counter,32));
end architecture; | gpl-3.0 | 7030a82b1df31ddaa334d6ffec0fbd06 | 0.465958 | 3.599804 | false | false | false | false |
chiggs/nvc | test/regress/agg5.vhd | 5 | 505 | entity agg5 is
end entity;
architecture test of agg5 is
signal vec : bit_vector(4 downto 1);
signal a, b : bit;
begin
vec <= ( 1 => a, 2 => b, others => '0' );
process is
begin
wait for 1 ns;
assert vec = X"0";
a <= '1';
wait for 1 ns;
assert vec = X"1";
b <= '1';
wait for 1 ns;
assert vec = X"3";
a <= '0';
wait for 1 ns;
assert vec = X"2";
wait;
end process;
end architecture;
| gpl-3.0 | b9e0a33686b288ad0afd9a92711eeb41 | 0.463366 | 3.389262 | false | false | false | false |
xiadz/oscilloscope | src/pixgen_mux.vhd | 1 | 1,372 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 21:10:21 05/22/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity pixgen_mux is
port (
nrst : in std_logic;
clk108 : in std_logic;
trace_vout : in std_logic_vector (7 downto 0);
time_base_vout : in std_logic_vector (7 downto 0);
settings_vout : in std_logic_vector (7 downto 0);
active_pixgen_source : in PIXGEN_SOURCE_T;
vout : out std_logic_vector (7 downto 0)
);
end pixgen_mux;
architecture behavioral of pixgen_mux is
begin
process (nrst, clk108) is
begin
if nrst = '0' then
vout <= "00000000";
elsif rising_edge (clk108) then
if active_pixgen_source = TRACE_PIXGEN_T then
vout <= trace_vout;
elsif active_pixgen_source = TIME_BASE_PIXGEN_T then
vout <= time_base_vout;
elsif active_pixgen_source = SETTINGS_PIXGEN_T then
vout <= settings_vout;
else
vout <= "00000000";
end if;
end if;
end process;
end behavioral;
| mit | 97e13d7a9d77e75a9c0ff7e6a9418b69 | 0.471574 | 4.145015 | false | false | false | false |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/voltage_source_arc.vhdl | 15 | 543 | ARCHITECTURE sinusodial OF voltage_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
v == (amplitude * sin(k * MATH_2_PI * now)) + offset;
END architecture sinusodial;
ARCHITECTURE pulse OF voltage_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
SIGNAL source_sig: real := 0.0;
BEGIN
p:PROCESS
BEGIN
source_sig <= (amplitude/2.0) + offset;
WAIT FOR width;
source_sig <= - (amplitude/2.0) + offset;
WAIT FOR period - width;
END process p;
-- BREAK v => 0.0;
v == source_sig;
END architecture pulse;
| gpl-2.0 | 5af50a54ce640b523c04b7322cd99428 | 0.664825 | 3.372671 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/xilinx_primitives/RAMB16_S9_S18-model.vhd | 1 | 1,061 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture model of RAMB16_S9_S18 is
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
shared variable mem : t_byte_array(0 to 2047) := (others => X"00");
begin
process(CLKA)
begin
if rising_edge(CLKA) then
if ENA = '1' then
DOA <= mem(to_integer(unsigned(ADDRA)));
if WEA = '1' then
mem(to_integer(unsigned(ADDRA))) := DIA;
end if;
end if;
end if;
end process;
process(CLKB)
variable addr : natural;
begin
if rising_edge(CLKB) then
if ENB = '1' then
addr := 2 * to_integer(unsigned(ADDRB));
DOB <= mem(addr + 1) & mem(addr);
if WEB = '1' then
mem(addr) := DIB(7 downto 0);
mem(addr + 1) := DIB(15 downto 8);
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 7a1a54aeb2ecda56b54a9477bfa085fb | 0.494816 | 3.858182 | false | false | false | false |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/voltage_dependend_capacitor.vhdl | 15 | 513 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY VOLTAGE_DEPENDEND_CAPACITOR IS
GENERIC ( PB : REAL := 1.0;
M : REAL := 0.5;
VT : REAL := 25.85e-6;
ISS : REAL := 1.0e-15;
TT : REAL := 4.0e-9;
CJ0 : REAL := 2.5e-12;
v_init : REAL := 0.0;
N :REAL := 1.0);
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY VOLTAGE_DEPENDEND_CAPACITOR;
| gpl-2.0 | 5fde7ccb86c19c8cdc2ed09c0689c982 | 0.60039 | 2.64433 | false | false | false | false |
armandas/Arcade | score_info.vhd | 2 | 3,019 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity score_info is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
score: in std_logic_vector(15 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end score_info;
architecture display of score_info is
constant WIDTH: integer := 48;
constant HEIGHT: integer := 8;
constant Y_OFFSET: integer := 8;
signal font_addr: std_logic_vector(8 downto 0);
signal font_data: std_logic_vector(0 to 7);
signal font_pixel: std_logic;
signal text_font_addr: std_logic_vector(8 downto 0);
signal number_font_addr: std_logic_vector(8 downto 0);
signal text_enable: std_logic;
signal number_enable: std_logic;
signal bcd: std_logic_vector(3 downto 0);
signal bcd0, bcd1, bcd2, bcd3, bcd4: std_logic_vector(3 downto 0);
begin
text_enable <= '1' when (px_x >= 0 and
px_x < WIDTH and
px_y >= Y_OFFSET and
px_y < Y_OFFSET + HEIGHT) else
'0';
number_enable <= '1' when (px_x >= WIDTH and
px_x < WIDTH + 40 and
px_y >= Y_OFFSET and
px_y < Y_OFFSET + HEIGHT) else
'0';
with px_x(9 downto 3) select
text_font_addr <= "110011000" when "0000000", -- S
"100011000" when "0000001", -- C
"101111000" when "0000010", -- O
"110010000" when "0000011", -- R
"100101000" when "0000100", -- E
"000000000" when others; -- space
bcd <= bcd0 when px_x(9 downto 3) = 10 else
bcd1 when px_x(9 downto 3) = 9 else
bcd2 when px_x(9 downto 3) = 8 else
bcd3 when px_x(9 downto 3) = 7 else
bcd4 when px_x(9 downto 3) = 6 else
(others => '0');
-- numbers start at memory location 128
-- '1' starts at 136, '2' at 144 and so on
-- bcd is multiplied by 8 to get the right digit
number_font_addr <= conv_std_logic_vector(128, 9) + (bcd & "000");
font_addr <= px_y(2 downto 0) + text_font_addr when text_enable = '1' else
px_y(2 downto 0) + number_font_addr when number_enable = '1' else
(others => '0');
font_pixel <= font_data(conv_integer(px_x(2 downto 0)));
rgb_pixel <= "111" when font_pixel = '1' else "000";
bin_to_bcd:
entity work.bin2bcd(behaviour)
generic map(N_BIN => 16)
port map(
clk => clk, not_reset => not_reset,
binary_in => score,
bcd0 => bcd0, bcd1 => bcd1, bcd2 => bcd2,
bcd3 => bcd3, bcd4 => bcd4
);
codepage:
entity work.codepage_rom(content)
port map(addr => font_addr, data => font_data);
end display;
| bsd-2-clause | 219cb2e6bf7dd04a1cd7bd98bd7b37df | 0.524346 | 3.602625 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios/nios/nios_inst.vhd | 1 | 8,937 | component nios is
port (
altmemddr_0_auxfull_clk : out std_logic; -- clk
altmemddr_0_auxhalf_clk : out std_logic; -- clk
clk50_clk : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
mem32_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
mem32_direction : in std_logic := 'X'; -- direction
mem32_byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byte_en
mem32_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
mem32_request : in std_logic := 'X'; -- request
mem32_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- tag
mem32_dack_tag : out std_logic_vector(7 downto 0); -- dack_tag
mem32_rdata : out std_logic_vector(31 downto 0); -- rdata
mem32_rack : out std_logic; -- rack
mem32_rack_tag : out std_logic_vector(7 downto 0); -- rack_tag
mem_external_local_refresh_ack : out std_logic; -- local_refresh_ack
mem_external_local_init_done : out std_logic; -- local_init_done
mem_external_reset_phy_clk_n : out std_logic; -- reset_phy_clk_n
memory_mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
memory_mem_clk : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_clk
memory_mem_clk_n : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_clk_n
memory_mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
memory_mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
memory_mem_addr : out std_logic_vector(13 downto 0); -- mem_addr
memory_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dm : out std_logic_vector(0 downto 0); -- mem_dm
pio_in_port : in std_logic_vector(31 downto 0) := (others => 'X'); -- in_port
pio_out_port : out std_logic_vector(31 downto 0); -- out_port
reset_reset_n : in std_logic := 'X'; -- reset_n
sys_clock_clk : out std_logic; -- clk
sys_reset_reset_n : out std_logic -- reset_n
);
end component nios;
u0 : component nios
port map (
altmemddr_0_auxfull_clk => CONNECTED_TO_altmemddr_0_auxfull_clk, -- altmemddr_0_auxfull.clk
altmemddr_0_auxhalf_clk => CONNECTED_TO_altmemddr_0_auxhalf_clk, -- altmemddr_0_auxhalf.clk
clk50_clk => CONNECTED_TO_clk50_clk, -- clk50.clk
io_ack => CONNECTED_TO_io_ack, -- io.ack
io_rdata => CONNECTED_TO_io_rdata, -- .rdata
io_read => CONNECTED_TO_io_read, -- .read
io_wdata => CONNECTED_TO_io_wdata, -- .wdata
io_write => CONNECTED_TO_io_write, -- .write
io_address => CONNECTED_TO_io_address, -- .address
io_irq => CONNECTED_TO_io_irq, -- .irq
mem32_address => CONNECTED_TO_mem32_address, -- mem32.address
mem32_direction => CONNECTED_TO_mem32_direction, -- .direction
mem32_byte_en => CONNECTED_TO_mem32_byte_en, -- .byte_en
mem32_wdata => CONNECTED_TO_mem32_wdata, -- .wdata
mem32_request => CONNECTED_TO_mem32_request, -- .request
mem32_tag => CONNECTED_TO_mem32_tag, -- .tag
mem32_dack_tag => CONNECTED_TO_mem32_dack_tag, -- .dack_tag
mem32_rdata => CONNECTED_TO_mem32_rdata, -- .rdata
mem32_rack => CONNECTED_TO_mem32_rack, -- .rack
mem32_rack_tag => CONNECTED_TO_mem32_rack_tag, -- .rack_tag
mem_external_local_refresh_ack => CONNECTED_TO_mem_external_local_refresh_ack, -- mem_external.local_refresh_ack
mem_external_local_init_done => CONNECTED_TO_mem_external_local_init_done, -- .local_init_done
mem_external_reset_phy_clk_n => CONNECTED_TO_mem_external_reset_phy_clk_n, -- .reset_phy_clk_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- memory.mem_odt
memory_mem_clk => CONNECTED_TO_memory_mem_clk, -- .mem_clk
memory_mem_clk_n => CONNECTED_TO_memory_mem_clk_n, -- .mem_clk_n
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_addr => CONNECTED_TO_memory_mem_addr, -- .mem_addr
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
pio_in_port => CONNECTED_TO_pio_in_port, -- pio.in_port
pio_out_port => CONNECTED_TO_pio_out_port, -- .out_port
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sys_clock_clk => CONNECTED_TO_sys_clock_clk, -- sys_clock.clk
sys_reset_reset_n => CONNECTED_TO_sys_reset_reset_n -- sys_reset.reset_n
);
| gpl-3.0 | e74679b95e20f0c5458531765e50edf8 | 0.379993 | 4.097662 | false | false | false | false |
xiadz/oscilloscope | src/tests/test_single_debouncer.vhd | 1 | 3,213 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:08:56 05/24/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_single_debouncer.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: single_debouncer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_single_debouncer IS
END test_single_debouncer;
ARCHITECTURE behavior OF test_single_debouncer IS
-- Component Declaration for the Unit Under Test (UUT)
constant n : integer := 5;
COMPONENT single_debouncer
GENERIC (n : natural := n);
PORT(
nrst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
--Inputs
signal nrst : std_logic := '0';
signal clk : std_logic := '0';
signal input : std_logic := '0';
--Outputs
signal output : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: single_debouncer
PORT MAP (
nrst => nrst,
clk => clk,
input => input,
output => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable i:integer;
begin
-- hold reset state for 100 ns.
nrst <= '0';
wait for 100 ns;
nrst <= '1';
wait for clk_period * 10;
while true loop
for i in 0 to 9 loop
input <= not input;
wait for clk_period;
assert output = input report "Should be equal, but is not";
wait for clk_period * (n + 1);
end loop;
input <= '0';
wait for clk_period * (n + 1);
input <= '1';
wait for clk_period;
for i in 1 to n loop
input <= '0';
wait for clk_period / 2;
assert output = '1' report "Should be equal '1', but is not";
input <= '1';
wait for clk_period / 2;
assert output = '1' report "Should be equal '1', but is not";
end loop;
wait for clk_period * (n + 1);
end loop;
wait;
end process;
END;
| mit | 80b24347f5a9a69b6a6bfa3e3154d912 | 0.547463 | 4.145806 | false | true | false | false |
ringof/radiofist_audio | ipcore_dir/dcm_6.vhd | 1 | 6,466 | -- file: dcm_6.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1_____6.000______0.000______50.0_____1866.667____150.000
-- CLK_OUT2_____1.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm_6 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_ADC : out std_logic;
DEC_CLK : out std_logic;
-- Status and control signals
RESET : in std_logic
);
end dcm_6;
architecture xilinx of dcm_6 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm_6,clk_wiz_v3_6,{component_name=dcm_6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 16.000,
CLKFX_DIVIDE => 8,
CLKFX_MULTIPLY => 3,
CLKIN_DIVIDE_BY_2 => TRUE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => RESET,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK_ADC,
I => clkfx);
clkout2_buf : BUFG
port map
(O => DEC_CLK,
I => clkdv);
end xilinx;
| mit | d569b9d5a1a9e06e766ea56c637e1c7c | 0.567739 | 4.248357 | false | false | false | false |
ringof/radiofist_audio | io_pads.vhd | 1 | 1,202 | -- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See LICENCE.txt for details
--
-- Signal conversion and debounce
library UNISIM;
library IEEE;
use UNISIM.VComponents.all;
use IEEE.STD_LOGIC_1164.all;
entity io_pads is
port (
clk : in STD_LOGIC;
clk_i : out STD_LOGIC;
lvds_p : in STD_LOGIC;
lvds_n : in STD_LOGIC;
comp_i : out STD_LOGIC;
reset : in STD_LOGIC;
reset_i : out STD_LOGIC;
adc_fb : out STD_LOGIC;
adc_fb_i : in STD_LOGIC;
dac_out : out STD_LOGIC;
dac_out_i : in STD_LOGIC;
test : inout STD_LOGIC_VECTOR(7 downto 0);
test_i : inout STD_LOGIC_VECTOR(7 downto 0)
);
end io_pads;
architecture RTL of io_pads is
component IBUFDS is
generic (IOSTANDARD : string);
port (
I : in STD_LOGIC;
IB : in STD_LOGIC;
O : out STD_LOGIC
);
end component;
begin
-- Converts difference between LVDS inputs into a STD_LOGIC signal
LVDS_buf : IBUFDS
generic map(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "LVDS25"
)
port map(
I => lvds_p,
IB => lvds_n,
O => comp_i
);
-- signal pass-throughs
clk_i <= clk;
reset_i <= reset;
adc_fb_i <= adc_fb;
dac_out_i <= dac_out;
test_i <= test;
end RTL;
| mit | a6988567362bd991ca66c48686aea1b3 | 0.643095 | 2.647577 | false | true | false | false |
ntb-ch/cb20 | FPGA_Designs/standard/cb20/synthesis/cb20_width_adapter_001.vhd | 1 | 10,454 | -- cb20_width_adapter_001.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 52;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 61;
IN_PKT_BYTE_CNT_L : integer := 59;
IN_PKT_TRANS_COMPRESSED_READ : integer := 53;
IN_PKT_BURSTWRAP_H : integer := 62;
IN_PKT_BURSTWRAP_L : integer := 62;
IN_PKT_BURST_SIZE_H : integer := 65;
IN_PKT_BURST_SIZE_L : integer := 63;
IN_PKT_RESPONSE_STATUS_H : integer := 87;
IN_PKT_RESPONSE_STATUS_L : integer := 86;
IN_PKT_TRANS_EXCLUSIVE : integer := 58;
IN_PKT_BURST_TYPE_H : integer := 67;
IN_PKT_BURST_TYPE_L : integer := 66;
IN_ST_DATA_W : integer := 88;
OUT_PKT_ADDR_H : integer := 34;
OUT_PKT_ADDR_L : integer := 18;
OUT_PKT_DATA_H : integer := 15;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 17;
OUT_PKT_BYTEEN_L : integer := 16;
OUT_PKT_BYTE_CNT_H : integer := 43;
OUT_PKT_BYTE_CNT_L : integer := 41;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 35;
OUT_PKT_BURST_SIZE_H : integer := 47;
OUT_PKT_BURST_SIZE_L : integer := 45;
OUT_PKT_RESPONSE_STATUS_H : integer := 69;
OUT_PKT_RESPONSE_STATUS_L : integer := 68;
OUT_PKT_TRANS_EXCLUSIVE : integer := 40;
OUT_PKT_BURST_TYPE_H : integer := 49;
OUT_PKT_BURST_TYPE_L : integer := 48;
OUT_ST_DATA_W : integer := 70;
ST_CHANNEL_W : integer := 6;
OPTIMIZE_FOR_RSP : integer := 1;
RESPONSE_PATH : integer := 1
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(5 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(87 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(69 downto 0); -- .data
out_channel : out std_logic_vector(5 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter_001;
architecture rtl of cb20_width_adapter_001 is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(69 downto 0); -- data
out_channel : out std_logic_vector(5 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter_001 : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter_001
| apache-2.0 | a951633941db14d8a6fcd35577afa7a0 | 0.45925 | 3.366828 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/cyclone4_test/vhdl_source/u2p_dut.vhd | 1 | 29,204 | -------------------------------------------------------------------------------
-- Title : u2p_dut
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel for u2p_dut.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity u2p_dut is
port (
-- slot side
SLOT_BUFFER_ENn : out std_logic;
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : in std_logic;
SLOT_ADDR : in std_logic_vector(15 downto 0);
SLOT_DATA : in std_logic_vector(7 downto 0);
SLOT_RWn : in std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : in std_logic;
SLOT_EXROMn : in std_logic;
SLOT_GAMEn : in std_logic;
SLOT_ROMHn : in std_logic;
SLOT_ROMLn : in std_logic;
SLOT_IO1n : in std_logic;
SLOT_IO2n : in std_logic;
SLOT_IRQn : in std_logic;
SLOT_NMIn : in std_logic;
SLOT_VCC : in std_logic;
SLOT_RST_DRV : out std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_DM : inout std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : in std_logic;
IEC_DATA : in std_logic;
IEC_CLOCK : in std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : in std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Misc
BOARD_REVn : in std_logic_vector(4 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : in std_logic := 'Z';
CAS_READ : in std_logic := 'Z';
CAS_WRITE : in std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_dut is
component nios_dut is
port (
audio_in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
audio_in_valid : in std_logic := 'X'; -- valid
audio_in_ready : out std_logic; -- ready
audio_out_data : out std_logic_vector(31 downto 0); -- data
audio_out_valid : out std_logic; -- valid
audio_out_ready : in std_logic := 'X'; -- ready
dummy_export : in std_logic := 'X'; -- export
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
jtag_io_input_vector : in std_logic_vector(47 downto 0) := (others => 'X'); -- input_vector
jtag_io_output_vector : out std_logic_vector(7 downto 0); -- output_vector
jtag_test_clocks_clock_1 : in std_logic := 'X'; -- clock_1
jtag_test_clocks_clock_2 : in std_logic := 'X'; -- clock_2
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
pio1_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
pio2_export : in std_logic_vector(19 downto 0) := (others => 'X'); -- export
pio3_export : out std_logic_vector(7 downto 0); -- export
sys_clock_clk : in std_logic := 'X'; -- clk
sys_reset_reset_n : in std_logic := 'X'; -- reset_n
uart_rxd : in std_logic := 'X'; -- rxd
uart_txd : out std_logic; -- txd
uart_cts_n : in std_logic := 'X'; -- cts_n
uart_rts_n : out std_logic -- rts_n
);
end component nios_dut;
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
signal por_n : std_logic;
signal ref_reset : std_logic;
signal por_count : unsigned(19 downto 0) := (others => '0');
signal sys_count : unsigned(23 downto 0) := (others => '0');
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal eth_reset : std_logic;
signal ulpi_reset_req : std_logic;
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal is_idle : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal cpu_mem_req : t_mem_req_32;
signal cpu_mem_resp : t_mem_resp_32;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_scl_i : std_logic;
signal i2c_scl_o : std_logic;
signal mdio_o : std_logic;
-- io buses
signal io_irq : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_u2p_req : t_io_req;
signal io_u2p_resp : t_io_resp;
signal io_req_new_io : t_io_req;
signal io_resp_new_io : t_io_resp;
signal io_req_remote : t_io_req;
signal io_resp_remote : t_io_resp;
signal io_req_ddr2 : t_io_req;
signal io_resp_ddr2 : t_io_resp;
-- misc io
signal audio_in_data : std_logic_vector(31 downto 0) := (others => '0'); -- data
signal audio_in_valid : std_logic := '0'; -- valid
signal audio_in_ready : std_logic; -- ready
signal audio_out_data : std_logic_vector(31 downto 0) := (others => '0'); -- data
signal audio_out_valid : std_logic; -- valid
signal audio_out_ready : std_logic := '0'; -- ready
signal audio_speaker : signed(15 downto 0);
signal pll_locked : std_logic;
signal pio1_export : std_logic_vector(31 downto 0) := (others => '0'); -- in_port
signal pio2_export : std_logic_vector(19 downto 0) := (others => '0'); -- in_port
signal pio3_export : std_logic_vector(7 downto 0); -- out_port
signal prim_uart_rxd : std_logic := '1';
signal prim_uart_txd : std_logic := '1';
signal prim_uart_cts_n : std_logic := '1';
signal prim_uart_rts_n : std_logic := '1';
signal io_uart_rxd : std_logic := '1';
signal io_uart_txd : std_logic := '1';
signal slot_test_vector : std_logic_vector(47 downto 0);
signal jtag_write_vector : std_logic_vector(7 downto 0);
-- Parallel cable connection
signal drv_via1_port_a_o : std_logic_vector(7 downto 0);
signal drv_via1_port_a_i : std_logic_vector(7 downto 0);
signal drv_via1_port_a_t : std_logic_vector(7 downto 0);
signal drv_via1_ca2_o : std_logic;
signal drv_via1_ca2_i : std_logic;
signal drv_via1_ca2_t : std_logic;
signal drv_via1_cb1_o : std_logic;
signal drv_via1_cb1_i : std_logic;
signal drv_via1_cb1_t : std_logic;
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_last : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic := '1';
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
begin
process(RMII_REFCLK)
begin
if rising_edge(RMII_REFCLK) then
if jtag_write_vector(7) = '1' then
por_count <= (others => '0');
por_n <= '0';
elsif por_count = X"FFFFF" then
por_n <= '1';
else
por_count <= por_count + 1;
por_n <= '0';
end if;
end if;
end process;
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_count <= sys_count + 1;
end if;
end process;
ref_reset <= not por_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => pll_locked );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => sys_reset,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => ulpi_reset_req,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
i_nios: nios_dut
port map (
audio_in_data => audio_in_data,
audio_in_valid => audio_in_valid,
audio_in_ready => audio_in_ready,
audio_out_data => audio_out_data,
audio_out_valid => audio_out_valid,
audio_out_ready => audio_out_ready,
dummy_export => '0',
io_ack => io_resp.ack,
io_rdata => io_resp.data,
io_read => io_req.read,
io_wdata => io_req.data,
io_write => io_req.write,
unsigned(io_address) => io_req.address,
io_irq => io_irq,
io_u2p_ack => io_u2p_resp.ack,
io_u2p_rdata => io_u2p_resp.data,
io_u2p_read => io_u2p_req.read,
io_u2p_wdata => io_u2p_req.data,
io_u2p_write => io_u2p_req.write,
unsigned(io_u2p_address) => io_u2p_req.address,
io_u2p_irq => '0',
jtag_io_input_vector => slot_test_vector,
jtag_io_output_vector => jtag_write_vector,
jtag_test_clocks_clock_1 => RMII_REFCLK,
jtag_test_clocks_clock_2 => ULPI_CLOCK,
unsigned(mem_mem_req_address) => cpu_mem_req.address,
mem_mem_req_byte_en => cpu_mem_req.byte_en,
mem_mem_req_read_writen => cpu_mem_req.read_writen,
mem_mem_req_request => cpu_mem_req.request,
mem_mem_req_tag => cpu_mem_req.tag,
mem_mem_req_wdata => cpu_mem_req.data,
mem_mem_resp_dack_tag => cpu_mem_resp.dack_tag,
mem_mem_resp_data => cpu_mem_resp.data,
mem_mem_resp_rack_tag => cpu_mem_resp.rack_tag,
pio1_export => pio1_export,
pio2_export => pio2_export,
pio3_export => pio3_export,
sys_clock_clk => sys_clock,
sys_reset_reset_n => not sys_reset,
uart_rxd => prim_uart_rxd,
uart_txd => prim_uart_txd,
uart_cts_n => prim_uart_cts_n,
uart_rts_n => prim_uart_rts_n
);
UART_TXD <= prim_uart_txd and io_uart_txd;
prim_uart_rxd <= UART_RXD;
io_uart_rxd <= UART_RXD;
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 10,
g_ports => 3
)
port map (
clock => sys_clock,
req => io_u2p_req,
resp => io_u2p_resp,
reqs(0) => io_req_new_io,
reqs(1) => io_req_ddr2,
reqs(2) => io_req_remote,
resps(0) => io_resp_new_io,
resps(1) => io_resp_ddr2,
resps(2) => io_resp_remote
);
i_memphy: entity work.ddr2_ctrl
port map (
ref_clock => RMII_REFCLK,
ref_reset => ref_reset,
sys_clock_o => sys_clock,
sys_reset_o => sys_reset,
clock => sys_clock,
reset => sys_reset,
io_req => io_req_ddr2,
io_resp => io_resp_ddr2,
inhibit => '0', --memctrl_inhibit,
is_idle => is_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_ODT => SDRAM_ODT,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA(1 downto 0),
SDRAM_DM => SDRAM_DM,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS
);
i_remote: entity work.update_io
port map (
clock => sys_clock,
reset => sys_reset,
slow_clock => audio_clock,
slow_reset => audio_reset,
io_req => io_req_remote,
io_resp => io_resp_remote,
flash_selck => FLASH_SELCK,
flash_sel => FLASH_SEL
);
i_u2p_io: entity work.u2p_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_new_io,
io_resp => io_resp_new_io,
mdc => MDIO_CLK,
mdio_i => MDIO_DATA,
mdio_o => mdio_o,
i2c_scl_i => i2c_scl_i,
i2c_scl_o => i2c_scl_o,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
iec_i => "1111",
board_rev => not BOARD_REVn,
iec_o => open,
eth_irq_i => ETH_IRQn,
speaker_en => SPEAKER_ENABLE,
hub_reset_n=> HUB_RESETn,
ulpi_reset => ulpi_reset_req
);
i2c_scl_i <= I2C_SCL and I2C_SCL_18;
i2c_sda_i <= I2C_SDA and I2C_SDA_18;
I2C_SCL <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA <= '0' when i2c_sda_o = '0' else 'Z';
I2C_SCL_18 <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA_18 <= '0' when i2c_sda_o = '0' else 'Z';
MDIO_DATA <= '0' when mdio_o = '0' else 'Z';
i_logic: entity work.ultimate_logic_32
generic map (
g_version => X"7F",
g_simulation => false,
g_ultimate2plus => true,
g_clock_freq => 62_500_000,
g_numerator => 32,
g_denominator => 125,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_microblaze => false,
g_big_endian => false,
g_icap => false,
g_uart => true,
g_uart_rx => true,
g_drive_1541 => false,
g_drive_1541_2 => false,
g_hardware_gcr => false,
g_ram_expansion => false,
g_extended_reu => false,
g_stereo_sid => false,
g_hardware_iec => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_cartridge => false,
g_command_intf => false,
g_drive_sound => false,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => false,
g_rmii => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
ext_io_req => io_req,
ext_io_resp => io_resp,
ext_mem_req => cpu_mem_req,
ext_mem_resp=> cpu_mem_resp,
cpu_irq => io_irq,
-- local bus side
mem_req => mem_req,
mem_resp => mem_resp,
-- Debug UART
UART_TXD => io_uart_txd,
UART_RXD => io_uart_rxd,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Parallel cable pins
drv_via1_port_a_o => drv_via1_port_a_o,
drv_via1_port_a_i => drv_via1_port_a_i,
drv_via1_port_a_t => drv_via1_port_a_t,
drv_via1_ca2_o => drv_via1_ca2_o,
drv_via1_ca2_i => drv_via1_ca2_i,
drv_via1_ca2_t => drv_via1_ca2_t,
drv_via1_cb1_o => drv_via1_cb1_o,
drv_via1_cb1_i => drv_via1_cb1_i,
drv_via1_cb1_t => drv_via1_cb1_t,
-- Ethernet interface
eth_clock => RMII_REFCLK,
eth_reset => eth_reset,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_eof => eth_tx_last,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
-- Buttons
BUTTON => not BUTTON );
-- Parallel cable not implemented. This is the way to stub it...
drv_via1_port_a_i <= drv_via1_port_a_o or not drv_via1_port_a_t;
drv_via1_ca2_i <= drv_via1_ca2_o or not drv_via1_ca2_t;
drv_via1_cb1_i <= drv_via1_cb1_o or not drv_via1_cb1_t;
-- Transceiver
i_rmii: entity work.rmii_transceiver
port map (
clock => RMII_REFCLK,
reset => eth_reset,
rmii_crs_dv => RMII_CRS_DV,
rmii_rxd => RMII_RX_DATA,
rmii_tx_en => RMII_TX_EN,
rmii_txd => RMII_TX_DATA,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_eof => eth_tx_last,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => '0' );
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_divider => 10,
g_left_shift => 0,
g_width => audio_speaker'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => audio_speaker,
dac_out => SPEAKER_DATA );
audio_speaker(15 downto 8) <= signed(audio_out_data(15 downto 8));
audio_speaker( 7 downto 0) <= signed(audio_out_data(23 downto 16));
process(jtag_write_vector, pio3_export, sys_count, pll_locked, por_n)
begin
case jtag_write_vector(6 downto 5) is
when "00" =>
LED_MOTORn <= sys_count(sys_count'high);
LED_DISKn <= pll_locked; -- if pll_locked = 0, led is on
LED_CARTn <= por_n; -- if por_n is 0, led is on
LED_SDACTn <= '0';
when "01" =>
LED_MOTORn <= not jtag_write_vector(0);
LED_DISKn <= not jtag_write_vector(1);
LED_CARTn <= not jtag_write_vector(2);
LED_SDACTn <= not jtag_write_vector(3);
when "10" =>
LED_MOTORn <= not pio3_export(0);
LED_DISKn <= not pio3_export(1);
LED_CARTn <= not pio3_export(2);
LED_SDACTn <= not pio3_export(3);
when others =>
LED_MOTORn <= '1';
LED_DISKn <= '1';
LED_CARTn <= '1';
LED_SDACTn <= '1';
end case;
end process;
ULPI_RESET <= por_n;
b_audio: block
signal stream_out_data : std_logic_vector(23 downto 0);
signal stream_out_tag : std_logic_vector(0 downto 0);
signal stream_out_valid : std_logic;
signal stream_in_data : std_logic_vector(23 downto 0);
signal stream_in_tag : std_logic_vector(0 downto 0);
signal stream_in_ready : std_logic;
signal audio_out_full : std_logic;
begin
i_aout: entity work.async_fifo_ft
generic map (
g_depth_bits => 4,
g_data_width => 25
)
port map(
wr_clock => sys_clock,
wr_reset => sys_reset,
wr_en => audio_out_valid,
wr_din(24) => audio_out_data(0),
wr_din(23 downto 16) => audio_out_data(15 downto 8),
wr_din(15 downto 8) => audio_out_data(23 downto 16),
wr_din(7 downto 0) => audio_out_data(31 downto 24),
wr_full => audio_out_full,
rd_clock => audio_clock,
rd_reset => audio_reset,
rd_next => stream_in_ready,
rd_dout(24 downto 24) => stream_in_tag,
rd_dout(23 downto 0) => stream_in_data,
rd_valid => open --stream_in_valid
);
audio_out_ready <= not audio_out_full;
i_ain: entity work.synchronizer_gzw
generic map(
g_width => 25,
g_fast => false
)
port map(
tx_clock => audio_clock,
tx_push => stream_out_valid,
tx_data(24 downto 24) => stream_out_tag,
tx_data(23 downto 0) => stream_out_data,
tx_done => open,
rx_clock => sys_clock,
rx_new_data => audio_in_valid,
rx_data(24) => audio_in_data(0),
rx_data(23 downto 16) => audio_in_data(15 downto 8),
rx_data(15 downto 8) => audio_in_data(23 downto 16),
rx_data(7 downto 0) => audio_in_data(31 downto 24)
);
i2s: entity work.i2s_serializer_old
port map (
clock => audio_clock,
reset => audio_reset,
i2s_out => AUDIO_SDO,
i2s_in => AUDIO_SDI,
i2s_bclk => AUDIO_BCLK,
i2s_fs => AUDIO_LRCLK,
stream_out_data => stream_out_data,
stream_out_tag => stream_out_tag,
stream_out_valid => stream_out_valid,
stream_in_data => stream_in_data,
stream_in_tag => stream_in_tag,
stream_in_valid => '1',
stream_in_ready => stream_in_ready );
AUDIO_MCLK <= audio_clock;
end block;
SLOT_BUFFER_ENn <= '0'; -- once configured, we can connect
pio1_export(31 downto 0) <= slot_test_vector(31 downto 0);
pio2_export(15 downto 0) <= slot_test_vector(47 downto 32);
pio2_export(18 downto 16) <= not BUTTON;
slot_test_vector <= CAS_MOTOR &
CAS_SENSE &
CAS_READ &
CAS_WRITE &
IEC_ATN &
IEC_DATA &
IEC_CLOCK &
IEC_RESET &
IEC_SRQ_IN &
SLOT_PHI2 &
SLOT_DOTCLK &
SLOT_RSTn &
SLOT_RWn &
SLOT_BA &
SLOT_DMAn &
SLOT_EXROMn &
SLOT_GAMEn &
SLOT_ROMHn &
SLOT_ROMLn &
SLOT_IO1n &
SLOT_IO2n &
SLOT_IRQn &
SLOT_NMIn &
SLOT_VCC &
SLOT_DATA &
SLOT_ADDR;
SLOT_RST_DRV <= '0'; -- Cannot be tested, because tester supplies a signal onto all pins
end architecture;
| gpl-3.0 | 48c5c8fa09162a42842c48c89594c25e | 0.453465 | 3.443056 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/submodules/flink_definitions.vhd | 1 | 3,686 | -------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- fLink definitions --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE fLink_definitions IS
-- Global
CONSTANT c_fLink_avs_data_width : INTEGER := 32;
CONSTANT c_fLink_avs_data_width_in_byte : INTEGER := c_fLink_avs_data_width/8;
-- Header registers
CONSTANT c_fLink_number_of_std_registers : INTEGER := 8;
CONSTANT c_fLink_typdef_address : INTEGER := 0;
CONSTANT c_fLink_mem_size_address : INTEGER := 1;
CONSTANT c_fLink_number_of_channels_address : INTEGER := 2;
CONSTANT c_fLink_unique_id_address : INTEGER := 3;
CONSTANT c_fLink_status_address : INTEGER := 4;
CONSTANT c_fLink_configuration_address : INTEGER := 5;
CONSTANT c_fLink_id_length : INTEGER := 16;
CONSTANT c_fLink_subtype_length : INTEGER := 8;
CONSTANT c_fLink_interface_version_length : INTEGER := 8;
CONSTANT c_fLink_reset_bit_num : INTEGER := 0;
-- Interface IDs:
CONSTANT c_fLink_info_id : INTEGER := 0;
CONSTANT c_fLink_analog_input_id : INTEGER := 1;
CONSTANT c_fLink_analog_output_id : INTEGER := 2;
CONSTANT c_fLink_digital_io_id : INTEGER := 5;
CONSTANT c_fLink_counter_id : INTEGER := 6;
CONSTANT c_fLink_timer_id : INTEGER := 7;
CONSTANT c_fLink_memory_id : INTEGER := 8;
CONSTANT c_fLink_pwm_out_id : INTEGER := 12;
CONSTANT c_fLink_ppwa_id : INTEGER := 13;
CONSTANT c_fLink_watchdog_id : INTEGER := 16;
CONSTANT c_fLink_sensor_id : INTEGER := 17;
END PACKAGE fLink_definitions;
| apache-2.0 | 08619e2f9b3b6f5cfb8dbc7279f7978e | 0.400977 | 4.388095 | false | false | false | false |
ringof/radiofist_audio | testbench/tb_clock.vhd | 1 | 1,400 | -- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See licence.txt for details
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_clock IS
END tb_clock;
ARCHITECTURE behavior OF tb_clock IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clock
PORT(
clk_in : IN std_logic;
reset : IN std_logic;
clk_6mhz : OUT std_logic;
decimation_clk : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_in : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal clk_6mhz : std_logic;
signal decimation_clk : std_logic;
-- Clock period definitions
constant clk_in_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: clock PORT MAP (
clk_in => clk_in,
reset => reset,
clk_6mhz => clk_6mhz,
decimation_clk => decimation_clk
);
-- Clock process definitions
clk_in_process :process
begin
clk_in <= '0';
wait for clk_in_period/2;
clk_in <= '1';
wait for clk_in_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for multiple of clk_in_period.
reset <= '1';
wait for 1000ns;
-- insert stimulus here
reset <= '0';
wait for clk_in_period*(100000);
wait;
end process;
END;
| mit | 3f4d7db41bd3ab8c66b5bc5265af3413 | 0.595 | 3.508772 | false | false | false | false |
xiadz/oscilloscope | src/main.vhd | 1 | 9,025 | ----------------------------------------------------------------------------------
-- Author: Marcin Osowski
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.types.all;
entity oscilloscope is
port(
uclk : in std_logic; -- 32 MHz stable
sw : in std_logic_vector (6 downto 0);
btn : in std_logic_vector (3 downto 0);
red : in std_logic;
green : in std_logic;
blue : in std_logic;
-- Project does not use any of the below
-- pins. They are here just to give them
-- constant value.
led : out std_logic_vector (7 downto 0);
seg : out std_logic_vector (7 downto 0);
an : out std_logic_vector (3 downto 0);
hsync : out std_logic;
vsync : out std_logic;
vout : out std_logic_vector (7 downto 0)
);
end entity oscilloscope;
architecture structural of oscilloscope is
signal rst : std_logic;
signal nrst : std_logic;
signal clk108 : std_logic;
signal clk108_ok : std_logic;
signal clk10khz : std_logic;
signal sw_3_delayed : std_logic_vector (6 downto 0);
signal btn_3_delayed : std_logic_vector (2 downto 0);
signal sw_debounced : std_logic_vector (6 downto 0);
signal btn_debounced : std_logic_vector (2 downto 0);
signal red_3_delayed : std_logic;
signal green_3_delayed : std_logic;
signal blue_3_delayed : std_logic;
signal trigger_btn : std_logic;
signal trigger_event : TRIGGER_EVENT_T;
signal red_enable : std_logic;
signal green_enable : std_logic;
signal blue_enable : std_logic;
signal continue_after_reading : std_logic;
signal time_resolution : integer range 0 to 15;
signal time_resolution_delayed : integer range 0 to 15;
signal overflow_indicator : std_logic;
signal red_after_trigger : std_logic;
signal green_after_trigger : std_logic;
signal blue_after_trigger : std_logic;
signal is_reading_active : std_logic;
signal flush_and_return_to_zero : std_logic;
signal write_enable : std_logic;
signal reader_red_value : std_logic;
signal reader_green_value : std_logic;
signal reader_blue_value : std_logic;
signal reader_screen_segment : natural range 0 to 13;
signal reader_screen_column : natural range 0 to 1279;
signal pre_hsync : std_logic;
signal pre_vsync : std_logic;
signal pre_vout : std_logic_vector (7 downto 0);
signal wea : std_logic;
signal addra : std_logic_vector (12 downto 0);
signal dina : std_logic_vector (8 downto 0);
signal addrb : std_logic_vector (12 downto 0);
signal doutb : std_logic_vector (8 downto 0);
begin
led <= (others => '0');
seg <= (others => '1');
an <= (others => '1');
display_clock_108mhz: entity work.clock_108mhz
port map (
CLKIN_IN => uclk,
RST_IN => btn (3),
CLKFX_OUT => clk108,
CLKIN_IBUFG_OUT => open,
LOCKED_OUT => clk108_ok
);
rst <= btn (3) and clk108_ok;
nrst <= not rst;
divider_10khz: entity work.divider
generic map (
n => 5400
)
port map (
clk_in => clk108,
nrst => nrst,
clk_out => clk10khz
);
btn_sw_3_delayer : entity work.n_cycles_delayer
generic map (
n => 3,
signal_width => 10
)
port map (
nrst => nrst,
clk => clk10khz,
input (9 downto 7) => btn (2 downto 0),
input (6 downto 0) => sw (6 downto 0),
output (9 downto 7) => btn_3_delayed (2 downto 0),
output (6 downto 0) => sw_3_delayed (6 downto 0)
);
input_signals_3_delayer : entity work.n_cycles_delayer
generic map (
n => 3,
signal_width => 3
)
port map (
nrst => nrst,
clk => clk108,
input (2) => red,
input (1) => green,
input (0) => blue,
output (2) => red_3_delayed,
output (1) => green_3_delayed,
output (0) => blue_3_delayed
);
btn_sw_debouncers: entity work.debouncer
generic map (
n => 50,
signal_width => 10
)
port map (
nrst => nrst,
clk => clk10khz,
input (9 downto 7) => btn_3_delayed,
input (6 downto 0) => sw_3_delayed,
output (9 downto 7) => btn_debounced,
output (6 downto 0) => sw_debounced
);
settings: entity work.settings
port map (
nrst => nrst,
clk108 => clk108,
sw => sw_debounced,
btn => btn_debounced,
trigger_btn => trigger_btn,
trigger_event => trigger_event,
red_enable => red_enable,
green_enable => green_enable,
blue_enable => blue_enable,
continue_after_reading => continue_after_reading,
time_resolution => time_resolution
);
trigger: entity work.trigger
port map (
nrst => nrst,
clk108 => clk108,
trigger_btn => trigger_btn,
trigger_event => trigger_event,
red_enable => red_enable,
green_enable => green_enable,
blue_enable => blue_enable,
continue_after_reading => continue_after_reading,
red_input => red_3_delayed,
green_input => green_3_delayed,
blue_input => blue_3_delayed,
overflow_indicator => overflow_indicator,
red_output => red_after_trigger,
green_output => green_after_trigger,
blue_output => blue_after_trigger,
is_reading_active => is_reading_active
);
time_resolution_delayed <= time_resolution when rising_edge (clk108);
reader: entity work.reader
port map (
nrst => nrst,
clk108 => clk108,
input_red => red_after_trigger,
input_green => green_after_trigger,
input_blue => blue_after_trigger,
is_reading_active => is_reading_active,
time_resolution => time_resolution_delayed,
overflow_indicator => overflow_indicator,
screen_segment => reader_screen_segment,
screen_column => reader_screen_column,
flush_and_return_to_zero => flush_and_return_to_zero,
write_enable => write_enable,
red_value => reader_red_value,
green_value => reader_green_value,
blue_value => reader_blue_value
);
bits_aggregator: entity work.bits_aggregator
port map (
nrst => nrst,
clk108 => clk108,
flush_and_return_to_zero => flush_and_return_to_zero,
write_enable => write_enable,
red_value => reader_red_value,
green_value => reader_green_value,
blue_value => reader_blue_value,
wea => wea,
addra => addra,
dina => dina
);
oscilloscope_display: entity work.oscilloscope_display
port map (
nrst => nrst,
clk108 => clk108,
is_reading_active => is_reading_active,
trigger_event => trigger_event,
red_enable => red_enable,
green_enable => green_enable,
blue_enable => blue_enable,
continue_after_reading => continue_after_reading,
time_resolution => time_resolution,
currently_read_screen_segment => reader_screen_segment,
currently_read_screen_column => reader_screen_column,
addrb => addrb,
doutb => doutb,
vout => pre_vout,
vsync => pre_vsync,
hsync => pre_hsync
);
vga_signal_formatter: entity work.one_cycle_delayer
generic map (
signal_width => 10
)
port map (
nrst => nrst,
clk => clk108,
input (9 downto 2) => pre_vout,
input (1) => pre_vsync,
input (0) => pre_hsync,
output (9 downto 2) => vout,
output (1) => vsync,
output (0) => hsync
);
trace_memory: entity work.trace_memory
port map (
clka => clk108,
wea(0) => wea,
addra => addra,
dina => dina,
clkb => clk108,
rstb => rst,
addrb => addrb,
doutb => doutb
);
end architecture structural;
| mit | e5c15606f08c55544c921731a8628815 | 0.510914 | 4.139908 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/c2n_playback/vhdl_sim/tape_speed_control_tb.vhd | 1 | 1,162 | --------------------------------------------------------------------------------
-- Entity: tape_speed_control_tb
-- Date:2016-04-17
-- Author: Gideon
--
-- Description: Testbench
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tape_speed_control_tb is
end tape_speed_control_tb;
architecture arch of tape_speed_control_tb is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal tick_out : std_logic;
signal motor_en : std_logic;
signal clock_stop : boolean := false;
begin
clock <= not clock after 10 ns when not clock_stop;
reset <= '1', '0' after 100 ns;
i_mut: entity work.tape_speed_control
port map (
clock => clock,
reset => reset,
motor_en => motor_en,
tick_out => tick_out
);
p_test: process
begin
motor_en <= '0';
wait for 1 ms;
motor_en <= '1';
wait for 199 ms;
motor_en <= '0';
wait for 400 ms;
clock_stop <= true;
end process;
end arch;
| gpl-3.0 | 75f6cec90bd00234bcfdd81f2f0f0acc | 0.491394 | 3.886288 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_source/usb1_ulpi_rx.vhd | 2 | 5,945 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
entity usb1_ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
pid : out std_logic_vector(3 downto 0);
valid_token : out std_logic;
valid_handsh : out std_logic;
token : out std_logic_vector(10 downto 0);
valid_packet : out std_logic;
data_valid : out std_logic;
data_start : out std_logic;
data_out : out std_logic_vector(7 downto 0);
error : out std_logic );
end usb1_ulpi_rx;
architecture gideon of usb1_ulpi_rx is
type t_state is (idle, token1, token2, check_token, check_token2, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(10 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_in : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
begin
token <= token_i;
data_out <= rx_data;
data_valid <= rx_store when state = data else '0';
process(clock)
begin
if rising_edge(clock) then
data_start <= '0';
error <= '0';
valid_token <= '0';
valid_packet <= '0';
valid_handsh <= '0';
case state is
when idle =>
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_allow_token then
state <= token1;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token1 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= idle; -- good enough?
end if;
when token2 =>
if rx_store='1' then
token_i(10 downto 8) <= rx_data(2 downto 0);
crc_in <= rx_data(7 downto 3);
state <= check_token;
end if;
when data =>
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
state <= check_token2; -- delay
when check_token2 =>
if crc_in = token_crc then
valid_token <= '1';
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
end if;
end if;
end process;
r_token: if g_allow_token generate
i_token_crc: entity work.usb1_token_crc
port map (
clock => clock,
sync => '1',
token_in => token_i,
crc => token_crc );
end generate;
crc_sync <= '1' when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
i_data_crc: entity work.usb1_data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => rx_data,
crc => data_crc );
end gideon;
| gpl-3.0 | 2533e9585f995ef945760f15658e32ad | 0.379479 | 4.552067 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/megafunctions/update/update_inst.vhd | 1 | 1,451 | component update is
port (
busy : out std_logic; -- busy
data_out : out std_logic_vector(28 downto 0); -- data_out
param : in std_logic_vector(2 downto 0) := (others => 'X'); -- param
read_param : in std_logic := 'X'; -- read_param
reconfig : in std_logic := 'X'; -- reconfig
reset_timer : in std_logic := 'X'; -- reset_timer
read_source : in std_logic_vector(1 downto 0) := (others => 'X'); -- read_source
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X' -- reset
);
end component update;
u0 : component update
port map (
busy => CONNECTED_TO_busy, -- busy.busy
data_out => CONNECTED_TO_data_out, -- data_out.data_out
param => CONNECTED_TO_param, -- param.param
read_param => CONNECTED_TO_read_param, -- read_param.read_param
reconfig => CONNECTED_TO_reconfig, -- reconfig.reconfig
reset_timer => CONNECTED_TO_reset_timer, -- reset_timer.reset_timer
read_source => CONNECTED_TO_read_source, -- read_source.read_source
clock => CONNECTED_TO_clock, -- clock.clk
reset => CONNECTED_TO_reset -- reset.reset
);
| gpl-3.0 | 99343a27918f6a43003a8ce4c780174f | 0.475534 | 3.618454 | false | true | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/host_sequencer.vhd | 1 | 17,784 | -------------------------------------------------------------------------------
-- Title : host_sequencer
-- Author : Gideon Zweijtzer
-------------------------------------------------------------------------------
-- Description: This block generates the traffic on the downstream USB port.
-- This block has knowledge about the speeds, the USB frames,
-- and generates traffic within the right time within the frame.
-- The data interface of this block is a BRAM interface. This
-- block implements the three-time retry as well.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
use work.usb_cmd_pkg.all;
--use work.tl_sctb_pkg.all;
--use work.tl_string_util_pkg.all;
entity host_sequencer is
generic (
g_buffer_depth_bits : natural := 11 ); -- 2K
port (
clock : in std_logic;
reset : in std_logic;
-- Access to buffer memory
buf_address : out unsigned(g_buffer_depth_bits-1 downto 0);
buf_en : out std_logic;
buf_we : out std_logic;
buf_rdata : in std_logic_vector(7 downto 0);
buf_wdata : out std_logic_vector(7 downto 0);
-- mode selection
sof_enable : in std_logic;
sof_tick : out std_logic;
speed : in std_logic_vector(1 downto 0);
frame_count : out unsigned(15 downto 0);
error_pulse : out std_logic;
-- low level command interface
usb_cmd_req : in t_usb_cmd_req;
usb_cmd_resp : out t_usb_cmd_resp;
-- I/O to interface block
usb_rx : in t_usb_rx;
usb_tx_req : out t_usb_tx_req;
usb_tx_resp : in t_usb_tx_resp );
end entity;
architecture rtl of host_sequencer is
-- length identifiers to ram address counters
signal tx_length : unsigned(9 downto 0) := (others => '0');
signal tx_no_data : std_logic := '1';
signal receive_en : std_logic := '0';
signal rx_length : unsigned(9 downto 0);
signal rx_no_data : std_logic;
signal send_packet_cmd : std_logic;
signal usb_tx_req_i : t_usb_tx_req;
signal valid_packet_received : std_logic;
signal data_toggle_received : std_logic := '0';
signal data_transmission_done : std_logic := '0';
begin
b_bram_control: block
signal buffer_addr_i : unsigned(9 downto 0) := (others => '1'); -- was undefined
type t_state is (idle, prefetch, transmit_msg, wait_tx_done);
signal state : t_state;
signal transmit_en : std_logic := '0';
signal tx_last_i : std_logic;
signal tx_data_valid : std_logic;
signal tx_send_packet : std_logic;
signal buffer_index : unsigned(1 downto 0);
begin
buffer_index <= usb_cmd_req.buffer_index;
buf_address <= buffer_index & buffer_addr_i(8 downto 0);
buf_we <= usb_rx.data_valid and receive_en;
buf_wdata <= usb_rx.data;
buf_en <= receive_en or transmit_en;
transmit_en <= '1' when (state = prefetch) or
((state = transmit_msg) and (usb_tx_resp.data_wait='0'))
else '0';
tx_data_valid <= '1' when (state = transmit_msg) and (usb_tx_resp.data_wait='0')
else '0';
tx_last_i <= '1' when (buffer_addr_i = tx_length) else '0';
process(clock)
begin
if rising_edge(clock) then
if usb_rx.data_start = '1' or send_packet_cmd = '1' then
-- if (send_packet_cmd = '0') then
-- sctb_trace("Receiving data in buffer " & hstr(buffer_index));
-- end if;
buffer_addr_i <= (others => '0');
rx_no_data <= '1';
elsif (receive_en = '1' and usb_rx.data_valid = '1') or
((transmit_en = '1') and not (tx_last_i='1' and tx_data_valid='1')) then
buffer_addr_i <= buffer_addr_i + 1;
rx_no_data <= '0';
end if;
valid_packet_received <= '0';
data_transmission_done <= '0';
if usb_rx.valid_packet = '1' and receive_en='1' then
rx_length <= buffer_addr_i;
valid_packet_received <= '1';
data_toggle_received <= get_togglebit(usb_rx.pid);
end if;
case state is
when idle =>
if send_packet_cmd = '1' then
-- sctb_trace("Sending data from buffer " & hstr(buffer_index));
state <= prefetch;
end if;
when prefetch =>
tx_send_packet <= '1';
state <= transmit_msg;
when transmit_msg =>
if tx_send_packet = '0' and tx_no_data = '1' then
state <= wait_tx_done;
elsif tx_last_i = '1' and tx_data_valid = '1' then
state <= wait_tx_done;
end if;
when wait_tx_done =>
if usb_tx_resp.busy = '0' then
data_transmission_done <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if usb_tx_resp.request_ack = '1' then
tx_send_packet <= '0';
end if;
if reset='1' then
state <= idle;
buffer_addr_i <= (others => '0');
tx_send_packet <= '0';
end if;
end if;
end process;
usb_tx_req_i.data <= buf_rdata;
usb_tx_req_i.data_valid <= tx_data_valid;
usb_tx_req_i.data_last <= tx_last_i when transmit_en='1' else '0';
usb_tx_req_i.send_packet <= tx_send_packet;
usb_tx_req_i.no_data <= tx_no_data;
end block;
usb_tx_req <= usb_tx_req_i;
b_replay: block
type t_state is (idle, wait_sof, wait_split_done, do_token, wait_token_done, do_data, wait_tx_done, wait_device_response, wait_handshake_done );
signal state : t_state;
signal timeout : std_logic;
signal start_timer : std_logic;
signal cmd_done : std_logic;
signal frame_div : integer range 0 to 8191;
signal frame_cnt : unsigned(15 downto 0) := (others => '0');
signal do_sof : std_logic;
signal sof_guard : std_logic := '0';
signal start_split_active : boolean;
signal complete_split_active : boolean;
begin
start_split_active <= (usb_cmd_req.do_split = '1') and (usb_cmd_req.split_sc = '0') and (speed = "10");
complete_split_active <= (usb_cmd_req.do_split = '1') and (usb_cmd_req.split_sc = '1') and (speed = "10");
process(clock)
begin
if rising_edge(clock) then
send_packet_cmd <= '0';
if frame_div = 800 then -- the last ~10% is unused for new transactions (test)
sof_guard <= '1';
end if;
if frame_div = 0 then
frame_div <= 7499; -- microframes
do_sof <= sof_enable;
sof_guard <= '0';
frame_cnt <= frame_cnt + 1;
else
frame_div <= frame_div - 1;
end if;
cmd_done <= '0';
sof_tick <= '0';
case state is
when idle =>
receive_en <= '0';
if do_sof='1' then
sof_tick <= '1';
do_sof <= '0';
usb_tx_req_i.pid <= c_pid_sof;
usb_tx_req_i.token.device_addr <= std_logic_vector(frame_cnt(9 downto 3));
usb_tx_req_i.token.endpoint_addr <= std_logic_vector(frame_cnt(13 downto 10));
case speed is
when "00" => -- low speed
if frame_cnt(2 downto 0) = "000" then
usb_tx_req_i.send_handsh <= '1';
state <= wait_sof;
end if;
when "01" => -- full speed
if frame_cnt(2 downto 0) = "000" then
usb_tx_req_i.send_token <= '1';
state <= wait_sof;
end if;
when "10" => -- high speed
usb_tx_req_i.send_token <= '1';
state <= wait_sof;
when others =>
null;
end case;
elsif sof_guard = '0' and usb_cmd_req.request = '1' and cmd_done = '0' then
-- default response
usb_cmd_resp.no_data <= '1';
usb_cmd_resp.data_length <= (others => '0');
usb_cmd_resp.togglebit <= '0';
usb_tx_req_i.split_token.e <= '0';
usb_tx_req_i.split_token.et <= usb_cmd_req.split_et;
usb_tx_req_i.split_token.sc <= usb_cmd_req.split_sc;
usb_tx_req_i.split_token.s <= usb_cmd_req.split_sp;
usb_tx_req_i.split_token.hub_address <= std_logic_vector(usb_cmd_req.split_hub_addr);
usb_tx_req_i.split_token.port_address <= "000" & std_logic_vector(usb_cmd_req.split_port_addr);
usb_tx_req_i.token.device_addr <= std_logic_vector(usb_cmd_req.device_addr);
usb_tx_req_i.token.endpoint_addr <= std_logic_vector(usb_cmd_req.endp_addr);
if usb_cmd_req.do_split = '1' then
usb_tx_req_i.pid <= c_pid_split;
usb_tx_req_i.send_split <= '1';
state <= wait_split_done;
else
state <= do_token;
end if;
end if;
when wait_sof =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
state <= idle;
end if;
when wait_split_done =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
state <= do_token;
end if;
when do_token =>
usb_tx_req_i.send_token <= '1';
state <= wait_token_done;
case usb_cmd_req.command is
when setup =>
usb_tx_req_i.pid <= c_pid_setup;
when in_request =>
usb_tx_req_i.pid <= c_pid_in;
when out_data =>
usb_tx_req_i.pid <= c_pid_out;
when others =>
usb_tx_req_i.pid <= c_pid_ping;
end case;
when wait_token_done =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
state <= do_data;
end if;
when do_data =>
case usb_cmd_req.command is
when setup | out_data =>
if usb_cmd_req.do_data = '1' then
send_packet_cmd <= '1';
tx_no_data <= usb_cmd_req.no_data;
tx_length <= usb_cmd_req.data_length;
if usb_cmd_req.togglebit='0' then
usb_tx_req_i.pid <= c_pid_data0;
else
usb_tx_req_i.pid <= c_pid_data1;
end if;
state <= wait_tx_done;
else
state <= wait_device_response;
end if;
when in_request =>
state <= wait_device_response;
receive_en <= usb_cmd_req.do_data;
when others =>
state <= wait_device_response;
end case;
when wait_tx_done =>
if data_transmission_done = '1' then
state <= wait_device_response;
end if;
when wait_device_response =>
usb_tx_req_i.pid <= c_pid_ack;
-- check if we did a start split to an interrupt (or iso) endpoint; in that case, we won't get any reply from the hub.
usb_cmd_resp.error_code <= "000";
if usb_cmd_req.split_et(0) = '1' and start_split_active then
usb_cmd_resp.result <= res_ack; -- we just fake the ack for the layer above that doesn't need to know about this USB quirk
cmd_done <= '1';
state <= idle;
elsif usb_rx.valid_handsh = '1' then
usb_cmd_resp.result <= encode_result(usb_rx.pid);
cmd_done <= '1';
state <= idle;
elsif usb_rx.error='1' or timeout='1' then
usb_cmd_resp.result <= res_error;
usb_cmd_resp.error_code <= usb_rx.error_code;
cmd_done <= '1';
state <= idle;
elsif valid_packet_received = '1' then -- woohoo!
usb_cmd_resp.result <= res_data;
usb_cmd_resp.no_data <= rx_no_data;
usb_cmd_resp.data_length <= rx_length;
usb_cmd_resp.togglebit <= data_toggle_received;
-- we send an ack to the device. Thank you!
if complete_split_active and usb_cmd_req.split_et(0)='1' then
cmd_done <= '1';
state <= idle;
else
usb_tx_req_i.send_handsh <= '1';
state <= wait_handshake_done;
end if;
end if;
when wait_handshake_done =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
cmd_done <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
usb_tx_req_i.pid <= X"0";
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_split <= '0';
usb_tx_req_i.send_handsh <= '0';
do_sof <= '0';
end if;
end if;
end process;
usb_cmd_resp.done <= cmd_done;
frame_count <= frame_cnt;
start_timer <= usb_tx_resp.busy or usb_rx.receiving;
i_timer: entity work.timer
generic map (
g_width => 10 )
port map (
clock => clock,
reset => reset,
start => start_timer,
start_value => to_unsigned(767, 10),
timeout => timeout );
end block;
i_error_pulse_timer: entity work.timer
generic map (
g_reset => '1',
g_width => 6
)
port map(
clock => clock,
reset => reset,
start => usb_rx.error,
start_value => to_unsigned(60, 6),
timeout => error_pulse -- active low, but that doesn't matter
);
end architecture;
| gpl-3.0 | e6e0c3678511c4add10475274e0c655a | 0.401934 | 4.277056 | false | false | false | false |
trondd/mkjpeg | design/quantizer/ROMQ.vhd | 2 | 2,839 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMQ.VHD
-- Created : Sun Aug 27 18:09 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT quantizer matrix
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity ROMQ is
generic
(
ROMADDR_W : INTEGER := 6;
ROMDATA_W : INTEGER := 8
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMQ;
architecture RTL of ROMQ is
type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER range 0 to 2**ROMDATA_W-1;
constant rom : ROMQ_TYPE :=
-- (
-- 16,11,10,16,24,40,51,61,
-- 12,12,14,19,26,58,60,55,
-- 14,13,16,24,40,57,69,56,
-- 14,17,22,29,51,87,80,62,
-- 18,22,37,56,68,109,103,77,
-- 24,35,55,64,81,104,113,92,
-- 49,64,78,87,103,121,120,101,
-- 72,92,95,98,112,100,103,99);
(
--8,6,6,7,6,5,8,
--7,7,7,9,9,8,10,12,
--20,13,12,11,11,12,25,18,19,15,20,29,
--26,31,30,29,26,28,28,32,36,46,39,32,
--34,44,35,28,28,40,55,41,44,48,49,52,52,52,
--31,39,57,61,56,50,60,46,51,52,50
1,1,1,1,1,1,1,1,
1,1,1,1,1,1,1,1,
1,1,1,1,1,1,1,1,
1,1,1,1,1,1,1,1,
1,1,1,1,1,1,1,1,
1,1,1,1,1,1,1,1,
1,1,1,1,1,1,1,1,
1,1,1,1,1,1,1,1
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
| lgpl-3.0 | 408054dbfc1fd694f18cd15e51949135 | 0.327932 | 3.602792 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_source/io_bus_bridge.vhd | 1 | 6,399 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_bus_bridge is
generic (
g_addr_width : natural := 8 );
port (
clock_a : in std_logic;
reset_a : in std_logic;
req_a : in t_io_req;
resp_a : out t_io_resp;
clock_b : in std_logic;
reset_b : in std_logic;
req_b : out t_io_req;
resp_b : in t_io_resp );
end entity;
architecture rtl of io_bus_bridge is
-- CLOCK_A
signal to_wr_en : std_logic;
signal to_wr_din : std_logic_vector(g_addr_width+8 downto 0);
signal to_wr_full : std_logic;
signal from_rd_en : std_logic;
signal from_rd_dout : std_logic_vector(7 downto 0);
signal from_rd_valid: std_logic;
type t_state_a is (idle, pending_w, pending_r, wait_rdata);
signal state_a : t_state_a;
-- CLOCK B
signal from_wr_en : std_logic;
signal to_rd_en : std_logic;
signal to_rd_dout : std_logic_vector(g_addr_width+8 downto 0);
signal to_rd_valid : std_logic;
type t_state_b is (idle, do_write, do_read);
signal state_b : t_state_b;
begin
-- generate ack
process(clock_a)
begin
if rising_edge(clock_a) then
resp_a.ack <= '0';
resp_a.data <= X"00";
case state_a is
when idle =>
if req_a.write='1' then
if to_wr_full = '1' then
state_a <= pending_w;
else
resp_a.ack <= '1';
end if;
elsif req_a.read='1' then
if to_wr_full = '1' then
state_a <= pending_r;
else
state_a <= wait_rdata;
end if;
end if;
when pending_w =>
if to_wr_full = '0' then
state_a <= idle;
resp_a.ack <= '1';
end if;
when pending_r =>
if to_wr_full = '0' then
state_a <= wait_rdata;
end if;
when wait_rdata =>
if from_rd_valid = '1' then
resp_a.ack <= '1';
resp_a.data <= from_rd_dout;
state_a <= idle;
end if;
when others =>
null;
end case;
if reset_a = '1' then
state_a <= idle;
end if;
end if;
end process;
process (state_a, to_wr_full, from_rd_valid, req_a)
begin
to_wr_en <= '0';
to_wr_din <= std_logic_vector(req_a.address(g_addr_width-1 downto 0)) & '0' & req_a.data;
from_rd_en <= '0';
case state_a is
when idle =>
if to_wr_full = '0' then
to_wr_en <= req_a.write or req_a.read;
to_wr_din(8) <= req_a.write;
end if;
when pending_w =>
if to_wr_full = '0' then
to_wr_en <= '1';
to_wr_din(8) <= '1';
end if;
when pending_r =>
if to_wr_full = '0' then
to_wr_en <= '1';
to_wr_din(8) <= '0';
end if;
when wait_rdata =>
if from_rd_valid='1' then
from_rd_en <= '1';
end if;
end case;
end process;
i_heen: entity work.async_fifo_ft
generic map (
g_data_width => g_addr_width + 9,
g_depth_bits => 3 )
port map (
wr_clock => clock_a,
wr_reset => reset_a,
wr_en => to_wr_en,
wr_din => to_wr_din,
wr_full => to_wr_full,
rd_clock => clock_b,
rd_reset => reset_b,
rd_next => to_rd_en,
rd_dout => to_rd_dout,
rd_valid => to_rd_valid );
i_weer: entity work.async_fifo_ft
generic map (
g_data_width => 8,
g_depth_bits => 3 )
port map (
wr_clock => clock_b,
wr_reset => reset_b,
wr_en => from_wr_en,
wr_din => resp_b.data,
rd_clock => clock_a,
rd_reset => reset_a,
rd_next => from_rd_en,
rd_dout => from_rd_dout,
rd_valid => from_rd_valid );
process(clock_b)
begin
if rising_edge(clock_b) then
req_b.read <= '0';
req_b.write <= '0';
case state_b is
when idle =>
if to_rd_valid='1' then
req_b.address(g_addr_width-1 downto 0) <= unsigned(to_rd_dout(g_addr_width+8 downto 9));
req_b.data <= to_rd_dout(7 downto 0);
if to_rd_dout(8)='1' then
req_b.write <= '1';
state_b <= do_write;
else
req_b.read <= '1';
state_b <= do_read;
end if;
end if;
when do_write =>
if resp_b.ack = '1' then
state_b <= idle;
end if;
when do_read =>
if resp_b.ack = '1' then
state_b <= idle;
end if;
end case;
if reset_b='1' then
state_b <= idle;
req_b <= c_io_req_init;
end if;
end if;
end process;
process(state_b, to_rd_valid, resp_b)
begin
to_rd_en <= '0';
from_wr_en <= '0';
case state_b is
when idle =>
if to_rd_valid = '1' then
to_rd_en <= '1';
end if;
when do_read =>
if resp_b.ack = '1' then
from_wr_en <= '1';
end if;
when others =>
null;
end case;
end process;
end rtl;
| gpl-3.0 | 1050c701277a6c5d4b383343a15c2f7d | 0.387248 | 3.709565 | false | false | false | false |
chiggs/nvc | test/regress/alias5.vhd | 5 | 1,222 | entity alias5 is
end entity;
architecture test of alias5 is
subtype bit_vector4 is bit_vector(3 downto 0);
type footype is ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0x, trx1, tr1x, trx0, trxz, trzx);
type bartype01 is array (footype range tr01 to tr10)
of time;
type yahtype01 is array (natural range <>) of bartype01;
procedure bufpath (
constant tpd : in yahtype01
) is
begin
report "tpd'left=" & integer'image(tpd'left);
report "tpd'right=" & integer'image(tpd'right);
end;
procedure vitalmux4 (
variable data : in bit_vector4;
constant tpd_data_q : in yahtype01
) is
alias atpd_data_q : yahtype01(data'range) is tpd_data_q;
begin
bufpath ( atpd_data_q );
assert atpd_data_q(data'left)(tr01) = 1 ns;
assert atpd_data_q(3 downto 3)(3)(tr01) = 1 ns;
end;
begin
process is
variable data : bit_vector4;
variable yah : yahtype01(5 downto 2);
begin
data := X"1";
yah := (others => (others => 1 ns ) );
vitalmux4(data, yah);
wait;
end process;
end architecture;
| gpl-3.0 | 5958244ad5f8962ed506c21ab2be3fd4 | 0.562193 | 3.311653 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_source/ethernet_rmii.vhd | 1 | 6,235 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : ethernet_rmii
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Filter block for ethernet frames
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.block_bus_pkg.all;
use work.mem_bus_pkg.all;
entity ethernet_rmii is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"12" );
port (
sys_clock : in std_logic;
sys_reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq_tx : out std_logic;
io_irq_rx : out std_logic;
-- interface to memory
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
----
eth_clock : in std_logic;
eth_reset : in std_logic;
rmii_crs_dv : in std_logic;
rmii_rxd : in std_logic_vector(1 downto 0);
rmii_tx_en : out std_logic;
rmii_txd : out std_logic_vector(1 downto 0) );
end entity;
architecture gideon of ethernet_rmii is
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_sof : std_logic := '0';
signal eth_tx_eof : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic;
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
signal ten_meg_mode : std_logic := '0';
signal io_req_free : t_io_req;
signal io_resp_free : t_io_resp;
signal io_req_rx : t_io_req;
signal io_resp_rx : t_io_resp;
signal io_req_tx : t_io_req;
signal io_resp_tx : t_io_resp;
signal alloc_req : std_logic := '0';
signal alloc_resp : t_alloc_resp;
signal used_req : t_used_req;
signal used_resp : std_logic;
signal mem_req_tx : t_mem_req_32;
signal mem_resp_tx : t_mem_resp_32;
signal mem_req_rx : t_mem_req_32;
signal mem_resp_rx : t_mem_resp_32;
begin
i_rmii: entity work.rmii_transceiver
port map (
clock => eth_clock,
reset => eth_reset,
rmii_crs_dv => rmii_crs_dv,
rmii_rxd => rmii_rxd,
rmii_tx_en => rmii_tx_en,
rmii_txd => rmii_txd,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => ten_meg_mode );
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 4,
g_range_hi => 5,
g_ports => 3
)
port map (
clock => sys_clock,
req => io_req,
resp => io_resp,
reqs(2) => io_req_free,
reqs(1) => io_req_tx,
reqs(0) => io_req_rx,
resps(2) => io_resp_free,
resps(1) => io_resp_tx,
resps(0) => io_resp_rx );
i_rx: entity work.eth_filter
generic map (
g_mem_tag => g_mem_tag
)
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_rx,
io_resp => io_resp_rx,
alloc_req => alloc_req,
alloc_resp => alloc_resp,
used_req => used_req,
used_resp => used_resp,
mem_req => mem_req_rx,
mem_resp => mem_resp_rx,
eth_clock => eth_clock,
eth_reset => eth_reset,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid );
i_tx: entity work.eth_transmit
generic map (
g_mem_tag => g_mem_tag xor X"01"
)
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_tx,
io_resp => io_resp_tx,
io_irq => io_irq_tx,
mem_req => mem_req_tx,
mem_resp => mem_resp_tx,
eth_clock => eth_clock,
eth_reset => eth_reset,
eth_tx_data => eth_tx_data,
eth_tx_sof => eth_tx_sof,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready );
i_free: entity work.free_queue
generic map(
g_store_size => true,
g_block_size => 1536
)
port map (
clock => sys_clock,
reset => sys_reset,
alloc_req => alloc_req,
alloc_resp => alloc_resp,
used_req => used_req,
used_resp => used_resp,
io_req => io_req_free,
io_resp => io_resp_free,
io_irq => io_irq_rx );
i_arb: entity work.mem_bus_arbiter_pri_32
generic map (
g_registered => true,
g_ports => 2
)
port map(
clock => sys_clock,
reset => sys_reset,
reqs(0) => mem_req_rx,
reqs(1) => mem_req_tx,
resps(0) => mem_resp_rx,
resps(1) => mem_resp_tx,
req => mem_req,
resp => mem_resp );
end architecture;
| gpl-3.0 | 2064a3cc8e8af7b553b2e72795ba5d23 | 0.431917 | 3.456208 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/memory/vhdl_source/pseudo_dpram.vhd | 1 | 2,012 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pseudo_dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
rd_address : in unsigned(g_depth_bits-1 downto 0);
rd_data : out std_logic_vector(g_width_bits-1 downto 0);
rd_en : in std_logic := '1';
wr_address : in unsigned(g_depth_bits-1 downto 0);
wr_data : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
wr_en : in std_logic := '0' );
attribute keep_hierarchy : string;
attribute keep_hierarchy of pseudo_dpram : entity is "yes";
end entity;
architecture xilinx of pseudo_dpram is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => (others => '0'));
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
attribute ramstyle : string;
attribute ramstyle of ram : variable is g_storage;
begin
process(clock)
begin
if rising_edge(clock) then
if g_read_first then
if rd_en='1' then
rd_data <= ram(to_integer(rd_address));
end if;
end if;
if wr_en='1' then
ram(to_integer(wr_address)) := wr_data;
end if;
if not g_read_first then
if rd_en='1' then
rd_data <= ram(to_integer(rd_address));
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 9334630f3aea26f082b7332c5d72beba | 0.500994 | 3.899225 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20_info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo.vhd | 1 | 8,381 | -- cb20_info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.11.08:07:37
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 89;
FIFO_DEPTH : integer := 2;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 1;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 1;
USE_MEMORY_BLOCKS : integer := 0;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_data : in std_logic_vector(88 downto 0) := (others => '0'); -- in.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
out_data : out std_logic_vector(88 downto 0); -- out.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
out_endofpacket : out std_logic; -- .endofpacket
almost_empty_data : out std_logic;
almost_full_data : out std_logic;
csr_address : in std_logic_vector(1 downto 0) := (others => '0');
csr_read : in std_logic := '0';
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic := '0';
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
in_channel : in std_logic := '0';
in_empty : in std_logic := '0';
in_error : in std_logic := '0';
out_channel : out std_logic;
out_empty : out std_logic;
out_error : out std_logic
);
end entity cb20_info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo;
architecture rtl of cb20_info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo is
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(88 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(88 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
begin
info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => SYMBOLS_PER_BEAT,
BITS_PER_SYMBOL => BITS_PER_SYMBOL,
FIFO_DEPTH => FIFO_DEPTH,
CHANNEL_WIDTH => CHANNEL_WIDTH,
ERROR_WIDTH => ERROR_WIDTH,
USE_PACKETS => USE_PACKETS,
USE_FILL_LEVEL => USE_FILL_LEVEL,
EMPTY_LATENCY => EMPTY_LATENCY,
USE_MEMORY_BLOCKS => USE_MEMORY_BLOCKS,
USE_STORE_FORWARD => USE_STORE_FORWARD,
USE_ALMOST_FULL_IF => USE_ALMOST_FULL_IF,
USE_ALMOST_EMPTY_IF => USE_ALMOST_EMPTY_IF
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_data => in_data, -- in.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
out_data => out_data, -- out.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
out_endofpacket => out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
end architecture rtl; -- of cb20_info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
| apache-2.0 | 8e1001bee6e148046e27ec46d7da792e | 0.430498 | 3.964522 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate2_test.vhd | 1 | 5,170 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ultimate2_test is
port (
CLOCK : in std_logic;
-- slot side
PHI2 : out std_logic;
DOTCLK : out std_logic;
RSTn : out std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : out std_logic_vector(15 downto 0);
SLOT_DATA : out std_logic_vector(7 downto 0);
RWn : out std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : out std_logic;
GAMEn : out std_logic;
ROMHn : out std_logic;
ROMLn : out std_logic;
IO1n : in std_logic;
IO2n : out std_logic;
IRQn : out std_logic;
NMIn : out std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : out std_logic := '0';
CAS_SENSE : out std_logic := 'Z';
CAS_READ : out std_logic := 'Z';
CAS_WRITE : out std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate2_test;
architecture structural of ultimate2_test is
signal counter : unsigned(23 downto 0) := (others => '0');
signal pulses : unsigned(23 downto 1) := (others => '0');
begin
process(CLOCK)
begin
if rising_edge(CLOCK) then
counter <= counter + 1;
pulses <= counter(23 downto 1) and counter(22 downto 0);
end if;
end process;
-- slot side
BUFFER_ENn <= '0';
SLOT_ADDR <= std_logic_vector(counter(23 downto 8));
SLOT_DATA <= std_logic_vector(counter(7 downto 0));
-- top
DMAn <= pulses(1);
--BA <= pulses(2);
ROMLn <= pulses(3);
IO2n <= pulses(4);
EXROMn <= pulses(5);
GAMEn <= pulses(6);
--IO1n <= pulses(7);
DOTCLK <= pulses(8);
RWn <= pulses(9);
IRQn <= pulses(10);
PHI2 <= pulses(11);
NMIn <= pulses(12);
RSTn <= pulses(13);
ROMHn <= pulses(14);
-- Cassette Interface
CAS_SENSE <= pulses(16);
CAS_READ <= pulses(17);
CAS_WRITE <= pulses(18);
CAS_MOTOR <= pulses(19);
IEC_DATA <= '0' when pulses(20) = '1' else 'Z';
IEC_CLOCK <= '0' when pulses(21) = '1' else 'Z';
IEC_ATN <= '0' when pulses(22) = '1' else 'Z';
IEC_SRQ_IN <= '0' when pulses(23) = '1' else 'Z';
-- local bus side
LB_ADDR <= (others => 'Z');
LB_DATA <= (others => 'Z');
SDRAM_CSn <= 'Z';
SDRAM_RASn <= 'Z';
SDRAM_CASn <= 'Z';
SDRAM_WEn <= 'Z';
SDRAM_DQM <= 'Z';
SDRAM_CKE <= 'Z';
SDRAM_CLK <= 'Z';
-- PWM outputs (for audio)
PWM_OUT <= "ZZ";
DISK_ACTn <= not counter(20);
CART_LEDn <= not counter(21);
SDACT_LEDn <= not counter(22);
MOTOR_LEDn <= not counter(23);
-- Debug UART
UART_TXD <= '1';
-- SD Card Interface
SD_SSn <= 'Z';
SD_CLK <= 'Z';
SD_MOSI <= 'Z';
SD_DATA <= "ZZ";
-- RTC Interface
RTC_CS <= '0';
RTC_SCK <= '0';
RTC_MOSI <= '0';
-- Flash Interface
FLASH_CSn <= '1';
FLASH_SCK <= '1';
FLASH_MOSI <= '1';
-- USB Interface (ULPI)
ULPI_RESET <= '0';
ULPI_STP <= '0';
ULPI_DATA <= (others => 'Z');
end structural;
| gpl-3.0 | a006ded76fccc095c92e957718acf01d | 0.498646 | 3.158216 | false | false | false | false |
chiggs/nvc | test/regress/access2.vhd | 5 | 774 | entity access2 is
end entity;
architecture test of access2 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
subtype int_vec10 is int_vec(1 to 10);
type int_vec10_ptr is access int_vec10;
subtype one_to_3 is integer range 1 to 3;
begin
process is
variable p : int_vec_ptr;
variable q : int_vec10_ptr;
variable r : int_vec_ptr;
begin
p := new int_vec(1 to 5);
p(1) := 2;
assert p(1) = 2;
deallocate(p);
assert p = null;
q := new int_vec10;
q(3) := 5;
assert q(3) = 5;
deallocate(q);
r := new int_vec(one_to_3'range);
deallocate(r);
wait;
end process;
end architecture;
| gpl-3.0 | a4556552745287133870a8b920ecacf3 | 0.549096 | 3.350649 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/sampler/vhdl_source/sampler2.vhd | 1 | 10,239 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
entity sampler is
generic (
g_clock_freq : natural := 50_000_000;
g_num_voices : positive := 8 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
irq : out std_logic;
sample_L : out signed(17 downto 0);
sample_R : out signed(17 downto 0);
new_sample : out std_logic );
end entity;
architecture gideon of sampler is
function iif(c : boolean; t : natural; f : natural) return natural is
begin
if c then return t; else return f; end if;
end function iif;
-- At this point there are 3 systems:
-- Ultimate-II running at 50 MHz
-- Ultimate-II+ running at 62.5 MHz
-- Ultimate-64 running at 66.66 MHz
-- The ratios are: 1, 5/4 and 4/3, or 12/12, 15/12 and 16/12. So we should divide by this value
-- Or multiply by: 20/20, 16/20 and 15/20
constant c_prescale_numerator : natural := iif(g_clock_freq = 50_000_000, 1, iif(g_clock_freq = 62_500_000, 4, 3));
constant c_prescale_denominator : natural := iif(g_clock_freq = 50_000_000, 1, iif(g_clock_freq = 62_500_000, 5, 4));
signal voice_i : integer range 0 to g_num_voices-1;
signal voice_state : t_voice_state_array(0 to g_num_voices-1) := (others => c_voice_state_init);
signal voice_sample_reg_h : t_sample_byte_array(0 to g_num_voices-1) := (others => (others => '0'));
signal voice_sample_reg_l : t_sample_byte_array(0 to g_num_voices-1) := (others => (others => '0'));
signal fetch_en : std_logic;
signal fetch_addr : unsigned(25 downto 0);
signal fetch_tag : std_logic_vector(7 downto 0);
signal interrupt : std_logic_vector(g_num_voices-1 downto 0);
signal interrupt_clr : std_logic_vector(g_num_voices-1 downto 0);
signal current_control : t_voice_control;
signal first_chan : std_logic;
signal cur_sam : signed(15 downto 0);
signal cur_vol : unsigned(5 downto 0);
signal cur_pan : unsigned(3 downto 0);
begin
i_regs: entity work.sampler_regs
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
rd_addr => voice_i,
control => current_control,
irq_status => interrupt,
irq_clear => interrupt_clr );
irq <= '1' when unsigned(interrupt) /= 0 else '0';
process(clock)
variable current_state : t_voice_state;
variable next_state : t_voice_state;
variable sample_reg : signed(15 downto 0);
variable v : integer range 0 to 15;
begin
if rising_edge(clock) then
if voice_i = g_num_voices-1 then
voice_i <= 0;
else
voice_i <= voice_i + 1;
end if;
for i in interrupt'range loop
if interrupt_clr(i)='1' then
interrupt(i) <= '0';
end if;
end loop;
fetch_en <= '0';
current_state := voice_state(0);
sample_reg := voice_sample_reg_h(voice_i) & voice_sample_reg_l(voice_i);
next_state := current_state;
case current_state.state is
when idle =>
if current_control.enable then -- and voice_i <= g_num_voices
next_state.state := fetch1;
next_state.position := (others => '0');
next_state.divider := current_control.rate;
next_state.sample_out := (others => '0');
end if;
when playing =>
if current_state.prescale + c_prescale_numerator >= c_prescale_denominator then
next_state.prescale := current_state.prescale + c_prescale_numerator - c_prescale_denominator;
if current_state.divider = 0 then
next_state.divider := current_control.rate;
next_state.sample_out := sample_reg;
next_state.state := fetch1;
if (current_state.position = current_control.repeat_b) then
if current_control.enable and current_control.repeat then
next_state.position := current_control.repeat_a;
end if;
elsif current_state.position = current_control.length then
next_state.state := finished;
if current_control.interrupt then
interrupt(voice_i) <= '1';
end if;
end if;
else
next_state.divider := current_state.divider - 1;
end if;
else
next_state.prescale := current_state.prescale + c_prescale_numerator;
end if;
if not current_control.enable and not current_control.repeat then
next_state.state := idle;
end if;
when finished =>
if not current_control.enable then
next_state.state := idle;
end if;
when fetch1 =>
fetch_en <= '1';
fetch_addr <= current_control.start_addr + current_state.position;
if current_control.mode = mono8 then
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '1'; -- high
next_state.state := playing;
if current_control.interleave then
next_state.position := current_state.position + 2; -- this and the next byte
else
next_state.position := current_state.position + 1; -- this byte only
end if;
else
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '0'; -- low
next_state.position := current_state.position + 1; -- go to the next byte
next_state.state := fetch2;
end if;
when fetch2 =>
fetch_en <= '1';
fetch_addr <= current_control.start_addr + current_state.position;
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '1'; -- high
next_state.state := playing;
if current_control.interleave then
next_state.position := current_state.position + 3; -- this and the two next bytes
else
next_state.position := current_state.position + 1; -- this byte only
end if;
when others =>
null;
end case;
cur_sam <= current_state.sample_out;
cur_vol <= current_control.volume;
cur_pan <= current_control.pan;
if voice_i=0 then
first_chan <= '1';
else
first_chan <= '0';
end if;
-- write port - state --
voice_state <= voice_state(1 to g_num_voices-1) & next_state;
-- write port - sample data --
if mem_resp.dack_tag(7 downto 5) = "110" then
v := to_integer(unsigned(mem_resp.dack_tag(4 downto 1)));
if mem_resp.dack_tag(0)='1' then
voice_sample_reg_h(v) <= signed(mem_resp.data);
else
voice_sample_reg_l(v) <= signed(mem_resp.data);
end if;
end if;
if reset='1' then
voice_i <= 0;
next_state.state := finished; -- shifted into the voice state vector automatically.
interrupt <= (others => '0');
end if;
end if;
end process;
b_mem_fifo: block
signal rack : std_logic;
signal fifo_din : std_logic_vector(33 downto 0);
signal fifo_dout : std_logic_vector(33 downto 0);
begin
fifo_din <= fetch_tag & std_logic_vector(fetch_addr);
i_fifo: entity work.srl_fifo
generic map (
Width => 34,
Depth => 15,
Threshold => 10 )
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => fetch_en,
FlushFifo => '0',
DataIn => fifo_din,
DataOut => fifo_dout,
SpaceInFifo => open,
DataInFifo => mem_req.request );
mem_req.read_writen <= '1';
mem_req.address <= unsigned(fifo_dout(25 downto 0));
mem_req.tag <= fifo_dout(33 downto 26);
mem_req.data <= X"00";
mem_req.size <= "00"; -- 1 byte at a time (can be optimized!)
rack <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag(7 downto 5)="110") else '0';
end block;
i_accu: entity work.sampler_accu
port map (
clock => clock,
reset => reset,
first_chan => first_chan,
sample_in => cur_sam,
volume_in => cur_vol,
pan_in => cur_pan,
sample_L => sample_L,
sample_R => sample_R,
new_sample => new_sample );
end gideon;
| gpl-3.0 | 796edd9e1d76698e1062c70351ecd77c | 0.476707 | 4.1071 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/c2n_record/vhdl_source/c2n_record.vhd | 1 | 8,349 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
irq : out std_logic;
phi2_tick : in std_logic;
c64_stopped : in std_logic;
pull_sense : out std_logic;
c2n_motor_in : in std_logic;
c2n_motor_out : out std_logic := '0'; -- not yet used
c2n_sense : in std_logic;
c2n_read : in std_logic;
c2n_write : in std_logic );
end c2n_record;
architecture gideon of c2n_record is
signal stream_en : std_logic;
signal mode : std_logic_vector(1 downto 0);
signal sel : std_logic;
signal read_s : std_logic;
signal read_c : std_logic;
signal read_d : std_logic;
signal read_event : std_logic;
signal enabled : std_logic;
signal counter : unsigned(23 downto 0);
signal diff : unsigned(23 downto 0);
signal remain : unsigned(2 downto 0);
signal error : std_logic;
signal irq_en : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_din : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
type t_state is (idle, listen, encode, multi1, multi2, multi3);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
signal motor_en : std_logic;
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
attribute register_duplication of read_c : signal is "no";
attribute register_duplication of motor_en : signal is "no";
begin
pull_sense <= sel and enabled;
filt: entity work.spike_filter generic map (10) port map(clock, read_s, read_c);
process(clock)
variable v_diff : unsigned(10 downto 0);
begin
if rising_edge(clock) then
if fifo_full='1' and enabled='1' then
error <= '1';
end if;
-- signal capture
stream_en <= c2n_sense and enabled; -- and c2n_motor;
motor_en <= c2n_motor_in;
read_s <= (c2n_read and not sel) or (c2n_write and sel);
read_d <= read_c;
case mode is
when "00" =>
read_event <= read_c and not read_d; -- rising edge
when "01" =>
read_event <= not read_c and read_d; -- falling edge
when others =>
read_event <= read_c xor read_d; -- both edges
end case;
-- filter for false pulses
-- if counter(23 downto 4) = X"00000" then
-- read_event <= '0';
-- end if;
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(0)='0' and enabled='1' then -- getting disabled
read_event <= '1'; -- why??
end if;
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(5 downto 4);
sel <= req.data(6);
irq_en <= req.data(7);
end if;
elsif req.read='1' then
resp.ack <= '1';
if req.address(11)='0' then
resp.data <= status;
else
resp.data <= fifo_dout;
end if;
end if;
irq <= irq_en and fifo_almostfull;
-- listening process
if stream_en='1' then
if phi2_tick='1' then
counter <= counter + 1;
end if;
else
counter <= (others => '0');
end if;
fifo_write <= '0';
case state is
when idle =>
if stream_en='1' then
state <= listen;
end if;
when listen =>
if read_event='1' then
diff <= counter;
if phi2_tick='1' then
counter <= to_unsigned(1, counter'length);
else
counter <= to_unsigned(0, counter'length);
end if;
state <= encode;
elsif stream_en='0' then
state <= idle;
end if;
when encode =>
fifo_write <= '1';
if (diff > 2040) or (motor_en = '0') then
fifo_din <= X"00";
state <= multi1;
else
v_diff := diff(10 downto 0) + remain;
if v_diff(10 downto 3) = X"00" then
fifo_din <= X"01";
else
fifo_din <= std_logic_vector(v_diff(10 downto 3));
end if;
remain <= v_diff(2 downto 0);
state <= listen;
end if;
when multi1 =>
fifo_din <= std_logic_vector(diff(7 downto 0));
fifo_write <= '1';
state <= multi2;
when multi2 =>
fifo_din <= std_logic_vector(diff(15 downto 8));
fifo_write <= '1';
state <= multi3;
when multi3 =>
fifo_din <= std_logic_vector(diff(23 downto 16));
fifo_write <= '1';
state <= listen;
when others =>
null;
end case;
if reset='1' then
fifo_din <= (others => '0');
enabled <= '0';
counter <= (others => '0');
error <= '0';
mode <= "00";
sel <= '0';
remain <= "000";
irq_en <= '0';
end if;
end if;
end process;
fifo_read <= '1' when req.read='1' and req.address(11)='1' else '0';
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 512,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => fifo_din,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= not fifo_empty;
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when listen,
"11" when others;
end gideon;
| gpl-3.0 | 453caf1d7a1e27c936abdd022400e41b | 0.415858 | 4.22093 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/align_read_to_bram.vhd | 1 | 5,884 | --------------------------------------------------------------------------------
-- Entity: align_read_to_bram
-- Date:2015-03-14
-- Author: Gideon
--
-- Description: This module aligns 32 bit reads from memory to writes to BRAM
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity align_read_to_bram is
port (
clock : in std_logic;
reset : in std_logic;
rdata : in std_logic_vector(31 downto 0);
rdata_valid : in std_logic;
first_word : in std_logic;
last_word : in std_logic;
offset : in unsigned(1 downto 0);
last_bytes : in unsigned(1 downto 0);
wdata : out std_logic_vector(31 downto 0);
wmask : out std_logic_vector(3 downto 0);
wnext : out std_logic );
end align_read_to_bram;
-- This unit implements data rotation. This is done to support streaming from memory.
-- Length that this unit gets is: actual length + offset + 3. This indicates the last byte that
-- is being read and thus valid for writing.
-- int (size / 4) = number of words to be accessed.
-- (size and 3) = info about byte enables of last beat 0 = 0001, 1 = 0011, 2 = 0111, 3 = 1111.
-- for writing, these byte enables shall still be rotated to the right.
-- offset = info about byte enables of first beat, and rotation value
-- Note that for an offset of 0, it doesn't really matter if we write a few extra bytes in the BRAM,
-- because we're aligned. However, for an offset other than 0, it determines whether
-- we should write the last beat or not.
architecture arch of align_read_to_bram is
type t_state is (idle, stream, last);
signal state : t_state;
signal remain : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
wmask <= X"0";
wnext <= '0';
-- we always get 3210, regardless of the offset.
-- If the offset is 0, we pass all data
-- If the offset is 1, we save 3 bytes (321x), and go to the next state
-- If the offset is 2, we save 2 bytes (32xx), and go to the next state
-- If the offset is 3, we save 1 byte (3xxx), and go to the next state
-- In case the offset was sent to the DRAM, we get:
-- If the offset is 1, we save 3 bytes (x321), and go to the next state
-- If the offset is 2, we save 2 bytes (xx32), and go to the next state
-- If the offset is 3, we save 1 byte (xxx3), and go to the next state
case state is
when idle =>
wdata <= rdata;
if rdata_valid = '1' then -- we assume first word
remain <= rdata;
case offset is
when "00" => -- aligned
wmask <= X"F";
wnext <= '1';
when others =>
if last_word = '1' then
state <= last;
else
state <= stream;
end if;
end case;
end if;
when stream =>
case offset is
when "01" =>
-- We use 3 bytes from the previous word, and one from the current word
wdata <= rdata(31 downto 24) & remain(23 downto 0);
when "10" =>
-- We use 2 bytes from the previous word, and two from the current word
wdata <= rdata(31 downto 16) & remain(15 downto 0);
when "11" =>
-- We use 1 bytes from the previous word, and three from the current word
wdata <= rdata(31 downto 8) & remain( 7 downto 0);
when others =>
wdata <= rdata;
end case;
if rdata_valid = '1' then
remain <= rdata;
wmask <= X"F";
wnext <= '1';
if last_word = '1' then
if offset > last_bytes then
state <= idle;
else
state <= last;
end if;
end if;
end if;
when last =>
case offset is
when "01" =>
-- We use 3 bytes from the previous word, and one from the current word
wdata <= rdata(31 downto 24) & remain(23 downto 0);
when "10" =>
-- We use 2 bytes from the previous word, and two from the current word
wdata <= rdata(31 downto 16) & remain(15 downto 0);
when "11" =>
-- We use 1 bytes from the previous word, and three from the current word
wdata <= rdata(31 downto 8) & remain( 7 downto 0);
when others =>
wdata <= rdata;
end case;
wmask <= X"F";
state <= idle;
-- case last_bytes is
-- when "01" =>
-- wmask <= "0001";
-- when "10" =>
-- wmask <= "0011";
-- when "11" =>
-- wmask <= "0111";
-- when others =>
-- wmask <= "0000";
-- end case;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 1d352877856d2eb78bd51fe4bba29cce | 0.456152 | 4.666138 | false | false | false | false |
mkreider/cocotb2 | examples/endian_swapper/hdl/endian_swapper.vhdl | 4 | 7,129 | -------------------------------------------------------------------------------
-- Copyright (c) 2014 Potential Ventures Ltd
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of Potential Ventures Ltd nor
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------
--
--
-- Endian swapping module.
--
-- Simple example with Avalon streaming interfaces and a CSR bus
--
-- Avalon-ST has readyLatency of 0
-- Avalon-MM has fixed readLatency of 1
--
-- Exposes 2 32-bit registers via the Avalon-MM interface
--
-- Address 0: bit 0 [R/W] byteswap enable
-- bits 31-1: [N/A] reserved
-- Adress 1: bits 31-0: [RO] packet count
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity endian_swapper_vhdl is
generic (
DATA_BYTES : integer := 8);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
stream_in_data : in std_ulogic_vector(DATA_BYTES*8-1 downto 0);
stream_in_empty : in std_ulogic_vector(2 downto 0);
stream_in_valid : in std_ulogic;
stream_in_startofpacket : in std_ulogic;
stream_in_endofpacket : in std_ulogic;
stream_in_ready : out std_ulogic;
stream_out_data : out std_ulogic_vector(DATA_BYTES*8-1 downto 0);
stream_out_empty : out std_ulogic_vector(2 downto 0);
stream_out_valid : out std_ulogic;
stream_out_startofpacket: out std_ulogic;
stream_out_endofpacket : out std_ulogic;
stream_out_ready : in std_ulogic;
csr_address : in std_ulogic_vector(1 downto 0);
csr_readdata : out std_ulogic_vector(31 downto 0);
csr_readdatavalid : out std_ulogic;
csr_read : in std_ulogic;
csr_write : in std_ulogic;
csr_waitrequest : out std_ulogic;
csr_writedata : in std_ulogic_vector(31 downto 0)
);
end;
architecture impl of endian_swapper_vhdl is
function byteswap(data : in std_ulogic_vector(63 downto 0)) return std_ulogic_vector is begin
return data(7 downto 0) &
data(15 downto 8) &
data(23 downto 16) &
data(31 downto 24) &
data(39 downto 32) &
data(47 downto 40) &
data(55 downto 48) &
data(63 downto 56);
end;
signal csr_waitrequest_int : std_ulogic;
signal stream_out_endofpacket_int: std_ulogic;
signal flush_pipe : std_ulogic;
signal in_packet : std_ulogic;
signal byteswapping : std_ulogic;
signal packet_count : unsigned(31 downto 0);
begin
process (clk, reset_n) begin
if (reset_n = '0') then
flush_pipe <= '0';
in_packet <= '0';
packet_count <= to_unsigned(0, 32);
elsif rising_edge(clk) then
if (flush_pipe = '1' and stream_out_ready = '1') then
flush_pipe <= stream_in_endofpacket and stream_in_valid and stream_out_ready;
elsif (flush_pipe = '0') then
flush_pipe <= stream_in_endofpacket and stream_in_valid and stream_out_ready;
end if;
if (stream_out_ready = '1' and stream_in_valid = '1') then
stream_out_empty <= stream_in_empty;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket_int <= stream_in_endofpacket;
if (byteswapping = '0') then
stream_out_data <= stream_in_data;
else
stream_out_data <= byteswap(stream_in_data);
end if;
if (stream_in_startofpacket = '1' and stream_in_valid = '1') then
packet_count <= packet_count + 1;
in_packet <= '1';
end if;
if (stream_in_endofpacket = '1' and stream_in_valid = '1') then
in_packet <= '0';
end if;
end if;
end if;
end process;
stream_in_ready <= stream_out_ready;
stream_out_endofpacket <= stream_out_endofpacket_int;
stream_out_valid <= '1' when (stream_in_valid = '1' and stream_out_endofpacket_int = '0') or flush_pipe = '1' else '0';
-- Hold off CSR accesses during packet transfers to prevent changing of endian configuration mid-packet
csr_waitrequest_int <= '1' when reset_n = '0' or in_packet = '1' or (stream_in_startofpacket = '1' and stream_in_valid = '1') or flush_pipe = '1' else '0';
csr_waitrequest <= csr_waitrequest_int;
process (clk, reset_n) begin
if (reset_n = '0') then
byteswapping <= '0';
csr_readdatavalid <= '0';
elsif rising_edge(clk) then
if (csr_read = '1') then
csr_readdatavalid <= not csr_waitrequest_int;
case csr_address is
when "00" => csr_readdata <= (31 downto 1 => '0') & byteswapping;
when "01" => csr_readdata <= std_ulogic_vector(packet_count);
when others => csr_readdata <= (31 downto 0 => 'X');
end case;
elsif (csr_write = '1' and csr_waitrequest_int = '0') then
case csr_address is
when "00" => byteswapping <= csr_writedata(0);
when others => null;
end case;
end if;
end if;
end process;
-- Unfortunately this workaround is required for Aldec: Need to schedule an event
fake_process :process
begin
wait for 50 ns;
end process;
end architecture;
| bsd-3-clause | 9870ac4540cca7e6b9b113c5cafc2f21 | 0.584374 | 3.960556 | false | false | false | false |
asicguy/crash | fpga/src/bpsk_mod/bpsk_mod.vhd | 2 | 8,635 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: tx_mod.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Transmit data modulator. Biphase modulates signal with
-- input binary data with option to trigger.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bpsk_mod is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Binary Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used (TODO: maybe use for near empty input FIFO?)
-- AXIS Stream Master Interface (Modulated complex samples)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
trigger_stb : in std_logic);
end entity;
architecture RTL of bpsk_mod is
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
type slv_256x32 is array(0 to 255) of std_logic_vector(31 downto 0);
signal ctrl_reg : slv_256x32 := (others=>(others=>'0'));
signal status_reg : slv_256x32 := (others=>(others=>'0'));
signal axis_master_tdest_hold : std_logic_vector(2 downto 0);
signal axis_master_tdest_safe : std_logic_vector(2 downto 0);
signal mod_data : std_logic_vector(63 downto 0);
signal bit_cnt : integer range 0 to 63;
signal enable : std_logic;
signal external_enable : std_logic;
signal external_trigger_enable : std_logic;
signal packet_size_cnt : integer;
signal packet_size : integer;
signal trigger_stb_reg : std_logic;
signal transmitting : std_logic;
begin
axis_slave_irq <= '0';
axis_master_irq <= '0';
axis_master_tdest <= axis_master_tdest_safe;
proc_modulate : process(clk,enable,external_enable)
begin
if (enable = '0' AND external_enable = '0') then
axis_slave_tready <= '0';
axis_master_tvalid <= '0';
axis_master_tlast <= '0';
axis_master_tdata <= (others=>'0');
packet_size_cnt <= packet_size; -- This is intentional
transmitting <= '0';
else
if rising_edge(clk) then
transmitting <= '1';
-- TODO: This code takes 65 clock cycles to transfer 64 complex samples. Should look into
-- redoing this so the single clock cycle delay is avoided.
-- Grab the AXI-Stream data when enabled
if (axis_slave_tvalid = '1' AND bit_cnt = 0) then
axis_slave_tready <= '1';
axis_master_tvalid <= '1';
mod_data <= axis_slave_tdata;
else
axis_slave_tready <= '0';
end if;
-- Count the number of data bits sent
axis_master_tlast <= '0';
if (axis_master_tready = '1') then
if (bit_cnt = 63) then
if (packet_size_cnt = 1) then
axis_master_tlast <= '1';
packet_size_cnt <= packet_size;
else
packet_size_cnt <= packet_size_cnt - 1;
end if;
axis_master_tvalid <= '0';
bit_cnt <= 0;
else
bit_cnt <= bit_cnt + 1;
end if;
end if;
-- Modulate I & Q
-- I
if (mod_data(bit_cnt) = '1') then
axis_master_tdata(31 downto 0) <= x"7FFFFFFF";
else
axis_master_tdata(31 downto 0) <= x"80000000";
end if;
-- Q
axis_master_tdata(63 downto 32) <= (others=>'0');
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Control and status registers.
-------------------------------------------------------------------------------
proc_ctrl_status_reg : process(clk,rst_n)
begin
if (rst_n = '0') then
external_enable <= '0';
ctrl_reg <= (others=>(others=>'0'));
axis_master_tdest_safe <= (others=>'0');
trigger_stb_reg <= '0';
else
if rising_edge(clk) then
-- Update control registers only when accelerator 0 is accessed
if (ctrl_stb = '1') then
ctrl_reg(to_integer(unsigned(ctrl_addr(7 downto 0)))) <= ctrl_data;
end if;
-- Output status register
if (status_stb = '1') then
status_data <= status_reg(to_integer(unsigned(status_addr(7 downto 0))));
end if;
-- The destination can only update when no data is being transmitted, i.e. FFT disabled
if (enable = '0' AND external_enable = '0') then
axis_master_tdest_safe <= axis_master_tdest_hold;
end if;
-- Register sideband signals
trigger_stb_reg <= trigger_stb;
-- Enable on trigger and disable only when external_trigger_enable is deasserted
if (trigger_stb_reg = '1' AND external_trigger_enable = '1') then
external_enable <= '1';
end if;
if (external_trigger_enable = '0') then
external_enable <= '0';
end if;
end if;
end if;
end process;
-- Control Registers
-- Bank 0 (Enable and destination)
enable <= ctrl_reg(0)(0);
external_trigger_enable <= ctrl_reg(0)(1);
axis_master_tdest_hold <= ctrl_reg(0)(31 downto 29);
-- Bank 1 (Packet size)
packet_size <= to_integer(unsigned(ctrl_reg(1)(31 downto 0)));
-- Status Registers
-- Bank 0 (Enable and destination Readback)
status_reg(0)(0) <= enable;
status_reg(0)(1) <= external_trigger_enable;
status_reg(0)(31 downto 29) <= axis_master_tdest_hold;
-- Bank 1 (Packet size Readback)
status_reg(1) <= std_logic_vector(to_unsigned(packet_size,32));
-- Bank 2
status_reg(2)(0) <= transmitting;
end architecture; | gpl-3.0 | 2e22c69a11b55b2e840b9ffde381a2f1 | 0.480023 | 4.385475 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/u2p_io.vhd | 1 | 4,825 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.io_bus_pkg.all;
entity u2p_io is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
mdc : out std_logic;
mdio_i : in std_logic;
mdio_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_i : in std_logic;
i2c_scl_o : out std_logic;
i2c_sda_o : out std_logic;
iec_i : in std_logic_vector(3 downto 0) := X"F";
iec_o : out std_logic_vector(3 downto 0);
board_rev : in std_logic_vector(4 downto 0);
eth_irq_i : in std_logic;
hub_reset_n : out std_logic;
speaker_en : out std_logic;
ulpi_reset : out std_logic;
speaker_vol : out std_logic_vector(3 downto 0);
buffer_en : out std_logic );
end entity;
architecture rtl of u2p_io is
signal mdc_out : std_logic;
signal mdio_out : std_logic;
signal i2c_scl_out : std_logic;
signal i2c_sda_out : std_logic;
signal speaker_en_i : std_logic;
signal speaker_vol_i : std_logic_vector(3 downto 0);
signal hub_reset_i : std_logic;
signal ulpi_reset_i : std_logic;
begin
process(clock, reset)
variable local : unsigned(3 downto 0);
begin
if reset = '1' then -- switched to asynchronous reset
i2c_scl_o <= '1';
i2c_sda_o <= '1';
mdc_out <= '1';
mdio_o <= '1';
speaker_en_i <= '0';
hub_reset_i <= '0';
ulpi_reset_i <= '0';
buffer_en <= '0';
iec_o <= (others => '1');
elsif rising_edge(clock) then
local := io_req.address(3 downto 0);
io_resp <= c_io_resp_init;
if io_req.read = '1' then
io_resp.ack <= '1';
case local is
when X"0" | X"1" | X"8" =>
io_resp.data(0) <= i2c_scl_i;
when X"2" | X"3" | X"9" =>
io_resp.data(0) <= i2c_sda_i;
when X"4" | X"5" | X"A" =>
io_resp.data(0) <= mdc_out;
when X"6" | X"7" | X"B" =>
io_resp.data(0) <= mdio_i;
when X"C" =>
io_resp.data(0) <= speaker_en_i;
io_resp.data(7 downto 3) <= board_rev;
when X"D" =>
io_resp.data(0) <= hub_reset_i;
when X"E" =>
io_resp.data(0) <= eth_irq_i;
io_resp.data(7 downto 4) <= iec_i;
when X"F" =>
io_resp.data(0) <= ulpi_reset_i;
when others =>
null;
end case;
end if;
if io_req.write = '1' then
io_resp.ack <= '1';
case local is
when X"0" =>
i2c_scl_o <= '0';
when X"1" =>
i2c_scl_o <= '1';
when X"2" =>
i2c_sda_o <= '0';
when X"3" =>
i2c_sda_o <= '1';
when X"4" =>
mdc_out <= '0';
when X"5" =>
mdc_out <= '1';
when X"6" =>
mdio_o <= '0';
when X"7" =>
mdio_o <= '1';
when X"8" =>
i2c_scl_o <= io_req.data(0);
when X"9" =>
i2c_sda_o <= io_req.data(0);
when X"A" =>
mdc_out <= io_req.data(0);
when X"B" =>
mdio_o <= io_req.data(0);
when X"C" =>
speaker_en_i <= io_req.data(0);
speaker_vol_i <= io_req.data(4 downto 1);
when X"D" =>
hub_reset_i <= io_req.data(0);
when X"E" =>
iec_o <= io_req.data(7 downto 4);
when X"F" =>
ulpi_reset_i <= io_req.data(0);
if io_req.data(7) = '1' then
buffer_en <= '1';
elsif io_req.data(6) = '1' then
buffer_en <= '0';
end if;
when others =>
null;
end case;
end if;
end if;
end process;
mdc <= mdc_out;
speaker_en <= speaker_en_i;
speaker_vol <= speaker_vol_i;
hub_reset_n <= not (hub_reset_i or reset);
ulpi_reset <= ulpi_reset_i or reset;
end architecture;
| gpl-3.0 | ce91a0535ad2af7b3e5b2c50ca591d2a | 0.386321 | 3.441512 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/freezer.vhd | 1 | 3,036 | library ieee;
use ieee.std_logic_1164.all;
entity freezer is
generic (
g_ext_activate : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
RST_in : in std_logic;
button_freeze : in std_logic;
cpu_cycle_done : in std_logic;
cpu_write : in std_logic;
activate : in std_logic := '0';
freezer_state : out std_logic_vector(1 downto 0); -- debug
unfreeze : in std_logic; -- could be software driven, or automatic, depending on cartridge
freeze_trig : out std_logic;
freeze_act : out std_logic );
end freezer;
architecture gideon of freezer is
signal reset_in : std_logic;
signal wr_cnt : integer range 0 to 3;
signal do_freeze : std_logic;
signal do_freeze_d : std_logic;
signal activate_c : std_logic;
signal activate_d : std_logic;
type t_state is (idle, triggered, enter_freeze, button);
signal state : t_state;
begin
freeze_trig <= '1' when (state = triggered) else '0';
process(clock)
begin
if rising_edge(clock) then
activate_c <= activate;
activate_d <= activate_c;
do_freeze <= button_freeze;
do_freeze_d <= do_freeze;
reset_in <= reset or RST_in;
if cpu_cycle_done='1' then
if cpu_write='1' then
if wr_cnt/=3 then
wr_cnt <= wr_cnt + 1;
end if;
else
wr_cnt <= 0;
end if;
end if;
case state is
when idle =>
freeze_act <= '0';
if do_freeze_d='0' and do_freeze='1' then -- push
state <= triggered;
end if;
when triggered =>
if (g_ext_activate and activate_d='1') or (not g_ext_activate and wr_cnt=3) then
state <= enter_freeze;
freeze_act <= '1';
end if;
when enter_freeze =>
if unfreeze='1' then
freeze_act <= '0';
state <= button;
end if;
when button =>
if do_freeze='0' then -- wait until button is not pressed anymore
state <= idle;
end if;
when others =>
state <= idle;
end case;
if reset_in='1' then
state <= idle;
wr_cnt <= 0;
activate_d <= '0';
end if;
end if;
end process;
with state select freezer_state <=
"00" when idle,
"01" when triggered,
"10" when enter_freeze,
"11" when button,
"00" when others;
end gideon;
| gpl-3.0 | 3cf28828593ebe1dcba206b5cd37135e | 0.443347 | 4.246154 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/tb_via6522.vhd | 1 | 24,682 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_via6522 is
end tb_via6522;
architecture tb of tb_via6522 is
signal clock : std_logic := '0';
signal rising : std_logic := '0';
signal falling : std_logic := '0';
signal reset : std_logic;
signal addr : std_logic_vector(3 downto 0) := X"0";
signal wen : std_logic := '0';
signal ren : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := X"00";
signal data_out : std_logic_vector(7 downto 0) := X"00";
signal irq : std_logic;
signal cycle : integer := 0;
-- pio --
signal port_a_o : std_logic_vector(7 downto 0);
signal port_a_t : std_logic_vector(7 downto 0);
-- signal port_a_i : std_logic_vector(7 downto 0);
signal port_b_o : std_logic_vector(7 downto 0);
signal port_b_t : std_logic_vector(7 downto 0);
-- signal port_b_i : std_logic_vector(7 downto 0);
-- handshake pins
-- signal ca1_i : std_logic;
signal ca2_o : std_logic;
-- signal ca2_i : std_logic;
signal ca2_t : std_logic;
signal cb1_o : std_logic;
-- signal cb1_i : std_logic;
signal cb1_t : std_logic;
signal cb2_o : std_logic;
-- signal cb2_i : std_logic;
signal cb2_t : std_logic;
signal ca1, ca2 : std_logic;
signal cb1, cb2 : std_logic;
signal port_a : std_logic_vector(7 downto 0);
signal port_b : std_logic_vector(7 downto 0);
signal test_id : integer := 0;
begin
port_a <= (others => 'H');
port_b <= (others => 'H');
ca1 <= 'H';
ca2 <= ca2_o when ca2_t='1' else 'H';
cb1 <= cb1_o when cb1_t='1' else 'H';
cb2 <= cb2_o when cb2_t='1' else 'H';
process(port_a_o, port_a_t, port_b_o, port_b_t)
begin
for i in 0 to 7 loop
if port_a_t(i)='1' then
port_a(i) <= port_a_o(i);
else
port_a(i) <= 'H';
end if;
if port_b_t(i)='1' then
port_b(i) <= port_b_o(i);
else
port_b(i) <= 'H';
end if;
end loop;
end process;
via: entity work.via6522
port map (
clock => clock,
rising => rising,
falling => falling,
reset => reset,
addr => addr,
wen => wen,
ren => ren,
data_in => data_in,
data_out => data_out,
-- pio --
port_a_o => port_a_o,
port_a_t => port_a_t,
port_a_i => port_a,
port_b_o => port_b_o,
port_b_t => port_b_t,
port_b_i => port_b,
-- handshake pins
ca1_i => ca1,
ca2_o => ca2_o,
ca2_i => ca2,
ca2_t => ca2_t,
cb1_o => cb1_o,
cb1_i => cb1,
cb1_t => cb1_t,
cb2_o => cb2_o,
cb2_i => cb2,
cb2_t => cb2_t,
irq => irq );
clock <= not clock after 50 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
wait until clock='1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
rising <= '1';
wait until clock='1';
rising <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
falling <= '1';
wait until clock='1';
falling <= '0';
cycle <= cycle + 1;
end process;
test: process
procedure do_write(a: std_logic_vector(3 downto 0); d: std_logic_vector(7 downto 0)) is
begin
addr <= a;
data_in <= d;
wen <= '1';
wait until falling='1';
wait until clock = '1';
wen <= '0';
end do_write;
procedure do_read(a: std_logic_vector(3 downto 0); d: out std_logic_vector(7 downto 0)) is
begin
addr <= a;
ren <= '1';
wait until falling='1';
wait until clock='1';
wait for 1 ns;
ren <= '0';
d := data_out;
end do_read;
variable start : time;
variable read_data : std_logic_vector(7 downto 0);
constant test_byte : std_logic_vector(7 downto 0) := X"47";
constant test_byte2 : std_logic_vector(7 downto 0) := X"E2";
begin
ca1 <= 'Z';
ca2 <= 'Z';
cb1 <= 'Z';
cb2 <= 'Z';
port_b <= (others => 'Z');
wait until reset='0';
for i in 0 to 15 loop
do_read(conv_std_logic_vector(i, 4), read_data);
end loop;
test_id <= 1;
do_write(X"0", X"55"); -- set data = 55
do_write(X"2", X"33"); -- set direction = 33
do_read (X"0", read_data);
assert read_data = "HH01HH01" report "Data port B seems wrong" severity error;
test_id <= 2;
do_write(X"1", X"99"); -- set data = 99
do_write(X"3", X"AA"); -- set direction = AA
do_read (X"0", read_data);
assert read_data = "1H0H1H0H" report "Data port A seems wrong" severity error;
-- TEST SHIFT REGISTER --
test_id <= 11;
do_write(X"8", X"05"); -- timer 2 latch = 5
do_write(X"E", X"84"); -- enable IRQ on shift register
do_write(X"B", X"04"); -- Shift Control = 1 (shift in on timer 2)
do_write(X"9", X"00"); -- Do load of T2CH to make sure that timer2 low gets loaded too.
do_write(X"A", X"00"); -- dummy write to SR, to start transfer
start := now;
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= test_byte(i);
if i = 7 then
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
if irq = '0' then wait until irq = '1'; end if;
assert (now - start) = 111.5 us report "Timing error serial mode 1." severity error;
test_id <= 12;
do_write(X"B", X"08"); -- Shift Control = 2 (shift in on system clock)
do_read (X"A", read_data); -- check byte from previous transmit
assert read_data = test_byte report "Data byte came in was not correct (mode 1)." severity error;
for i in 7 downto 0 loop
wait until cb1='0';
cb2 <= not test_byte(i);
if i = 7 then
start := now;
end if;
end loop;
wait until cb1='1';
cb2 <= 'Z';
if irq = '0' then wait until irq = '1'; end if;
assert integer((now - start)/7 us) = 2 report "Timing error serial mode 2." severity error;
test_id <= 13;
do_write(X"B", X"0C"); -- Shift Control = 3 (shift in under control of cb1)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = not test_byte report "Data byte came in was not correct (mode 2)." severity error;
for i in test_byte2'range loop
cb1 <= '0';
wait for 2 us;
cb2 <= test_byte2(i);
wait for 2 us;
cb1 <= '1';
wait for 2 us;
end loop;
cb2 <= 'Z';
cb1 <= 'Z';
test_id <= 14;
do_write(X"B", X"10"); -- Shift Control = 4 (shift out continuously)
do_read (X"A", read_data); -- check byte from previous transmitm, trigger new
assert read_data = test_byte2 report "Data byte came in was not correct (mode 3)." severity error;
wait for 450 us;
assert irq = '0' report "An IRQ was generated, but not expected.";
do_write(X"B", X"00"); -- stop endless loop
test_id <= 15;
do_write(X"8", X"03"); -- timer 2 latch = 3 (10 us per bit)
do_write(X"B", X"14"); -- Shift Control = 5 (shift out on Timer 2)
do_write(X"A", X"55");
-- keep peeking T2CL
wait until rising='1';
addr <= X"8";
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
if irq = '0' then wait until irq = '1'; end if;
assert read_data = X"55" report "Data byte sent out was not correct (mode 5)." severity error;
test_id <= 16;
do_write(X"B", X"18"); -- Shift Control = 6 (shift out on system clock)
do_write(X"A", X"81");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
if irq = '0' then wait until irq = '1'; end if;
assert read_data = X"81" report "Data byte sent out was not correct (mode 6)." severity error;
test_id <= 17;
do_write(X"B", X"1c"); -- Shift Control = 7 (shift out on own clock)
do_write(X"A", X"B3");
for i in 7 downto 0 loop
cb1 <= '0';
wait for 2 us;
read_data(i) := cb2;
cb1 <= '1';
wait for 2 us;
end loop;
cb1 <= 'Z';
assert read_data = X"B3" report "Data byte sent out was not correct (mode 7)." severity error;
test_id <= 18;
-- again test mode 5 (shift on timer 2)
do_write(X"8", X"03"); -- timer 2 latch = 3 (10 us per bit)
do_write(X"9", X"00"); -- timer 2 latch = 3 (10 us per bit)
do_write(X"B", X"14"); -- Shift Control = 5 (shift out on Timer 2)
do_write(X"A", X"55");
for i in 7 downto 0 loop
wait until cb1='1';
read_data(i) := cb2;
end loop;
assert read_data = X"55" report "Data byte 2 sent out was not correct (mode 5)." severity error;
do_write(X"B", X"00"); -- disable shift register
do_write(X"E", X"7F"); -- clear all interupt enable flags
report "Serial tests done. Now starting timer 1";
-- TEST TIMER 1 --
test_id <= 21;
do_write(X"E", X"C0"); -- enable interrupt on Timer 1
-- timer 1 is now in one shot mode, output disabled
do_write(X"4", X"30"); -- Set timer to 0x230
do_write(X"5", X"02"); -- ... and start one shot
start := now;
if irq = '0' then wait until irq = '1'; end if;
assert integer((now - start)/ 1 us) = 561 report "Interrupt of timer 1 received. Duration Error." severity error;
do_read (X"4", read_data);
wait until clock='1';
assert irq = '0' report "Expected interrupt to be cleared by reading address 4." severity error;
test_id <= 22;
do_write(X"B", X"40"); -- timer in cont. mode
do_write(X"4", X"20"); -- timer = 0x120
do_write(X"5", X"01"); -- trigger, and go
if irq = '0' then wait until irq = '1'; end if;
start := now;
do_read(X"4", read_data);
if irq = '0' then wait until irq = '1'; end if;
report "Time between interrupts: " & time'image(now - start) severity note;
assert integer((now - start) / 1 us) = 290 report "Timer 1 continuous mode, interrupt distance wrong. " & time'image(now-start) severity error;
test_id <= 23;
do_write(X"B", X"80"); -- timer 1 one shot, PB7 enabled
do_write(X"4", X"44"); -- set timer to 0x0044
assert irq = '1' report "Expected IRQ still to be set" severity error;
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
wait until clock='1';
assert irq = '0' report "Expected IRQ to be cleared" severity error;
if irq = '0' then wait until irq = '1'; end if;
assert (now - start) = 69.5 us report "Timer 1 one shot output mode, interrupt distance wrong." severity error;
test_id <= 24;
do_write(X"B", X"C0"); -- timer 1 continuous, PB7 enabled
do_write(X"4", X"24"); -- set timer to 0x0024
do_write(X"5", X"00"); -- set timer, clear flag, go!
start := now;
if irq = '0' then wait until irq = '1'; end if;
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"7", X"00"); -- re-write latch value, reset flag
if irq = '0' then wait until irq = '1'; end if;
assert port_b(7)='0' report "Expected bit 7 of PB to be '0'" severity error;
do_read(X"4", read_data); --reset flag
if irq = '0' then wait until irq = '1'; end if;
assert port_b(7)='1' report "Expected bit 7 of PB to be '1'" severity error;
do_write(X"B", X"00"); -- timer 1 one shot, output disabled
do_write(X"E", X"7E"); -- clear interrupt enable flags
-- TEST TIMER 2 --
test_id <= 31;
do_write(X"E", X"A0"); -- Set interrupt on timer 2
do_write(X"8", X"33"); -- Set lower latch to 33.
wait for 10 us; -- observe timer to count
wait until falling='1';
do_write(X"9", X"02"); -- Set timer to 0x233 and wait for IRQ
start := now;
if irq = '0' then wait until irq = '1'; end if;
-- report integer'image(integer((now - start) / 1 us)) severity note;
assert (now - start) = 564.5 us report "Timer 2 one shot mode, interrupt time wrong." severity error;
do_read(X"8", read_data);
test_id <= 32;
do_write(X"B", X"20"); -- set to pulse count mode
do_write(X"2", X"00"); -- set port B to input
do_write(X"8", X"0A"); -- set to 10 pulses
do_write(X"9", X"00"); -- high byte and trigger
wait for 5 us;
for i in 0 to 10 loop
port_b(6) <= '0';
wait for 5 us;
port_b(6) <= '1';
wait for 1 us;
assert not((i > 9) and (irq = '0')) report "Expected IRQ to be 1 after 10th pulse" severity error;
assert not((i < 10) and (irq = '1')) report "Expected IRQ to be 0 before 10th pulse" severity error;
wait for 15 us;
end loop;
-- TEST CA1 --
test_id <= 41;
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"82"); -- interrupt on CA1
wait until clock='1';
-- no transitions have taken place yet on CA1, hence IRQ should be low
assert irq='0' report "Expected CA1 interrupt to be low before any transition." severity error;
ca1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after negative transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by reading port a." severity error;
do_write(X"C", X"01"); -- CA1 control = '1', expecting rising edge
wait for 2 us;
ca1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA1 IRQ to be set after positive transition." severity error;
do_write(X"1", X"47");
wait for 2 us;
assert irq='0' report "Expected CA1 IRQ to be cleared by writing port A." severity error;
-- TEST CB1 --
test_id <= 42;
cb1 <= '1';
do_write(X"0", X"11"); -- clear flag
do_write(X"C", X"00");
do_write(X"E", X"7F");
do_write(X"E", X"90"); -- interrupt on CB1
wait until clock='1';
-- no transitions have taken place yet on CB1, hence IRQ should be low
assert irq='0' report "Expected CB1 interrupt to be low before any transition." severity error;
cb1 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after negative transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by reading port B." severity error;
do_write(X"C", X"10"); -- CB1 control = '1', expecting rising edge
wait for 2 us;
cb1 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB1 IRQ to be set after positive transition." severity error;
do_write(X"0", X"47");
wait for 2 us;
assert irq='0' report "Expected CB1 IRQ to be cleared by writing port B." severity error;
-- TEST CA2 --
-- mode 0: input, negative transition, Port A out clears flag
test_id <= 43;
ca2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"01"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"81"); -- enable CA2 interrupt
wait for 2 us;
assert irq='0' report "Expected CA2 interrupt to be low before any transition." severity error;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition." severity error;
do_write(X"1", X"44"); -- write to Port a
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by writing to port A." severity error;
-- mode 2: input, positive transition, Port A in/out clears flag
do_write(X"C", X"04"); -- mode 2
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='0' report "Expected CA2 IRQ to be cleared by reading port A." severity error;
-- mode 1 / 3, read/write to port A does NOT clear the interrupt flag
do_write(X"C", X"02"); -- mode 1
wait for 2 us;
ca2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"01"); -- clear flag manually
do_write(X"C", X"06"); -- mode 3
wait for 2 us;
ca2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"1", read_data);
wait for 2 us;
assert irq='1' report "Expected CA2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"01"); -- clear flag manually
-- mode 4
ca2 <= 'Z';
do_write(X"C", X"08"); -- mode 4
do_write(X"1", X"31"); -- write to Port A
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 4)." severity error;
ca1 <= '0';
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to have gone high upon active transition on CA1 (mode 4)." severity error;
ca1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"0A"); -- mode 5
wait until falling='1';
do_write(X"1", X"32"); -- write to port A
wait until falling='1' and clock='1';
wait for 1 ns;
assert ca2 = '0' report "Expected CA2 to have gone low upon writing to Port A (mode 5)." severity error;
wait until falling='1' and clock='1';
wait for 1 ns;
assert ca2 = '1' report "Expected CA2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"0C"); -- mode 6
wait for 2 us;
assert ca2 = '0' report "Expected CA2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"0E"); -- mode 7
wait for 2 us;
assert ca2 = '1' report "Expected CA2 to be high in mode 7." severity error;
-- TEST CB2 --
test_id <= 44;
-- mode 0: input, negative transition, Port B out clears flag
cb2 <= '1';
do_write(X"C", X"00"); -- mode 0
do_write(X"D", X"08"); -- clear flag
do_write(X"E", X"7F"); -- reset all interrupt enables
do_write(X"E", X"88"); -- enable CB2 interrupt
wait for 2 us;
assert irq='0' report "Expected CB2 interrupt to be low before any transition." severity error;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition." severity error;
do_write(X"0", X"44"); -- write to Port B
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by writing to port B." severity error;
-- mode 2: input, positive transition, Port B in/out clears flag
do_write(X"C", X"40"); -- mode 2
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='0' report "Expected CB2 IRQ to be cleared by reading port B." severity error;
-- mode 1 / 3, read/write to port B does NOT clear the interrupt flag
do_write(X"C", X"20"); -- mode 1
wait for 2 us;
cb2 <= '0';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after negative transition (mode 1)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after negative transition (mode 1)." severity error;
do_write(X"D", X"08"); -- clear flag manually
do_write(X"C", X"60"); -- mode 3
wait for 2 us;
cb2 <= '1';
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be set after positive transition (mode 3)." severity error;
do_read(X"0", read_data);
wait for 2 us;
assert irq='1' report "Expected CB2 IRQ to be STILL set after positive transition (mode 3)." severity error;
do_write(X"D", X"08"); -- clear flag manually
-- mode 4
cb2 <= 'Z';
do_write(X"C", X"80"); -- mode 4
do_write(X"0", X"31"); -- write to Port B
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 4)." severity error;
cb1 <= '0';
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to have gone high upon active transition on CB1 (mode 4)." severity error;
cb1 <= '1';
wait for 2 us;
-- mode 5
do_write(X"C", X"A0"); -- mode 5
wait until falling='1';
do_write(X"0", X"32"); -- write to port B
wait until falling='1' and clock='1';
wait for 1 ns;
assert cb2 = '0' report "Expected CB2 to have gone low upon writing to Port B (mode 5)." severity error;
wait until falling='1' and clock='1';
wait for 1 ns;
assert cb2 = '1' report "Expected CB2 to have gone high after one cycle (mode 5)." severity error;
-- mode 6
do_write(X"C", X"C0"); -- mode 6
wait for 2 us;
assert cb2 = '0' report "Expected CB2 to be low in mode 6" severity error;
-- mode 7
do_write(X"C", X"E0"); -- mode 7
wait for 2 us;
assert cb2 = '1' report "Expected CB2 to be high in mode 7." severity error;
report "All tests done";
wait;
end process;
end tb;
| gpl-3.0 | e13ce9c203ca36e662915d2be0a3ed05 | 0.499352 | 3.653345 | false | true | false | false |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/mem32_to_avalon_bridge.vhd | 3 | 5,788 | -------------------------------------------------------------------------------
-- Title : mem32_to_avalon_bridge
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module bridges the memory bus to avalon, in order to
-- attach it to the DDR2 memory controller (for the time being).
-- Note that the Ultimate2 logic actually used the burst size
-- re-ordering, which is something that the avalon memory
-- controller does not support. For this reason, this block
-- performs data word rotation.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem32_to_avalon_bridge is
port (
clock : in std_logic;
reset : in std_logic;
memreq_tag : in std_logic_vector(7 downto 0);
memreq_request : in std_logic;
memreq_read_writen : in std_logic;
memreq_address : in std_logic_vector(25 downto 0);
memreq_byte_en : in std_logic_vector(3 downto 0);
memreq_data : in std_logic_vector(31 downto 0);
memresp_data : out std_logic_vector(31 downto 0);
memresp_rack : out std_logic;
memresp_rack_tag : out std_logic_vector(7 downto 0);
memresp_dack_tag : out std_logic_vector(7 downto 0);
avm_read : out std_logic;
avm_write : out std_logic;
avm_address : out std_logic_vector(25 downto 0);
avm_writedata : out std_logic_vector(31 downto 0);
avm_byte_enable : out std_logic_vector(3 downto 0);
avm_ready : in std_logic;
avm_readdata : in std_logic_vector(31 downto 0);
avm_readdatavalid : in std_logic );
end entity;
architecture rtl of mem32_to_avalon_bridge is
signal wr : unsigned(2 downto 0);
signal rd : unsigned(2 downto 0);
signal full : std_logic;
type t_tag_store is array(natural range <>) of std_logic_vector(7 downto 0);
signal tag_store : t_tag_store(0 to 7);
type t_offset_store is array(natural range <>) of std_logic_vector(1 downto 0);
signal offset_store : t_offset_store(0 to 7);
begin
memresp_rack_tag <= X"00" when avm_ready = '0' else memreq_tag;
memresp_rack <= avm_ready and memreq_request and not full;
avm_read <= memreq_request and not full and memreq_read_writen;
avm_write <= memreq_request and not full and not memreq_read_writen;
avm_address <= memreq_address(25 downto 2) & "00";
-- Avalon is little endian.
-- For example, if the memory reads the bytes A0 EA 67 FE, logically, FE will be
-- on address 3, while A0 is on address 0. The word from memory will be "FE67EAA0": Order: 3210
-- So, when address is 0, the byte is already in the correct location.
-- When address is 1, "EA" needs to be returned in the lower byte, so word is rotated: 0321
-- WHen address is 2, "67" needs to be returned in the lower byte, so word is rotated: 1032
-- ...
-- For write: the data is supplied in the lower byte (0). The same rotation applies:
with memreq_address(1 downto 0) select avm_writedata <=
memreq_data(23 downto 0) & memreq_data(31 downto 24) when "01", -- --X-
memreq_data(15 downto 0) & memreq_data(31 downto 16) when "10", -- -X--
memreq_data( 7 downto 0) & memreq_data(31 downto 8) when "11", -- X---
memreq_data when others; -- ---X
with memreq_address(1 downto 0) select avm_byte_enable <=
memreq_byte_en(2 downto 0) & memreq_byte_en(3 downto 3) when "01",
memreq_byte_en(1 downto 0) & memreq_byte_en(3 downto 2) when "10",
memreq_byte_en(0 downto 0) & memreq_byte_en(3 downto 1) when "11",
memreq_byte_en when others;
full <= '1' when (wr - rd) = "110" else '0';
process(clock)
variable v_rdoff : std_logic_vector(1 downto 0);
begin
if rising_edge(clock) then
if memreq_request='1' then
if memreq_read_writen = '1' then
if avm_ready = '1' and full = '0' then
tag_store(to_integer(wr)) <= memreq_tag;
offset_store(to_integer(wr)) <= memreq_address(1 downto 0);
wr <= wr + 1;
end if;
end if;
end if;
memresp_dack_tag <= X"00";
if avm_readdatavalid = '1' then
memresp_dack_tag <= tag_store(to_integer(rd));
v_rdoff := offset_store(to_integer(rd));
case v_rdoff is
when "01" =>
memresp_data <= avm_readdata(7 downto 0) & avm_readdata(31 downto 8);
when "10" =>
memresp_data <= avm_readdata(15 downto 0) & avm_readdata(31 downto 16);
when "11" =>
memresp_data <= avm_readdata(23 downto 0) & avm_readdata(31 downto 24);
when others =>
memresp_data <= avm_readdata;
end case;
rd <= rd + 1;
end if;
if reset='1' then
rd <= (others => '0');
wr <= (others => '0');
tag_store <= (others => (others => '0')); -- avoid using M9K for just 64 bits
offset_store <= (others => (others => '0')); -- or even more so for just 16 bits
end if;
end if;
end process;
end architecture;
| gpl-3.0 | e0c5feea688da147e771efbb19678ebd | 0.530408 | 3.833113 | false | false | false | false |
bgunebakan/toyrobot | Distance_calculation.vhd | 1 | 2,107 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:02:55 12/18/2014
-- Design Name:
-- Module Name: Distance_calculation - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Distance_calculation is
Port ( clk : in STD_LOGIC;
Calculation_Reset : in STD_LOGIC;
distance : out STD_LOGIC_VECTOR (8 downto 0);
pulse : in STD_LOGIC);
end Distance_calculation;
architecture Behavioral of Distance_calculation is
component Counter is
generic(n: POSITIVE :=10);
Port (clk: in STD_LOGIC;
enable: in STD_LOGIC;
reset: in STD_LOGIC;
Counter_output: out STD_LOGIC_VECTOR(n-1 downto 0));
end component;
signal Pulse_width : STD_LOGIC_VECTOR(21 downto 0);
begin
CounterPulse: Counter generic map(22) port map(clk,pulse,not Calculation_Reset,Pulse_width);
Distance_calculation: process(pulse)
variable Result: integer;
variable multiplier : STD_LOGIC_VECTOR(23 downto 0);
begin
if(pulse ='0') then
multiplier := Pulse_width*"11";
Result := to_integer(unsigned(multiplier(23 downto 13) ));
if(Result > 458) then
distance <= "111111111";
else
distance <= STD_LOGIC_VECTOR(to_unsigned(Result,9));
end if;
end if;
end process Distance_calculation;
end Behavioral;
| gpl-2.0 | 634a9052460f3ad631963bf15c9a8055 | 0.590888 | 3.998102 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502/vhdl_source/proc_core.vhd | 1 | 7,201 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
irq_n : in std_logic := '1';
nmi_n : in std_logic := '1';
so_n : in std_logic := '1';
sync_out : out std_logic;
pc_out : out std_logic_vector(15 downto 0);
inst_out : out std_logic_vector(7 downto 0);
addr_out : out std_logic_vector(16 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
read_write_n : out std_logic );
end proc_core;
architecture structural of proc_core is
signal index_carry : std_logic;
signal pc_carry : std_logic;
signal branch_taken : boolean;
signal i_reg : std_logic_vector(7 downto 0);
signal d_reg : std_logic_vector(7 downto 0);
signal a_reg : std_logic_vector(7 downto 0);
signal x_reg : std_logic_vector(7 downto 0);
signal y_reg : std_logic_vector(7 downto 0);
signal s_reg : std_logic_vector(7 downto 0);
signal p_reg : std_logic_vector(7 downto 0);
signal latch_dreg : std_logic;
signal reg_update : std_logic;
signal copy_d2p : std_logic;
signal sync : std_logic;
signal rwn : std_logic;
signal vect_bit : std_logic;
signal a_mux : t_amux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal dout_mux : t_dout_mux;
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal vect_addr : std_logic_vector(3 downto 0);
signal interrupt : std_logic;
signal vectoring : std_logic;
signal set_i_flag : std_logic;
signal new_flags : std_logic_vector(7 downto 0);
signal n_out : std_logic;
signal v_out : std_logic;
signal c_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal a16 : std_logic;
begin
inst_out <= i_reg; -- for debug only
new_flags(7) <= n_out;
new_flags(6) <= v_out;
new_flags(5) <= '1';
new_flags(4) <= p_reg(4);
new_flags(3) <= d_out;
new_flags(2) <= i_out;
new_flags(1) <= z_out;
new_flags(0) <= c_out;
ctrl: entity work.proc_control
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
interrupt => interrupt,
vectoring => vectoring,
set_i_flag => set_i_flag,
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
sync => sync,
latch_dreg => latch_dreg,
reg_update => reg_update,
copy_d2p => copy_d2p,
vect_bit => vect_bit,
a16 => a16,
rwn => rwn,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper );
oper: entity work.data_oper
generic map (
support_bcd => support_bcd )
port map (
inst => i_reg,
n_in => p_reg(7),
v_in => p_reg(6),
z_in => p_reg(1),
c_in => p_reg(0),
d_in => p_reg(3),
i_in => p_reg(2),
data_in => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
regs: entity work.proc_registers
generic map (
vector_page => vector_page )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- package pins
data_in => data_in,
data_out => data_out,
so_n => so_n,
-- data from "data_oper"
alu_data => alu_out,
mem_data => mem_out,
new_flags => new_flags,
-- from implied handler
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
set_data => impl_out,
-- from interrupt controller
vect_addr => vect_addr,
-- from processor state machine and decoder
sync => sync,
latch_dreg => latch_dreg,
set_i_flag => set_i_flag,
vectoring => vectoring,
reg_update => reg_update,
copy_d2p => copy_d2p,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper,
-- outputs to processor state machine
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
-- register outputs
addr_out => addr_out(15 downto 0),
d_reg => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
p_reg => p_reg,
pc_out => pc_out );
intr: entity work.proc_interrupt
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
i_flag => p_reg(2),
vect_bit => vect_bit,
interrupt => interrupt,
vect_addr => vect_addr );
read_write_n <= rwn;
addr_out(16) <= a16;
sync_out <= sync;
end structural;
| gpl-3.0 | 4402f61f202fb85c464fee15e5b1973f | 0.434384 | 3.500729 | false | false | false | false |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/bjt_transistor_simple_arc.vhdl | 15 | 1,525 | -- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE simple_arc OF BJT_transistor_simple IS
terminal unnamed_net8 : electrical;
terminal unnamed_net7 : electrical;
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- Architecture statement part
SP1 : ENTITY SP_DIODE(SPICE_Diode_Model)
GENERIC MAP (
VT => VT,
AF => AF,
KF => KF,
PT => PT,
EG => EG,
M => ME,
PB => PE,
TT => TF,
CJ0 => CJE,
ISS => ISS)
PORT MAP ( ANODE => unnamed_net8,
KATHODE => unnamed_net5);
CS2 : ENTITY SPICE_cs(current_controlled)
GENERIC MAP (
N => BF,
VT => VT,
ISS => ISS)
PORT MAP ( urt => unnamed_net4,
lrt => unnamed_net5,
ult => unnamed_net1,
llt => unnamed_net8);
CAP2 : ENTITY CAPACITOR
PORT MAP ( LT => unnamed_net5,
RT => unnamed_net1);
CAP1 : ENTITY CAPACITOR
PORT MAP ( LT => unnamed_net1,
RT => unnamed_net4);
GND1 : ENTITY GROUND_NODE
PORT MAP ( T1 => unnamed_net7);
CAP3 : ENTITY CAPACITOR
GENERIC MAP (
c => CCS)
PORT MAP ( LT => unnamed_net7,
RT => unnamed_net4);
RES_emitter : ENTITY RESISTOR
GENERIC MAP (
r => RE)
PORT MAP ( RT => unnamed_net5,
LT => emitter);
RES_collector : ENTITY RESISTOR
GENERIC MAP (
r => RC)
PORT MAP ( RT => collector,
LT => unnamed_net4);
RES_base : ENTITY RESISTOR
GENERIC MAP (
r => RB)
PORT MAP ( RT => unnamed_net1,
LT => base);
END ARCHITECTURE simple_arc;
| gpl-2.0 | 0f60722913e5552cacf29b51fce10fca | 0.615738 | 2.813653 | false | false | false | false |
mkreider/cocotb2 | examples/mixed_language/hdl/toplevel.vhdl | 4 | 2,976 | -- Example using mixed-language simulation
--
-- Here we have a VHDL toplevel that instantiates both SV and VHDL
-- sub entities
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity endian_swapper_mixed is
generic (
DATA_BYTES : integer := 8);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
stream_in_data : in std_ulogic_vector(DATA_BYTES*8-1 downto 0);
stream_in_empty : in std_ulogic_vector(2 downto 0);
stream_in_valid : in std_ulogic;
stream_in_startofpacket : in std_ulogic;
stream_in_endofpacket : in std_ulogic;
stream_in_ready : out std_ulogic;
stream_out_data : out std_ulogic_vector(DATA_BYTES*8-1 downto 0);
stream_out_empty : out std_ulogic_vector(2 downto 0);
stream_out_valid : out std_ulogic;
stream_out_startofpacket: out std_ulogic;
stream_out_endofpacket : out std_ulogic;
stream_out_ready : in std_ulogic;
csr_address : in std_ulogic_vector(1 downto 0);
csr_readdata : out std_ulogic_vector(31 downto 0);
csr_readdatavalid : out std_ulogic;
csr_read : in std_ulogic;
csr_write : in std_ulogic;
csr_waitrequest : out std_ulogic;
csr_writedata : in std_ulogic_vector(31 downto 0)
);
end;
architecture impl of endian_swapper_mixed is begin
i_swapper_sv : entity work.endian_swapper_sv
generic map (
DATA_BYTES => DATA_BYTES
) port map (
clk => clk,
reset_n => reset_n,
stream_in_empty => stream_in_empty,
stream_in_data => stream_in_data,
stream_in_endofpacket => stream_in_endofpacket,
stream_in_startofpacket => stream_in_startofpacket,
stream_in_valid => stream_in_valid,
stream_in_ready => stream_in_ready,
stream_out_empty => stream_out_empty,
stream_out_data => stream_out_data,
stream_out_endofpacket => stream_out_endofpacket,
stream_out_startofpacket=> stream_out_startofpacket,
stream_out_valid => stream_out_valid,
stream_out_ready => stream_out_ready,
csr_address => csr_address,
csr_readdata => csr_readdata,
csr_readdatavalid => csr_readdatavalid,
csr_read => csr_read,
csr_write => csr_write,
csr_waitrequest => csr_waitrequest,
csr_writedata => csr_writedata
);
end architecture;
| bsd-3-clause | 6475b150d587257b1332c085339ebb11 | 0.511089 | 4.03252 | false | false | false | false |
ringof/radiofist_audio | fir_filter_wrapper.vhd | 1 | 911 | -- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See LICENCE.txt for details
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fir_filter_wrapper is
port (
din : in STD_LOGIC_VECTOR(23 downto 0);
dout : out STD_LOGIC_VECTOR(9 downto 0);
reset : in STD_LOGIC;
clk : in STD_LOGIC
);
end fir_filter_wrapper;
architecture RTL of fir_filter_wrapper is
component fir_filter
generic (
MSBI : integer := 7; --Most significant bit of FIR input
MSBO : integer := 9 --Most significant bit of FIR output
);
port (
DIN : in STD_LOGIC_VECTOR(MSBI downto 0);
DOUT : out STD_LOGIC_VECTOR(MBSO downto 0);
CLK : in STD_LOGIC;
SCLR : in STD_LOGIC;
RFD : out STD_LOGIC;
RDY : out STD_LOGIC
);
end component;
begin
fir_filter1 : fir_filter
port map(
DIN => din,
DOUT => dout,
CLK => clk,
SCLR => reset,
RFD => open,
RDY => open
);
end RTL;
| mit | adbb3428766c0a29e4b2ca762188bd8d | 0.650933 | 2.882911 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/acia/vhdl_sim/tb_acia6551.vhd | 1 | 6,964 | --------------------------------------------------------------------------------
-- Entity: acia6551
-- Date:2018-11-24
-- Author: gideon
--
-- Description: This is the testbench for the 6551.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
use work.acia6551_pkg.all;
use work.tl_string_util_pkg.all;
entity tb_acia6551 is
end entity;
architecture testbench of tb_acia6551 is
signal clock : std_logic := '0';
signal reset : std_logic;
signal slot_req : t_slot_req;
signal slot_resp : t_slot_resp;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_irq : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_acia: entity work.acia6551
port map (
clock => clock,
reset => reset,
slot_req => slot_req,
slot_resp => slot_resp,
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq
);
i_io_master: entity work.io_bus_bfm
generic map (
g_name => "io"
)
port map (
clock => clock,
req => io_req,
resp => io_resp
);
i_slot_master: entity work.slot_bus_master_bfm
generic map (
g_name => "slot"
)
port map (
clock => clock,
req => slot_req,
resp => slot_resp
);
p_test: process
variable io : p_io_bus_bfm_object;
variable slot : p_slot_bus_master_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable status : std_logic_vector(7 downto 0);
procedure check_io_irq(level : std_logic; flags : std_logic_vector(7 downto 0) := X"00") is
variable reg : std_logic_vector(7 downto 0);
begin
wait until clock = '1';
wait until clock = '1';
wait until clock = '1';
assert level = io_irq report "Level of IO_irq is wrong." severity error;
if level = '1' then
io_read(io, c_reg_irq_source, reg);
assert flags = reg report "IRQ flags unexpected. " & hstr(reg) & "/=" & hstr(flags)
severity error;
io_write(io, c_reg_irq_source, flags);
end if;
end procedure;
procedure read_status_and_data(exp: boolean := false; expdata : std_logic_vector(7 downto 0) := X"00") is
begin
slot_io_read(slot, c_addr_status_register, status);
slot_io_read(slot, c_addr_data_register, data);
report hstr(status) & ":" & hstr(data);
if exp and status(3) = '0' then
report "Rx Data expected, but not available."
severity error;
end if;
if not exp and status(3) = '1' then
report "NO data expected, but there is Rx data available."
severity error;
end if;
if exp and status(3) = '1' and data /= expdata then
report "Wrong Rx data read."
severity error;
end if;
end procedure;
procedure read_tx(exp: boolean := false; expdata : std_logic_vector(7 downto 0) := X"00") is
variable head, tail : std_logic_vector(7 downto 0);
begin
io_read(io, c_reg_tx_head, head);
io_read(io, c_reg_tx_tail, tail);
io_read(io, unsigned(tail) + X"800", data);
report hstr(head) & ":" & hstr(tail) & ":" & hstr(data);
if head /= tail then
io_write(io, c_reg_tx_tail, std_logic_vector(unsigned(tail) + 1));
assert exp report "There is data, but you didn't expected any." severity error;
assert data = expdata report "Data is not as expected?" severity error;
else
assert not exp report "There is no data, but you did expect some!" severity error;
end if;
end procedure;
begin
bind_io_bus_bfm("io", io);
bind_slot_bus_master_bfm("slot", slot);
wait until reset = '0';
check_io_irq('0');
-- Enable and pass four bytes to the RX of the Host
io_write(io, c_reg_enable, X"19" ); -- enable IRQ on DTR change and control write
io_write(io, X"900", X"47");
io_write(io, X"901", X"69");
io_write(io, X"902", X"64");
io_write(io, X"903", X"65");
io_write(io, c_reg_rx_head, X"04" );
-- On the host side, read status. It should show no data, since DTR is not set
read_status_and_data;
-- Set DTR
slot_io_write(slot, c_addr_command_register, X"03");
check_io_irq('1', X"12"); -- Checks and clears IRQ
check_io_irq('0');
-- set the virtual baud rate
slot_io_write(slot, c_addr_control_register, X"1A");
check_io_irq('1', X"0A"); -- Checks and clears IRQ
check_io_irq('0');
io_read(io, c_reg_control, status);
assert status = X"1A" report "Control read register is different from what we wrote earlier." severity error;
-- Now that DTR is set, reading the host status should show that there is data available
read_status_and_data(true, X"47");
read_status_and_data(true, X"69");
read_status_and_data(true, X"64");
read_status_and_data(true, X"65");
read_status_and_data;
io_write(io, X"904", X"6f");
io_write(io, X"905", X"6e");
io_write(io, c_reg_rx_head, X"06" );
read_status_and_data(true, X"6F");
read_status_and_data(true, X"6E");
read_status_and_data;
io_write(io, c_reg_enable, X"05"); -- enable Tx Interrupt
assert io_irq = '0' report "IO IRQ should be zero now." severity error;
-- Now the other way around (from Host to Appl)
slot_io_write(slot, c_addr_data_register, X"01");
slot_io_write(slot, c_addr_data_register, X"02");
slot_io_write(slot, c_addr_data_register, X"03");
slot_io_write(slot, c_addr_data_register, X"04");
assert io_irq = '1' report "IO IRQ should be active now." severity error;
read_tx(true, X"01");
read_tx(true, X"02");
read_tx(true, X"03");
read_tx(true, X"04");
read_tx;
for i in 0 to 260 loop
slot_io_write(slot, c_addr_data_register, std_logic_vector(to_unsigned((i + 6) mod 256, 8)));
end loop;
read_tx(true, X"06");
read_tx(true, X"07");
read_tx(true, X"08");
read_tx(true, X"09");
read_tx(true, X"0A");
wait;
end process;
end architecture;
| gpl-3.0 | 236a6a123c7e38ed2c8c4081a96a0066 | 0.525991 | 3.511851 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_source/io_bus_pkg.vhd | 2 | 1,315 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package io_bus_pkg is
type t_io_req is record
read : std_logic;
write : std_logic;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_io_resp is record
data : std_logic_vector(7 downto 0);
ack : std_logic;
end record;
constant c_io_req_init : t_io_req := (
read => '0',
write => '0',
address => X"00000",
data => X"00" );
constant c_io_resp_init : t_io_resp := (
data => X"00",
ack => '0' );
type t_io_req_array is array(natural range <>) of t_io_req;
type t_io_resp_array is array(natural range <>) of t_io_resp;
function or_reduce(ar: t_io_resp_array) return t_io_resp;
end package;
package body io_bus_pkg is
function or_reduce(ar: t_io_resp_array) return t_io_resp is
variable ret : t_io_resp;
begin
ret := c_io_resp_init;
for i in ar'range loop
ret.ack := ret.ack or ar(i).ack;
ret.data := ret.data or ar(i).data;
end loop;
return ret;
end function or_reduce;
end package body;
| gpl-3.0 | a6aa59bdf1a9b4e369d06321f037e57b | 0.51711 | 3.363171 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_source/io_bus_bridge2.vhd | 1 | 2,381 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_bus_bridge2 is
generic (
g_addr_width : natural := 8 );
port (
clock_a : in std_logic;
reset_a : in std_logic;
req_a : in t_io_req;
resp_a : out t_io_resp;
clock_b : in std_logic;
reset_b : in std_logic;
req_b : out t_io_req;
resp_b : in t_io_resp );
end entity;
architecture rtl of io_bus_bridge2 is
constant c_io_bus_req_vector_width : natural := g_addr_width + 10;
signal request_a : std_logic;
signal req_vector_a : std_logic_vector(c_io_bus_req_vector_width-1 downto 0);
signal request_b : std_logic;
signal req_vector_b : std_logic_vector(c_io_bus_req_vector_width-1 downto 0);
signal address_b : unsigned(19 downto 0) := (others => '0');
signal resp_vector_a : std_logic_vector(7 downto 0);
signal response_a : std_logic;
begin
req_vector_a <= std_logic_vector(req_a.address(g_addr_width-1 downto 0)) & req_a.data & req_a.read & req_a.write;
request_a <= req_a.write or req_a.read;
i_heen: entity work.synchronizer_gzw
generic map(
g_width => req_vector_a'length,
g_fast => true
)
port map(
tx_clock => clock_a,
tx_push => request_a,
tx_data => req_vector_a,
tx_done => open,
rx_clock => clock_b,
rx_new_data => request_b,
rx_data => req_vector_b );
address_b(g_addr_width-1 downto 0) <= unsigned(req_vector_b(9 + g_addr_width downto 10));
req_b.address <= address_b;
req_b.data <= req_vector_b(9 downto 2);
req_b.read <= req_vector_b(1) and request_b;
req_b.write <= req_vector_b(0) and request_b;
i_terug: entity work.synchronizer_gzw
generic map(
g_width => 8,
g_fast => true
)
port map(
tx_clock => clock_b,
tx_push => resp_b.ack,
tx_data => resp_b.data,
tx_done => open,
rx_clock => clock_a,
rx_new_data => response_a,
rx_data => resp_vector_a );
resp_a.ack <= response_a;
resp_a.data <= resp_vector_a when response_a = '1' else X"00";
end rtl;
| gpl-3.0 | e0f1461685a9a5a855ce5a6f80f60252 | 0.532969 | 3.010114 | false | false | false | false |
asicguy/crash | fpga/src/common/synchronizer.vhd | 2 | 3,005 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: synchronizer.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Sychronizer to cross clock domains using two registers. If
-- the signal is a strobe, the edge can be specified.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic := '0');
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic; -- Asynchronous input
sync : out std_logic); -- Synchronized output
end entity;
architecture RTL of synchronizer is
component edge_detect
generic (
EDGE : string := "R"); -- "R"ising, "F"alling, "B"oth, or "N"one.
port (
clk : in std_logic;
reset : in std_logic;
input_detect : in std_logic; -- Input data
edge_detect_stb : out std_logic); -- Edge detected strobe
end component;
signal async_meta1 : std_logic;
signal async_meta2 : std_logic;
begin
proc_synchronize : process(clk,reset)
begin
if (reset = '1') then
async_meta1 <= RESET_OUTPUT;
async_meta2 <= RESET_OUTPUT;
else
if rising_edge(clk) then
async_meta1 <= async;
async_meta2 <= async_meta1;
end if;
end if;
end process;
gen_if_use_edge_detect : if (STROBE_EDGE(STROBE_EDGE'left) /= 'N') generate
inst_edge_detect : edge_detect
generic map (
EDGE => STROBE_EDGE)
port map (
clk => clk,
reset => reset,
input_detect => async_meta2,
edge_detect_stb => sync);
end generate;
gen_if_no_edge_detect : if (STROBE_EDGE(STROBE_EDGE'left) = 'N') generate
sync <= async_meta2;
end generate;
end RTL; | gpl-3.0 | 8525693a2006b70e5f7f1432cbf1bd35 | 0.529118 | 4.127747 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/packages/vhdl_bfm/wave_pkg.vhd | 5 | 5,471 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Wave package
-------------------------------------------------------------------------------
-- File : wave_pkg.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package provides ways to write (and maybe in future read)
-- .wav files.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_file_io_pkg.all;
package wave_pkg is
type t_wave_channel is record
number_of_samples : integer;
memory : h_mem_object;
end record;
type t_wave_channel_array is array(natural range <>) of t_wave_channel;
procedure open_channel(chan : out t_wave_channel);
procedure push_sample(chan : inout t_wave_channel; sample : integer);
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array);
end package;
package body wave_pkg is
procedure open_channel(chan : out t_wave_channel) is
variable ch : t_wave_channel;
begin
register_mem_model("path", "channel", ch.memory);
ch.number_of_samples := 0;
chan := ch;
end procedure;
procedure push_sample(chan : inout t_wave_channel; sample : integer) is
variable s : integer;
begin
s := sample;
if s > 32767 then s := 32767; end if;
if s < -32768 then s := -32768; end if;
write_memory_int(chan.memory, chan.number_of_samples, s);
chan.number_of_samples := chan.number_of_samples + 1;
end procedure;
procedure write_vector_le(x : std_logic_vector; file f : t_binary_file; r : inout t_binary_file_rec) is
variable bytes : integer := (x'length + 7) / 8;
variable xa : std_logic_vector(7+bytes*8 downto 0);
begin
xa := (others => '0');
xa(x'length-1 downto 0) := x;
for i in 0 to bytes-1 loop
write_byte(f, xa(i*8+7 downto i*8), r);
end loop;
end procedure;
procedure write_int_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(31 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 32));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_short_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(15 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 16));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array) is
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
variable stat : file_open_status;
variable file_size : integer;
variable data_size : integer;
variable max_length : integer;
begin
-- open file
file_open(stat, myfile, name, write_mode);
assert (stat = open_ok)
report "Could not open file " & name & " for writing."
severity failure;
init_record(myrec);
max_length := 0;
for i in channels'range loop
if channels(i).number_of_samples > max_length then
max_length := channels(i).number_of_samples;
end if;
end loop;
data_size := (max_length * channels'length * 2);
file_size := 12 + 16 + 8 + data_size;
-- header
write_vector_le(X"46464952", myfile, myrec); -- "RIFF"
write_int_le (file_size-8, myfile, myrec);
write_vector_le(X"45564157", myfile, myrec); -- "WAVE"
-- chunk header
write_vector_le(X"20746D66", myfile, myrec); -- "fmt "
write_int_le (16, myfile, myrec);
write_short_le (1, myfile, myrec); -- compression code = uncompressed
write_short_le (channels'length, myfile, myrec);
write_int_le (rate, myfile, myrec); -- sample rate
write_int_le (rate * channels'length * 2, myfile, myrec); -- Bps
write_short_le (channels'length * 2, myfile, myrec); -- alignment
write_short_le (16, myfile, myrec); -- bits per sample
write_vector_le(X"61746164", myfile, myrec); -- "data"
write_int_le (data_size, myfile, myrec);
-- now write out all data!
for i in 0 to max_length-1 loop
for j in channels'range loop
write_short_le(read_memory_int(channels(j).memory, i), myfile, myrec);
end loop;
end loop;
purge(myfile, myrec);
file_close(myfile);
end procedure;
end;
| gpl-3.0 | d78a5bd5999dee63d6af2df4928cb8f0 | 0.499726 | 3.978909 | false | false | false | false |
chiggs/nvc | test/regress/const5.vhd | 5 | 804 | entity const5 is
end entity;
architecture test of const5 is
subtype byte_t is bit_vector(7 downto 0);
type byte_array_t is array (natural range <>) of byte_t;
procedure popcount_assert
( value : in byte_t;
pop : in integer )
is
variable cnt : natural := 0;
begin
for i in value'range loop
if value(i) = '1' then
cnt := cnt + 1;
end if;
end loop;
report integer'image(cnt);
assert cnt = pop;
end procedure;
begin
stim_p: process is
constant COME_ADDRS : byte_array_t := ( X"08", X"10", X"20" );
begin
for i in 0 to 2 loop
popcount_assert(value => COME_ADDRS(i), pop => 1);
end loop;
wait;
end process;
end architecture;
| gpl-3.0 | 169f80938a6a28eb38ec606c8b2b1578 | 0.538557 | 3.739535 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/watchdog/cb20/synthesis/cb20.vhd | 1 | 487,644 | -- cb20.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20 is
port (
clk_clk : in std_logic := '0'; -- clk.clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
eim_slave_to_avalon_master_0_conduit_end_ioslv_data : inout std_logic_vector(15 downto 0) := (others => '0'); -- eim_slave_to_avalon_master_0_conduit_end.ioslv_data
eim_slave_to_avalon_master_0_conduit_end_isl_cs_n : in std_logic := '0'; -- .isl_cs_n
eim_slave_to_avalon_master_0_conduit_end_isl_oe_n : in std_logic := '0'; -- .isl_oe_n
eim_slave_to_avalon_master_0_conduit_end_isl_we_n : in std_logic := '0'; -- .isl_we_n
eim_slave_to_avalon_master_0_conduit_end_osl_data_ack : out std_logic; -- .osl_data_ack
eim_slave_to_avalon_master_0_conduit_end_islv_address : in std_logic_vector(15 downto 0) := (others => '0'); -- .islv_address
dacad5668_0_conduit_end_osl_sclk : out std_logic; -- dacad5668_0_conduit_end.osl_sclk
dacad5668_0_conduit_end_oslv_Ss : out std_logic; -- .oslv_Ss
dacad5668_0_conduit_end_osl_mosi : out std_logic; -- .osl_mosi
dacad5668_0_conduit_end_osl_LDAC_n : out std_logic; -- .osl_LDAC_n
dacad5668_0_conduit_end_osl_CLR_n : out std_logic; -- .osl_CLR_n
fqd_interface_0_conduit_end_B : in std_logic_vector(7 downto 0) := (others => '0'); -- fqd_interface_0_conduit_end.B
fqd_interface_0_conduit_end_A : in std_logic_vector(7 downto 0) := (others => '0'); -- .A
gpio_block_0_conduit_end_export : inout std_logic_vector(8 downto 0) := (others => '0'); -- gpio_block_0_conduit_end.export
pwm_interface_0_conduit_end_export : out std_logic_vector(3 downto 0); -- pwm_interface_0_conduit_end.export
gpio_block_1_conduit_end_export : inout std_logic_vector(7 downto 0) := (others => '0'); -- gpio_block_1_conduit_end.export
watchdog_block_0_wd_signals_granted : out std_logic; -- watchdog_block_0_wd_signals.granted
watchdog_block_0_wd_signals_watchdog_pwm : out std_logic; -- .watchdog_pwm
ppwa_block_0_conduit_end_export : in std_logic_vector(1 downto 0) := (others => '0') -- ppwa_block_0_conduit_end.export
);
end entity cb20;
architecture rtl of cb20 is
component cb20_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component cb20_altpll_0;
component info_device is
generic (
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
description : std_logic_vector(223 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
dev_size : integer := 0
);
port (
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
);
end component info_device;
component eim_slave_to_avalon_master is
generic (
TRANSFER_WIDTH : integer := 16
);
port (
ioslv_data : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
isl_cs_n : in std_logic := 'X'; -- export
isl_oe_n : in std_logic := 'X'; -- export
isl_we_n : in std_logic := 'X'; -- export
osl_data_ack : out std_logic; -- export
islv_address : in std_logic_vector(15 downto 0) := (others => 'X'); -- export
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
islv_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
islv_waitrequest : in std_logic := 'X'; -- waitrequest
oslv_address : out std_logic_vector(15 downto 0); -- address
oslv_read : out std_logic; -- read
oslv_write : out std_logic; -- write
oslv_writedata : out std_logic_vector(15 downto 0) -- writedata
);
end component eim_slave_to_avalon_master;
component avalon_dacad5668_interface is
generic (
BASE_CLK : integer := 33000000;
SCLK_FREQUENCY : integer := 10000000;
INTERNAL_REFERENCE : std_logic := '0';
UNIQUE_ID : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
osl_sclk : out std_logic; -- export
oslv_Ss : out std_logic; -- export
osl_mosi : out std_logic; -- export
osl_LDAC_n : out std_logic; -- export
osl_CLR_n : out std_logic; -- export
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
);
end component avalon_dacad5668_interface;
component avalon_fqd_counter_interface is
generic (
number_of_fqds : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
islv_enc_B : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
islv_enc_A : in std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component avalon_fqd_counter_interface;
component avalon_pwm_interface is
generic (
number_of_pwms : integer := 1;
base_clk : integer := 125000000;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(5 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_pwm : out std_logic_vector(3 downto 0) -- export
);
end component avalon_pwm_interface;
component avalon_watchdog_interface is
generic (
base_clk : integer := 125000000;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
isl_avs_write : in std_logic := 'X'; -- write
isl_avs_read : in std_logic := 'X'; -- read
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
osl_granted : out std_logic; -- export
osl_watchdog_pwm : out std_logic -- export
);
end component avalon_watchdog_interface;
component avalon_ppwa_interface is
generic (
number_of_ppwas : integer := 1;
base_clk : integer := 125000000;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
islv_signals_to_measure : in std_logic_vector(1 downto 0) := (others => 'X') -- export
);
end component avalon_ppwa_interface;
component altera_merlin_master_translator is
generic (
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W : integer := 10;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 1;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 0;
AV_REGISTERINCOMINGSIGNALS : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(16 downto 0); -- address
uav_burstcount : out std_logic_vector(1 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(1 downto 0); -- byteenable
uav_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(15 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
av_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
av_begintransfer : in std_logic := 'X'; -- begintransfer
av_chipselect : in std_logic := 'X'; -- chipselect
av_readdatavalid : out std_logic; -- readdatavalid
av_lock : in std_logic := 'X'; -- lock
av_debugaccess : in std_logic := 'X'; -- debugaccess
uav_clken : out std_logic; -- clken
av_clken : in std_logic := 'X'; -- clken
uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
av_response : out std_logic_vector(1 downto 0); -- response
uav_writeresponserequest : out std_logic; -- writeresponserequest
uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component altera_merlin_master_translator;
component altera_merlin_master_agent is
generic (
PKT_PROTECTION_H : integer := 80;
PKT_PROTECTION_L : integer := 80;
PKT_BEGIN_BURST : integer := 81;
PKT_BURSTWRAP_H : integer := 79;
PKT_BURSTWRAP_L : integer := 77;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 94;
PKT_BURST_TYPE_L : integer := 93;
PKT_BYTE_CNT_H : integer := 76;
PKT_BYTE_CNT_L : integer := 74;
PKT_ADDR_H : integer := 73;
PKT_ADDR_L : integer := 42;
PKT_TRANS_COMPRESSED_READ : integer := 41;
PKT_TRANS_POSTED : integer := 40;
PKT_TRANS_WRITE : integer := 39;
PKT_TRANS_READ : integer := 38;
PKT_TRANS_LOCK : integer := 82;
PKT_TRANS_EXCLUSIVE : integer := 83;
PKT_DATA_H : integer := 37;
PKT_DATA_L : integer := 6;
PKT_BYTEEN_H : integer := 5;
PKT_BYTEEN_L : integer := 2;
PKT_SRC_ID_H : integer := 1;
PKT_SRC_ID_L : integer := 1;
PKT_DEST_ID_H : integer := 0;
PKT_DEST_ID_L : integer := 0;
PKT_THREAD_ID_H : integer := 88;
PKT_THREAD_ID_L : integer := 87;
PKT_CACHE_H : integer := 92;
PKT_CACHE_L : integer := 89;
PKT_DATA_SIDEBAND_H : integer := 105;
PKT_DATA_SIDEBAND_L : integer := 98;
PKT_QOS_H : integer := 109;
PKT_QOS_L : integer := 106;
PKT_ADDR_SIDEBAND_H : integer := 97;
PKT_ADDR_SIDEBAND_L : integer := 93;
PKT_RESPONSE_STATUS_H : integer := 111;
PKT_RESPONSE_STATUS_L : integer := 110;
ST_DATA_W : integer := 112;
ST_CHANNEL_W : integer := 1;
AV_BURSTCOUNT_W : integer := 3;
SUPPRESS_0_BYTEEN_RSP : integer := 1;
ID : integer := 1;
BURSTWRAP_VALUE : integer := 4;
CACHE_VALUE : integer := 0;
SECURE_ACCESS_BIT : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(69 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic; -- ready
av_response : out std_logic_vector(1 downto 0); -- response
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component altera_merlin_master_agent;
component altera_merlin_slave_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(16 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(87 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(88 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(88 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(33 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_agent;
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(88 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(88 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
component cb20_addr_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(69 downto 0); -- data
src_channel : out std_logic_vector(7 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component cb20_addr_router;
component cb20_id_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(87 downto 0); -- data
src_channel : out std_logic_vector(7 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component cb20_id_router;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_in2 : in std_logic := 'X'; -- reset
reset_in3 : in std_logic := 'X'; -- reset
reset_in4 : in std_logic := 'X'; -- reset
reset_in5 : in std_logic := 'X'; -- reset
reset_in6 : in std_logic := 'X'; -- reset
reset_in7 : in std_logic := 'X'; -- reset
reset_in8 : in std_logic := 'X'; -- reset
reset_in9 : in std_logic := 'X'; -- reset
reset_in10 : in std_logic := 'X'; -- reset
reset_in11 : in std_logic := 'X'; -- reset
reset_in12 : in std_logic := 'X'; -- reset
reset_in13 : in std_logic := 'X'; -- reset
reset_in14 : in std_logic := 'X'; -- reset
reset_in15 : in std_logic := 'X' -- reset
);
end component altera_reset_controller;
component cb20_cmd_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(69 downto 0); -- data
src0_channel : out std_logic_vector(7 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(69 downto 0); -- data
src1_channel : out std_logic_vector(7 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(69 downto 0); -- data
src2_channel : out std_logic_vector(7 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(69 downto 0); -- data
src3_channel : out std_logic_vector(7 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(69 downto 0); -- data
src4_channel : out std_logic_vector(7 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic; -- endofpacket
src5_ready : in std_logic := 'X'; -- ready
src5_valid : out std_logic; -- valid
src5_data : out std_logic_vector(69 downto 0); -- data
src5_channel : out std_logic_vector(7 downto 0); -- channel
src5_startofpacket : out std_logic; -- startofpacket
src5_endofpacket : out std_logic; -- endofpacket
src6_ready : in std_logic := 'X'; -- ready
src6_valid : out std_logic; -- valid
src6_data : out std_logic_vector(69 downto 0); -- data
src6_channel : out std_logic_vector(7 downto 0); -- channel
src6_startofpacket : out std_logic; -- startofpacket
src6_endofpacket : out std_logic; -- endofpacket
src7_ready : in std_logic := 'X'; -- ready
src7_valid : out std_logic; -- valid
src7_data : out std_logic_vector(69 downto 0); -- data
src7_channel : out std_logic_vector(7 downto 0); -- channel
src7_startofpacket : out std_logic; -- startofpacket
src7_endofpacket : out std_logic -- endofpacket
);
end component cb20_cmd_xbar_demux;
component cb20_rsp_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(69 downto 0); -- data
src0_channel : out std_logic_vector(7 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component cb20_rsp_xbar_demux;
component cb20_rsp_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(69 downto 0); -- data
src_channel : out std_logic_vector(7 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X'; -- endofpacket
sink5_ready : out std_logic; -- ready
sink5_valid : in std_logic := 'X'; -- valid
sink5_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
sink5_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink5_startofpacket : in std_logic := 'X'; -- startofpacket
sink5_endofpacket : in std_logic := 'X'; -- endofpacket
sink6_ready : out std_logic; -- ready
sink6_valid : in std_logic := 'X'; -- valid
sink6_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
sink6_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink6_startofpacket : in std_logic := 'X'; -- startofpacket
sink6_endofpacket : in std_logic := 'X'; -- endofpacket
sink7_ready : out std_logic; -- ready
sink7_valid : in std_logic := 'X'; -- valid
sink7_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
sink7_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink7_startofpacket : in std_logic := 'X'; -- startofpacket
sink7_endofpacket : in std_logic := 'X' -- endofpacket
);
end component cb20_rsp_xbar_mux;
component cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component cb20_info_device_0_avalon_slave_translator;
component cb20_gpio_block_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(3 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component cb20_gpio_block_0_avalon_slave_0_translator;
component cb20_pwm_interface_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(5 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component cb20_pwm_interface_0_avalon_slave_0_translator;
component cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_channel : out std_logic_vector(7 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component cb20_width_adapter;
component cb20_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(69 downto 0); -- data
out_channel : out std_logic_vector(7 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component cb20_width_adapter_001;
component cb20_gpio_block_0 is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => 'X') -- export
);
end component cb20_gpio_block_0;
component cb20_gpio_block_1 is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component cb20_gpio_block_1;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [EIM_Slave_to_Avalon_Master_0:isl_clk, EIM_Slave_to_Avalon_Master_0_avalon_master_translator:clk, EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:clk, addr_router:clk, cmd_xbar_demux:clk, dacad5668_0:isl_clk, dacad5668_0_avalon_slave_translator:clk, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:clk, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, fqd_interface_0:isl_clk, fqd_interface_0_avalon_slave_0_translator:clk, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, gpio_block_0:isl_clk, gpio_block_0_avalon_slave_0_translator:clk, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, gpio_block_1:isl_clk, gpio_block_1_avalon_slave_0_translator:clk, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, id_router_006:clk, id_router_007:clk, info_device_0:isl_clk, info_device_0_avalon_slave_translator:clk, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:clk, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, ppwa_block_0:isl_clk, ppwa_block_0_avalon_slave_0_translator:clk, ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, pwm_interface_0:isl_clk, pwm_interface_0_avalon_slave_0_translator:clk, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_demux_007:clk, rsp_xbar_mux:clk, rst_controller_001:clk, watchdog_block_0:isl_clk, watchdog_block_0_avalon_slave_0_translator:clk, watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk, width_adapter_006:clk, width_adapter_007:clk, width_adapter_008:clk, width_adapter_009:clk, width_adapter_010:clk, width_adapter_011:clk, width_adapter_012:clk, width_adapter_013:clk, width_adapter_014:clk, width_adapter_015:clk]
signal eim_slave_to_avalon_master_0_avalon_master_waitrequest : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_waitrequest -> EIM_Slave_to_Avalon_Master_0:islv_waitrequest
signal eim_slave_to_avalon_master_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0:oslv_writedata -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_writedata
signal eim_slave_to_avalon_master_0_avalon_master_address : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0:oslv_address -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_address
signal eim_slave_to_avalon_master_0_avalon_master_write : std_logic; -- EIM_Slave_to_Avalon_Master_0:oslv_write -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_write
signal eim_slave_to_avalon_master_0_avalon_master_read : std_logic; -- EIM_Slave_to_Avalon_Master_0:oslv_read -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_read
signal eim_slave_to_avalon_master_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_readdata -> EIM_Slave_to_Avalon_Master_0:islv_readdata
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- info_device_0:osl_avs_waitrequest -> info_device_0_avalon_slave_translator:av_waitrequest
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- info_device_0_avalon_slave_translator:av_writedata -> info_device_0:islv_avs_write_data
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- info_device_0_avalon_slave_translator:av_address -> info_device_0:islv_avs_address
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_write : std_logic; -- info_device_0_avalon_slave_translator:av_write -> info_device_0:isl_avs_write
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_read : std_logic; -- info_device_0_avalon_slave_translator:av_read -> info_device_0:isl_avs_read
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- info_device_0:oslv_avs_read_data -> info_device_0_avalon_slave_translator:av_readdata
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- info_device_0_avalon_slave_translator:av_byteenable -> info_device_0:islv_avs_byteenable
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- dacad5668_0:osl_avs_waitrequest -> dacad5668_0_avalon_slave_translator:av_waitrequest
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- dacad5668_0_avalon_slave_translator:av_writedata -> dacad5668_0:islv_avs_write_data
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- dacad5668_0_avalon_slave_translator:av_address -> dacad5668_0:islv_avs_address
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_write : std_logic; -- dacad5668_0_avalon_slave_translator:av_write -> dacad5668_0:isl_avs_write
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_read : std_logic; -- dacad5668_0_avalon_slave_translator:av_read -> dacad5668_0:isl_avs_read
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- dacad5668_0:oslv_avs_read_data -> dacad5668_0_avalon_slave_translator:av_readdata
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- dacad5668_0_avalon_slave_translator:av_byteenable -> dacad5668_0:islv_avs_byteenable
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- fqd_interface_0:osl_avs_waitrequest -> fqd_interface_0_avalon_slave_0_translator:av_waitrequest
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- fqd_interface_0_avalon_slave_0_translator:av_writedata -> fqd_interface_0:islv_avs_write_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- fqd_interface_0_avalon_slave_0_translator:av_address -> fqd_interface_0:islv_avs_address
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- fqd_interface_0_avalon_slave_0_translator:av_write -> fqd_interface_0:isl_avs_write
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- fqd_interface_0_avalon_slave_0_translator:av_read -> fqd_interface_0:isl_avs_read
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- fqd_interface_0:oslv_avs_read_data -> fqd_interface_0_avalon_slave_0_translator:av_readdata
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- fqd_interface_0_avalon_slave_0_translator:av_byteenable -> fqd_interface_0:islv_avs_byteenable
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- gpio_block_0:osl_avs_waitrequest -> gpio_block_0_avalon_slave_0_translator:av_waitrequest
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- gpio_block_0_avalon_slave_0_translator:av_writedata -> gpio_block_0:islv_avs_write_data
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(3 downto 0); -- gpio_block_0_avalon_slave_0_translator:av_address -> gpio_block_0:islv_avs_address
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- gpio_block_0_avalon_slave_0_translator:av_write -> gpio_block_0:isl_avs_write
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- gpio_block_0_avalon_slave_0_translator:av_read -> gpio_block_0:isl_avs_read
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- gpio_block_0:oslv_avs_read_data -> gpio_block_0_avalon_slave_0_translator:av_readdata
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_0_avalon_slave_0_translator:av_byteenable -> gpio_block_0:islv_avs_byteenable
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- pwm_interface_0:osl_avs_waitrequest -> pwm_interface_0_avalon_slave_0_translator:av_waitrequest
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- pwm_interface_0_avalon_slave_0_translator:av_writedata -> pwm_interface_0:islv_avs_write_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(5 downto 0); -- pwm_interface_0_avalon_slave_0_translator:av_address -> pwm_interface_0:islv_avs_address
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- pwm_interface_0_avalon_slave_0_translator:av_write -> pwm_interface_0:isl_avs_write
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- pwm_interface_0_avalon_slave_0_translator:av_read -> pwm_interface_0:isl_avs_read
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- pwm_interface_0:oslv_avs_read_data -> pwm_interface_0_avalon_slave_0_translator:av_readdata
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- pwm_interface_0_avalon_slave_0_translator:av_byteenable -> pwm_interface_0:islv_avs_byteenable
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- gpio_block_1:osl_avs_waitrequest -> gpio_block_1_avalon_slave_0_translator:av_waitrequest
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- gpio_block_1_avalon_slave_0_translator:av_writedata -> gpio_block_1:islv_avs_write_data
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(3 downto 0); -- gpio_block_1_avalon_slave_0_translator:av_address -> gpio_block_1:islv_avs_address
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- gpio_block_1_avalon_slave_0_translator:av_write -> gpio_block_1:isl_avs_write
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- gpio_block_1_avalon_slave_0_translator:av_read -> gpio_block_1:isl_avs_read
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- gpio_block_1:oslv_avs_read_data -> gpio_block_1_avalon_slave_0_translator:av_readdata
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_1_avalon_slave_0_translator:av_byteenable -> gpio_block_1:islv_avs_byteenable
signal watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- watchdog_block_0:osl_avs_waitrequest -> watchdog_block_0_avalon_slave_0_translator:av_waitrequest
signal watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- watchdog_block_0_avalon_slave_0_translator:av_writedata -> watchdog_block_0:islv_avs_write_data
signal watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- watchdog_block_0_avalon_slave_0_translator:av_address -> watchdog_block_0:islv_avs_address
signal watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- watchdog_block_0_avalon_slave_0_translator:av_write -> watchdog_block_0:isl_avs_write
signal watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- watchdog_block_0_avalon_slave_0_translator:av_read -> watchdog_block_0:isl_avs_read
signal watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- watchdog_block_0:oslv_avs_read_data -> watchdog_block_0_avalon_slave_0_translator:av_readdata
signal watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- watchdog_block_0_avalon_slave_0_translator:av_byteenable -> watchdog_block_0:islv_avs_byteenable
signal ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- ppwa_block_0:osl_avs_waitrequest -> ppwa_block_0_avalon_slave_0_translator:av_waitrequest
signal ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- ppwa_block_0_avalon_slave_0_translator:av_writedata -> ppwa_block_0:islv_avs_write_data
signal ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- ppwa_block_0_avalon_slave_0_translator:av_address -> ppwa_block_0:islv_avs_address
signal ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- ppwa_block_0_avalon_slave_0_translator:av_write -> ppwa_block_0:isl_avs_write
signal ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- ppwa_block_0_avalon_slave_0_translator:av_read -> ppwa_block_0:isl_avs_read
signal ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- ppwa_block_0:oslv_avs_read_data -> ppwa_block_0_avalon_slave_0_translator:av_readdata
signal ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- ppwa_block_0_avalon_slave_0_translator:av_byteenable -> ppwa_block_0:islv_avs_byteenable
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_waitrequest -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_waitrequest
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(1 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_burstcount -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_burstcount
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_writedata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_writedata -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_writedata
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_address : std_logic_vector(16 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_address -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_address
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_lock : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_lock -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_lock
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_write : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_write -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_write
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_read : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_read -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_read
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdata -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_readdata
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_debugaccess -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(1 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_byteenable -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_byteenable
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_readdatavalid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- info_device_0_avalon_slave_translator:uav_waitrequest -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> info_device_0_avalon_slave_translator:uav_burstcount
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> info_device_0_avalon_slave_translator:uav_writedata
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_address -> info_device_0_avalon_slave_translator:uav_address
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_write -> info_device_0_avalon_slave_translator:uav_write
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_lock -> info_device_0_avalon_slave_translator:uav_lock
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_read -> info_device_0_avalon_slave_translator:uav_read
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- info_device_0_avalon_slave_translator:uav_readdata -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- info_device_0_avalon_slave_translator:uav_readdatavalid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> info_device_0_avalon_slave_translator:uav_debugaccess
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> info_device_0_avalon_slave_translator:uav_byteenable
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- dacad5668_0_avalon_slave_translator:uav_waitrequest -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> dacad5668_0_avalon_slave_translator:uav_burstcount
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> dacad5668_0_avalon_slave_translator:uav_writedata
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_address -> dacad5668_0_avalon_slave_translator:uav_address
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_write -> dacad5668_0_avalon_slave_translator:uav_write
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_lock -> dacad5668_0_avalon_slave_translator:uav_lock
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_read -> dacad5668_0_avalon_slave_translator:uav_read
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- dacad5668_0_avalon_slave_translator:uav_readdata -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- dacad5668_0_avalon_slave_translator:uav_readdatavalid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> dacad5668_0_avalon_slave_translator:uav_debugaccess
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> dacad5668_0_avalon_slave_translator:uav_byteenable
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- fqd_interface_0_avalon_slave_0_translator:uav_waitrequest -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> fqd_interface_0_avalon_slave_0_translator:uav_burstcount
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> fqd_interface_0_avalon_slave_0_translator:uav_writedata
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> fqd_interface_0_avalon_slave_0_translator:uav_address
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> fqd_interface_0_avalon_slave_0_translator:uav_write
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> fqd_interface_0_avalon_slave_0_translator:uav_lock
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> fqd_interface_0_avalon_slave_0_translator:uav_read
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- fqd_interface_0_avalon_slave_0_translator:uav_readdata -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- fqd_interface_0_avalon_slave_0_translator:uav_readdatavalid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> fqd_interface_0_avalon_slave_0_translator:uav_debugaccess
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> fqd_interface_0_avalon_slave_0_translator:uav_byteenable
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- gpio_block_0_avalon_slave_0_translator:uav_waitrequest -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> gpio_block_0_avalon_slave_0_translator:uav_burstcount
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> gpio_block_0_avalon_slave_0_translator:uav_writedata
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> gpio_block_0_avalon_slave_0_translator:uav_address
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> gpio_block_0_avalon_slave_0_translator:uav_write
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> gpio_block_0_avalon_slave_0_translator:uav_lock
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> gpio_block_0_avalon_slave_0_translator:uav_read
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- gpio_block_0_avalon_slave_0_translator:uav_readdata -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- gpio_block_0_avalon_slave_0_translator:uav_readdatavalid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> gpio_block_0_avalon_slave_0_translator:uav_debugaccess
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> gpio_block_0_avalon_slave_0_translator:uav_byteenable
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- pwm_interface_0_avalon_slave_0_translator:uav_waitrequest -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> pwm_interface_0_avalon_slave_0_translator:uav_burstcount
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> pwm_interface_0_avalon_slave_0_translator:uav_writedata
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> pwm_interface_0_avalon_slave_0_translator:uav_address
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> pwm_interface_0_avalon_slave_0_translator:uav_write
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> pwm_interface_0_avalon_slave_0_translator:uav_lock
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> pwm_interface_0_avalon_slave_0_translator:uav_read
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- pwm_interface_0_avalon_slave_0_translator:uav_readdata -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- pwm_interface_0_avalon_slave_0_translator:uav_readdatavalid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pwm_interface_0_avalon_slave_0_translator:uav_debugaccess
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> pwm_interface_0_avalon_slave_0_translator:uav_byteenable
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- gpio_block_1_avalon_slave_0_translator:uav_waitrequest -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> gpio_block_1_avalon_slave_0_translator:uav_burstcount
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> gpio_block_1_avalon_slave_0_translator:uav_writedata
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> gpio_block_1_avalon_slave_0_translator:uav_address
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> gpio_block_1_avalon_slave_0_translator:uav_write
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> gpio_block_1_avalon_slave_0_translator:uav_lock
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> gpio_block_1_avalon_slave_0_translator:uav_read
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- gpio_block_1_avalon_slave_0_translator:uav_readdata -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- gpio_block_1_avalon_slave_0_translator:uav_readdatavalid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> gpio_block_1_avalon_slave_0_translator:uav_debugaccess
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> gpio_block_1_avalon_slave_0_translator:uav_byteenable
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- watchdog_block_0_avalon_slave_0_translator:uav_waitrequest -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> watchdog_block_0_avalon_slave_0_translator:uav_burstcount
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> watchdog_block_0_avalon_slave_0_translator:uav_writedata
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> watchdog_block_0_avalon_slave_0_translator:uav_address
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> watchdog_block_0_avalon_slave_0_translator:uav_write
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> watchdog_block_0_avalon_slave_0_translator:uav_lock
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> watchdog_block_0_avalon_slave_0_translator:uav_read
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- watchdog_block_0_avalon_slave_0_translator:uav_readdata -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- watchdog_block_0_avalon_slave_0_translator:uav_readdatavalid -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> watchdog_block_0_avalon_slave_0_translator:uav_debugaccess
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> watchdog_block_0_avalon_slave_0_translator:uav_byteenable
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- ppwa_block_0_avalon_slave_0_translator:uav_waitrequest -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> ppwa_block_0_avalon_slave_0_translator:uav_burstcount
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> ppwa_block_0_avalon_slave_0_translator:uav_writedata
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> ppwa_block_0_avalon_slave_0_translator:uav_address
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> ppwa_block_0_avalon_slave_0_translator:uav_write
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> ppwa_block_0_avalon_slave_0_translator:uav_lock
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> ppwa_block_0_avalon_slave_0_translator:uav_read
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- ppwa_block_0_avalon_slave_0_translator:uav_readdata -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- ppwa_block_0_avalon_slave_0_translator:uav_readdatavalid -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> ppwa_block_0_avalon_slave_0_translator:uav_debugaccess
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> ppwa_block_0_avalon_slave_0_translator:uav_byteenable
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(69 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_ready
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
signal watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_006:sink_ready -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
signal ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_007:sink_ready -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> altpll_0:reset
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [EIM_Slave_to_Avalon_Master_0_avalon_master_translator:reset, EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:reset, addr_router:reset, cmd_xbar_demux:reset, dacad5668_0_avalon_slave_translator:reset, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:reset, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, fqd_interface_0_avalon_slave_0_translator:reset, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, gpio_block_0_avalon_slave_0_translator:reset, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, gpio_block_1_avalon_slave_0_translator:reset, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, info_device_0_avalon_slave_translator:reset, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:reset, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, ppwa_block_0_avalon_slave_0_translator:reset, ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, pwm_interface_0_avalon_slave_0_translator:reset, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_mux:reset, rst_controller_001_reset_out_reset:in, watchdog_block_0_avalon_slave_0_translator:reset, watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_004:reset, width_adapter_005:reset, width_adapter_006:reset, width_adapter_007:reset, width_adapter_008:reset, width_adapter_009:reset, width_adapter_010:reset, width_adapter_011:reset, width_adapter_012:reset, width_adapter_013:reset, width_adapter_014:reset, width_adapter_015:reset]
signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> width_adapter:in_endofpacket
signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> width_adapter:in_valid
signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> width_adapter:in_startofpacket
signal cmd_xbar_demux_src0_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src0_data -> width_adapter:in_data
signal cmd_xbar_demux_src0_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux:src0_channel -> width_adapter:in_channel
signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> width_adapter_002:in_endofpacket
signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> width_adapter_002:in_valid
signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> width_adapter_002:in_startofpacket
signal cmd_xbar_demux_src1_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src1_data -> width_adapter_002:in_data
signal cmd_xbar_demux_src1_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux:src1_channel -> width_adapter_002:in_channel
signal cmd_xbar_demux_src2_endofpacket : std_logic; -- cmd_xbar_demux:src2_endofpacket -> width_adapter_004:in_endofpacket
signal cmd_xbar_demux_src2_valid : std_logic; -- cmd_xbar_demux:src2_valid -> width_adapter_004:in_valid
signal cmd_xbar_demux_src2_startofpacket : std_logic; -- cmd_xbar_demux:src2_startofpacket -> width_adapter_004:in_startofpacket
signal cmd_xbar_demux_src2_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src2_data -> width_adapter_004:in_data
signal cmd_xbar_demux_src2_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux:src2_channel -> width_adapter_004:in_channel
signal cmd_xbar_demux_src3_endofpacket : std_logic; -- cmd_xbar_demux:src3_endofpacket -> width_adapter_006:in_endofpacket
signal cmd_xbar_demux_src3_valid : std_logic; -- cmd_xbar_demux:src3_valid -> width_adapter_006:in_valid
signal cmd_xbar_demux_src3_startofpacket : std_logic; -- cmd_xbar_demux:src3_startofpacket -> width_adapter_006:in_startofpacket
signal cmd_xbar_demux_src3_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src3_data -> width_adapter_006:in_data
signal cmd_xbar_demux_src3_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux:src3_channel -> width_adapter_006:in_channel
signal cmd_xbar_demux_src4_endofpacket : std_logic; -- cmd_xbar_demux:src4_endofpacket -> width_adapter_008:in_endofpacket
signal cmd_xbar_demux_src4_valid : std_logic; -- cmd_xbar_demux:src4_valid -> width_adapter_008:in_valid
signal cmd_xbar_demux_src4_startofpacket : std_logic; -- cmd_xbar_demux:src4_startofpacket -> width_adapter_008:in_startofpacket
signal cmd_xbar_demux_src4_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src4_data -> width_adapter_008:in_data
signal cmd_xbar_demux_src4_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux:src4_channel -> width_adapter_008:in_channel
signal cmd_xbar_demux_src5_endofpacket : std_logic; -- cmd_xbar_demux:src5_endofpacket -> width_adapter_010:in_endofpacket
signal cmd_xbar_demux_src5_valid : std_logic; -- cmd_xbar_demux:src5_valid -> width_adapter_010:in_valid
signal cmd_xbar_demux_src5_startofpacket : std_logic; -- cmd_xbar_demux:src5_startofpacket -> width_adapter_010:in_startofpacket
signal cmd_xbar_demux_src5_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src5_data -> width_adapter_010:in_data
signal cmd_xbar_demux_src5_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux:src5_channel -> width_adapter_010:in_channel
signal cmd_xbar_demux_src6_endofpacket : std_logic; -- cmd_xbar_demux:src6_endofpacket -> width_adapter_012:in_endofpacket
signal cmd_xbar_demux_src6_valid : std_logic; -- cmd_xbar_demux:src6_valid -> width_adapter_012:in_valid
signal cmd_xbar_demux_src6_startofpacket : std_logic; -- cmd_xbar_demux:src6_startofpacket -> width_adapter_012:in_startofpacket
signal cmd_xbar_demux_src6_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src6_data -> width_adapter_012:in_data
signal cmd_xbar_demux_src6_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux:src6_channel -> width_adapter_012:in_channel
signal cmd_xbar_demux_src7_endofpacket : std_logic; -- cmd_xbar_demux:src7_endofpacket -> width_adapter_014:in_endofpacket
signal cmd_xbar_demux_src7_valid : std_logic; -- cmd_xbar_demux:src7_valid -> width_adapter_014:in_valid
signal cmd_xbar_demux_src7_startofpacket : std_logic; -- cmd_xbar_demux:src7_startofpacket -> width_adapter_014:in_startofpacket
signal cmd_xbar_demux_src7_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src7_data -> width_adapter_014:in_data
signal cmd_xbar_demux_src7_channel : std_logic_vector(7 downto 0); -- cmd_xbar_demux:src7_channel -> width_adapter_014:in_channel
signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
signal rsp_xbar_demux_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
signal rsp_xbar_demux_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
signal rsp_xbar_demux_src0_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
signal rsp_xbar_demux_001_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
signal rsp_xbar_demux_001_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
signal rsp_xbar_demux_001_src0_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
signal rsp_xbar_demux_002_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
signal rsp_xbar_demux_002_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
signal rsp_xbar_demux_002_src0_ready : std_logic; -- rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
signal rsp_xbar_demux_003_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
signal rsp_xbar_demux_003_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
signal rsp_xbar_demux_004_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
signal rsp_xbar_demux_004_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
signal rsp_xbar_demux_004_src0_ready : std_logic; -- rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux:sink5_endofpacket
signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux:sink5_valid
signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux:sink5_startofpacket
signal rsp_xbar_demux_005_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux:sink5_data
signal rsp_xbar_demux_005_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux:sink5_channel
signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux:sink5_ready -> rsp_xbar_demux_005:src0_ready
signal rsp_xbar_demux_006_src0_endofpacket : std_logic; -- rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux:sink6_endofpacket
signal rsp_xbar_demux_006_src0_valid : std_logic; -- rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux:sink6_valid
signal rsp_xbar_demux_006_src0_startofpacket : std_logic; -- rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux:sink6_startofpacket
signal rsp_xbar_demux_006_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_006:src0_data -> rsp_xbar_mux:sink6_data
signal rsp_xbar_demux_006_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux:sink6_channel
signal rsp_xbar_demux_006_src0_ready : std_logic; -- rsp_xbar_mux:sink6_ready -> rsp_xbar_demux_006:src0_ready
signal rsp_xbar_demux_007_src0_endofpacket : std_logic; -- rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux:sink7_endofpacket
signal rsp_xbar_demux_007_src0_valid : std_logic; -- rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux:sink7_valid
signal rsp_xbar_demux_007_src0_startofpacket : std_logic; -- rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux:sink7_startofpacket
signal rsp_xbar_demux_007_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_007:src0_data -> rsp_xbar_mux:sink7_data
signal rsp_xbar_demux_007_src0_channel : std_logic_vector(7 downto 0); -- rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux:sink7_channel
signal rsp_xbar_demux_007_src0_ready : std_logic; -- rsp_xbar_mux:sink7_ready -> rsp_xbar_demux_007:src0_ready
signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> cmd_xbar_demux:sink_valid
signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
signal addr_router_src_data : std_logic_vector(69 downto 0); -- addr_router:src_data -> cmd_xbar_demux:sink_data
signal addr_router_src_channel : std_logic_vector(7 downto 0); -- addr_router:src_channel -> cmd_xbar_demux:sink_channel
signal addr_router_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> addr_router:src_ready
signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_src_data : std_logic_vector(69 downto 0); -- rsp_xbar_mux:src_data -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_src_channel : std_logic_vector(7 downto 0); -- rsp_xbar_mux:src_channel -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_src_ready : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
signal cmd_xbar_demux_src0_ready : std_logic; -- width_adapter:in_ready -> cmd_xbar_demux:src0_ready
signal width_adapter_src_endofpacket : std_logic; -- width_adapter:out_endofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_src_valid : std_logic; -- width_adapter:out_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_src_startofpacket : std_logic; -- width_adapter:out_startofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_src_data : std_logic_vector(87 downto 0); -- width_adapter:out_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_src_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter:out_ready
signal width_adapter_src_channel : std_logic_vector(7 downto 0); -- width_adapter:out_channel -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> width_adapter_001:in_endofpacket
signal id_router_src_valid : std_logic; -- id_router:src_valid -> width_adapter_001:in_valid
signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> width_adapter_001:in_startofpacket
signal id_router_src_data : std_logic_vector(87 downto 0); -- id_router:src_data -> width_adapter_001:in_data
signal id_router_src_channel : std_logic_vector(7 downto 0); -- id_router:src_channel -> width_adapter_001:in_channel
signal id_router_src_ready : std_logic; -- width_adapter_001:in_ready -> id_router:src_ready
signal width_adapter_001_src_endofpacket : std_logic; -- width_adapter_001:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
signal width_adapter_001_src_valid : std_logic; -- width_adapter_001:out_valid -> rsp_xbar_demux:sink_valid
signal width_adapter_001_src_startofpacket : std_logic; -- width_adapter_001:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
signal width_adapter_001_src_data : std_logic_vector(69 downto 0); -- width_adapter_001:out_data -> rsp_xbar_demux:sink_data
signal width_adapter_001_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> width_adapter_001:out_ready
signal width_adapter_001_src_channel : std_logic_vector(7 downto 0); -- width_adapter_001:out_channel -> rsp_xbar_demux:sink_channel
signal cmd_xbar_demux_src1_ready : std_logic; -- width_adapter_002:in_ready -> cmd_xbar_demux:src1_ready
signal width_adapter_002_src_endofpacket : std_logic; -- width_adapter_002:out_endofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_002_src_valid : std_logic; -- width_adapter_002:out_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_002_src_startofpacket : std_logic; -- width_adapter_002:out_startofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_002_src_data : std_logic_vector(87 downto 0); -- width_adapter_002:out_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_002_src_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_002:out_ready
signal width_adapter_002_src_channel : std_logic_vector(7 downto 0); -- width_adapter_002:out_channel -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> width_adapter_003:in_endofpacket
signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> width_adapter_003:in_valid
signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> width_adapter_003:in_startofpacket
signal id_router_001_src_data : std_logic_vector(87 downto 0); -- id_router_001:src_data -> width_adapter_003:in_data
signal id_router_001_src_channel : std_logic_vector(7 downto 0); -- id_router_001:src_channel -> width_adapter_003:in_channel
signal id_router_001_src_ready : std_logic; -- width_adapter_003:in_ready -> id_router_001:src_ready
signal width_adapter_003_src_endofpacket : std_logic; -- width_adapter_003:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
signal width_adapter_003_src_valid : std_logic; -- width_adapter_003:out_valid -> rsp_xbar_demux_001:sink_valid
signal width_adapter_003_src_startofpacket : std_logic; -- width_adapter_003:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
signal width_adapter_003_src_data : std_logic_vector(69 downto 0); -- width_adapter_003:out_data -> rsp_xbar_demux_001:sink_data
signal width_adapter_003_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> width_adapter_003:out_ready
signal width_adapter_003_src_channel : std_logic_vector(7 downto 0); -- width_adapter_003:out_channel -> rsp_xbar_demux_001:sink_channel
signal cmd_xbar_demux_src2_ready : std_logic; -- width_adapter_004:in_ready -> cmd_xbar_demux:src2_ready
signal width_adapter_004_src_endofpacket : std_logic; -- width_adapter_004:out_endofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_004_src_valid : std_logic; -- width_adapter_004:out_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_004_src_startofpacket : std_logic; -- width_adapter_004:out_startofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_004_src_data : std_logic_vector(87 downto 0); -- width_adapter_004:out_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_004_src_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_004:out_ready
signal width_adapter_004_src_channel : std_logic_vector(7 downto 0); -- width_adapter_004:out_channel -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> width_adapter_005:in_endofpacket
signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> width_adapter_005:in_valid
signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> width_adapter_005:in_startofpacket
signal id_router_002_src_data : std_logic_vector(87 downto 0); -- id_router_002:src_data -> width_adapter_005:in_data
signal id_router_002_src_channel : std_logic_vector(7 downto 0); -- id_router_002:src_channel -> width_adapter_005:in_channel
signal id_router_002_src_ready : std_logic; -- width_adapter_005:in_ready -> id_router_002:src_ready
signal width_adapter_005_src_endofpacket : std_logic; -- width_adapter_005:out_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
signal width_adapter_005_src_valid : std_logic; -- width_adapter_005:out_valid -> rsp_xbar_demux_002:sink_valid
signal width_adapter_005_src_startofpacket : std_logic; -- width_adapter_005:out_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
signal width_adapter_005_src_data : std_logic_vector(69 downto 0); -- width_adapter_005:out_data -> rsp_xbar_demux_002:sink_data
signal width_adapter_005_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> width_adapter_005:out_ready
signal width_adapter_005_src_channel : std_logic_vector(7 downto 0); -- width_adapter_005:out_channel -> rsp_xbar_demux_002:sink_channel
signal cmd_xbar_demux_src3_ready : std_logic; -- width_adapter_006:in_ready -> cmd_xbar_demux:src3_ready
signal width_adapter_006_src_endofpacket : std_logic; -- width_adapter_006:out_endofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_006_src_valid : std_logic; -- width_adapter_006:out_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_006_src_startofpacket : std_logic; -- width_adapter_006:out_startofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_006_src_data : std_logic_vector(87 downto 0); -- width_adapter_006:out_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_006_src_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_006:out_ready
signal width_adapter_006_src_channel : std_logic_vector(7 downto 0); -- width_adapter_006:out_channel -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> width_adapter_007:in_endofpacket
signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> width_adapter_007:in_valid
signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> width_adapter_007:in_startofpacket
signal id_router_003_src_data : std_logic_vector(87 downto 0); -- id_router_003:src_data -> width_adapter_007:in_data
signal id_router_003_src_channel : std_logic_vector(7 downto 0); -- id_router_003:src_channel -> width_adapter_007:in_channel
signal id_router_003_src_ready : std_logic; -- width_adapter_007:in_ready -> id_router_003:src_ready
signal width_adapter_007_src_endofpacket : std_logic; -- width_adapter_007:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
signal width_adapter_007_src_valid : std_logic; -- width_adapter_007:out_valid -> rsp_xbar_demux_003:sink_valid
signal width_adapter_007_src_startofpacket : std_logic; -- width_adapter_007:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
signal width_adapter_007_src_data : std_logic_vector(69 downto 0); -- width_adapter_007:out_data -> rsp_xbar_demux_003:sink_data
signal width_adapter_007_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> width_adapter_007:out_ready
signal width_adapter_007_src_channel : std_logic_vector(7 downto 0); -- width_adapter_007:out_channel -> rsp_xbar_demux_003:sink_channel
signal cmd_xbar_demux_src4_ready : std_logic; -- width_adapter_008:in_ready -> cmd_xbar_demux:src4_ready
signal width_adapter_008_src_endofpacket : std_logic; -- width_adapter_008:out_endofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_008_src_valid : std_logic; -- width_adapter_008:out_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_008_src_startofpacket : std_logic; -- width_adapter_008:out_startofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_008_src_data : std_logic_vector(87 downto 0); -- width_adapter_008:out_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_008_src_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_008:out_ready
signal width_adapter_008_src_channel : std_logic_vector(7 downto 0); -- width_adapter_008:out_channel -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> width_adapter_009:in_endofpacket
signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> width_adapter_009:in_valid
signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> width_adapter_009:in_startofpacket
signal id_router_004_src_data : std_logic_vector(87 downto 0); -- id_router_004:src_data -> width_adapter_009:in_data
signal id_router_004_src_channel : std_logic_vector(7 downto 0); -- id_router_004:src_channel -> width_adapter_009:in_channel
signal id_router_004_src_ready : std_logic; -- width_adapter_009:in_ready -> id_router_004:src_ready
signal width_adapter_009_src_endofpacket : std_logic; -- width_adapter_009:out_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
signal width_adapter_009_src_valid : std_logic; -- width_adapter_009:out_valid -> rsp_xbar_demux_004:sink_valid
signal width_adapter_009_src_startofpacket : std_logic; -- width_adapter_009:out_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
signal width_adapter_009_src_data : std_logic_vector(69 downto 0); -- width_adapter_009:out_data -> rsp_xbar_demux_004:sink_data
signal width_adapter_009_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> width_adapter_009:out_ready
signal width_adapter_009_src_channel : std_logic_vector(7 downto 0); -- width_adapter_009:out_channel -> rsp_xbar_demux_004:sink_channel
signal cmd_xbar_demux_src5_ready : std_logic; -- width_adapter_010:in_ready -> cmd_xbar_demux:src5_ready
signal width_adapter_010_src_endofpacket : std_logic; -- width_adapter_010:out_endofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_010_src_valid : std_logic; -- width_adapter_010:out_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_010_src_startofpacket : std_logic; -- width_adapter_010:out_startofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_010_src_data : std_logic_vector(87 downto 0); -- width_adapter_010:out_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_010_src_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_010:out_ready
signal width_adapter_010_src_channel : std_logic_vector(7 downto 0); -- width_adapter_010:out_channel -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> width_adapter_011:in_endofpacket
signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> width_adapter_011:in_valid
signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> width_adapter_011:in_startofpacket
signal id_router_005_src_data : std_logic_vector(87 downto 0); -- id_router_005:src_data -> width_adapter_011:in_data
signal id_router_005_src_channel : std_logic_vector(7 downto 0); -- id_router_005:src_channel -> width_adapter_011:in_channel
signal id_router_005_src_ready : std_logic; -- width_adapter_011:in_ready -> id_router_005:src_ready
signal width_adapter_011_src_endofpacket : std_logic; -- width_adapter_011:out_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
signal width_adapter_011_src_valid : std_logic; -- width_adapter_011:out_valid -> rsp_xbar_demux_005:sink_valid
signal width_adapter_011_src_startofpacket : std_logic; -- width_adapter_011:out_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
signal width_adapter_011_src_data : std_logic_vector(69 downto 0); -- width_adapter_011:out_data -> rsp_xbar_demux_005:sink_data
signal width_adapter_011_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> width_adapter_011:out_ready
signal width_adapter_011_src_channel : std_logic_vector(7 downto 0); -- width_adapter_011:out_channel -> rsp_xbar_demux_005:sink_channel
signal cmd_xbar_demux_src6_ready : std_logic; -- width_adapter_012:in_ready -> cmd_xbar_demux:src6_ready
signal width_adapter_012_src_endofpacket : std_logic; -- width_adapter_012:out_endofpacket -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_012_src_valid : std_logic; -- width_adapter_012:out_valid -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_012_src_startofpacket : std_logic; -- width_adapter_012:out_startofpacket -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_012_src_data : std_logic_vector(87 downto 0); -- width_adapter_012:out_data -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_012_src_ready : std_logic; -- watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_012:out_ready
signal width_adapter_012_src_channel : std_logic_vector(7 downto 0); -- width_adapter_012:out_channel -> watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_006_src_endofpacket : std_logic; -- id_router_006:src_endofpacket -> width_adapter_013:in_endofpacket
signal id_router_006_src_valid : std_logic; -- id_router_006:src_valid -> width_adapter_013:in_valid
signal id_router_006_src_startofpacket : std_logic; -- id_router_006:src_startofpacket -> width_adapter_013:in_startofpacket
signal id_router_006_src_data : std_logic_vector(87 downto 0); -- id_router_006:src_data -> width_adapter_013:in_data
signal id_router_006_src_channel : std_logic_vector(7 downto 0); -- id_router_006:src_channel -> width_adapter_013:in_channel
signal id_router_006_src_ready : std_logic; -- width_adapter_013:in_ready -> id_router_006:src_ready
signal width_adapter_013_src_endofpacket : std_logic; -- width_adapter_013:out_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
signal width_adapter_013_src_valid : std_logic; -- width_adapter_013:out_valid -> rsp_xbar_demux_006:sink_valid
signal width_adapter_013_src_startofpacket : std_logic; -- width_adapter_013:out_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
signal width_adapter_013_src_data : std_logic_vector(69 downto 0); -- width_adapter_013:out_data -> rsp_xbar_demux_006:sink_data
signal width_adapter_013_src_ready : std_logic; -- rsp_xbar_demux_006:sink_ready -> width_adapter_013:out_ready
signal width_adapter_013_src_channel : std_logic_vector(7 downto 0); -- width_adapter_013:out_channel -> rsp_xbar_demux_006:sink_channel
signal cmd_xbar_demux_src7_ready : std_logic; -- width_adapter_014:in_ready -> cmd_xbar_demux:src7_ready
signal width_adapter_014_src_endofpacket : std_logic; -- width_adapter_014:out_endofpacket -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_014_src_valid : std_logic; -- width_adapter_014:out_valid -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_014_src_startofpacket : std_logic; -- width_adapter_014:out_startofpacket -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_014_src_data : std_logic_vector(87 downto 0); -- width_adapter_014:out_data -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_014_src_ready : std_logic; -- ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_014:out_ready
signal width_adapter_014_src_channel : std_logic_vector(7 downto 0); -- width_adapter_014:out_channel -> ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_007_src_endofpacket : std_logic; -- id_router_007:src_endofpacket -> width_adapter_015:in_endofpacket
signal id_router_007_src_valid : std_logic; -- id_router_007:src_valid -> width_adapter_015:in_valid
signal id_router_007_src_startofpacket : std_logic; -- id_router_007:src_startofpacket -> width_adapter_015:in_startofpacket
signal id_router_007_src_data : std_logic_vector(87 downto 0); -- id_router_007:src_data -> width_adapter_015:in_data
signal id_router_007_src_channel : std_logic_vector(7 downto 0); -- id_router_007:src_channel -> width_adapter_015:in_channel
signal id_router_007_src_ready : std_logic; -- width_adapter_015:in_ready -> id_router_007:src_ready
signal width_adapter_015_src_endofpacket : std_logic; -- width_adapter_015:out_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
signal width_adapter_015_src_valid : std_logic; -- width_adapter_015:out_valid -> rsp_xbar_demux_007:sink_valid
signal width_adapter_015_src_startofpacket : std_logic; -- width_adapter_015:out_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
signal width_adapter_015_src_data : std_logic_vector(69 downto 0); -- width_adapter_015:out_data -> rsp_xbar_demux_007:sink_data
signal width_adapter_015_src_ready : std_logic; -- rsp_xbar_demux_007:sink_ready -> width_adapter_015:out_ready
signal width_adapter_015_src_channel : std_logic_vector(7 downto 0); -- width_adapter_015:out_channel -> rsp_xbar_demux_007:sink_channel
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [EIM_Slave_to_Avalon_Master_0:isl_reset_n, dacad5668_0:isl_reset_n, fqd_interface_0:isl_reset_n, gpio_block_0:isl_reset_n, gpio_block_1:isl_reset_n, info_device_0:isl_reset_n, ppwa_block_0:isl_reset_n, pwm_interface_0:isl_reset_n, watchdog_block_0:isl_reset_n]
begin
altpll_0 : component cb20_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset
read => open, -- pll_slave.read
write => open, -- .write
address => open, -- .address
readdata => open, -- .readdata
writedata => open, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
info_device_0 : component info_device
generic map (
unique_id => "00010010011100000000000000000001",
description => "01100011011000100011001000110000001000000111011101101001011101000110100000100000011101110110010001110100001011000010000000110010001110000010111000110101001011100011001000110000001100100011000000000000000000000000000000000000",
dev_size => 1024
)
port map (
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
islv_avs_address => info_device_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_slave.address
isl_avs_read => info_device_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => info_device_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => info_device_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
oslv_avs_read_data => info_device_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
osl_avs_waitrequest => info_device_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => info_device_0_avalon_slave_translator_avalon_anti_slave_0_byteenable -- .byteenable
);
eim_slave_to_avalon_master_0 : component eim_slave_to_avalon_master
generic map (
TRANSFER_WIDTH => 16
)
port map (
ioslv_data => eim_slave_to_avalon_master_0_conduit_end_ioslv_data, -- conduit_end.export
isl_cs_n => eim_slave_to_avalon_master_0_conduit_end_isl_cs_n, -- .export
isl_oe_n => eim_slave_to_avalon_master_0_conduit_end_isl_oe_n, -- .export
isl_we_n => eim_slave_to_avalon_master_0_conduit_end_isl_we_n, -- .export
osl_data_ack => eim_slave_to_avalon_master_0_conduit_end_osl_data_ack, -- .export
islv_address => eim_slave_to_avalon_master_0_conduit_end_islv_address, -- .export
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
islv_readdata => eim_slave_to_avalon_master_0_avalon_master_readdata, -- avalon_master.readdata
islv_waitrequest => eim_slave_to_avalon_master_0_avalon_master_waitrequest, -- .waitrequest
oslv_address => eim_slave_to_avalon_master_0_avalon_master_address, -- .address
oslv_read => eim_slave_to_avalon_master_0_avalon_master_read, -- .read
oslv_write => eim_slave_to_avalon_master_0_avalon_master_write, -- .write
oslv_writedata => eim_slave_to_avalon_master_0_avalon_master_writedata -- .writedata
);
dacad5668_0 : component avalon_dacad5668_interface
generic map (
BASE_CLK => 200000000,
SCLK_FREQUENCY => 10000000,
INTERNAL_REFERENCE => '0',
UNIQUE_ID => "00010010011100000010000000000001"
)
port map (
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
osl_sclk => dacad5668_0_conduit_end_osl_sclk, -- conduit_end.export
oslv_Ss => dacad5668_0_conduit_end_oslv_Ss, -- .export
osl_mosi => dacad5668_0_conduit_end_osl_mosi, -- .export
osl_LDAC_n => dacad5668_0_conduit_end_osl_LDAC_n, -- .export
osl_CLR_n => dacad5668_0_conduit_end_osl_CLR_n, -- .export
islv_avs_address => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_slave.address
isl_avs_read => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
oslv_avs_read_data => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
osl_avs_waitrequest => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_byteenable -- .byteenable
);
fqd_interface_0 : component avalon_fqd_counter_interface
generic map (
number_of_fqds => 8,
unique_id => "00010010011100000110000000000001"
)
port map (
oslv_avs_read_data => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
isl_avs_read => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
islv_avs_address => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
osl_avs_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
islv_enc_B => fqd_interface_0_conduit_end_B, -- conduit_end.export
islv_enc_A => fqd_interface_0_conduit_end_A -- .export
);
gpio_block_0 : component cb20_gpio_block_0
generic map (
number_of_gpios => 9,
unique_id => "00010010011100000101000000000001"
)
port map (
oslv_avs_read_data => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
islv_avs_address => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
isl_avs_read => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
osl_avs_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_write_data => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
islv_avs_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
oslv_gpios => gpio_block_0_conduit_end_export -- conduit_end.export
);
pwm_interface_0 : component avalon_pwm_interface
generic map (
number_of_pwms => 4,
base_clk => 200000000,
unique_id => "00010010011100001100000000000001"
)
port map (
oslv_avs_read_data => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
islv_avs_address => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
isl_avs_read => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
osl_avs_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
oslv_pwm => pwm_interface_0_conduit_end_export -- conduit_end.export
);
gpio_block_1 : component cb20_gpio_block_1
generic map (
number_of_gpios => 8,
unique_id => "00010010011100000101000000000010"
)
port map (
oslv_avs_read_data => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
islv_avs_address => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
isl_avs_read => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
osl_avs_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_write_data => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
islv_avs_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
oslv_gpios => gpio_block_1_conduit_end_export -- conduit_end.export
);
watchdog_block_0 : component avalon_watchdog_interface
generic map (
base_clk => 200000000,
unique_id => "00010010011100010000000000000001"
)
port map (
islv_avs_write_data => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- avalon_slave_0.writedata
oslv_avs_read_data => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
isl_avs_write => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
isl_avs_read => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
islv_avs_address => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
osl_avs_waitrequest => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
osl_granted => watchdog_block_0_wd_signals_granted, -- wd_signals.export
osl_watchdog_pwm => watchdog_block_0_wd_signals_watchdog_pwm -- .export
);
ppwa_block_0 : component avalon_ppwa_interface
generic map (
number_of_ppwas => 2,
base_clk => 200000000,
unique_id => "00010010011100001101000000000001"
)
port map (
islv_avs_write_data => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- avalon_slave_0.writedata
oslv_avs_read_data => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
islv_avs_address => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
isl_avs_read => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
osl_avs_waitrequest => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
islv_signals_to_measure => ppwa_block_0_conduit_end_export -- conduit_end.export
);
eim_slave_to_avalon_master_0_avalon_master_translator : component altera_merlin_master_translator
generic map (
AV_ADDRESS_W => 16,
AV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 2,
USE_READ => 1,
USE_WRITE => 1,
USE_BEGINBURSTTRANSFER => 0,
USE_BEGINTRANSFER => 0,
USE_CHIPSELECT => 0,
USE_BURSTCOUNT => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_LINEWRAPBURSTS => 0,
AV_REGISTERINCOMINGSIGNALS => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_read, -- .read
uav_write => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => eim_slave_to_avalon_master_0_avalon_master_address, -- avalon_anti_master_0.address
av_waitrequest => eim_slave_to_avalon_master_0_avalon_master_waitrequest, -- .waitrequest
av_read => eim_slave_to_avalon_master_0_avalon_master_read, -- .read
av_readdata => eim_slave_to_avalon_master_0_avalon_master_readdata, -- .readdata
av_write => eim_slave_to_avalon_master_0_avalon_master_write, -- .write
av_writedata => eim_slave_to_avalon_master_0_avalon_master_writedata, -- .writedata
av_burstcount => "1", -- (terminated)
av_byteenable => "11", -- (terminated)
av_beginbursttransfer => '0', -- (terminated)
av_begintransfer => '0', -- (terminated)
av_chipselect => '0', -- (terminated)
av_readdatavalid => open, -- (terminated)
av_lock => '0', -- (terminated)
av_debugaccess => '0', -- (terminated)
uav_clken => open, -- (terminated)
av_clken => '1', -- (terminated)
uav_response => "00", -- (terminated)
av_response => open, -- (terminated)
uav_writeresponserequest => open, -- (terminated)
uav_writeresponsevalid => '0', -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
info_device_0_avalon_slave_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => info_device_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => info_device_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => info_device_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => info_device_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => info_device_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => info_device_0_avalon_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => info_device_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
dacad5668_0_avalon_slave_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
fqd_interface_0_avalon_slave_0_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
gpio_block_0_avalon_slave_0_translator : component cb20_gpio_block_0_avalon_slave_0_translator
generic map (
AV_ADDRESS_W => 4,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
pwm_interface_0_avalon_slave_0_translator : component cb20_pwm_interface_0_avalon_slave_0_translator
generic map (
AV_ADDRESS_W => 6,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
gpio_block_1_avalon_slave_0_translator : component cb20_gpio_block_0_avalon_slave_0_translator
generic map (
AV_ADDRESS_W => 4,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
watchdog_block_0_avalon_slave_0_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => watchdog_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
ppwa_block_0_avalon_slave_0_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => ppwa_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent
generic map (
PKT_PROTECTION_H => 63,
PKT_PROTECTION_L => 61,
PKT_BEGIN_BURST => 52,
PKT_BURSTWRAP_H => 44,
PKT_BURSTWRAP_L => 44,
PKT_BURST_SIZE_H => 47,
PKT_BURST_SIZE_L => 45,
PKT_BURST_TYPE_H => 49,
PKT_BURST_TYPE_L => 48,
PKT_BYTE_CNT_H => 43,
PKT_BYTE_CNT_L => 41,
PKT_ADDR_H => 34,
PKT_ADDR_L => 18,
PKT_TRANS_COMPRESSED_READ => 35,
PKT_TRANS_POSTED => 36,
PKT_TRANS_WRITE => 37,
PKT_TRANS_READ => 38,
PKT_TRANS_LOCK => 39,
PKT_TRANS_EXCLUSIVE => 40,
PKT_DATA_H => 15,
PKT_DATA_L => 0,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_SRC_ID_H => 56,
PKT_SRC_ID_L => 54,
PKT_DEST_ID_H => 59,
PKT_DEST_ID_L => 57,
PKT_THREAD_ID_H => 60,
PKT_THREAD_ID_L => 60,
PKT_CACHE_H => 67,
PKT_CACHE_L => 64,
PKT_DATA_SIDEBAND_H => 51,
PKT_DATA_SIDEBAND_L => 51,
PKT_QOS_H => 53,
PKT_QOS_L => 53,
PKT_ADDR_SIDEBAND_H => 50,
PKT_ADDR_SIDEBAND_L => 50,
PKT_RESPONSE_STATUS_H => 69,
PKT_RESPONSE_STATUS_L => 68,
ST_DATA_W => 70,
ST_CHANNEL_W => 8,
AV_BURSTCOUNT_W => 2,
SUPPRESS_0_BYTEEN_RSP => 1,
ID => 0,
BURSTWRAP_VALUE => 1,
CACHE_VALUE => 0,
SECURE_ACCESS_BIT => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
av_address => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_address, -- av.address
av_write => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_write, -- .write
av_read => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_src_data, -- .data
rp_channel => rsp_xbar_mux_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_src_ready, -- .ready
av_response => open, -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 8,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_src_ready, -- cp.ready
cp_valid => width_adapter_src_valid, -- .valid
cp_data => width_adapter_src_data, -- .data
cp_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_src_channel, -- .channel
rf_sink_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 8,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_002_src_ready, -- cp.ready
cp_valid => width_adapter_002_src_valid, -- .valid
cp_data => width_adapter_002_src_data, -- .data
cp_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_002_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_002_src_channel, -- .channel
rf_sink_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 8,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_004_src_ready, -- cp.ready
cp_valid => width_adapter_004_src_valid, -- .valid
cp_data => width_adapter_004_src_data, -- .data
cp_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_004_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_004_src_channel, -- .channel
rf_sink_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 8,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_006_src_ready, -- cp.ready
cp_valid => width_adapter_006_src_valid, -- .valid
cp_data => width_adapter_006_src_data, -- .data
cp_startofpacket => width_adapter_006_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_006_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_006_src_channel, -- .channel
rf_sink_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 8,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_008_src_ready, -- cp.ready
cp_valid => width_adapter_008_src_valid, -- .valid
cp_data => width_adapter_008_src_data, -- .data
cp_startofpacket => width_adapter_008_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_008_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_008_src_channel, -- .channel
rf_sink_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 8,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_010_src_ready, -- cp.ready
cp_valid => width_adapter_010_src_valid, -- .valid
cp_data => width_adapter_010_src_data, -- .data
cp_startofpacket => width_adapter_010_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_010_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_010_src_channel, -- .channel
rf_sink_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 8,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_012_src_ready, -- cp.ready
cp_valid => width_adapter_012_src_valid, -- .valid
cp_data => width_adapter_012_src_data, -- .data
cp_startofpacket => width_adapter_012_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_012_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_012_src_channel, -- .channel
rf_sink_ready => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 8,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_014_src_ready, -- cp.ready
cp_valid => width_adapter_014_src_valid, -- .valid
cp_data => width_adapter_014_src_data, -- .data
cp_startofpacket => width_adapter_014_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_014_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_014_src_channel, -- .channel
rf_sink_ready => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
addr_router : component cb20_addr_router
port map (
sink_ready => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_src_ready, -- src.ready
src_valid => addr_router_src_valid, -- .valid
src_data => addr_router_src_data, -- .data
src_channel => addr_router_src_channel, -- .channel
src_startofpacket => addr_router_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_src_endofpacket -- .endofpacket
);
id_router : component cb20_id_router
port map (
sink_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_src_ready, -- src.ready
src_valid => id_router_src_valid, -- .valid
src_data => id_router_src_data, -- .data
src_channel => id_router_src_channel, -- .channel
src_startofpacket => id_router_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_src_endofpacket -- .endofpacket
);
id_router_001 : component cb20_id_router
port map (
sink_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_001_src_ready, -- src.ready
src_valid => id_router_001_src_valid, -- .valid
src_data => id_router_001_src_data, -- .data
src_channel => id_router_001_src_channel, -- .channel
src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_001_src_endofpacket -- .endofpacket
);
id_router_002 : component cb20_id_router
port map (
sink_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_002_src_ready, -- src.ready
src_valid => id_router_002_src_valid, -- .valid
src_data => id_router_002_src_data, -- .data
src_channel => id_router_002_src_channel, -- .channel
src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_002_src_endofpacket -- .endofpacket
);
id_router_003 : component cb20_id_router
port map (
sink_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_003_src_ready, -- src.ready
src_valid => id_router_003_src_valid, -- .valid
src_data => id_router_003_src_data, -- .data
src_channel => id_router_003_src_channel, -- .channel
src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_003_src_endofpacket -- .endofpacket
);
id_router_004 : component cb20_id_router
port map (
sink_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_004_src_ready, -- src.ready
src_valid => id_router_004_src_valid, -- .valid
src_data => id_router_004_src_data, -- .data
src_channel => id_router_004_src_channel, -- .channel
src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_004_src_endofpacket -- .endofpacket
);
id_router_005 : component cb20_id_router
port map (
sink_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_005_src_ready, -- src.ready
src_valid => id_router_005_src_valid, -- .valid
src_data => id_router_005_src_data, -- .data
src_channel => id_router_005_src_channel, -- .channel
src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_005_src_endofpacket -- .endofpacket
);
id_router_006 : component cb20_id_router
port map (
sink_ready => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => watchdog_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_006_src_ready, -- src.ready
src_valid => id_router_006_src_valid, -- .valid
src_data => id_router_006_src_data, -- .data
src_channel => id_router_006_src_channel, -- .channel
src_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_006_src_endofpacket -- .endofpacket
);
id_router_007 : component cb20_id_router
port map (
sink_ready => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => ppwa_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_007_src_ready, -- src.ready
src_valid => id_router_007_src_valid, -- .valid
src_data => id_router_007_src_data, -- .data
src_channel => id_router_007_src_channel, -- .channel
src_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_007_src_endofpacket -- .endofpacket
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
cmd_xbar_demux : component cb20_cmd_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_src_ready, -- sink.ready
sink_channel => addr_router_src_channel, -- .channel
sink_data => addr_router_src_data, -- .data
sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_src_valid, -- .valid
src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_src0_valid, -- .valid
src0_data => cmd_xbar_demux_src0_data, -- .data
src0_channel => cmd_xbar_demux_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_src1_valid, -- .valid
src1_data => cmd_xbar_demux_src1_data, -- .data
src1_channel => cmd_xbar_demux_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_src2_valid, -- .valid
src2_data => cmd_xbar_demux_src2_data, -- .data
src2_channel => cmd_xbar_demux_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_src3_valid, -- .valid
src3_data => cmd_xbar_demux_src3_data, -- .data
src3_channel => cmd_xbar_demux_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_src4_valid, -- .valid
src4_data => cmd_xbar_demux_src4_data, -- .data
src4_channel => cmd_xbar_demux_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_src4_endofpacket, -- .endofpacket
src5_ready => cmd_xbar_demux_src5_ready, -- src5.ready
src5_valid => cmd_xbar_demux_src5_valid, -- .valid
src5_data => cmd_xbar_demux_src5_data, -- .data
src5_channel => cmd_xbar_demux_src5_channel, -- .channel
src5_startofpacket => cmd_xbar_demux_src5_startofpacket, -- .startofpacket
src5_endofpacket => cmd_xbar_demux_src5_endofpacket, -- .endofpacket
src6_ready => cmd_xbar_demux_src6_ready, -- src6.ready
src6_valid => cmd_xbar_demux_src6_valid, -- .valid
src6_data => cmd_xbar_demux_src6_data, -- .data
src6_channel => cmd_xbar_demux_src6_channel, -- .channel
src6_startofpacket => cmd_xbar_demux_src6_startofpacket, -- .startofpacket
src6_endofpacket => cmd_xbar_demux_src6_endofpacket, -- .endofpacket
src7_ready => cmd_xbar_demux_src7_ready, -- src7.ready
src7_valid => cmd_xbar_demux_src7_valid, -- .valid
src7_data => cmd_xbar_demux_src7_data, -- .data
src7_channel => cmd_xbar_demux_src7_channel, -- .channel
src7_startofpacket => cmd_xbar_demux_src7_startofpacket, -- .startofpacket
src7_endofpacket => cmd_xbar_demux_src7_endofpacket -- .endofpacket
);
rsp_xbar_demux : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_001_src_ready, -- sink.ready
sink_channel => width_adapter_001_src_channel, -- .channel
sink_data => width_adapter_001_src_data, -- .data
sink_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_001_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_src0_valid, -- .valid
src0_data => rsp_xbar_demux_src0_data, -- .data
src0_channel => rsp_xbar_demux_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_001 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_003_src_ready, -- sink.ready
sink_channel => width_adapter_003_src_channel, -- .channel
sink_data => width_adapter_003_src_data, -- .data
sink_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_003_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_003_src_valid, -- .valid
src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid
src0_data => rsp_xbar_demux_001_src0_data, -- .data
src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_002 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_005_src_ready, -- sink.ready
sink_channel => width_adapter_005_src_channel, -- .channel
sink_data => width_adapter_005_src_data, -- .data
sink_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_005_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
src0_data => rsp_xbar_demux_002_src0_data, -- .data
src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_003 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_007_src_ready, -- sink.ready
sink_channel => width_adapter_007_src_channel, -- .channel
sink_data => width_adapter_007_src_data, -- .data
sink_startofpacket => width_adapter_007_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_007_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_007_src_valid, -- .valid
src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid
src0_data => rsp_xbar_demux_003_src0_data, -- .data
src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_004 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_009_src_ready, -- sink.ready
sink_channel => width_adapter_009_src_channel, -- .channel
sink_data => width_adapter_009_src_data, -- .data
sink_startofpacket => width_adapter_009_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_009_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_009_src_valid, -- .valid
src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid
src0_data => rsp_xbar_demux_004_src0_data, -- .data
src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_005 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_011_src_ready, -- sink.ready
sink_channel => width_adapter_011_src_channel, -- .channel
sink_data => width_adapter_011_src_data, -- .data
sink_startofpacket => width_adapter_011_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_011_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_011_src_valid, -- .valid
src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid
src0_data => rsp_xbar_demux_005_src0_data, -- .data
src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_006 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_013_src_ready, -- sink.ready
sink_channel => width_adapter_013_src_channel, -- .channel
sink_data => width_adapter_013_src_data, -- .data
sink_startofpacket => width_adapter_013_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_013_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_013_src_valid, -- .valid
src0_ready => rsp_xbar_demux_006_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_006_src0_valid, -- .valid
src0_data => rsp_xbar_demux_006_src0_data, -- .data
src0_channel => rsp_xbar_demux_006_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_006_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_007 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_015_src_ready, -- sink.ready
sink_channel => width_adapter_015_src_channel, -- .channel
sink_data => width_adapter_015_src_data, -- .data
sink_startofpacket => width_adapter_015_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_015_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_015_src_valid, -- .valid
src0_ready => rsp_xbar_demux_007_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_007_src0_valid, -- .valid
src0_data => rsp_xbar_demux_007_src0_data, -- .data
src0_channel => rsp_xbar_demux_007_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_007_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux : component cb20_rsp_xbar_mux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_src_ready, -- src.ready
src_valid => rsp_xbar_mux_src_valid, -- .valid
src_data => rsp_xbar_mux_src_data, -- .data
src_channel => rsp_xbar_mux_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src0_valid, -- .valid
sink0_channel => rsp_xbar_demux_src0_channel, -- .channel
sink0_data => rsp_xbar_demux_src0_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src0_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src0_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src0_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src0_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src0_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src0_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src0_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src0_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src0_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src0_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
sink4_ready => rsp_xbar_demux_004_src0_ready, -- sink4.ready
sink4_valid => rsp_xbar_demux_004_src0_valid, -- .valid
sink4_channel => rsp_xbar_demux_004_src0_channel, -- .channel
sink4_data => rsp_xbar_demux_004_src0_data, -- .data
sink4_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
sink4_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket
sink5_ready => rsp_xbar_demux_005_src0_ready, -- sink5.ready
sink5_valid => rsp_xbar_demux_005_src0_valid, -- .valid
sink5_channel => rsp_xbar_demux_005_src0_channel, -- .channel
sink5_data => rsp_xbar_demux_005_src0_data, -- .data
sink5_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
sink5_endofpacket => rsp_xbar_demux_005_src0_endofpacket, -- .endofpacket
sink6_ready => rsp_xbar_demux_006_src0_ready, -- sink6.ready
sink6_valid => rsp_xbar_demux_006_src0_valid, -- .valid
sink6_channel => rsp_xbar_demux_006_src0_channel, -- .channel
sink6_data => rsp_xbar_demux_006_src0_data, -- .data
sink6_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
sink6_endofpacket => rsp_xbar_demux_006_src0_endofpacket, -- .endofpacket
sink7_ready => rsp_xbar_demux_007_src0_ready, -- sink7.ready
sink7_valid => rsp_xbar_demux_007_src0_valid, -- .valid
sink7_channel => rsp_xbar_demux_007_src0_channel, -- .channel
sink7_data => rsp_xbar_demux_007_src0_data, -- .data
sink7_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
sink7_endofpacket => rsp_xbar_demux_007_src0_endofpacket -- .endofpacket
);
width_adapter : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src0_valid, -- sink.valid
in_channel => cmd_xbar_demux_src0_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src0_ready, -- .ready
in_data => cmd_xbar_demux_src0_data, -- .data
out_endofpacket => width_adapter_src_endofpacket, -- src.endofpacket
out_data => width_adapter_src_data, -- .data
out_channel => width_adapter_src_channel, -- .channel
out_valid => width_adapter_src_valid, -- .valid
out_ready => width_adapter_src_ready, -- .ready
out_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_001 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_src_valid, -- sink.valid
in_channel => id_router_src_channel, -- .channel
in_startofpacket => id_router_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_src_endofpacket, -- .endofpacket
in_ready => id_router_src_ready, -- .ready
in_data => id_router_src_data, -- .data
out_endofpacket => width_adapter_001_src_endofpacket, -- src.endofpacket
out_data => width_adapter_001_src_data, -- .data
out_channel => width_adapter_001_src_channel, -- .channel
out_valid => width_adapter_001_src_valid, -- .valid
out_ready => width_adapter_001_src_ready, -- .ready
out_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_002 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src1_valid, -- sink.valid
in_channel => cmd_xbar_demux_src1_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src1_ready, -- .ready
in_data => cmd_xbar_demux_src1_data, -- .data
out_endofpacket => width_adapter_002_src_endofpacket, -- src.endofpacket
out_data => width_adapter_002_src_data, -- .data
out_channel => width_adapter_002_src_channel, -- .channel
out_valid => width_adapter_002_src_valid, -- .valid
out_ready => width_adapter_002_src_ready, -- .ready
out_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_003 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_001_src_valid, -- sink.valid
in_channel => id_router_001_src_channel, -- .channel
in_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_001_src_endofpacket, -- .endofpacket
in_ready => id_router_001_src_ready, -- .ready
in_data => id_router_001_src_data, -- .data
out_endofpacket => width_adapter_003_src_endofpacket, -- src.endofpacket
out_data => width_adapter_003_src_data, -- .data
out_channel => width_adapter_003_src_channel, -- .channel
out_valid => width_adapter_003_src_valid, -- .valid
out_ready => width_adapter_003_src_ready, -- .ready
out_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_004 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src2_valid, -- sink.valid
in_channel => cmd_xbar_demux_src2_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src2_ready, -- .ready
in_data => cmd_xbar_demux_src2_data, -- .data
out_endofpacket => width_adapter_004_src_endofpacket, -- src.endofpacket
out_data => width_adapter_004_src_data, -- .data
out_channel => width_adapter_004_src_channel, -- .channel
out_valid => width_adapter_004_src_valid, -- .valid
out_ready => width_adapter_004_src_ready, -- .ready
out_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_005 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_002_src_valid, -- sink.valid
in_channel => id_router_002_src_channel, -- .channel
in_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_002_src_endofpacket, -- .endofpacket
in_ready => id_router_002_src_ready, -- .ready
in_data => id_router_002_src_data, -- .data
out_endofpacket => width_adapter_005_src_endofpacket, -- src.endofpacket
out_data => width_adapter_005_src_data, -- .data
out_channel => width_adapter_005_src_channel, -- .channel
out_valid => width_adapter_005_src_valid, -- .valid
out_ready => width_adapter_005_src_ready, -- .ready
out_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_006 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src3_valid, -- sink.valid
in_channel => cmd_xbar_demux_src3_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src3_ready, -- .ready
in_data => cmd_xbar_demux_src3_data, -- .data
out_endofpacket => width_adapter_006_src_endofpacket, -- src.endofpacket
out_data => width_adapter_006_src_data, -- .data
out_channel => width_adapter_006_src_channel, -- .channel
out_valid => width_adapter_006_src_valid, -- .valid
out_ready => width_adapter_006_src_ready, -- .ready
out_startofpacket => width_adapter_006_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_007 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_003_src_valid, -- sink.valid
in_channel => id_router_003_src_channel, -- .channel
in_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_003_src_endofpacket, -- .endofpacket
in_ready => id_router_003_src_ready, -- .ready
in_data => id_router_003_src_data, -- .data
out_endofpacket => width_adapter_007_src_endofpacket, -- src.endofpacket
out_data => width_adapter_007_src_data, -- .data
out_channel => width_adapter_007_src_channel, -- .channel
out_valid => width_adapter_007_src_valid, -- .valid
out_ready => width_adapter_007_src_ready, -- .ready
out_startofpacket => width_adapter_007_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_008 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src4_valid, -- sink.valid
in_channel => cmd_xbar_demux_src4_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src4_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src4_ready, -- .ready
in_data => cmd_xbar_demux_src4_data, -- .data
out_endofpacket => width_adapter_008_src_endofpacket, -- src.endofpacket
out_data => width_adapter_008_src_data, -- .data
out_channel => width_adapter_008_src_channel, -- .channel
out_valid => width_adapter_008_src_valid, -- .valid
out_ready => width_adapter_008_src_ready, -- .ready
out_startofpacket => width_adapter_008_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_009 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_004_src_valid, -- sink.valid
in_channel => id_router_004_src_channel, -- .channel
in_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_004_src_endofpacket, -- .endofpacket
in_ready => id_router_004_src_ready, -- .ready
in_data => id_router_004_src_data, -- .data
out_endofpacket => width_adapter_009_src_endofpacket, -- src.endofpacket
out_data => width_adapter_009_src_data, -- .data
out_channel => width_adapter_009_src_channel, -- .channel
out_valid => width_adapter_009_src_valid, -- .valid
out_ready => width_adapter_009_src_ready, -- .ready
out_startofpacket => width_adapter_009_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_010 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src5_valid, -- sink.valid
in_channel => cmd_xbar_demux_src5_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src5_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src5_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src5_ready, -- .ready
in_data => cmd_xbar_demux_src5_data, -- .data
out_endofpacket => width_adapter_010_src_endofpacket, -- src.endofpacket
out_data => width_adapter_010_src_data, -- .data
out_channel => width_adapter_010_src_channel, -- .channel
out_valid => width_adapter_010_src_valid, -- .valid
out_ready => width_adapter_010_src_ready, -- .ready
out_startofpacket => width_adapter_010_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_011 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_005_src_valid, -- sink.valid
in_channel => id_router_005_src_channel, -- .channel
in_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_005_src_endofpacket, -- .endofpacket
in_ready => id_router_005_src_ready, -- .ready
in_data => id_router_005_src_data, -- .data
out_endofpacket => width_adapter_011_src_endofpacket, -- src.endofpacket
out_data => width_adapter_011_src_data, -- .data
out_channel => width_adapter_011_src_channel, -- .channel
out_valid => width_adapter_011_src_valid, -- .valid
out_ready => width_adapter_011_src_ready, -- .ready
out_startofpacket => width_adapter_011_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_012 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src6_valid, -- sink.valid
in_channel => cmd_xbar_demux_src6_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src6_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src6_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src6_ready, -- .ready
in_data => cmd_xbar_demux_src6_data, -- .data
out_endofpacket => width_adapter_012_src_endofpacket, -- src.endofpacket
out_data => width_adapter_012_src_data, -- .data
out_channel => width_adapter_012_src_channel, -- .channel
out_valid => width_adapter_012_src_valid, -- .valid
out_ready => width_adapter_012_src_ready, -- .ready
out_startofpacket => width_adapter_012_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_013 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_006_src_valid, -- sink.valid
in_channel => id_router_006_src_channel, -- .channel
in_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_006_src_endofpacket, -- .endofpacket
in_ready => id_router_006_src_ready, -- .ready
in_data => id_router_006_src_data, -- .data
out_endofpacket => width_adapter_013_src_endofpacket, -- src.endofpacket
out_data => width_adapter_013_src_data, -- .data
out_channel => width_adapter_013_src_channel, -- .channel
out_valid => width_adapter_013_src_valid, -- .valid
out_ready => width_adapter_013_src_ready, -- .ready
out_startofpacket => width_adapter_013_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_014 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src7_valid, -- sink.valid
in_channel => cmd_xbar_demux_src7_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src7_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src7_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src7_ready, -- .ready
in_data => cmd_xbar_demux_src7_data, -- .data
out_endofpacket => width_adapter_014_src_endofpacket, -- src.endofpacket
out_data => width_adapter_014_src_data, -- .data
out_channel => width_adapter_014_src_channel, -- .channel
out_valid => width_adapter_014_src_valid, -- .valid
out_ready => width_adapter_014_src_ready, -- .ready
out_startofpacket => width_adapter_014_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_015 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 8,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_007_src_valid, -- sink.valid
in_channel => id_router_007_src_channel, -- .channel
in_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_007_src_endofpacket, -- .endofpacket
in_ready => id_router_007_src_ready, -- .ready
in_data => id_router_007_src_data, -- .data
out_endofpacket => width_adapter_015_src_endofpacket, -- src.endofpacket
out_data => width_adapter_015_src_data, -- .data
out_channel => width_adapter_015_src_channel, -- .channel
out_valid => width_adapter_015_src_valid, -- .valid
out_ready => width_adapter_015_src_ready, -- .ready
out_startofpacket => width_adapter_015_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
end architecture rtl; -- of cb20
| apache-2.0 | 219fc49d76ae275ed333698b168c862f | 0.497326 | 3.955773 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/token_crc_check.vhd | 2 | 1,986 | -------------------------------------------------------------------------------
-- Title : token_crc_check.vhd
-------------------------------------------------------------------------------
-- File : token_crc_check.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB data
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_check is
port (
clock : in std_logic;
sync : in std_logic;
valid : in std_logic;
data_in : in std_logic_vector(7 downto 0);
crc : out std_logic_vector(4 downto 0) );
end token_crc_check;
architecture Gideon of token_crc_check is
constant polynom : std_logic_vector(4 downto 0) := "00100";
signal crc_reg : std_logic_vector(polynom'range);
-- CRC-5 = x5 + x2 + 1
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
if sync = '1' then
crc_reg <= (others => '1');
elsif valid = '1' then
tmp := crc_reg;
for i in data_in'reverse_range loop -- LSB first!
d := data_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & d;
if d = '1' then
tmp := tmp xor polynom;
end if;
end loop;
crc_reg <= tmp;
end if;
end if;
end process;
process(crc_reg)
begin
for i in crc_reg'range loop -- reverse and invert
crc(crc'high-i) <= not(crc_reg(i));
end loop;
end process;
end Gideon;
| gpl-3.0 | 7d9b3f92fc2c24425838104274c7876f | 0.415911 | 4.308026 | false | false | false | false |
chiggs/nvc | test/bounds/bounds.vhd | 1 | 4,167 | entity bounds is
end entity;
architecture test of bounds is
type foo is range 1 to 5;
type my_vec1 is array (positive range <>) of integer;
type my_vec2 is array (foo range <>) of integer;
signal s : my_vec1(1 to 10);
signal n : my_vec1(1 downto 10);
subtype bool_true is boolean range true to true;
function fun(x : in bit_vector(7 downto 0)) return bit;
procedure proc(x : in bit_vector(7 downto 0));
function natfunc(x : in natural) return boolean;
function enumfunc(x : in bool_true) return boolean;
function realfunc(x : in real) return boolean;
type matrix is array (integer range <>, integer range <>) of integer;
procedure proc2(x : in matrix(1 to 3, 1 to 3));
begin
process is
variable a : my_vec1(0 to 10); -- Error
variable b : my_vec2(1 to 60); -- Error
begin
end process;
s(-52) <= 5; -- Error
s(1 to 11) <= (others => 0); -- Error
s(0 to 2) <= (others => 0); -- Error
process is
begin
report (0 => 'a'); -- Error
end process;
process is
variable v1 : bit_vector(3 downto 0);
variable v2 : bit_vector(8 downto 1);
variable m1 : matrix(1 to 3, 2 to 4);
variable m2 : matrix(1 to 3, 1 to 4);
begin
assert fun(v1) = '1'; -- Error
proc(v1); -- Error
proc(v2); -- OK
proc2(m1); -- OK
proc2(m2); -- Error
end process;
s <= s(1 to 9); -- Error
n <= s(1 to 2); -- Error
n <= (1, 2, 3); -- Error
process is
variable v : my_vec1(1 to 3);
begin
v := s; -- Error
end process;
process is
variable x : integer;
begin
x := s(11); -- Error!
x := s(-1); -- Error!
end process;
process is
variable a : my_vec1(1 to 3);
begin
a := (1, 2, 3); -- OK
a := (5 => 1, 1 => 2, 0 => 3); -- Error
end process;
process is
subtype alpha is character range 'a' to 'z';
variable a : alpha;
variable p : positive;
begin
a := 'c'; -- OK
a := '1'; -- Error
p := 0; -- Error
end process;
process is
begin
assert s'length(5) = 5; -- Error
end process;
process is
begin
assert natfunc(-1); -- Error
end process;
process is
subtype str is string;
constant c : str := "hello"; -- OK
begin
end process;
process is
variable a : my_vec1(1 to 3);
begin
a := (1, others => 2); -- OK
a := (5 => 1, others => 2); -- Error
end process;
process is
type mat2d is array (integer range <>, integer range <>)
of integer;
procedure p(m : in mat2d);
begin
p(((0, 1, 2, 3), (1 to 2 => 5))); -- Error
end process;
-- Reduced from Billowitch tc1374
process is
type t_rec3 is record
f1 : boolean;
end record;
subtype st_rec3 is t_rec3 ;
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype st_arr3 is t_arr3 (1 to 5, true downto false) ;
variable v_st_arr3 : st_arr3;
begin
v_st_arr3(1, true) := (f1 => false);
end process;
process is
variable i : integer;
attribute a : bit_vector;
attribute a of i : variable is "101";
begin
assert i'a(14) = '0'; -- Error
end process;
process is
constant FPO_LOG_MAX_ITERATIONS : integer := 9;
type T_FPO_LOG_ALPHA is array (0 to FPO_LOG_MAX_ITERATIONS-1) of integer;
variable alpha : T_FPO_LOG_ALPHA;
begin
if alpha(0 to 5) = (5, 4, 6, 6, 6, 6) then -- OK
null;
end if;
end process;
end architecture;
| gpl-3.0 | a16306ac483a294b7bf9a3ea1e745493 | 0.474442 | 3.819432 | false | false | false | false |
chiggs/nvc | test/regress/driver1.vhd | 5 | 1,222 | entity driver1 is
end entity;
architecture test of driver1 is
type u is (A, B, C);
type uv is array (natural range <>) of u;
function func (x : uv) return u is
begin
--report "func called";
for i in x'range loop
-- report u'image(x(i));
end loop;
for i in x'range loop
if x(i) = A then
return A;
end if;
end loop;
return B;
end function;
subtype r is func u;
signal s : r := B;
signal k : r := C;
begin
one: process is
begin
assert s = B;
s <= A;
wait for 1 ns;
assert s = A;
s <= B;
wait for 1 ns;
assert s = B;
null;
wait for 1 ns;
assert s = A;
wait;
end process;
two: process is
begin
assert s = B;
s <= B;
wait for 1 ns;
assert s = A;
null;
wait for 1 ns;
assert s = B;
s <= A;
wait for 1 ns;
assert s = A;
wait;
end process;
three: process is
begin
k <= C;
wait for 1 ns;
assert k = B;
wait;
end process;
end architecture;
| gpl-3.0 | 44ca5a1b77399ca67d8e139724e4b2e2 | 0.442717 | 3.81875 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/ddr2_ctrl.vhd | 1 | 16,576 | -------------------------------------------------------------------------------
-- Title : External Memory controller for DDR2 SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (single beat), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ddr2_ctrl is
generic (
SDRAM_Refr_delay : integer := 7;
SDRAM_Refr_period : integer := 488 );
port (
ref_clock : in std_logic := '0';
ref_reset : in std_logic := '0';
sys_clock_o : out std_logic;
sys_reset_o : out std_logic;
user_clock_1 : out std_logic := '0';
user_clock_2 : out std_logic := '0';
user_clock_3 : out std_logic := '0';
clock : in std_logic := '0';
reset : in std_logic := '0';
io_req : in t_io_req;
io_resp : out t_io_resp;
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req_32;
resp : out t_mem_resp_32;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
-- command group
SDRAM_CKE : out std_logic := '0'; -- bit 5
SDRAM_ODT : out std_logic := '0';
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1'; -- bit 0
-- address group
SDRAM_A : out std_logic_vector(13 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
-- data group
SDRAM_DM : inout std_logic := 'Z';
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
-- dqs
SDRAM_DQS : inout std_logic := 'Z');
end entity;
-- 16 + 6 = 22 address/command timing
-- 8 + 1 = 9 data timing
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ddr2_ctrl is
constant c_cmd_inactive : std_logic_vector(3 downto 0) := "1111";
constant c_cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant c_cmd_active : std_logic_vector(3 downto 0) := "0011";
constant c_cmd_read : std_logic_vector(3 downto 0) := "0101";
constant c_cmd_write : std_logic_vector(3 downto 0) := "0100";
constant c_cmd_bterm : std_logic_vector(3 downto 0) := "0110";
constant c_cmd_precharge : std_logic_vector(3 downto 0) := "0010";
constant c_cmd_refresh : std_logic_vector(3 downto 0) := "0001";
constant c_cmd_mode_reg : std_logic_vector(3 downto 0) := "0000";
type t_state is (idle, sd_read, sd_write, sd_write_2, delay_1, delay_2);
type t_output is record
sdram_cmd : std_logic_vector(3 downto 0);
sdram_odt : std_logic;
sdram_cke : std_logic;
sdram_a : std_logic_vector(13 downto 0);
sdram_ba : std_logic_vector(1 downto 0);
write : std_logic;
wmask : std_logic_vector(3 downto 0);
wdata : std_logic_vector(31 downto 0);
end record;
type t_internal_state is record
state : t_state;
col_addr : std_logic_vector(9 downto 0);
bank_addr : std_logic_vector(1 downto 0);
refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
refr_delay : integer range 0 to SDRAM_Refr_delay-1;
delay : integer range 0 to 7;
do_refresh : std_logic;
refresh_inhibit : std_logic;
tag : std_logic_vector(req.tag'range);
rack : std_logic;
rack_tag : std_logic_vector(req.tag'range);
wmask : std_logic_vector(3 downto 0);
wdata : std_logic_vector(31 downto 0);
end record;
constant c_internal_state_init : t_internal_state := (
state => idle,
col_addr => (others => '0'),
bank_addr => (others => '0'),
refresh_cnt => 0,
refr_delay => SDRAM_Refr_delay-1,
delay => 7,
do_refresh => '0',
refresh_inhibit => '0',
tag => (others => '0'),
rack => '0',
rack_tag => (others => '0'),
wmask => (others => '0'),
wdata => (others => '0')
);
type t_tag_array is array(natural range <>) of std_logic_vector(req.tag'range);
signal dack_pipe : t_tag_array(4 downto 0) := (others => (others => '0'));
signal outp : t_output;
signal cur : t_internal_state := c_internal_state_init;
signal nxt : t_internal_state;
signal phasecounterselect : std_logic_vector(2 downto 0);
signal phasestep : std_logic_vector(3 downto 0);
signal phaseupdown : std_logic;
signal phasedone : std_logic;
signal mode : std_logic_vector(1 downto 0);
signal addr_first : std_logic_vector(21 downto 0);
signal addr_second : std_logic_vector(21 downto 0);
signal phy_wdata : std_logic_vector(35 downto 0);
signal phy_rdata : std_logic_vector(35 downto 0);
signal phy_write : std_logic;
signal enable_sdram : std_logic;
signal rdata : std_logic_vector(31 downto 0);
signal do_read : std_logic;
signal ext_addr : std_logic_vector(15 downto 0);
signal ext_cmd : std_logic_vector(3 downto 0);
signal ext_cmd_valid : std_logic;
signal ext_cmd_done : std_logic;
begin
is_idle <= '1' when cur.state = idle else '0';
resp.data <= rdata;
resp.rack <= nxt.rack; -- was cur
resp.rack_tag <= nxt.rack_tag; -- was cur
resp.dack_tag <= dack_pipe(dack_pipe'high);
process(req, inhibit, cur, ext_cmd, ext_cmd_valid, ext_addr, enable_sdram)
procedure send_refresh_cmd is
begin
outp.sdram_cmd <= c_cmd_refresh;
nxt.do_refresh <= '0';
nxt.refr_delay <= SDRAM_Refr_delay - 1;
end procedure;
procedure accept_req is
begin
nxt.rack <= '1';
nxt.rack_tag <= req.tag;
nxt.tag <= req.tag;
nxt.wdata <= req.data;
nxt.wmask <= not req.byte_en;
nxt.col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
nxt.bank_addr <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
outp.sdram_ba <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
outp.sdram_a <= std_logic_vector(req.address(25 downto 12)); -- 14 row bits
outp.sdram_cmd <= c_cmd_active;
end procedure;
begin
nxt <= cur; -- default no change
nxt.rack <= '0';
nxt.rack_tag <= (others => '0');
outp.sdram_cmd <= c_cmd_inactive;
outp.sdram_cke <= enable_sdram;
outp.sdram_odt <= enable_sdram;
outp.sdram_ba <= (others => 'X');
outp.sdram_a <= (others => 'X');
outp.wmask <= "0000";
outp.write <= '0';
outp.wdata <= (others => 'X');
ext_cmd_done <= '0';
do_read <= '0';
if cur.refr_delay /= 0 then
nxt.refr_delay <= cur.refr_delay - 1;
end if;
if cur.delay /= 0 then
nxt.delay <= cur.delay - 1;
end if;
if inhibit='1' then
nxt.refresh_inhibit <= '1';
end if;
case cur.state is
when idle =>
-- first cycle after inhibit goes 1, should not be a refresh
-- this enables putting cartridge images in sdram, because we guarantee the first access after inhibit to be a cart cycle
if cur.do_refresh='1' and cur.refresh_inhibit='0' then
send_refresh_cmd;
elsif ext_cmd_valid = '1' and cur.refr_delay = 0 then
outp.sdram_cmd <= ext_cmd;
outp.sdram_a <= ext_addr(13 downto 0);
outp.sdram_ba <= ext_addr(15 downto 14);
ext_cmd_done <= '1';
nxt.state <= delay_1;
elsif inhibit='0' then -- make sure we are allowed to start a new cycle
nxt.refresh_inhibit <= '0';
if req.request='1' and cur.refr_delay = 0 then
accept_req;
if req.read_writen = '1' then
nxt.state <= sd_read;
else
nxt.state <= sd_write;
end if;
end if;
end if;
when sd_read =>
outp.sdram_ba <= cur.bank_addr;
outp.sdram_a(13 downto 11) <= "000";
outp.sdram_a(10) <= '1'; -- auto precharge
outp.sdram_a(9 downto 0) <= cur.col_addr;
outp.sdram_cmd <= c_cmd_read;
do_read <= '1';
nxt.state <= delay_1;
when delay_1 =>
nxt.state <= delay_2;
when delay_2 =>
nxt.state <= idle;
when sd_write =>
outp.sdram_ba <= cur.bank_addr;
outp.sdram_a(13 downto 11) <= "000";
outp.sdram_a(10) <= '1'; -- auto precharge
outp.sdram_a(9 downto 0) <= cur.col_addr;
outp.sdram_cmd <= c_cmd_write;
outp.wdata <= (others => '0');
outp.wmask <= (others => '0');
nxt.state <= sd_write_2;
when sd_write_2 =>
outp.wdata <= cur.wdata;
outp.wmask <= cur.wmask;
outp.write <= '1';
nxt.state <= delay_1;
when others =>
null;
end case;
if cur.refresh_cnt = SDRAM_Refr_period-1 then
nxt.do_refresh <= '1';
nxt.refresh_cnt <= 0;
else
nxt.refresh_cnt <= cur.refresh_cnt + 1;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
cur <= nxt;
if do_read = '1' then
dack_pipe(0) <= cur.tag;
else
dack_pipe(0) <= (others => '0');
end if;
dack_pipe(dack_pipe'high downto 1) <= dack_pipe(dack_pipe'high-1 downto 0);
addr_first <= outp.sdram_cke & outp.sdram_odt & outp.sdram_cmd & outp.sdram_ba & outp.sdram_a;
addr_second <= outp.sdram_cke & outp.sdram_odt & "1111" & outp.sdram_ba & outp.sdram_a;
phy_wdata <= outp.wmask(3) & outp.wdata(31 downto 24) &
outp.wmask(2) & outp.wdata(23 downto 16) &
outp.wmask(1) & outp.wdata(15 downto 08) &
outp.wmask(0) & outp.wdata(07 downto 00);
phy_write <= outp.write;
if reset='1' then
cur <= c_internal_state_init;
end if;
end if;
end process;
rdata <= phy_rdata(34 downto 27) & phy_rdata(25 downto 18) & phy_rdata(16 downto 9) & phy_rdata(7 downto 0);
i_phy: entity work.mem_io
generic map (
g_data_width => 9,
g_addr_cmd_width => 22
)
port map(
ref_clock => ref_clock,
ref_reset => ref_reset,
sys_clock => sys_clock_o,
sys_reset => sys_reset_o,
phasecounterselect => phasecounterselect,
phasestep => phasestep(0),
phaseupdown => phaseupdown,
phasedone => phasedone,
mode => mode,
addr_first => addr_first,
addr_second => addr_second,
wdata => phy_wdata,
wdata_oe => phy_write,
rdata => phy_rdata,
user_clock_1 => user_clock_1,
user_clock_2 => user_clock_2,
user_clock_3 => user_clock_3,
mem_clk_p => SDRAM_CLK,
mem_clk_n => SDRAM_CLKn,
mem_addr(21) => SDRAM_CKE,
mem_addr(20) => SDRAM_ODT,
mem_addr(19) => SDRAM_CSn,
mem_addr(18) => SDRAM_RASn,
mem_addr(17) => SDRAM_CASn,
mem_addr(16) => SDRAM_WEn,
mem_addr(15 downto 14) => SDRAM_BA,
mem_addr(13 downto 0) => SDRAM_A,
mem_dqs => SDRAM_DQS,
mem_dq(8) => SDRAM_DM,
mem_dq(7 downto 0) => SDRAM_DQ
);
-- peripheral registers
process(clock)
variable local : unsigned(3 downto 0);
begin
if rising_edge(clock) then
local := io_req.address(3 downto 0);
io_resp <= c_io_resp_init;
if ext_cmd_done = '1' then
ext_cmd_valid <= '0';
end if;
phasestep <= '0' & phasestep(3 downto 1);
if io_req.read = '1' then
io_resp.ack <= '1';
case local is
when X"5" =>
io_resp.data(0) <= phasedone;
when others =>
null;
end case;
end if;
if io_req.write = '1' then
io_resp.ack <= '1';
case local is
when X"0" =>
ext_addr(7 downto 0) <= io_req.data;
when X"1" =>
ext_addr(15 downto 8) <= io_req.data;
when X"2" =>
ext_cmd <= io_req.data(3 downto 0);
ext_cmd_valid <= '1';
when X"8" =>
mode <= io_req.data(1 downto 0);
when X"9" =>
phasecounterselect <= io_req.data(2 downto 0);
phaseupdown <= io_req.data(3);
phasestep <= io_req.data(7 downto 4);
when X"C" =>
enable_sdram <= io_req.data(0);
when others =>
null;
end case;
end if;
if reset = '1' then
mode <= "00";
enable_sdram <= '0';
phasecounterselect <= "000";
phaseupdown <= '0';
phasestep <= (others => '0');
ext_cmd_valid <= '0';
end if;
end if;
end process;
end Gideon;
-- 125 MHz
-- ACT to READ: tRCD = 15 ns ( = 2 CLKs (16))
-- ACT to PRCH: tRAS = 40 ns ( = 5 CLKs (40))
-- ACT to ACT: tRC = 55 ns ( = 7 CLKs (56))
-- ACT to ACTb: tRRD = 7.5ns ( = 1 CLKs (8))
-- PRCH time; tRP = 15 ns ( = 2 CLKs (16))
-- wr. recov. tWR = 15 ns ( = 2 CLKs (16)) (starting from last data word)
-- CL=3
-- 0 1 2 3 4 5 6 7 8 9
-- BL4 A - R - p - - -
-- - - - - - DDDD-
-- BL4W A - W - - - - - - -
-- - - - - DDDD- - p -
-- Conclusion: In order to meet tRC, without checking for the bank, we always need 7 clks => 8 clks.
-- It also turns out that write with precharge needs a cycle time of 5 system ticks (10x8 ns) => 80 ns
-- Reads can be done faster; with 8 clocks for each access (4 system clocks) => 64 ns.
-- Reads in a 8-ticks stramine will result in a 25% bus utilization. (62.5 MB/s)
-- Note that both reads as well as writes can be issued 2 system clocks after one another IF
-- the bank bits are different! This will yield a bus utilization of 50% (125 MB/s)
-- CL=3
-- 0 1 2 3 4 5 6 7 8 9
-- BL4 A - R - p - - -
-- - - - - - DDDD-
-- - - - - A - R - p - - -
-- - - - - - - - - - DDDD-
--
-- BL4W A - W - - - - - - -
-- - - - - DDDD- - p -
-- - - - - A - W - - - - - - -
-- - - - - - - - - DDDD- - p -
| gpl-3.0 | b1b30b3dd9020f50680270853a5a1909 | 0.456805 | 3.690937 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/proc_control.vhd | 1 | 18,437 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
entity proc_control is
generic (
g_no_halt : boolean := false );
port (
clock : in std_logic;
clock_en : in std_logic;
ready : in std_logic;
reset : in std_logic;
interrupt : in std_logic;
vect_sel : in std_logic_vector(2 downto 1);
i_reg : in std_logic_vector(7 downto 0);
index_carry : in std_logic;
pc_carry : in std_logic;
branch_taken : in boolean;
state_idx : out integer range 0 to 31;
sync : out std_logic;
dummy_cycle : out std_logic;
latch_dreg : out std_logic;
copy_d2p : out std_logic;
reg_update : out std_logic;
flags_update : out std_logic;
rwn : out std_logic;
vect_addr : out std_logic_vector(3 downto 0);
nmi_done : out std_logic;
set_i_flag : out std_logic;
vectoring : out std_logic;
a16 : out std_logic;
taking_intr : out std_logic;
a_mux : out t_amux := c_amux_pc;
dout_mux : out t_dout_mux;
pc_oper : out t_pc_oper;
s_oper : out t_sp_oper;
adl_oper : out t_adl_oper;
adh_oper : out t_adh_oper );
end proc_control;
architecture gideon of proc_control is
type t_state is (fetch, decode, absolute, abs_hi, abs_fix, branch, branch_fix,
indir1, indir2, jump_sub, jump, retrn, rmw1, rmw2, vector, startup,
zp, zp_idx, zp_indir, push1, push2, push3, pull1, pull2, pull3, pre_irq );
signal state : t_state;
signal next_state : t_state;
signal rwn_i : std_logic;
signal next_cp_p : std_logic;
signal next_rwn : std_logic;
signal next_dreg : std_logic;
signal next_amux : t_amux;
signal next_dout : t_dout_mux;
signal next_dummy : std_logic;
signal next_irqinh : std_logic;
signal next_flags : std_logic;
signal vectoring_i : std_logic;
signal intg_i : std_logic;
signal vect_bit_i : std_logic;
signal vect_reg : std_logic_vector(2 downto 1);
signal sync_i : std_logic;
signal irq_inhibit : std_logic;
signal trigger_upd : boolean;
begin
-- combinatroial process
process(state, i_reg, index_carry, pc_carry, branch_taken, intg_i, vectoring_i, irq_inhibit)
variable v_stack_idx : std_logic_vector(1 downto 0);
begin
-- defaults
sync_i <= '0';
pc_oper <= increment;
next_amux <= c_amux_pc;
next_rwn <= '1';
next_state <= state;
adl_oper <= keep;
adh_oper <= keep;
s_oper <= keep;
next_dreg <= '1';
next_cp_p <= '0';
next_dout <= reg_d;
next_dummy <= '0';
next_irqinh <= '0';
next_flags <= '0';
v_stack_idx := stack_idx(i_reg);
case state is
when fetch =>
if intg_i = '1' then
pc_oper <= keep;
else
pc_oper <= increment;
end if;
next_state <= decode;
sync_i <= '1';
when pre_irq =>
pc_oper <= keep;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_pch;
next_state <= push1;
next_amux <= c_amux_stack;
when decode =>
adl_oper <= load_bus;
adh_oper <= clear;
if is_absolute(i_reg) then
if is_abs_jump(i_reg) then
next_state <= jump;
else
next_state <= absolute;
end if;
elsif is_implied(i_reg) then
pc_oper <= keep;
if is_stack(i_reg) then -- PHP, PLP, PHA, PLA
next_amux <= c_amux_stack;
case v_stack_idx is
when "00" => -- PHP
next_state <= push3;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_flags;
when "10" => -- PHA
next_state <= push3;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_accu;
when others =>
next_state <= pull1;
end case;
else
next_state <= fetch;
end if;
elsif is_zeropage(i_reg) then
next_amux <= c_amux_addr;
if is_indirect(i_reg) then
if is_postindexed(i_reg) then
next_state <= zp_indir;
else
next_state <= zp;
next_dummy <= '1';
end if;
else
next_state <= zp;
if is_store(i_reg) and not is_postindexed(i_reg) then
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_axy;
end if;
end if;
elsif is_relative(i_reg) then
next_state <= branch;
elsif is_stack(i_reg) then -- non-implied stack operations like BRK, JSR, RTI and RTS
next_amux <= c_amux_stack;
case v_stack_idx is
when c_stack_idx_brk =>
if vectoring_i = '1' then
pc_oper <= keep;
end if;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_pch;
next_state <= push1;
when c_stack_idx_jsr =>
next_dreg <= '0';
next_dout <= reg_pch;
next_state <= jump_sub;
when c_stack_idx_rti =>
next_state <= pull1;
when c_stack_idx_rts =>
next_state <= pull2;
when others =>
null;
end case;
elsif is_immediate(i_reg) then
next_state <= fetch;
elsif g_no_halt then
next_state <= fetch;
end if;
when absolute =>
next_state <= abs_hi;
next_amux <= c_amux_addr;
adh_oper <= load_bus;
if is_postindexed(i_reg) then
adl_oper <= add_idx;
elsif not is_zeropage(i_reg) then
if is_store(i_reg) then
next_rwn <='0';
next_dreg <= '0';
next_dout <= reg_axy;
end if;
end if;
if is_zeropage(i_reg) then
pc_oper <= keep;
else
pc_oper <= increment;
end if;
when abs_hi =>
pc_oper <= keep;
if is_postindexed(i_reg) then
if is_load(i_reg) and index_carry='0' then
next_amux <= c_amux_pc;
next_state <= fetch;
else
next_amux <= c_amux_addr;
next_state <= abs_fix;
if index_carry='1' then
adh_oper <= increment;
end if;
end if;
if is_store(i_reg) then
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_axy;
end if;
else -- not post-indexed
if is_jump(i_reg) then
next_amux <= c_amux_addr;
next_state <= jump;
adl_oper <= increment;
elsif is_rmw(i_reg) then
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_d;
next_dummy <= '1';
next_state <= rmw1;
next_amux <= c_amux_addr;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
end if;
when abs_fix =>
pc_oper <= keep;
if is_rmw(i_reg) then
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_d;
next_dummy <= '1';
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when branch =>
next_amux <= c_amux_pc;
if branch_taken then
pc_oper <= from_alu; -- add offset
next_state <= branch_fix;
else
next_state <= decode;
sync_i <= '1';
if intg_i='1' then
pc_oper <= keep;
end if;
end if;
when branch_fix =>
next_amux <= c_amux_pc;
if pc_carry='1' then
next_state <= fetch;
pc_oper <= keep; -- this will fix the PCH, since the carry is set
else
next_state <= decode;
sync_i <= '1';
if intg_i='1' then
pc_oper <= keep;
else
pc_oper <= increment;
end if;
end if;
when indir1 =>
pc_oper <= keep;
next_state <= indir2;
next_amux <= c_amux_addr;
adl_oper <= copy_dreg;
adh_oper <= load_bus;
if is_store(i_reg) then
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_axy;
end if;
when indir2 =>
pc_oper <= keep;
if is_rmw(i_reg) then
next_dummy <= '1';
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_d;
next_state <= rmw1;
next_amux <= c_amux_addr;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when jump_sub =>
next_state <= push1;
pc_oper <= keep;
next_dout <= reg_pch;
next_rwn <= '0';
next_dreg <= '0';
next_amux <= c_amux_stack;
when jump =>
pc_oper <= copy;
next_amux <= c_amux_pc;
if is_stack(i_reg) and v_stack_idx=c_stack_idx_rts then
next_state <= retrn;
else
next_irqinh <= irq_inhibit;
next_state <= fetch;
end if;
when retrn =>
pc_oper <= increment;
next_state <= fetch;
when pull1 =>
s_oper <= increment;
next_state <= pull2;
next_amux <= c_amux_stack;
pc_oper <= keep;
when pull2 =>
pc_oper <= keep;
if is_implied(i_reg) then
next_state <= fetch;
next_amux <= c_amux_pc;
next_cp_p <= not v_stack_idx(1); -- only for PLP
else -- it was a stack operation, but not implied (RTS/RTI)
s_oper <= increment;
next_state <= pull3;
next_amux <= c_amux_stack;
next_cp_p <= not v_stack_idx(0); -- only for RTI
end if;
when pull3 =>
pc_oper <= keep;
s_oper <= increment;
next_state <= jump;
next_amux <= c_amux_stack;
when push1 =>
pc_oper <= keep;
s_oper <= decrement;
next_state <= push2;
next_amux <= c_amux_stack;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_pcl;
when push2 =>
pc_oper <= keep;
s_oper <= decrement;
if v_stack_idx=c_stack_idx_jsr then
next_state <= jump;
next_amux <= c_amux_pc;
else
next_state <= push3;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_flags;
next_amux <= c_amux_stack;
end if;
when push3 =>
pc_oper <= keep;
s_oper <= decrement;
if is_implied(i_reg) then -- PHP, PHA
next_amux <= c_amux_pc;
next_state <= fetch;
else
next_state <= vector;
next_amux <= c_amux_vector;
end if;
when rmw1 =>
pc_oper <= keep;
next_state <= rmw2;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dreg <= '1'; -- exception for illegals like SLO
next_flags <= '1';
next_dout <= shift_res;
when rmw2 =>
pc_oper <= keep;
next_state <= fetch;
next_amux <= c_amux_pc;
when vector =>
next_state <= jump;
pc_oper <= keep;
next_irqinh <= '1';
next_amux <= c_amux_vector;
when startup =>
next_state <= vector;
pc_oper <= keep;
next_amux <= c_amux_vector;
when zp =>
pc_oper <= keep;
if is_postindexed(i_reg) or is_indirect(i_reg) then
adl_oper <= add_idx;
next_state <= zp_idx;
next_amux <= c_amux_addr;
if is_postindexed(i_reg) and is_store(i_reg) then
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_axy;
end if;
elsif is_rmw(i_reg) then
next_dummy <= '1';
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_d;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when zp_idx =>
pc_oper <= keep;
if is_indirect(i_reg) then
next_state <= indir1;
adl_oper <= increment;
next_amux <= c_amux_addr;
elsif is_rmw(i_reg) then
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_d;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when zp_indir =>
pc_oper <= keep;
next_state <= absolute;
next_amux <= c_amux_addr;
adl_oper <= increment;
when others =>
null;
end case;
end process;
reg_update <= '1' when (state = fetch) and trigger_upd else '0';
nmi_done <= not vect_reg(2) when state = vector else '0'; -- Only for NMIs
set_i_flag <= '1' when state = vector else '0';
vect_bit_i <= '0' when state = vector else '1';
vect_addr <= '1' & vect_reg & vect_bit_i;
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
if next_state = branch or next_state = fetch then
if interrupt = '1' and next_irqinh = '0' then
intg_i <= '1';
end if;
elsif state = vector and ready = '1' then
intg_i <= '0';
end if;
if ready='1' or rwn_i='0' then
state <= next_state;
a_mux <= next_amux;
dout_mux <= next_dout;
rwn_i <= next_rwn;
latch_dreg <= next_dreg; -- and next_rwn;
copy_d2p <= next_cp_p;
dummy_cycle <= next_dummy;
irq_inhibit <= next_irqinh;
flags_update <= next_flags;
trigger_upd <= affect_registers(i_reg);
if sync_i='1' and intg_i='1' then
vectoring_i <= '1';
elsif state = vector then
vectoring_i <= '0';
end if;
if next_amux = c_amux_vector or next_amux = c_amux_pc then
a16 <= '1';
else
a16 <= '0';
end if;
if next_state = vector then
vect_reg <= vect_sel;
end if;
end if;
end if;
if reset='1' then
a16 <= '1';
state <= startup; --vector;
vect_reg <= vect_sel;
a_mux <= c_amux_vector;
rwn_i <= '1';
latch_dreg <= '1';
dout_mux <= reg_d;
copy_d2p <= '0';
vectoring_i <= '0';
dummy_cycle <= '0';
irq_inhibit <= '0';
flags_update <= '0';
intg_i <= '0';
end if;
end if;
end process;
vectoring <= intg_i; --vectoring_i;
sync <= sync_i;
rwn <= rwn_i;
state_idx <= t_state'pos(state);
taking_intr <= vectoring_i;
end architecture;
| gpl-3.0 | 77cc600dafc405694bc08d96d51a2185 | 0.385638 | 4.08984 | false | false | false | false |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/voltage_dependend_capacitor_arc.vhdl | 15 | 362 | ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
| gpl-2.0 | 39194ae50fd44d968d1d8d29c479ec3e | 0.560773 | 2.549296 | false | false | false | false |
armandas/Plong | graphics.vhd | 1 | 15,274 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity graphics is
port(
clk, not_reset: in std_logic;
nes1_up, nes1_down: in std_logic;
nes2_up, nes2_down: in std_logic;
nes_start: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
video_on: in std_logic;
rgb_stream: out std_logic_vector(2 downto 0);
ball_bounced: out std_logic;
ball_missed: out std_logic
);
end graphics;
architecture dispatcher of graphics is
constant SCREEN_WIDTH: integer := 640;
constant SCREEN_HEIGHT: integer := 480;
type game_states is (start, waiting, playing, game_over);
signal state, state_next: game_states;
type counter_storage is array(0 to 3) of std_logic_vector(17 downto 0);
constant COUNTER_VALUES: counter_storage :=
(
"110010110111001101", -- 208333
"101000101100001011", -- 166667
"100001111010001001", -- 138889
"011101000100001000" -- 119048
);
-- counters to determine ball control frequency
signal ball_control_counter,
ball_control_counter_next: std_logic_vector(17 downto 0);
signal ball_control_value: integer;
-- counts how many times the ball hits the bar
-- used to determine ball speed
signal bounce_counter, bounce_counter_next: std_logic_vector(7 downto 0);
constant MIDDLE_LINE_POS: integer := SCREEN_WIDTH / 2;
signal middle_line_on: std_logic;
signal middle_line_rgb: std_logic_vector(2 downto 0);
signal score_1, score_1_next: std_logic_vector(5 downto 0);
signal score_2, score_2_next: std_logic_vector(5 downto 0);
signal score_on: std_logic;
signal current_score: std_logic_vector(5 downto 0);
signal score_font_addr: std_logic_vector(8 downto 0);
-- message format is "PLAYER p WINS!"
-- where p is replaced by player_id
signal message_on, player_id_on: std_logic;
signal message_font_addr, player_id_font_addr: std_logic_vector(8 downto 0);
signal font_addr: std_logic_vector(8 downto 0);
signal font_data: std_logic_vector(0 to 7);
signal font_pixel: std_logic;
signal font_rgb: std_logic_vector(2 downto 0);
constant BALL_SIZE: integer := 16; -- ball is square
signal ball_enable: std_logic;
signal ball_addr: std_logic_vector(3 downto 0);
signal ball_px_addr: std_logic_vector(3 downto 0);
signal ball_data: std_logic_vector(0 to BALL_SIZE - 1);
signal ball_pixel: std_logic;
signal ball_rgb: std_logic_vector(2 downto 0);
signal ball_x, ball_x_next: std_logic_vector(9 downto 0);
signal ball_y, ball_y_next: std_logic_vector(9 downto 0);
signal ball_h_dir, ball_h_dir_next, ball_v_dir, ball_v_dir_next: std_logic;
signal ball_bounce, ball_miss: std_logic;
constant BAR_1_POS: integer := 20;
constant BAR_2_POS: integer := 600;
constant BAR_WIDTH: integer := 20;
constant BAR_HEIGHT: integer := 64;
signal bar_pos: integer;
signal bar_addr: std_logic_vector(5 downto 0);
signal bar_data: std_logic_vector(0 to BAR_WIDTH - 1);
signal bar_pixel: std_logic;
signal bar_rgb: std_logic_vector(2 downto 0);
signal bar_1_y, bar_1_y_next,
bar_2_y, bar_2_y_next: std_logic_vector(9 downto 0);
signal ball_on, bar_on: std_logic;
begin
process(state, ball_x, nes_start, score_1, score_2)
begin
state_next <= state;
ball_enable <= '0';
ball_miss <= '0';
score_1_next <= score_1;
score_2_next <= score_2;
case state is
when start =>
score_1_next <= (others => '0');
score_2_next <= (others => '0');
state_next <= waiting;
when waiting =>
ball_enable <= '0';
if score_1 = 7 or score_2 = 7 then
state_next <= game_over;
elsif nes_start = '1' then
state_next <= playing;
end if;
when playing =>
ball_enable <= '1';
if ball_x = 0 then
-- player 2 wins
score_2_next <= score_2 + 1;
state_next <= waiting;
ball_miss <= '1';
elsif ball_x = SCREEN_WIDTH - BALL_SIZE then
-- player 1 wins
score_1_next <= score_1 + 1;
state_next <= waiting;
ball_miss <= '1';
end if;
when game_over =>
if nes_start = '1' then
state_next <= start;
end if;
end case;
end process;
process(clk, not_reset)
begin
if not_reset = '0' then
state <= start;
ball_x <= (others => '0');
ball_y <= (others => '0');
bar_1_y <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BAR_HEIGHT / 2, 10);
bar_2_y <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BAR_HEIGHT / 2, 10);
ball_h_dir <= '0';
ball_v_dir <= '0';
bounce_counter <= (others => '0');
ball_control_counter <= (others => '0');
score_1 <= (others => '0');
score_2 <= (others => '0');
elsif clk'event and clk = '0' then
state <= state_next;
ball_x <= ball_x_next;
ball_y <= ball_y_next;
bar_1_y <= bar_1_y_next;
bar_2_y <= bar_2_y_next;
ball_h_dir <= ball_h_dir_next;
ball_v_dir <= ball_v_dir_next;
bounce_counter <= bounce_counter_next;
ball_control_counter <= ball_control_counter_next;
score_1 <= score_1_next;
score_2 <= score_2_next;
end if;
end process;
score_on <= '1' when px_y(9 downto 3) = 1 and
(px_x(9 downto 3) = 42 or px_x(9 downto 3) = 37) else
'0';
current_score <= score_1 when px_x < 320 else score_2;
-- numbers start at memory location 128
-- '1' starts at 136, '2' at 144 and so on
score_font_addr <= conv_std_logic_vector(128, 9) +
(current_score(2 downto 0) & current_score(5 downto 3));
player_id_on <= '1' when state = game_over and px_y(9 downto 3) = 29 and
(px_x(9 downto 3) = 19 or px_x(9 downto 3) = 59) else
'0';
-- player_id will display either 1 or 2
player_id_font_addr <= "010001000" when px_x < 320 else "010010000";
message_on <= '1' when state = game_over and
-- message on player_1's side
((score_1 > score_2 and
px_x(9 downto 3) >= 12 and
px_x(9 downto 3) < 26 and
px_y(9 downto 3) = 29) or
-- message on player_2's side
(score_2 > score_1 and
px_x(9 downto 3) >= 52 and
px_x(9 downto 3) < 66 and
px_y(9 downto 3) = 29)) else
'0';
with px_x(9 downto 3) select
message_font_addr <= "110000000" when "0110100"|"0001100", -- P
"101100000" when "0110101"|"0001101", -- L
"100001000" when "0110110"|"0001110", -- A
"111001000" when "0110111"|"0001111", -- Y
"100101000" when "0111000"|"0010000", -- E
"110010000" when "0111001"|"0010001", -- R
"111100000" when "0111011"|"0010011", -- not visible
"110111000" when "0111101"|"0010101", -- W
"101111000" when "0111110"|"0010110", -- O
"101110000" when "0111111"|"0010111", -- N
"000001000" when "1000000"|"0011000", -- !
"000000000" when others;
-- font address mutltiplexer
font_addr <= px_y(2 downto 0) + score_font_addr when score_on = '1' else
px_y(2 downto 0) + player_id_font_addr when player_id_on = '1' else
px_y(2 downto 0) + message_font_addr when message_on = '1' else
(others => '0');
font_pixel <= font_data(conv_integer(px_x(2 downto 0)));
font_rgb <= "000" when font_pixel = '1' else "111";
direction_control: process(
ball_control_counter,
ball_x, ball_y,
ball_h_dir, ball_v_dir,
ball_h_dir_next, ball_v_dir_next,
bar_1_y, bar_2_y
)
begin
ball_h_dir_next <= ball_h_dir;
ball_v_dir_next <= ball_v_dir;
ball_bounce <= '0';
--
-- BEWARE! Looks like ball_bounce signal is generated twice
-- due to slower clock! Too lazy to fix now :D
--
if ball_control_counter = 0 then
if ball_x = bar_1_pos + BAR_WIDTH and
ball_y + BALL_SIZE > bar_1_y and
ball_y < bar_1_y + BAR_HEIGHT then
ball_h_dir_next <= '1';
ball_bounce <= '1';
elsif ball_x + BALL_SIZE = bar_2_pos and
ball_y + BALL_SIZE > bar_2_y and
ball_y < bar_2_y + BAR_HEIGHT then
ball_h_dir_next <= '0';
ball_bounce <= '1';
elsif ball_x < bar_1_pos + BAR_WIDTH and
ball_x + BALL_SIZE > bar_1_pos then
if ball_y + BALL_SIZE = bar_1_y then
ball_v_dir_next <= '0';
elsif ball_y = bar_1_y + BAR_HEIGHT then
ball_v_dir_next <= '1';
end if;
elsif ball_x + BALL_SIZE > bar_2_pos and
ball_x < bar_2_pos + BAR_WIDTH then
if ball_y + BALL_SIZE = bar_2_y then
ball_v_dir_next <= '0';
elsif ball_y = bar_2_y + BAR_HEIGHT then
ball_v_dir_next <= '1';
end if;
end if;
if ball_y = 0 then
ball_v_dir_next <= '1';
elsif ball_y = SCREEN_HEIGHT - BALL_SIZE then
ball_v_dir_next <= '0';
end if;
end if;
end process;
bounce_counter_next <= bounce_counter + 1 when ball_bounce = '1' else
(others => '0') when ball_miss = '1' else
bounce_counter;
ball_control_value <= 0 when bounce_counter < 4 else
1 when bounce_counter < 15 else
2 when bounce_counter < 25 else
3;
ball_control_counter_next <= ball_control_counter + 1 when ball_control_counter < COUNTER_VALUES(ball_control_value) else
(others => '0');
ball_control: process(
ball_control_counter,
ball_x, ball_y,
ball_x_next, ball_y_next,
ball_h_dir, ball_v_dir,
ball_enable
)
begin
ball_x_next <= ball_x;
ball_y_next <= ball_y;
if ball_enable = '1' then
if ball_control_counter = 0 then
if ball_h_dir = '1' then
ball_x_next <= ball_x + 1;
else
ball_x_next <= ball_x - 1;
end if;
if ball_v_dir = '1' then
ball_y_next <= ball_y + 1;
else
ball_y_next <= ball_y - 1;
end if;
end if;
else
ball_x_next <= conv_std_logic_vector(SCREEN_WIDTH / 2 - BALL_SIZE / 2, 10);
ball_y_next <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BALL_SIZE / 2, 10);
end if;
end process;
bar_control: process(
bar_1_y, bar_2_y,
nes1_up, nes1_down,
nes2_up, nes2_down
)
begin
bar_1_y_next <= bar_1_y;
bar_2_y_next <= bar_2_y;
if nes1_up = '1' then
if bar_1_y > 0 then
bar_1_y_next <= bar_1_y - 1;
end if;
elsif nes1_down = '1' then
if bar_1_y < SCREEN_HEIGHT - BAR_HEIGHT - 1 then
bar_1_y_next <= bar_1_y + 1;
end if;
end if;
if nes2_up = '1' then
if bar_2_y > 0 then
bar_2_y_next <= bar_2_y - 1;
end if;
elsif nes2_down = '1' then
if bar_2_y < SCREEN_HEIGHT - BAR_HEIGHT - 1 then
bar_2_y_next <= bar_2_y + 1;
end if;
end if;
end process;
middle_line_on <= '1' when px_x = MIDDLE_LINE_POS else '0';
middle_line_rgb <= "000" when px_y(0) = '1' else "111";
ball_on <= '1' when px_x >= ball_x and
px_x < (ball_x + BALL_SIZE) and
px_y >= ball_y and
px_y < (ball_y + BALL_SIZE) else
'0';
-- whether bar_1 or bar_2 is on
bar_on <= '1' when (px_x >= BAR_1_POS and
px_x < BAR_1_POS + BAR_WIDTH and
px_y >= bar_1_y and
px_y < bar_1_y + BAR_HEIGHT) or
(px_x >= BAR_2_POS and
px_x < BAR_2_POS + BAR_WIDTH and
px_y >= bar_2_y and
px_y < bar_2_y + BAR_HEIGHT) else
'0';
ball_addr <= px_y(3 downto 0) - ball_y(3 downto 0);
ball_px_addr <= px_x(3 downto 0) - ball_x(3 downto 0);
ball_pixel <= ball_data(conv_integer(ball_px_addr));
ball_rgb <= "000" when ball_pixel = '1' else "111";
bar_addr <= (px_y(5 downto 0) - bar_1_y(5 downto 0)) when px_x < 320 else
(px_y(5 downto 0) - bar_2_y(5 downto 0));
bar_pos <= BAR_1_POS when px_x < 320 else BAR_2_POS;
bar_pixel <= bar_data(conv_integer(px_x - bar_pos));
bar_rgb <= "000" when bar_pixel = '1' else "111";
process(
ball_on, bar_on,
ball_rgb, bar_rgb,
score_on, message_on, font_rgb,
middle_line_on, middle_line_rgb,
video_on
)
begin
if video_on = '1' then
if bar_on = '1' then
rgb_stream <= bar_rgb;
elsif ball_on = '1' then
rgb_stream <= ball_rgb;
elsif middle_line_on = '1' then
rgb_stream <= middle_line_rgb;
-- scores and messages share rgb stream
elsif score_on = '1' or message_on = '1' then
rgb_stream <= font_rgb;
else
-- background is white
rgb_stream <= "111";
end if;
else
-- blank screen
rgb_stream <= "000";
end if;
end process;
ball_unit:
entity work.ball_rom(content)
port map(addr => ball_addr, data => ball_data);
bar_unit:
entity work.bar_rom(content)
port map(clk => clk, addr => bar_addr, data => bar_data);
font_unit:
entity work.codepage_rom(content)
port map(addr => font_addr, data => font_data);
ball_bounced <= ball_bounce;
ball_missed <= ball_miss;
end dispatcher; | bsd-2-clause | 73f009f7fc43d029c54e0afe00286d5c | 0.491423 | 3.598963 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/standard/cb20/synthesis/cb20_info_device_0_avalon_slave_translator.vhd | 1 | 14,655 | -- cb20_info_device_0_avalon_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 5;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(4 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_info_device_0_avalon_slave_translator;
architecture rtl of cb20_info_device_0_avalon_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
info_device_0_avalon_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_info_device_0_avalon_slave_translator
| apache-2.0 | ef4e01bd83169c822942b87a7542d2fd | 0.429887 | 4.348665 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/debug/vhdl_source/eth_debug_stream.vhd | 1 | 2,287 | -------------------------------------------------------------------------------
-- Title : eth_debug_stream
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Merges bus debug data to ethernet Tx stream for U2P (Dummy!)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity eth_debug_stream is
port (
eth_clock : in std_logic;
eth_reset : in std_logic;
eth_u2p_data : in std_logic_vector(7 downto 0);
eth_u2p_last : in std_logic;
eth_u2p_valid : in std_logic;
eth_u2p_ready : out std_logic;
eth_tx_data : out std_logic_vector(7 downto 0);
eth_tx_last : out std_logic;
eth_tx_valid : out std_logic;
eth_tx_ready : in std_logic := '1';
--
sys_clock : in std_logic;
sys_reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
c64_debug_select : out std_logic_vector(2 downto 0);
c64_debug_data : in std_logic_vector(31 downto 0);
c64_debug_valid : in std_logic;
drv_debug_data : in std_logic_vector(31 downto 0);
drv_debug_valid : in std_logic;
IEC_ATN : in std_logic;
IEC_CLOCK : in std_logic;
IEC_DATA : in std_logic );
end entity;
architecture structural of eth_debug_stream is
begin
-- Because the Ethernet Debug streamer uses propriatary IP, this
-- module is simply a dummy; indicating that it does not support
-- this feature. The network TX connection is simply passed through.
c64_debug_select <= "000";
-- Direct Connection
eth_tx_data <= eth_u2p_data;
eth_tx_last <= eth_u2p_last;
eth_tx_valid <= eth_u2p_valid;
eth_u2p_ready <= eth_tx_ready;
process(sys_clock)
begin
if rising_edge(sys_clock) then
io_resp <= c_io_resp_init;
io_resp.ack <= io_req.read or io_req.write;
end if;
end process;
end architecture;
| gpl-3.0 | a218ed42cda00b77a1738ad9268b0097 | 0.509838 | 3.562305 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/sampler/vhdl_source/sampler.vhd | 1 | 10,202 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
entity sampler is
generic (
g_clock_freq : natural := 50_000_000;
g_num_voices : positive := 8 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
irq : out std_logic;
sample_L : out signed(17 downto 0);
sample_R : out signed(17 downto 0);
new_sample : out std_logic );
end entity;
architecture gideon of sampler is
function iif(c : boolean; t : natural; f : natural) return natural is
begin
if c then return t; else return f; end if;
end function iif;
-- At this point there are 3 systems:
-- Ultimate-II running at 50 MHz
-- Ultimate-II+ running at 62.5 MHz
-- Ultimate-64 running at 66.66 MHz
-- The ratios are: 1, 5/4 and 4/3, or 12/12, 15/12 and 16/12. So we should divide by this value
-- Or multiply by: 20/20, 16/20 and 15/20
constant c_iterations : natural := iif(g_clock_freq = 50_000_000, 8, 10);
signal voice_i : integer range 0 to g_num_voices-1;
signal iter_i : integer range 0 to c_iterations-1;
signal active_i : std_logic;
signal voice_state : t_voice_state_array(0 to g_num_voices-1) := (others => c_voice_state_init);
signal voice_sample_reg_h : t_sample_byte_array(0 to g_num_voices-1) := (others => (others => '0'));
signal voice_sample_reg_l : t_sample_byte_array(0 to g_num_voices-1) := (others => (others => '0'));
signal fetch_en : std_logic;
signal fetch_addr : unsigned(25 downto 0);
signal fetch_tag : std_logic_vector(7 downto 0);
signal interrupt : std_logic_vector(g_num_voices-1 downto 0);
signal interrupt_clr : std_logic_vector(g_num_voices-1 downto 0);
signal current_control : t_voice_control;
signal first_chan : std_logic;
signal cur_sam : signed(15 downto 0);
signal cur_vol : unsigned(5 downto 0);
signal cur_pan : unsigned(3 downto 0);
begin
i_regs: entity work.sampler_regs
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
rd_addr => voice_i,
control => current_control,
irq_status => interrupt,
irq_clear => interrupt_clr );
irq <= '1' when unsigned(interrupt) /= 0 else '0';
process(clock)
variable current_state : t_voice_state;
variable next_state : t_voice_state;
variable sample_reg : signed(15 downto 0);
variable v : integer range 0 to 15;
begin
if rising_edge(clock) then
if voice_i = g_num_voices-1 then
active_i <= '0';
else
voice_i <= voice_i + 1;
end if;
if iter_i = c_iterations-1 then
voice_i <= 0;
iter_i <= 0;
active_i <= '1';
else
iter_i <= iter_i + 1;
end if;
for i in interrupt'range loop
if interrupt_clr(i)='1' then
interrupt(i) <= '0';
end if;
end loop;
fetch_en <= '0';
current_state := voice_state(0);
sample_reg := voice_sample_reg_h(voice_i) & voice_sample_reg_l(voice_i);
next_state := current_state;
case current_state.state is
when idle =>
if current_control.enable and voice_i <= g_num_voices then
next_state.state := fetch1;
next_state.position := (others => '0');
next_state.divider := current_control.rate;
next_state.sample_out := (others => '0');
end if;
when playing =>
if current_state.divider = 0 then
next_state.divider := current_control.rate;
next_state.sample_out := sample_reg;
next_state.state := fetch1;
if (current_state.position = current_control.repeat_b) then
if current_control.enable and current_control.repeat then
next_state.position := current_control.repeat_a;
end if;
elsif current_state.position = current_control.length then
next_state.state := finished;
if current_control.interrupt then
interrupt(voice_i) <= '1';
end if;
end if;
else
next_state.divider := current_state.divider - 1;
end if;
if not current_control.enable and not current_control.repeat then
next_state.state := idle;
end if;
when finished =>
if not current_control.enable then
next_state.state := idle;
end if;
when fetch1 =>
fetch_en <= '1';
fetch_addr <= current_control.start_addr + current_state.position;
if current_control.mode = mono8 then
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '1'; -- high
next_state.state := playing;
if current_control.interleave then
next_state.position := current_state.position + 2; -- this and the next byte
else
next_state.position := current_state.position + 1; -- this byte only
end if;
else
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '0'; -- low
next_state.position := current_state.position + 1; -- go to the next byte
next_state.state := fetch2;
end if;
when fetch2 =>
fetch_en <= '1';
fetch_addr <= current_control.start_addr + current_state.position;
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '1'; -- high
next_state.state := playing;
if current_control.interleave then
next_state.position := current_state.position + 3; -- this and the two next bytes
else
next_state.position := current_state.position + 1; -- this byte only
end if;
when others =>
null;
end case;
cur_sam <= current_state.sample_out;
cur_vol <= current_control.volume;
cur_pan <= current_control.pan;
if voice_i=0 then
first_chan <= '1';
else
first_chan <= '0';
end if;
-- write port - state --
if active_i = '1' then
voice_state <= voice_state(1 to g_num_voices-1) & next_state;
else
cur_sam <= (others => '0');
fetch_en <= '0';
end if;
-- write port - sample data --
if mem_resp.dack_tag(7 downto 5) = "110" then
v := to_integer(unsigned(mem_resp.dack_tag(4 downto 1)));
if mem_resp.dack_tag(0)='1' then
voice_sample_reg_h(v) <= signed(mem_resp.data);
else
voice_sample_reg_l(v) <= signed(mem_resp.data);
end if;
end if;
if reset='1' then
voice_i <= 0;
iter_i <= 0;
active_i <= '1';
next_state.state := finished; -- shifted into the voice state vector automatically.
interrupt <= (others => '0');
end if;
end if;
end process;
b_mem_fifo: block
signal rack : std_logic;
signal fifo_din : std_logic_vector(33 downto 0);
signal fifo_dout : std_logic_vector(33 downto 0);
begin
fifo_din <= fetch_tag & std_logic_vector(fetch_addr);
i_fifo: entity work.srl_fifo
generic map (
Width => 34,
Depth => 15,
Threshold => 10 )
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => fetch_en,
FlushFifo => '0',
DataIn => fifo_din,
DataOut => fifo_dout,
SpaceInFifo => open,
DataInFifo => mem_req.request );
mem_req.read_writen <= '1';
mem_req.address <= unsigned(fifo_dout(25 downto 0));
mem_req.tag <= fifo_dout(33 downto 26);
mem_req.data <= X"00";
mem_req.size <= "00"; -- 1 byte at a time (can be optimized!)
rack <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag(7 downto 5)="110") else '0';
end block;
i_accu: entity work.sampler_accu
port map (
clock => clock,
reset => reset,
first_chan => first_chan,
sample_in => cur_sam,
volume_in => cur_vol,
pan_in => cur_pan,
sample_L => sample_L,
sample_R => sample_R,
new_sample => new_sample );
end gideon;
| gpl-3.0 | 1d8f876d09f8f41a1ffa7266239bb84a | 0.465791 | 4.12202 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/ultimate_fpga/vhdl_source/cyclone_test.vhd | 1 | 6,043 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cyclone_test is
port (
-- slot side
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : inout std_logic;
SLOT_BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : out std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : out std_logic;
SLOT_ROMLn : out std_logic;
SLOT_IO1n : out std_logic;
SLOT_IO2n : out std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DM : out std_logic := 'Z';
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic := 'Z';
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end cyclone_test;
architecture structural of cyclone_test is
signal clock : std_logic;
signal counter : unsigned(23 downto 0) := (others => '0');
signal pulses : unsigned(23 downto 1) := (others => '0');
begin
clock <= RMII_REFCLK;
process(clock)
begin
if rising_edge(clock) then
counter <= counter + 1;
pulses <= counter(23 downto 1) and counter(22 downto 0);
end if;
end process;
-- slot side
-- BUFFER_ENn <= '0';
SLOT_ADDR <= std_logic_vector(counter(23 downto 8));
SLOT_DATA <= std_logic_vector(counter(7 downto 0));
-- top
SLOT_DMAn <= pulses(1);
-- SLOT_BA <= pulses(2);
SLOT_ROMLn <= pulses(3);
SLOT_IO2n <= pulses(4);
SLOT_EXROMn <= pulses(5);
SLOT_GAMEn <= pulses(6);
SLOT_IO1n <= pulses(7);
-- SLOT_DOTCLK <= pulses(8);
SLOT_RWn <= pulses(9);
SLOT_IRQn <= pulses(10);
-- SLOT_PHI2 <= pulses(11);
SLOT_NMIn <= pulses(12);
SLOT_RSTn <= pulses(13);
SLOT_ROMHn <= pulses(14);
-- Cassette Interface
CAS_SENSE <= pulses(16);
CAS_READ <= pulses(17);
CAS_WRITE <= pulses(18);
-- CAS_MOTOR <= pulses(19);
I2C_SCL <= pulses(2);
I2C_SDA <= pulses(8);
I2C_SCL_18 <= pulses(3);
I2C_SDA_18 <= pulses(11);
-- local bus side
SDRAM_A <= (others => 'Z');
SDRAM_BA <= (others => 'Z');
SDRAM_CSn <= 'Z';
SDRAM_RASn <= 'Z';
SDRAM_CASn <= 'Z';
SDRAM_WEn <= 'Z';
SDRAM_DM <= 'Z';
SDRAM_CKE <= 'Z';
SDRAM_CLK <= 'Z';
-- PWM outputs (for audio)
SPEAKER_DATA <= '0';
SPEAKER_ENABLE <= '0';
-- IEC bus
IEC_ATN <= 'Z';
IEC_DATA <= 'Z';
IEC_CLOCK <= 'Z';
IEC_SRQ_IN <= 'Z';
LED_DISKn <= '0';
LED_CARTn <= '0';
LED_SDACTn <= '0';
LED_MOTORn <= '0';
-- Debug UART
UART_TXD <= '1';
-- Flash Interface
FLASH_CSn <= '1';
FLASH_SCK <= '1';
FLASH_MOSI <= '1';
-- USB Interface (ULPI)
ULPI_RESET <= '0';
ULPI_STP <= '0';
ULPI_DATA <= (others => 'Z');
SLOT_BUFFER_ENn <= '0';
end structural;
| gpl-3.0 | 33cc558cedb60dd773abf42a704e59a6 | 0.509184 | 3.094214 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/slot_server_v4.vhd | 1 | 33,050 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.cart_slot_pkg.all;
entity slot_server_v4 is
generic (
g_clock_freq : natural := 50_000_000;
g_tag_slot : std_logic_vector(7 downto 0) := X"08";
g_tag_reu : std_logic_vector(7 downto 0) := X"10";
g_ram_base_reu : std_logic_vector(27 downto 0) := X"1000000"; -- should be on 16M boundary, or should be limited in size
g_ram_base_cart : std_logic_vector(27 downto 0) := X"0EF0000"; -- should be on a 64K boundary
g_rom_base_cart : std_logic_vector(27 downto 0) := X"0F00000"; -- should be on a 1M boundary
g_kernal_base : std_logic_vector(27 downto 0) := X"0EA8000"; -- should be on a 32K boundary
g_direct_dma : boolean := false;
g_ext_freeze_act: boolean := false;
g_cartreset_init: std_logic := '0';
g_boot_stop : boolean := false;
g_big_endian : boolean;
g_kernal_repl : boolean := true;
g_control_read : boolean := true;
g_command_intf : boolean := true;
g_ram_expansion : boolean := true;
g_extended_reu : boolean := false;
g_sampler : boolean := false;
g_acia : boolean := false;
g_eeprom : boolean := true;
g_implement_sid : boolean := true;
g_sid_voices : natural := 3;
g_8voices : boolean := false;
g_vic_copper : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
VCC : in std_logic := '1';
phi2_i : in std_logic;
io1n_i : in std_logic;
io2n_i : in std_logic;
romln_i : in std_logic;
romhn_i : in std_logic;
dman_o : out std_logic := '1';
ba_i : in std_logic := '0';
rstn_i : in std_logic := '1';
rstn_o : out std_logic := '1';
slot_addr_o : out unsigned(15 downto 0);
slot_addr_i : in unsigned(15 downto 0) := (others => '1');
slot_addr_tl : out std_logic;
slot_addr_th : out std_logic;
slot_data_o : out std_logic_vector(7 downto 0);
slot_data_i : in std_logic_vector(7 downto 0) := (others => '1');
slot_data_t : out std_logic;
rwn_o : out std_logic;
rwn_i : in std_logic;
ultimax : out std_logic;
exromn_i : in std_logic := '1';
exromn_o : out std_logic;
gamen_i : in std_logic := '1';
gamen_o : out std_logic;
irqn_i : in std_logic := '1';
irqn_o : out std_logic;
nmin_i : in std_logic := '1';
nmin_o : out std_logic;
-- other hardware pins
BUFFER_ENn : out std_logic;
sense : in std_logic;
buttons : in std_logic_vector(2 downto 0);
cart_led_n : out std_logic;
trigger_1 : out std_logic;
trigger_2 : out std_logic;
-- debug / freezer
freeze_activate : in std_logic := '0';
freezer_state : out std_logic_vector(1 downto 0);
sync : out std_logic;
sw_trigger : out std_logic;
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
debug_select : in std_logic_vector(2 downto 0) := "000";
-- audio output
sid_left : out signed(17 downto 0);
sid_right : out signed(17 downto 0);
samp_left : out signed(17 downto 0);
samp_right : out signed(17 downto 0);
-- timing output
phi2_tick : out std_logic;
c64_stopped : out std_logic;
-- master on memory bus
memctrl_inhibit : out std_logic;
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
direct_dma_req : out t_dma_req := c_dma_req_init;
direct_dma_resp : in t_dma_resp := c_dma_resp_init;
-- slave on io bus
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq_cmd : out std_logic;
io_irq_acia : out std_logic );
end slot_server_v4;
architecture structural of slot_server_v4 is
signal phi2_tick_i : std_logic;
signal phi2_fall : std_logic;
signal phi2_recovered : std_logic;
signal vic_cycle : std_logic;
signal do_sample_addr : std_logic;
signal do_sample_io : std_logic;
signal do_io_event : std_logic;
signal do_probe_end : std_logic;
signal timing_inhibit : std_logic;
signal slave_dout : std_logic_vector(7 downto 0);
signal slave_dtri : std_logic := '0';
signal master_dout : std_logic_vector(7 downto 0);
signal master_dtri : std_logic := '0';
signal address_tri_l : std_logic;
signal address_tri_h : std_logic;
signal address_out : std_logic_vector(15 downto 0);
signal rwn_out : std_logic;
signal control : t_cart_control;
signal status : t_cart_status := (others => '0');
signal allow_serve : std_logic;
-- interface with freezer (cartridge) logic
signal serve_enable : std_logic := '0'; -- from cartridge emulation logic
signal serve_inhibit : std_logic := '0';
signal serve_vic : std_logic := '0';
signal serve_128 : std_logic := '0';
signal serve_rom : std_logic := '0'; -- ROML or ROMH
signal serve_io1 : std_logic := '0'; -- IO1n
signal serve_io2 : std_logic := '0'; -- IO2n
signal allow_write : std_logic := '0';
-- kernal replacement logic
signal kernal_area : std_logic := '0';
signal kernal_probe : std_logic := '0';
signal kernal_addr_out : std_logic := '0';
signal force_ultimax : std_logic := '0';
signal cpu_write : std_logic;
signal epyx_timeout : std_logic;
signal reu_dma_n : std_logic := '1'; -- direct from REC
signal cmd_if_freeze : std_logic := '0'; -- same function as reu_dma_n, but then from CI
signal reset_button : std_logic;
signal freeze_button : std_logic;
signal actual_c64_reset : std_logic;
signal dma_n : std_logic := '1';
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal exrom_n : std_logic := '1';
signal game_n : std_logic := '1';
signal unfreeze : std_logic;
signal freeze_trig : std_logic;
signal freeze_active : std_logic;
signal io_req_dma : t_io_req;
signal io_resp_dma : t_io_resp := c_io_resp_init;
signal io_req_peri : t_io_req;
signal io_resp_peri : t_io_resp := c_io_resp_init;
signal io_req_sid : t_io_req;
signal io_resp_sid : t_io_resp := c_io_resp_init;
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_req_cmd : t_io_req;
signal io_resp_cmd : t_io_resp := c_io_resp_init;
signal io_req_copper : t_io_req;
signal io_resp_copper : t_io_resp := c_io_resp_init;
signal io_req_samp_cpu : t_io_req;
signal io_resp_samp_cpu : t_io_resp := c_io_resp_init;
signal io_req_acia : t_io_req;
signal io_resp_acia : t_io_resp := c_io_resp_init;
signal io_req_eeprom : t_io_req;
signal io_resp_eeprom : t_io_resp := c_io_resp_init;
signal dma_req_io : t_dma_req;
signal dma_resp_io : t_dma_resp := c_dma_resp_init;
signal dma_req_reu : t_dma_req;
signal dma_resp_reu : t_dma_resp := c_dma_resp_init;
signal dma_req_copper : t_dma_req;
signal dma_resp_copper : t_dma_resp := c_dma_resp_init;
signal dma_req : t_dma_req;
signal dma_resp : t_dma_resp := c_dma_resp_init;
signal write_ff00 : std_logic;
signal slot_req : t_slot_req;
signal slot_resp : t_slot_resp := c_slot_resp_init;
signal slot_resp_reu : t_slot_resp := c_slot_resp_init;
signal slot_resp_cart : t_slot_resp := c_slot_resp_init;
signal slot_resp_sid : t_slot_resp := c_slot_resp_init;
signal slot_resp_cmd : t_slot_resp := c_slot_resp_init;
signal slot_resp_samp : t_slot_resp := c_slot_resp_init;
signal slot_resp_acia : t_slot_resp := c_slot_resp_init;
signal mem_req_reu : t_mem_req := c_mem_req_init;
signal mem_resp_reu : t_mem_resp := c_mem_resp_init;
signal mem_req_samp : t_mem_req := c_mem_req_init;
signal mem_resp_samp : t_mem_resp := c_mem_resp_init;
signal mem_req_32_slot : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_slot : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_reu : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_reu : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_samp : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_samp : t_mem_resp_32 := c_mem_resp_32_init;
-- signal mem_req_trace : t_mem_req;
-- signal mem_resp_trace : t_mem_resp;
signal mem_rack_slot : std_logic;
signal mem_dack_slot : std_logic;
signal phi2_tick_avail : std_logic;
begin
reset_button <= buttons(0) when control.swap_buttons='0' else buttons(2);
freeze_button <= buttons(2) when control.swap_buttons='0' else buttons(0);
i_split_64K: entity work.io_bus_splitter
generic map (
g_range_lo => 16,
g_range_hi => 16,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_peri, -- 4040000
reqs(1) => io_req_dma, -- 4050000
resps(0) => io_resp_peri,
resps(1) => io_resp_dma );
i_bridge: entity work.io_to_dma_bridge
generic map (
g_ignore_stop => true )
port map (
clock => clock,
reset => reset,
c64_stopped => status.c64_stopped,
io_req => io_req_dma,
io_resp => io_resp_dma,
dma_req => dma_req_io,
dma_resp => dma_resp_io );
i_split_8K: entity work.io_bus_splitter
generic map (
g_range_lo => 13,
g_range_hi => 15,
g_ports => 7 )
port map (
clock => clock,
req => io_req_peri,
resp => io_resp_peri,
reqs(0) => io_req_regs, -- 4040000
reqs(1) => io_req_sid, -- 4042000
reqs(2) => io_req_cmd, -- 4044000
reqs(3) => io_req_copper, -- 4046000
reqs(4) => io_req_samp_cpu, -- 4048000
reqs(5) => io_req_acia, -- 404A000
reqs(6) => io_req_eeprom, -- 404C000
resps(0) => io_resp_regs,
resps(1) => io_resp_sid,
resps(2) => io_resp_cmd,
resps(3) => io_resp_copper,
resps(4) => io_resp_samp_cpu,
resps(5) => io_resp_acia,
resps(6) => io_resp_eeprom );
i_registers: entity work.cart_slot_registers
generic map (
g_kernal_repl => g_kernal_repl,
g_boot_stop => g_boot_stop,
g_cartreset_init=> g_cartreset_init,
g_ram_expansion => g_ram_expansion )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control,
status => status );
serve_inhibit <= status.c64_stopped and not control.serve_while_stopped;
i_timing: entity work.slot_timing
port map (
clock => clock,
reset => reset,
-- Cartridge pins
PHI2 => phi2_i,
BA => ba_i,
serve_vic => serve_vic,
serve_enable => serve_enable,
serve_inhibit => serve_inhibit,
allow_serve => allow_serve,
timing_addr => control.timing_addr_valid,
edge_recover => control.phi2_edge_recover,
phi2_tick => phi2_tick_i,
phi2_fall => phi2_fall,
phi2_recovered => phi2_recovered,
clock_det => status.clock_detect,
vic_cycle => vic_cycle,
inhibit => timing_inhibit,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_probe_end => do_probe_end,
do_io_event => do_io_event );
mem_req_32_slot.tag <= g_tag_slot;
mem_req_32_slot.byte_en <= "1000" when g_big_endian else "0001";
mem_rack_slot <= '1' when mem_resp_32_slot.rack_tag = g_tag_slot else '0';
mem_dack_slot <= '1' when mem_resp_32_slot.dack_tag = g_tag_slot else '0';
i_slave: entity work.slot_slave
generic map (
g_big_endian => g_big_endian )
port map (
clock => clock,
reset => reset,
-- Cartridge pins
VCC => VCC,
RSTn => rstn_i,
IO1n => io1n_i,
IO2n => io2n_i,
ROMLn => romln_i,
ROMHn => romhn_i,
GAMEn => gamen_i,
EXROMn => exromn_i,
RWn => rwn_i,
BA => ba_i,
ADDRESS => slot_addr_i,
DATA_in => slot_data_i,
DATA_out => slave_dout,
DATA_tri => slave_dtri,
-- interface with memory controller
mem_req => mem_req_32_slot.request,
mem_rwn => mem_req_32_slot.read_writen,
mem_wdata => mem_req_32_slot.data,
mem_rack => mem_rack_slot,
mem_dack => mem_dack_slot,
mem_rdata => mem_resp_32_slot.data,
-- mem_addr comes from cartridge logic
-- synchronized outputs
reset_out => actual_c64_reset,
-- timing inputs
phi2_tick => phi2_tick_i,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_io_event => do_io_event,
do_probe_end => do_probe_end,
dma_active_n => dma_n, -- required to stop epyx cap to discharge (!)
-- interface with freezer (cartridge) logic
allow_serve => allow_serve,
serve_128 => serve_128, -- 8000-FFFF
serve_rom => serve_rom, -- ROML or ROMH
serve_io1 => serve_io1, -- IO1n
serve_io2 => serve_io2, -- IO2n
allow_write => allow_write,
-- kernal emulation
kernal_enable => control.kernal_enable,
kernal_probe => kernal_probe,
kernal_area => kernal_area,
force_ultimax => force_ultimax,
cpu_write => cpu_write,
epyx_timeout => epyx_timeout,
slot_req => slot_req,
slot_resp => slot_resp,
-- interface with hardware
BUFFER_ENn => BUFFER_ENn );
r_master: if not g_direct_dma generate
i_master: entity work.slot_master_v4
generic map (
g_start_in_stopped_state => g_boot_stop )
port map (
clock => clock,
reset => reset,
-- Cartridge pins
DMAn => dma_n,
BA => ba_i,
RWn_in => rwn_i,
RWn_out => rwn_o,
RWn_tri => open,
ADDRESS_out => address_out,
ADDRESS_tri_h => address_tri_h,
ADDRESS_tri_l => address_tri_l,
DATA_in => slot_data_i,
DATA_out => master_dout,
DATA_tri => master_dtri,
-- timing inputs
vic_cycle => vic_cycle,
phi2_recovered => phi2_recovered,
phi2_tick => phi2_tick_i,
do_sample_addr => do_sample_addr,
do_io_event => do_io_event,
reu_dma_n => reu_dma_n,
cmd_if_freeze => cmd_if_freeze,
-- request from the cpu to do a cycle on the cart bus
dma_req => dma_req,
dma_resp => dma_resp,
-- system control
stop_cond => control.c64_stop_mode,
c64_stop => control.c64_stop,
c64_stopped => status.c64_stopped );
end generate;
r_no_master: if g_direct_dma generate
process(clock)
begin
if rising_edge(clock) then
if phi2_fall = '1' then
status.c64_stopped <= control.c64_stop;
end if;
end if;
end process;
dma_n <= not (status.c64_stopped or not reu_dma_n or cmd_if_freeze);
RWN_out <= '1';
ADDRESS_out <= (others => '1');
ADDRESS_tri_h <= '0';
ADDRESS_tri_l <= '0';
direct_dma_req <= dma_req;
dma_resp <= direct_dma_resp;
end generate;
i_freeze: entity work.freezer
generic map (
g_ext_activate => g_ext_freeze_act )
port map (
clock => clock,
reset => reset,
RST_in => reset_button,
button_freeze => freeze_button,
cpu_cycle_done => do_io_event,
cpu_write => cpu_write,
activate => freeze_activate,
freezer_state => freezer_state,
unfreeze => unfreeze,
freeze_trig => freeze_trig,
freeze_act => freeze_active );
i_cart_logic: entity work.all_carts_v5
generic map (
g_eeprom => g_eeprom,
g_kernal_base => g_kernal_base,
g_georam_base => g_ram_base_reu,
g_rom_base => g_rom_base_cart,
g_ram_base => g_ram_base_cart )
port map (
clock => clock,
reset => reset,
RST_in => reset_button,
c64_reset => control.c64_reset,
freeze_trig => freeze_trig,
freeze_act => freeze_active,
unfreeze => unfreeze,
cart_active => status.cart_active,
cart_logic => control.cartridge_type,
cart_variant => control.cartridge_variant,
cart_force => control.cartridge_force,
cart_kill => control.cartridge_kill,
epyx_timeout => epyx_timeout,
slot_req => slot_req,
slot_resp => slot_resp_cart,
io_req_eeprom => io_req_eeprom,
io_resp_eeprom => io_resp_eeprom,
mem_addr => mem_req_32_slot.address,
serve_enable => serve_enable,
serve_vic => serve_vic,
serve_128 => serve_128, -- 8000-FFFF
serve_rom => serve_rom, -- ROML or ROMH
serve_io1 => serve_io1, -- IO1n
serve_io2 => serve_io2, -- IO2n
allow_write => allow_write,
kernal_area => kernal_area,
kernal_enable => control.kernal_enable,
irq_n => irq_n,
nmi_n => nmi_n,
exrom_n => exrom_n,
game_n => game_n,
CART_LEDn => cart_led_n,
size_ctrl => control.reu_size );
r_sid: if g_implement_sid generate
begin
i_sid: entity work.sid_peripheral
generic map (
g_8voices => g_8voices,
g_num_voices => g_sid_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_sid,
io_resp => io_resp_sid,
slot_req => slot_req,
slot_resp => slot_resp_sid,
start_iter => phi2_tick_avail,
sample_left => sid_left,
sample_right => sid_right );
end generate;
g_cmd: if g_command_intf generate
i_cmd: entity work.command_interface
port map (
clock => clock,
reset => reset,
-- C64 side interface
slot_req => slot_req,
slot_resp => slot_resp_cmd,
freeze => cmd_if_freeze,
write_ff00 => write_ff00,
-- io interface for local cpu
io_req => io_req_cmd, -- we get an 8K range
io_resp => io_resp_cmd,
io_irq => io_irq_cmd );
end generate;
write_ff00 <= '1' when slot_req.late_write='1' and slot_req.io_address=X"FF00" else '0';
g_reu: if g_ram_expansion generate
begin
i_reu: entity work.reu
generic map (
g_extended => g_extended_reu,
g_ram_base => unsigned(g_ram_base_reu),
g_ram_tag => g_tag_reu )
port map (
clock => clock,
reset => actual_c64_reset,
-- register interface
slot_req => slot_req,
slot_resp => slot_resp_reu,
write_ff00 => write_ff00,
-- system interface
phi2_tick => do_io_event,
reu_dma_n => reu_dma_n,
inhibit => status.c64_stopped,
size_ctrl => control.reu_size,
enable => control.reu_enable,
-- memory interface
mem_req => mem_req_reu,
mem_resp => mem_resp_reu,
dma_req => dma_req_reu,
dma_resp => dma_resp_reu );
end generate;
r_copper: if g_vic_copper generate
i_copper: entity work.copper
port map (
clock => clock,
reset => reset,
irq_n => irqn_i,
phi2_tick => phi2_tick_i,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
io_req => io_req_copper,
io_resp => io_resp_copper,
dma_req => dma_req_copper,
dma_resp => dma_resp_copper,
slot_req => slot_req,
slot_resp => open ); -- never required, just snoop!
end generate;
r_sampler: if g_sampler generate
signal local_io_req : t_io_req := c_io_req_init;
signal local_io_resp : t_io_resp;
signal io_req_samp : t_io_req;
signal io_resp_samp : t_io_resp;
signal irq_samp : std_logic;
begin
i_io_bridge: entity work.slot_to_io_bridge
generic map (
g_io_base => X"48000", -- dont care in this context
g_slot_start => "100100000",
g_slot_stop => "111111111" )
port map (
clock => clock,
reset => reset,
enable => control.sampler_enable,
irq_in => irq_samp,
slot_req => slot_req,
slot_resp => slot_resp_samp,
io_req => local_io_req,
io_resp => local_io_resp );
i_io_arb_sampler: entity work.io_bus_arbiter_pri
generic map (
g_ports => 2 )
port map (
clock => clock,
reset => reset,
reqs(0) => io_req_samp_cpu,
reqs(1) => local_io_req,
resps(0) => io_resp_samp_cpu,
resps(1) => local_io_resp,
req => io_req_samp,
resp => io_resp_samp );
i_sampler: entity work.sampler
generic map (
g_clock_freq => g_clock_freq,
g_num_voices => 8 )
port map (
clock => clock,
reset => actual_c64_reset,
io_req => io_req_samp,
io_resp => io_resp_samp,
mem_req => mem_req_samp,
mem_resp => mem_resp_samp,
irq => irq_samp,
sample_L => samp_left,
sample_R => samp_right,
new_sample => open );
end generate;
r_acia: if g_acia generate
i_acia: entity work.acia6551
port map (
clock => clock,
reset => reset,
c64_reset => actual_c64_reset,
slot_tick => phi2_tick_i,
slot_req => slot_req,
slot_resp => slot_resp_acia,
io_req => io_req_acia,
io_resp => io_resp_acia,
io_irq => io_irq_acia
);
end generate;
r_no_acia: if not g_acia generate
i_dummy: entity work.io_dummy
port map (
clock => clock,
io_req => io_req_acia,
io_resp => io_resp_acia
);
end generate;
slot_resp <= or_reduce(slot_resp_reu & slot_resp_cart & slot_resp_sid & slot_resp_cmd &
slot_resp_samp & slot_resp_acia);
p_probe_address_delay: process(clock)
variable kernal_probe_d : std_logic_vector(2 downto 0) := (others => '0');
begin
if rising_edge(clock) then
kernal_addr_out <= kernal_probe_d(0);
kernal_probe_d := kernal_probe & kernal_probe_d(kernal_probe_d'high downto 1);
end if;
end process;
process(address_out, kernal_addr_out, kernal_probe, address_tri_l, address_tri_h)
begin
slot_addr_o <= unsigned(address_out);
slot_addr_tl <= address_tri_l;
slot_addr_th <= address_tri_h;
if kernal_addr_out='1' and kernal_probe='1' then
slot_addr_o(15 downto 13) <= "101";
slot_addr_th <= '1';
end if;
end process;
slot_data_o <= slave_dout when (slave_dtri='1') else
master_dout when (master_dtri='1') else
X"FF";
slot_data_t <= slave_dtri or master_dtri;
-- open drain outputs
irqn_o <= '0' when irq_n='0' or slot_resp.irq='1' else '1';
nmin_o <= '0' when (control.c64_nmi='1') or (nmi_n='0') or (slot_resp.nmi='1') else '1';
rstn_o <= '0' when (reset_button='1' and status.c64_stopped='0') or
(control.c64_reset='1') else '1';
dman_o <= '0' when (dma_n='0' or kernal_probe='1') else '1';
process(control, status, exrom_n, game_n, force_ultimax, kernal_probe)
begin
exromn_o <= '1';
gamen_o <= '1';
if (force_ultimax = '1') or (control.c64_ultimax = '1') then
gamen_o <= '0';
elsif kernal_probe = '1' then
gamen_o <= '0';
exromn_o <= '0';
else
if (status.cart_active='1' and exrom_n='0') then
exromn_o <= '0';
end if;
if (status.cart_active='1' and game_n='0') then
gamen_o <= '0';
end if;
end if;
end process;
-- arbitration
i_dma_arb: entity work.dma_bus_arbiter_pri
generic map (
g_ports => 3 )
port map (
clock => clock,
reset => reset,
reqs(0) => dma_req_io,
reqs(1) => dma_req_reu,
reqs(2) => dma_req_copper,
resps(0) => dma_resp_io,
resps(1) => dma_resp_reu,
resps(2) => dma_resp_copper,
req => dma_req,
resp => dma_resp );
i_conv32_reu: entity work.mem_to_mem32(route_through)
generic map (
g_big_endian => g_big_endian )
port map(
clock => clock,
reset => reset,
mem_req_8 => mem_req_reu,
mem_resp_8 => mem_resp_reu,
mem_req_32 => mem_req_32_reu,
mem_resp_32 => mem_resp_32_reu );
i_conv32_samp: entity work.mem_to_mem32(route_through)
generic map (
g_big_endian => g_big_endian )
port map(
clock => clock,
reset => reset,
mem_req_8 => mem_req_samp,
mem_resp_8 => mem_resp_samp,
mem_req_32 => mem_req_32_samp,
mem_resp_32 => mem_resp_32_samp );
i_mem_arb: entity work.mem_bus_arbiter_pri_32
generic map (
g_ports => 3 )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_32_slot,
reqs(1) => mem_req_32_reu,
reqs(2) => mem_req_32_samp,
-- reqs(3) => mem_req_trace,
resps(0) => mem_resp_32_slot,
resps(1) => mem_resp_32_reu,
resps(2) => mem_resp_32_samp,
-- resps(3) => mem_resp_trace,
req => mem_req,
resp => mem_resp );
-- Delay the inhibit one clock cycle, because our
-- arbiter introduces one clock cycle delay as well.
process(clock)
begin
if rising_edge(clock) then
memctrl_inhibit <= timing_inhibit;
status.c64_vcc <= VCC;
status.exrom <= not exromn_i;
status.game <= not gamen_i;
status.reset_in <= not rstn_i;
end if;
end process;
phi2_tick_avail <= phi2_tick_i;
phi2_tick <= phi2_tick_avail;
c64_stopped <= status.c64_stopped;
ultimax <= control.c64_ultimax;
-- write 0x54 to $DFFE to generate a trigger
sw_trigger <= '1' when slot_req.io_write = '1' and slot_req.io_address(8 downto 0) = "111111110" and slot_req.data = X"54" else '0';
-- write 0x0D to $DFFF to generate a sync
sync <= '1' when slot_req.io_write = '1' and slot_req.io_address(8 downto 0) = "111111111" and slot_req.data = X"0D" else '0';
status.nmi <= not nmin_i when rising_edge(clock);
b_debug: block
signal phi_c : std_logic := '0';
signal phi_d1 : std_logic := '0';
signal phi_d2 : std_logic := '0';
signal vector_c : std_logic_vector(31 downto 0) := (others => '0');
signal vector_d1 : std_logic_vector(31 downto 0) := (others => '0');
signal vector_d2 : std_logic_vector(31 downto 0) := (others => '0');
signal ba_history : std_logic_vector(2 downto 0) := (others => '0');
alias cpu_cycle_enable : std_logic is debug_select(0);
alias vic_cycle_enable : std_logic is debug_select(1);
alias drv_enable : std_logic is debug_select(2);
begin
-- Debug Stream
process(clock)
variable vector_in : std_logic_vector(31 downto 0);
begin
if rising_edge(clock) then
vector_in := phi2_i & gamen_i & exromn_i & not (romhn_i and romln_i) &
ba_i & irqn_i & nmin_i & rwn_i &
slot_data_i & std_logic_vector(slot_addr_i);
phi_c <= phi2_i;
phi_d1 <= phi_c;
phi_d2 <= phi_d1;
vector_c <= vector_in;
vector_d1 <= vector_c;
vector_d2 <= vector_d1;
-- BA 1 1 1 0 0 0 0 0 0 0 1 1 1
-- BA0 1 1 1 1 0 0 0 0 0 0 0 1 1
-- BA1 1 1 1 1 1 0 0 0 0 0 0 0 1
-- BA2 1 1 1 1 1 1 0 0 0 0 0 0 0
-- CPU 1 1 1 1 1 1 0 0 0 0 1 1 1
--
debug_valid <= '0';
debug_data <= vector_d2;
if phi_d2 /= phi_d1 then
if phi_d2 = '1' then
ba_history <= ba_history(1 downto 0) & vector_d2(27); -- BA position!
end if;
if phi_d2 = '1' then
if (vector_d2(27) = '1' or ba_history /= "000" or drv_enable = '1') and cpu_cycle_enable = '1' then
debug_valid <= '1';
elsif vic_cycle_enable = '1' then
debug_valid <= '1';
end if;
elsif vic_cycle_enable = '1' then
debug_valid <= '1';
end if;
end if;
end if;
end process;
end block;
end structural;
| gpl-3.0 | 9d570451ac91a95b52218c0a5337be36 | 0.475885 | 3.383844 | false | false | false | false |
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