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markusC64/1541ultimate2 | fpga/io/usb/vhdl_source/usb1_ulpi_bus.vhd | 2 | 7,417 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb1_ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of usb1_ulpi_bus : entity is "yes";
end usb1_ulpi_bus;
architecture gideon of usb1_ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal reg_cmd_d4 : std_logic;
signal reg_cmd_d5 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
type t_state is ( idle, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d5;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
reg_cmd_d4 <= reg_cmd_d3;
reg_cmd_d5 <= reg_cmd_d4;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
state <= transmit;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing_data =>
if ULPI_NXT='1' and ULPI_DIR='0' then
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '0';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start;
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and tx_valid and not ulpi_last;
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z');
end gideon;
| gpl-3.0 | 1ce37b65a30415da75de86ae5a98668b | 0.44789 | 3.666337 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/cia_pkg.vhd | 1 | 3,109 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cia_pkg is
type pio_t is
record
pra : std_logic_vector(7 downto 0);
ddra : std_logic_vector(7 downto 0);
prb : std_logic_vector(7 downto 0);
ddrb : std_logic_vector(7 downto 0);
end record;
constant pio_default : pio_t := (others => (others => '0'));
type timer_t is
record
run : std_logic;
pbon : std_logic;
outmode : std_logic;
runmode : std_logic;
load : std_logic;
inmode : std_logic_vector(1 downto 0);
end record;
constant timer_default : timer_t := (
run => '0',
pbon => '0',
outmode => '0',
runmode => '0',
load => '0',
inmode => "00" );
type time_t is
record
pm : std_logic;
hr : unsigned(4 downto 0);
minh : unsigned(2 downto 0);
minl : unsigned(3 downto 0);
sech : unsigned(2 downto 0);
secl : unsigned(3 downto 0);
tenths : unsigned(3 downto 0);
end record;
constant time_default : time_t := ('1', "10001", "000", X"0", "000", X"0", X"0");
constant alarm_default : time_t := ('0', "00000", "000", X"0", "000", X"0", X"0");
type tod_t is
record
alarm_set : std_logic;
freq_sel : std_logic;
tod : time_t;
alarm : time_t;
end record;
constant tod_default : tod_t := (
alarm_set => '0',
freq_sel => '0',
tod => time_default,
alarm => alarm_default );
procedure do_tod_tick(signal t : inout time_t);
end;
package body cia_pkg is
procedure do_tod_tick(signal t : inout time_t) is
begin
if t.tenths=X"9" then
t.tenths <= X"0";
if t.secl=X"9" then
t.secl <= X"0";
if t.sech="101" then
t.sech <= "000";
if t.minl=X"9" then
t.minl <= X"0";
if t.minh="101" then
t.minh <= "000";
if t.hr="01001" then
t.hr <= "10000";
elsif t.hr="01111" then
t.hr <= "00000";
elsif t.hr="11111" then
t.hr <= "10000";
elsif t.hr="10010" then
t.hr <= "00001";
elsif t.hr="10001" then
t.hr <= "10010";
t.pm <= not t.pm;
else
t.hr <= t.hr + 1;
end if;
else
t.minh <= t.minh + 1;
end if;
else
t.minl <= t.minl + 1;
end if;
else
t.sech <= t.sech + 1;
end if;
else
t.secl <= t.secl + 1;
end if;
else
t.tenths <= t.tenths + 1;
end if;
end procedure do_tod_tick;
end; | gpl-3.0 | e4d9324252eaaac3db091703f9ae66c4 | 0.41203 | 3.493258 | false | false | false | false |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/sp_diode.vhdl | 15 | 539 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY SP_DIODE IS
GENERIC ( RS : REAL := 1.0;
VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
M : REAL := 0.5;
PB : REAL := 1.0;
TT : REAL := 0.0;
CJ0 : REAL := 0.0;
N : REAL := 1.0;
ISS : REAL := 10.0e-14 );
PORT ( terminal KATHODE : electrical;
terminal ANODE : electrical );
END ENTITY SP_DIODE;
| gpl-2.0 | 2632134c0c70759e600882a722fb28ea | 0.567718 | 2.483871 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/ultimate_fpga/vhdl_source/u2p_nios2_solo.vhd | 1 | 33,598 | -------------------------------------------------------------------------------
-- Title : u2p_nios
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel based on the "solo" nios; without Altera DDR2 ctrl.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.my_math_pkg.all;
use work.audio_type_pkg.all;
entity u2p_nios_solo is
generic (
g_dual_drive : boolean := true );
port (
-- slot side
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : inout std_logic;
SLOT_BUFFER_ENn : out std_logic;
SLOT_ADDR : inout unsigned(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : out std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : in std_logic;
SLOT_ROMLn : in std_logic;
SLOT_IO1n : in std_logic;
SLOT_IO2n : in std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
SLOT_DRV_RST : out std_logic := '0';
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_DM : inout std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Misc
BOARD_REVn : in std_logic_vector(4 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_nios_solo is
component nios_solo is
port (
clk_clk : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component nios_solo;
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
signal por_n : std_logic;
signal ref_reset : std_logic;
signal por_count : unsigned(15 downto 0) := (others => '0');
signal led_n : std_logic_vector(0 to 3);
signal RSTn_out : std_logic;
signal irq_oc, nmi_oc, rst_oc, dma_oc, exrom_oc, game_oc : std_logic;
signal slot_addr_o : unsigned(15 downto 0);
signal slot_addr_tl : std_logic;
signal slot_addr_th : std_logic;
signal slot_data_o : std_logic_vector(7 downto 0);
signal slot_data_t : std_logic;
signal slot_rwn_o : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal eth_reset : std_logic;
signal ulpi_reset_req : std_logic;
signal button_i : std_logic_vector(2 downto 0);
signal buffer_en : std_logic;
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal is_idle : std_logic;
signal cpu_mem_req : t_mem_req_32;
signal cpu_mem_resp : t_mem_resp_32;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal uart_txd_from_logic : std_logic;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_scl_i : std_logic;
signal i2c_scl_o : std_logic;
signal mdio_o : std_logic;
signal sw_trigger : std_logic;
signal trigger : std_logic;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
signal sw_iec_o : std_logic_vector(3 downto 0);
signal sw_iec_i : std_logic_vector(3 downto 0);
-- Cassette
signal c2n_read_in : std_logic;
signal c2n_write_in : std_logic;
signal c2n_read_out : std_logic;
signal c2n_write_out : std_logic;
signal c2n_read_en : std_logic;
signal c2n_write_en : std_logic;
signal c2n_sense_in : std_logic;
signal c2n_sense_out : std_logic;
signal c2n_motor_in : std_logic;
signal c2n_motor_out : std_logic;
-- io buses
signal io_irq : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_u2p_req : t_io_req;
signal io_u2p_resp : t_io_resp;
signal io_u2p_req_small : t_io_req;
signal io_u2p_resp_small: t_io_resp;
signal io_u2p_req_big : t_io_req;
signal io_u2p_resp_big : t_io_resp;
signal io_req_new_io : t_io_req;
signal io_resp_new_io : t_io_resp;
signal io_req_remote : t_io_req;
signal io_resp_remote : t_io_resp;
signal io_req_ddr2 : t_io_req;
signal io_resp_ddr2 : t_io_resp;
signal io_req_mixer : t_io_req;
signal io_resp_mixer : t_io_resp;
signal io_req_debug : t_io_req;
signal io_resp_debug : t_io_resp;
-- Parallel cable connection
signal drv_track_is_0 : std_logic;
signal drv_via1_port_a_o : std_logic_vector(7 downto 0);
signal drv_via1_port_a_i : std_logic_vector(7 downto 0);
signal drv_via1_port_a_t : std_logic_vector(7 downto 0);
signal drv_via1_ca2_o : std_logic;
signal drv_via1_ca2_i : std_logic;
signal drv_via1_ca2_t : std_logic;
signal drv_via1_cb1_o : std_logic;
signal drv_via1_cb1_i : std_logic;
signal drv_via1_cb1_t : std_logic;
-- audio
signal audio_speaker : signed(12 downto 0);
signal speaker_vol : std_logic_vector(3 downto 0);
signal ult_drive1 : signed(17 downto 0);
signal ult_drive2 : signed(17 downto 0);
signal ult_tape_r : signed(17 downto 0);
signal ult_tape_w : signed(17 downto 0);
signal ult_samp_l : signed(17 downto 0);
signal ult_samp_r : signed(17 downto 0);
signal ult_sid_1 : signed(17 downto 0);
signal ult_sid_2 : signed(17 downto 0);
signal c64_debug_select : std_logic_vector(2 downto 0);
signal c64_debug_data : std_logic_vector(31 downto 0);
signal c64_debug_valid : std_logic;
signal drv_debug_data : std_logic_vector(31 downto 0);
signal drv_debug_valid : std_logic;
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_last : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic := '1';
signal eth_u2p_data : std_logic_vector(7 downto 0);
signal eth_u2p_last : std_logic;
signal eth_u2p_valid : std_logic;
signal eth_u2p_ready : std_logic := '1';
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
begin
process(RMII_REFCLK)
begin
if rising_edge(RMII_REFCLK) then
if por_count = X"FFFF" then
por_n <= '1';
else
por_n <= '0';
por_count <= por_count + 1;
end if;
end if;
end process;
ref_reset <= not por_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => open );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => sys_reset,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => ulpi_reset_req,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
i_nios: nios_solo
port map (
clk_clk => sys_clock,
reset_reset_n => not sys_reset,
io_ack => io_resp.ack,
io_rdata => io_resp.data,
io_read => io_req.read,
io_wdata => io_req.data,
io_write => io_req.write,
unsigned(io_address) => io_req.address,
io_irq => io_irq,
io_u2p_ack => io_u2p_resp.ack,
io_u2p_rdata => io_u2p_resp.data,
io_u2p_read => io_u2p_req.read,
io_u2p_wdata => io_u2p_req.data,
io_u2p_write => io_u2p_req.write,
unsigned(io_u2p_address) => io_u2p_req.address,
io_u2p_irq => '0',
unsigned(mem_mem_req_address) => cpu_mem_req.address,
mem_mem_req_byte_en => cpu_mem_req.byte_en,
mem_mem_req_read_writen => cpu_mem_req.read_writen,
mem_mem_req_request => cpu_mem_req.request,
mem_mem_req_tag => cpu_mem_req.tag,
mem_mem_req_wdata => cpu_mem_req.data,
mem_mem_resp_dack_tag => cpu_mem_resp.dack_tag,
mem_mem_resp_data => cpu_mem_resp.data,
mem_mem_resp_rack_tag => cpu_mem_resp.rack_tag
);
i_split_u2p: entity work.io_bus_splitter
generic map (
g_range_lo => 16,
g_range_hi => 16,
g_ports => 2
)
port map (
clock => sys_clock,
req => io_u2p_req,
resp => io_u2p_resp,
reqs(0) => io_u2p_req_small,
reqs(1) => io_u2p_req_big,
resps(0) => io_u2p_resp_small,
resps(1) => io_u2p_resp_big
);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 9,
g_ports => 3
)
port map (
clock => sys_clock,
req => io_u2p_req_small,
resp => io_u2p_resp_small,
reqs(0) => io_req_new_io,
reqs(1) => io_req_ddr2,
reqs(2) => io_req_remote,
resps(0) => io_resp_new_io,
resps(1) => io_resp_ddr2,
resps(2) => io_resp_remote
);
i_split2: entity work.io_bus_splitter
generic map (
g_range_lo => 12,
g_range_hi => 12,
g_ports => 2
)
port map (
clock => sys_clock,
req => io_u2p_req_big,
resp => io_u2p_resp_big,
reqs(0) => io_req_mixer,
reqs(1) => io_req_debug,
resps(0) => io_resp_mixer,
resps(1) => io_resp_debug
);
i_memphy: entity work.ddr2_ctrl
port map (
ref_clock => RMII_REFCLK,
ref_reset => ref_reset,
sys_clock_o => sys_clock,
sys_reset_o => sys_reset,
clock => sys_clock,
reset => sys_reset,
io_req => io_req_ddr2,
io_resp => io_resp_ddr2,
inhibit => memctrl_inhibit,
is_idle => is_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_ODT => SDRAM_ODT,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA(1 downto 0),
SDRAM_DM => SDRAM_DM,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS
);
i_remote: entity work.update_io
port map (
clock => sys_clock,
reset => sys_reset,
slow_clock => audio_clock,
slow_reset => audio_reset,
io_req => io_req_remote,
io_resp => io_resp_remote,
flash_selck => FLASH_SELCK,
flash_sel => FLASH_SEL
);
i_u2p_io: entity work.u2p_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_new_io,
io_resp => io_resp_new_io,
mdc => MDIO_CLK,
mdio_i => MDIO_DATA,
mdio_o => mdio_o,
i2c_scl_i => i2c_scl_i,
i2c_scl_o => i2c_scl_o,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
iec_i => sw_iec_i,
iec_o => sw_iec_o,
board_rev => not BOARD_REVn,
eth_irq_i => ETH_IRQn,
speaker_en => SPEAKER_ENABLE,
speaker_vol=> speaker_vol,
hub_reset_n=> HUB_RESETn,
ulpi_reset => ulpi_reset_req,
buffer_en => buffer_en
);
i2c_scl_i <= I2C_SCL and I2C_SCL_18;
i2c_sda_i <= I2C_SDA and I2C_SDA_18;
I2C_SCL <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA <= '0' when i2c_sda_o = '0' else 'Z';
I2C_SCL_18 <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA_18 <= '0' when i2c_sda_o = '0' else 'Z';
MDIO_DATA <= '0' when mdio_o = '0' else 'Z';
i_logic: entity work.ultimate_logic_32
generic map (
g_simulation => false,
g_ultimate2plus => true,
g_clock_freq => 62_500_000,
g_numerator => 32,
g_denominator => 125,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_microblaze => false,
g_big_endian => false,
g_icap => false,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => g_dual_drive,
g_mm_drive => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_8voices => true,
g_hardware_iec => true,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => true,
g_acia => true,
g_rmii => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
ext_io_req => io_req,
ext_io_resp => io_resp,
ext_mem_req => cpu_mem_req,
ext_mem_resp=> cpu_mem_resp,
cpu_irq => io_irq,
-- slot side
BUFFER_ENn => open,
VCC => SLOT_VCC,
phi2_i => SLOT_PHI2,
dotclk_i => SLOT_DOTCLK,
rstn_i => SLOT_RSTn,
rstn_o => RSTn_out,
slot_addr_o => slot_addr_o,
slot_addr_i => SLOT_ADDR,
slot_addr_tl=> slot_addr_tl,
slot_addr_th=> slot_addr_th,
slot_data_o => slot_data_o,
slot_data_i => SLOT_DATA,
slot_data_t => slot_data_t,
rwn_i => SLOT_RWn,
rwn_o => slot_rwn_o,
exromn_i => SLOT_EXROMn,
exromn_o => exrom_oc,
gamen_i => SLOT_GAMEn,
gamen_o => game_oc,
irqn_i => SLOT_IRQn,
irqn_o => irq_oc,
nmin_i => SLOT_NMIn,
nmin_o => nmi_oc,
ba_i => SLOT_BA,
dman_o => dma_oc,
romhn_i => SLOT_ROMHn,
romln_i => SLOT_ROMLn,
io1n_i => SLOT_IO1n,
io2n_i => SLOT_IO2n,
-- local bus side
mem_inhibit => memctrl_inhibit,
mem_req => mem_req,
mem_resp => mem_resp,
-- Audio outputs
audio_speaker => audio_speaker,
speaker_vol => speaker_vol,
aud_drive1 => ult_drive1,
aud_drive2 => ult_drive2,
aud_tape_r => ult_tape_r,
aud_tape_w => ult_tape_w,
aud_samp_l => ult_samp_l,
aud_samp_r => ult_samp_r,
aud_sid_1 => ult_sid_1,
aud_sid_2 => ult_sid_2,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
MOTOR_LEDn => led_n(0),
DISK_ACTn => led_n(1),
CART_LEDn => led_n(2),
SDACT_LEDn => led_n(3),
-- Parallel cable pins
drv_track_is_0 => drv_track_is_0,
drv_via1_port_a_o => drv_via1_port_a_o,
drv_via1_port_a_i => drv_via1_port_a_i,
drv_via1_port_a_t => drv_via1_port_a_t,
drv_via1_ca2_o => drv_via1_ca2_o,
drv_via1_ca2_i => drv_via1_ca2_i,
drv_via1_ca2_t => drv_via1_ca2_t,
drv_via1_cb1_o => drv_via1_cb1_o,
drv_via1_cb1_i => drv_via1_cb1_i,
drv_via1_cb1_t => drv_via1_cb1_t,
-- Debug UART
UART_TXD => uart_txd_from_logic,
UART_RXD => UART_RXD,
-- Debug buses
drv_debug_data => drv_debug_data,
drv_debug_valid => drv_debug_valid,
c64_debug_data => c64_debug_data,
c64_debug_valid => c64_debug_valid,
c64_debug_select => c64_debug_select,
-- SD Card Interface
SD_SSn => open,
SD_CLK => open,
SD_MOSI => open,
SD_MISO => '1',
SD_CARDDETn => '1',
SD_DATA => open,
-- RTC Interface
RTC_CS => open,
RTC_SCK => open,
RTC_MOSI => open,
RTC_MISO => '1',
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
c2n_read_in => c2n_read_in,
c2n_write_in => c2n_write_in,
c2n_read_out => c2n_read_out,
c2n_write_out => c2n_write_out,
c2n_read_en => c2n_read_en,
c2n_write_en => c2n_write_en,
c2n_sense_in => c2n_sense_in,
c2n_sense_out => c2n_sense_out,
c2n_motor_in => c2n_motor_in,
c2n_motor_out => c2n_motor_out,
-- Ethernet Interface (RMII)
eth_clock => RMII_REFCLK,
eth_reset => eth_reset,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_u2p_data,
eth_tx_eof => eth_u2p_last,
eth_tx_valid => eth_u2p_valid,
eth_tx_ready => eth_u2p_ready,
-- Buttons
sw_trigger => sw_trigger,
trigger => sw_trigger,
BUTTON => button_i );
-- Parallel cable not implemented. This is the way to stub it...
drv_via1_port_a_i(7 downto 1) <= drv_via1_port_a_o(7 downto 1) or not drv_via1_port_a_t(7 downto 1);
drv_via1_port_a_i(0) <= drv_track_is_0; -- for 1541C
drv_via1_ca2_i <= drv_via1_ca2_o or not drv_via1_ca2_t;
drv_via1_cb1_i <= drv_via1_cb1_o or not drv_via1_cb1_t;
process(sys_clock)
variable c, d : std_logic := '0';
begin
if rising_edge(sys_clock) then
trigger <= d;
d := c;
c := button_i(0);
end if;
end process;
SLOT_RSTn <= '0' when RSTn_out = '0' else 'Z';
SLOT_DRV_RST <= not RSTn_out when rising_edge(sys_clock); -- Drive this pin HIGH when we want to reset the C64 (uses NFET on Rev.E boards)
SLOT_ADDR(15 downto 12) <= slot_addr_o(15 downto 12) when slot_addr_th = '1' else (others => 'Z');
SLOT_ADDR(11 downto 00) <= slot_addr_o(11 downto 00) when slot_addr_tl = '1' else (others => 'Z');
SLOT_DATA <= slot_data_o when slot_data_t = '1' else (others => 'Z');
SLOT_RWn <= slot_rwn_o when slot_addr_tl = '1' else 'Z';
irq_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => irq_oc, oc_out => SLOT_IRQn);
nmi_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => nmi_oc, oc_out => SLOT_NMIn);
dma_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => dma_oc, oc_out => SLOT_DMAn);
exr_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => exrom_oc, oc_out => SLOT_EXROMn);
gam_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => game_oc, oc_out => SLOT_GAMEn);
LED_MOTORn <= led_n(0) xor sys_reset;
LED_DISKn <= led_n(1) xor sys_reset;
LED_CARTn <= led_n(2) xor sys_reset;
LED_SDACTn <= led_n(3) xor sys_reset;
IEC_SRQ_IN <= '0' when iec_srq_o = '0' or sw_iec_o(3) = '0' else 'Z';
IEC_ATN <= '0' when iec_atn_o = '0' or sw_iec_o(2) = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' or sw_iec_o(1) = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' or sw_iec_o(0) = '0' else 'Z';
sw_iec_i <= IEC_SRQ_IN & IEC_ATN & IEC_DATA & IEC_CLOCK;
button_i <= not BUTTON;
ULPI_RESET <= por_n;
UART_TXD <= uart_txd_from_logic; -- and uart_txd_from_qsys;
-- Tape
c2n_motor_in <= CAS_MOTOR;
CAS_SENSE <= '0' when c2n_sense_out = '1' else 'Z';
c2n_sense_in <= not CAS_SENSE;
CAS_READ <= c2n_read_out when c2n_read_en = '1' else 'Z';
c2n_read_in <= CAS_READ;
CAS_WRITE <= c2n_write_out when c2n_write_en = '1' else 'Z';
c2n_write_in <= CAS_WRITE;
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_divider => 10,
g_width => audio_speaker'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => audio_speaker,
dac_out => SPEAKER_DATA );
b_audio: block
signal aud_drive1 : signed(17 downto 0);
signal aud_drive2 : signed(17 downto 0);
signal aud_tape_r : signed(17 downto 0);
signal aud_tape_w : signed(17 downto 0);
signal aud_samp_l : signed(17 downto 0);
signal aud_samp_r : signed(17 downto 0);
signal aud_sid_1 : signed(17 downto 0);
signal aud_sid_2 : signed(17 downto 0);
signal audio_sid1 : std_logic_vector(17 downto 0);
signal audio_sid2 : std_logic_vector(17 downto 0);
signal codec_left_in : std_logic_vector(23 downto 0);
signal codec_right_in : std_logic_vector(23 downto 0);
signal codec_left_out : std_logic_vector(23 downto 0);
signal codec_right_out : std_logic_vector(23 downto 0);
signal audio_get_sample : std_logic;
signal sys_get_sample : std_logic;
signal inputs : t_audio_array(0 to 9);
begin
-- the SID sound from the socket comes in from the codec
i2s: entity work.i2s_serializer
port map (
clock => audio_clock,
reset => audio_reset,
i2s_out => AUDIO_SDO,
i2s_in => AUDIO_SDI,
i2s_bclk => AUDIO_BCLK,
i2s_fs => AUDIO_LRCLK,
sample_pulse => audio_get_sample,
left_sample_out => codec_left_in,
right_sample_out => codec_right_in,
left_sample_in => codec_left_out,
right_sample_in => codec_right_out );
AUDIO_MCLK <= audio_clock;
i_sync_get: entity work.pulse_synchronizer
port map (
clock_in => audio_clock,
pulse_in => audio_get_sample,
clock_out => sys_clock,
pulse_out => sys_get_sample
);
i_ultfilt1: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_drive1, audio_clock, aud_drive1 );
i_ultfilt2: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_drive2, audio_clock, aud_drive2 );
i_ultfilt3: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_tape_r, audio_clock, aud_tape_r );
i_ultfilt4: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_tape_w, audio_clock, aud_tape_w );
i_ultfilt5: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_samp_l, audio_clock, aud_samp_l );
i_ultfilt6: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_samp_r, audio_clock, aud_samp_r );
i_ultfilt7: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_sid_1, audio_clock, aud_sid_1 );
i_ultfilt8: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_sid_2, audio_clock, aud_sid_2 );
inputs(0) <= aud_sid_1;
inputs(1) <= aud_sid_2;
inputs(2) <= signed(codec_left_in(23 downto 6));
inputs(3) <= signed(codec_right_in(23 downto 6));
inputs(4) <= aud_samp_l;
inputs(5) <= aud_samp_r;
inputs(6) <= aud_drive1;
inputs(7) <= aud_drive2;
inputs(8) <= aud_tape_r;
inputs(9) <= aud_tape_w;
-- Now we have ten sources, all in audio domain, let's do some mixing
i_mixer: entity work.generic_mixer
generic map(
g_num_sources => 10
)
port map(
clock => audio_clock,
reset => audio_reset,
start => audio_get_sample,
sys_clock => sys_clock,
req => io_req_mixer,
resp => io_resp_mixer,
inputs => inputs,
out_L => codec_left_out,
out_R => codec_right_out
);
end block;
SLOT_BUFFER_ENn <= not buffer_en;
i_debug_eth: entity work.eth_debug_stream
port map (
eth_clock => RMII_REFCLK,
eth_reset => eth_reset,
eth_u2p_data => eth_u2p_data,
eth_u2p_last => eth_u2p_last,
eth_u2p_valid => eth_u2p_valid,
eth_u2p_ready => eth_u2p_ready,
eth_tx_data => eth_tx_data,
eth_tx_last => eth_tx_last,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
sys_clock => sys_clock,
sys_reset => sys_reset,
io_req => io_req_debug,
io_resp => io_resp_debug,
c64_debug_select => c64_debug_select,
c64_debug_data => c64_debug_data,
c64_debug_valid => c64_debug_valid,
drv_debug_data => drv_debug_data,
drv_debug_valid => drv_debug_valid,
IEC_ATN => IEC_ATN,
IEC_CLOCK => IEC_CLOCK,
IEC_DATA => IEC_DATA
);
-- Transceiver
i_rmii: entity work.rmii_transceiver
port map (
clock => RMII_REFCLK,
reset => eth_reset,
rmii_crs_dv => RMII_CRS_DV,
rmii_rxd => RMII_RX_DATA,
rmii_tx_en => RMII_TX_EN,
rmii_txd => RMII_TX_DATA,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_eof => eth_tx_last,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => '0' );
end architecture;
| gpl-3.0 | a19e979f3425a71bbf7a4740057df3d4 | 0.49122 | 3.148828 | false | false | false | false |
chiggs/nvc | test/regress/case3.vhd | 5 | 1,231 | entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
decode_z: with x(3 downto 0) select z <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
stim: process is
begin
wait for 0 ns;
assert y = 0;
assert z = 0;
x <= X"4";
wait for 1 ns;
assert y = 4;
assert y = 4;
x <= X"f";
wait for 1 ns;
assert y = 15;
assert z = 15;
wait;
end process;
end architecture;
| gpl-3.0 | e19c72286a45b507c8f23830b211b7df | 0.41186 | 3.256614 | false | false | false | false |
nussbrot/AdvPT | wb_i2c_bridge/vhdl/wb_i2c_bridge.vhd | 2 | 21,678 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2015 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project : Solectrix Global Library
-- File : wb_i2c_bridge.vhd
-- Created : 23.11.2015
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--*
--* @short WB to I2C Master bridge (Byte/Word accesses; 14 Bit address)
--*
--* @author akoehler
--* @date 23.11.2015
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- 23.11.2015 akoehler: Created
-- 03.05.2016 tstoehr: Update to i2c bridge / makes 8 bit i2c transfers possible
-- 13.05.2016 tstoehr: Updated signal initialisations
-- 18.05.2017 sforster: Rework according to detailed design
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY rtl_lib;
-------------------------------------------------------------------------------
ENTITY wb_i2c_bridge IS
GENERIC(
g_transaction_bytes : INTEGER RANGE 1 TO 2 := 1); -- 1: Byte; 2: Word
PORT (
-- clock/reset
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
-- Wishbone slave
i_wb_cyc : IN STD_LOGIC;
i_wb_stb : IN STD_LOGIC;
i_wb_we : IN STD_LOGIC;
i_wb_sel : IN STD_LOGIC_VECTOR(g_transaction_bytes -1 DOWNTO 0);
i_wb_addr : IN STD_LOGIC_VECTOR( 13 DOWNTO 0);
i_wb_data : IN STD_LOGIC_VECTOR(g_transaction_bytes*8-1 DOWNTO 0);
o_wb_data : OUT STD_LOGIC_VECTOR(g_transaction_bytes*8-1 DOWNTO 0);
o_wb_ack : OUT STD_LOGIC;
-- I2C master
i_scl_pad : IN STD_LOGIC;
o_scl_pad : OUT STD_LOGIC;
o_scl_padoen : OUT STD_LOGIC;
i_sda_pad : IN STD_LOGIC;
o_sda_pad : OUT STD_LOGIC;
o_sda_padoen : OUT STD_LOGIC;
-- configuration
i_cfg_core_en : IN STD_LOGIC := '1';
i_cfg_clk_div : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
i_cfg_dev_addr : IN STD_LOGIC_VECTOR( 6 DOWNTO 0);
-- status/error
o_status : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_err_irq : OUT STD_LOGIC);
END ENTITY wb_i2c_bridge;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF wb_i2c_bridge IS
-----------------------------------------------------------------------------
-- TYPEs
-----------------------------------------------------------------------------
TYPE t_status_reg IS RECORD
i2c_carrier_idle : STD_LOGIC;
i2c_core_idle : STD_LOGIC;
i2c_core_en : STD_LOGIC;
trx_acc_type : STD_LOGIC;
trx_err_nack_rep_dev_adr : STD_LOGIC;
trx_err_nack_dat_lsb : STD_LOGIC;
trx_err_nack_dat_msb : STD_LOGIC;
trx_err_nack_adr_lsb : STD_LOGIC;
trx_err_nack_adr_msb : STD_LOGIC;
trx_err_nack_dev_adr : STD_LOGIC;
trx_err_arb_rep_dev_adr : STD_LOGIC;
trx_err_arb_restart : STD_LOGIC;
trx_err_arb_dat_lsb : STD_LOGIC;
trx_err_arb_dat_msb : STD_LOGIC;
trx_err_arb_adr_lsb : STD_LOGIC;
trx_err_arb_adr_msb : STD_LOGIC;
trx_err_arb_dev_adr : STD_LOGIC;
trx_err_arb_start : STD_LOGIC;
trx_adr_err : STD_LOGIC;
END RECORD;
-----------------------------------------------------------------------------
TYPE t_fsm_states IS (idle, i2c_start, dev_adr, reg_adr_msb, reg_adr_lsb,
tx_reg_dat_msb, tx_reg_dat_lsb, i2c_restart,
rep_dev_adr, rx_reg_dat_msb, rx_reg_dat_lsb,
abort, i2c_stop, done);
-----------------------------------------------------------------------------
-- SIGNALs
-----------------------------------------------------------------------------
SIGNAL s_fsm_state : t_fsm_states;
SIGNAL s_status_reg : t_status_reg;
SIGNAL s_trx_error : STD_LOGIC; -- I2C transmission error
-- Wishbone
SIGNAL s_wb_ack : STD_LOGIC;
SIGNAL s_wb_dat_o : STD_LOGIC_VECTOR(g_transaction_bytes*8-1 DOWNTO 0);
-- I2C command/data signals for byte controller
SIGNAL s_i2c_start : STD_LOGIC;
SIGNAL s_i2c_stop : STD_LOGIC;
SIGNAL s_i2c_read : STD_LOGIC;
SIGNAL s_i2c_write : STD_LOGIC;
SIGNAL s_i2c_ack_in : STD_LOGIC;
SIGNAL s_i2c_cmd_done : STD_LOGIC;
SIGNAL s_i2c_ack_out : STD_LOGIC;
SIGNAL s_i2c_busy : STD_LOGIC;
SIGNAL s_i2c_al : STD_LOGIC; -- arbitration lost
SIGNAL s_i2c_din : STD_LOGIC_VECTOR(7 DOWNTO 0); -- transmit register
SIGNAL s_i2c_dout : STD_LOGIC_VECTOR(7 DOWNTO 0); -- receive register
-- IRQ
SIGNAL s_err_irq : STD_LOGIC;
BEGIN
-----------------------------------------------------------------------------
-- output assignments
-----------------------------------------------------------------------------
o_wb_ack <= s_wb_ack;
o_wb_data <= s_wb_dat_o;
o_err_irq <= s_err_irq;
--
o_status(28 DOWNTO 25) <= (OTHERS => '0');
o_status(23 DOWNTO 15) <= (OTHERS => '0');
o_status (31) <= s_status_reg.i2c_carrier_idle;
o_status (30) <= s_status_reg.i2c_core_idle;
o_status (29) <= s_status_reg.i2c_core_en;
o_status (24) <= s_status_reg.trx_acc_type;
o_status (14) <= s_status_reg.trx_err_nack_rep_dev_adr;
o_status (13) <= s_status_reg.trx_err_nack_dat_lsb;
o_status (12) <= s_status_reg.trx_err_nack_dat_msb;
o_status (11) <= s_status_reg.trx_err_nack_adr_lsb;
o_status (10) <= s_status_reg.trx_err_nack_adr_msb;
o_status ( 9) <= s_status_reg.trx_err_nack_dev_adr;
o_status ( 8) <= s_status_reg.trx_err_arb_rep_dev_adr;
o_status ( 7) <= s_status_reg.trx_err_arb_restart;
o_status ( 6) <= s_status_reg.trx_err_arb_dat_lsb;
o_status ( 5) <= s_status_reg.trx_err_arb_dat_msb;
o_status ( 4) <= s_status_reg.trx_err_arb_adr_lsb;
o_status ( 3) <= s_status_reg.trx_err_arb_adr_msb;
o_status ( 2) <= s_status_reg.trx_err_arb_dev_adr;
o_status ( 1) <= s_status_reg.trx_err_arb_start;
o_status ( 0) <= s_status_reg.trx_adr_err;
-----------------------------------------------------------------------------
--* purpose : Register
--* type : sequential, rising edge, no reset
-----------------------------------------------------------------------------
p_reg_data : PROCESS (clk)
BEGIN
IF (rising_edge(clk)) THEN
s_status_reg.i2c_core_en <= i_cfg_core_en;
s_status_reg.i2c_core_idle <= NOT s_i2c_busy;
s_status_reg.i2c_carrier_idle <= i_scl_pad AND i_sda_pad;
END IF;
END PROCESS p_reg_data;
-----------------------------------------------------------------------------
--* purpose : I2C core control
--* type : sequential, rising edge, low active synchronous reset
-----------------------------------------------------------------------------
p_i2c_core_ctrl : PROCESS (clk, rst_n)
BEGIN
IF (rst_n = '0') THEN
s_fsm_state <= idle;
s_err_irq <= '0';
s_i2c_start <= '0';
s_i2c_stop <= '0';
s_i2c_write <= '0';
s_i2c_read <= '0';
s_i2c_ack_in <= '0';
s_i2c_din <= (OTHERS => '0');
s_wb_ack <= '0';
s_wb_dat_o <= (OTHERS => '0');
s_trx_error <= '0';
s_status_reg.trx_acc_type <= '0';
s_status_reg.trx_err_nack_rep_dev_adr <= '0';
s_status_reg.trx_err_nack_dat_lsb <= '0';
s_status_reg.trx_err_nack_dat_msb <= '0';
s_status_reg.trx_err_nack_adr_lsb <= '0';
s_status_reg.trx_err_nack_adr_msb <= '0';
s_status_reg.trx_err_nack_dev_adr <= '0';
s_status_reg.trx_err_arb_rep_dev_adr <= '0';
s_status_reg.trx_err_arb_restart <= '0';
s_status_reg.trx_err_arb_dat_lsb <= '0';
s_status_reg.trx_err_arb_dat_msb <= '0';
s_status_reg.trx_err_arb_adr_lsb <= '0';
s_status_reg.trx_err_arb_adr_msb <= '0';
s_status_reg.trx_err_arb_dev_adr <= '0';
s_status_reg.trx_err_arb_start <= '0';
s_status_reg.trx_adr_err <= '0';
ELSIF (rising_edge(clk)) THEN
-- default values
s_err_irq <= '0';
s_wb_ack <= '0';
s_i2c_start <= '0';
s_i2c_stop <= '0';
s_i2c_write <= '0';
s_i2c_read <= '0';
s_i2c_ack_in <= '0';
-- FSM
CASE s_fsm_state IS
---------------------------------------------------------------------
WHEN idle =>
---------------------------------------------------------------------
IF (i_wb_cyc = '1' AND i_wb_stb = '1' AND s_wb_ack = '0') THEN
-- check WB address: aligned and Byte-select(s) "complete"
IF ( (SIGNED(i_wb_sel) /= -1) OR
(g_transaction_bytes = 2 AND i_wb_addr(0) = '1') ) THEN
s_fsm_state <= done;
s_status_reg.trx_adr_err <= '1';
s_trx_error <= '1';
ELSE
s_fsm_state <= i2c_start;
s_status_reg.trx_adr_err <= '0';
s_trx_error <= '0';
END IF;
s_wb_dat_o <= (OTHERS => '0');
s_status_reg.trx_acc_type <= i_wb_we;
s_status_reg.trx_err_nack_rep_dev_adr <= '0';
s_status_reg.trx_err_nack_dat_lsb <= '0';
s_status_reg.trx_err_nack_dat_msb <= '0';
s_status_reg.trx_err_nack_adr_lsb <= '0';
s_status_reg.trx_err_nack_adr_msb <= '0';
s_status_reg.trx_err_nack_dev_adr <= '0';
s_status_reg.trx_err_arb_rep_dev_adr <= '0';
s_status_reg.trx_err_arb_restart <= '0';
s_status_reg.trx_err_arb_dat_lsb <= '0';
s_status_reg.trx_err_arb_dat_msb <= '0';
s_status_reg.trx_err_arb_adr_lsb <= '0';
s_status_reg.trx_err_arb_adr_msb <= '0';
s_status_reg.trx_err_arb_dev_adr <= '0';
s_status_reg.trx_err_arb_start <= '0';
END IF;
---------------------------------------------------------------------
WHEN i2c_start => -- TX I2C start signal
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0' AND s_i2c_al = '0') THEN
s_i2c_start <= '1';
ELSE
IF (s_i2c_al = '1') THEN
s_fsm_state <= done;
s_status_reg.trx_err_arb_start <= '1';
s_trx_error <= '1';
ELSE
s_fsm_state <= dev_adr;
END IF;
END IF;
---------------------------------------------------------------------
WHEN dev_adr => -- TX device address & write command
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0' AND s_i2c_al = '0') THEN
s_i2c_write <= '1';
s_i2c_din <= i_cfg_dev_addr & '0'; -- & '0': write access
ELSE
IF (s_i2c_al = '1') THEN
s_fsm_state <= done;
s_status_reg.trx_err_arb_dev_adr <= '1';
s_trx_error <= '1';
ELSIF (s_i2c_ack_out = '1') THEN
s_fsm_state <= abort;
ELSE
s_fsm_state <= reg_adr_msb;
END IF;
s_status_reg.trx_err_nack_dev_adr <= s_i2c_ack_out;
END IF;
---------------------------------------------------------------------
WHEN reg_adr_msb => -- TX register address MSB
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0' AND s_i2c_al = '0') THEN
s_i2c_write <= '1';
s_i2c_din <= "00" & i_wb_addr(13 DOWNTO 8);
ELSE
IF (s_i2c_al = '1') THEN
s_fsm_state <= done;
s_status_reg.trx_err_arb_adr_msb <= '1';
s_trx_error <= '1';
ELSIF (s_i2c_ack_out = '1') THEN
s_fsm_state <= abort;
ELSE
s_fsm_state <= reg_adr_lsb;
END IF;
s_status_reg.trx_err_nack_adr_msb <= s_i2c_ack_out;
END IF;
---------------------------------------------------------------------
WHEN reg_adr_lsb => -- TX register address LSB
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0' AND s_i2c_al = '0') THEN
s_i2c_write <= '1';
s_i2c_din <= i_wb_addr(7 DOWNTO 0);
ELSE
IF (s_i2c_al = '1') THEN
s_fsm_state <= done;
s_status_reg.trx_err_arb_adr_lsb <= '1';
s_trx_error <= '1';
ELSIF (s_i2c_ack_out = '1') THEN
s_fsm_state <= abort;
ELSE
IF (i_wb_we = '1') THEN
-- transmit 1 Byte
IF(g_transaction_bytes = 1) THEN
s_fsm_state <= tx_reg_dat_lsb;
-- transmit 2 Bytes
ELSIF(g_transaction_bytes = 2) THEN
s_fsm_state <= tx_reg_dat_msb;
END IF;
ELSE
s_fsm_state <= i2c_restart;
END IF;
END IF;
s_status_reg.trx_err_nack_adr_lsb <= s_i2c_ack_out;
END IF;
---------------------------------------------------------------------
WHEN tx_reg_dat_msb => -- TX device register data MSB
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0' AND s_i2c_al = '0') THEN
s_i2c_write <= '1';
s_i2c_din <= i_wb_data(((g_transaction_bytes * 8) - 1) DOWNTO (g_transaction_bytes * 8) - 8);
ELSE
IF (s_i2c_al = '1') THEN
s_fsm_state <= done;
s_status_reg.trx_err_arb_dat_msb <= '1';
s_trx_error <= '1';
ELSIF (s_i2c_ack_out = '1') THEN
s_fsm_state <= abort;
ELSE
s_fsm_state <= tx_reg_dat_lsb;
END IF;
s_status_reg.trx_err_nack_dat_msb <= s_i2c_ack_out;
END IF;
---------------------------------------------------------------------
WHEN tx_reg_dat_lsb => -- TX device register data LSB
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0' AND s_i2c_al = '0') THEN
s_i2c_write <= '1';
s_i2c_din <= i_wb_data(7 DOWNTO 0);
ELSE
IF (s_i2c_al = '1') THEN
s_fsm_state <= done;
s_status_reg.trx_err_arb_dat_lsb <= '1';
s_trx_error <= '1';
ELSIF (s_i2c_ack_out = '1') THEN
s_fsm_state <= abort;
ELSE
s_fsm_state <= i2c_stop;
END IF;
s_status_reg.trx_err_nack_dat_lsb <= s_i2c_ack_out;
END IF;
---------------------------------------------------------------------
WHEN i2c_restart => -- TX repeat I2C START signal
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0' AND s_i2c_al = '0') THEN
s_i2c_start <= '1';
ELSE
IF (s_i2c_al = '1') THEN
s_fsm_state <= done;
s_status_reg.trx_err_arb_restart <= '1';
s_trx_error <= '1';
ELSE
s_fsm_state <= rep_dev_adr;
END IF;
END IF;
---------------------------------------------------------------------
WHEN rep_dev_adr => -- TX device address & read command
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0' AND s_i2c_al = '0') THEN
s_i2c_write <= '1';
s_i2c_din <= i_cfg_dev_addr & '1'; -- & '1': read access
ELSE
IF (s_i2c_al = '1') THEN
s_fsm_state <= done;
s_status_reg.trx_err_arb_rep_dev_adr <= '1';
s_trx_error <= '1';
ELSIF (s_i2c_ack_out = '1') THEN
s_fsm_state <= abort;
ELSE
-- receive 1 Byte
IF(g_transaction_bytes = 1) THEN
s_fsm_state <= rx_reg_dat_lsb;
-- receive 2 Bytes
ELSIF(g_transaction_bytes = 2) THEN
s_fsm_state <= rx_reg_dat_msb;
END IF;
END IF;
s_status_reg.trx_err_nack_rep_dev_adr <= s_i2c_ack_out;
END IF;
---------------------------------------------------------------------
WHEN rx_reg_dat_msb => -- RX register data MSB
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0' AND s_i2c_al = '0') THEN
s_i2c_read <= '1';
ELSE
IF (s_i2c_al = '1') THEN
s_fsm_state <= done;
s_status_reg.trx_err_arb_dat_msb <= '1';
s_trx_error <= '1';
ELSIF (s_i2c_ack_out = '1') THEN
s_fsm_state <= abort;
ELSE
s_fsm_state <= rx_reg_dat_lsb;
s_wb_dat_o((g_transaction_bytes*8-1) DOWNTO g_transaction_bytes*8-8) <= s_i2c_dout;
END IF;
s_status_reg.trx_err_nack_dat_msb <= s_i2c_ack_out;
END IF;
---------------------------------------------------------------------
WHEN rx_reg_dat_lsb => -- RX register data LSB
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0' AND s_i2c_al = '0') THEN
s_i2c_read <= '1';
s_i2c_ack_in <= '1';
ELSE
IF (s_i2c_al = '1') THEN
s_fsm_state <= done;
s_status_reg.trx_err_arb_dat_lsb <= '1';
s_trx_error <= '1';
-- ELSIF (s_i2c_ack_out = '1') THEN
-- s_fsm_state <= abort;
ELSE
s_fsm_state <= i2c_stop;
s_wb_dat_o(7 DOWNTO 0) <= s_i2c_dout;
END IF;
s_status_reg.trx_err_nack_dat_lsb <= NOT s_i2c_ack_out; -- TBD
s_trx_error <= NOT s_i2c_ack_out; -- TBD
END IF;
---------------------------------------------------------------------
WHEN abort => -- TX I2C stop signal
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0') THEN
s_i2c_stop <= '1';
ELSE
s_fsm_state <= done;
END IF;
s_trx_error <= '1';
---------------------------------------------------------------------
WHEN i2c_stop => -- TX I2C stop signal
---------------------------------------------------------------------
IF (s_i2c_cmd_done = '0') THEN
s_i2c_stop <= '1';
ELSE
s_fsm_state <= done;
END IF;
---------------------------------------------------------------------
WHEN done => -- transfer done
---------------------------------------------------------------------
s_fsm_state <= idle;
s_err_irq <= s_trx_error;
s_wb_ack <= '1';
END CASE;
END IF;
END PROCESS p_i2c_core_ctrl;
-----------------------------------------------------------------------------
-- I2C core (I2C master; Byte transactions)
-----------------------------------------------------------------------------
wb_i2c_master_byte_ctrl_1 : ENTITY rtl_lib.wb_i2c_master_byte_ctrl
PORT MAP (
clk => clk,
rst_n => rst_n,
--
i_ena => i_cfg_core_en,
i_clk_cnt => i_cfg_clk_div,
-- input signals
i_start => s_i2c_start,
i_stop => s_i2c_stop,
i_read => s_i2c_read,
i_write => s_i2c_write,
i_ack_in => s_i2c_ack_in,
i_din => s_i2c_din,
-- output signals
o_cmd_done=> s_i2c_cmd_done,
o_ack_out => s_i2c_ack_out,
o_i2c_busy=> s_i2c_busy,
o_i2c_al => s_i2c_al,
o_dout => s_i2c_dout,
-- i2c lines
i_scl => i_scl_pad,
o_scl => o_scl_pad,
o_scl_oen => o_scl_padoen,
i_sda => i_sda_pad,
o_sda => o_sda_pad,
o_sda_oen => o_sda_padoen);
-----------------------------------------------------------------------------
END ARCHITECTURE rtl;
| mit | 10da0f11e57be077154f186c11e0be6f | 0.390211 | 3.531194 | false | false | false | false |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_source/sid_peripheral.vhd | 1 | 3,769 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_peripheral is
generic (
g_8voices : boolean := false;
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
io_req : in t_io_req;
io_resp : out t_io_resp;
start_iter : in std_logic;
sample_left : out signed(17 downto 0);
sample_right : out signed(17 downto 0) );
end sid_peripheral;
architecture structural of sid_peripheral is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_filt0 : t_io_req;
signal io_resp_filt0: t_io_resp;
signal io_req_filt1 : t_io_req;
signal io_resp_filt1: t_io_resp;
signal control : t_sid_control;
signal sid_addr : unsigned(7 downto 0);
signal sid_wren : std_logic;
signal sid_wdata : std_logic_vector(7 downto 0);
signal sid_rdata : std_logic_vector(7 downto 0);
begin
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- 4042000
reqs(1) => io_req_filt0, -- 4042800
reqs(2) => io_req_filt1, -- 4043000
resps(0) => io_resp_regs,
resps(1) => io_resp_filt0,
resps(2) => io_resp_filt1 );
i_regs: entity work.sid_io_regs
generic map (
g_8voices => g_8voices,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control );
i_sid_mapper: entity work.sid_mapper
port map (
clock => clock,
reset => reset,
control => control,
slot_req => slot_req,
slot_resp => slot_resp,
sid_addr => sid_addr,
sid_wren => sid_wren,
sid_wdata => sid_wdata,
sid_rdata => sid_rdata );
i_sid_engine: entity work.sid_top
generic map (
g_8voices => g_8voices,
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
addr => sid_addr,
wren => sid_wren,
wdata => sid_wdata,
rdata => sid_rdata,
comb_wave_l => control.comb_wave_left,
comb_wave_r => control.comb_wave_right,
io_req_filt0 => io_req_filt0,
io_resp_filt0 => io_resp_filt0,
io_req_filt1 => io_req_filt1,
io_resp_filt1 => io_resp_filt1,
start_iter => start_iter,
sample_left => sample_left,
sample_right => sample_right );
end structural;
| gpl-3.0 | 8cb865983ed82ff150a9901e25bea508 | 0.482091 | 3.55566 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/watchdog/cb20/synthesis/submodules/flink_definitions.vhd | 2 | 4,267 | -------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- fLink definitions --
-- --
-- THIS FILE WAS CREATED AUTOMATICALLY - do not change --
-- --
-- Created with: flinkinterface/func_id/ --
-- create_flink_definitions.vhd_flinkVHDL.sh --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE fLink_definitions IS
-- Global
CONSTANT c_fLink_avs_data_width : INTEGER := 32;
CONSTANT c_fLink_avs_data_width_in_byte : INTEGER := c_fLink_avs_data_width/8;
-- Header registers
CONSTANT c_fLink_number_of_std_registers : INTEGER := 8;
CONSTANT c_fLink_typdef_address : INTEGER := 0;
CONSTANT c_fLink_mem_size_address : INTEGER := 1;
CONSTANT c_fLink_number_of_channels_address : INTEGER := 2;
CONSTANT c_fLink_unique_id_address : INTEGER := 3;
CONSTANT c_fLink_status_address : INTEGER := 4;
CONSTANT c_fLink_configuration_address : INTEGER := 5;
CONSTANT c_fLink_id_length : INTEGER := 16;
CONSTANT c_fLink_subtype_length : INTEGER := 8;
CONSTANT c_fLink_interface_version_length : INTEGER := 8;
CONSTANT c_fLink_reset_bit_num : INTEGER := 0;
-- Interface IDs:
CONSTANT c_fLink_info_id : INTEGER RANGE 0 TO 65535 := 0;
CONSTANT c_fLink_analog_input_id : INTEGER RANGE 0 TO 65535 := 1;
CONSTANT c_fLink_analog_output_id : INTEGER RANGE 0 TO 65535 := 2;
CONSTANT c_fLink_digital_io_id : INTEGER RANGE 0 TO 65535 := 5;
CONSTANT c_fLink_counter_id : INTEGER RANGE 0 TO 65535 := 6;
CONSTANT c_fLink_timer_id : INTEGER RANGE 0 TO 65535 := 7;
CONSTANT c_fLink_memory_id : INTEGER RANGE 0 TO 65535 := 8;
CONSTANT c_fLink_pwm_out_id : INTEGER RANGE 0 TO 65535 := 12;
CONSTANT c_fLink_ppwa_id : INTEGER RANGE 0 TO 65535 := 13;
CONSTANT c_fLink_watchdog_id : INTEGER RANGE 0 TO 65535 := 16;
CONSTANT c_fLink_sensor_id : INTEGER RANGE 0 TO 65535 := 17;
END PACKAGE fLink_definitions;
| apache-2.0 | d1cdfaaf1773f6ab7bcf1f8c09a32290 | 0.405437 | 4.549041 | false | false | false | false |
chiggs/nvc | test/regress/cond3.vhd | 5 | 669 | entity cond3 is
end entity;
architecture test of cond3 is
signal x, y, z : integer := 0;
begin
x <= y + 1, y + 2 after 2 ns when z > 0 else 0;
process is
begin
wait for 1 ns;
assert x = 0;
z <= 1;
wait for 1 ns;
assert x = 1;
wait for 2 ns;
assert x = 2;
y <= 2;
z <= 1;
wait for 1 ns;
assert x = 3;
wait for 2 ns;
assert x = 4;
y <= 5;
wait for 1 ns;
assert x = 6;
wait for 2 ns;
assert x = 7;
z <= 0;
wait for 1 ns;
assert x = 0;
wait;
end process;
end architecture;
| gpl-3.0 | e87b9ab15b6fd6e61fe1a436f9b3c7fe | 0.433483 | 3.539683 | false | false | false | false |
fpgaddicted/5bit-shift-register-structural- | top_module.vhd | 1 | 2,301 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:49:40 04/09/2017
-- Design Name:
-- Module Name: top_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity display_controller is
Port ( seg7 : out STD_LOGIC_VECTOR (0 to 7);
clk : in STD_LOGIC;
opcode : in STD_LOGIC_VECTOR (2 downto 0);
reset : in STD_LOGIC;
anodes : out STD_LOGIC_VECTOR (3 downto 0));
end display_controller;
architecture Driver of display_controller is
COMPONENT decoder_states IS
PORT (
op : in STD_LOGIC_VECTOR (3 downto 0);
data_o : out STD_LOGIC_VECTOR (0 to 7);
anode_s : in STD_LOGIC_VECTOR (3 downto 0));
END COMPONENT;
COMPONENT anode_fsm IS
PORT (
clk : in STD_LOGIC;
anode_o : out STD_LOGIC_VECTOR (3 downto 0);
reset : in STD_LOGIC);
END COMPONENT;
COMPONENT prescaler IS
PORT (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC);
END COMPONENT;
signal an : std_logic_vector (3 downto 0);
signal click : std_logic;
signal dec : std_logic_vector (3 downto 0);
begin
fsm1 : anode_fsm
PORT MAP (
clk => click,
anode_o => an,
reset => reset
);
display : decoder_states
PORT MAP (
op => dec,
data_o => seg7,
anode_s => an
);
clock : prescaler
PORT MAP (
clk_in => clk,
clk_out => click,
reset => reset
);
anodes <= an;
dec <=(reset,opcode(2),opcode(1),opcode(0));
end Driver;
| gpl-3.0 | ff53fe7859be13567b13bd8acb8fe831 | 0.531943 | 3.652381 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/synchroniser/vhdl_source/level_synchronizer.vhd | 1 | 2,773 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2008, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Level synchronizer block
-------------------------------------------------------------------------------
-- Description: The level synchronizer block synchronizes an asynchronous
-- input to the clock of the receiving module. Two flip-flops are
-- used to avoid metastability of the synchronized signal.
--
-- Please read Ran Ginosars paper "Fourteen ways to fool your
-- synchronizer" before considering modifications to this module!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity level_synchronizer is
generic (
g_reset_val : std_logic := '0'
);
port (
-- Clock signal
clock : in std_logic;
-- Asynchronous input
reset : in std_logic := '0';
-- Asynchronous input
input : in std_logic;
-- Synchronized input
input_c : out std_logic
);
---------------------------------------------------------------------------
-- Synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of level_synchronizer : entity is "no";
attribute register_balancing : string;
attribute register_balancing of level_synchronizer : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of level_synchronizer : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of level_synchronizer : entity is true;
---------------------------------------------------------------------------
end level_synchronizer;
architecture rtl of level_synchronizer is
signal sync1 : std_logic := g_reset_val;
signal sync2 : std_logic := g_reset_val;
begin
p_input_synchronization : process(clock)
begin
if rising_edge(clock) then
sync1 <= input;
sync2 <= sync1;
if reset = '1' then
sync1 <= g_reset_val;
sync2 <= g_reset_val;
end if;
end if;
end process;
input_c <= sync2;
end rtl;
| gpl-3.0 | 997e2c8740106318473e75842aa61d0d | 0.443924 | 5.579477 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_tester/nios_tester/nios_tester_inst.vhd | 1 | 9,101 | component nios_tester is
port (
audio_in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
audio_in_valid : in std_logic := 'X'; -- valid
audio_in_ready : out std_logic; -- ready
audio_out_data : out std_logic_vector(31 downto 0); -- data
audio_out_valid : out std_logic; -- valid
audio_out_ready : in std_logic := 'X'; -- ready
dummy_export : in std_logic := 'X'; -- export
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
jtag0_jtag_tck : out std_logic; -- jtag_tck
jtag0_jtag_tms : out std_logic; -- jtag_tms
jtag0_jtag_tdi : out std_logic; -- jtag_tdi
jtag0_jtag_tdo : in std_logic := 'X'; -- jtag_tdo
jtag1_jtag_tck : out std_logic; -- jtag_tck
jtag1_jtag_tms : out std_logic; -- jtag_tms
jtag1_jtag_tdi : out std_logic; -- jtag_tdi
jtag1_jtag_tdo : in std_logic := 'X'; -- jtag_tdo
jtag_in_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
jtag_in_valid : in std_logic := 'X'; -- valid
jtag_in_ready : out std_logic; -- ready
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
pio_in_port : in std_logic_vector(31 downto 0) := (others => 'X'); -- in_port
pio_out_port : out std_logic_vector(31 downto 0); -- out_port
spi_MISO : in std_logic := 'X'; -- MISO
spi_MOSI : out std_logic; -- MOSI
spi_SCLK : out std_logic; -- SCLK
spi_SS_n : out std_logic; -- SS_n
sys_clock_clk : in std_logic := 'X'; -- clk
sys_reset_reset_n : in std_logic := 'X' -- reset_n
);
end component nios_tester;
u0 : component nios_tester
port map (
audio_in_data => CONNECTED_TO_audio_in_data, -- audio_in.data
audio_in_valid => CONNECTED_TO_audio_in_valid, -- .valid
audio_in_ready => CONNECTED_TO_audio_in_ready, -- .ready
audio_out_data => CONNECTED_TO_audio_out_data, -- audio_out.data
audio_out_valid => CONNECTED_TO_audio_out_valid, -- .valid
audio_out_ready => CONNECTED_TO_audio_out_ready, -- .ready
dummy_export => CONNECTED_TO_dummy_export, -- dummy.export
io_ack => CONNECTED_TO_io_ack, -- io.ack
io_rdata => CONNECTED_TO_io_rdata, -- .rdata
io_read => CONNECTED_TO_io_read, -- .read
io_wdata => CONNECTED_TO_io_wdata, -- .wdata
io_write => CONNECTED_TO_io_write, -- .write
io_address => CONNECTED_TO_io_address, -- .address
io_irq => CONNECTED_TO_io_irq, -- .irq
io_u2p_ack => CONNECTED_TO_io_u2p_ack, -- io_u2p.ack
io_u2p_rdata => CONNECTED_TO_io_u2p_rdata, -- .rdata
io_u2p_read => CONNECTED_TO_io_u2p_read, -- .read
io_u2p_wdata => CONNECTED_TO_io_u2p_wdata, -- .wdata
io_u2p_write => CONNECTED_TO_io_u2p_write, -- .write
io_u2p_address => CONNECTED_TO_io_u2p_address, -- .address
io_u2p_irq => CONNECTED_TO_io_u2p_irq, -- .irq
jtag0_jtag_tck => CONNECTED_TO_jtag0_jtag_tck, -- jtag0.jtag_tck
jtag0_jtag_tms => CONNECTED_TO_jtag0_jtag_tms, -- .jtag_tms
jtag0_jtag_tdi => CONNECTED_TO_jtag0_jtag_tdi, -- .jtag_tdi
jtag0_jtag_tdo => CONNECTED_TO_jtag0_jtag_tdo, -- .jtag_tdo
jtag1_jtag_tck => CONNECTED_TO_jtag1_jtag_tck, -- jtag1.jtag_tck
jtag1_jtag_tms => CONNECTED_TO_jtag1_jtag_tms, -- .jtag_tms
jtag1_jtag_tdi => CONNECTED_TO_jtag1_jtag_tdi, -- .jtag_tdi
jtag1_jtag_tdo => CONNECTED_TO_jtag1_jtag_tdo, -- .jtag_tdo
jtag_in_data => CONNECTED_TO_jtag_in_data, -- jtag_in.data
jtag_in_valid => CONNECTED_TO_jtag_in_valid, -- .valid
jtag_in_ready => CONNECTED_TO_jtag_in_ready, -- .ready
mem_mem_req_address => CONNECTED_TO_mem_mem_req_address, -- mem.mem_req_address
mem_mem_req_byte_en => CONNECTED_TO_mem_mem_req_byte_en, -- .mem_req_byte_en
mem_mem_req_read_writen => CONNECTED_TO_mem_mem_req_read_writen, -- .mem_req_read_writen
mem_mem_req_request => CONNECTED_TO_mem_mem_req_request, -- .mem_req_request
mem_mem_req_tag => CONNECTED_TO_mem_mem_req_tag, -- .mem_req_tag
mem_mem_req_wdata => CONNECTED_TO_mem_mem_req_wdata, -- .mem_req_wdata
mem_mem_resp_dack_tag => CONNECTED_TO_mem_mem_resp_dack_tag, -- .mem_resp_dack_tag
mem_mem_resp_data => CONNECTED_TO_mem_mem_resp_data, -- .mem_resp_data
mem_mem_resp_rack_tag => CONNECTED_TO_mem_mem_resp_rack_tag, -- .mem_resp_rack_tag
pio_in_port => CONNECTED_TO_pio_in_port, -- pio.in_port
pio_out_port => CONNECTED_TO_pio_out_port, -- .out_port
spi_MISO => CONNECTED_TO_spi_MISO, -- spi.MISO
spi_MOSI => CONNECTED_TO_spi_MOSI, -- .MOSI
spi_SCLK => CONNECTED_TO_spi_SCLK, -- .SCLK
spi_SS_n => CONNECTED_TO_spi_SS_n, -- .SS_n
sys_clock_clk => CONNECTED_TO_sys_clock_clk, -- sys_clock.clk
sys_reset_reset_n => CONNECTED_TO_sys_reset_reset_n -- sys_reset.reset_n
);
| gpl-3.0 | 0682bdc597fd5e627d012dec36639a0c | 0.41468 | 3.605784 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_sim/mblite_simu_cached.vhd | 2 | 4,760 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu_cached is
end entity;
architecture test of mblite_simu_cached is
signal clock : std_logic := '0';
signal reset : std_logic;
signal mmem_o : dmem_out_type;
signal mmem_i : dmem_in_type;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
signal invalidate : std_logic := '0';
signal inv_addr : std_logic_vector(31 downto 0) := X"00003FFC";
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 1048575) := (others => (others => '0')); -- 4MB
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_core: entity work.cached_mblite
port map (
clock => clock,
reset => reset,
invalidate => invalidate,
inv_addr => inv_addr,
mmem_o => mmem_o,
mmem_i => mmem_i,
irq_i => irq_i,
irq_o => irq_o );
-- IRQ generation @ 100 kHz (every 10 us)
process
begin
for i in 1 to 50 loop
wait for 10 us;
wait until clock='1';
irq_i <= '1';
wait until clock='1';
irq_i <= '0';
end loop;
wait;
end process;
process
begin
wait until reset='0';
wait until clock='1';
wait until clock='1';
while true loop
invalidate <= '0';
wait until clock='1';
invalidate <= '0';
wait until clock='1';
wait until clock='1';
end loop;
end process;
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
mmem_i.dat_i <= (others => 'X');
if mmem_o.ena_o = '1' then
if mmem_o.adr_o(31 downto 25) = "0000000" then
if mmem_o.we_o = '1' then
for i in 0 to 3 loop
if mmem_o.sel_o(i) = '1' then
memory(to_integer(unsigned(mmem_o.adr_o(21 downto 2))))(i*8+7 downto i*8) := mmem_o.dat_o(i*8+7 downto i*8);
end if;
end loop;
else -- read
mmem_i.dat_i <= memory(to_integer(unsigned(mmem_o.adr_o(21 downto 2))));
end if;
else -- I/O
if mmem_o.we_o = '1' then -- write
case mmem_o.adr_o(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := mmem_o.dat_o(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(mmem_o.adr_o) & " dropped";
end case;
else -- read
case mmem_o.adr_o(19 downto 0) is
when X"0000C" => -- Capabilities
mmem_i.dat_i <= X"00000002";
when X"00012" => -- UART_FLAGS
mmem_i.dat_i <= X"40404040";
when X"2000A" => -- 1541_A memmap
mmem_i.dat_i <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
mmem_i.dat_i <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(mmem_o.adr_o) & " dropped";
mmem_i.dat_i <= X"00000000";
end case;
end if;
end if;
end if;
if reset = '1' then
mmem_i.ena_i <= '1';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 1fa534050f4d86475a78d80980380fec | 0.427311 | 3.976608 | false | false | false | false |
trondd/mkjpeg | design/ctrlsm.vhd | 2 | 11,252 | -------------------------------------------------------------------------------
-- File Name : CtrlSM.vhd
--
-- Project : JPEG_ENC
--
-- Module : CtrlSM
--
-- Content : CtrlSM
--
-- Description : CtrlSM core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity CtrlSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- output IF
outif_almost_full : in std_logic;
-- HOST IF
sof : in std_logic;
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
jpeg_ready : out std_logic;
jpeg_busy : out std_logic;
-- FDCT
fdct_start : out std_logic;
fdct_ready : in std_logic;
fdct_sm_settings : out T_SM_SETTINGS;
-- ZIGZAG
zig_start : out std_logic;
zig_ready : in std_logic;
zig_sm_settings : out T_SM_SETTINGS;
-- Quantizer
qua_start : out std_logic;
qua_ready : in std_logic;
qua_sm_settings : out T_SM_SETTINGS;
-- RLE
rle_start : out std_logic;
rle_ready : in std_logic;
rle_sm_settings : out T_SM_SETTINGS;
-- Huffman
huf_start : out std_logic;
huf_ready : in std_logic;
huf_sm_settings : out T_SM_SETTINGS;
-- ByteStuffdr
bs_start : out std_logic;
bs_ready : in std_logic;
bs_sm_settings : out T_SM_SETTINGS;
-- JFIF GEN
jfif_start : out std_logic;
jfif_ready : in std_logic;
jfif_eoi : out std_logic;
-- OUT MUX
out_mux_ctrl : out std_logic
);
end entity CtrlSM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of CtrlSM is
constant NUM_STAGES : integer := 6;
constant CMP_MAX : std_logic_vector(2 downto 0) := "100";
type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
signal Reg : T_ARR_SM_SETTINGS;
signal main_state : T_STATE;
signal start : std_logic_vector(NUM_STAGES+1 downto 1);
signal idle : std_logic_vector(NUM_STAGES+1 downto 1);
signal start_PB : std_logic_vector(NUM_STAGES downto 1);
signal ready_PB : std_logic_vector(NUM_STAGES downto 1);
signal fsm : ARR_FSM;
signal start1_d : std_logic;
signal RSM : T_SM_SETTINGS;
signal out_mux_ctrl_s : std_logic;
signal out_mux_ctrl_s2 : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_sm_settings <= Reg(1);
zig_sm_settings <= Reg(2);
qua_sm_settings <= Reg(3);
rle_sm_settings <= Reg(4);
huf_sm_settings <= Reg(5);
bs_sm_settings <= Reg(6);
fdct_start <= start_PB(1);
ready_PB(1) <= fdct_ready;
zig_start <= start_PB(2);
ready_PB(2) <= zig_ready;
qua_start <= start_PB(3);
ready_PB(3) <= qua_ready;
rle_start <= start_PB(4);
ready_PB(4) <= rle_ready;
huf_start <= start_PB(5);
ready_PB(5) <= huf_ready;
bs_start <= start_PB(6);
ready_PB(6) <= bs_ready;
-----------------------------------------------------------------------------
-- CTRLSM 1..NUM_STAGES
-----------------------------------------------------------------------------
G_S_CTRL_SM : for i in 1 to NUM_STAGES generate
-- CTRLSM 1..NUM_STAGES
U_S_CTRL_SM : entity work.SingleSM
port map
(
CLK => CLK,
RST => RST,
-- from/to SM(m)
start_i => start(i),
idle_o => idle(i),
-- from/to SM(m+1)
idle_i => idle(i+1),
start_o => start(i+1),
-- from/to processing block
pb_rdy_i => ready_PB(i),
pb_start_o => start_PB(i),
-- state out
fsm_o => fsm(i)
);
end generate G_S_CTRL_SM;
idle(NUM_STAGES+1) <= not outif_almost_full;
-------------------------------------------------------------------
-- Regs
-------------------------------------------------------------------
G_REG_SM : for i in 1 to NUM_STAGES generate
p_reg1 : process(CLK, RST)
begin
if RST = '1' then
Reg(i) <= C_SM_SETTINGS;
elsif CLK'event and CLK = '1' then
if start(i) = '1' then
if i = 1 then
Reg(i).x_cnt <= RSM.x_cnt;
Reg(i).y_cnt <= RSM.y_cnt;
Reg(i).cmp_idx <= RSM.cmp_idx;
else
Reg(i) <= Reg(i-1);
end if;
end if;
end if;
end process;
end generate G_REG_SM;
-------------------------------------------------------------------
-- Main_SM
-------------------------------------------------------------------
p_main_sm : process(CLK, RST)
begin
if RST = '1' then
main_state <= IDLES;
start(1) <= '0';
start1_d <= '0';
jpeg_ready <= '0';
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jpeg_busy <= '0';
RSM.cmp_idx <= (others => '0');
out_mux_ctrl_s <= '0';
out_mux_ctrl_s2 <= '0';
jfif_eoi <= '0';
out_mux_ctrl <= '0';
jfif_start <= '0';
elsif CLK'event and CLK = '1' then
start(1) <= '0';
start1_d <= start(1);
jpeg_ready <= '0';
jfif_start <= '0';
out_mux_ctrl_s2 <= out_mux_ctrl_s;
out_mux_ctrl <= out_mux_ctrl_s2;
case main_state is
-------------------------------
-- IDLE
-------------------------------
when IDLES =>
if sof = '1' then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= (others => '0');
jfif_start <= '1';
out_mux_ctrl_s <= '0';
jfif_eoi <= '0';
main_state <= JFIF;
end if;
-------------------------------
-- JFIF
-------------------------------
when JFIF =>
if jfif_ready = '1' then
out_mux_ctrl_s <= '1';
main_state <= HORIZ;
end if;
-------------------------------
-- HORIZ
-------------------------------
when HORIZ =>
if RSM.x_cnt < unsigned(img_size_x) then
main_state <= COMP;
else
RSM.x_cnt <= (others => '0');
main_state <= VERT;
end if;
-------------------------------
-- COMP
-------------------------------
when COMP =>
if idle(1) = '1' and start(1) = '0' then
if RSM.cmp_idx < unsigned(CMP_MAX) then
start(1) <= '1';
else
RSM.cmp_idx <= (others => '0');
RSM.x_cnt <= RSM.x_cnt + 16;
main_state <= HORIZ;
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when VERT =>
if RSM.y_cnt < unsigned(img_size_y)-8 then
RSM.x_cnt <= (others => '0');
RSM.y_cnt <= RSM.y_cnt + 8;
main_state <= HORIZ;
else
if idle(NUM_STAGES downto 1) = (NUM_STAGES-1 downto 0 => '1') then
main_state <= EOI;
jfif_eoi <= '1';
out_mux_ctrl_s <= '0';
jfif_start <= '1';
end if;
end if;
-------------------------------
-- VERT
-------------------------------
when EOI =>
if jfif_ready = '1' then
jpeg_ready <= '1';
main_state <= IDLES;
end if;
-------------------------------
-- others
-------------------------------
when others =>
main_state <= IDLES;
end case;
if start1_d = '1' then
RSM.cmp_idx <= RSM.cmp_idx + 1;
end if;
if main_state = IDLES then
jpeg_busy <= '0';
else
jpeg_busy <= '1';
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | 39976f9c1e22c4e85906e3ab1eb7a805 | 0.313011 | 4.64 | false | false | false | false |
xiadz/oscilloscope | src/settings.vhd | 1 | 2,994 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 13:36:26 05/24/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity settings is
port (
-- Inputs
nrst : in std_logic;
clk108 : in std_logic;
sw : in std_logic_vector (6 downto 0);
btn : in std_logic_vector (2 downto 0);
-- Outputs
trigger_btn : out std_logic := '0';
trigger_event : out TRIGGER_EVENT_T;
red_enable : out std_logic := '0';
green_enable : out std_logic := '0';
blue_enable : out std_logic := '0';
continue_after_reading : out std_logic;
time_resolution : out integer range 0 to 15 := 0
);
end settings;
architecture behavioral of settings is
signal prev_btn_1 : std_logic := '0';
signal prev_btn_2 : std_logic := '0';
signal internal_continue_after_reading : std_logic := '0';
signal internal_trigger_event : TRIGGER_EVENT_T := BUTTON_TRIGGER_T;
begin
continue_after_reading <= internal_continue_after_reading;
trigger_event <= internal_trigger_event;
process (nrst, clk108) is
begin
if nrst = '0' then
trigger_btn <= '0';
internal_trigger_event <= BUTTON_TRIGGER_T;
red_enable <= '0';
green_enable <= '0';
blue_enable <= '0';
internal_continue_after_reading <= '0';
time_resolution <= 0;
prev_btn_1 <= '0';
prev_btn_2 <= '0';
elsif rising_edge (clk108) then
trigger_btn <= btn (0);
prev_btn_2 <= btn (2);
if btn (2) = '1' and prev_btn_2 = '0' then
-- cycle through available modes
if internal_trigger_event = BUTTON_TRIGGER_T then
internal_trigger_event <= RED_TRIGGER_T;
elsif internal_trigger_event = RED_TRIGGER_T then
internal_trigger_event <= GREEN_TRIGGER_T;
elsif internal_trigger_event = GREEN_TRIGGER_T then
internal_trigger_event <= BLUE_TRIGGER_T;
elsif internal_trigger_event = BLUE_TRIGGER_T then
internal_trigger_event <= BUTTON_TRIGGER_T;
end if;
end if;
red_enable <= sw (6);
green_enable <= sw (5);
blue_enable <= sw (4);
prev_btn_1 <= btn (1);
if btn (1) = '1' and prev_btn_1 = '0' then
internal_continue_after_reading <= not internal_continue_after_reading;
end if;
time_resolution <= to_integer (unsigned (sw (3 downto 0)));
end if;
end process;
end behavioral; | mit | 0656d593d6c393ab7313ebe0e0f69e85 | 0.489646 | 4.175732 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_sim/nano_addresses_pkg.vhd | 1 | 1,678 | --------------------------------------------------------------------------------
-- Entity: nano_addresses_pkg
-- Date:2018-07-14
-- Author: gideon
--
-- Description: Package with addresses in Nano RAM
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package nano_addresses_pkg is
constant Command : unsigned(19 downto 0) := X"00600";
constant Command_DevEP : unsigned(19 downto 0) := X"00602";
constant Command_Length : unsigned(19 downto 0) := X"00604";
constant Command_MaxTrans : unsigned(19 downto 0) := X"00606";
constant Command_Interval : unsigned(19 downto 0) := X"00608";
constant Command_LastFrame: unsigned(19 downto 0) := X"0060A";
constant Command_SplitCtl : unsigned(19 downto 0) := X"0060C";
constant Command_Result : unsigned(19 downto 0) := X"0060E";
constant Command_MemLo : unsigned(19 downto 0) := X"00610";
constant Command_MemHi : unsigned(19 downto 0) := X"00612";
constant Command_Started : unsigned(19 downto 0) := X"00614";
constant Command_Timeout : unsigned(19 downto 0) := X"00616";
constant Command_Size : natural := 24; -- bytes
constant c_nano_simulation : unsigned(19 downto 0) := X"007D6";
constant c_nano_dosuspend : unsigned(19 downto 0) := X"007D8";
constant c_nano_doreset : unsigned(19 downto 0) := X"007DA";
constant c_nano_busspeed : unsigned(19 downto 0) := X"007DC";
constant c_nano_numpipes : unsigned(19 downto 0) := X"007DE";
constant c_nano_enable : unsigned(19 downto 0) := X"00800";
end package;
| gpl-3.0 | 846743f7627e0c509fc96646b3fed20e | 0.596544 | 3.679825 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/watchdog/cb20/synthesis/cb20_gpio_block_1.vhd | 1 | 3,970 | -- cb20_gpio_block_1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_1 is
generic (
number_of_gpios : integer := 8;
unique_id : std_logic_vector(31 downto 0) := "00010010011100000101000000000010"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- avalon_slave_0.readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => '0'); -- .address
isl_avs_read : in std_logic := '0'; -- .read
isl_avs_write : in std_logic := '0'; -- .write
osl_avs_waitrequest : out std_logic; -- .waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
isl_clk : in std_logic := '0'; -- clock_sink.clk
isl_reset_n : in std_logic := '0'; -- reset_sink.reset_n
oslv_gpios : inout std_logic_vector(7 downto 0) := (others => '0') -- conduit_end.export
);
end entity cb20_gpio_block_1;
architecture rtl of cb20_gpio_block_1 is
component avalon_gpio_interface is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component avalon_gpio_interface;
begin
number_of_gpios_check : if number_of_gpios /= 8 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
unique_id_check : if unique_id /= "00010010011100000101000000000010" generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
gpio_block_1 : component avalon_gpio_interface
generic map (
number_of_gpios => 8,
unique_id => "00010010011100000101000000000010"
)
port map (
oslv_avs_read_data => oslv_avs_read_data, -- avalon_slave_0.readdata
islv_avs_address => islv_avs_address, -- .address
isl_avs_read => isl_avs_read, -- .read
isl_avs_write => isl_avs_write, -- .write
osl_avs_waitrequest => osl_avs_waitrequest, -- .waitrequest
islv_avs_write_data => islv_avs_write_data, -- .writedata
islv_avs_byteenable => islv_avs_byteenable, -- .byteenable
isl_clk => isl_clk, -- clock_sink.clk
isl_reset_n => isl_reset_n, -- reset_sink.reset_n
oslv_gpios => oslv_gpios -- conduit_end.export
);
end architecture rtl; -- of cb20_gpio_block_1
| apache-2.0 | e5c904fc137a61b489b4b472fb13e47d | 0.522166 | 3.538324 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/watchdog/cb20/synthesis/cb20_width_adapter.vhd | 1 | 10,430 | -- cb20_width_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 34;
IN_PKT_ADDR_L : integer := 18;
IN_PKT_DATA_H : integer := 15;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 17;
IN_PKT_BYTEEN_L : integer := 16;
IN_PKT_BYTE_CNT_H : integer := 43;
IN_PKT_BYTE_CNT_L : integer := 41;
IN_PKT_TRANS_COMPRESSED_READ : integer := 35;
IN_PKT_BURSTWRAP_H : integer := 44;
IN_PKT_BURSTWRAP_L : integer := 44;
IN_PKT_BURST_SIZE_H : integer := 47;
IN_PKT_BURST_SIZE_L : integer := 45;
IN_PKT_RESPONSE_STATUS_H : integer := 69;
IN_PKT_RESPONSE_STATUS_L : integer := 68;
IN_PKT_TRANS_EXCLUSIVE : integer := 40;
IN_PKT_BURST_TYPE_H : integer := 49;
IN_PKT_BURST_TYPE_L : integer := 48;
IN_ST_DATA_W : integer := 70;
OUT_PKT_ADDR_H : integer := 52;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 61;
OUT_PKT_BYTE_CNT_L : integer := 59;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 53;
OUT_PKT_BURST_SIZE_H : integer := 65;
OUT_PKT_BURST_SIZE_L : integer := 63;
OUT_PKT_RESPONSE_STATUS_H : integer := 87;
OUT_PKT_RESPONSE_STATUS_L : integer := 86;
OUT_PKT_TRANS_EXCLUSIVE : integer := 58;
OUT_PKT_BURST_TYPE_H : integer := 67;
OUT_PKT_BURST_TYPE_L : integer := 66;
OUT_ST_DATA_W : integer := 88;
ST_CHANNEL_W : integer := 8;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(7 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(69 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(87 downto 0); -- .data
out_channel : out std_logic_vector(7 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter;
architecture rtl of cb20_width_adapter is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_channel : out std_logic_vector(7 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter
| apache-2.0 | e546e3b6ddf2506db20ab5715fb3384b | 0.458581 | 3.372131 | false | false | false | false |
chiggs/nvc | test/regress/record6.vhd | 3 | 1,261 | entity record6 is
end entity;
architecture test of record6 is
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
type rec_array is array (natural range <>) of rec;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
end function;
function make_rec_array(x : rec; l, r : natural) return rec_array is
variable ra : rec_array(l to r) := (others => x);
begin
return ra;
end function;
function get_bit(v : in rec) return bit is
begin
return v.x(v.y);
end function;
begin
process is
variable r : rec;
begin
r.x := "101";
r.y := 1;
assert get_bit(r) = '1';
r.y := 2;
assert get_bit(r) = '0';
assert get_bit(make_rec("011", 2)) = '1';
r.x := make_rec("010", 1).x;
assert r.x = "010";
r.y := make_rec("010", 1).y;
assert r.y = 1;
r := make_rec("010", 1);
assert make_rec_array(r, 1, 2) = ( ("010", 1), ("010", 1) );
assert make_rec_array(("111", 5), 1, 2) = ( ("111", 5), ("111", 5) );
wait;
end process;
end architecture;
| gpl-3.0 | f6f4c46e6b791e149daed7bca695c670 | 0.495638 | 3.208651 | false | false | false | false |
armandas/Arcade | vga_sync.vhd | 2 | 3,419 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga is
port(
clk, not_reset: in std_logic;
hsync, vsync: out std_logic;
video_on, p_tick: out std_logic;
pixel_x, pixel_y: out std_logic_vector (9 downto 0)
);
end vga;
architecture sync of vga is
-- VGA 640x480 sync parameters
constant HD: integer := 640; -- horizontal display area
constant HF: integer := 16; -- h. front porch
constant HB: integer := 48; -- h. back porch
constant HR: integer := 96; -- h. retrace
constant VD: integer := 480; -- vertical display area
constant VF: integer := 11; -- v. front porch
constant VB: integer := 31; -- v. back porch
constant VR: integer := 2; -- v. retrace
-- mod-2 counter
signal mod2, mod2_next: std_logic;
-- sync counters
signal v_count, v_count_next: std_logic_vector(9 downto 0);
signal h_count, h_count_next: std_logic_vector(9 downto 0);
-- output buffer
signal v_sync, h_sync: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signal
signal h_end, v_end, pixel_tick: std_logic;
begin
process(clk, not_reset)
begin
if not_reset = '0' then
mod2 <= '0';
v_count <= (others => '0');
h_count <= (others => '0');
v_sync <= '0';
h_sync <= '0';
elsif clk'event and clk = '0' then
mod2 <= mod2_next;
v_count <= v_count_next;
h_count <= h_count_next;
v_sync <= v_sync_next;
h_sync <= h_sync_next;
end if;
end process;
-- mod-2 circuit to generate 25 MHz enable tick
mod2_next <= not mod2;
-- 25 MHz pixel tick
pixel_tick <= '1' when mod2 = '1' else '0';
-- end of counters (799 and 524 pixels)
h_end <= '1' when h_count = (HD + HF + HB + HR - 1) else '0';
v_end <= '1' when v_count = (VD + VF + VB + VR - 1) else '0';
-- mod-800 horizontal sync counter
process(h_count, h_end, pixel_tick)
begin
if pixel_tick = '1' then
if h_end = '1' then
h_count_next <= (others => '0');
else
h_count_next <= h_count + 1;
end if;
else
h_count_next <= h_count;
end if;
end process;
-- mod-525 vertical sync counter
process(v_count, h_end, v_end, pixel_tick)
begin
if pixel_tick = '1' and h_end = '1' then
if v_end = '1' then
v_count_next <= (others => '0');
else
v_count_next <= v_count + 1;
end if;
else
v_count_next <= v_count;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <= '1' when (h_count >= (HD + HF)) and
(h_count <= (HD + HF + HR - 1)) else
'0';
v_sync_next <= '1' when (v_count >= (VD + VF)) and
(v_count <= (VD + VF + VR - 1)) else
'0';
-- video on/off
video_on <= '1' when (h_count < HD) and (v_count < VD) else '0';
-- output signal
hsync <= h_sync;
vsync <= v_sync;
pixel_x <= h_count;
pixel_y <= v_count;
p_tick <= pixel_tick;
end sync;
| bsd-2-clause | 249b56bca7c2f86f2aace6b63e077c5e | 0.495759 | 3.443102 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_sim/mblite_sdram_tb.vhd | 2 | 2,359 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: fpga_mem_test_v5_tb
-- Date:2015-01-02
-- Author: Gideon
-- Description: Testbench for FPGA mem tester
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mblite_sdram_tb is
end entity;
architecture arch of mblite_sdram_tb is
signal CLOCK_50 : std_logic := '0';
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
signal MOTOR_LEDn : std_logic;
signal DISK_ACTn : std_logic;
signal BUTTON : std_logic_vector(0 to 2) := "111";
begin
CLOCK_50 <= not CLOCK_50 after 10 ns;
fpga: entity work.mblite_sdram
port map (
CLOCK_50 => CLOCK_50,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA,
SDRAM_DQ => SDRAM_DQ,
BUTTON => BUTTON,
MOTOR_LEDn => MOTOR_LEDn,
DISK_ACTn => DISK_ACTn );
ram: entity work.dram_8
generic map(
g_cas_latency => 3,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2
)
port map(
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A,
BA => SDRAM_BA,
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ
);
end arch;
| gpl-3.0 | bbea0f910f46d8e567a755d3a6e12353 | 0.467147 | 3.651703 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_logic_32.vhd | 1 | 54,756 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
use work.dma_bus_pkg.all;
entity ultimate_logic_32 is
generic (
g_version : unsigned(7 downto 0) := X"1C";
g_simulation : boolean := true;
g_ultimate2plus : boolean := false;
g_ultimate_64 : boolean := false;
g_clock_freq : natural := 50_000_000;
g_numerator : natural := 8;
g_denominator : natural := 25;
g_baud_rate : natural := 115_200;
g_timer_rate : natural := 200_000;
g_fpga_type : natural := 0;
g_cartreset_init: std_logic := '0';
g_boot_stop : boolean := false;
g_direct_dma : boolean := false;
g_ext_freeze_act: boolean := false;
g_microblaze : boolean := true;
g_big_endian : boolean := true;
g_boot_rom : boolean := false;
g_video_overlay : boolean := false;
g_icap : boolean := false;
g_uart : boolean := true;
g_uart_rx : boolean := false;
g_drive_1541 : boolean := true;
g_drive_1541_2 : boolean := false;
g_mm_drive : boolean := true;
g_hardware_gcr : boolean := true;
g_cartridge : boolean := true;
g_eeprom : boolean := true;
g_command_intf : boolean := true;
g_acia : boolean := false;
g_stereo_sid : boolean := true;
g_8voices : boolean := true;
g_ram_expansion : boolean := true;
g_extended_reu : boolean := false;
g_hardware_iec : boolean := true;
g_c2n_streamer : boolean := true;
g_c2n_recorder : boolean := true;
g_drive_sound : boolean := true;
g_rtc_chip : boolean := true;
g_rtc_timer : boolean := false;
g_usb_host2 : boolean := true;
g_spi_flash : boolean := true;
g_vic_copper : boolean := false;
g_sampler : boolean := true;
g_rmii : boolean := false;
g_sdcard : boolean := false;
g_kernal_repl : boolean := true );
port (
-- globals
sys_clock : in std_logic;
sys_reset : in std_logic;
mb_reset : in std_logic := '0';
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- slot side
BUFFER_ENn : out std_logic := '1';
phi2_i : in std_logic := '0';
dotclk_i : in std_logic := '0';
rstn_o : out std_logic := '1';
rstn_i : in std_logic := '1';
slot_addr_o : out unsigned(15 downto 0);
slot_addr_i : in unsigned(15 downto 0) := (others => '1');
slot_addr_tl: out std_logic;
slot_addr_th: out std_logic;
slot_data_o : out std_logic_vector(7 downto 0);
slot_data_i : in std_logic_vector(7 downto 0) := (others => '1');
slot_data_t : out std_logic;
rwn_i : in std_logic := '1';
rwn_o : out std_logic;
ultimax : out std_logic;
exromn_i : in std_logic := '1';
exromn_o : out std_logic;
gamen_i : in std_logic := '1';
gamen_o : out std_logic;
irqn_i : in std_logic := '1';
irqn_o : out std_logic;
nmin_i : in std_logic := '1';
nmin_o : out std_logic;
ba_i : in std_logic := '0';
dman_o : out std_logic;
romhn_i : in std_logic := '1';
romln_i : in std_logic := '1';
io1n_i : in std_logic := '1';
io2n_i : in std_logic := '1';
VCC : in std_logic := '1';
freeze_activate : in std_logic := '0';
-- local bus side
mem_inhibit : out std_logic;
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
-- Direct DMA for U64
direct_dma_req : out t_dma_req := c_dma_req_init;
direct_dma_resp : in t_dma_resp := c_dma_resp_init;
-- Audio outputs
audio_speaker : out signed(12 downto 0);
audio_left : out signed(18 downto 0);
audio_right : out signed(18 downto 0);
speaker_vol : in std_logic_vector(3 downto 0) := X"0";
aud_drive1 : out signed(17 downto 0);
aud_drive2 : out signed(17 downto 0);
aud_tape_r : out signed(17 downto 0);
aud_tape_w : out signed(17 downto 0);
aud_samp_l : out signed(17 downto 0);
aud_samp_r : out signed(17 downto 0);
aud_sid_1 : out signed(17 downto 0);
aud_sid_2 : out signed(17 downto 0);
-- IEC bus
-- actual levels of the pins --
iec_reset_i : in std_logic := '1';
iec_atn_i : in std_logic := '1';
iec_data_i : in std_logic := '1';
iec_clock_i : in std_logic := '1';
iec_srq_i : in std_logic := '1';
iec_reset_o : out std_logic := '1';
iec_atn_o : out std_logic;
iec_data_o : out std_logic;
iec_clock_o : out std_logic;
iec_srq_o : out std_logic;
MOTOR_LEDn : out std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
motor_led2n : out std_logic;
disk_act2n : out std_logic;
power_led3n : out std_logic;
act_led3n : out std_logic;
-- Parallel cable pins
drv_track_is_0 : out std_logic;
drv_via1_port_a_o : out std_logic_vector(7 downto 0);
drv_via1_port_a_i : in std_logic_vector(7 downto 0);
drv_via1_port_a_t : out std_logic_vector(7 downto 0);
drv_via1_ca2_o : out std_logic;
drv_via1_ca2_i : in std_logic;
drv_via1_ca2_t : out std_logic;
drv_via1_cb1_o : out std_logic;
drv_via1_cb1_i : in std_logic;
drv_via1_cb1_t : out std_logic;
-- Debug port
drv_debug_data : out std_logic_vector(31 downto 0);
drv_debug_valid : out std_logic;
c64_debug_data : out std_logic_vector(31 downto 0);
c64_debug_valid : out std_logic;
c64_debug_select : in std_logic_vector(2 downto 0) := "000";
usb_debug_data : out std_logic_vector(31 downto 0);
usb_debug_valid : out std_logic;
usb_error_pulse : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic := '1';
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic := '1';
SD_CARDDETn : in std_logic := '1';
SD_DATA : inout std_logic_vector(2 downto 1) := "ZZ";
-- LED interface
LED_CLK : out std_logic;
LED_DATA : out std_logic;
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic := '0';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic := '0';
-- USB Interface (ULPI)
ULPI_NXT : in std_logic := '0';
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic := '0';
ULPI_DATA : inout std_logic_vector(7 downto 0) := "ZZZZZZZZ";
-- Cassette Interface
c2n_read_in : in std_logic := '1';
c2n_write_in : in std_logic := '1';
c2n_read_out : out std_logic := '1';
c2n_write_out : out std_logic := '1';
c2n_read_en : out std_logic := '0';
c2n_write_en : out std_logic := '0';
c2n_sense_in : in std_logic := '0';
c2n_sense_out : out std_logic := '0';
c2n_motor_in : in std_logic := '0';
c2n_motor_out : out std_logic := '0';
-- Ethernet interface
eth_clock : in std_logic := '0';
eth_reset : in std_logic := '0';
eth_tx_data : out std_logic_vector(7 downto 0);
eth_tx_eof : out std_logic;
eth_tx_valid : out std_logic;
eth_tx_ready : in std_logic;
eth_rx_data : in std_logic_vector(7 downto 0);
eth_rx_sof : in std_logic;
eth_rx_eof : in std_logic;
eth_rx_valid : in std_logic;
-- Interface to other graphical output (Full HD of course and in 3D!) ;-)
vid_clock : in std_logic := '0';
vid_reset : in std_logic := '0';
vid_h_count : in unsigned(11 downto 0) := (others => '0');
vid_v_count : in unsigned(11 downto 0) := (others => '0');
vid_active : out std_logic;
vid_opaque : out std_logic;
vid_data : out unsigned(3 downto 0);
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '1');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '1');
-- Simulation port
ext_io_req : in t_io_req := c_io_req_init;
ext_io_resp : out t_io_resp;
ext_mem_req : in t_mem_req_32 := c_mem_req_32_init;
ext_mem_resp: out t_mem_resp_32;
cpu_irq : out std_logic;
trigger : in std_logic := '0';
sw_trigger : out std_logic;
-- Buttons
button : in std_logic_vector(2 downto 0) );
end ultimate_logic_32;
architecture logic of ultimate_logic_32 is
function to_std(b : boolean) return std_logic is
begin
if b then
return '1';
end if;
return '0';
end function;
impure function create_capabilities return std_logic_vector is
variable cap : std_logic_vector(31 downto 0) := (others => '0');
begin
cap(00) := to_std(g_uart);
cap(01) := to_std(g_drive_1541);
cap(02) := to_std(g_drive_1541_2);
cap(03) := to_std(g_drive_sound);
cap(04) := to_std(g_hardware_gcr);
cap(05) := to_std(g_hardware_iec);
cap(06) := '0'; -- unused
cap(07) := to_std(g_c2n_streamer);
cap(08) := to_std(g_c2n_recorder);
cap(09) := to_std(g_cartridge);
cap(10) := to_std(g_ram_expansion);
cap(11) := to_std(g_mm_drive);
cap(12) := to_std(g_rtc_chip);
cap(13) := to_std(g_rtc_timer);
cap(14) := to_std(g_spi_flash);
cap(15) := to_std(g_icap);
cap(16) := to_std(g_extended_reu);
cap(17) := to_std(g_stereo_sid);
cap(18) := to_std(g_command_intf);
cap(19) := to_std(g_vic_copper);
cap(20) := to_std(g_video_overlay);
cap(21) := to_std(g_sampler);
cap(22) := to_std(g_eeprom);
cap(23) := to_std(g_usb_host2);
cap(24) := to_std(g_rmii);
cap(25) := to_std(g_ultimate2plus);
cap(26) := to_std(g_ultimate_64);
cap(27) := to_std(g_acia);
cap(29 downto 28) := std_logic_vector(to_unsigned(g_fpga_type, 2));
cap(30) := to_std(g_boot_rom);
cap(31) := to_std(g_simulation);
return cap;
end function;
constant c_capabilities : std_logic_vector(31 downto 0) := create_capabilities;
constant c_tag_1541_cpu_1 : std_logic_vector(7 downto 0) := X"01";
constant c_tag_1541_floppy_1 : std_logic_vector(7 downto 0) := X"02";
constant c_tag_1541_disk_1 : std_logic_vector(7 downto 0) := X"03";
constant c_tag_1541_audio_1 : std_logic_vector(7 downto 0) := X"04";
constant c_tag_1541_cpu_2 : std_logic_vector(7 downto 0) := X"05";
constant c_tag_1541_floppy_2 : std_logic_vector(7 downto 0) := X"06";
constant c_tag_1541_disk_2 : std_logic_vector(7 downto 0) := X"07";
constant c_tag_1541_audio_2 : std_logic_vector(7 downto 0) := X"08";
constant c_tag_slot : std_logic_vector(7 downto 0) := X"09";
constant c_tag_reu : std_logic_vector(7 downto 0) := X"0A";
constant c_tag_usb2 : std_logic_vector(7 downto 0) := X"0B";
constant c_tag_cpu_i : std_logic_vector(7 downto 0) := X"0C";
constant c_tag_cpu_d : std_logic_vector(7 downto 0) := X"0D";
constant c_tag_rmii : std_logic_vector(7 downto 0) := X"0E"; -- and 0F
-- Timing
signal tick_16MHz : std_logic;
signal tick_4MHz : std_logic;
signal tick_1MHz : std_logic;
signal tick_1kHz : std_logic;
-- Memory interface
signal mem_req_32_cpu : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_cpu : t_mem_resp_32 := c_mem_resp_32_init;
-- converted to 32 bits
signal mem_req_32_1541 : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_1541 : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_1541_2 : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_1541_2 : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_cart : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_cart : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_usb : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_usb : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_rmii : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_rmii : t_mem_resp_32 := c_mem_resp_32_init;
-- IO Bus
signal cpu_io_busy : std_logic;
signal cpu_io_req : t_io_req;
signal cpu_io_resp : t_io_resp := c_io_resp_init;
signal io_req : t_io_req;
signal io_resp : t_io_resp := c_io_resp_init;
signal io_req_1541 : t_io_req;
signal io_resp_1541 : t_io_resp := c_io_resp_init;
signal io_req_1541_1 : t_io_req;
signal io_resp_1541_1 : t_io_resp := c_io_resp_init;
signal io_req_1541_2 : t_io_req;
signal io_resp_1541_2 : t_io_resp := c_io_resp_init;
signal io_req_itu : t_io_req;
signal io_resp_itu : t_io_resp := c_io_resp_init;
signal io_req_cart : t_io_req;
signal io_resp_cart : t_io_resp := c_io_resp_init;
signal io_req_io : t_io_req;
signal io_resp_io : t_io_resp := c_io_resp_init;
signal io_req_big_io : t_io_req;
signal io_resp_big_io : t_io_resp := c_io_resp_init;
signal io_req_sd : t_io_req;
signal io_resp_sd : t_io_resp := c_io_resp_init;
signal io_req_rtc : t_io_req;
signal io_resp_rtc : t_io_resp := c_io_resp_init;
signal io_req_rtc_tmr : t_io_req;
signal io_resp_rtc_tmr : t_io_resp := c_io_resp_init;
signal io_req_gcr_dec : t_io_req;
signal io_resp_gcr_dec : t_io_resp := c_io_resp_init;
signal io_req_flash : t_io_req;
signal io_resp_flash : t_io_resp := c_io_resp_init;
signal io_req_iec : t_io_req;
signal io_resp_iec : t_io_resp := c_io_resp_init;
signal io_req_usb : t_io_req;
signal io_resp_usb : t_io_resp := c_io_resp_init;
signal io_req_c2n : t_io_req;
signal io_resp_c2n : t_io_resp := c_io_resp_init;
signal io_req_c2n_rec : t_io_req;
signal io_resp_c2n_rec : t_io_resp := c_io_resp_init;
signal io_req_icap : t_io_req;
signal io_resp_icap : t_io_resp := c_io_resp_init;
signal io_req_aud_sel : t_io_req;
signal io_resp_aud_sel : t_io_resp := c_io_resp_init;
signal io_req_rmii : t_io_req;
signal io_resp_rmii : t_io_resp := c_io_resp_init;
signal io_req_debug : t_io_req;
signal io_resp_debug : t_io_resp := c_io_resp_init;
signal io_irq : std_logic;
signal drive_sample_1 : signed(12 downto 0) := (others => '0');
signal drive_sample_2 : signed(12 downto 0) := (others => '0');
signal audio_tape_read : signed(18 downto 0);
signal audio_tape_write : signed(18 downto 0);
signal sid_left : signed(17 downto 0);
signal sid_right : signed(17 downto 0);
signal samp_left : signed(17 downto 0);
signal samp_right : signed(17 downto 0);
signal audio_select_left : std_logic_vector(3 downto 0);
signal audio_select_right : std_logic_vector(3 downto 0);
-- IEC signal routing
signal atn_o, atn_i : std_logic := '1';
signal clk_o, clk_i : std_logic := '1';
signal data_o, data_i : std_logic := '1';
signal srq_o, srq_i : std_logic := '1';
signal atn_o_2 : std_logic := '1';
signal clk_o_2 : std_logic := '1';
signal data_o_2 : std_logic := '1';
signal srq_o_2 : std_logic := '1';
signal hw_atn_o : std_logic := '1';
signal hw_clk_o : std_logic := '1';
signal hw_data_o : std_logic := '1';
signal hw_srq_o : std_logic := '1';
-- Cassette
signal c2n_play_sense_out : std_logic := '0';
signal c2n_play_motor_out : std_logic := '0';
signal c2n_rec_sense_out : std_logic := '0';
signal c2n_rec_motor_out : std_logic := '0';
signal c2n_read_en_i : std_logic := '0';
signal c2n_read_out_i : std_logic := '0';
-- miscellaneous interconnect
signal c64_reset_in : std_logic;
signal c64_reset_in_n : std_logic;
signal c64_irq_n : std_logic;
signal c64_irq : std_logic;
signal phi2_tick : std_logic;
signal c64_stopped : std_logic;
signal cas_read_c : std_logic;
signal cas_write_c : std_logic;
signal busy_led : std_logic;
signal sd_act_stretched : std_logic := '0';
signal disk_led_n : std_logic := '1';
signal motor_led_n : std_logic := '1';
signal cart_led_n : std_logic := '1';
signal c2n_pull_sense : std_logic := '0';
signal freezer_state : std_logic_vector(1 downto 0);
signal dirty_led_1_n : std_logic := '1';
signal dirty_led_2_n : std_logic := '1';
signal dman_oi : std_logic;
signal trigger_1 : std_logic;
signal trigger_2 : std_logic;
signal sync : std_logic;
signal sys_irq_usb : std_logic := '0';
signal sys_irq_tape : std_logic := '0';
signal sys_irq_iec : std_logic := '0';
signal sys_irq_cmdif : std_logic := '0';
signal sys_irq_acia : std_logic := '0';
signal sys_irq_eth_tx : std_logic := '0';
signal sys_irq_eth_rx : std_logic := '0';
signal sys_irq_1541_1 : std_logic := '0';
signal sys_irq_1541_2 : std_logic := '0';
signal misc_io : std_logic_vector(7 downto 0);
signal audio_speaker_tmp : signed(17 downto 0);
begin
r_mb: if g_microblaze generate
signal invalidate : std_logic;
signal inv_addr : std_logic_vector(31 downto 0);
begin
i_cpu: entity work.mblite_wrapper
generic map (
g_tag_i => c_tag_cpu_i,
g_tag_d => c_tag_cpu_d )
port map (
clock => sys_clock,
reset => sys_reset,
mb_reset => mb_reset,
irq_i => io_irq,
disable_i => misc_io(1),
disable_d => misc_io(2),
invalidate => invalidate,
inv_addr => inv_addr,
-- memory interface
mem_req => mem_req_32_cpu,
mem_resp => mem_resp_32_cpu,
io_busy => cpu_io_busy,
io_req => cpu_io_req,
io_resp => cpu_io_resp );
-- TODO: also invalidate for rmii
invalidate <= misc_io(0) when (mem_resp_32_usb.rack_tag(5 downto 0) = c_tag_usb2(5 downto 0)) and (mem_req_32_usb.read_writen = '0') else '0';
inv_addr(31 downto 26) <= (others => '0');
inv_addr(25 downto 0) <= std_logic_vector(mem_req_32_usb.address);
end generate;
-- r_no_mb: if not g_microblaze generate
-- -- route the memory access of the processor to the outside world
-- mem_req_32_cpu <= ext_mem_req;
-- ext_mem_resp <= mem_resp_32_cpu;
-- end generate;
cpu_irq <= io_irq;
i_io_arb: entity work.io_bus_arbiter_pri
generic map (
g_ports => 2 )
port map (
clock => sys_clock,
reset => sys_reset,
reqs(0) => ext_io_req,
reqs(1) => cpu_io_req,
resps(0) => ext_io_resp,
resps(1) => cpu_io_resp,
req => io_req,
resp => io_resp );
i_timing: entity work.fractional_div
generic map(
g_numerator => g_numerator,
g_denominator => g_denominator
)
port map(
clock => sys_clock,
tick => tick_16MHz,
tick_by_4 => tick_4MHz,
tick_by_16 => tick_1MHz,
one_16000 => tick_1kHz
);
c64_reset_in <= not c64_reset_in_n;
i_itu: entity work.itu
generic map (
g_version => g_version,
g_capabilities => c_capabilities,
g_uart => g_uart,
g_uart_rx => g_uart_rx,
g_edge_init => "10000101",
g_edge_write => false,
g_baudrate => g_baud_rate )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_itu,
io_resp => io_resp_itu,
tick_4MHz => tick_4MHz,
tick_1us => tick_1MHz,
tick_1ms => tick_1kHz,
buttons => button,
irq_high(0) => sys_irq_acia,
irq_high(1) => sys_irq_1541_1,
irq_high(2) => sys_irq_1541_2,
irq_high(7 downto 3) => "00000",
irq_in(7) => c64_reset_in,
irq_in(6) => sys_irq_eth_tx,
irq_in(5) => sys_irq_eth_rx,
irq_in(4) => sys_irq_cmdif,
irq_in(3) => sys_irq_tape,
irq_in(2) => sys_irq_usb,
irq_out => io_irq,
busy_led => busy_led,
misc_io => misc_io,
uart_txd => UART_TXD,
uart_rxd => UART_RXD );
r_drive: if g_drive_1541 generate
begin
r_mm: if g_mm_drive generate
i_drive: entity work.mm_drive
generic map (
g_big_endian => g_big_endian,
g_cpu_tag => c_tag_1541_cpu_1,
g_floppy_tag => c_tag_1541_floppy_1,
g_disk_tag => c_tag_1541_disk_1,
g_audio_tag => c_tag_1541_audio_1,
g_audio => g_drive_sound,
g_audio_base => X"0EC0000",
g_ram_base => X"0EE0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- timing
tick_16MHz => tick_16MHz,
tick_4MHz => tick_4MHz,
tick_1kHz => tick_1kHz,
-- slave port on io bus
io_req => io_req_1541_1,
io_resp => io_resp_1541_1,
io_irq => sys_irq_1541_1,
-- master port on memory bus
mem_req => mem_req_32_1541,
mem_resp => mem_resp_32_1541,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
fast_clk_o => srq_o,
fast_clk_i => srq_i,
iec_reset_n => iec_reset_i,
c64_reset_n => c64_reset_in_n,
-- Debug port
debug_data => drv_debug_data,
debug_valid => drv_debug_valid,
-- Parallel cable pins
via1_port_a_o => drv_via1_port_a_o,
via1_port_a_i => drv_via1_port_a_i,
via1_port_a_t => drv_via1_port_a_t,
via1_ca2_o => drv_via1_ca2_o,
via1_ca2_i => drv_via1_ca2_i,
via1_ca2_t => drv_via1_ca2_t,
via1_cb1_o => drv_via1_cb1_o,
via1_cb1_i => drv_via1_cb1_i,
via1_cb1_t => drv_via1_cb1_t,
-- LED
act_led_n => disk_led_n,
motor_led_n => motor_led_n,
dirty_led_n => dirty_led_1_n,
-- audio out
audio_sample => drive_sample_1 );
end generate;
r_standard: if not g_mm_drive generate
i_drive: entity work.c1541_drive
generic map (
g_big_endian => g_big_endian,
g_cpu_tag => c_tag_1541_cpu_1,
g_floppy_tag => c_tag_1541_floppy_1,
g_audio_tag => c_tag_1541_audio_1,
g_audio => g_drive_sound,
g_audio_base => X"0EC0000",
g_ram_base => X"0EE0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- timing
tick_16MHz => tick_16MHz,
tick_4MHz => tick_4MHz,
tick_1kHz => tick_1kHz,
-- slave port on io bus
io_req => io_req_1541_1,
io_resp => io_resp_1541_1,
-- master port on memory bus
mem_req => mem_req_32_1541,
mem_resp => mem_resp_32_1541,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
iec_reset_n => iec_reset_i,
c64_reset_n => c64_reset_in_n,
-- Debug port
debug_data => drv_debug_data,
debug_valid => drv_debug_valid,
-- Parallel cable pins
via1_port_a_o => drv_via1_port_a_o,
via1_port_a_i => drv_via1_port_a_i,
via1_port_a_t => drv_via1_port_a_t,
via1_ca2_o => drv_via1_ca2_o,
via1_ca2_i => drv_via1_ca2_i,
via1_ca2_t => drv_via1_ca2_t,
via1_cb1_o => drv_via1_cb1_o,
via1_cb1_i => drv_via1_cb1_i,
via1_cb1_t => drv_via1_cb1_t,
-- LED
act_led_n => disk_led_n,
motor_led_n => motor_led_n,
dirty_led_n => dirty_led_1_n,
-- audio out
audio_sample => drive_sample_1 );
end generate;
end generate;
audio_speaker_tmp <= (drive_sample_1 + drive_sample_2) * signed(resize(unsigned(speaker_vol),5));
audio_speaker <= audio_speaker_tmp(16 downto 4);
r_drive_2: if g_drive_1541_2 generate
-- Parallel cable pins
signal via1_port_a_o : std_logic_vector(7 downto 0);
signal via1_port_a_i : std_logic_vector(7 downto 0);
signal via1_port_a_t : std_logic_vector(7 downto 0);
signal via1_ca2_o : std_logic;
signal via1_ca2_i : std_logic;
signal via1_ca2_t : std_logic;
signal via1_cb1_o : std_logic;
signal via1_cb1_i : std_logic;
signal via1_cb1_t : std_logic;
begin
r_mm: if g_mm_drive generate
i_drive: entity work.mm_drive
generic map (
g_big_endian => g_big_endian,
g_cpu_tag => c_tag_1541_cpu_2,
g_floppy_tag => c_tag_1541_floppy_2,
g_disk_tag => c_tag_1541_disk_2,
g_audio_tag => c_tag_1541_audio_2,
g_audio => g_drive_sound,
g_audio_base => X"0EB0000",
g_ram_base => X"0ED0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- timing
tick_16MHz => tick_16MHz,
tick_4MHz => tick_4MHz,
tick_1kHz => tick_1kHz,
-- slave port on io bus
io_req => io_req_1541_2,
io_resp => io_resp_1541_2,
io_irq => sys_irq_1541_2,
-- master port on memory bus
mem_req => mem_req_32_1541_2,
mem_resp => mem_resp_32_1541_2,
-- serial bus pins
atn_o => atn_o_2, -- open drain
atn_i => atn_i,
clk_o => clk_o_2, -- open drain
clk_i => clk_i,
data_o => data_o_2, -- open drain
data_i => data_i,
fast_clk_o => srq_o_2,
fast_clk_i => srq_i,
iec_reset_n => iec_reset_i,
c64_reset_n => c64_reset_in_n,
-- Parallel cable pins
via1_port_a_o => via1_port_a_o,
via1_port_a_i => via1_port_a_i,
via1_port_a_t => via1_port_a_t,
via1_ca2_o => via1_ca2_o,
via1_ca2_i => via1_ca2_i,
via1_ca2_t => via1_ca2_t,
via1_cb1_o => via1_cb1_o,
via1_cb1_i => via1_cb1_i,
via1_cb1_t => via1_cb1_t,
-- LED
act_led_n => disk_act2n,
motor_led_n => motor_led2n,
-- dirty_led_n => dirty_led_2_n,
-- audio out
audio_sample => drive_sample_2 );
end generate;
r_standard: if not g_mm_drive generate
i_drive: entity work.c1541_drive
generic map (
g_big_endian => g_big_endian,
g_cpu_tag => c_tag_1541_cpu_2,
g_floppy_tag => c_tag_1541_floppy_2,
g_audio_tag => c_tag_1541_audio_2,
g_audio => g_drive_sound,
g_audio_base => X"0EB0000",
g_ram_base => X"0ED0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- timing
tick_16MHz => tick_16MHz,
tick_4MHz => tick_4MHz,
tick_1kHz => tick_1kHz,
-- slave port on io bus
io_req => io_req_1541_2,
io_resp => io_resp_1541_2,
-- master port on memory bus
mem_req => mem_req_32_1541_2,
mem_resp => mem_resp_32_1541_2,
-- serial bus pins
atn_o => atn_o_2, -- open drain
atn_i => atn_i,
clk_o => clk_o_2, -- open drain
clk_i => clk_i,
data_o => data_o_2, -- open drain
data_i => data_i,
iec_reset_n => iec_reset_i,
c64_reset_n => c64_reset_in_n,
-- Parallel cable pins
via1_port_a_o => via1_port_a_o,
via1_port_a_i => via1_port_a_i,
via1_port_a_t => via1_port_a_t,
via1_ca2_o => via1_ca2_o,
via1_ca2_i => via1_ca2_i,
via1_ca2_t => via1_ca2_t,
via1_cb1_o => via1_cb1_o,
via1_cb1_i => via1_cb1_i,
via1_cb1_t => via1_cb1_t,
-- LED
act_led_n => disk_act2n,
motor_led_n => motor_led2n,
-- dirty_led_n => dirty_led_2_n,
-- audio out
audio_sample => drive_sample_2 );
end generate;
via1_port_a_i <= via1_port_a_o or not via1_port_a_t;
via1_ca2_i <= via1_ca2_o or not via1_ca2_t;
via1_cb1_i <= via1_cb1_o or not via1_cb1_t;
end generate;
r_cart: if g_cartridge generate
i_slot_srv: entity work.slot_server_v4
generic map (
g_clock_freq => g_clock_freq,
g_direct_dma => g_direct_dma,
g_ext_freeze_act=> g_ext_freeze_act,
g_tag_slot => c_tag_slot,
g_tag_reu => c_tag_reu,
g_ram_base_reu => X"1000000", -- should be on 16M boundary, or should be limited in size
g_rom_base_cart => X"0F00000", -- should be on a 1M boundary
g_ram_base_cart => X"0EF0000", -- should be on a 64K boundary
g_kernal_base => X"0EA8000", -- should be on a 32K boundary
g_big_endian => g_big_endian,
g_cartreset_init=> g_cartreset_init,
g_boot_stop => g_boot_stop,
g_control_read => true,
g_kernal_repl => g_kernal_repl,
g_ram_expansion => g_ram_expansion,
g_extended_reu => g_extended_reu,
g_command_intf => g_command_intf,
g_acia => g_acia,
g_eeprom => g_eeprom,
g_sampler => g_sampler,
g_implement_sid => g_stereo_sid,
g_sid_voices => 16,
g_8voices => g_8voices,
g_vic_copper => g_vic_copper )
port map (
clock => sys_clock,
reset => sys_reset,
-- Cartridge pins
VCC => VCC,
phi2_i => phi2_i,
rstn_i => rstn_i,
rstn_o => rstn_o,
slot_addr_i => slot_addr_i,
slot_addr_o => slot_addr_o,
slot_addr_tl => slot_addr_tl,
slot_addr_th => slot_addr_th,
slot_data_i => slot_data_i,
slot_data_o => slot_data_o,
slot_data_t => slot_data_t,
rwn_i => rwn_i,
rwn_o => rwn_o, -- goes with addr_t
ba_i => ba_i,
dman_o => dman_oi,
ultimax => ultimax,
exromn_i => exromn_i,
exromn_o => exromn_o,
gamen_i => gamen_i,
gamen_o => gamen_o,
irqn_i => irqn_i,
irqn_o => irqn_o,
nmin_i => nmin_i,
nmin_o => nmin_o,
romhn_i => romhn_i,
romln_i => romln_i,
io1n_i => io1n_i,
io2n_i => io2n_i,
-- other hardware pins
BUFFER_ENn => BUFFER_ENn,
sense => c2n_sense_in,
buttons => button,
cart_led_n => cart_led_n,
-- audio
sid_left => sid_left,
sid_right => sid_right,
samp_left => samp_left,
samp_right => samp_right,
-- debug
freeze_activate => freeze_activate,
freezer_state => freezer_state,
sync => sync,
sw_trigger => sw_trigger,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
debug_data => c64_debug_data,
debug_valid => c64_debug_valid,
debug_select => c64_debug_select,
-- timing output
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
-- master on memory bus
memctrl_inhibit => mem_inhibit,
mem_req => mem_req_32_cart,
mem_resp => mem_resp_32_cart,
direct_dma_req => direct_dma_req,
direct_dma_resp => direct_dma_resp,
-- slave on io bus
io_req => io_req_cart,
io_resp => io_resp_cart,
io_irq_cmd => sys_irq_cmdif,
io_irq_acia => sys_irq_acia );
dman_o <= dman_oi;
end generate;
i_split1: entity work.io_bus_splitter
generic map (
g_range_lo => 17,
g_range_hi => 19,
g_ports => 8 )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_itu, -- 4000000 ( 16 ... 400000F)
reqs(1) => io_req_1541, -- 4020000 ( 8K... 4021FFF) & 4024000 for drive B
reqs(2) => io_req_cart, -- 4040000 (128K... 405FFFF)
reqs(3) => io_req_io, -- 4060000 ( 2K... 4060FFF)
reqs(4) => io_req_usb, -- 4080000 ( 8K... 4081FFF)
reqs(5) => io_req_c2n, -- 40A0000 ( 4K... 40A0FFF)
reqs(6) => io_req_c2n_rec, -- 40C0000 ( 4K... 40C0FFF)
reqs(7) => io_req_big_io, -- 40E0000 (128K... 40FFFFF)
resps(0) => io_resp_itu,
resps(1) => io_resp_1541,
resps(2) => io_resp_cart,
resps(3) => io_resp_io,
resps(4) => io_resp_usb,
resps(5) => io_resp_c2n,
resps(6) => io_resp_c2n_rec,
resps(7) => io_resp_big_io );
i_split2: entity work.io_bus_splitter
generic map (
g_range_lo => 14,
g_range_hi => 15,
g_ports => 3 )
port map (
clock => sys_clock,
req => io_req_1541,
resp => io_resp_1541,
reqs(0) => io_req_1541_1, -- 4020000
reqs(1) => io_req_1541_2, -- 4024000
reqs(2) => io_req_iec, -- 4028000
resps(0) => io_resp_1541_1,
resps(1) => io_resp_1541_2,
resps(2) => io_resp_iec );
i_split3: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 11,
g_ports => 9 )
port map (
clock => sys_clock,
req => io_req_io,
resp => io_resp_io,
reqs(0) => io_req_sd, -- 4060000
reqs(1) => io_req_rtc, -- 4060100
reqs(2) => io_req_flash, -- 4060200
reqs(3) => io_req_debug, -- 4060300
reqs(4) => io_req_rtc_tmr, -- 4060400
reqs(5) => io_req_gcr_dec, -- 4060500
reqs(6) => io_req_icap, -- 4060600
reqs(7) => io_req_aud_sel, -- 4060700
reqs(8) => io_req_rmii, -- 4060800
resps(0) => io_resp_sd,
resps(1) => io_resp_rtc,
resps(2) => io_resp_flash,
resps(3) => io_resp_debug,
resps(4) => io_resp_rtc_tmr,
resps(5) => io_resp_gcr_dec,
resps(6) => io_resp_icap,
resps(7) => io_resp_aud_sel,
resps(8) => io_resp_rmii );
r_usb2: if g_usb_host2 generate
i_usb2: entity work.usb_host_nano
generic map (
g_big_endian => g_big_endian,
g_tag => c_tag_usb2,
g_simulation => g_simulation )
port map (
clock => ULPI_CLOCK,
reset => ulpi_reset,
ulpi_nxt => ulpi_nxt,
ulpi_dir => ulpi_dir,
ulpi_stp => ulpi_stp,
ulpi_data => ulpi_data,
debug_data => usb_debug_data,
debug_valid => usb_debug_valid,
error_pulse => usb_error_pulse,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_mem_req => mem_req_32_usb,
sys_mem_resp => mem_resp_32_usb,
sys_io_req => io_req_usb,
sys_io_resp => io_resp_usb,
sys_irq => sys_irq_usb );
end generate;
r_sdcard: if g_sdcard generate
signal sd_busy : std_logic;
begin
i_sd: entity work.spi_peripheral_io
generic map (
g_fixed_rate => false,
g_init_rate => 500,
g_crc => true )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_sd,
io_resp => io_resp_sd,
busy => sd_busy,
SD_DETECTn => SD_CARDDETn,
SD_WRPROTn => '1', --SD_WRPROTn,
SPI_SSn => SD_SSn,
SPI_CLK => SD_CLK,
SPI_MOSI => SD_MOSI,
SPI_MISO => SD_MISO );
i_stretch: entity work.pulse_stretch
generic map ( g_clock_freq / 200) -- 5 ms
port map (
clock => sys_clock,
reset => sys_reset,
pulse_in => sd_busy,
pulse_out => sd_act_stretched );
end generate;
r_no_sdcard: if not g_sdcard generate
i_sd_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_sd,
io_resp => io_resp_sd );
SD_SSn <= '1';
SD_CLK <= '1';
SD_MOSI <= '1';
end generate;
LED_CLK <= 'Z';
LED_DATA <= 'Z';
r_spi_flash: if g_spi_flash generate
i_spi_flash: entity work.spi_peripheral_io
generic map (
g_fixed_rate => true,
g_init_rate => 1,
g_crc => false )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_flash,
io_resp => io_resp_flash,
SD_DETECTn => '0',
SD_WRPROTn => '1',
SPI_SSn => FLASH_CSn,
SPI_CLK => FLASH_SCK,
SPI_MOSI => FLASH_MOSI,
SPI_MISO => FLASH_MISO );
end generate;
r_no_spi_flash: if not g_spi_flash generate
i_flash_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_flash,
io_resp => io_resp_flash );
end generate;
r_rtc: if g_rtc_chip generate
signal spi_ss_n : std_logic;
begin
i_spi_rtc: entity work.spi_peripheral_io
generic map (
g_fixed_rate => true,
g_init_rate => 31,
g_crc => false )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_rtc,
io_resp => io_resp_rtc,
SD_DETECTn => '0',
SD_WRPROTn => '1',
SPI_SSn => spi_ss_n,
SPI_CLK => RTC_SCK,
SPI_MOSI => RTC_MOSI,
SPI_MISO => RTC_MISO );
RTC_CS <= not spi_ss_n;
end generate;
r_no_rtc: if not g_rtc_chip generate
i_rtc_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_rtc,
io_resp => io_resp_rtc );
end generate;
r_rtc_timer: if g_rtc_timer generate
i_rtc_timer: entity work.real_time_clock
generic map (
g_freq => g_clock_freq )
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_rtc_tmr,
resp => io_resp_rtc_tmr );
end generate;
r_no_rtc_timer: if not g_rtc_chip generate
i_rtc_timer_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_rtc_tmr,
io_resp => io_resp_rtc_tmr );
end generate;
r_gcr_codec: if g_hardware_gcr generate
i_gcr_codec: entity work.gcr_codec
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_gcr_dec,
resp => io_resp_gcr_dec );
end generate;
r_iec: if g_hardware_iec generate
i_iec: entity work.iec_processor_io
port map (
clock => sys_clock,
reset => sys_reset,
tick => tick_1MHz,
srq_i => srq_i,
srq_o => hw_srq_o,
atn_i => atn_i,
atn_o => hw_atn_o,
clk_i => clk_i,
clk_o => hw_clk_o,
data_i => data_i,
data_o => hw_data_o,
irq => sys_irq_iec, -- TODO: is not connected anywhere
req => io_req_iec,
resp => io_resp_iec );
end generate;
r_c2n: if g_c2n_streamer generate
i_c2n: entity work.c2n_playback_io -- tap -> signals
generic map (
g_clock_freq => g_clock_freq )
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_c2n,
resp => io_resp_c2n,
c64_stopped => c64_stopped,
c2n_sense_in => c2n_sense_in,
c2n_motor_in => c2n_motor_in,
c2n_sense_out => c2n_play_sense_out,
c2n_motor_out => c2n_play_motor_out,
c2n_out_en_r => c2n_read_en_i,
c2n_out_en_w => c2n_write_en,
c2n_out_r => c2n_read_out_i,
c2n_out_w => c2n_write_out );
end generate;
c2n_read_out <= c2n_read_out_i;
c2n_read_en <= c2n_read_en_i;
r_c2n_rec: if g_c2n_recorder generate -- signals => tap
i_c2n: entity work.c2n_record
port map (
clock => sys_clock,
reset => sys_reset,
irq => sys_irq_tape,
req => io_req_c2n_rec,
resp => io_resp_c2n_rec,
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
c2n_sense => c2n_sense_in,
c2n_motor_in => c2n_motor_in,
c2n_write => c2n_write_in,
c2n_read => c2n_read_in,
pull_sense => c2n_rec_sense_out,
c2n_motor_out => c2n_rec_motor_out );
end generate;
c2n_sense_out <= c2n_play_sense_out or c2n_rec_sense_out;
c2n_motor_out <= c2n_play_motor_out or c2n_rec_motor_out;
r_icap: if g_icap generate
i_icap: entity work.icap
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_icap,
io_resp => io_resp_icap );
end generate;
r_overlay: if g_video_overlay generate
i_overlay: entity work.char_generator_peripheral
generic map (
g_screen_size => 11,
g_color_ram => true )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_big_io, -- to be split later
io_resp => io_resp_big_io,
keyb_col => keyb_col,
keyb_row => keyb_row,
overlay_on => overlay_on,
pix_clock => vid_clock,
pix_reset => vid_reset,
h_count => vid_h_count,
v_count => vid_v_count,
pixel_active => vid_active,
pixel_opaque => vid_opaque,
pixel_data => vid_data );
end generate;
i_mem_arb: entity work.mem_bus_arbiter_pri_32
generic map (
g_ports => 7,
g_registered => false )
port map (
clock => sys_clock,
reset => sys_reset,
reqs(0) => mem_req_32_cart,
reqs(1) => mem_req_32_1541,
reqs(2) => mem_req_32_1541_2,
reqs(3) => mem_req_32_rmii,
reqs(4) => mem_req_32_usb,
reqs(5) => mem_req_32_cpu,
reqs(6) => ext_mem_req,
resps(0) => mem_resp_32_cart,
resps(1) => mem_resp_32_1541,
resps(2) => mem_resp_32_1541_2,
resps(3) => mem_resp_32_rmii,
resps(4) => mem_resp_32_usb,
resps(5) => mem_resp_32_cpu,
resps(6) => ext_mem_resp,
req => mem_req,
resp => mem_resp );
i_aud_select: entity work.audio_select
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_aud_sel,
resp => io_resp_aud_sel,
select_left => audio_select_left,
select_right => audio_select_right );
-- generate raw samples for audio
audio_tape_read <= to_signed(-100000, 19) when cas_read_c = '0' else to_signed(100000, 19);
audio_tape_write <= to_signed(-100000, 19) when cas_write_c = '0' else to_signed(100000, 19);
-- direct outputs for mixing in U64
aud_drive1 <= drive_sample_1(11 downto 0) & "000000";
aud_drive2 <= drive_sample_2(11 downto 0) & "000000";
aud_tape_r <= audio_tape_read(18 downto 1);
aud_tape_w <= audio_tape_write(18 downto 1);
aud_samp_l <= samp_left;
aud_samp_r <= samp_right;
aud_sid_1 <= sid_left;
aud_sid_2 <= sid_right;
process(sys_clock)
begin
if rising_edge(sys_clock) then
cas_read_c <= (c2n_read_in and not c2n_read_en_i) or (c2n_read_out_i and c2n_read_en_i);
cas_write_c <= c2n_write_in;
audio_left <= (others => '0');
audio_right <= (others => '0');
case audio_select_left is
when X"0" =>
audio_left(18 downto 7) <= drive_sample_1(11 downto 0);
when X"1" =>
audio_left(18 downto 7) <= drive_sample_2(11 downto 0);
when X"2" =>
audio_left <= audio_tape_read;
when X"3" =>
audio_left <= audio_tape_write;
when X"4" =>
audio_left <= sid_left & '0';
when X"5" =>
audio_left <= sid_right & '0';
when X"6" =>
audio_left <= samp_left & '0';
when X"7" =>
audio_left <= samp_right & '0';
when others =>
null;
end case;
case audio_select_right is
when X"0" =>
audio_right(18 downto 7) <= drive_sample_1(11 downto 0);
when X"1" =>
audio_right(18 downto 7) <= drive_sample_2(11 downto 0);
when X"2" =>
audio_right <= audio_tape_read;
when X"3" =>
audio_right <= audio_tape_write;
when X"4" =>
audio_right <= sid_left & '0';
when X"5" =>
audio_right <= sid_right & '0';
when X"6" =>
audio_right <= samp_left & '0';
when X"7" =>
audio_right <= samp_right & '0';
when others =>
null;
end case;
end if;
end process;
iec_atn_o <= '0' when atn_o='0' or atn_o_2='0' or hw_atn_o='0' else '1';
iec_clock_o <= '0' when clk_o='0' or clk_o_2='0' or hw_clk_o='0' else '1';
iec_data_o <= '0' when data_o='0' or data_o_2='0' or hw_data_o='0' else '1';
iec_srq_o <= '0' when srq_o='0' or srq_o_2='0' or hw_srq_o='0' else '1';
MOTOR_LEDn <= motor_led_n;
DISK_ACTn <= disk_led_n;
CART_LEDn <= cart_led_n;
SDACT_LEDn <= (dirty_led_1_n and dirty_led_2_n and not (sd_act_stretched or busy_led));
filt1: entity work.spike_filter generic map (10) port map(sys_clock, iec_atn_i, atn_i);
filt2: entity work.spike_filter generic map (10) port map(sys_clock, iec_clock_i, clk_i);
filt3: entity work.spike_filter generic map (10) port map(sys_clock, iec_data_i, data_i);
filt4: entity work.spike_filter generic map (10) port map(sys_clock, iec_srq_i, srq_i);
filt5: entity work.spike_filter port map(sys_clock, irqn_i, c64_irq_n);
filt6: entity work.spike_filter port map(sys_clock, rstn_i, c64_reset_in_n );
c64_irq <= not c64_irq_n;
-- dummy
SD_DATA <= "ZZ";
i_debug_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_debug,
io_resp => io_resp_debug );
r_rmii: if g_rmii generate
begin
i_rmii: entity work.ethernet_interface
generic map (
g_mem_tag => c_tag_rmii
)
port map(
sys_clock => sys_clock,
sys_reset => sys_reset,
io_req => io_req_rmii,
io_resp => io_resp_rmii,
io_irq_tx => sys_irq_eth_tx,
io_irq_rx => sys_irq_eth_rx,
mem_req => mem_req_32_rmii,
mem_resp => mem_resp_32_rmii,
eth_clock => eth_clock,
eth_reset => eth_reset,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready );
end generate;
end logic;
| gpl-3.0 | f27275f0b9e6e45b6e56beb5817dafe6 | 0.453083 | 3.207733 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/itu/vhdl_source/itu.vhd | 1 | 11,982 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.itu_pkg.all;
entity itu is
generic (
g_version : unsigned(7 downto 0) := X"FE";
g_uart : boolean := true;
g_uart_rx : boolean := true;
g_edge_init : std_logic_vector(7 downto 0) := "00000001";
g_capabilities : std_logic_vector(31 downto 0) := X"5555AAAA";
g_edge_write : boolean := true;
g_baudrate : integer := 115_200 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
irq_out : out std_logic;
tick_4MHz : in std_logic;
tick_1us : in std_logic;
tick_1ms : in std_logic;
buttons : in std_logic_vector(2 downto 0);
irq_timer_tick : in std_logic := '0';
irq_in : in std_logic_vector(7 downto 2);
irq_flags : out std_logic_vector(7 downto 0);
irq_high : in std_logic_vector(7 downto 0) := X"00";
busy_led : out std_logic;
misc_io : out std_logic_vector(7 downto 0);
uart_txd : out std_logic;
uart_rxd : in std_logic := '1';
uart_rts : out std_logic;
uart_cts : in std_logic := '1' );
end itu;
architecture gideon of itu is
constant c_timer_div : integer := 5;
constant c_baud_div : integer := (4_000_000 + g_baudrate / 2) / g_baudrate;
signal imask : std_logic_vector(7 downto 0);
signal iedge : std_logic_vector(7 downto 0) := g_edge_init;
signal timer : unsigned(7 downto 0);
signal timer_tick : std_logic;
signal timer_div : integer range 0 to c_timer_div - 1;
signal imask_high : std_logic_vector(7 downto 0);
signal irq_timer_val : unsigned(15 downto 0);
signal irq_timer_cnt : unsigned(23 downto 0);
signal irq_timer_en : std_logic;
signal irq_timer_select : std_logic;
signal irq_en : std_logic;
signal irq_c : std_logic_vector(7 downto 0);
signal irq_d : std_logic_vector(7 downto 0);
signal irq_edge_flag : std_logic_vector(7 downto 0);
signal irq_active : std_logic_vector(7 downto 0);
signal uart_irq : std_logic;
signal io_req_it : t_io_req;
signal io_resp_it : t_io_resp;
signal io_req_uart : t_io_req;
signal io_resp_uart : t_io_resp;
signal io_req_ms : t_io_req;
signal io_resp_ms : t_io_resp;
signal ms_timer : unsigned(15 downto 0) := (others => '0');
signal usb_busy : std_logic;
signal sd_busy : std_logic;
begin
process(clock)
variable new_irq_edge_flag : std_logic_vector(irq_edge_flag'range);
begin
if rising_edge(clock) then
timer_tick <= '0';
if tick_1us = '1' then
if timer_div = 0 then
timer_div <= c_timer_div - 1;
timer_tick <= '1';
else
timer_div <= timer_div - 1;
end if;
end if;
if timer_tick='1' then
if timer /= X"00" then
timer <= timer - 1;
end if;
end if;
if tick_1ms = '1' then
ms_timer <= ms_timer + 1;
end if;
irq_c(7 downto 2) <= irq_in(7 downto 2);
irq_c(1) <= uart_irq;
irq_c(0) <= '0';
if irq_timer_en='1' then
if irq_timer_cnt = 0 then
irq_c(0) <= '1';
if irq_timer_select='1' then
irq_timer_cnt <= X"00" & irq_timer_val;
else
irq_timer_cnt <= irq_timer_val & X"FF";
end if;
elsif irq_timer_select='0' or irq_timer_tick='1' then
irq_timer_cnt <= irq_timer_cnt - 1;
end if;
end if;
irq_d <= irq_c;
io_resp_it <= c_io_resp_init;
new_irq_edge_flag := irq_edge_flag;
if io_req_it.write='1' then
io_resp_it.ack <= '1';
case io_req_it.address(3 downto 0) is
when c_itu_irq_global =>
irq_en <= io_req_it.data(0);
when c_itu_irq_enable =>
imask <= imask or io_req_it.data;
when c_itu_irq_disable =>
imask <= imask and not io_req_it.data;
when c_itu_irq_edge =>
if g_edge_write then
iedge <= io_req_it.data;
end if;
when c_itu_irq_clear =>
new_irq_edge_flag := new_irq_edge_flag and not io_req_it.data;
when c_itu_timer =>
timer <= unsigned(io_req_it.data);
when c_itu_irq_timer_en =>
irq_timer_en <= io_req_it.data(0);
irq_timer_select <= io_req_it.data(1);
if irq_timer_en='0' then
irq_timer_cnt <= irq_timer_val & X"FF";
end if;
when c_itu_irq_timer_lo =>
irq_timer_val(7 downto 0) <= unsigned(io_req_it.data);
when c_itu_irq_timer_hi =>
irq_timer_val(15 downto 8) <= unsigned(io_req_it.data);
when others =>
null;
end case;
elsif io_req_it.read='1' then
io_resp_it.ack <= '1';
case io_req_it.address(3 downto 0) is
when c_itu_irq_global =>
io_resp_it.data(0) <= irq_en;
when c_itu_irq_enable =>
io_resp_it.data <= imask;
when c_itu_irq_edge =>
io_resp_it.data <= iedge;
when c_itu_irq_active =>
io_resp_it.data <= irq_active;
when c_itu_timer =>
io_resp_it.data <= std_logic_vector(timer);
when c_itu_irq_timer_en =>
io_resp_it.data(0) <= irq_timer_en;
io_resp_it.data(1) <= irq_timer_select;
when c_itu_irq_timer_lo =>
io_resp_it.data <= std_logic_vector(irq_timer_cnt(7 downto 0));
when c_itu_irq_timer_hi =>
io_resp_it.data <= std_logic_vector(irq_timer_cnt(15 downto 8));
when c_itu_fpga_version =>
io_resp_it.data <= std_logic_vector(g_version);
when c_itu_capabilities0 =>
io_resp_it.data <= g_capabilities(31 downto 24);
when c_itu_capabilities1 =>
io_resp_it.data <= g_capabilities(23 downto 16);
when c_itu_capabilities2 =>
io_resp_it.data <= g_capabilities(15 downto 8);
when c_itu_capabilities3 =>
io_resp_it.data <= g_capabilities( 7 downto 0);
when c_itu_buttons =>
io_resp_it.data <= buttons & "00000";
when others =>
null;
end case;
end if;
io_resp_ms <= c_io_resp_init;
if io_req_ms.write='1' then
io_resp_ms.ack <= '1';
case io_req_ms.address(3 downto 0) is
when c_itu_usb_busy =>
usb_busy <= io_req_ms.data(0);
when c_itu_sd_busy =>
sd_busy <= io_req_ms.data(0);
when c_itu_misc_io =>
misc_io <= io_req_ms.data;
when c_itu_irq_en_high =>
imask_high <= io_req_ms.data;
when others =>
null;
end case;
elsif io_req_ms.read='1' then
io_resp_ms.ack <= '1';
case io_req_ms.address(3 downto 0) is
when c_itu_ms_timer_lo =>
io_resp_ms.data <= std_logic_vector(ms_timer(7 downto 0));
when c_itu_ms_timer_hi =>
io_resp_ms.data <= std_logic_vector(ms_timer(15 downto 8));
when c_itu_irq_act_high =>
io_resp_ms.data <= irq_high and imask_high;
when c_itu_irq_en_high =>
io_resp_ms.data <= imask_high;
when others =>
null;
end case;
end if;
for i in 0 to 7 loop
if iedge(i)='1' then
if irq_c(i)='1' and irq_d(i)='0' then
new_irq_edge_flag(i) := '1';
end if;
end if;
end loop;
irq_edge_flag <= new_irq_edge_flag;
irq_out <= '0';
if irq_en = '1' then
if (irq_active and imask) /= X"00" then
irq_out <= '1';
end if;
if (irq_high and imask_high) /= X"00" then
irq_out <= '1';
end if;
end if;
if reset='1' then
irq_en <= '1';
imask <= (others => '0');
imask_high <= (others => '0');
iedge <= g_edge_init;
irq_edge_flag <= (others => '0');
timer <= (others => '0');
irq_timer_en <= '0';
irq_timer_select <= '0';
irq_timer_val <= X"8000";
irq_timer_cnt <= (others => '0');
ms_timer <= (others => '0');
usb_busy <= '0';
sd_busy <= '0';
misc_io <= (others => '0');
end if;
end if;
end process;
irq_active <= irq_edge_flag or (irq_c and not iedge);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 4,
g_range_hi => 5,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_it,
reqs(1) => io_req_uart,
reqs(2) => io_req_ms,
resps(0) => io_resp_it,
resps(1) => io_resp_uart,
resps(2) => io_resp_ms );
r_uart: if g_uart generate
uart: entity work.uart_peripheral_io
generic map (
g_impl_rx => g_uart_rx,
g_divisor => c_baud_div )
port map (
clock => clock,
reset => reset,
tick => tick_4MHz,
io_req => io_req_uart,
io_resp => io_resp_uart,
irq => uart_irq,
rts => uart_rts,
cts => uart_cts,
txd => uart_txd,
rxd => uart_rxd );
end generate;
no_uart: if not g_uart generate
process(clock)
begin
if rising_edge(clock) then
io_resp_uart <= c_io_resp_init;
io_resp_uart.ack <= io_req_uart.read or io_req_uart.write;
end if;
end process;
end generate;
busy_led <= usb_busy or sd_busy;
irq_flags <= irq_active;
end architecture;
| gpl-3.0 | a5709495b8fc9ab5f764d8bd3d923e0d | 0.419045 | 3.785782 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/execute.vhd | 1 | 12,072 | ----------------------------------------------------------------------------------------------
--
-- Input file : execute.vhd
-- Design name : execute
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The Execution Unit performs all arithmetic operations and makes
-- the branch decision. Furthermore the forwarding logic is located
-- here. Everything is computed within a single clock-cycle
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity execute is generic
(
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port
(
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end execute;
architecture arch of execute is
type execute_reg_type is record
carry : std_logic;
break_in_progress : std_logic;
flush_ex : std_logic;
end record;
signal r, rin : execute_out_type;
signal reg, regin : execute_reg_type;
begin
exec_o <= r;
execute_comb: process(exec_i, r, reg)
variable v : execute_out_type;
variable v_reg : execute_reg_type;
variable alu_src_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable alu_src_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable carry : std_logic;
variable result : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable result_add : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable zero : std_logic;
variable equal : std_logic;
variable dat_a, dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable sel_dat_a, sel_dat_b, sel_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable special_reg : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v_reg := reg;
sel_dat_a := select_register_data(exec_i.dat_a, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_a));
sel_dat_b := select_register_data(exec_i.dat_b, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_b));
sel_dat_d := select_register_data(exec_i.dat_d, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.ctrl_wrb.reg_d));
if reg.flush_ex = '1' then
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
v.ctrl_wrb.reg_d := (others => '0');
else
v.ctrl_mem := exec_i.ctrl_mem;
v.ctrl_wrb := exec_i.ctrl_wrb;
if exec_i.ctrl_wrb.reg_d = "00000" then
v.ctrl_wrb.reg_write := '0';
end if;
end if;
if exec_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(exec_i.mem_result, exec_i.ctrl_mem_wrb.transfer_size, exec_i.alu_result(1 downto 0));
else
mem_result := exec_i.alu_result;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_a) = '1' then
-- Forward Execution Result to REG a
dat_a := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_a) = '1' then
-- Forward Memory Result to REG a
dat_a := mem_result;
else
-- DEFAULT: value of REG a
dat_a := sel_dat_a;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_b) = '1' then
-- Forward (latched) Execution Result to REG b
dat_b := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_b) = '1' then
-- Forward Memory Result to REG b
dat_b := mem_result;
else
-- DEFAULT: value of REG b
dat_b := sel_dat_b;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Execution Result to REG d
v.dat_d := align_mem_store(r.alu_result, exec_i.ctrl_mem.transfer_size);
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Memory Result to REG d
v.dat_d := align_mem_store(mem_result, exec_i.ctrl_mem.transfer_size);
else
-- DEFAULT: value of REG d
v.dat_d := align_mem_store(sel_dat_d, exec_i.ctrl_mem.transfer_size);
end if;
-- In case more than just one special register needs to be supported, a multiplexer can be made here. For now, just MSR.
special_reg := (31 => reg.carry,
3 => reg.break_in_progress,
2 => reg.carry,
1 => r.interrupt_enable,
others => '0' );
-- Set the first operand of the ALU
case exec_i.ctrl_ex.alu_src_a is
when ALU_SRC_PC => alu_src_a := sign_extend(exec_i.program_counter, '0', 32);
when ALU_SRC_NOT_REGA => alu_src_a := not dat_a;
when ALU_SRC_SPR => alu_src_a := special_reg;
when others => alu_src_a := dat_a;
end case;
-- Set the second operand of the ALU
case exec_i.ctrl_ex.alu_src_b is
when ALU_SRC_IMM => alu_src_b := exec_i.imm;
when ALU_SRC_NOT_IMM => alu_src_b := not exec_i.imm;
when ALU_SRC_NOT_REGB => alu_src_b := not dat_b;
when others => alu_src_b := dat_b;
end case;
-- Determine value of carry in
case exec_i.ctrl_ex.carry is
when CARRY_ALU => carry := reg.carry;
when CARRY_ONE => carry := '1';
when CARRY_ARITH => carry := alu_src_a(CFG_DMEM_WIDTH - 1);
when others => carry := '0';
end case;
result_add := add(alu_src_a, alu_src_b, carry);
equal := compare(dat_a, dat_b);
case exec_i.ctrl_ex.alu_op is
when ALU_ADD => result := result_add;
when ALU_OR => result := '0' & (alu_src_a or alu_src_b);
when ALU_AND => result := '0' & (alu_src_a and alu_src_b);
when ALU_XOR => result := '0' & (alu_src_a xor alu_src_b);
when ALU_SHIFT => result := alu_src_a(0) & carry & alu_src_a(CFG_DMEM_WIDTH - 1 downto 1);
when ALU_SEXT8 => result := '0' & sign_extend(alu_src_a(7 downto 0), alu_src_a(7), 32);
when ALU_SEXT16 => result := '0' & sign_extend(alu_src_a(15 downto 0), alu_src_a(15), 32);
when ALU_PEQ => result := X"00000000" & (equal xor exec_i.ctrl_ex.operation(0));
when ALU_MUL =>
if G_USE_HW_MUL = true then
result := '0' & multiply(alu_src_a, alu_src_b);
else
result := (others => '0');
end if;
when ALU_BS =>
if G_USE_BARREL = true then
result := '0' & shift(alu_src_a, alu_src_b(4 downto 0), exec_i.imm(10), exec_i.imm(9));
else
result := (others => '0');
end if;
when others =>
result := (others => '0');
report "Invalid ALU operation" severity FAILURE;
end case;
if reg.flush_ex = '0' then
-- Set carry register
if exec_i.ctrl_ex.carry_keep = CARRY_KEEP then
v_reg.carry := reg.carry;
else
v_reg.carry := result(CFG_DMEM_WIDTH);
end if;
-- MSR operations
case exec_i.ctrl_ex.msr_op is
when MSR_SET_I =>
v.interrupt_enable := '1';
when MSR_CLR_I =>
v.interrupt_enable := '0';
when LOAD_MSR =>
v_reg.break_in_progress := dat_a(3);
v_reg.carry := dat_a(2);
v.interrupt_enable := dat_a(1);
when MSR_SET =>
v_reg.break_in_progress := exec_i.imm(3) or reg.break_in_progress;
v_reg.carry := exec_i.imm(2) or reg.carry;
v.interrupt_enable := exec_i.imm(1) or r.interrupt_enable;
when MSR_CLR =>
v_reg.break_in_progress := not exec_i.imm(3) and reg.break_in_progress;
v_reg.carry := not exec_i.imm(2) and reg.carry;
v.interrupt_enable := not exec_i.imm(1) and r.interrupt_enable;
when others =>
null;
end case;
end if;
zero := is_zero(dat_a);
-- Overwrite branch condition
if reg.flush_ex = '1' then
v.branch := '0';
else
-- Determine branch condition
case exec_i.ctrl_ex.branch_cond is
when BNC => v.branch := '1';
when BEQ => v.branch := zero;
when BNE => v.branch := not zero;
when BLT => v.branch := dat_a(CFG_DMEM_WIDTH - 1);
when BLE => v.branch := dat_a(CFG_DMEM_WIDTH - 1) or zero;
when BGT => v.branch := not (dat_a(CFG_DMEM_WIDTH - 1) or zero);
when BGE => v.branch := not dat_a(CFG_DMEM_WIDTH - 1);
when others => v.branch := '0';
end case;
end if;
v.alu_result := result(CFG_DMEM_WIDTH - 1 downto 0);
-- Handle CMPU and CMP
if exec_i.ctrl_ex.compare_op = '1' then
if ( exec_i.ctrl_ex.operation = "11" ) then
v.alu_result(CFG_DMEM_WIDTH - 1) := not result_add(CFG_DMEM_WIDTH); -- unsigned = bit 32 of result
elsif ( exec_i.ctrl_ex.operation = "01" ) then
v.alu_result(CFG_DMEM_WIDTH - 1) := (result_add(CFG_DMEM_WIDTH) xor alu_src_a(CFG_DMEM_WIDTH-1) xor alu_src_b(CFG_DMEM_WIDTH-1)); -- signed
end if;
end if;
v.program_counter := exec_i.program_counter;
-- Determine flush signals
v.flush_id := v.branch;
v_reg.flush_ex := v.branch and not exec_i.ctrl_ex.delay;
rin <= v;
regin <= v_reg;
end process;
execute_seq: process(clk_i)
procedure proc_execute_reset is
begin
r.alu_result <= (others => '0');
r.dat_d <= (others => '0');
r.branch <= '0';
r.program_counter <= (others => '0');
r.flush_id <= '0';
r.interrupt_enable <= '0';
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.mem_read <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
reg.carry <= '0';
reg.break_in_progress <= '0';
reg.flush_ex <= '0';
end procedure proc_execute_reset;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_execute_reset;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 4b5754f79e4bbef5103dcc4c570a4d35 | 0.498343 | 3.495078 | false | false | false | false |
chiggs/nvc | test/regress/cond1.vhd | 5 | 685 | entity cond1 is
end entity;
architecture test of cond1 is
signal x : integer := 5;
begin
process is
variable y : integer;
begin
y := 5;
if x = y then
report "x = y";
x <= 4;
end if;
if x = y + 1 then
report "x = y + 1" severity failure;
else
null;
report "x /= y + 1";
end if;
if x = y - 1 then
report "x = y - 1" severity failure;
elsif x = y then
report "x = y still";
else
report "x /= y - 1 and x /= y" severity failure;
end if;
wait;
end process;
end architecture;
| gpl-3.0 | 47a5762dfe66a0fbaddb42046729e163 | 0.439416 | 4.005848 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/packages/vhdl_source/file_io_pkg.vhd | 1 | 9,546 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: File IO routines
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package file_io_pkg is
subtype t_byte is std_logic_vector(7 downto 0);
function nibbletohex(nibble : std_logic_vector(3 downto 0)) return character;
function hextonibble(c : character) return std_logic_vector;
function ishexchar(c : character) return boolean;
procedure vectohex(vec : std_logic_vector; str : out string);
function vectohex(vec : std_logic_vector; len : integer) return string;
procedure getcharfromfile(file myfile : text; l : inout line; stop : out boolean; hex : out character);
procedure getbytefromfile(file myfile : text; l : inout line; fileend : out boolean; dat : out t_byte);
type t_binary_file is file of integer;
type t_binary_file_handle is record
offset : integer range 0 to 4;
longvec : std_logic_vector(31 downto 0);
end record;
constant emptysp : string := " ";
procedure initrecord(rec : inout t_binary_file_handle);
procedure readbyte(file f : t_binary_file; b : out t_byte; rec : inout t_binary_file_handle);
procedure writebyte(file f : t_binary_file; b : in t_byte; rec : inout t_binary_file_handle);
procedure purge(file f : t_binary_file; rec : inout t_binary_file_handle);
procedure onoffchar(l : inout line; ena : std_logic; ch : character);
procedure onoffchar(l : inout line; ena : std_logic; ch, alt : character);
procedure hexout(l : inout line; ena : std_logic; vec : std_logic_vector; len : integer);
procedure write_s(variable li : inout line; s : string);
end;
package body file_io_pkg is
function nibbletohex(nibble : std_logic_vector(3 downto 0)) return character is
variable r : character := '?';
begin
case nibble is
when "0000" => r := '0';
when "0001" => r := '1';
when "0010" => r := '2';
when "0011" => r := '3';
when "0100" => r := '4';
when "0101" => r := '5';
when "0110" => r := '6';
when "0111" => r := '7';
when "1000" => r := '8';
when "1001" => r := '9';
when "1010" => r := 'a';
when "1011" => r := 'b';
when "1100" => r := 'c';
when "1101" => r := 'd';
when "1110" => r := 'e';
when "1111" => r := 'f';
when others => r := 'x';
end case;
return r;
end nibbletohex;
function hextonibble(c : character) return std_logic_vector is
variable z : std_logic_vector(3 downto 0);
begin
case c is
when '0' => z := "0000";
when '1' => z := "0001";
when '2' => z := "0010";
when '3' => z := "0011";
when '4' => z := "0100";
when '5' => z := "0101";
when '6' => z := "0110";
when '7' => z := "0111";
when '8' => z := "1000";
when '9' => z := "1001";
when 'a' => z := "1010";
when 'b' => z := "1011";
when 'c' => z := "1100";
when 'd' => z := "1101";
when 'e' => z := "1110";
when 'f' => z := "1111";
when 'A' => z := "1010";
when 'B' => z := "1011";
when 'C' => z := "1100";
when 'D' => z := "1101";
when 'E' => z := "1110";
when 'F' => z := "1111";
when others => z := "XXXX";
end case;
return z;
end hextonibble;
function ishexchar(c : character) return boolean is
begin
case c is
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7' => return true;
when '8'|'9'|'a'|'b'|'c'|'d'|'e'|'f' => return true;
when 'A'|'B'|'C'|'D'|'E'|'F' => return true;
when others => return false;
end case;
return false;
end ishexchar;
procedure vectohex(vec : std_logic_vector; str : out string) is
variable tempvec : std_logic_vector(str'length * 4 downto 1) := (others => '0');
variable j : integer;
variable myvec : std_logic_vector(vec'range);
variable len, mylow, myhigh : integer;
begin
myvec := vec;
len := str'length;
mylow := vec'low;
myhigh := vec'high;
if vec'length < tempvec'length then
tempvec(vec'length downto 1) := vec;
else
tempvec := vec(vec'low + tempvec'length - 1 downto vec'low);
end if;
for i in str'range loop
j := (str'right - i) * 4;
str(i) := nibbletohex(tempvec(j+4 downto j+1));
end loop;
end vectohex;
function vectohex(vec : std_logic_vector; len : integer) return string is
variable str : string(1 to len);
begin
vectohex(vec, str);
return str;
end vectohex;
procedure getcharfromfile(file myfile : text; l : inout line; stop : out boolean; hex : out character) is
variable good : boolean := false;
begin
while not(good) loop
read(l, hex, good);
if not(good) then
if endfile(myfile) then
stop := true;
hex := '1';
return;
end if;
readline(myfile, l);
end if;
end loop;
end getcharfromfile;
procedure getbytefromfile(file myfile : text; l : inout line; fileend : out boolean; dat : out t_byte) is
variable hex : character;
variable d : t_byte;
variable stop : boolean := false;
begin
d := x"00";
l1 : loop
getcharfromfile(myfile, l, stop, hex);
if stop or ishexchar(hex) then
exit l1;
end if;
end loop l1;
d(3 downto 0) := hextonibble(hex);
-- see if we can read another good hex char
getcharfromfile(myfile, l, stop, hex);
if not(stop) and ishexchar(hex) then
d(7 downto 4) := d(3 downto 0);
d(3 downto 0) := hextonibble(hex);
end if;
fileend := stop;
dat := d;
end getbytefromfile;
procedure onoffchar(l : inout line; ena : std_logic; ch : character) is
begin
if ena = '1' then
write(l, ch);
else
write(l, ' ');
end if;
end onoffchar;
procedure onoffchar(l : inout line; ena : std_logic; ch, alt : character) is
begin
if ena = '1' then
write(l, ch);
else
write(l, alt);
end if;
end onoffchar;
procedure hexout(l : inout line; ena : std_logic; vec : std_logic_vector; len : integer) is
begin
if ena = '1' then
write(l, vectohex(vec, len));
else
write(l, emptysp(1 to len));
end if;
end hexout;
procedure initrecord(rec : inout t_binary_file_handle) is
begin
rec.offset := 0;
rec.longvec := (others => '0');
end procedure;
procedure readbyte(file f : t_binary_file; b : out t_byte; rec : inout t_binary_file_handle) is
variable i : integer;
begin
if rec.offset = 0 then
read(f, i);
rec.longvec := std_logic_vector(to_unsigned(i, 32));
end if;
b := rec.longvec(7 downto 0);
rec.longvec := "00000000" & rec.longvec(31 downto 8); -- lsb first
if rec.offset = 3 then
rec.offset := 0;
else
rec.offset := rec.offset + 1;
end if;
end procedure;
procedure writebyte(file f : t_binary_file; b : in t_byte; rec : inout t_binary_file_handle) is
variable i : integer;
begin
rec.longvec(31 downto 24) := b;
if rec.offset = 3 then
i := to_integer(unsigned(rec.longvec));
write(f, i);
rec.offset := 0;
else
rec.offset := rec.offset + 1;
rec.longvec := "00000000" & rec.longvec(31 downto 8); -- lsb first
end if;
end procedure;
procedure purge(file f : t_binary_file; rec : inout t_binary_file_handle) is
variable i : integer;
begin
if rec.offset /= 0 then
i := to_integer(unsigned(rec.longvec));
write(f, i);
end if;
end procedure;
procedure write_s(variable li : inout line; s : string) is
begin
write(li, s);
end write_s;
end;
| gpl-3.0 | 5e7e92d43e209844ccd0396c02a45704 | 0.468259 | 3.889976 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_source/dmem_splitter.vhd | 1 | 6,286 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: dmem_splitter
-- Date:2015-02-28
-- Author: Gideon
-- Description: This module takes the Wishbone alike memory bus and splits it
-- into a 32 bit DRAM bus and an 8-bit IO bus
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
library mblite;
use mblite.core_Pkg.all;
entity dmem_splitter is
generic (
g_tag : std_logic_vector(7 downto 0) := X"AE";
g_support_io : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
dmem_i : out dmem_in_type;
dmem_o : in dmem_out_type;
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
io_busy : out std_logic;
io_req : out t_io_req;
io_resp : in t_io_resp );
end entity;
architecture arch of dmem_splitter is
type t_state is (idle, mem_read, mem_write, io_access);
signal state : t_state;
signal mem_req_i : t_mem_req_32 := c_mem_req_32_init;
signal io_req_i : t_io_req;
type t_int4_array is array(natural range <>) of integer range 0 to 3;
-- 0 1 2 3 4 5 6 7 8 9 A B C D E F => 1,2,4,8 byte, 3,C word, F dword
constant c_remain : t_int4_array(0 to 15) := ( 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 3 );
signal remain : integer range 0 to 3;
begin
mem_req <= mem_req_i;
process(state, mem_resp)
begin
dmem_i.ena_i <= '0';
case state is
when idle =>
dmem_i.ena_i <= '1';
when mem_read | io_access =>
dmem_i.ena_i <= '0';
when mem_write =>
-- if mem_resp.rack = '1' then
-- dmem_i.ena_i <= '1';
-- end if;
when others =>
dmem_i.ena_i <= '0';
end case;
end process;
process(io_req_i, mem_req_i)
begin
io_req <= io_req_i;
-- Fill in the byte to write, based on the address
-- Note that mem-req stored the 32 bits data, so we can use it, dmem.o might have become invalid
case io_req_i.address(1 downto 0) is
when "00" =>
io_req.data <= mem_req_i.data(31 downto 24);
when "01" =>
io_req.data <= mem_req_i.data(23 downto 16);
when "10" =>
io_req.data <= mem_req_i.data(15 downto 08);
when "11" =>
io_req.data <= mem_req_i.data(07 downto 00);
when others =>
null;
end case;
end process;
process(clock)
begin
if rising_edge(clock) then
io_req_i.read <= '0';
io_req_i.write <= '0';
case state is
when idle =>
if dmem_o.ena_o = '1' then
dmem_i.dat_i <= (others => 'X');
mem_req_i.address <= unsigned(dmem_o.adr_o(mem_req_i.address'range));
mem_req_i.address(1 downto 0) <= "00";
mem_req_i.byte_en <= dmem_o.sel_o;
mem_req_i.data <= dmem_o.dat_o;
mem_req_i.read_writen <= not dmem_o.we_o;
mem_req_i.tag <= g_tag;
io_req_i.address <= unsigned(dmem_o.adr_o(19 downto 0));
remain <= c_remain(to_integer(unsigned(dmem_o.sel_o)));
if dmem_o.adr_o(26) = '0' or not g_support_io then
mem_req_i.request <= '1';
if dmem_o.we_o = '1' then
state <= mem_write;
else
state <= mem_read;
end if;
else -- I/O
if dmem_o.we_o = '1' then
io_req_i.write <= '1';
else
io_req_i.read <= '1';
end if;
state <= io_access;
end if;
end if;
when mem_read =>
if mem_resp.rack_tag = g_tag then
mem_req_i.request <= '0';
end if;
if mem_resp.dack_tag = g_tag then
dmem_i.dat_i <= mem_resp.data;
state <= idle;
end if;
when mem_write =>
if mem_resp.rack_tag = g_tag then
mem_req_i.request <= '0';
state <= idle;
end if;
when io_access =>
case io_req_i.address(1 downto 0) is
when "00" =>
dmem_i.dat_i(31 downto 24) <= io_resp.data;
when "01" =>
dmem_i.dat_i(23 downto 16) <= io_resp.data;
when "10" =>
dmem_i.dat_i(15 downto 8) <= io_resp.data;
when "11" =>
dmem_i.dat_i(7 downto 0) <= io_resp.data;
when others =>
null;
end case;
if io_resp.ack = '1' then
if remain = 0 then
state <= idle;
else
remain <= remain - 1;
io_req_i.address(1 downto 0) <= io_req_i.address(1 downto 0) + 1;
if mem_req_i.read_writen = '0' then
io_req_i.write <= '1';
else
io_req_i.read <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
mem_req_i.request <= '0';
end if;
end if;
end process;
io_busy <= '1' when state = io_access else '0';
end arch;
| gpl-3.0 | 9666527db60e7a3cdfd3be39377a3569 | 0.407095 | 3.764072 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd | 1 | 8,099 | -- cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.11.08:07:37
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 34;
FIFO_DEPTH : integer := 2;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 0;
USE_MEMORY_BLOCKS : integer := 0;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_data : in std_logic_vector(33 downto 0) := (others => '0'); -- in.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
out_data : out std_logic_vector(33 downto 0); -- out.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
almost_empty_data : out std_logic;
almost_full_data : out std_logic;
csr_address : in std_logic_vector(1 downto 0) := (others => '0');
csr_read : in std_logic := '0';
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic := '0';
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
in_channel : in std_logic := '0';
in_empty : in std_logic := '0';
in_endofpacket : in std_logic := '0';
in_error : in std_logic := '0';
in_startofpacket : in std_logic := '0';
out_channel : out std_logic;
out_empty : out std_logic;
out_endofpacket : out std_logic;
out_error : out std_logic;
out_startofpacket : out std_logic
);
end entity cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo;
architecture rtl of cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(33 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
begin
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => SYMBOLS_PER_BEAT,
BITS_PER_SYMBOL => BITS_PER_SYMBOL,
FIFO_DEPTH => FIFO_DEPTH,
CHANNEL_WIDTH => CHANNEL_WIDTH,
ERROR_WIDTH => ERROR_WIDTH,
USE_PACKETS => USE_PACKETS,
USE_FILL_LEVEL => USE_FILL_LEVEL,
EMPTY_LATENCY => EMPTY_LATENCY,
USE_MEMORY_BLOCKS => USE_MEMORY_BLOCKS,
USE_STORE_FORWARD => USE_STORE_FORWARD,
USE_ALMOST_FULL_IF => USE_ALMOST_FULL_IF,
USE_ALMOST_EMPTY_IF => USE_ALMOST_EMPTY_IF
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_data => in_data, -- in.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
out_data => out_data, -- out.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
end architecture rtl; -- of cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo
| apache-2.0 | bedcdd3019567f5524f994d985134156 | 0.428942 | 3.901252 | false | false | false | false |
nussbrot/AdvPT | wb_test/src/vhdl/wbs_test.vhd | 2 | 20,456 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2017 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project : glb_lib
-- File : wbs_test.vhd
-- Created : 18.05.2017
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--*
--* @short Wishbone register module
--* Auto-generated by 'export_wbs.tcl' based on '../../../../sxl/tpl/wb_reg_no_rst.tpl.vhd'
--*
--* Needed Libraries and Packages:
--* @li ieee.std_logic_1164 standard multi-value logic package
--* @li ieee.numeric_std
--*
--* @author rhallmen
--* @date 30.06.2016
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- 18.05.2017 rhallmen: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-------------------------------------------------------------------------------
ENTITY wbs_test IS
GENERIC (
g_addr_bits : INTEGER := 8);
PORT (
-- Wishbone interface
clk : IN STD_LOGIC;
i_wb_cyc : IN STD_LOGIC;
i_wb_stb : IN STD_LOGIC;
i_wb_we : IN STD_LOGIC;
i_wb_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wb_addr : IN STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
i_wb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_ack : OUT STD_LOGIC;
o_wb_rty : OUT STD_LOGIC;
o_wb_err : OUT STD_LOGIC;
-- Custom ports
o_rw_slice0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
o_rw_slice1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_rw_bit : OUT STD_LOGIC;
i_ro_slice0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
i_ro_slice1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
i_ro_bit : IN STD_LOGIC;
o_wo_slice0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
o_wo_slice1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_wo_bit : OUT STD_LOGIC;
o_tr_slice0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
o_tr_slice1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_tr_bit : OUT STD_LOGIC;
o_en_bit : OUT STD_LOGIC;
o_en_slice : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_no_rw_rw_bit : OUT STD_LOGIC;
o_no_rw_rw_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
i_no_rw_ro_bit : IN STD_LOGIC;
i_no_rw_ro_slice : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_rw_wo_bit : OUT STD_LOGIC;
o_no_rw_wo_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_rw_tr_bit : OUT STD_LOGIC;
o_no_rw_tr_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_notify_rw_trd : OUT STD_LOGIC;
o_notify_rw_twr : OUT STD_LOGIC;
o_no_ro_rw_bit : OUT STD_LOGIC;
o_no_ro_rw_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
i_no_ro_ro_bit : IN STD_LOGIC;
i_no_ro_ro_slice : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_ro_wo_bit : OUT STD_LOGIC;
o_no_ro_wo_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_ro_tr_bit : OUT STD_LOGIC;
o_no_ro_tr_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_notify_ro_trd : OUT STD_LOGIC;
o_no_wo_rw_bit : OUT STD_LOGIC;
o_no_wo_rw_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
i_no_wo_ro_bit : IN STD_LOGIC;
i_no_wo_ro_slice : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_wo_wo_bit : OUT STD_LOGIC;
o_no_wo_wo_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_wo_tr_bit : OUT STD_LOGIC;
o_no_wo_tr_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_notify_wo_twr : OUT STD_LOGIC;
o_const_bit0 : OUT STD_LOGIC;
o_const_bit1 : OUT STD_LOGIC;
o_const_slice0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_const_slice1 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END ENTITY wbs_test;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF wbs_test IS
-----------------------------------------------------------------------------
-- Procedures
-----------------------------------------------------------------------------
-- Write access to 32bit register
PROCEDURE set_reg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg : INOUT STD_LOGIC_VECTOR) IS
BEGIN
FOR i IN s_reg'RANGE LOOP
IF (i_wr_mask(i) = '1' AND i_wr_en(i/8) = '1') THEN
s_reg(i) <= i_wr_data(i);
END IF;
END LOOP;
END PROCEDURE set_reg;
-- Write access to single bit register.
-- Since the index is lost, we rely on the mask to set the correct value.
PROCEDURE set_reg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg : INOUT STD_LOGIC) IS
BEGIN
FOR i IN i_wr_mask'RANGE LOOP
IF (i_wr_mask(i) = '1' AND i_wr_en(i/8) = '1') THEN
s_reg <= i_wr_data(i);
END IF;
END LOOP;
END PROCEDURE set_reg;
-- Write access to single trigger signal
PROCEDURE set_trg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT c_wr_mask : IN NATURAL RANGE 0 TO 31;
SIGNAL s_flag : INOUT STD_LOGIC) IS
BEGIN
IF (i_wr_en(c_wr_mask/8) = '1' AND i_wr_data(c_wr_mask) = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_trg;
-- Write access to trigger signal vector
PROCEDURE set_trg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT c_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_flag : INOUT STD_LOGIC_VECTOR) IS
BEGIN
FOR i IN 0 TO 31 LOOP
IF (c_wr_mask(i) = '1') THEN
IF (i_wr_en(i/8) = '1' AND i_wr_data(i) = '1') THEN
s_flag(i) <= '1';
ELSE
s_flag(i) <= '0';
END IF;
END IF;
END LOOP;
END PROCEDURE set_trg;
-- Drive Trigger On Write signal
PROCEDURE set_twr (
i_wr_en : IN STD_LOGIC;
SIGNAL s_flag : OUT STD_LOGIC) IS
BEGIN -- PROCEDURE set_twr
IF (i_wr_en = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_twr;
-- Drive Trigger On Read signal
PROCEDURE set_trd (
i_rd_en : IN STD_LOGIC;
SIGNAL s_flag : OUT STD_LOGIC) IS
BEGIN -- PROCEDURE set_trd
IF (i_rd_en = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_trd;
-- helper to cast integer to slv
FUNCTION f_reset_cast(number : NATURAL; len : POSITIVE)
RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN STD_LOGIC_VECTOR(to_unsigned(number, len));
END FUNCTION f_reset_cast;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
CONSTANT c_addr_read_write : INTEGER := 16#0000#;
CONSTANT c_addr_read_only : INTEGER := 16#0004#;
CONSTANT c_addr_write_only : INTEGER := 16#0008#;
CONSTANT c_addr_trigger : INTEGER := 16#000C#;
CONSTANT c_addr_enum : INTEGER := 16#0010#;
CONSTANT c_addr_notify_rw : INTEGER := 16#0014#;
CONSTANT c_addr_notify_ro : INTEGER := 16#0018#;
CONSTANT c_addr_notify_wo : INTEGER := 16#001C#;
CONSTANT c_addr_const : INTEGER := 16#0020#;
CONSTANT c_has_read_notifies : BOOLEAN := TRUE;
-----------------------------------------------------------------------------
-- WB interface signals
-----------------------------------------------------------------------------
SIGNAL s_wb_ack : STD_LOGIC;
SIGNAL s_wb_err : STD_LOGIC;
SIGNAL s_wb_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_data : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_int_we : STD_LOGIC_VECTOR(i_wb_sel'RANGE);
SIGNAL s_int_trd : STD_LOGIC;
SIGNAL s_int_twr : STD_LOGIC;
SIGNAL s_int_addr_valid : STD_LOGIC;
SIGNAL s_int_data_rb : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_wb_data : STD_LOGIC_VECTOR(o_wb_data'RANGE);
-----------------------------------------------------------------------------
-- Custom registers
-----------------------------------------------------------------------------
SIGNAL s_reg_read_write : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_read_only : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_write_only : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_trigger : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_enum : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"80002000";
SIGNAL s_reg_notify_rw : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
SIGNAL s_reg_notify_ro : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
SIGNAL s_reg_notify_wo : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
SIGNAL s_reg_const : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"71002280";
SIGNAL s_wo_wo_slice0 : STD_LOGIC_VECTOR(31 DOWNTO 16) := (OTHERS => '0');
SIGNAL s_wo_wo_slice1 : STD_LOGIC_VECTOR(15 DOWNTO 8) := (OTHERS => '0');
SIGNAL s_wo_wo_bit : STD_LOGIC := '0';
SIGNAL s_trg_tr_slice0 : STD_LOGIC_VECTOR(31 DOWNTO 16) := (OTHERS => '0');
SIGNAL s_trg_tr_slice1 : STD_LOGIC_VECTOR(15 DOWNTO 8) := (OTHERS => '0');
SIGNAL s_trg_tr_bit : STD_LOGIC := '0';
SIGNAL s_wo_no_rw_wo_bit : STD_LOGIC := '0';
SIGNAL s_wo_no_rw_wo_slice : STD_LOGIC_VECTOR(14 DOWNTO 8) := (OTHERS => '1');
SIGNAL s_trg_no_rw_tr_bit : STD_LOGIC := '0';
SIGNAL s_trg_no_rw_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '1');
SIGNAL s_wo_no_ro_wo_bit : STD_LOGIC := '0';
SIGNAL s_wo_no_ro_wo_slice : STD_LOGIC_VECTOR(14 DOWNTO 8) := (OTHERS => '1');
SIGNAL s_trg_no_ro_tr_bit : STD_LOGIC := '0';
SIGNAL s_trg_no_ro_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '1');
SIGNAL s_wo_no_wo_wo_bit : STD_LOGIC := '0';
SIGNAL s_wo_no_wo_wo_slice : STD_LOGIC_VECTOR(14 DOWNTO 8) := (OTHERS => '1');
SIGNAL s_trg_no_wo_tr_bit : STD_LOGIC := '0';
SIGNAL s_trg_no_wo_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '1');
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
--* purpose : Wishbone Bus Control
--* type : sequential, rising edge, no reset
wb_ctrl : PROCESS (clk)
BEGIN -- PROCESS wb_ctrl
IF rising_edge(clk) THEN
s_wb_ack <= '0';
s_wb_err <= '0';
s_int_data <= i_wb_data;
s_int_addr <= s_wb_addr;
s_int_we <= (OTHERS => '0');
s_int_trd <= '0';
s_int_twr <= '0';
-- check if anyone requests access
IF (s_wb_ack = '0' AND s_wb_err = '0' AND i_wb_cyc = '1' AND i_wb_stb = '1') THEN
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
IF (i_wb_we = '1') THEN
s_int_we <= i_wb_sel;
s_int_twr <= '1';
ELSE
s_int_trd <= '1';
END IF;
END IF;
s_wb_data <= s_int_data_rb;
END IF;
END PROCESS wb_ctrl;
s_wb_addr <= UNSIGNED(i_wb_addr);
o_wb_data <= s_wb_data;
o_wb_ack <= s_wb_ack;
o_wb_err <= s_wb_err;
o_wb_rty <= '0';
-----------------------------------------------------------------------------
-- WB address validation
WITH to_integer(s_wb_addr) SELECT
s_int_addr_valid <=
'1' WHEN c_addr_read_write,
'1' WHEN c_addr_read_only,
'1' WHEN c_addr_write_only,
'1' WHEN c_addr_trigger,
'1' WHEN c_addr_enum,
'1' WHEN c_addr_notify_rw,
'1' WHEN c_addr_notify_ro,
'1' WHEN c_addr_notify_wo,
'1' WHEN c_addr_const,
'0' WHEN OTHERS;
-----------------------------------------------------------------------------
--* purpose : register access
--* type : sequential, rising edge, high active synchronous reset
reg_access : PROCESS (clk)
BEGIN -- PROCESS reg_access
IF rising_edge(clk) THEN
-- default values / clear trigger signals
s_trg_tr_slice0 <= (OTHERS => '0');
s_trg_tr_slice1 <= (OTHERS => '0');
s_trg_tr_bit <= '0';
s_trg_no_rw_tr_bit <= '0';
s_trg_no_rw_tr_slice <= (OTHERS => '0');
s_trg_no_ro_tr_bit <= '0';
s_trg_no_ro_tr_slice <= (OTHERS => '0');
s_trg_no_wo_tr_bit <= '0';
s_trg_no_wo_tr_slice <= (OTHERS => '0');
o_notify_rw_trd <= '0';
o_notify_rw_twr <= '0';
o_notify_ro_trd <= '0';
o_notify_wo_twr <= '0';
-- WRITE registers
CASE to_integer(s_int_addr) IS
WHEN c_addr_read_write => set_reg(s_int_data, s_int_we, x"FFFFFF08", s_reg_read_write);
WHEN c_addr_write_only => set_reg(s_int_data, s_int_we, x"FFFF0000", s_wo_wo_slice0);
set_reg(s_int_data, s_int_we, x"0000FF00", s_wo_wo_slice1);
set_reg(s_int_data, s_int_we, x"00000008", s_wo_wo_bit);
WHEN c_addr_trigger => set_trg(s_int_data, s_int_we, x"FFFF0000", s_trg_tr_slice0);
set_trg(s_int_data, s_int_we, x"0000FF00", s_trg_tr_slice1);
set_trg(s_int_data, s_int_we, 3, s_trg_tr_bit);
WHEN c_addr_enum => set_reg(s_int_data, s_int_we, x"80003000", s_reg_enum);
WHEN c_addr_notify_rw => set_reg(s_int_data, s_int_we, x"FF000000", s_reg_notify_rw);
set_reg(s_int_data, s_int_we, x"00008000", s_wo_no_rw_wo_bit);
set_reg(s_int_data, s_int_we, x"00007F00", s_wo_no_rw_wo_slice);
set_trg(s_int_data, s_int_we, 7, s_trg_no_rw_tr_bit);
set_trg(s_int_data, s_int_we, x"0000007F", s_trg_no_rw_tr_slice);
set_trd(s_int_trd, o_notify_rw_trd);
set_twr(s_int_twr, o_notify_rw_twr);
WHEN c_addr_notify_ro => set_reg(s_int_data, s_int_we, x"FF000000", s_reg_notify_ro);
set_reg(s_int_data, s_int_we, x"00008000", s_wo_no_ro_wo_bit);
set_reg(s_int_data, s_int_we, x"00007F00", s_wo_no_ro_wo_slice);
set_trg(s_int_data, s_int_we, 7, s_trg_no_ro_tr_bit);
set_trg(s_int_data, s_int_we, x"0000007F", s_trg_no_ro_tr_slice);
set_trd(s_int_trd, o_notify_ro_trd);
WHEN c_addr_notify_wo => set_reg(s_int_data, s_int_we, x"FF000000", s_reg_notify_wo);
set_reg(s_int_data, s_int_we, x"00008000", s_wo_no_wo_wo_bit);
set_reg(s_int_data, s_int_we, x"00007F00", s_wo_no_wo_wo_slice);
set_trg(s_int_data, s_int_we, 7, s_trg_no_wo_tr_bit);
set_trg(s_int_data, s_int_we, x"0000007F", s_trg_no_wo_tr_slice);
set_twr(s_int_twr, o_notify_wo_twr);
WHEN OTHERS => NULL;
END CASE;
-- READ-ONLY registers (override WRITE registers)
s_reg_read_only(31 DOWNTO 16) <= i_ro_slice0;
s_reg_read_only(15 DOWNTO 8) <= i_ro_slice1;
s_reg_read_only(3) <= i_ro_bit;
s_reg_notify_rw(23) <= i_no_rw_ro_bit;
s_reg_notify_rw(22 DOWNTO 16) <= i_no_rw_ro_slice;
s_reg_notify_ro(23) <= i_no_ro_ro_bit;
s_reg_notify_ro(22 DOWNTO 16) <= i_no_ro_ro_slice;
s_reg_notify_wo(23) <= i_no_wo_ro_bit;
s_reg_notify_wo(22 DOWNTO 16) <= i_no_wo_ro_slice;
END IF;
END PROCESS reg_access;
-----------------------------------------------------------------------------
-- WB output data multiplexer
WITH to_integer(s_wb_addr) SELECT
s_int_data_rb <=
s_reg_read_write AND x"FFFFFF08" WHEN c_addr_read_write,
s_reg_read_only AND x"FFFFFF08" WHEN c_addr_read_only,
s_reg_enum AND x"80003000" WHEN c_addr_enum,
s_reg_notify_rw AND x"FFFF0000" WHEN c_addr_notify_rw,
s_reg_notify_ro AND x"FFFF0000" WHEN c_addr_notify_ro,
s_reg_notify_wo AND x"FFFF0000" WHEN c_addr_notify_wo,
s_reg_const AND x"FF003EC0" WHEN c_addr_const,
(OTHERS => '0') WHEN OTHERS;
-----------------------------------------------------------------------------
-- output mappings
o_rw_slice0 <= s_reg_read_write(31 DOWNTO 16);
o_rw_slice1 <= s_reg_read_write(15 DOWNTO 8);
o_rw_bit <= s_reg_read_write(3);
o_wo_slice0 <= s_wo_wo_slice0(31 DOWNTO 16);
o_wo_slice1 <= s_wo_wo_slice1(15 DOWNTO 8);
o_wo_bit <= s_wo_wo_bit;
o_tr_slice0 <= s_trg_tr_slice0(31 DOWNTO 16);
o_tr_slice1 <= s_trg_tr_slice1(15 DOWNTO 8);
o_tr_bit <= s_trg_tr_bit;
o_en_bit <= s_reg_enum(31);
o_en_slice <= s_reg_enum(13 DOWNTO 12);
o_no_rw_rw_bit <= s_reg_notify_rw(31);
o_no_rw_rw_slice <= s_reg_notify_rw(30 DOWNTO 24);
o_no_rw_wo_bit <= s_wo_no_rw_wo_bit;
o_no_rw_wo_slice <= s_wo_no_rw_wo_slice(14 DOWNTO 8);
o_no_rw_tr_bit <= s_trg_no_rw_tr_bit;
o_no_rw_tr_slice <= s_trg_no_rw_tr_slice(6 DOWNTO 0);
o_no_ro_rw_bit <= s_reg_notify_ro(31);
o_no_ro_rw_slice <= s_reg_notify_ro(30 DOWNTO 24);
o_no_ro_wo_bit <= s_wo_no_ro_wo_bit;
o_no_ro_wo_slice <= s_wo_no_ro_wo_slice(14 DOWNTO 8);
o_no_ro_tr_bit <= s_trg_no_ro_tr_bit;
o_no_ro_tr_slice <= s_trg_no_ro_tr_slice(6 DOWNTO 0);
o_no_wo_rw_bit <= s_reg_notify_wo(31);
o_no_wo_rw_slice <= s_reg_notify_wo(30 DOWNTO 24);
o_no_wo_wo_bit <= s_wo_no_wo_wo_bit;
o_no_wo_wo_slice <= s_wo_no_wo_wo_slice(14 DOWNTO 8);
o_no_wo_tr_bit <= s_trg_no_wo_tr_bit;
o_no_wo_tr_slice <= s_trg_no_wo_tr_slice(6 DOWNTO 0);
o_const_bit0 <= s_reg_const(7);
o_const_bit1 <= s_reg_const(6);
o_const_slice0 <= s_reg_const(31 DOWNTO 24);
o_const_slice1 <= s_reg_const(13 DOWNTO 9);
END ARCHITECTURE rtl;
| mit | cae518c0ddffad8f092102e3c0441988 | 0.470375 | 3.218883 | false | false | false | false |
chiggs/nvc | test/regress/assign3.vhd | 5 | 621 | entity assign3 is
end entity;
architecture test of assign3 is
begin
process is
variable x : bit_vector(7 downto 0);
variable y : bit_vector(7 downto 0) := (
0 => '1', 2 => '1', 4 => '1', 6 => '1',
others => '0' );
begin
assert x(0) = '0';
x := (others => '1');
assert x(0) = '1';
assert x(5) = '1';
x := y;
assert x(0) = '1';
assert x(5) = '0';
assert x(6) = '1';
assert x(7) = '0';
assert x = y;
y(4) := '0';
assert x /= y;
wait;
end process;
end architecture;
| gpl-3.0 | 27fa3f603027c68284ee658a7ecc44a0 | 0.415459 | 3.184615 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502/vhdl_sim/tb_decode.vhd | 1 | 15,855 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
use work.pkg_6502_opcodes.all;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_decode is
end tb_decode;
architecture tb of tb_decode is
signal i_reg : std_logic_vector(7 downto 0);
signal s_is_absolute : boolean;
signal s_is_abs_jump : boolean;
signal s_is_immediate : boolean;
signal s_is_implied : boolean;
signal s_is_stack : boolean;
signal s_is_push : boolean;
signal s_is_zeropage : boolean;
signal s_is_indirect : boolean;
signal s_is_relative : boolean;
signal s_is_load : boolean;
signal s_is_store : boolean;
signal s_is_shift : boolean;
signal s_is_alu : boolean;
signal s_is_rmw : boolean;
signal s_is_jump : boolean;
signal s_is_postindexed : boolean;
signal s_is_illegal : boolean;
signal s_select_index_y : boolean;
signal s_store_a_from_alu : boolean;
-- signal s_load_a : boolean;
signal s_load_x : boolean;
signal s_load_y : boolean;
signal clock : std_logic := '0';
signal reset : std_logic := '0';
type t_state is (fetch, decode, absolute, abs_hi, abs_fix, branch, branch_fix,
indir1, indir2, jump_sub, jump, retrn, rmw1, rmw2, vector, startup,
zp, zp_idx, zp_indir, push1, push2, push3, pull1, pull2, pull3 );
signal state : t_state;
signal state_idx : integer range 0 to 31;
signal opcode : string(1 to 13);
signal sync : std_logic;
signal dummy_cycle : std_logic;
signal latch_dreg : std_logic;
signal copy_d2p : std_logic;
signal reg_update : std_logic;
signal rwn : std_logic;
signal vect_addr : std_logic_vector(3 downto 0);
signal a16 : std_logic;
signal a_mux : t_amux := c_amux_pc;
signal dout_mux : t_dout_mux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal stop_clock : boolean := false;
begin
s_is_absolute <= is_absolute(i_reg);
s_is_abs_jump <= is_abs_jump(i_reg);
s_is_immediate <= is_immediate(i_reg);
s_is_implied <= is_implied(i_reg);
s_is_stack <= is_stack(i_reg);
s_is_push <= is_push(i_reg);
s_is_zeropage <= is_zeropage(i_reg);
s_is_indirect <= is_indirect(i_reg);
s_is_relative <= is_relative(i_reg);
s_is_load <= is_load(i_reg);
s_is_store <= is_store(i_reg);
s_is_shift <= is_shift(i_reg);
s_is_alu <= is_alu(i_reg);
s_is_rmw <= is_rmw(i_reg);
s_is_jump <= is_jump(i_reg);
s_is_postindexed <= is_postindexed(i_reg);
s_is_illegal <= is_illegal(i_reg);
s_select_index_y <= select_index_y(i_reg);
s_store_a_from_alu <= store_a_from_alu(i_reg);
--s_load_a <= load_a(i_reg);
s_load_x <= load_x(i_reg);
s_load_y <= load_y(i_reg);
test: process
variable ireg : std_logic_vector(7 downto 0);
variable v_opcode : string(1 to 13);
begin
for i in 0 to 255 loop
ireg := std_logic_vector(to_unsigned(i, 8));
v_opcode := opcode_array(i);
assert not (v_opcode(4)=' ' and is_illegal(ireg)) report "Function says it's illegal, opcode does not." & v_opcode severity error;
assert not (v_opcode(4)='*' and not is_illegal(ireg)) report "Opcode says it's illegal, function says it's not." & v_opcode severity error;
end loop;
wait;
end process;
dump: process
variable inst : std_logic_vector(7 downto 0);
variable bool : boolean;
variable L : line;
type t_bool_array is array(natural range <>) of boolean;
type t_sel_array is array(natural range <>) of std_logic_vector(1 downto 0);
variable b_is_absolute : t_bool_array(0 to 255);
variable b_is_abs_jump : t_bool_array(0 to 255);
variable b_is_immediate : t_bool_array(0 to 255);
variable b_is_implied : t_bool_array(0 to 255);
variable b_is_stack : t_bool_array(0 to 255);
variable b_is_push : t_bool_array(0 to 255);
variable b_is_zeropage : t_bool_array(0 to 255);
variable b_is_indirect : t_bool_array(0 to 255);
variable b_is_relative : t_bool_array(0 to 255);
variable b_is_load : t_bool_array(0 to 255);
variable b_is_store : t_bool_array(0 to 255);
variable b_is_shift : t_bool_array(0 to 255);
variable b_is_alu : t_bool_array(0 to 255);
variable b_is_rmw : t_bool_array(0 to 255);
variable b_is_jump : t_bool_array(0 to 255);
variable b_is_postindexed : t_bool_array(0 to 255);
variable b_select_index_y : t_bool_array(0 to 255);
variable b_store_a_from_alu : t_bool_array(0 to 255);
variable b_shift_sel : t_sel_array(0 to 255);
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
procedure output_bool(bool : boolean) is
begin
if bool then
write_str(L, " (*) ");
else
write_str(L, " . ");
end if;
end procedure;
procedure output_shift_sel(bool : boolean; sel: std_logic_vector(1 downto 0)) is
type t_string_array is array(natural range <>) of string(1 to 5);
constant c_shift_sel_str : t_string_array(0 to 3) := ( "0xFF ", "data ", "accu ", " A&D " );
begin
if bool then
write_str(L, c_shift_sel_str(to_integer(unsigned(sel))));
else
write_str(L, " . ");
end if;
end procedure;
procedure print_table(b : t_bool_array; title: string) is
begin
write(L, title);
writeline(output, L);
writeline(output, L);
write_str(L, " ");
for x in 0 to 7 loop
inst := std_logic_vector(to_unsigned(x*32, 8));
write(L, VecToHex(inst, 2));
write_str(L, " ");
end loop;
writeline(output, L);
for y in 0 to 31 loop
inst := std_logic_vector(to_unsigned(y, 8));
write(L, VecToHex(inst, 2));
write(L, ' ');
for x in 0 to 7 loop
output_bool(b(y + x*32));
end loop;
writeline(output, L);
end loop;
writeline(output, L);
writeline(output, L);
end procedure;
procedure print_sel_table(title: string) is
begin
write(L, title);
writeline(output, L);
writeline(output, L);
write_str(L, " ");
for x in 0 to 7 loop
inst := std_logic_vector(to_unsigned(x*32, 8));
write(L, VecToHex(inst, 2));
write_str(L, " ");
end loop;
writeline(output, L);
for y in 0 to 31 loop
inst := std_logic_vector(to_unsigned(y, 8));
write(L, VecToHex(inst, 2));
write(L, ' ');
for x in 0 to 7 loop
output_shift_sel(b_is_shift(y + x*32), b_shift_sel(y + x*32));
end loop;
writeline(output, L);
end loop;
writeline(output, L);
writeline(output, L);
end procedure;
procedure write_bool(variable L : inout line; b : boolean; t : string; f : string := "") is
begin
write(L, ";");
if b then
write(L, t);
else
write(L, f);
end if;
end procedure;
procedure write_signals(variable L : inout line) is
begin
write_bool(L, latch_dreg='1', "LatchDREG");
write_bool(L, reg_update='1', "RegUpdate");
write_bool(L, copy_d2p='1', "Load P");
write_bool(L, rwn='0', "Write");
write_bool(L, a16='1', "Inst", "Data");
write(L, ";ADDR:" & t_amux'image(a_mux));
write(L, ";DOUT:" & t_dout_mux'image(dout_mux));
write(L, ";PC:" & t_pc_oper'image(pc_oper));
write(L, ";SP:" & t_sp_oper'image(s_oper));
write(L, ";ADL:" & t_adl_oper'image(adl_oper));
write(L, ";ADH:" & t_adh_oper'image(adh_oper));
end procedure;
file fout : text;
type t_string_array is array(natural range <>) of string(1 to 3);
constant alu_strings : t_string_array(0 to 7) := ("OR ", "AND", "EOR", "ADC", "---", "LD ", "CMP", "SBC" );
constant shift_strings : t_string_array(0 to 7) := ("ASL", "ROL", "LSR", "ROR", "---", "LD ", "DEC", "INC" );
variable j : integer;
begin
for i in 0 to 255 loop
inst := std_logic_vector(to_unsigned(i, 8));
b_is_absolute(i) := is_absolute(inst);
b_is_abs_jump(i) := is_abs_jump(inst);
b_is_immediate(i) := is_immediate(inst);
b_is_implied(i) := is_implied(inst);
b_is_stack(i) := is_stack(inst);
b_is_push(i) := is_push(inst);
b_is_zeropage(i) := is_zeropage(inst);
b_is_indirect(i) := is_indirect(inst);
b_is_relative(i) := is_relative(inst);
b_is_load(i) := is_load(inst);
b_is_store(i) := is_store(inst);
b_is_shift(i) := is_shift(inst);
b_is_alu(i) := is_alu(inst);
b_is_rmw(i) := is_rmw(inst);
b_is_jump(i) := is_jump(inst);
b_is_postindexed(i) := is_postindexed(inst);
b_select_index_y(i) := select_index_y(inst);
b_store_a_from_alu(i) := store_a_from_alu(inst);
b_shift_sel(i) := shifter_in_select(inst);
end loop;
print_table(b_is_absolute , "is_absolute");
print_table(b_is_abs_jump , "is_abs_jump");
print_table(b_is_immediate , "is_immediate");
print_table(b_is_implied , "is_implied");
print_table(b_is_stack , "is_stack");
print_table(b_is_push , "is_push");
print_table(b_is_zeropage , "is_zeropage");
print_table(b_is_indirect , "is_indirect");
print_table(b_is_relative , "is_relative");
print_table(b_is_load , "is_load");
print_table(b_is_store , "is_store");
print_table(b_is_shift , "is_shift");
print_table(b_is_alu , "is_alu");
print_table(b_is_rmw , "is_rmw");
print_table(b_is_jump , "is_jump");
print_table(b_is_postindexed , "is_postindexed");
print_table(b_select_index_y , "Select index Y");
print_table(b_store_a_from_alu , "Store A from ALU");
print_sel_table("Shifter Input");
reset <= '1';
wait until clock = '1';
wait until clock = '1';
reset <= '0';
file_open(fout, "opcodes.csv", WRITE_MODE);
write(L, "Code;Opcode;State;IMM#;IMPL;ABS;REL;RMW;ZP;INDIR;INDEXED;X/Y;AJMP;JUMP;STACK;PUSH;LOAD;STORE;SHIFT;ALU;ALU->A;->SH" );
writeline(fout, L);
for i in 0 to 256 loop
j := i mod 256;
while sync /= '1' loop
write(L, ";;" & t_state'image(state));
write(L, ";;;;;;;;;;;;;;;;;;;");
write_signals(L);
writeline(fout,L);
wait until clock = '1';
end loop;
i_reg <= std_logic_vector(to_unsigned(j, 8));
write(L, VecToHex(std_logic_vector(to_unsigned(j, 8)), 2));
write(L, ";" & opcode_array(j));
write(L, ";" & t_state'image(state));
write_bool(L, b_is_immediate(j) , "IMM#");
write_bool(L, b_is_implied(j) , "IMPL");
write_bool(L, b_is_absolute(j) , "ABS");
write_bool(L, b_is_relative(j) , "REL");
write_bool(L, b_is_rmw(j) , "RMW");
write_bool(L, b_is_zeropage(j) , "ZP");
write_bool(L, b_is_indirect(j) , "INDIR");
write_bool(L, b_is_postindexed(j), "INDEXED");
write_bool(L, b_select_index_y(j), "Y", "X" );
write_bool(L, b_is_abs_jump(j) , "AJMP");
write_bool(L, b_is_jump(j) , "JUMP");
write_bool(L, b_is_stack(j) , "STACK");
write_bool(L, b_is_push(j) and b_is_stack(j), "PUSH");
write_bool(L, b_is_load(j) , "LOAD");
write_bool(L, b_is_store(j) , "STORE");
write_bool(L, b_is_shift(j) , "SHIFT:" & shift_strings(to_integer(unsigned(i_reg(7 downto 5)))));
write_bool(L, b_is_alu(j) , "ALU:" & alu_strings(to_integer(unsigned(i_reg(7 downto 5)))));
write_bool(L, b_store_a_from_alu(j), "ALU->A");
write(L, ";");
output_shift_sel(b_is_shift(j), b_shift_sel(j));
write_signals(L);
writeline(fout,L);
wait until clock = '1';
end loop;
stop_clock <= true;
file_close(fout);
wait;
end process;
clock <= not clock after 0.5 us when not stop_clock;
i_proc: entity work.proc_control
generic map (true)
port map (
clock => clock,
clock_en => '1',
ready => '1',
reset => reset,
interrupt => '0',
i_reg => i_reg,
index_carry => '0',
pc_carry => '0',
branch_taken => true,
sync => sync,
dummy_cycle => open,
state_idx => state_idx,
latch_dreg => latch_dreg,
copy_d2p => copy_d2p,
reg_update => reg_update,
rwn => rwn,
-- set_i_flag => set_i_flag,
-- nmi_done => nmi_done,
vect_sel => "00",
vect_addr => vect_addr,
a16 => a16,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper
);
state <= t_state'val(state_idx);
opcode <= opcode_array(to_integer(unsigned(i_reg)));
end tb;
| gpl-3.0 | 472082574abfa5b660e57583d9c3f1a8 | 0.463513 | 3.446739 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4b.vhd | 2 | 12,444 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM (burst capable)
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v4b is
generic (
g_simulation : boolean := false;
A_Width : integer := 15;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req;
resp : out t_mem_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v4b;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v4b is
-- SRCW
constant c_cmd_inactive : std_logic_vector(3 downto 0) := "1111";
constant c_cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant c_cmd_active : std_logic_vector(3 downto 0) := "0011";
constant c_cmd_read : std_logic_vector(3 downto 0) := "0101";
constant c_cmd_write : std_logic_vector(3 downto 0) := "0100";
constant c_cmd_bterm : std_logic_vector(3 downto 0) := "0110";
constant c_cmd_precharge : std_logic_vector(3 downto 0) := "0010";
constant c_cmd_refresh : std_logic_vector(3 downto 0) := "0001";
constant c_cmd_mode_reg : std_logic_vector(3 downto 0) := "0000";
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(3 downto 0);
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", c_cmd_precharge ),
( X"0222", c_cmd_mode_reg ), -- mode register, burstlen=4, writelen=1, CAS lat = 2
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ),
( X"0000", c_cmd_refresh ) );
type t_state is (boot, init, idle, sd_read, read_single, read_single_end, sd_write, wait_for_precharge, delay_to_terminate);
signal state : t_state;
signal sdram_cmd : std_logic_vector(3 downto 0) := "1111";
signal sdram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sdram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal rwn_i : std_logic;
signal tag : std_logic_vector(req.tag'range);
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal refresh_inhibit: std_logic := '0';
signal not_clock : std_logic;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal refr_delay : integer range 0 to 3;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal dack_count : unsigned(1 downto 0) := "00";
signal count_out : unsigned(1 downto 0) := "00";
signal dack : std_logic := '0';
signal dack_pre : std_logic := '0';
signal rack : std_logic := '0';
signal dack_tag_pre : std_logic_vector(req.tag'range) := (others => '0');
signal rack_tag : std_logic_vector(req.tag'range) := (others => '0');
signal dack_tag : std_logic_vector(req.tag'range) := (others => '0');
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
attribute iob of sdram_cmd : signal is "true";
attribute iob of mem_a_i : signal is "true";
attribute iob of SDRAM_CKE : signal is "false";
begin
is_idle <= '1' when state = idle else '0';
req_i <= req.request;
resp.data <= rdata_i;
resp.rack <= rack;
resp.rack_tag <= rack_tag;
resp.dack_tag <= dack_tag;
resp.count <= count_out;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
sdram_cmd <= c_cmd_refresh;
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
rack <= '1';
rack_tag <= req.tag;
tag <= req.tag;
rwn_i <= req.read_writen;
dack_count <= req.size;
sdram_d_o <= req.data;
mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
mem_a_i(14 downto 13) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
sdram_cmd <= c_cmd_active;
end procedure;
begin
if rising_edge(clock) then
rack <= '0';
rack_tag <= (others => '0');
dack_pre <= '0';
dack_tag_pre <= (others => '0');
dack <= dack_pre;
dack_tag <= dack_tag_pre;
if dack='1' then
count_out <= count_out + 1;
else
count_out <= "00";
end if;
rdata_i <= MEM_D; -- clock in
sdram_cmd <= c_cmd_inactive;
SDRAM_CKE <= enable_sdram;
sdram_d_t <= '0';
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
if delay /= 0 then
delay <= delay - 1;
end if;
if inhibit='1' then
refresh_inhibit <= '1';
end if;
case state is
when boot =>
refresh_inhibit <= '0';
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
sdram_cmd(3) <= '1';
sdram_cmd(2 downto 0) <= c_init_array(init_cnt).cmd(2 downto 0);
if delay = 0 then
delay <= 7;
sdram_cmd(3) <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 1, should not be a refresh
-- this enables putting cartridge images in sdram, because we guarantee the first access after inhibit to be a cart cycle
if do_refresh='1' and refresh_inhibit='0' then
send_refresh_cmd;
elsif inhibit='0' then -- make sure we are allowed to start a new cycle
if req_i='1' and refr_delay = 0 then
accept_req;
refresh_inhibit <= '0';
if req.read_writen = '1' then
state <= sd_read;
else
state <= sd_write;
end if;
end if;
end if;
when sd_read =>
mem_a_i(10) <= '0'; -- no auto precharge
mem_a_i(9 downto 0) <= col_addr;
sdram_cmd <= c_cmd_read;
if dack_count = "00" then
state <= read_single;
else
state <= delay_to_terminate;
end if;
when read_single =>
dack_pre <= '1';
dack_tag_pre <= tag;
sdram_cmd <= c_cmd_bterm;
state <= read_single_end;
when read_single_end =>
sdram_cmd <= c_cmd_precharge;
state <= idle;
when delay_to_terminate =>
dack_pre <= '1';
dack_tag_pre <= tag;
dack_count <= dack_count - 1;
delay <= 2;
if dack_count = "00" then
sdram_cmd <= c_cmd_precharge;
state <= idle;
end if;
when sd_write =>
if delay = 0 then
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sdram_cmd <= c_cmd_write;
sdram_d_t <= '1';
delay <= 2;
state <= wait_for_precharge;
end if;
when wait_for_precharge =>
if delay = 0 then
state <= idle;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
sdram_d_t <= '0';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
refresh_inhibit <= '0';
end if;
end if;
end process;
MEM_D <= sdram_d_o when sdram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
SDRAM_CSn <= sdram_cmd(3);
SDRAM_RASn <= sdram_cmd(2);
SDRAM_CASn <= sdram_cmd(1);
SDRAM_WEn <= sdram_cmd(0);
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
-- ACT to READ: tRCD = 20 ns ( = 1 CLK)
-- ACT to PRCH: tRAS = 44 ns ( = 3 CLKs)
-- ACT to ACT: tRC = 66 ns ( = 4 CLKs)
-- ACT to ACTb: tRRD = 15 ns ( = 1 CLK)
-- PRCH time; tRP = 20 ns ( = 1 CLK)
-- wr. recov. tWR=8ns+1clk ( = 2 CLKs) (starting from last data word)
-- CL=2
-- 0 1 2 3 4 5 6 7 8 9
-- BL1 A R P +
-- - - - D
-- +: ONLY if same bank, otherwise we don't meet tRC.
-- BL2 A R - P
-- - - - D D
-- BL3 A R - - P
-- - - - D D D
-- BL4 A r - - - p
-- - - - D D D D
-- BL1W A(W)= = p
-- - D - - -
-- BL4 A r - - - p - A
-- - - - D D D D
-- BL1W A(W)= = p
-- - D - - -
| gpl-3.0 | cc34cac9138d45ebdab9e5e00b4c82d5 | 0.447203 | 3.69697 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/harness_floppy.vhd | 1 | 5,319 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : harness_floppy
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Simulation wrapper for floppy
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
use work.rocket_pkg.all;
entity harness_floppy is
end entity;
architecture Harness of harness_floppy is
signal clock : std_logic := '0';
signal reset : std_logic;
signal tick_16MHz : std_logic;
signal mem_rdata : std_logic_vector(7 downto 0) := X"00";
signal do_read : std_logic;
signal do_write : std_logic;
signal do_advance : std_logic;
signal floppy_inserted : std_logic := '1';
signal motor_on : std_logic := '1';
signal sync : std_logic;
signal mode : std_logic := '0';
signal write_prot_n : std_logic := '1';
signal step : std_logic_vector(1 downto 0) := "00";
signal byte_ready : std_logic;
signal soe : std_logic := '1';
signal rate_ctrl : std_logic_vector(1 downto 0) := "11";
signal read_data : std_logic_vector(7 downto 0);
signal read_data_d : std_logic_vector(7 downto 0) := X"FF";
type t_bytes is array(natural range <>) of std_logic_vector(7 downto 0);
-- constant input : t_bytes := ( X"FF", X"FF", X"55", X"55", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
-- X"00", X"00", X"00", X"00", X"55", X"F7", X"54", X"55", X"55", X"55", X"55",
-- X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"AA" );
constant input : t_bytes := (
X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55", X"55",
X"55", X"55", X"55", X"55", X"55", X"55", X"5F", X"55", X"55", X"F5", X"25", X"4B", X"52", X"94", X"B5", X"29",
X"4A", X"52", X"94", X"A4", X"A4", X"A4", X"A4", X"A4", X"A4", X"A4", X"A4", X"AB", X"BB", X"FF", X"FF", X"FF",
X"FF", X"FF", X"FD", X"57", X"56", X"A9", X"24", X"00", X"02", X"AB", X"53", X"BB", X"BB", X"BB", X"BB", X"BB",
X"BB", X"BB", X"BA", X"5A", X"96", X"A5", X"A9", X"6A", X"5A", X"96", X"A5", X"A9", X"6A", X"5A", X"96", X"A5",
X"A9", X"6A", X"5A", X"96", X"A5", X"A9", X"6A", X"5A", X"96", X"A5", X"A9", X"6A", X"5A", X"96", X"A5", X"A9" );
--constant bytes_per_track : natural := rocket_array'length;
constant bytes_per_track : natural := 7756;
constant bits_per_track : natural := 8 * bytes_per_track;
constant half_clocks_per_track : natural := 100_000_000 / 5; -- 5 RPS = 300 RPM
signal bit_time : unsigned(9 downto 0) := to_unsigned((half_clocks_per_track / bits_per_track) + 43, 10); -- steps of 10 ns (half clocks)
begin
clock <= not clock after 10 ns; -- 50 MHz
reset <= '1', '0' after 100 ns;
mode <= transport '0', '1' after 5 ms, '0' after 10 ms;
i_div: entity work.fractional_div
generic map (
g_numerator => 8,
g_denominator => 25
)
port map (
clock => clock,
tick => tick_16MHz
);
i_floppy: entity work.floppy_stream
port map (
clock => clock,
reset => reset,
tick_16MHz => tick_16MHz,
mem_rdata => mem_rdata,
do_read => do_read,
do_write => do_write,
do_advance => do_advance,
floppy_inserted => floppy_inserted,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
bit_time => bit_time,
read_data => read_data
);
process
begin
for i in input'range loop
mem_rdata <= input(i);
wait until do_read = '1';
end loop;
end process;
process(byte_ready)
variable last : time := 0.0 ns;
begin
if falling_edge(byte_ready) then
read_data_d <= read_data;
-- report hstr(read_data) & " after " & time'image(now - last);
last := now;
end if;
end process;
process
variable L : line;
variable limit : natural := 0;
begin
wait until byte_ready = '0' or sync = '0';
if sync = '0' then
writeline(output, L);
write(L, "sync ");
limit := 0;
end if;
if byte_ready = '0' then
limit := limit + 1;
if limit <= 32 then
write(L, hstr(read_data) & " ");
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 3d8732d378d10c4c4b84974da83ab1bb | 0.459485 | 3.213897 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/uart_lite/vhdl_source/tx.vhd | 1 | 2,939 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Serial Transmitter: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
-- Description: This module sends a character over a serial line
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tx is
generic (clks_per_bit : integer := 434); -- 115k2 @ 50 MHz
port (
clk : in std_logic;
reset : in std_logic;
tick : in std_logic;
dotx : in std_logic;
txchar : in std_logic_vector(7 downto 0);
cts : in std_logic := '1';
txd : out std_logic;
done : out std_logic );
end tx;
architecture gideon of tx is
signal bitcnt : integer range 0 to 9;
signal bitvec : std_logic_vector(8 downto 0);
signal timer : integer range 0 to clks_per_bit;
type state_t is (Idle, Waiting, Transmitting);
signal state : state_t;
signal cts_c : std_logic := '1';
begin
process(clk, reset)
begin
if rising_edge(clk) then
cts_c <= cts;
case state is
when Idle =>
if DoTx='1' then
if cts_c='1' then
state <= Transmitting;
else
state <= Waiting;
end if;
bitcnt <= 9;
bitvec <= not(txchar) & '1';
timer <= clks_per_bit - 1;
end if;
when Waiting =>
if cts_c='1' then
state <= Transmitting;
end if;
when Transmitting =>
if tick = '1' then
if timer=0 then
timer <= clks_per_bit - 1;
if bitcnt = 0 then
state <= Idle;
else
bitcnt <= bitcnt - 1;
bitvec <= '0' & bitvec(8 downto 1);
end if;
else
timer <= timer - 1;
end if;
end if;
end case;
end if;
if reset='1' then
state <= Idle;
bitcnt <= 0;
timer <= 0;
bitvec <= (others => '0');
end if;
end process;
done <= '1' when state=Idle else '0';
txd <= not(bitvec(0));
end gideon;
| gpl-3.0 | 57b2e9381e5395fbc4618a1d2fc02155 | 0.366451 | 4.849835 | false | false | false | false |
chiggs/nvc | test/regress/case6.vhd | 5 | 619 | entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
y <= 4;
end case;
end process;
process is
begin
wait for 1 ns;
assert y = 4;
x <= 2;
wait for 1 ns;
assert y = 1;
x <= 10;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
| gpl-3.0 | a1be2e10c7bd6826215867f9ea39d320 | 0.400646 | 4.126667 | false | false | false | false |
fpgaddicted/5bit-shift-register-structural- | mux8to1.vhd | 1 | 1,375 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:29:53 03/31/2017
-- Design Name:
-- Module Name: mux8to1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux8to1 is
Port ( Y : out STD_LOGIC;
sel : in STD_LOGIC_VECTOR (2 downto 0);
I : in STD_LOGIC_VECTOR (7 downto 0));
end mux8to1;
architecture Behavioral of mux8to1 is
begin
process(sel, I)
begin
case sel is
when "000" => Y <= I(0);
when "001" => Y <= I(1);
when "010" => Y <= I(2);
when "011" => Y <= I(3);
when "100" => Y <= I(4);
when "101" => Y <= I(5);
when "110" => Y <= I(6);
when others => Y <=I(7);
end case;
end process;
end Behavioral;
| gpl-3.0 | 19adcd60f070a349cf74921105e2e2c7 | 0.52 | 3.428928 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_sim/rmii_transceiver_tb.vhd | 1 | 4,041 | -------------------------------------------------------------------------------
-- Title : rmii_transceiver_tb
-- Author : Gideon Zweijtzer ([email protected])
-------------------------------------------------------------------------------
-- Description: Testbench for rmii transceiver
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity rmii_transceiver_tb is
end entity;
architecture testcase of rmii_transceiver_tb is
signal clock : std_logic := '0'; -- 50 MHz reference clock
signal reset : std_logic;
signal rmii_crs_dv : std_logic;
signal rmii_rxd : std_logic_vector(1 downto 0);
signal rmii_tx_en : std_logic;
signal rmii_txd : std_logic_vector(1 downto 0);
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_sof : std_logic;
signal eth_tx_eof : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic;
signal ten_meg_mode : std_logic;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant c_frame_with_crc : t_byte_array := (
X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12", X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11", X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C", X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E", X"0F", X"10", X"11", X"12", X"13"
-- , X"7A", X"D5", X"6B", X"B3"
);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.rmii_transceiver
port map (
clock => clock,
reset => reset,
rmii_crs_dv => rmii_crs_dv,
rmii_rxd => rmii_rxd,
rmii_tx_en => rmii_tx_en,
rmii_txd => rmii_txd,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_sof => eth_tx_sof,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => ten_meg_mode
);
rmii_crs_dv <= rmii_tx_en;
rmii_rxd <= rmii_txd;
test: process
variable i : natural;
begin
eth_tx_data <= X"00";
eth_tx_sof <= '0';
eth_tx_eof <= '0';
eth_tx_valid <= '0';
ten_meg_mode <= '0';
wait until reset = '0';
wait until clock = '1';
i := 0;
L1: loop
wait until clock = '1';
if eth_tx_valid = '0' or eth_tx_ready = '1' then
if eth_tx_eof = '1' then
eth_tx_valid <= '0';
eth_tx_data <= X"00";
exit L1;
else
eth_tx_data <= c_frame_with_crc(i);
eth_tx_valid <= '1';
if i = c_frame_with_crc'left then
eth_tx_sof <= '1';
else
eth_tx_sof <= '0';
end if;
if i = c_frame_with_crc'right then
eth_tx_eof <= '1';
else
eth_tx_eof <= '0';
end if;
i := i + 1;
end if;
end if;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 | 9b9842e432633717c26926a2c48916d7 | 0.429102 | 3.317734 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/uart_lite/vhdl_source/uart_peripheral_fast.vhd | 1 | 5,195 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity uart_peripheral_fast is
generic (
g_divisor : natural := 35 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
irq : out std_logic;
txd : out std_logic;
rxd : in std_logic := '1';
rts : out std_logic;
cts : in std_logic := '1' );
end uart_peripheral_fast;
architecture gideon of uart_peripheral_fast is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic := '0';
signal rxfifo_get : std_logic := '0';
signal rxfifo_dout : std_logic_vector(7 downto 0) := X"00";
signal rxfifo_full : std_logic := '0';
signal rxfifo_dav : std_logic := '0';
signal overflow : std_logic := '0';
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(1 downto 0);
signal rdata_mux : std_logic_vector(7 downto 0);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_afull : std_logic := '1';
signal txfifo_empty : std_logic := '0';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
constant c_uart_data : unsigned(1 downto 0) := "00";
constant c_uart_get : unsigned(1 downto 0) := "01";
constant c_uart_flags : unsigned(1 downto 0) := "10";
constant c_uart_imask : unsigned(1 downto 0) := "11";
begin
i_tx_fifo: entity work.sync_fifo
generic map (
g_depth => 1024,
g_data_width => 8,
g_threshold => 512,
g_fall_through => true
)
port map(
clock => clock,
reset => reset,
rd_en => txfifo_get,
wr_en => txfifo_put,
din => io_req.data,
dout => txfifo_dout,
flush => '0',
empty => txfifo_empty,
almost_full => txfifo_afull,
full => txfifo_full,
valid => txfifo_dav
);
my_tx: entity work.tx
generic map (g_divisor)
port map (
clk => clock,
reset => reset,
tick => '1',
dotx => dotx,
txchar => txchar,
cts => cts,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (g_divisor)
port map (
clk => clock,
reset => reset,
tick => '1',
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
i_rxfifo: entity work.sync_fifo
generic map(
g_depth => 1024,
g_data_width => 8,
g_threshold => 1000,
g_fall_through => true
)
port map(
clock => clock,
reset => reset,
wr_en => rx_ack,
din => rxchar,
rd_en => rxfifo_get,
dout => rxfifo_dout,
flush => '0',
almost_full => rxfifo_full,
valid => rxfifo_dav
);
txfifo_put <= '1' when io_req.write = '1' and io_req.address(1 downto 0) = c_uart_data else '0';
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
io_resp <= c_io_resp_init;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
dotx <= txfifo_dav and done and not dotx;
txchar <= txfifo_dout;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(1 downto 0) is
when c_uart_data => -- dout
-- outside of process
when c_uart_get => -- din
rxfifo_get <= '1';
when c_uart_flags => -- clear flags
overflow <= overflow and not io_req.data(0);
when c_uart_imask => -- interrupt control
imask <= io_req.data(1 downto 0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
io_resp.data <= rdata_mux;
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
irq <= (flags(3) and imask(1)) or (flags(7) and imask(0));
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= txfifo_empty;
flags(3) <= not txfifo_afull;
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
rts <= not rxfifo_full;
with io_req.address(1 downto 0) select rdata_mux <=
rxfifo_dout when c_uart_data,
flags when c_uart_flags,
"000000" & imask when c_uart_imask,
X"00" when others;
end gideon;
| gpl-3.0 | c3ae40b4c0179724f911fe22b444ca61 | 0.489124 | 3.317369 | false | false | false | false |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_sim/tb_sid_from_stream.vhd | 1 | 4,740 | -------------------------------------------------------------------------------
-- Date $Date: 2005/04/12 19:09:27 $
-- Author $Author: Gideon $
-- Revision $Revision: 1.1 $
-- Log $Log: oscillator.vhd,v $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.wave_pkg.all;
entity tb_sid_from_stream is
end entity;
architecture tb of tb_sid_from_stream is
signal clock : std_logic := '0';
signal reset : std_logic;
signal addr : unsigned(7 downto 0) := (others => '0');
signal wren : std_logic := '0';
signal wdata : std_logic_vector(7 downto 0) := (others => '0');
signal rdata : std_logic_vector(7 downto 0) := (others => '0');
signal start_iter : std_logic := '0';
signal sid_pwm : std_logic := '0';
signal sample_out : signed(17 downto 0);
signal stop_clock : boolean := false;
signal vc : real := 0.0;
constant R : real := 2200.0;
constant C : real := 0.000000022;
constant c_cpu_period : time := 1014973 ps;
constant c_half_clock : time := c_cpu_period / 8;
constant c_clock : time := c_half_clock * 2;
begin
clock <= not clock after c_half_clock when not stop_clock; -- 5 MHz
reset <= '1', '0' after 1 us;
sid: entity work.sid_top
generic map (
g_filter_div => 20, -- 194 for 50 MHz;
g_num_voices => 3 )
port map (
clock => clock,
reset => reset,
addr => addr,
wren => wren,
wdata => wdata,
rdata => rdata,
start_iter => start_iter,
sample_left => sample_out );
-- i_pdm_sid: entity work.sigma_delta_dac
-- generic map (
-- g_left_shift => 0,
-- g_width => sample_out'length )
-- port map (
-- clock => clock,
-- reset => reset,
--
-- dac_in => sample_out,
--
-- dac_out => sid_pwm );
--
-- filter: process(clock)
-- variable v_dac : real;
-- variable i_r : real;
-- variable q_c : real;
-- begin
-- if rising_edge(clock) then
-- if sid_pwm='0' then
-- v_dac := -1.2;
-- else
-- v_dac := 1.2;
-- end if;
-- i_r := (v_dac - vc) / R;
-- q_c := i_r * 200.0e-9; -- 200 ns;
-- vc <= vc + (q_c / C);
-- end if;
-- end process;
--
test: process
variable trace_in : h_mem_object;
variable addr_i : integer := 0;
variable delay : time := 1 ns;
variable t : unsigned(15 downto 0);
variable data : std_logic_vector(31 downto 0);
begin
register_mem_model(tb_sid_from_stream'path_name, "trace", trace_in);
load_memory("Commando.sid_tune1.stream", trace_in, X"00000000");
wait until reset='0';
wait until clock='1';
L1: while now < 5000 ms loop
data := read_memory_32(trace_in, std_logic_vector(to_unsigned(addr_i, 32)));
addr_i := addr_i + 4;
wdata <= data(31 downto 24);
addr <= unsigned(data(23 downto 16));
t := unsigned(data(15 downto 0));
if t = 0 then
exit L1;
end if;
wren <= '1';
wait for 1 * c_clock;
wren <= '0';
wait for 3 * c_clock;
delay := (1 us) * (to_integer(t)-1);
wait for delay;
end loop;
stop_clock <= true;
wait;
end process test;
process
begin
wait for 3 * c_clock;
start_iter <= '1';
wait for 1 * c_clock;
start_iter <= '0';
if stop_clock then
wait;
end if;
end process;
-- this clock is a little faster (1 Mhz instead of 985250 Hz, thus we need to adjust our sample rate by the same amount
-- which means we need to sample at 48718 Hz instead of 48kHz. Sample period =
process
variable chan : t_wave_channel;
begin
open_channel(chan);
while not stop_clock loop
wait for 20833 ns; -- 20526 ns;
push_sample(chan, to_integer(sample_out(17 downto 2)));
end loop;
write_wave("sid_wave_commando.wav", 48000, (0 => chan));
wait;
end process;
end tb;
| gpl-3.0 | 0acb6ffb0e7a1b0c1bdd6d3b73ce0a74 | 0.462025 | 3.615561 | false | false | false | false |
chiggs/nvc | test/regress/issue153.vhd | 4 | 2,179 | entity test_inst is
generic(
G_ROUND : natural := 0;
G_ROUND_ENABLE : boolean := false
);
port(
i_value : in bit_vector(7 downto 0);
o_ena : out bit;
o_value : out bit_vector(7 downto 0)
);
end test_inst;
architecture rtl of test_inst is
begin
o_ena <='1' when G_ROUND_ENABLE else '0';
o_value <=(others=>'1') when G_ROUND=1 and G_ROUND_ENABLE else not i_value;
end architecture rtl;
entity issue153 is
end entity issue153;
architecture beh of issue153 is
constant G_ROUND_ENABLE:boolean:=true;
constant C_ADDROUND : bit_vector(7 downto 0):="00001111";
constant C_ZERO8 : bit_vector(7 downto 0):=(others=>'0');
signal s_ena:bit_vector(7 downto 0);
type T_IN_DATA is array(integer range<>) of bit_vector(7 downto 0);
--signal s_value: T_IN_DATA(7 downto -1);-- this should work anyway, uncomment this to compare with ghdl for bug 2
signal s_value: T_IN_DATA(7 downto 0);--this is for bug 1, nvc should report error
begin
GEN_MACS_V : for v in 0 to 7 generate
signal C :bit_vector(7 downto 0);
signal D :bit_vector(7 downto 0);
begin
--should fail here, but doesn't
--GHDL failed here with "bound check failure"
-- ghdl drives correct values on each instances, nvc doesn't
C <= C_ADDROUND when v=0 and G_ROUND_ENABLE else s_value(v-1);--bug 1
-- below is workaround, but I am lazy enough to not use it :))))
--c_gen: if v=0 and G_ROUND_ENABLE generate
-- C <= C_ADDROUND;
--end generate c_gen;
--nc_gen: if v>0 generate
-- C <= s_value(v-1);
--end generate nc_gen;
test_i : entity work.test_inst
generic map(
G_ROUND => 1
)
port map(
i_value => C,
o_ena => s_ena(v),
o_value => s_value(v)
);
end generate GEN_MACS_V;
process
begin
wait for 1 ns;
assert s_value(0) = not C_ADDROUND;
assert s_value(1) = C_ADDROUND;
wait;
end process;
end architecture;
| gpl-3.0 | 5f74a6744b3ce265afc3cfecbc3d07b3 | 0.562643 | 3.537338 | false | true | false | false |
nussbrot/AdvPT | wb_i2c_bridge/vhdl/wbs_cfg_i2c_bridge.vhd | 2 | 9,633 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2017 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project : glb_lib
-- File : wbs_cfg_i2c_bridge.vhd
-- Created : 09.06.2017
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--*
--* @short Wishbone register module
--* Auto-generated by 'export_wbs.tcl' based on '../../../../sxl/tpl/wb_reg_no_rst.tpl.vhd'
--*
--* Needed Libraries and Packages:
--* @li ieee.std_logic_1164 standard multi-value logic package
--* @li ieee.numeric_std
--*
--* @author sforster
--* @date 30.06.2016
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- 09.06.2017 sforster: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-------------------------------------------------------------------------------
ENTITY wbs_cfg_i2c_bridge IS
GENERIC (
g_addr_bits : INTEGER := 7);
PORT (
-- Wishbone interface
clk : IN STD_LOGIC;
i_wb_cyc : IN STD_LOGIC;
i_wb_stb : IN STD_LOGIC;
i_wb_we : IN STD_LOGIC;
i_wb_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wb_addr : IN STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
i_wb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_ack : OUT STD_LOGIC;
o_wb_rty : OUT STD_LOGIC;
o_wb_err : OUT STD_LOGIC;
-- Custom ports
o_dev_addr : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_clk_div : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
i_status : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ENTITY wbs_cfg_i2c_bridge;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF wbs_cfg_i2c_bridge IS
-----------------------------------------------------------------------------
-- Procedures
-----------------------------------------------------------------------------
-- Write access to 32bit register
PROCEDURE set_reg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg : INOUT STD_LOGIC_VECTOR) IS
BEGIN
FOR i IN s_reg'RANGE LOOP
IF (i_wr_mask(i) = '1' AND i_wr_en(i/8) = '1') THEN
s_reg(i) <= i_wr_data(i);
END IF;
END LOOP;
END PROCEDURE set_reg;
-- Write access to single bit register.
-- Since the index is lost, we rely on the mask to set the correct value.
PROCEDURE set_reg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg : INOUT STD_LOGIC) IS
BEGIN
FOR i IN i_wr_mask'RANGE LOOP
IF (i_wr_mask(i) = '1' AND i_wr_en(i/8) = '1') THEN
s_reg <= i_wr_data(i);
END IF;
END LOOP;
END PROCEDURE set_reg;
-- Write access to single trigger signal
PROCEDURE set_trg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT c_wr_mask : IN NATURAL RANGE 0 TO 31;
SIGNAL s_flag : INOUT STD_LOGIC) IS
BEGIN
IF (i_wr_en(c_wr_mask/8) = '1' AND i_wr_data(c_wr_mask) = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_trg;
-- Write access to trigger signal vector
PROCEDURE set_trg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT c_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_flag : INOUT STD_LOGIC_VECTOR) IS
BEGIN
FOR i IN 0 TO 31 LOOP
IF (c_wr_mask(i) = '1') THEN
IF (i_wr_en(i/8) = '1' AND i_wr_data(i) = '1') THEN
s_flag(i) <= '1';
ELSE
s_flag(i) <= '0';
END IF;
END IF;
END LOOP;
END PROCEDURE set_trg;
-- Drive Trigger On Write signal
PROCEDURE set_twr (
i_wr_en : IN STD_LOGIC;
SIGNAL s_flag : OUT STD_LOGIC) IS
BEGIN -- PROCEDURE set_twr
IF (i_wr_en = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_twr;
-- Drive Trigger On Read signal
PROCEDURE set_trd (
i_rd_en : IN STD_LOGIC;
SIGNAL s_flag : OUT STD_LOGIC) IS
BEGIN -- PROCEDURE set_trd
IF (i_rd_en = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_trd;
-- helper to cast integer to slv
FUNCTION f_reset_cast(number : NATURAL; len : POSITIVE)
RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN STD_LOGIC_VECTOR(to_unsigned(number, len));
END FUNCTION f_reset_cast;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
CONSTANT c_addr_config : INTEGER := 16#0000#;
CONSTANT c_addr_status : INTEGER := 16#0004#;
CONSTANT c_has_read_notifies : BOOLEAN := FALSE;
-----------------------------------------------------------------------------
-- WB interface signals
-----------------------------------------------------------------------------
SIGNAL s_wb_ack : STD_LOGIC;
SIGNAL s_wb_err : STD_LOGIC;
SIGNAL s_wb_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_data : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_int_we : STD_LOGIC_VECTOR(i_wb_sel'RANGE);
SIGNAL s_int_trd : STD_LOGIC;
SIGNAL s_int_twr : STD_LOGIC;
SIGNAL s_int_addr_valid : STD_LOGIC;
SIGNAL s_int_data_rb : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_wb_data : STD_LOGIC_VECTOR(o_wb_data'RANGE);
-----------------------------------------------------------------------------
-- Custom registers
-----------------------------------------------------------------------------
SIGNAL s_reg_config : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00200010";
SIGNAL s_reg_status : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
--* purpose : Wishbone Bus Control
--* type : sequential, rising edge, no reset
wb_ctrl : PROCESS (clk)
BEGIN -- PROCESS wb_ctrl
IF rising_edge(clk) THEN
s_wb_ack <= '0';
s_wb_err <= '0';
s_int_data <= i_wb_data;
s_int_addr <= s_wb_addr;
s_int_we <= (OTHERS => '0');
s_int_trd <= '0';
s_int_twr <= '0';
-- check if anyone requests access
IF (s_wb_ack = '0' AND s_wb_err = '0' AND i_wb_cyc = '1' AND i_wb_stb = '1') THEN
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
IF (i_wb_we = '1') THEN
s_int_we <= i_wb_sel;
s_int_twr <= '1';
ELSE
s_int_trd <= '1';
END IF;
END IF;
s_wb_data <= s_int_data_rb;
END IF;
END PROCESS wb_ctrl;
s_wb_addr <= UNSIGNED(i_wb_addr);
o_wb_data <= s_wb_data;
o_wb_ack <= s_wb_ack;
o_wb_err <= s_wb_err;
o_wb_rty <= '0';
-----------------------------------------------------------------------------
-- WB address validation
WITH to_integer(s_wb_addr) SELECT
s_int_addr_valid <=
'1' WHEN c_addr_config,
'1' WHEN c_addr_status,
'0' WHEN OTHERS;
-----------------------------------------------------------------------------
--* purpose : register access
--* type : sequential, rising edge, high active synchronous reset
reg_access : PROCESS (clk)
BEGIN -- PROCESS reg_access
IF rising_edge(clk) THEN
-- default values / clear trigger signals
-- WRITE registers
CASE to_integer(s_int_addr) IS
WHEN c_addr_config => set_reg(s_int_data, s_int_we, x"FFFF007F", s_reg_config);
WHEN OTHERS => NULL;
END CASE;
-- READ-ONLY registers (override WRITE registers)
s_reg_status(31 DOWNTO 0) <= i_status;
END IF;
END PROCESS reg_access;
-----------------------------------------------------------------------------
-- WB output data multiplexer
WITH to_integer(s_wb_addr) SELECT
s_int_data_rb <=
s_reg_config AND x"FFFF007F" WHEN c_addr_config,
s_reg_status AND x"FFFFFFFF" WHEN c_addr_status,
(OTHERS => '0') WHEN OTHERS;
-----------------------------------------------------------------------------
-- output mappings
o_dev_addr <= s_reg_config(6 DOWNTO 0);
o_clk_div <= s_reg_config(31 DOWNTO 16);
END ARCHITECTURE rtl;
| mit | 5be22bddcc2e1d9fef77b9cc35cf466c | 0.466625 | 3.723618 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/c1571_drive.vhd | 1 | 12,972 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity c1571_drive is
generic (
g_big_endian : boolean;
g_audio_tag : std_logic_vector(7 downto 0) := X"01";
g_floppy_tag : std_logic_vector(7 downto 0) := X"02";
g_disk_tag : std_logic_vector(7 downto 0) := X"03";
g_cpu_tag : std_logic_vector(7 downto 0) := X"04";
g_audio : boolean := true;
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
drive_stop : in std_logic := '0';
-- timing
tick_16MHz : in std_logic;
tick_4MHz : in std_logic;
tick_1kHz : in std_logic;
-- slave port on io bus
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic;
-- master port on memory bus
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
fast_clk_o : out std_logic; -- open drain
fast_clk_i : in std_logic;
iec_reset_n : in std_logic := '1';
c64_reset_n : in std_logic := '1';
-- Debug port
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
-- LED
act_led_n : out std_logic;
motor_led_n : out std_logic;
dirty_led_n : out std_logic;
-- audio out
audio_sample : out signed(12 downto 0) );
end c1571_drive;
architecture structural of c1571_drive is
signal tick_16M_i : std_logic;
signal cia_rising : std_logic;
signal cpu_clock_en : std_logic;
signal iec_reset_o : std_logic;
signal do_track_out : std_logic;
signal do_track_in : std_logic;
signal do_head_bang : std_logic;
signal en_hum : std_logic;
signal en_slip : std_logic;
signal use_c64_reset : std_logic;
signal floppy_inserted : std_logic := '0';
signal force_ready : std_logic;
signal bank_is_ram : std_logic_vector(7 downto 1);
signal two_MHz : std_logic;
signal power : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal side : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal track : unsigned(6 downto 0);
signal drive_address : std_logic_vector(1 downto 0) := "00";
signal write_prot_n : std_logic := '1';
signal disk_change_n : std_logic := '1';
signal rdy_n : std_logic := '1';
signal track_0 : std_logic := '0';
signal drv_reset : std_logic := '1';
signal disk_rdata : std_logic_vector(7 downto 0);
signal disk_wdata : std_logic_vector(7 downto 0);
signal drive_stop_i : std_logic;
signal stop_on_freeze : std_logic;
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_param : t_io_req;
signal io_resp_param : t_io_resp;
signal io_req_dirty : t_io_req;
signal io_resp_dirty : t_io_resp;
signal io_req_wd : t_io_req;
signal io_resp_wd : t_io_resp;
signal mem_req_cpu : t_mem_req;
signal mem_resp_cpu : t_mem_resp;
signal mem_req_flop : t_mem_req;
signal mem_resp_flop : t_mem_resp;
signal mem_req_snd : t_mem_req := c_mem_req_init;
signal mem_resp_snd : t_mem_resp;
signal mem_req_disk : t_mem_req;
signal mem_resp_disk : t_mem_resp;
signal mem_req_8 : t_mem_req := c_mem_req_init;
signal mem_resp_8 : t_mem_resp;
signal mem_busy : std_logic;
signal count : unsigned(7 downto 0) := X"00";
signal led_intensity : unsigned(1 downto 0);
begin
i_splitter: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 4
)
port map(
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_dirty,
reqs(2) => io_req_param,
reqs(3) => io_req_wd,
resps(0) => io_resp_regs,
resps(1) => io_resp_dirty,
resps(2) => io_resp_param,
resps(3) => io_resp_wd
);
i_timing: entity work.c1541_timing
port map (
clock => clock,
reset => reset,
tick_4MHz => tick_4MHz,
two_MHz_mode => two_MHz,
mem_busy => mem_busy,
use_c64_reset=> use_c64_reset,
c64_reset_n => c64_reset_n,
iec_reset_n => iec_reset_n,
iec_reset_o => iec_reset_o,
power => power,
drive_stop => drive_stop_i,
cia_rising => cia_rising,
cpu_clock_en => cpu_clock_en ); -- 1 MHz or 2 MHz
drive_stop_i <= drive_stop and stop_on_freeze;
tick_16M_i <= tick_16MHz and not drive_stop_i;
i_cpu: entity work.cpu_part_1571
generic map (
g_cpu_tag => g_cpu_tag,
g_disk_tag => g_disk_tag,
g_ram_base => g_ram_base )
port map (
clock => clock,
falling => cpu_clock_en,
rising => cia_rising,
reset => drv_reset,
tick_1kHz => tick_1kHz,
tick_4MHz => tick_4MHz,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
fast_clk_o => fast_clk_o, -- open drain
fast_clk_i => fast_clk_i,
-- trace data
debug_data => debug_data,
debug_valid => debug_valid,
-- configuration
-- bank_is_ram => bank_is_ram,
-- memory interface
mem_req_cpu => mem_req_cpu,
mem_resp_cpu => mem_resp_cpu,
mem_req_disk => mem_req_disk,
mem_resp_disk => mem_resp_disk,
mem_busy => mem_busy,
-- i/o interface to wd177x
io_req => io_req_wd,
io_resp => io_resp_wd,
io_irq => io_irq,
-- drive pins
power => power,
drive_address => drive_address,
write_prot_n => write_prot_n,
motor_on => motor_on,
mode => mode,
step => step,
side => side,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
two_MHz => two_MHz,
rdy_n => rdy_n,
disk_change_n => disk_change_n,
track_0 => track_0,
drv_rdata => disk_rdata,
drv_wdata => disk_wdata,
-- other
act_led => act_led_n );
rdy_n <= not (motor_on and floppy_inserted) and not force_ready; -- should have a delay
i_flop: entity work.floppy
generic map (
g_big_endian => g_big_endian,
g_tag => g_floppy_tag )
port map (
clock => clock,
reset => drv_reset,
tick_16MHz => tick_16M_i,
-- signals from MOS 6522 VIA
stepper_en => motor_on,
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
side => side,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
read_data => disk_rdata,
write_data => disk_wdata,
track => track,
track_is_0 => track_0,
---
io_req_param => io_req_param,
io_resp_param => io_resp_param,
io_req_dirty => io_req_dirty,
io_resp_dirty => io_resp_dirty,
---
floppy_inserted => floppy_inserted,
do_track_out => do_track_out,
do_track_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
dirty_led_n => dirty_led_n,
---
mem_req => mem_req_flop,
mem_resp => mem_resp_flop );
r_snd: if g_audio generate
i_snd: entity work.floppy_sound
generic map (
g_tag => g_audio_tag,
sound_base => g_audio_base(26 downto 15),
motor_hum_addr => X"0000",
flop_slip_addr => X"1200",
track_in_addr => X"2400",
track_out_addr => X"2C00",
head_bang_addr => X"3480",
motor_len => 4410,
track_in_len => X"0800", -- ~100 ms;
track_out_len => X"0880", -- ~100 ms;
head_bang_len => X"0880" ) -- ~100 ms;
port map (
clock => clock,
reset => drv_reset,
tick_4MHz => tick_4MHz,
do_trk_out => do_track_out,
do_trk_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
-- memory interface
mem_req => mem_req_snd,
mem_resp => mem_resp_snd,
-- audio
sample_out => audio_sample );
end generate;
i_regs: entity work.drive_registers
port map (
clock => clock,
reset => reset,
tick_1kHz => tick_1kHz,
io_req => io_req_regs,
io_resp => io_resp_regs,
iec_reset_o => iec_reset_o,
use_c64_reset => use_c64_reset,
power => power,
drv_reset => drv_reset,
drive_address => drive_address,
floppy_inserted => floppy_inserted,
disk_change_n => disk_change_n,
force_ready => force_ready,
write_prot_n => write_prot_n,
bank_is_ram => bank_is_ram,
stop_on_freeze => stop_on_freeze,
track => track,
side => side,
mode => mode,
motor_on => motor_on );
-- memory arbitration
i_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 4,
g_registered => false )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_flop,
reqs(1) => mem_req_cpu,
reqs(2) => mem_req_snd,
reqs(3) => mem_req_disk,
resps(0) => mem_resp_flop,
resps(1) => mem_resp_cpu,
resps(2) => mem_resp_snd,
resps(3) => mem_resp_disk,
req => mem_req_8,
resp => mem_resp_8 );
i_conv32: entity work.mem_to_mem32(route_through)
generic map (
g_big_endian => g_big_endian )
port map(
clock => clock,
reset => reset,
mem_req_8 => mem_req_8,
mem_resp_8 => mem_resp_8,
mem_req_32 => mem_req,
mem_resp_32 => mem_resp );
process(clock)
variable led_int : unsigned(7 downto 0);
begin
if rising_edge(clock) then
count <= count + 1;
if count=X"00" then
motor_led_n <= '0'; -- on
end if;
led_int := led_intensity & led_intensity & led_intensity & led_intensity;
if count=led_int then
motor_led_n <= '1'; -- off
end if;
end if;
end process;
led_intensity <= "00" when power='0' else
"01" when floppy_inserted='0' else
"10" when motor_on='0' else
"11";
end architecture;
| gpl-3.0 | a23697691cb4127485dc52091a0ced1b | 0.452205 | 3.437202 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_bfm/iec_bus_bfm.vhd | 1 | 20,279 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package iec_bus_bfm_pkg is
type t_iec_bus_bfm_object;
type p_iec_bus_bfm_object is access t_iec_bus_bfm_object;
type t_iec_status is (ok, no_devices, no_response, timeout, no_eoi_ack);
type t_iec_state is (idle, talker, listener);
type t_iec_command is (none, send_atn, send_msg, atn_to_listen, send_drf);
type t_iec_data is array(natural range <>) of std_logic_vector(7 downto 0);
type t_iec_message is record
data : t_iec_data(0 to 256);
len : integer;
end record;
type t_iec_to_bfm is
record
command : t_iec_command;
end record;
type t_iec_from_bfm is
record
busy : boolean;
end record;
constant c_iec_to_bfm_init : t_iec_to_bfm := (
command => none );
constant c_iec_from_bfm_init : t_iec_from_bfm := (
busy => false );
type t_iec_bus_bfm_object is record
next_bfm : p_iec_bus_bfm_object;
name1 : string(1 to 256);
name2 : string(1 to 256);
-- interface to the user
status : t_iec_status;
state : t_iec_state;
stopped : boolean;
sample_time : time;
-- buffer
msg_buf : t_iec_message;
-- internal to bfm
to_bfm : t_iec_to_bfm;
-- internal from bfm
from_bfm : t_iec_from_bfm;
end record;
constant c_atn_to_ckl : time := 5 us;
constant c_atn_resp_max : time := 1000 us;
constant c_non_eoi : time := 40 us;
constant c_clk_low : time := 50 us;
constant c_clk_high : time := 50 us;
constant c_frame_hs_max : time := 1000 us;
constant c_frame_release : time := 20 us;
constant c_byte_to_byte : time := 100 us;
constant c_eoi_min : time := 200 us;
constant c_eoi : time := 500 us; -- was 250
constant c_eoi_hold : time := 60 us;
constant c_tlkr_resp_dly : time := 60 us; -- max
constant c_talk_atn_rel : time := 30 us;
constant c_talk_atn_ack : time := 250 us; -- ?
constant c_fast_serial : time := 10 us;
------------------------------------------------------------------------------------
shared variable iec_bus_bfms : p_iec_bus_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_iec_bus_bfm(name1, name2 : string; variable pntr: inout p_iec_bus_bfm_object);
procedure bind_iec_bus_bfm(named : string; variable pntr: inout p_iec_bus_bfm_object);
------------------------------------------------------------------------------------
procedure iec_stop(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_talk(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_listen(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_drf(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_send_atn(variable bfm : inout p_iec_bus_bfm_object;
byte : std_logic_vector(7 downto 0);
atn_off : boolean := false);
procedure iec_turnaround(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: t_iec_message);
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: string);
procedure iec_get_message(variable bfm : inout p_iec_bus_bfm_object;
variable msg : inout t_iec_message);
procedure iec_print_message(variable msg : inout t_iec_message);
end iec_bus_bfm_pkg;
package body iec_bus_bfm_pkg is
procedure register_iec_bus_bfm(name1, name2 : string;
variable pntr : inout p_iec_bus_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_iec_bus_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name1(name1'range) := name1;
pntr.name2(name2'range) := name2;
pntr.status := ok;
pntr.state := idle;
pntr.stopped := false; -- active;
pntr.sample_time := 1 us;
pntr.to_bfm := c_iec_to_bfm_init;
pntr.from_bfm := c_iec_from_bfm_init;
-- add this pointer to the head of the linked list
if iec_bus_bfms = null then -- first entry
iec_bus_bfms := pntr;
else -- insert new entry
pntr.next_bfm := iec_bus_bfms;
iec_bus_bfms := pntr;
end if;
end register_iec_bus_bfm;
procedure bind_iec_bus_bfm(named : string;
variable pntr : inout p_iec_bus_bfm_object) is
variable p : p_iec_bus_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := iec_bus_bfms; -- start at the root
L1: while p /= null loop
if p.name1(named'range) = named or p.name2(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_iec_bus_bfm;
------------------------------------------------------------------------------
procedure iec_stop(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.stopped := true;
end procedure;
procedure iec_talk(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.state := talker;
end procedure;
procedure iec_listen(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.state := listener;
end procedure;
procedure iec_send_atn(variable bfm : inout p_iec_bus_bfm_object;
byte : std_logic_vector(7 downto 0);
atn_off : boolean := false) is
begin
bfm.msg_buf.data(0) := byte;
bfm.msg_buf.len := 1;
if atn_off then
bfm.msg_buf.data(1) := X"01";
else
bfm.msg_buf.data(1) := X"00";
end if;
bfm.to_bfm.command := send_atn;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_turnaround(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.to_bfm.command := atn_to_listen;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_drf(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.to_bfm.command := send_drf;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: t_iec_message) is
begin
bfm.msg_buf := msg;
bfm.to_bfm.command := send_msg;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: string) is
variable leng : integer;
begin
leng := msg'length;
for i in 1 to leng loop
bfm.msg_buf.data(i-1) := std_logic_vector(to_unsigned(character'pos(msg(i)), 8));
end loop;
bfm.msg_buf.len := leng;
iec_send_message(bfm, bfm.msg_buf);
end procedure;
procedure iec_get_message(variable bfm : inout p_iec_bus_bfm_object;
variable msg : inout t_iec_message) is
begin
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.state = listener loop
wait for bfm.sample_time;
end loop;
msg := bfm.msg_buf;
end procedure;
procedure iec_print_message(variable msg : inout t_iec_message) is
variable L : line;
variable c : character;
begin
for i in 0 to msg.len-1 loop
c := character'val(to_integer(unsigned(msg.data(i))));
write(L, c);
end loop;
writeline(output, L);
end procedure;
end;
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iec_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity iec_bus_bfm is
generic (g_given_name : string := "iec_bfm");
port (
iec_clock : inout std_logic;
iec_data : inout std_logic;
iec_atn : inout std_logic;
iec_srq : inout std_logic );
end entity;
architecture bfm of iec_bus_bfm is
shared variable this : p_iec_bus_bfm_object := null;
signal bound : boolean := false;
signal clk_i : std_logic;
signal clk_o : std_logic;
signal data_i : std_logic;
signal data_o : std_logic;
signal atn_i : std_logic;
signal atn_o : std_logic;
signal srq_i : std_logic;
signal srq_o : std_logic;
signal fast_byte : std_logic_vector(7 downto 0) := X"00";
signal fast_byte_available : boolean;
signal fast_byte_reset : boolean;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_iec_bus_bfm(iec_bus_bfm'path_name, g_given_name, this);
bound <= true;
wait;
end process;
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
srq_i <= iec_srq and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
iec_srq <= '0' when srq_o='0' else 'H';
-- |<--------- Byte sent under attention (to devices) ------------>|
--
-- ___ ____ _____ _____
-- ATN |________________________________________________________|
-- : :
-- ___ ______ ________ ___ ___ ___ ___ ___ ___ ___ ___ :
-- CLK : |_____| |_| |_| |_| |_| |_| |_| |_| |_| |______________ _____
-- : : : : :
-- : Tat : :Th: Tne : : Tf : Tr :
-- ____ ________ : : :___________________________________:____:
-- DATA ___|\\\\\__:__| |__||__||__||__||__||__||__||__| |_________ _____
-- : 0 1 2 3 4 5 6 7 :
-- : LSB MSB :
-- : : :
-- : : Data Valid Listener: Data Accepted
-- : Listener READY-FOR-DATA
protocol: process
procedure do_send_atn is
begin
atn_o <= '0';
wait for c_atn_to_ckl;
clk_o <= '0';
if data_i='1' then
wait until data_i='0' for c_atn_resp_max;
end if;
if data_i='1' then
this.status := no_devices;
return;
end if;
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
wait for c_non_eoi;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= this.msg_buf.data(0)(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
wait for c_frame_release;
if this.msg_buf.data(1)(0) = '1' then
atn_o <= '1';
end if;
end procedure;
procedure send_byte(byte : std_logic_vector(7 downto 0)) is
begin
atn_o <= '1';
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
wait for c_non_eoi;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= byte(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
wait for c_byte_to_byte;
end procedure;
procedure end_handshake(byte : std_logic_vector(7 downto 0)) is
begin
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
-- wait for c_eoi;
-- data_o <= '0';
-- wait for c_eoi_hold;
-- data_o <= '1';
wait until data_i='0' for c_eoi; -- wait for 250 �s to see that listener has acked eoi
if data_i='1' then
this.status := no_eoi_ack;
return;
end if;
wait until data_i='1'; -- wait for listener to be ready again
wait for c_tlkr_resp_dly;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= byte(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
wait for c_byte_to_byte;
clk_o <= '1';
end procedure;
procedure do_send_drf is
begin
for i in 0 to 7 loop
srq_o <= '0';
wait for c_fast_serial;
srq_o <= '1';
wait for c_fast_serial;
end loop;
end procedure;
procedure talk_atn_turnaround is
begin
report "Start ATN Turnaround.";
atn_o <= '1';
wait for c_talk_atn_rel;
clk_o <= '1';
data_o <= '0';
wait for c_talk_atn_rel;
if clk_i /= '0' then
wait until clk_i = '0';
end if;
report "We are now listener.";
this.state := listener;
this.msg_buf.len := 0; -- clear buffer for incoming data
end procedure;
procedure receive_byte is
variable b : std_logic_vector(7 downto 0);
variable eoi : boolean;
-- variable c : character;
-- variable L : LINE;
begin
eoi := false;
if clk_i='0' then
wait until clk_i='1';
end if;
fast_byte_reset <= true;
wait for c_clk_low; -- dummy
data_o <= '1';
fast_byte_reset <= false;
-- check for end of message handshake (data pulses low after >200 �s for >60 �s)
wait until clk_i = '0' for c_eoi_min;
if clk_i='1' then -- eoi timeout
eoi := true;
-- ack eoi
data_o <= '0';
wait for c_eoi_hold;
data_o <= '1';
end if;
L1: for i in 0 to 7 loop
wait until clk_i='1' or fast_byte_available;
if fast_byte_available then
b := fast_byte;
exit L1;
end if;
b(i) := data_i;
end loop;
if not fast_byte_available then
wait until clk_i='0';
else
wait for c_fast_serial;
end if;
this.msg_buf.data(this.msg_buf.len) := b;
this.msg_buf.len := this.msg_buf.len + 1;
if eoi then
this.state := idle;
data_o <= '1';
else
data_o <= '0';
end if;
end procedure;
begin
atn_o <= '1';
data_o <= '1';
clk_o <= '1';
srq_o <= '1';
wait until bound;
while not this.stopped loop
wait for this.sample_time;
case this.to_bfm.command is
when none =>
null;
when send_atn =>
this.from_bfm.busy := true;
do_send_atn;
this.from_bfm.busy := false;
when send_msg =>
this.from_bfm.busy := true;
if this.msg_buf.len > 1 then
L1: for i in 0 to this.msg_buf.len-2 loop
send_byte(this.msg_buf.data(i));
if this.status /= ok then
exit L1;
end if;
end loop;
end if;
assert this.status = ok
report "Sending data message failed."
severity error;
end_handshake(this.msg_buf.data(this.msg_buf.len-1));
assert this.status = ok
report "Sending data message failed (Last Byte)."
severity error;
this.from_bfm.busy := false;
when atn_to_listen =>
this.from_bfm.busy := true;
talk_atn_turnaround;
this.from_bfm.busy := false;
when send_drf =>
this.from_bfm.busy := true;
do_send_drf;
this.from_bfm.busy := false;
end case;
this.to_bfm.command := none;
if this.state = listener then
receive_byte;
end if;
end loop;
wait;
end process;
process(srq_i, fast_byte_reset)
variable cnt : integer := 0;
begin
if fast_byte_reset then
cnt := 7;
fast_byte_available <= false;
elsif rising_edge(srq_i) then
if cnt >= 0 then
fast_byte(cnt) <= data_i;
end if;
if cnt = 0 then
fast_byte_available <= true;
end if;
cnt := cnt - 1;
end if;
end process;
-- if in idle state, and atn_i becomes '0', then become device and listen
-- but that is only needed for devices... (not for the controller)
-- if listener (means that I am addressed), listen to all bytes
-- if end of message is detected, switch back to idle state.
end architecture;
| gpl-3.0 | 6fd9fec48c5d4981a84f4a05410432e2 | 0.44616 | 4.004939 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_source/cpu_wrapper_zpu.vhd | 2 | 6,587 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_wrapper_zpu is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"20";
g_internal_prg : boolean := true;
g_boot_rom : boolean := false;
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
break_o : out std_logic;
error : out std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
irq : in std_logic;
io_req : out t_io_req;
io_resp : in t_io_resp );
end cpu_wrapper_zpu;
architecture logical of cpu_wrapper_zpu is
signal cpu_address : std_logic_vector(26 downto 0);
signal cpu_size : std_logic_vector(1 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_write : std_logic;
signal cpu_instr : std_logic;
signal cpu_req : std_logic;
signal cpu_rack : std_logic;
signal cpu_dack : std_logic;
signal ram_rack : std_logic := '0';
signal ram_dack : std_logic := '0';
signal ram_claimed : std_logic := '0';
signal ram_rdata : std_logic_vector(7 downto 0) := X"FF";
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal break_o_i : std_logic;
signal reset_cpu : std_logic;
type t_state is (idle, busy);
signal state : t_state;
type t_crash_state is (all_ok, flash_on, flash_off);
signal crash_state : t_crash_state := all_ok;
signal delay : integer range 0 to 8388607 := 0;
begin
break_o <= break_o_i;
core: entity work.zpu
generic map (
g_addr_size => cpu_address'length,
g_stack_size => 12,
g_prog_size => 20, -- Program size
g_dont_care => '-') -- Value used to fill the unused bits, can be '-' or '0'
port map (
clock => clock,
reset => reset_cpu,
interrupt_i => irq,
break_o => break_o_i,
mem_address => cpu_address,
mem_instr => cpu_instr,
mem_size => cpu_size,
mem_req => cpu_req,
mem_write => cpu_write,
mem_rack => cpu_rack,
mem_dack => cpu_dack,
mem_wdata => cpu_wdata,
mem_rdata => cpu_rdata );
r_int_ram: if g_internal_prg generate
r_boot: if g_boot_rom generate
i_zpuram: entity work.mem32k
generic map (
simulation => g_simulation )
port map (
clock => clock,
reset => reset,
address => cpu_address,
request => cpu_req,
mwrite => cpu_write,
wdata => cpu_wdata,
rdata => ram_rdata,
rack => ram_rack,
dack => ram_dack,
claimed => ram_claimed );
end generate;
r_noboot: if not g_boot_rom generate
i_zpuram: entity work.mem4k
generic map (
simulation => g_simulation )
port map (
clock => clock,
reset => reset,
address => cpu_address,
request => cpu_req,
mwrite => cpu_write,
wdata => cpu_wdata,
rdata => ram_rdata,
rack => ram_rack,
dack => ram_dack,
claimed => ram_claimed );
end generate;
end generate;
cpu_rdata <= io_resp.data when io_resp.ack='1'
else mem_resp.data when mem_dack='1'
else ram_rdata;
cpu_rack <= io_resp.ack or mem_rack or ram_rack;
cpu_dack <= (io_resp.ack and not cpu_write) or mem_dack or ram_dack;
mem_req.request <= '1' when cpu_req='1' and cpu_address(26)='0' and ram_claimed='0'
else '0';
mem_req.tag <= g_mem_tag;
mem_req.address <= unsigned(cpu_address(25 downto 0));
mem_req.read_writen <= not cpu_write;
mem_req.data <= cpu_wdata;
mem_req.size <= "00"; -- to be optimized
mem_rack <= '1' when mem_resp.rack_tag = g_mem_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_mem_tag else '0';
io_req.address(19 downto 0) <= unsigned(cpu_address(19 downto 0));
-- with cpu_address(24) select
-- io_req.address( 1 downto 0) <=
-- unsigned(cpu_address(1 downto 0) xor cpu_size) when '0',
-- unsigned(cpu_address(1 downto 0)) when others;
io_req.data <= cpu_wdata;
p_io: process(clock)
begin
if rising_edge(clock) then
io_req.read <= '0';
io_req.write <= '0';
case state is
when idle =>
if cpu_req='1' and cpu_address(26)='1' then
io_req.read <= not cpu_write;
io_req.write <= cpu_write;
state <= busy;
end if;
when busy =>
if io_resp.ack='1' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
p_crash: process(clock)
begin
if rising_edge(clock) then
case crash_state is
when all_ok =>
reset_cpu <= '0';
error <= '0';
delay <= 6_250_000;
if break_o_i='1' then
reset_cpu <= '1';
crash_state <= flash_on;
end if;
when flash_on =>
reset_cpu <= '1';
error <= '1';
if delay = 0 then
crash_state <= flash_off;
delay <= 6_250_000;
else
delay <= delay - 1;
end if;
when flash_off =>
reset_cpu <= '1';
error <= '0';
if delay = 0 then
crash_state <= flash_on;
delay <= 6_250_000;
else
delay <= delay - 1;
end if;
when others =>
crash_state <= flash_on;
end case;
if reset='1' then
error <= '0';
reset_cpu <= '1';
crash_state <= all_ok;
end if;
end if;
end process;
end logical;
| gpl-3.0 | d89a1dae3cd01fbc8a8d6d557cc5a768 | 0.482465 | 3.474156 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_tester/nios_tester/synthesis/nios_tester.vhd | 1 | 120,216 | -- nios_tester.vhd
-- Generated using ACDS version 18.1 625
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_tester is
port (
audio_in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- audio_in.data
audio_in_valid : in std_logic := '0'; -- .valid
audio_in_ready : out std_logic; -- .ready
audio_out_data : out std_logic_vector(31 downto 0); -- audio_out.data
audio_out_valid : out std_logic; -- .valid
audio_out_ready : in std_logic := '0'; -- .ready
dummy_export : in std_logic := '0'; -- dummy.export
io_ack : in std_logic := '0'; -- io.ack
io_rdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .rdata
io_read : out std_logic; -- .read
io_wdata : out std_logic_vector(7 downto 0); -- .wdata
io_write : out std_logic; -- .write
io_address : out std_logic_vector(19 downto 0); -- .address
io_irq : in std_logic := '0'; -- .irq
io_u2p_ack : in std_logic := '0'; -- io_u2p.ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .rdata
io_u2p_read : out std_logic; -- .read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- .wdata
io_u2p_write : out std_logic; -- .write
io_u2p_address : out std_logic_vector(19 downto 0); -- .address
io_u2p_irq : in std_logic := '0'; -- .irq
jtag0_jtag_tck : out std_logic; -- jtag0.jtag_tck
jtag0_jtag_tms : out std_logic; -- .jtag_tms
jtag0_jtag_tdi : out std_logic; -- .jtag_tdi
jtag0_jtag_tdo : in std_logic := '0'; -- .jtag_tdo
jtag1_jtag_tck : out std_logic; -- jtag1.jtag_tck
jtag1_jtag_tms : out std_logic; -- .jtag_tms
jtag1_jtag_tdi : out std_logic; -- .jtag_tdi
jtag1_jtag_tdo : in std_logic := '0'; -- .jtag_tdo
jtag_in_data : in std_logic_vector(7 downto 0) := (others => '0'); -- jtag_in.data
jtag_in_valid : in std_logic := '0'; -- .valid
jtag_in_ready : out std_logic; -- .ready
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem.mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- .mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- .mem_req_read_writen
mem_mem_req_request : out std_logic; -- .mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- .mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- .mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => '0'); -- .mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => '0'); -- .mem_resp_rack_tag
pio_in_port : in std_logic_vector(31 downto 0) := (others => '0'); -- pio.in_port
pio_out_port : out std_logic_vector(31 downto 0); -- .out_port
spi_MISO : in std_logic := '0'; -- spi.MISO
spi_MOSI : out std_logic; -- .MOSI
spi_SCLK : out std_logic; -- .SCLK
spi_SS_n : out std_logic; -- .SS_n
sys_clock_clk : in std_logic := '0'; -- sys_clock.clk
sys_reset_reset_n : in std_logic := '0' -- sys_reset.reset_n
);
end entity nios_tester;
architecture rtl of nios_tester is
component nios_tester_audio_in_dma is
port (
mm_write_address : out std_logic_vector(25 downto 0); -- address
mm_write_write : out std_logic; -- write
mm_write_byteenable : out std_logic_vector(3 downto 0); -- byteenable
mm_write_writedata : out std_logic_vector(31 downto 0); -- writedata
mm_write_waitrequest : in std_logic := 'X'; -- waitrequest
clock_clk : in std_logic := 'X'; -- clk
reset_n_reset_n : in std_logic := 'X'; -- reset_n
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
csr_write : in std_logic := 'X'; -- write
csr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_read : in std_logic := 'X'; -- read
csr_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
descriptor_slave_write : in std_logic := 'X'; -- write
descriptor_slave_waitrequest : out std_logic; -- waitrequest
descriptor_slave_writedata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
descriptor_slave_byteenable : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
csr_irq_irq : out std_logic; -- irq
st_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
st_sink_valid : in std_logic := 'X'; -- valid
st_sink_ready : out std_logic -- ready
);
end component nios_tester_audio_in_dma;
component nios_tester_audio_out_dma is
port (
mm_read_address : out std_logic_vector(25 downto 0); -- address
mm_read_read : out std_logic; -- read
mm_read_byteenable : out std_logic_vector(3 downto 0); -- byteenable
mm_read_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
mm_read_waitrequest : in std_logic := 'X'; -- waitrequest
mm_read_readdatavalid : in std_logic := 'X'; -- readdatavalid
clock_clk : in std_logic := 'X'; -- clk
reset_n_reset_n : in std_logic := 'X'; -- reset_n
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
csr_write : in std_logic := 'X'; -- write
csr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_read : in std_logic := 'X'; -- read
csr_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
descriptor_slave_write : in std_logic := 'X'; -- write
descriptor_slave_waitrequest : out std_logic; -- waitrequest
descriptor_slave_writedata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
descriptor_slave_byteenable : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
csr_irq_irq : out std_logic; -- irq
st_source_data : out std_logic_vector(31 downto 0); -- data
st_source_valid : out std_logic; -- valid
st_source_ready : in std_logic := 'X' -- ready
);
end component nios_tester_audio_out_dma;
component avalon_to_mem32_bridge is
generic (
g_tag : std_logic_vector(7 downto 0) := "01011011"
);
port (
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
avs_waitrequest : out std_logic; -- waitrequest
avs_readdata : out std_logic_vector(31 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
clock : in std_logic := 'X'; -- clk
mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_req_request : out std_logic; -- mem_req_request
mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X') -- mem_resp_rack_tag
);
end component avalon_to_mem32_bridge;
component avalon_to_io_bridge is
port (
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
avs_ready : out std_logic; -- waitrequest_n
avs_readdata : out std_logic_vector(7 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
clock : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
avs_irq : out std_logic -- irq
);
end component avalon_to_io_bridge;
component jtag_host is
port (
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avs_ready : out std_logic; -- waitrequest_n
avs_readdata : out std_logic_vector(31 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
jtag_tck : out std_logic; -- jtag_tck
jtag_tms : out std_logic; -- jtag_tms
jtag_tdi : out std_logic; -- jtag_tdi
jtag_tdo : in std_logic := 'X' -- jtag_tdo
);
end component jtag_host;
component nios_tester_jtagdebug is
port (
mm_write_address : out std_logic_vector(25 downto 0); -- address
mm_write_write : out std_logic; -- write
mm_write_writedata : out std_logic_vector(7 downto 0); -- writedata
mm_write_waitrequest : in std_logic := 'X'; -- waitrequest
clock_clk : in std_logic := 'X'; -- clk
reset_n_reset_n : in std_logic := 'X'; -- reset_n
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
csr_write : in std_logic := 'X'; -- write
csr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_read : in std_logic := 'X'; -- read
csr_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
descriptor_slave_write : in std_logic := 'X'; -- write
descriptor_slave_waitrequest : out std_logic; -- waitrequest
descriptor_slave_writedata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
descriptor_slave_byteenable : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
csr_irq_irq : out std_logic; -- irq
st_sink_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
st_sink_valid : in std_logic := 'X'; -- valid
st_sink_ready : out std_logic -- ready
);
end component nios_tester_jtagdebug;
component nios_tester_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(31 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(29 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component nios_tester_nios2_gen2_0;
component nios_tester_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X'; -- reset_req
freeze : in std_logic := 'X' -- freeze
);
end component nios_tester_onchip_memory2_0;
component nios_tester_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic := 'X'; -- export
irq : out std_logic -- irq
);
end component nios_tester_pio_0;
component nios_tester_pio_1 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
out_port : out std_logic_vector(31 downto 0) -- export
);
end component nios_tester_pio_1;
component nios_tester_spi_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
data_to_cpu : out std_logic_vector(15 downto 0); -- readdata
mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
read_n : in std_logic := 'X'; -- read_n
spi_select : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic; -- irq
MISO : in std_logic := 'X'; -- export
MOSI : out std_logic; -- export
SCLK : out std_logic; -- export
SS_n : out std_logic -- export
);
end component nios_tester_spi_0;
component nios_tester_mm_interconnect_0 is
port (
clk_0_clk_clk : in std_logic := 'X'; -- clk
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
audio_in_dma_mm_write_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
audio_in_dma_mm_write_waitrequest : out std_logic; -- waitrequest
audio_in_dma_mm_write_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
audio_in_dma_mm_write_write : in std_logic := 'X'; -- write
audio_in_dma_mm_write_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
audio_out_dma_mm_read_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
audio_out_dma_mm_read_waitrequest : out std_logic; -- waitrequest
audio_out_dma_mm_read_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
audio_out_dma_mm_read_read : in std_logic := 'X'; -- read
audio_out_dma_mm_read_readdata : out std_logic_vector(31 downto 0); -- readdata
audio_out_dma_mm_read_readdatavalid : out std_logic; -- readdatavalid
jtagdebug_mm_write_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
jtagdebug_mm_write_waitrequest : out std_logic; -- waitrequest
jtagdebug_mm_write_write : in std_logic := 'X'; -- write
jtagdebug_mm_write_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(29 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
audio_in_dma_csr_address : out std_logic_vector(2 downto 0); -- address
audio_in_dma_csr_write : out std_logic; -- write
audio_in_dma_csr_read : out std_logic; -- read
audio_in_dma_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
audio_in_dma_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
audio_in_dma_csr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
audio_in_dma_descriptor_slave_write : out std_logic; -- write
audio_in_dma_descriptor_slave_writedata : out std_logic_vector(127 downto 0); -- writedata
audio_in_dma_descriptor_slave_byteenable : out std_logic_vector(15 downto 0); -- byteenable
audio_in_dma_descriptor_slave_waitrequest : in std_logic := 'X'; -- waitrequest
audio_out_dma_csr_address : out std_logic_vector(2 downto 0); -- address
audio_out_dma_csr_write : out std_logic; -- write
audio_out_dma_csr_read : out std_logic; -- read
audio_out_dma_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
audio_out_dma_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
audio_out_dma_csr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
audio_out_dma_descriptor_slave_write : out std_logic; -- write
audio_out_dma_descriptor_slave_writedata : out std_logic_vector(127 downto 0); -- writedata
audio_out_dma_descriptor_slave_byteenable : out std_logic_vector(15 downto 0); -- byteenable
audio_out_dma_descriptor_slave_waitrequest : in std_logic := 'X'; -- waitrequest
avalon2mem_0_avalon_slave_0_address : out std_logic_vector(25 downto 0); -- address
avalon2mem_0_avalon_slave_0_write : out std_logic; -- write
avalon2mem_0_avalon_slave_0_read : out std_logic; -- read
avalon2mem_0_avalon_slave_0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
avalon2mem_0_avalon_slave_0_writedata : out std_logic_vector(31 downto 0); -- writedata
avalon2mem_0_avalon_slave_0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
avalon2mem_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
avalon2mem_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
io_bridge_0_avalon_slave_0_address : out std_logic_vector(19 downto 0); -- address
io_bridge_0_avalon_slave_0_write : out std_logic; -- write
io_bridge_0_avalon_slave_0_read : out std_logic; -- read
io_bridge_0_avalon_slave_0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
io_bridge_0_avalon_slave_0_writedata : out std_logic_vector(7 downto 0); -- writedata
io_bridge_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
io_bridge_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
io_bridge_1_avalon_slave_0_address : out std_logic_vector(19 downto 0); -- address
io_bridge_1_avalon_slave_0_write : out std_logic; -- write
io_bridge_1_avalon_slave_0_read : out std_logic; -- read
io_bridge_1_avalon_slave_0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
io_bridge_1_avalon_slave_0_writedata : out std_logic_vector(7 downto 0); -- writedata
io_bridge_1_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
io_bridge_1_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_0_avalon_slave_0_address : out std_logic_vector(7 downto 0); -- address
jtag_0_avalon_slave_0_write : out std_logic; -- write
jtag_0_avalon_slave_0_read : out std_logic; -- read
jtag_0_avalon_slave_0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_0_avalon_slave_0_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
jtag_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_1_avalon_slave_0_address : out std_logic_vector(7 downto 0); -- address
jtag_1_avalon_slave_0_write : out std_logic; -- write
jtag_1_avalon_slave_0_read : out std_logic; -- read
jtag_1_avalon_slave_0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_1_avalon_slave_0_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_1_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
jtag_1_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
jtagdebug_csr_address : out std_logic_vector(2 downto 0); -- address
jtagdebug_csr_write : out std_logic; -- write
jtagdebug_csr_read : out std_logic; -- read
jtagdebug_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtagdebug_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
jtagdebug_csr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
jtagdebug_descriptor_slave_write : out std_logic; -- write
jtagdebug_descriptor_slave_writedata : out std_logic_vector(127 downto 0); -- writedata
jtagdebug_descriptor_slave_byteenable : out std_logic_vector(15 downto 0); -- byteenable
jtagdebug_descriptor_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(8 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
pio_1_s1_address : out std_logic_vector(2 downto 0); -- address
pio_1_s1_write : out std_logic; -- write
pio_1_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_1_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_1_s1_chipselect : out std_logic; -- chipselect
spi_0_spi_control_port_address : out std_logic_vector(2 downto 0); -- address
spi_0_spi_control_port_write : out std_logic; -- write
spi_0_spi_control_port_read : out std_logic; -- read
spi_0_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
spi_0_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata
spi_0_spi_control_port_chipselect : out std_logic -- chipselect
);
end component nios_tester_mm_interconnect_0;
component nios_tester_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
receiver4_irq : in std_logic := 'X'; -- irq
receiver5_irq : in std_logic := 'X'; -- irq
receiver6_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component nios_tester_irq_mapper;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(29 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal audio_out_dma_mm_read_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_out_dma_mm_read_readdata -> audio_out_dma:mm_read_readdata
signal audio_out_dma_mm_read_waitrequest : std_logic; -- mm_interconnect_0:audio_out_dma_mm_read_waitrequest -> audio_out_dma:mm_read_waitrequest
signal audio_out_dma_mm_read_address : std_logic_vector(25 downto 0); -- audio_out_dma:mm_read_address -> mm_interconnect_0:audio_out_dma_mm_read_address
signal audio_out_dma_mm_read_read : std_logic; -- audio_out_dma:mm_read_read -> mm_interconnect_0:audio_out_dma_mm_read_read
signal audio_out_dma_mm_read_byteenable : std_logic_vector(3 downto 0); -- audio_out_dma:mm_read_byteenable -> mm_interconnect_0:audio_out_dma_mm_read_byteenable
signal audio_out_dma_mm_read_readdatavalid : std_logic; -- mm_interconnect_0:audio_out_dma_mm_read_readdatavalid -> audio_out_dma:mm_read_readdatavalid
signal audio_in_dma_mm_write_waitrequest : std_logic; -- mm_interconnect_0:audio_in_dma_mm_write_waitrequest -> audio_in_dma:mm_write_waitrequest
signal audio_in_dma_mm_write_address : std_logic_vector(25 downto 0); -- audio_in_dma:mm_write_address -> mm_interconnect_0:audio_in_dma_mm_write_address
signal audio_in_dma_mm_write_byteenable : std_logic_vector(3 downto 0); -- audio_in_dma:mm_write_byteenable -> mm_interconnect_0:audio_in_dma_mm_write_byteenable
signal audio_in_dma_mm_write_write : std_logic; -- audio_in_dma:mm_write_write -> mm_interconnect_0:audio_in_dma_mm_write_write
signal audio_in_dma_mm_write_writedata : std_logic_vector(31 downto 0); -- audio_in_dma:mm_write_writedata -> mm_interconnect_0:audio_in_dma_mm_write_writedata
signal jtagdebug_mm_write_waitrequest : std_logic; -- mm_interconnect_0:jtagdebug_mm_write_waitrequest -> jtagdebug:mm_write_waitrequest
signal jtagdebug_mm_write_address : std_logic_vector(25 downto 0); -- jtagdebug:mm_write_address -> mm_interconnect_0:jtagdebug_mm_write_address
signal jtagdebug_mm_write_write : std_logic; -- jtagdebug:mm_write_write -> mm_interconnect_0:jtagdebug_mm_write_write
signal jtagdebug_mm_write_writedata : std_logic_vector(7 downto 0); -- jtagdebug:mm_write_writedata -> mm_interconnect_0:jtagdebug_mm_write_writedata
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata : std_logic_vector(7 downto 0); -- io_bridge_1:avs_readdata -> mm_interconnect_0:io_bridge_1_avalon_slave_0_readdata
signal io_bridge_1_avalon_slave_0_waitrequest : std_logic; -- io_bridge_1:avs_ready -> io_bridge_1_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_address : std_logic_vector(19 downto 0); -- mm_interconnect_0:io_bridge_1_avalon_slave_0_address -> io_bridge_1:avs_address
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_read : std_logic; -- mm_interconnect_0:io_bridge_1_avalon_slave_0_read -> io_bridge_1:avs_read
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid : std_logic; -- io_bridge_1:avs_readdatavalid -> mm_interconnect_0:io_bridge_1_avalon_slave_0_readdatavalid
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_write : std_logic; -- mm_interconnect_0:io_bridge_1_avalon_slave_0_write -> io_bridge_1:avs_write
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_0:io_bridge_1_avalon_slave_0_writedata -> io_bridge_1:avs_writedata
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata : std_logic_vector(31 downto 0); -- avalon2mem_0:avs_readdata -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_readdata
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest : std_logic; -- avalon2mem_0:avs_waitrequest -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_address : std_logic_vector(25 downto 0); -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_address -> avalon2mem_0:avs_address
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_read -> avalon2mem_0:avs_read
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_byteenable -> avalon2mem_0:avs_byteenable
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid : std_logic; -- avalon2mem_0:avs_readdatavalid -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_write -> avalon2mem_0:avs_write
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_writedata -> avalon2mem_0:avs_writedata
signal mm_interconnect_0_jtag_0_avalon_slave_0_readdata : std_logic_vector(31 downto 0); -- jtag_0:avs_readdata -> mm_interconnect_0:jtag_0_avalon_slave_0_readdata
signal jtag_0_avalon_slave_0_waitrequest : std_logic; -- jtag_0:avs_ready -> jtag_0_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_jtag_0_avalon_slave_0_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:jtag_0_avalon_slave_0_address -> jtag_0:avs_address
signal mm_interconnect_0_jtag_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:jtag_0_avalon_slave_0_read -> jtag_0:avs_read
signal mm_interconnect_0_jtag_0_avalon_slave_0_readdatavalid : std_logic; -- jtag_0:avs_readdatavalid -> mm_interconnect_0:jtag_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_jtag_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:jtag_0_avalon_slave_0_write -> jtag_0:avs_write
signal mm_interconnect_0_jtag_0_avalon_slave_0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_0_avalon_slave_0_writedata -> jtag_0:avs_writedata
signal mm_interconnect_0_jtag_1_avalon_slave_0_readdata : std_logic_vector(31 downto 0); -- jtag_1:avs_readdata -> mm_interconnect_0:jtag_1_avalon_slave_0_readdata
signal jtag_1_avalon_slave_0_waitrequest : std_logic; -- jtag_1:avs_ready -> jtag_1_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_jtag_1_avalon_slave_0_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:jtag_1_avalon_slave_0_address -> jtag_1:avs_address
signal mm_interconnect_0_jtag_1_avalon_slave_0_read : std_logic; -- mm_interconnect_0:jtag_1_avalon_slave_0_read -> jtag_1:avs_read
signal mm_interconnect_0_jtag_1_avalon_slave_0_readdatavalid : std_logic; -- jtag_1:avs_readdatavalid -> mm_interconnect_0:jtag_1_avalon_slave_0_readdatavalid
signal mm_interconnect_0_jtag_1_avalon_slave_0_write : std_logic; -- mm_interconnect_0:jtag_1_avalon_slave_0_write -> jtag_1:avs_write
signal mm_interconnect_0_jtag_1_avalon_slave_0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_1_avalon_slave_0_writedata -> jtag_1:avs_writedata
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata : std_logic_vector(7 downto 0); -- io_bridge_0:avs_readdata -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdata
signal io_bridge_0_avalon_slave_0_waitrequest : std_logic; -- io_bridge_0:avs_ready -> io_bridge_0_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_address : std_logic_vector(19 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_address -> io_bridge_0:avs_address
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_read -> io_bridge_0:avs_read
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid : std_logic; -- io_bridge_0:avs_readdatavalid -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_write -> io_bridge_0:avs_write
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_writedata -> io_bridge_0:avs_writedata
signal mm_interconnect_0_audio_out_dma_csr_readdata : std_logic_vector(31 downto 0); -- audio_out_dma:csr_readdata -> mm_interconnect_0:audio_out_dma_csr_readdata
signal mm_interconnect_0_audio_out_dma_csr_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:audio_out_dma_csr_address -> audio_out_dma:csr_address
signal mm_interconnect_0_audio_out_dma_csr_read : std_logic; -- mm_interconnect_0:audio_out_dma_csr_read -> audio_out_dma:csr_read
signal mm_interconnect_0_audio_out_dma_csr_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:audio_out_dma_csr_byteenable -> audio_out_dma:csr_byteenable
signal mm_interconnect_0_audio_out_dma_csr_write : std_logic; -- mm_interconnect_0:audio_out_dma_csr_write -> audio_out_dma:csr_write
signal mm_interconnect_0_audio_out_dma_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_out_dma_csr_writedata -> audio_out_dma:csr_writedata
signal mm_interconnect_0_audio_in_dma_csr_readdata : std_logic_vector(31 downto 0); -- audio_in_dma:csr_readdata -> mm_interconnect_0:audio_in_dma_csr_readdata
signal mm_interconnect_0_audio_in_dma_csr_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:audio_in_dma_csr_address -> audio_in_dma:csr_address
signal mm_interconnect_0_audio_in_dma_csr_read : std_logic; -- mm_interconnect_0:audio_in_dma_csr_read -> audio_in_dma:csr_read
signal mm_interconnect_0_audio_in_dma_csr_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:audio_in_dma_csr_byteenable -> audio_in_dma:csr_byteenable
signal mm_interconnect_0_audio_in_dma_csr_write : std_logic; -- mm_interconnect_0:audio_in_dma_csr_write -> audio_in_dma:csr_write
signal mm_interconnect_0_audio_in_dma_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_in_dma_csr_writedata -> audio_in_dma:csr_writedata
signal mm_interconnect_0_jtagdebug_csr_readdata : std_logic_vector(31 downto 0); -- jtagdebug:csr_readdata -> mm_interconnect_0:jtagdebug_csr_readdata
signal mm_interconnect_0_jtagdebug_csr_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:jtagdebug_csr_address -> jtagdebug:csr_address
signal mm_interconnect_0_jtagdebug_csr_read : std_logic; -- mm_interconnect_0:jtagdebug_csr_read -> jtagdebug:csr_read
signal mm_interconnect_0_jtagdebug_csr_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:jtagdebug_csr_byteenable -> jtagdebug:csr_byteenable
signal mm_interconnect_0_jtagdebug_csr_write : std_logic; -- mm_interconnect_0:jtagdebug_csr_write -> jtagdebug:csr_write
signal mm_interconnect_0_jtagdebug_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtagdebug_csr_writedata -> jtagdebug:csr_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_audio_out_dma_descriptor_slave_waitrequest : std_logic; -- audio_out_dma:descriptor_slave_waitrequest -> mm_interconnect_0:audio_out_dma_descriptor_slave_waitrequest
signal mm_interconnect_0_audio_out_dma_descriptor_slave_byteenable : std_logic_vector(15 downto 0); -- mm_interconnect_0:audio_out_dma_descriptor_slave_byteenable -> audio_out_dma:descriptor_slave_byteenable
signal mm_interconnect_0_audio_out_dma_descriptor_slave_write : std_logic; -- mm_interconnect_0:audio_out_dma_descriptor_slave_write -> audio_out_dma:descriptor_slave_write
signal mm_interconnect_0_audio_out_dma_descriptor_slave_writedata : std_logic_vector(127 downto 0); -- mm_interconnect_0:audio_out_dma_descriptor_slave_writedata -> audio_out_dma:descriptor_slave_writedata
signal mm_interconnect_0_audio_in_dma_descriptor_slave_waitrequest : std_logic; -- audio_in_dma:descriptor_slave_waitrequest -> mm_interconnect_0:audio_in_dma_descriptor_slave_waitrequest
signal mm_interconnect_0_audio_in_dma_descriptor_slave_byteenable : std_logic_vector(15 downto 0); -- mm_interconnect_0:audio_in_dma_descriptor_slave_byteenable -> audio_in_dma:descriptor_slave_byteenable
signal mm_interconnect_0_audio_in_dma_descriptor_slave_write : std_logic; -- mm_interconnect_0:audio_in_dma_descriptor_slave_write -> audio_in_dma:descriptor_slave_write
signal mm_interconnect_0_audio_in_dma_descriptor_slave_writedata : std_logic_vector(127 downto 0); -- mm_interconnect_0:audio_in_dma_descriptor_slave_writedata -> audio_in_dma:descriptor_slave_writedata
signal mm_interconnect_0_jtagdebug_descriptor_slave_waitrequest : std_logic; -- jtagdebug:descriptor_slave_waitrequest -> mm_interconnect_0:jtagdebug_descriptor_slave_waitrequest
signal mm_interconnect_0_jtagdebug_descriptor_slave_byteenable : std_logic_vector(15 downto 0); -- mm_interconnect_0:jtagdebug_descriptor_slave_byteenable -> jtagdebug:descriptor_slave_byteenable
signal mm_interconnect_0_jtagdebug_descriptor_slave_write : std_logic; -- mm_interconnect_0:jtagdebug_descriptor_slave_write -> jtagdebug:descriptor_slave_write
signal mm_interconnect_0_jtagdebug_descriptor_slave_writedata : std_logic_vector(127 downto 0); -- mm_interconnect_0:jtagdebug_descriptor_slave_writedata -> jtagdebug:descriptor_slave_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_pio_1_s1_chipselect : std_logic; -- mm_interconnect_0:pio_1_s1_chipselect -> pio_1:chipselect
signal mm_interconnect_0_pio_1_s1_readdata : std_logic_vector(31 downto 0); -- pio_1:readdata -> mm_interconnect_0:pio_1_s1_readdata
signal mm_interconnect_0_pio_1_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:pio_1_s1_address -> pio_1:address
signal mm_interconnect_0_pio_1_s1_write : std_logic; -- mm_interconnect_0:pio_1_s1_write -> mm_interconnect_0_pio_1_s1_write:in
signal mm_interconnect_0_pio_1_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_1_s1_writedata -> pio_1:writedata
signal mm_interconnect_0_spi_0_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_0_spi_control_port_chipselect -> spi_0:spi_select
signal mm_interconnect_0_spi_0_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_0:data_to_cpu -> mm_interconnect_0:spi_0_spi_control_port_readdata
signal mm_interconnect_0_spi_0_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_0_spi_control_port_address -> spi_0:mem_addr
signal mm_interconnect_0_spi_0_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_0_spi_control_port_read -> mm_interconnect_0_spi_0_spi_control_port_read:in
signal mm_interconnect_0_spi_0_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_0_spi_control_port_write -> mm_interconnect_0_spi_0_spi_control_port_write:in
signal mm_interconnect_0_spi_0_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_0_spi_control_port_writedata -> spi_0:data_from_cpu
signal irq_mapper_receiver0_irq : std_logic; -- audio_out_dma:csr_irq_irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- audio_in_dma:csr_irq_irq -> irq_mapper:receiver1_irq
signal irq_mapper_receiver2_irq : std_logic; -- jtagdebug:csr_irq_irq -> irq_mapper:receiver2_irq
signal irq_mapper_receiver3_irq : std_logic; -- io_bridge_1:avs_irq -> irq_mapper:receiver3_irq
signal irq_mapper_receiver4_irq : std_logic; -- pio_0:irq -> irq_mapper:receiver4_irq
signal irq_mapper_receiver5_irq : std_logic; -- spi_0:irq -> irq_mapper:receiver5_irq
signal irq_mapper_receiver6_irq : std_logic; -- io_bridge_0:avs_irq -> irq_mapper:receiver6_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [avalon2mem_0:reset, io_bridge_0:reset, io_bridge_1:reset, irq_mapper:reset, jtag_0:reset, jtag_1:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal sys_reset_reset_n_ports_inv : std_logic; -- sys_reset_reset_n:inv -> rst_controller:reset_in0
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_inv : std_logic; -- io_bridge_1_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:io_bridge_1_avalon_slave_0_waitrequest
signal mm_interconnect_0_jtag_0_avalon_slave_0_inv : std_logic; -- jtag_0_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:jtag_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_jtag_1_avalon_slave_0_inv : std_logic; -- jtag_1_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:jtag_1_avalon_slave_0_waitrequest
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_inv : std_logic; -- io_bridge_0_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:io_bridge_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_pio_1_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_1_s1_write:inv -> pio_1:write_n
signal mm_interconnect_0_spi_0_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_0_spi_control_port_read:inv -> spi_0:read_n
signal mm_interconnect_0_spi_0_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_0_spi_control_port_write:inv -> spi_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [audio_in_dma:reset_n_reset_n, audio_out_dma:reset_n_reset_n, jtagdebug:reset_n_reset_n, nios2_gen2_0:reset_n, pio_0:reset_n, pio_1:reset_n, spi_0:reset_n]
begin
audio_in_dma : component nios_tester_audio_in_dma
port map (
mm_write_address => audio_in_dma_mm_write_address, -- mm_write.address
mm_write_write => audio_in_dma_mm_write_write, -- .write
mm_write_byteenable => audio_in_dma_mm_write_byteenable, -- .byteenable
mm_write_writedata => audio_in_dma_mm_write_writedata, -- .writedata
mm_write_waitrequest => audio_in_dma_mm_write_waitrequest, -- .waitrequest
clock_clk => sys_clock_clk, -- clock.clk
reset_n_reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
csr_writedata => mm_interconnect_0_audio_in_dma_csr_writedata, -- csr.writedata
csr_write => mm_interconnect_0_audio_in_dma_csr_write, -- .write
csr_byteenable => mm_interconnect_0_audio_in_dma_csr_byteenable, -- .byteenable
csr_readdata => mm_interconnect_0_audio_in_dma_csr_readdata, -- .readdata
csr_read => mm_interconnect_0_audio_in_dma_csr_read, -- .read
csr_address => mm_interconnect_0_audio_in_dma_csr_address, -- .address
descriptor_slave_write => mm_interconnect_0_audio_in_dma_descriptor_slave_write, -- descriptor_slave.write
descriptor_slave_waitrequest => mm_interconnect_0_audio_in_dma_descriptor_slave_waitrequest, -- .waitrequest
descriptor_slave_writedata => mm_interconnect_0_audio_in_dma_descriptor_slave_writedata, -- .writedata
descriptor_slave_byteenable => mm_interconnect_0_audio_in_dma_descriptor_slave_byteenable, -- .byteenable
csr_irq_irq => irq_mapper_receiver1_irq, -- csr_irq.irq
st_sink_data => audio_in_data, -- st_sink.data
st_sink_valid => audio_in_valid, -- .valid
st_sink_ready => audio_in_ready -- .ready
);
audio_out_dma : component nios_tester_audio_out_dma
port map (
mm_read_address => audio_out_dma_mm_read_address, -- mm_read.address
mm_read_read => audio_out_dma_mm_read_read, -- .read
mm_read_byteenable => audio_out_dma_mm_read_byteenable, -- .byteenable
mm_read_readdata => audio_out_dma_mm_read_readdata, -- .readdata
mm_read_waitrequest => audio_out_dma_mm_read_waitrequest, -- .waitrequest
mm_read_readdatavalid => audio_out_dma_mm_read_readdatavalid, -- .readdatavalid
clock_clk => sys_clock_clk, -- clock.clk
reset_n_reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
csr_writedata => mm_interconnect_0_audio_out_dma_csr_writedata, -- csr.writedata
csr_write => mm_interconnect_0_audio_out_dma_csr_write, -- .write
csr_byteenable => mm_interconnect_0_audio_out_dma_csr_byteenable, -- .byteenable
csr_readdata => mm_interconnect_0_audio_out_dma_csr_readdata, -- .readdata
csr_read => mm_interconnect_0_audio_out_dma_csr_read, -- .read
csr_address => mm_interconnect_0_audio_out_dma_csr_address, -- .address
descriptor_slave_write => mm_interconnect_0_audio_out_dma_descriptor_slave_write, -- descriptor_slave.write
descriptor_slave_waitrequest => mm_interconnect_0_audio_out_dma_descriptor_slave_waitrequest, -- .waitrequest
descriptor_slave_writedata => mm_interconnect_0_audio_out_dma_descriptor_slave_writedata, -- .writedata
descriptor_slave_byteenable => mm_interconnect_0_audio_out_dma_descriptor_slave_byteenable, -- .byteenable
csr_irq_irq => irq_mapper_receiver0_irq, -- csr_irq.irq
st_source_data => audio_out_data, -- st_source.data
st_source_valid => audio_out_valid, -- .valid
st_source_ready => audio_out_ready -- .ready
);
avalon2mem_0 : component avalon_to_mem32_bridge
generic map (
g_tag => "01011011"
)
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_avalon2mem_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_avalon2mem_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_avalon2mem_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata, -- .writedata
avs_byteenable => mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable, -- .byteenable
avs_waitrequest => mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest, -- .waitrequest
avs_readdata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => sys_clock_clk, -- clock.clk
mem_req_address => mem_mem_req_address, -- mem.mem_req_address
mem_req_byte_en => mem_mem_req_byte_en, -- .mem_req_byte_en
mem_req_read_writen => mem_mem_req_read_writen, -- .mem_req_read_writen
mem_req_request => mem_mem_req_request, -- .mem_req_request
mem_req_tag => mem_mem_req_tag, -- .mem_req_tag
mem_req_wdata => mem_mem_req_wdata, -- .mem_req_wdata
mem_resp_dack_tag => mem_mem_resp_dack_tag, -- .mem_resp_dack_tag
mem_resp_data => mem_mem_resp_data, -- .mem_resp_data
mem_resp_rack_tag => mem_mem_resp_rack_tag -- .mem_resp_rack_tag
);
io_bridge_0 : component avalon_to_io_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
avs_ready => io_bridge_0_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => sys_clock_clk, -- clock.clk
io_ack => io_ack, -- io.ack
io_rdata => io_rdata, -- .rdata
io_read => io_read, -- .read
io_wdata => io_wdata, -- .wdata
io_write => io_write, -- .write
io_address => io_address, -- .address
io_irq => io_irq, -- .irq
avs_irq => irq_mapper_receiver6_irq -- irq.irq
);
io_bridge_1 : component avalon_to_io_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_io_bridge_1_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_io_bridge_1_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_io_bridge_1_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata, -- .writedata
avs_ready => io_bridge_1_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => sys_clock_clk, -- clock.clk
io_ack => io_u2p_ack, -- io.ack
io_rdata => io_u2p_rdata, -- .rdata
io_read => io_u2p_read, -- .read
io_wdata => io_u2p_wdata, -- .wdata
io_write => io_u2p_write, -- .write
io_address => io_u2p_address, -- .address
io_irq => io_u2p_irq, -- .irq
avs_irq => irq_mapper_receiver3_irq -- irq.irq
);
jtag_0 : component jtag_host
port map (
clock => sys_clock_clk, -- clock.clk
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_jtag_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_jtag_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_jtag_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_jtag_0_avalon_slave_0_writedata, -- .writedata
avs_ready => jtag_0_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_jtag_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_jtag_0_avalon_slave_0_readdatavalid, -- .readdatavalid
jtag_tck => jtag0_jtag_tck, -- jtag.jtag_tck
jtag_tms => jtag0_jtag_tms, -- .jtag_tms
jtag_tdi => jtag0_jtag_tdi, -- .jtag_tdi
jtag_tdo => jtag0_jtag_tdo -- .jtag_tdo
);
jtag_1 : component jtag_host
port map (
clock => sys_clock_clk, -- clock.clk
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_jtag_1_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_jtag_1_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_jtag_1_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_jtag_1_avalon_slave_0_writedata, -- .writedata
avs_ready => jtag_1_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_jtag_1_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_jtag_1_avalon_slave_0_readdatavalid, -- .readdatavalid
jtag_tck => jtag1_jtag_tck, -- jtag.jtag_tck
jtag_tms => jtag1_jtag_tms, -- .jtag_tms
jtag_tdi => jtag1_jtag_tdi, -- .jtag_tdi
jtag_tdo => jtag1_jtag_tdo -- .jtag_tdo
);
jtagdebug : component nios_tester_jtagdebug
port map (
mm_write_address => jtagdebug_mm_write_address, -- mm_write.address
mm_write_write => jtagdebug_mm_write_write, -- .write
mm_write_writedata => jtagdebug_mm_write_writedata, -- .writedata
mm_write_waitrequest => jtagdebug_mm_write_waitrequest, -- .waitrequest
clock_clk => sys_clock_clk, -- clock.clk
reset_n_reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
csr_writedata => mm_interconnect_0_jtagdebug_csr_writedata, -- csr.writedata
csr_write => mm_interconnect_0_jtagdebug_csr_write, -- .write
csr_byteenable => mm_interconnect_0_jtagdebug_csr_byteenable, -- .byteenable
csr_readdata => mm_interconnect_0_jtagdebug_csr_readdata, -- .readdata
csr_read => mm_interconnect_0_jtagdebug_csr_read, -- .read
csr_address => mm_interconnect_0_jtagdebug_csr_address, -- .address
descriptor_slave_write => mm_interconnect_0_jtagdebug_descriptor_slave_write, -- descriptor_slave.write
descriptor_slave_waitrequest => mm_interconnect_0_jtagdebug_descriptor_slave_waitrequest, -- .waitrequest
descriptor_slave_writedata => mm_interconnect_0_jtagdebug_descriptor_slave_writedata, -- .writedata
descriptor_slave_byteenable => mm_interconnect_0_jtagdebug_descriptor_slave_byteenable, -- .byteenable
csr_irq_irq => irq_mapper_receiver2_irq, -- csr_irq.irq
st_sink_data => jtag_in_data, -- st_sink.data
st_sink_valid => jtag_in_valid, -- .valid
st_sink_ready => jtag_in_ready -- .ready
);
nios2_gen2_0 : component nios_tester_nios2_gen2_0
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component nios_tester_onchip_memory2_0
port map (
clk => sys_clock_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
freeze => '0' -- (terminated)
);
pio_0 : component nios_tester_pio_0
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
in_port => dummy_export, -- external_connection.export
irq => irq_mapper_receiver4_irq -- irq.irq
);
pio_1 : component nios_tester_pio_1
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_1_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_1_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_1_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_1_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_1_s1_readdata, -- .readdata
in_port => pio_in_port, -- external_connection.export
out_port => pio_out_port -- .export
);
spi_0 : component nios_tester_spi_0
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
data_from_cpu => mm_interconnect_0_spi_0_spi_control_port_writedata, -- spi_control_port.writedata
data_to_cpu => mm_interconnect_0_spi_0_spi_control_port_readdata, -- .readdata
mem_addr => mm_interconnect_0_spi_0_spi_control_port_address, -- .address
read_n => mm_interconnect_0_spi_0_spi_control_port_read_ports_inv, -- .read_n
spi_select => mm_interconnect_0_spi_0_spi_control_port_chipselect, -- .chipselect
write_n => mm_interconnect_0_spi_0_spi_control_port_write_ports_inv, -- .write_n
irq => irq_mapper_receiver5_irq, -- irq.irq
MISO => spi_MISO, -- external.export
MOSI => spi_MOSI, -- .export
SCLK => spi_SCLK, -- .export
SS_n => spi_SS_n -- .export
);
mm_interconnect_0 : component nios_tester_mm_interconnect_0
port map (
clk_0_clk_clk => sys_clock_clk, -- clk_0_clk.clk
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
audio_in_dma_mm_write_address => audio_in_dma_mm_write_address, -- audio_in_dma_mm_write.address
audio_in_dma_mm_write_waitrequest => audio_in_dma_mm_write_waitrequest, -- .waitrequest
audio_in_dma_mm_write_byteenable => audio_in_dma_mm_write_byteenable, -- .byteenable
audio_in_dma_mm_write_write => audio_in_dma_mm_write_write, -- .write
audio_in_dma_mm_write_writedata => audio_in_dma_mm_write_writedata, -- .writedata
audio_out_dma_mm_read_address => audio_out_dma_mm_read_address, -- audio_out_dma_mm_read.address
audio_out_dma_mm_read_waitrequest => audio_out_dma_mm_read_waitrequest, -- .waitrequest
audio_out_dma_mm_read_byteenable => audio_out_dma_mm_read_byteenable, -- .byteenable
audio_out_dma_mm_read_read => audio_out_dma_mm_read_read, -- .read
audio_out_dma_mm_read_readdata => audio_out_dma_mm_read_readdata, -- .readdata
audio_out_dma_mm_read_readdatavalid => audio_out_dma_mm_read_readdatavalid, -- .readdatavalid
jtagdebug_mm_write_address => jtagdebug_mm_write_address, -- jtagdebug_mm_write.address
jtagdebug_mm_write_waitrequest => jtagdebug_mm_write_waitrequest, -- .waitrequest
jtagdebug_mm_write_write => jtagdebug_mm_write_write, -- .write
jtagdebug_mm_write_writedata => jtagdebug_mm_write_writedata, -- .writedata
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
audio_in_dma_csr_address => mm_interconnect_0_audio_in_dma_csr_address, -- audio_in_dma_csr.address
audio_in_dma_csr_write => mm_interconnect_0_audio_in_dma_csr_write, -- .write
audio_in_dma_csr_read => mm_interconnect_0_audio_in_dma_csr_read, -- .read
audio_in_dma_csr_readdata => mm_interconnect_0_audio_in_dma_csr_readdata, -- .readdata
audio_in_dma_csr_writedata => mm_interconnect_0_audio_in_dma_csr_writedata, -- .writedata
audio_in_dma_csr_byteenable => mm_interconnect_0_audio_in_dma_csr_byteenable, -- .byteenable
audio_in_dma_descriptor_slave_write => mm_interconnect_0_audio_in_dma_descriptor_slave_write, -- audio_in_dma_descriptor_slave.write
audio_in_dma_descriptor_slave_writedata => mm_interconnect_0_audio_in_dma_descriptor_slave_writedata, -- .writedata
audio_in_dma_descriptor_slave_byteenable => mm_interconnect_0_audio_in_dma_descriptor_slave_byteenable, -- .byteenable
audio_in_dma_descriptor_slave_waitrequest => mm_interconnect_0_audio_in_dma_descriptor_slave_waitrequest, -- .waitrequest
audio_out_dma_csr_address => mm_interconnect_0_audio_out_dma_csr_address, -- audio_out_dma_csr.address
audio_out_dma_csr_write => mm_interconnect_0_audio_out_dma_csr_write, -- .write
audio_out_dma_csr_read => mm_interconnect_0_audio_out_dma_csr_read, -- .read
audio_out_dma_csr_readdata => mm_interconnect_0_audio_out_dma_csr_readdata, -- .readdata
audio_out_dma_csr_writedata => mm_interconnect_0_audio_out_dma_csr_writedata, -- .writedata
audio_out_dma_csr_byteenable => mm_interconnect_0_audio_out_dma_csr_byteenable, -- .byteenable
audio_out_dma_descriptor_slave_write => mm_interconnect_0_audio_out_dma_descriptor_slave_write, -- audio_out_dma_descriptor_slave.write
audio_out_dma_descriptor_slave_writedata => mm_interconnect_0_audio_out_dma_descriptor_slave_writedata, -- .writedata
audio_out_dma_descriptor_slave_byteenable => mm_interconnect_0_audio_out_dma_descriptor_slave_byteenable, -- .byteenable
audio_out_dma_descriptor_slave_waitrequest => mm_interconnect_0_audio_out_dma_descriptor_slave_waitrequest, -- .waitrequest
avalon2mem_0_avalon_slave_0_address => mm_interconnect_0_avalon2mem_0_avalon_slave_0_address, -- avalon2mem_0_avalon_slave_0.address
avalon2mem_0_avalon_slave_0_write => mm_interconnect_0_avalon2mem_0_avalon_slave_0_write, -- .write
avalon2mem_0_avalon_slave_0_read => mm_interconnect_0_avalon2mem_0_avalon_slave_0_read, -- .read
avalon2mem_0_avalon_slave_0_readdata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata, -- .readdata
avalon2mem_0_avalon_slave_0_writedata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata, -- .writedata
avalon2mem_0_avalon_slave_0_byteenable => mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable, -- .byteenable
avalon2mem_0_avalon_slave_0_readdatavalid => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid, -- .readdatavalid
avalon2mem_0_avalon_slave_0_waitrequest => mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest, -- .waitrequest
io_bridge_0_avalon_slave_0_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- io_bridge_0_avalon_slave_0.address
io_bridge_0_avalon_slave_0_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
io_bridge_0_avalon_slave_0_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- .read
io_bridge_0_avalon_slave_0_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
io_bridge_0_avalon_slave_0_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
io_bridge_0_avalon_slave_0_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
io_bridge_0_avalon_slave_0_waitrequest => mm_interconnect_0_io_bridge_0_avalon_slave_0_inv, -- .waitrequest
io_bridge_1_avalon_slave_0_address => mm_interconnect_0_io_bridge_1_avalon_slave_0_address, -- io_bridge_1_avalon_slave_0.address
io_bridge_1_avalon_slave_0_write => mm_interconnect_0_io_bridge_1_avalon_slave_0_write, -- .write
io_bridge_1_avalon_slave_0_read => mm_interconnect_0_io_bridge_1_avalon_slave_0_read, -- .read
io_bridge_1_avalon_slave_0_readdata => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata, -- .readdata
io_bridge_1_avalon_slave_0_writedata => mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata, -- .writedata
io_bridge_1_avalon_slave_0_readdatavalid => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid, -- .readdatavalid
io_bridge_1_avalon_slave_0_waitrequest => mm_interconnect_0_io_bridge_1_avalon_slave_0_inv, -- .waitrequest
jtag_0_avalon_slave_0_address => mm_interconnect_0_jtag_0_avalon_slave_0_address, -- jtag_0_avalon_slave_0.address
jtag_0_avalon_slave_0_write => mm_interconnect_0_jtag_0_avalon_slave_0_write, -- .write
jtag_0_avalon_slave_0_read => mm_interconnect_0_jtag_0_avalon_slave_0_read, -- .read
jtag_0_avalon_slave_0_readdata => mm_interconnect_0_jtag_0_avalon_slave_0_readdata, -- .readdata
jtag_0_avalon_slave_0_writedata => mm_interconnect_0_jtag_0_avalon_slave_0_writedata, -- .writedata
jtag_0_avalon_slave_0_readdatavalid => mm_interconnect_0_jtag_0_avalon_slave_0_readdatavalid, -- .readdatavalid
jtag_0_avalon_slave_0_waitrequest => mm_interconnect_0_jtag_0_avalon_slave_0_inv, -- .waitrequest
jtag_1_avalon_slave_0_address => mm_interconnect_0_jtag_1_avalon_slave_0_address, -- jtag_1_avalon_slave_0.address
jtag_1_avalon_slave_0_write => mm_interconnect_0_jtag_1_avalon_slave_0_write, -- .write
jtag_1_avalon_slave_0_read => mm_interconnect_0_jtag_1_avalon_slave_0_read, -- .read
jtag_1_avalon_slave_0_readdata => mm_interconnect_0_jtag_1_avalon_slave_0_readdata, -- .readdata
jtag_1_avalon_slave_0_writedata => mm_interconnect_0_jtag_1_avalon_slave_0_writedata, -- .writedata
jtag_1_avalon_slave_0_readdatavalid => mm_interconnect_0_jtag_1_avalon_slave_0_readdatavalid, -- .readdatavalid
jtag_1_avalon_slave_0_waitrequest => mm_interconnect_0_jtag_1_avalon_slave_0_inv, -- .waitrequest
jtagdebug_csr_address => mm_interconnect_0_jtagdebug_csr_address, -- jtagdebug_csr.address
jtagdebug_csr_write => mm_interconnect_0_jtagdebug_csr_write, -- .write
jtagdebug_csr_read => mm_interconnect_0_jtagdebug_csr_read, -- .read
jtagdebug_csr_readdata => mm_interconnect_0_jtagdebug_csr_readdata, -- .readdata
jtagdebug_csr_writedata => mm_interconnect_0_jtagdebug_csr_writedata, -- .writedata
jtagdebug_csr_byteenable => mm_interconnect_0_jtagdebug_csr_byteenable, -- .byteenable
jtagdebug_descriptor_slave_write => mm_interconnect_0_jtagdebug_descriptor_slave_write, -- jtagdebug_descriptor_slave.write
jtagdebug_descriptor_slave_writedata => mm_interconnect_0_jtagdebug_descriptor_slave_writedata, -- .writedata
jtagdebug_descriptor_slave_byteenable => mm_interconnect_0_jtagdebug_descriptor_slave_byteenable, -- .byteenable
jtagdebug_descriptor_slave_waitrequest => mm_interconnect_0_jtagdebug_descriptor_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
pio_1_s1_address => mm_interconnect_0_pio_1_s1_address, -- pio_1_s1.address
pio_1_s1_write => mm_interconnect_0_pio_1_s1_write, -- .write
pio_1_s1_readdata => mm_interconnect_0_pio_1_s1_readdata, -- .readdata
pio_1_s1_writedata => mm_interconnect_0_pio_1_s1_writedata, -- .writedata
pio_1_s1_chipselect => mm_interconnect_0_pio_1_s1_chipselect, -- .chipselect
spi_0_spi_control_port_address => mm_interconnect_0_spi_0_spi_control_port_address, -- spi_0_spi_control_port.address
spi_0_spi_control_port_write => mm_interconnect_0_spi_0_spi_control_port_write, -- .write
spi_0_spi_control_port_read => mm_interconnect_0_spi_0_spi_control_port_read, -- .read
spi_0_spi_control_port_readdata => mm_interconnect_0_spi_0_spi_control_port_readdata, -- .readdata
spi_0_spi_control_port_writedata => mm_interconnect_0_spi_0_spi_control_port_writedata, -- .writedata
spi_0_spi_control_port_chipselect => mm_interconnect_0_spi_0_spi_control_port_chipselect -- .chipselect
);
irq_mapper : component nios_tester_irq_mapper
port map (
clk => sys_clock_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
receiver4_irq => irq_mapper_receiver4_irq, -- receiver4.irq
receiver5_irq => irq_mapper_receiver5_irq, -- receiver5.irq
receiver6_irq => irq_mapper_receiver6_irq, -- receiver6.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => sys_reset_reset_n_ports_inv, -- reset_in0.reset
clk => sys_clock_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
sys_reset_reset_n_ports_inv <= not sys_reset_reset_n;
mm_interconnect_0_io_bridge_1_avalon_slave_0_inv <= not io_bridge_1_avalon_slave_0_waitrequest;
mm_interconnect_0_jtag_0_avalon_slave_0_inv <= not jtag_0_avalon_slave_0_waitrequest;
mm_interconnect_0_jtag_1_avalon_slave_0_inv <= not jtag_1_avalon_slave_0_waitrequest;
mm_interconnect_0_io_bridge_0_avalon_slave_0_inv <= not io_bridge_0_avalon_slave_0_waitrequest;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_pio_1_s1_write_ports_inv <= not mm_interconnect_0_pio_1_s1_write;
mm_interconnect_0_spi_0_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_0_spi_control_port_read;
mm_interconnect_0_spi_0_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_0_spi_control_port_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of nios_tester
| gpl-3.0 | 4cea55618a6263be0a24e14bab2a24cf | 0.480934 | 3.872439 | false | false | false | false |
xiadz/oscilloscope | src/bits_aggregator.vhd | 1 | 3,657 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 19:43:33 05/27/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bits_aggregator is
port (
-- Inputs
nrst : in std_logic;
clk108 : in std_logic;
flush_and_return_to_zero : in std_logic;
write_enable : in std_logic;
red_value : in std_logic;
green_value : in std_logic;
blue_value : in std_logic;
-- Outputs
wea : out std_logic;
addra : out std_logic_vector (12 downto 0);
dina : out std_logic_vector (8 downto 0)
);
end bits_aggregator;
architecture behavioral of bits_aggregator is
signal mod3 : integer range 0 to 2 := 0;
signal next_mod3 : integer range 0 to 2;
signal mod3_overflow : std_logic := '0';
signal address : std_logic_vector (12 downto 0) := (others => '0');
signal next_address : std_logic_vector (12 downto 0);
signal row_buffer : std_logic_vector (5 downto 0) := (others => '0');
signal next_row : std_logic_vector (8 downto 0) := (others => '0');
begin
-- Process calculates next_mod3, mod3_overflow, next_address
process (mod3, address) is
begin
if mod3 = 2 then
next_mod3 <= 0;
mod3_overflow <= '1';
next_address <= address + 1;
else
next_mod3 <= mod3 + 1;
mod3_overflow <= '0';
next_address <= address;
end if;
end process;
-- Process calculates next_row
process (mod3, row_buffer, red_value, green_value, blue_value) is
begin
if mod3 = 0 then
next_row (0) <= red_value;
next_row (1) <= green_value;
next_row (2) <= blue_value;
next_row (8 downto 3) <= (others => '0');
elsif mod3 = 1 then
next_row (2 downto 0) <= row_buffer (2 downto 0);
next_row (3) <= red_value;
next_row (4) <= green_value;
next_row (5) <= blue_value;
next_row (8 downto 6) <= (others => '0');
else
next_row (5 downto 0) <= row_buffer (5 downto 0);
next_row (6) <= red_value;
next_row (7) <= green_value;
next_row (8) <= blue_value;
end if;
end process;
process (nrst, clk108) is
begin
if nrst = '0' then
mod3 <= 0;
address <= (others => '0');
wea <= '0';
addra <= (others => '0');
dina <= (others => '0');
elsif rising_edge (clk108) then
if flush_and_return_to_zero = '1' then
mod3 <= 0;
address <= (others => '0');
row_buffer <= (others => '0');
addra <= address;
dina <= next_row;
wea <= '1';
elsif write_enable = '1' then
mod3 <= next_mod3;
address <= next_address;
row_buffer <= next_row (5 downto 0);
if mod3_overflow = '1' then
addra <= address;
dina <= next_row;
wea <= '1';
else
wea <= '0';
end if;
else
wea <= '0';
end if;
end if;
end process;
end behavioral;
| mit | 4c340773aa92b6672abec4b5793e191c | 0.439978 | 4.040884 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/mm_startup_1571_tc.vhd | 1 | 10,965 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_bfm_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.c1541_pkg.all;
use work.tl_string_util_pkg.all;
use work.iec_bus_bfm_pkg.all;
entity mm_startup_1571_tc is
end;
architecture tc of mm_startup_1571_tc is
signal irq : std_logic;
constant c_wd177x_command : unsigned(15 downto 0) := X"1800";
constant c_wd177x_track : unsigned(15 downto 0) := X"1801";
constant c_wd177x_sector : unsigned(15 downto 0) := X"1802";
constant c_wd177x_datareg : unsigned(15 downto 0) := X"1803";
constant c_wd177x_status_clear : unsigned(15 downto 0) := X"1804";
constant c_wd177x_status_set : unsigned(15 downto 0) := X"1805";
constant c_wd177x_irq_ack : unsigned(15 downto 0) := X"1806";
constant c_wd177x_dma_mode : unsigned(15 downto 0) := X"1807";
constant c_wd177x_dma_addr : unsigned(15 downto 0) := X"1808"; -- DWORD
constant c_wd177x_dma_len : unsigned(15 downto 0) := X"180C"; -- WORD
constant c_param_ram : unsigned(15 downto 0) := X"1000";
begin
i_harness: entity work.harness_mm
port map (
io_irq => irq
);
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
variable value : unsigned(31 downto 0);
variable params : std_logic_vector(31 downto 0);
variable rotation_speed : natural;
variable bit_time : natural;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
bind_iec_bus_bfm("iec_bfm", bfm);
load_memory("../../../roms/1571-rom.310654-05.bin", dram, X"00008000");
-- load_memory("../../../roms/sounds.bin", dram, X"00000000");
load_memory("../../../disks/cpm.g71", dram, X"00100000" ); -- 1 MB offset
wait for 20 us;
io_write(io, c_drvreg_drivetype, X"01"); -- switch to 1571 mode
io_write(io, c_drvreg_power, X"01");
wait for 20 us;
io_write(io, c_drvreg_reset, X"00");
rotation_speed := (31250000 / 20);
for i in 0 to 34 loop
value := unsigned(read_memory_32(dram, std_logic_vector(to_unsigned(16#100000# + 12 + i*8, 32))));
value := value + X"00100000";
params(15 downto 0) := read_memory_16(dram, std_logic_vector(value));
value := value + 2;
bit_time := rotation_speed / to_integer(unsigned(params(15 downto 0)));
params(31 downto 16) := std_logic_vector(to_unsigned(bit_time, 16));
report "Track " & integer'image(i+1) & ": " & hstr(value) & " - " & hstr(params);
io_write_32(io, c_param_ram + 16*i, std_logic_vector(value) );
io_write_32(io, c_param_ram + 16*i + 4, params );
io_write_32(io, c_param_ram + 16*i + 12, params );
end loop;
wait for 800 ms;
io_write(io, c_drvreg_inserted, X"01");
-- iec_drf(bfm);
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
iec_send_atn(bfm, X"5F", true); -- Drives, Untalk!
wait for 10 ms;
iec_send_atn(bfm, X"28"); -- Drive 8, Listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_send_message(bfm, "U0>M1"); -- 1571 Mode!
wait for 10 ms;
iec_send_atn(bfm, X"3F", true); -- UnListen
wait for 1000 ms;
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
-- Type Command 7 6 5 4 3 2 1 0
-- -------------------------------------------------------
-- I Restore 0 0 0 0 h v r1 r0
-- I Seek 0 0 0 1 h v r1 r0
-- I Step 0 0 1 u h v r1 r0
-- I Step in 0 1 0 u h v r1 r0
-- I Step out 0 1 1 u h v r1 r0
-- II Read sector 1 0 0 m h/s e 0/c 0
-- II Write sector 1 0 1 m h/s e p/c a
-- III Read address 1 1 0 0 h/0 e 0 0
-- III Read track 1 1 1 0 h/0 e 0 0
-- III Write track 1 1 1 1 h/0 e p/0 0
-- IV Force interrupt 1 1 0 1 i3 i2 i1 i0
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable cmd : std_logic_vector(7 downto 0);
variable byte : std_logic_vector(7 downto 0);
variable track : natural := 0;
variable sector : natural := 0;
variable dir : std_logic := '1';
variable side : std_logic := '0';
procedure do_step(update : std_logic) is
begin
if dir = '0' then
if track < 80 then
track := track + 1;
end if;
else
if track > 0 then
track := track - 1;
end if;
end if;
if update = '1' then
io_read(io, c_wd177x_track, byte);
if dir = '0' then
byte := std_logic_vector(unsigned(byte) + 1);
else
byte := std_logic_vector(unsigned(byte) - 1);
end if;
io_write(io, c_wd177x_track, byte);
end if;
end procedure;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
while true loop
wait until irq = '1';
io_read(io, c_wd177x_command, cmd);
report "Command: " & hstr(cmd);
wait for 50 us;
if cmd(7 downto 4) = "0000" then
report "WD1770 Command: Restore";
io_write(io, c_wd177x_track, X"00"); -- set track to zero
track := 0;
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 4) = "0001" then
io_read(io, c_wd177x_datareg, byte);
report "WD1770 Command: Seek: Track = " & integer'image(to_integer(unsigned(byte)));
io_write(io, c_wd177x_track, byte);
track := to_integer(unsigned(byte));
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "001" then
report "WD1770 Command: Step.";
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "010" then
report "WD1770 Command: Step In.";
dir := '1';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "011" then
report "WD1770 Command: Step Out.";
dir := '0';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "100" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Read Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"0000C000" ); -- read a piece of the ROM for now
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"01"); -- read
-- data transfer, so we are not yet done
elsif cmd(7 downto 5) = "101" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Write Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"02"); -- write
-- data transfer, so we are not yet done
elsif cmd(7 downto 4) = "1100" then
report "WD1770 Command: Read Address.";
write_memory_8(dram, X"00020000", std_logic_vector(to_unsigned(track, 8)) );
write_memory_8(dram, X"00020001", X"00" ); -- side (!!)
write_memory_8(dram, X"00020002", std_logic_vector(to_unsigned(sector, 8)) );
write_memory_8(dram, X"00020003", X"02" ); -- sector length = 512
write_memory_8(dram, X"00020004", X"F9" ); -- CRC1
write_memory_8(dram, X"00020005", X"5E" ); -- CRC2
io_write_32(io, c_wd177x_dma_addr, X"00020000" );
io_write(io, c_wd177x_dma_len, X"06");
io_write(io, c_wd177x_dma_len+1, X"00"); -- transfer 6 bytes
io_write(io, c_wd177x_dma_mode, X"01"); -- read
elsif cmd(7 downto 4) = "1110" then
report "WD1770 Command: Read Track (not implemented).";
elsif cmd(7 downto 4) = "1111" then
report "WD1770 Command: Write Track.";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"6A");
io_write(io, c_wd177x_dma_len+1, X"18"); -- 6250 bytes
io_write(io, c_wd177x_dma_mode, X"02"); -- write
elsif cmd(7 downto 4) = "1101" then
io_write(io, c_wd177x_dma_mode, X"00"); -- stop
io_write(io, c_wd177x_status_clear, X"01");
end if;
io_write(io, c_wd177x_irq_ack, X"00");
end loop;
end process;
end architecture;
| gpl-3.0 | 148b50a1d57d14ec0f6960007c8eaaa8 | 0.487825 | 3.369699 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/ulpi_tx.vhd | 1 | 11,383 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_tx is
generic (
g_simulation : boolean := false;
g_support_split : boolean := true;
g_support_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
-- Bus Interface
tx_start : out std_logic;
tx_last : out std_logic;
tx_valid : out std_logic;
tx_next : in std_logic;
tx_data : out std_logic_vector(7 downto 0);
rx_busy : in std_logic;
-- CRC calculator
crc_sync : out std_logic;
crc_dvalid : out std_logic;
data_to_crc : out std_logic_vector(7 downto 0);
data_crc : in std_logic_vector(15 downto 0);
-- Status
status : in std_logic_vector(7 downto 0);
speed : in std_logic_vector(1 downto 0);
usb_tx_req : in t_usb_tx_req;
usb_tx_resp : out t_usb_tx_resp );
end ulpi_tx;
architecture gideon of ulpi_tx is
type t_state is (idle, crc_1, crc_2, token0, token1, token2, token3,
transmit, wait4next, write_end, handshake, gap, gap2);
signal state : t_state;
signal tx_data_i : std_logic_vector(7 downto 0);
signal tx_last_i : std_logic;
signal token_crc : std_logic_vector(4 downto 0) := "00000";
signal split_crc : std_logic_vector(4 downto 0) := "00000";
signal no_data_d : std_logic;
signal gap_count : integer range 0 to 2047;
signal rd_data : std_logic_vector(7 downto 0);
signal rd_last : std_logic;
signal rd_next : std_logic;
signal token_vector : std_logic_vector(18 downto 0);
signal long : boolean;
signal fifo_flush : std_logic;
signal busy : std_logic;
signal sending_sof : boolean;
signal tx_allowed : std_logic;
signal start_value : unsigned(10 downto 0);
signal start_timer : std_logic;
signal tx_put : std_logic;
signal almost_full : std_logic;
-- internal fifo is 3 bytes as it seems. 3 bytes is at max 40 bits incl. 1.5 SE0 EOP. at Full speed this is 40*5 = 200 clocks
-- at low speed this is 40*40 clocks = 1600
type t_int_array is array (natural range <>) of integer;
constant c_gap_values : t_int_array(0 to 3) := ( 1599, 199, 13, 13 );
-- XILINX USB STICK:
-- On high speed, gap values 0x05 - 0x25 WORK.. (bigger than 0x25 doesn't, smaller than 0x05 doesn't..)
-- TRUST USB 2.0 Hub:
-- On high speed, gap values 0x07 - 0x1D WORK.. with the exception of 0x09.
-- Samsung DVD-Burner:
-- On high speed, gap values 0x00 - 0x23 WORK.. with the exception of 0x04.
-- Western Digital external HD:
-- On high speed, gap values 0x05 - 0x21 WORK.. with the exception of 0x06 and 0x09.
--
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "sequential";
begin
usb_tx_resp.request_ack <= (usb_tx_req.send_token or usb_tx_req.send_handsh or usb_tx_req.send_packet or usb_tx_req.send_split)
when (state = idle) and (tx_allowed = '1') else '0';
usb_tx_resp.busy <= busy;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
fifo_flush <= '0';
tx_data_i <= X"00";
no_data_d <= usb_tx_req.no_data;
long <= false;
sending_sof <= usb_tx_req.pid = c_pid_sof;
if tx_allowed = '1' then
if usb_tx_req.send_token='1' and g_support_token then
token_vector <= token_to_vector(usb_tx_req.token) & X"00";
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
state <= token1;
elsif usb_tx_req.send_split='1' and g_support_split then
token_vector <= split_token_to_vector(usb_tx_req.split_token);
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
long <= true;
state <= token0;
elsif usb_tx_req.send_handsh='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
tx_last_i <= '1';
state <= handshake;
elsif usb_tx_req.send_packet='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
state <= wait4next;
end if;
end if;
when wait4next =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '1';
if no_data_d='1' then
state <= crc_1;
else
state <= transmit;
end if;
end if;
when handshake =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
state <= gap;
end if;
when write_end =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
state <= idle;
end if;
when crc_1 =>
if tx_next = '1' then
tx_last_i <= '1';
fifo_flush <= '1';
state <= crc_2;
end if;
when crc_2 =>
if tx_next = '1' then
tx_last_i <= '0';
tx_valid <= '0';
state <= gap;
end if;
when token0 =>
if tx_next = '1' then
tx_start <= '0';
tx_data_i <= token_vector(7 downto 0);
state <= token1;
end if;
when token1 =>
if tx_next = '1' then
tx_start <= '0';
tx_data_i <= token_vector(15 downto 8);
state <= token2;
end if;
when token2 =>
if tx_next = '1' then
if long then
tx_data_i <= split_crc & token_vector(18 downto 16);
else
tx_data_i <= token_crc & token_vector(18 downto 16);
end if;
tx_last_i <= '1';
state <= token3;
end if;
when token3 =>
if tx_next = '1' then
tx_last_i <= '0';
tx_valid <= '0';
state <= gap;
end if;
when gap => -- pulse timer
state <= gap2;
when gap2 =>
if tx_allowed = '1' then
state <= idle;
end if;
when transmit =>
if tx_next='1' and rd_last='1' then
state <= crc_1;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
fifo_flush <= '0';
end if;
end if;
end process;
crc_dvalid <= '1' when (state = transmit) and tx_next='1' else '0';
--crc_sync <= '1' when (state = idle) else '0';
crc_sync <= usb_tx_req.send_packet;
busy <= '0' when (state = idle) else '1'; -- or (state = gap) else '1';
g_token: if g_support_token generate
i_token_crc: entity work.token_crc
port map (
clock => clock,
token_in => token_vector(18 downto 8),
crc => token_crc );
end generate;
g_split: if g_support_split generate
i_split_crc: entity work.token_crc_19
port map (
clock => clock,
token_in => token_vector(18 downto 0),
crc => split_crc );
end generate;
with state select tx_data <=
rd_data when transmit,
data_crc(7 downto 0) when crc_1,
data_crc(15 downto 8) when crc_2,
tx_data_i when others;
tx_last <= tx_last_i;
rd_next <= '1' when (tx_next = '1') and (state = transmit) else '0';
tx_put <= usb_tx_req.data_valid and not almost_full;
usb_tx_resp.data_wait <= almost_full;
i_tx_fifo: entity work.srl_fifo
generic map (
Width => 9,
Threshold => 13 )
port map (
clock => clock,
reset => reset,
GetElement => rd_next,
PutElement => tx_put,
FlushFifo => fifo_flush,
DataIn(8) => usb_tx_req.data_last,
DataIn(7 downto 0) => usb_tx_req.data,
DataOut(8) => rd_last,
DataOut(7 downto 0) => rd_data,
SpaceInFifo => open,
AlmostFull => almost_full,
DataInFifo => open );
data_to_crc <= rd_data;
start_timer <= '1' when state = gap else rx_busy; -- we start the tx_backoff timer when we are receiving, or when we finished transmitting
process(sending_sof, speed, status)
begin
if g_simulation then
start_value <= to_unsigned(15, start_value'length);
elsif rx_busy = '1' then
start_value <= to_unsigned(12, start_value'length);
elsif sending_sof and speed(1)='1' then
start_value <= to_unsigned(22, start_value'length);
else
case speed is
when "00" => start_value <= to_unsigned(c_gap_values(0), start_value'length);
when "01" => start_value <= to_unsigned(c_gap_values(1), start_value'length);
when others => start_value <= to_unsigned(c_gap_values(2), start_value'length);
end case;
end if;
end process;
i_timer: entity work.timer
generic map (
g_reset => '1',
g_width => 11 )
port map (
clock => clock,
reset => reset,
start => start_timer,
start_value => start_value,
timeout => tx_allowed );
end gideon;
| gpl-3.0 | 26084f88706280c09af47a38e4ec4b76 | 0.432311 | 3.995437 | false | false | false | false |
xiadz/oscilloscope | src/settings_pixgen.vhd | 1 | 10,242 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 20:16:43 05/22/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.types.all;
entity settings_pixgen is
port (
nrst : in std_logic;
clk108 : in std_logic;
segment : in integer range 0 to 15;
segment_change : in std_logic;
subsegment : in integer range 0 to 3;
subsegment_change : in std_logic;
line : in integer range 0 to 15;
line_change : in std_logic;
column : in integer range 0 to 1279;
column_mod_8 : in integer range 0 to 7;
column_div_8 : in integer range 0 to 159;
column_change : in std_logic;
page_change : in std_logic;
active_pixgen_source : in PIXGEN_SOURCE_T;
is_reading_active : in std_logic;
trigger_event : in TRIGGER_EVENT_T;
red_enable : in std_logic;
green_enable : in std_logic;
blue_enable : in std_logic;
continue_after_reading : in std_logic;
time_resolution : in integer range 0 to 15;
char : out short_character;
char_pixel : in std_logic;
vout : out std_logic_vector (7 downto 0)
);
end settings_pixgen;
architecture behavioral of settings_pixgen is
constant s_red_sig : short_string := to_short_string (" Red signal (C6): ???abled (SW6)");
constant s_green_sig : short_string := to_short_string ("Green signal (B6): ???abled (SW5)");
constant s_blue_sig : short_string := to_short_string (" Blue signal (C5): ???abled (SW4)");
constant s_enabled : short_string := to_short_string (" en");
constant s_disabled : short_string := to_short_string ("dis");
constant s_resolution : short_string := to_short_string (" Resolution: ???????? (SW3 ~ SW0)");
constant s_trigger : short_string := to_short_string (" Trigger on: ???????? (BTN2 to change)");
constant s_after : short_string := to_short_string ("After reading: ???????? (BTN1 to change)");
type res_array_t is array (0 to 15) of short_string (7 downto 0);
constant res_array : res_array_t := (
to_short_string (" 54 Mhz"),
to_short_string ("21.6 Mhz"),
to_short_string ("10.8 Mhz"),
to_short_string (" 5.4 Mhz"),
to_short_string (" 1 Mhz"),
to_short_string (" 500 khz"),
to_short_string (" 250 khz"),
to_short_string (" 100 khz"),
to_short_string (" 50 khz"),
to_short_string (" 25 khz"),
to_short_string (" 10 khz"),
to_short_string (" 5 khz"),
to_short_string (" 2.5 khz"),
to_short_string (" 1 khz"),
to_short_string (" 500 hz"),
to_short_string (" 250 hz")
);
constant s_btn0 : short_string := to_short_string (" BTN0");
constant s_red : short_string := to_short_string (" red");
constant s_green : short_string := to_short_string (" green");
constant s_blue : short_string := to_short_string (" blue");
constant s_continue : short_string := to_short_string ("continue");
constant s_stop : short_string := to_short_string (" stop");
constant s_reading_active : short_string := to_short_string (" Running... (press BTN0 to stop)");
constant s_reading_stopped : short_string := to_short_string ("Stopped. Waiting for trigger event.");
begin
process (nrst, clk108) is
begin
if nrst = '0' then
char <= character_conv_table (0);
elsif rising_edge (clk108) then
if segment = 14 then
-- Upper settings segment (segment = 14)
if subsegment = 0 then
-- Red subsegment
if column_div_8 < 19 then
char <= s_red_sig (column_div_8);
elsif column_div_8 < 22 then
if red_enable = '1' then
char <= s_enabled (column_div_8 - 19);
else
char <= s_disabled (column_div_8 - 19);
end if;
elsif column_div_8 < s_red_sig'length then
char <= s_red_sig (column_div_8);
else
char <= to_short_character (' ');
end if;
elsif subsegment = 1 then
-- Green subsegment
if column_div_8 < 19 then
char <= s_green_sig (column_div_8);
elsif column_div_8 < 22 then
if green_enable = '1' then
char <= s_enabled (column_div_8 - 19);
else
char <= s_disabled (column_div_8 - 19);
end if;
elsif column_div_8 < s_green_sig'length then
char <= s_green_sig (column_div_8);
else
char <= to_short_character (' ');
end if;
elsif subsegment = 2 then
-- Blue subsegment
if column_div_8 < 19 then
char <= s_blue_sig (column_div_8);
elsif column_div_8 < 22 then
if blue_enable = '1' then
char <= s_enabled (column_div_8 - 19);
else
char <= s_disabled (column_div_8 - 19);
end if;
elsif column_div_8 < s_blue_sig'length then
char <= s_blue_sig (column_div_8);
else
char <= to_short_character (' ');
end if;
else
-- Empty subsegment
char <= to_short_character (' ');
end if;
else
-- Lower settings segment (segment = 15)
if subsegment = 0 then
-- Resolution subsegment
if column_div_8 < 15 then
char <= s_resolution (column_div_8);
elsif column_div_8 < 23 then
char <= res_array (time_resolution) (column_div_8 - 15);
elsif column_div_8 < s_resolution'length then
char <= s_resolution (column_div_8);
else
char <= to_short_character (' ');
end if;
elsif subsegment = 1 then
-- Trigger subsegment
if column_div_8 < 15 then
char <= s_trigger (column_div_8);
elsif column_div_8 < 23 then
if trigger_event = RED_TRIGGER_T then
char <= s_red (column_div_8 - 15);
elsif trigger_event = GREEN_TRIGGER_T then
char <= s_green (column_div_8 - 15);
elsif trigger_event = BLUE_TRIGGER_T then
char <= s_blue (column_div_8 - 15);
else
char <= s_btn0 (column_div_8 - 15);
end if;
elsif column_div_8 < s_trigger'length then
char <= s_trigger (column_div_8);
else
char <= to_short_character (' ');
end if;
elsif subsegment = 2 then
-- Behaviour after reading subsegment
if column_div_8 < 15 then
char <= s_after (column_div_8);
elsif column_div_8 < 23 then
if continue_after_reading = '1' then
char <= s_continue (column_div_8 - 15);
else
char <= s_stop (column_div_8 - 15);
end if;
elsif column_div_8 < s_after'length then
char <= s_after (column_div_8);
else
char <= to_short_character (' ');
end if;
else
-- Status subsegment.
if column_div_8 < 125 then
char <= to_short_character (' ');
else
if is_reading_active = '1' then
char <= s_reading_active (column_div_8 - 125);
else
char <= s_reading_stopped (column_div_8 - 125);
end if;
end if;
end if;
end if;
end if;
end process;
process (char_pixel, segment, subsegment) is
begin
if char_pixel = '1' then
if segment = 14 then
if subsegment = 0 then
vout <= "11100000";
elsif subsegment = 1 then
vout <= "00011100";
elsif subsegment = 2 then
vout <= "00000011";
else
vout <= "11111111";
end if;
else
vout <= "11111111";
end if;
else
vout <= "00000000";
end if;
end process;
end behavioral;
| mit | 88e43341373c1ba5d9cf6f09ba4abd8f | 0.418278 | 4.71547 | false | false | false | false |
armandas/Arcade | player.vhd | 1 | 5,268 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity player is
port(
clk, not_reset: in std_logic;
bump_sound, miss_sound: in std_logic;
shooting_sound, explosion_sound: in std_logic;
buzzer: out std_logic
);
end player;
architecture behaviour of player is
signal pitch: std_logic_vector(18 downto 0);
signal duration: std_logic_vector(25 downto 0);
signal volume: std_logic_vector(2 downto 0);
signal enable: std_logic;
signal d_counter, d_counter_next: std_logic_vector(25 downto 0);
signal note, note_next: std_logic_vector(8 downto 0);
signal note_addr, note_addr_next: std_logic_vector(4 downto 0);
signal change_note: std_logic;
-- data source for tunes
signal source, source_next: std_logic_vector(1 downto 0);
-- container for current data selected by multiplexer
signal data: std_logic_vector(8 downto 0);
-- data containers for use with ROMs. Add more as needed.
signal data_1, data_2, data_3, data_4: std_logic_vector(8 downto 0);
type state_type is (off, playing);
signal state, state_next: state_type;
signal start: std_logic;
begin
process(clk, not_reset)
begin
if not_reset = '0' then
state <= off;
source <= (others => '0');
note_addr <= (others => '0');
note <= (others => '0');
d_counter <= (others => '0');
elsif clk'event and clk = '1' then
state <= state_next;
source <= source_next;
note_addr <= note_addr_next;
note <= note_next;
d_counter <= d_counter_next;
end if;
end process;
process(state, start, enable, duration, d_counter, note_addr, change_note)
begin
state_next <= state;
note_addr_next <= note_addr;
case state is
when off =>
note_addr_next <= (others => '0');
if start = '1' then
state_next <= playing;
end if;
when playing =>
if duration = 0 then
state_next <= off;
elsif change_note = '1' then
note_addr_next <= note_addr + 1;
end if;
end case;
end process;
enable <= '1' when state = playing else '0';
change_note <= '1' when d_counter = duration else '0';
d_counter_next <= d_counter + 1 when (enable = '1' and
d_counter < duration) else
(others => '0');
with note(8 downto 6) select
pitch <= "1101110111110010001" when "001", -- 110 Hz
"0110111011111001000" when "010", -- 220 Hz
"0011011101111100100" when "011", -- 440 Hz
"0001101110111110010" when "100", -- 880 Hz
"0000110111011111001" when "101", -- 1760 Hz
"0000011011101111100" when "110", -- 3520 Hz
"0000001101110111110" when "111", -- 7040 Hz
"0000000000000000000" when others;
with note(5 downto 3) select
duration <= "00000010111110101111000010" when "001", -- 1/64
"00000101111101011110000100" when "010", -- 1/32
"00001011111010111100001000" when "011", -- 1/16
"00010111110101111000010000" when "100", -- 1/8
"00101111101011110000100000" when "101", -- 1/4
"01011111010111100001000000" when "110", -- 1/2
"10111110101111000010000000" when "111", -- 1/1
"00000000000000000000000000" when others;
volume <= note(2 downto 0);
start <= '1' when (bump_sound = '1' or
miss_sound = '1' or
shooting_sound = '1' or
explosion_sound = '1') else
'0';
-- data source
source_next <= "00" when bump_sound = '1' else
"01" when miss_sound = '1' else
"10" when shooting_sound = '1' else
"11" when explosion_sound = '1' else
source;
data <= data_1 when source = 0 else
data_2 when source = 1 else
data_3 when source = 2 else
data_4;
note_next <= data;
bump:
entity work.bump_sound(content)
port map(
addr => note_addr(1 downto 0),
data => data_1
);
miss:
entity work.lost_ball_sound(content)
port map(
addr => note_addr(1 downto 0),
data => data_2
);
shooting:
entity work.shooting_sound(content)
port map(
addr => note_addr,
data => data_3
);
explosion:
entity work.explosion_sound(content)
port map(
addr => note_addr,
data => data_4
);
sounds:
entity work.sounds(generator)
port map(
clk => clk, not_reset => not_reset,
enable => enable,
period => pitch,
volume => volume,
buzzer => buzzer
);
end behaviour; | bsd-2-clause | 7bd052412654b8ea7f0b98cb060634d0 | 0.514996 | 4.131765 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_tester/nios_tester/synthesis/submodules/avalon_to_io_bridge.vhd | 6 | 2,741 | -------------------------------------------------------------------------------
-- Title : avalon_to_io_bridge
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module bridges the avalon bus to I/O
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity avalon_to_io_bridge is
port (
clock : in std_logic;
reset : in std_logic;
-- 8 bits Avalon bus interface
avs_read : in std_logic;
avs_write : in std_logic;
avs_address : in std_logic_vector(19 downto 0);
avs_writedata : in std_logic_vector(7 downto 0);
avs_ready : out std_logic;
avs_readdata : out std_logic_vector(7 downto 0);
avs_readdatavalid : out std_logic;
avs_irq : out std_logic;
io_read : out std_logic;
io_write : out std_logic;
io_address : out std_logic_vector(19 downto 0);
io_wdata : out std_logic_vector(7 downto 0);
io_rdata : in std_logic_vector(7 downto 0);
io_ack : in std_logic;
io_irq : in std_logic );
end entity;
architecture rtl of avalon_to_io_bridge is
type t_state is (idle, read_pending, write_pending);
signal state : t_state;
begin
avs_irq <= io_irq;
avs_ready <= '1' when (state = idle) else '0';
avs_readdatavalid <= '1' when (state = read_pending) and (io_ack = '1') else '0';
avs_readdata <= io_rdata;
process(clock)
begin
if rising_edge(clock) then
io_read <= '0';
io_write <= '0';
case state is
when idle =>
io_wdata <= avs_writedata;
io_address <= avs_address;
if avs_read='1' then
io_read <= '1';
state <= read_pending;
elsif avs_write='1' then
io_write <= '1';
state <= write_pending;
end if;
when read_pending =>
if io_ack = '1' then
state <= idle;
end if;
when write_pending =>
if io_ack = '1' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | c0528f42642d73c2abdb1dcdc50a62f7 | 0.42977 | 4.26947 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/sigma_delta_dac/vhdl_source/hf_noise.vhd | 2 | 3,289 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hf_noise is
generic (
g_hp_filter : boolean := true );
port (
clock : in std_logic;
enable : in std_logic;
reset : in std_logic;
q : out signed(15 downto 0) );
end entity;
architecture structural of hf_noise is
-- constant c_type : string := "Galois";
-- constant c_polynom : std_logic_vector := X"5D6DCB";
constant c_type : string := "Fibonacci";
constant c_polynom : std_logic_vector := X"E10000";
constant c_seed : std_logic_vector := X"000001";
signal raw_lfsr : std_logic_vector(c_polynom'length-1 downto 0);
signal noyse : signed(15 downto 0);
signal hp : signed(15 downto 0);
begin
i_lfsr: entity work.noise_generator
generic map (
g_type => c_type,
g_polynom => c_polynom,
g_seed => c_seed )
port map (
clock => clock,
enable => enable,
reset => reset,
q => raw_lfsr );
-- Reordering the bits somehow randomly,
-- gives a better spectral distribution
-- in case of Galois (flat!)! In face of Fibonacci,
-- this reordering gives ~20dB dips at odd
-- locations, depending on the reorder choice.
noyse(15) <= raw_lfsr(1);
noyse(14) <= raw_lfsr(4);
noyse(13) <= raw_lfsr(7);
noyse(12) <= raw_lfsr(10);
noyse(11) <= raw_lfsr(13);
noyse(10) <= raw_lfsr(16);
noyse(09) <= raw_lfsr(19);
noyse(08) <= raw_lfsr(22);
noyse(07) <= raw_lfsr(20);
noyse(06) <= raw_lfsr(17);
noyse(05) <= raw_lfsr(14);
noyse(04) <= raw_lfsr(11);
noyse(03) <= raw_lfsr(8);
noyse(02) <= raw_lfsr(5);
noyse(01) <= raw_lfsr(2);
noyse(00) <= raw_lfsr(18);
-- taking an up-range or down range gives a reasonably
-- flat frequency response, but lacks low frequencies (~20 dB)
-- In case of our high-freq noise that we need, this is not
-- a bad thing, as our filter doesn't need to be so sharp.
-- Fibonacci gives less low frequency noise than Galois!
-- differences seen with 1st order filter below were 5-10dB in
-- our band of interest.
-- noise <= signed(raw_lfsr(20 downto 5));
r_hp: if g_hp_filter generate
signal hp_a : signed(15 downto 0);
begin
i_hp: entity work.high_pass
generic map (
g_width => 15 )
port map (
clock => clock,
enable => enable,
reset => reset,
x => noyse(14 downto 0),
-- q => hp_a );
-- i_hp_b: entity work.high_pass
-- generic map (
-- g_width => 16 )
-- port map (
-- clock => clock,
-- reset => reset,
--
-- x => hp_a,
q => hp );
end generate;
q <= hp(15 downto 0) when g_hp_filter else noyse;
end structural;
| gpl-3.0 | 6c51fb20858b6fe1f240b38a2ce7b1db | 0.48647 | 3.56338 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/standard/cb20/synthesis/cb20_gpio_block_1.vhd | 1 | 3,970 | -- cb20_gpio_block_1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_1 is
generic (
number_of_gpios : integer := 8;
unique_id : std_logic_vector(31 downto 0) := "00010010011100000101000000000010"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- avalon_slave_0.readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => '0'); -- .address
isl_avs_read : in std_logic := '0'; -- .read
isl_avs_write : in std_logic := '0'; -- .write
osl_avs_waitrequest : out std_logic; -- .waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
isl_clk : in std_logic := '0'; -- clock_sink.clk
isl_reset_n : in std_logic := '0'; -- reset_sink.reset_n
oslv_gpios : inout std_logic_vector(7 downto 0) := (others => '0') -- conduit_end.export
);
end entity cb20_gpio_block_1;
architecture rtl of cb20_gpio_block_1 is
component avalon_gpio_interface is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component avalon_gpio_interface;
begin
number_of_gpios_check : if number_of_gpios /= 8 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
unique_id_check : if unique_id /= "00010010011100000101000000000010" generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
gpio_block_1 : component avalon_gpio_interface
generic map (
number_of_gpios => 8,
unique_id => "00010010011100000101000000000010"
)
port map (
oslv_avs_read_data => oslv_avs_read_data, -- avalon_slave_0.readdata
islv_avs_address => islv_avs_address, -- .address
isl_avs_read => isl_avs_read, -- .read
isl_avs_write => isl_avs_write, -- .write
osl_avs_waitrequest => osl_avs_waitrequest, -- .waitrequest
islv_avs_write_data => islv_avs_write_data, -- .writedata
islv_avs_byteenable => islv_avs_byteenable, -- .byteenable
isl_clk => isl_clk, -- clock_sink.clk
isl_reset_n => isl_reset_n, -- reset_sink.reset_n
oslv_gpios => oslv_gpios -- conduit_end.export
);
end architecture rtl; -- of cb20_gpio_block_1
| apache-2.0 | 7933fa99e11c0ec618ffa67a7cc1fbae | 0.522166 | 3.538324 | false | false | false | false |
xiadz/oscilloscope | src/screen_position_gen.vhd | 1 | 4,551 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity screen_position_gen is
port (
-- inputs
nrst : in std_logic;
clk108 : in std_logic;
vblank : in std_logic;
in_line_change : in std_logic;
in_page_change : in std_logic;
in_column : in integer range 0 to 1279;
in_column_change : in std_logic;
-- outputs
segment : out integer range 0 to 15;
segment_change : out std_logic;
subsegment : out integer range 0 to 3;
subsegment_change : out std_logic;
line : out integer range 0 to 15;
out_line_change : out std_logic;
out_column : out integer range 0 to 1279;
out_column_mod_8 : out integer range 0 to 7;
out_column_div_8 : out integer range 0 to 159;
out_column_change : out std_logic;
out_page_change : out std_logic;
active_pixgen_source : out PIXGEN_SOURCE_T
);
end screen_position_gen;
architecture behavioral of screen_position_gen is
signal internal_segment : integer range 0 to 15;
signal internal_subsegment : integer range 0 to 3;
signal internal_line : integer range 0 to 15;
signal next_segment : integer range 0 to 15;
signal next_subsegment : integer range 0 to 3;
signal next_line : integer range 0 to 15;
begin
segment <= internal_segment;
subsegment <= internal_subsegment;
line <= internal_line;
-- This process calculates next_line, next_subsegment, next_segment signals
process (in_line_change, in_page_change, internal_segment, internal_subsegment, internal_line) is
begin
if in_page_change = '1' then
next_line <= 0;
next_subsegment <= 0;
next_segment <= 0;
else
if in_line_change = '1' then
if internal_line = 15 then
next_line <= 0;
if internal_subsegment = 3 then
next_subsegment <= 0;
if internal_segment = 15 then
next_segment <= 0;
else
next_segment <= internal_segment + 1;
end if;
else
next_subsegment <= internal_subsegment + 1;
next_segment <= internal_segment;
end if;
else
next_line <= internal_line + 1;
next_subsegment <= internal_subsegment;
next_segment <= internal_segment;
end if;
else
next_line <= internal_line;
next_subsegment <= internal_subsegment;
next_segment <= internal_segment;
end if;
end if;
end process;
-- This proces generates all output signals
process (clk108, nrst) is
begin
if nrst = '0' then
elsif rising_edge (clk108) then
internal_line <= next_line;
internal_subsegment <= next_subsegment;
internal_segment <= next_segment;
out_line_change <= in_line_change;
if internal_subsegment /= next_subsegment then
subsegment_change <= '1';
else
subsegment_change <= '0';
end if;
if internal_segment /= next_segment then
segment_change <= '1';
else
segment_change <= '0';
end if;
out_column <= in_column;
out_column_mod_8 <= in_column mod 8;
out_column_div_8 <= in_column / 8;
out_column_change <= in_column_change;
out_page_change <= in_page_change;
if vblank = '1' then
active_pixgen_source <= BLANK_PIXGEN_T;
elsif next_segment < 14 then
if next_subsegment /= 3 then
active_pixgen_source <= TRACE_PIXGEN_T;
else
active_pixgen_source <= TIME_BASE_PIXGEN_T;
end if;
else
active_pixgen_source <= SETTINGS_PIXGEN_T;
end if;
end if;
end process;
end architecture behavioral;
| mit | c3af7cc063044268bd8c3381b07757d3 | 0.497253 | 4.505941 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_source/slot_to_io_bridge.vhd | 1 | 3,420 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2012 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Bus bridge between C64 Slot cycles and internal I/O bus.
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the bus-bridge between the C64 I/O
-- expansion and the internal I/O bus to the peripherals.
-- Due to the nature of the I/O bus, reads are not yet implemented.
-- In order to make this work an io_bus read shall be initiated
-- when a read takes place, but before the end of the C64 cycle.
-- The necessary signal is not defined yet in the slot_bus
-- definition.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
entity slot_to_io_bridge is
generic (
g_io_base : unsigned(19 downto 0);
g_slot_start : unsigned(8 downto 0);
g_slot_stop : unsigned(8 downto 0) );
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic := '1';
irq_in : in std_logic := '0';
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
io_req : out t_io_req;
io_resp : in t_io_resp );
end entity;
architecture rtl of slot_to_io_bridge is
signal last_read : std_logic_vector(7 downto 0);
signal reg_output : std_logic;
begin
slot_resp.nmi <= '0';
slot_resp.irq <= irq_in and enable;
slot_resp.data <= last_read when reg_output='1' else X"00";
process(clock)
variable addr : unsigned(8 downto 0);
begin
if rising_edge(clock) then
io_req <= c_io_req_init;
-- writes
addr := slot_req.io_address(8 downto 0);
if (addr >= g_slot_start) and (addr <= g_slot_stop) and (enable = '1') then
if slot_req.io_write='1' then
io_req.write <= '1';
io_req.address <= g_io_base + (addr - g_slot_start);
io_req.data <= slot_req.data;
end if;
end if;
-- reads
addr := slot_req.bus_address(8 downto 0);
if (addr >= g_slot_start) and (addr <= g_slot_stop) and (enable = '1') then
if slot_req.io_read_early='1' then
io_req.read <= '1';
io_req.address <= g_io_base + (addr - g_slot_start);
last_read <= X"AA";
end if;
end if;
if io_resp.ack = '1' then
last_read <= io_resp.data;
end if;
end if;
end process;
-- reads
reg_output <= enable when (slot_req.bus_address(8 downto 0) >= g_slot_start) and
(slot_req.bus_address(8 downto 0) <= g_slot_stop) else '0';
slot_resp.reg_output <= reg_output;
end architecture;
| gpl-3.0 | 3875a56a42cac66801f132e80e45bdb8 | 0.461404 | 3.877551 | false | false | false | false |
ringof/radiofist_audio | testbench/tb_sinc3_filter.vhd | 1 | 1,914 | -- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See licence.txt for details
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_sinc3_filter IS
END tb_sinc3_filter;
ARCHITECTURE behavior OF tb_sinc3_filter IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sinc3_filter
PORT(
reset : IN std_logic;
din : IN std_logic;
in_clk : IN std_logic;
out_clk : IN std_logic;
dout : OUT std_logic_vector(24 downto 0)
);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal din : std_logic := '0';
signal in_clk : std_logic := '0';
signal out_clk : std_logic := '0';
--Outputs
signal dout : std_logic_vector(24 downto 0);
-- Clock period definitions
constant in_clk_period : time := 31.25 ns;
constant out_clk_period : time := 1250 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sinc3_filter PORT MAP (
reset => reset,
din => din,
in_clk => in_clk,
out_clk => out_clk,
dout => dout
);
-- Clock process definitions
in_clk_process :process
begin
in_clk <= '0';
wait for in_clk_period/2;
in_clk <= '1';
wait for in_clk_period/2;
end process;
out_clk_process :process
begin
out_clk <= '0';
wait for out_clk_period/2;
out_clk <= '1';
wait for out_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '1';
wait for in_clk_period*10;
reset <= '0';
-- insert stimulus here
wait for out_clk_period;
din <= '0';
wait for out_clk_period;
din <= '1';
wait for out_clk_period;
din <= '0';
wait;
end process;
END;
| mit | f36ec153c811731e94d9da939c905e23 | 0.562696 | 3.346154 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/wd177x.vhd | 1 | 16,759 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
-- Concept:
-- The actual commands are implemented by the application software.
-- This allows direct coupling between a file and the read/write commands that
-- the drive performs. The drawback is maybe a timing incompatibility, but it
-- is currently assumed that this is not as strict as on a 1541. So this may
-- not be an issue. The "window" through which data is passed is located in
-- external memory. The location and length are determined by the software
-- and the actual transfer to/from the CPU in the 1571/1581 is done
-- autonomously by this block:
--
-- 'Read' command: (6502 <- data <- application)
-- * 1581 performs the seek (through other commands)
-- * 1581 writes the read command into the WD177x register
-- * This block generates an interrupt to the appication software
-- and sets the busy bit.
-- * Application software interprets the command, and places the
-- data to be read in a memory block and passes the pointer to
-- it to the 'DMA' registers. -> Can the pointer be fixed?!
-- * 1581 will see data appearing in the data register through the
-- data valid bit (S1). Reading the register pops the data, and
-- DMA controller places new data until all bytes have been
-- transferred.
-- * This block clears the busy bit and the command completes.
--
-- 'Write' commands: (6502 -> data -> application)
-- * 1581 writes the write command into the WD177x register
-- * Block sets the busy bit and generates the IRQ to the application
-- * Application software interprets the command, and sets the
-- memory write address in the DMA controller and starts it.
-- * The block keeps 'DRQ' (S1) asserted for as long as it accepts data
-- * When all bytes are transferred, another IRQ is generated.
-- * The application recognizes that a write has completed and
-- processes the data.
-- * Application clears the busy bit, possibly sets the status bits
-- and the command completes.
--
-- 'Force Interrupt' command aborts the current transfer. In case of
-- a read, the DMA controller is reset and the busy bit is cleared.
-- In case of a write, an interrupt is generated (because of the
-- command), and the DMA controller is stopped. The IRQ causes the
-- application software to know that the write has been aborted.
--
-- So, commands that transfer data TO the 1581 CPU are simply handled
-- by one call to the application software, and the logic completes it.
-- Commands that transfer data FROM the 1581 CPU are handled by two
-- calls to the application software; one to request a memory pointer
-- and one to process the data and reset the busy bit / complete the
-- command programmatically.
--
entity wd177x is
generic (
g_tag : std_logic_vector(7 downto 0) := X"03" );
port (
clock : in std_logic;
clock_en : in std_logic; -- only for register access
reset : in std_logic;
tick_1kHz : in std_logic;
tick_4MHz : in std_logic;
-- register interface from 6502
addr : in unsigned(1 downto 0);
wen : in std_logic;
ren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- track stepper interface (for audio samples)
motor_en : in std_logic; -- for index pulse
stepper_en : in std_logic;
step : out std_logic_vector(1 downto 0);
cur_track : in unsigned(6 downto 0) := (others => '0');
do_track_out : out std_logic;
do_track_in : out std_logic;
-- I/O interface from application CPU
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic );
end entity;
architecture behavioral of wd177x is
signal mem_rwn : std_logic;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
signal mem_request : std_logic := '0';
signal status_idx : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal track : std_logic_vector(7 downto 0);
signal sector : std_logic_vector(7 downto 0);
signal command : std_logic_vector(7 downto 0) := X"00";
signal disk_data : std_logic_vector(7 downto 0) := X"00";
signal disk_wdata_valid : std_logic;
signal disk_rdata_valid : std_logic;
alias st_motor_on : std_logic is status(7);
alias st_write_prot : std_logic is status(6);
alias st_rectype_spinup : std_logic is status(5);
alias st_rec_not_found : std_logic is status(4);
alias st_crc_error : std_logic is status(3);
alias st_lost_data : std_logic is status(2);
alias st_data_request : std_logic is status(1);
alias st_busy : std_logic is status(0);
signal dma_mode : std_logic_vector(1 downto 0);
signal transfer_addr : unsigned(23 downto 0) := (others => '0');
signal transfer_len : unsigned(13 downto 0) := (others => '0');
type t_dma_state is (idle, do_read, reading, do_write, writing, write_delay);
signal dma_state : t_dma_state;
-- Command queue
signal command_fifo_din : std_logic_vector(8 downto 0);
signal command_fifo_dout : std_logic_vector(8 downto 0);
signal command_fifo_push : std_logic;
signal command_fifo_pop : std_logic;
signal command_fifo_valid : std_logic;
signal completion : std_logic;
signal write_delay_cnt : unsigned(7 downto 0);
-- Stepper
signal goto_track : unsigned(6 downto 0);
signal step_time : unsigned(4 downto 0);
signal step_busy : std_logic;
signal index_out : std_logic;
signal index_enable : std_logic := '0';
signal index_polarity : std_logic := '0';
begin
mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0';
mem_req.address <= "00" & transfer_addr;
mem_req.data <= disk_data;
mem_req.read_writen <= mem_rwn;
mem_req.request <= mem_request;
mem_req.size <= "00"; -- one byte at a time
mem_req.tag <= g_tag;
process(status, index_out, index_enable, index_polarity, command)
begin
status_idx <= status;
if command(7) = '0' and index_enable = '1' then -- Type I command
status_idx(1) <= index_out xor index_polarity;
end if;
end process;
with addr select rdata <=
status_idx when "00",
track when "01",
sector when "10",
disk_data when others;
process(clock)
variable v_addr : unsigned(3 downto 0);
begin
if rising_edge(clock) then
command_fifo_push <= '0';
command_fifo_pop <= '0';
if wen = '1' and clock_en = '1' then
case addr is
when "00" =>
if st_busy = '0' or wdata(7 downto 4) = X"D" then
command <= wdata;
st_busy <= '1';
completion <= '0';
command_fifo_push <= '1';
disk_wdata_valid <= '0';
end if;
when "01" =>
track <= wdata;
when "10" =>
sector <= wdata;
when "11" =>
disk_data <= wdata;
disk_wdata_valid <= '1';
when others =>
null;
end case;
end if;
if ren = '1' and clock_en = '1' then
case addr is
when "11" =>
disk_rdata_valid <= '0';
if disk_rdata_valid = '1' then
st_data_request <= '0';
end if;
when others =>
null; -- no other operations upon a read so far
end case;
end if;
io_resp <= c_io_resp_init;
v_addr := io_req.address(3 downto 0);
if io_req.write = '1' then
io_resp.ack <= '1';
case v_addr is
when X"0" =>
index_enable <= io_req.data(0);
index_polarity <= io_req.data(1);
when X"1" =>
track <= io_req.data;
when X"4" =>
status <= status and not io_req.data;
when X"5" =>
status <= status or io_req.data;
when X"6" =>
command_fifo_pop <= '1';
when X"7" =>
dma_mode <= io_req.data(1 downto 0); -- 00 is off, 01 = read (to 1581), 10 = write (to appl)
when X"8" =>
transfer_addr(7 downto 0) <= unsigned(io_req.data);
when X"9" =>
transfer_addr(15 downto 8) <= unsigned(io_req.data);
when X"A" =>
transfer_addr(23 downto 16) <= unsigned(io_req.data);
when X"C" =>
transfer_len(7 downto 0) <= unsigned(io_req.data);
when X"D" =>
transfer_len(13 downto 8) <= unsigned(io_req.data(5 downto 0));
when X"E" =>
goto_track <= unsigned(io_req.data(goto_track'range));
when X"F" =>
step_time <= unsigned(io_req.data(4 downto 0));
when others =>
null;
end case;
end if;
if io_req.read = '1' then
io_resp.ack <= '1';
case v_addr is
when X"0" =>
io_resp.data <= command_fifo_dout(7 downto 0);
when X"1" =>
io_resp.data <= track;
when X"2" =>
io_resp.data <= sector;
when X"3" =>
io_resp.data <= disk_data;
when X"4"|X"5" =>
io_resp.data <= status;
when X"6" =>
io_resp.data(0) <= command_fifo_dout(8);
io_resp.data(7) <= command_fifo_valid;
when X"7" =>
io_resp.data(1 downto 0) <= dma_mode;
-- when X"8" =>
-- io_resp.data <= std_logic_vector(transfer_addr(7 downto 0));
-- when X"9" =>
-- io_resp.data <= std_logic_vector(transfer_addr(15 downto 8));
-- when X"A" =>
-- io_resp.data <= std_logic_vector(transfer_addr(23 downto 16));
when X"C" =>
io_resp.data <= std_logic_vector(transfer_len(7 downto 0));
when X"D" =>
io_resp.data(5 downto 0) <= std_logic_vector(transfer_len(13 downto 8));
when X"E" =>
io_resp.data(0) <= step_busy;
when X"F" =>
io_resp.data(4 downto 0) <= std_logic_vector(step_time);
when others =>
null;
end case;
end if;
case dma_state is
when idle =>
if dma_mode = "01" then
if disk_rdata_valid = '0' then
dma_state <= do_read;
end if;
elsif dma_mode = "10" then
st_data_request <= '1';
if disk_wdata_valid = '1' then
dma_state <= do_write;
st_data_request <= '0';
disk_wdata_valid <= '0';
end if;
else -- no dma
st_data_request <= '0';
disk_wdata_valid <= '0';
end if;
when do_read =>
if transfer_len = 0 then
st_busy <= '0';
dma_mode <= "00";
dma_state <= idle;
else
mem_request <= '1';
mem_rwn <= '1';
dma_state <= reading;
end if;
when reading =>
if mem_rack = '1' then
mem_request <= '0';
end if;
if mem_dack = '1' then
disk_data <= mem_resp.data;
disk_rdata_valid <= '1';
st_data_request <= '1';
transfer_len <= transfer_len - 1;
transfer_addr <= transfer_addr + 1;
dma_state <= idle;
end if;
when do_write =>
mem_request <= '1';
mem_rwn <= '0';
transfer_len <= transfer_len - 1;
dma_state <= writing;
when writing =>
write_delay_cnt <= X"FF"; -- 64 us
if mem_rack = '1' then
mem_request <= '0';
transfer_addr <= transfer_addr + 1;
dma_state <= idle;
if transfer_len = 0 then
dma_mode <= "11"; -- write complete
dma_state <= write_delay;
completion <= '1';
command_fifo_push <= '1';
end if;
end if;
when write_delay =>
if write_delay_cnt = 0 then
st_busy <= '0';
dma_state <= idle;
elsif tick_4MHz = '1' then
write_delay_cnt <= write_delay_cnt - 1;
end if;
when others =>
null;
end case;
if reset = '1' then
mem_request <= '0';
mem_rwn <= '1';
disk_wdata_valid <= '0';
disk_rdata_valid <= '0';
track <= X"01";
sector <= X"00";
command <= X"00";
status <= X"00";
dma_mode <= "00";
step_time <= "01100";
completion <= '0';
goto_track <= to_unsigned(0, goto_track'length);
write_delay_cnt <= X"00";
end if;
end if;
end process;
i_cmd_fifo: entity work.sync_fifo
generic map (
g_depth => 7,
g_data_width => 9,
g_threshold => 4,
g_storage => "MRAM",
g_fall_through => true
)
port map (
clock => clock,
reset => reset,
flush => '0',
rd_en => command_fifo_pop,
wr_en => command_fifo_push,
din => command_fifo_din,
dout => command_fifo_dout,
valid => command_fifo_valid
);
command_fifo_din <= completion & command;
io_irq <= command_fifo_valid;
i_stepper: entity work.stepper
port map (
clock => clock,
reset => reset,
tick_1KHz => tick_1KHz,
goto_track => goto_track,
cur_track => cur_track, -- from drive mechanics
step_time => step_time,
do_track_in => do_track_in,
do_track_out => do_track_out,
enable => stepper_en,
busy => step_busy,
step => step,
motor_en => motor_en,
index_out => index_out
);
end architecture;
| gpl-3.0 | 73442324dc6df34458cec2737ebbe9fc | 0.4585 | 4.172019 | false | false | false | false |
andreamerello/spartan-eth-tester | TxSample.vhd | 1 | 5,462 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TxSample is
Port ( Txck : in STD_LOGIC;
Txen : out STD_LOGIC;
Tx0 : out STD_LOGIC;
Tx1 : out STD_LOGIC;
Tx2 : out STD_LOGIC;
Tx3 : out STD_LOGIC;
Rx0 : in STD_LOGIC;
Rx1 : in STD_LOGIC;
Rx2 : in STD_LOGIC;
Rx3 : in STD_LOGIC;
Rxdv : in STD_LOGIC;
Rxer: in STD_LOGIC;
Phynrst : out STD_LOGIC;
Mainck: in STD_LOGIC;
Button: in STD_LOGIC;
Main_rst: in STD_LOGIC;
Led0: out STD_LOGIC;
Led1: out STD_LOGIC);
end TxSample;
architecture Behavioral of TxSample is
signal phy_ok: std_logic;
signal txrq: std_logic;
signal s_txrq: std_logic;
signal s1_txrq: std_logic;
signal tx_run: std_logic;
signal s1_tx_run: std_logic;
signal s_tx_run: std_logic;
signal s1_button: std_logic;
signal s_button: std_logic;
signal reset_counter: std_logic_vector (24 downto 0);
signal state: std_logic_vector (7 downto 0);
signal debounced_button: std_logic;
signal prev_button: std_logic;
signal stable_counter: std_logic_vector (24 downto 0);
signal prev_debounced_button: std_logic;
signal Main_nrst: std_logic;
begin
Main_nrst <= not Main_rst;
Led1 <= Main_nrst;
resetwait: process(Mainck, Main_nrst)
begin
if (Main_nrst = '0') then
reset_counter <= (others => '0');
elsif (Mainck'event AND Mainck = '1') then
reset_counter <= std_logic_vector(unsigned(reset_counter) + 1);
end if;
end process;
resetphy: process(Mainck, Main_nrst)
begin
if (Main_nrst = '0') then
Phynrst <= '0';
phy_ok <= '0';
elsif (Mainck'event AND Mainck = '1') then
if (unsigned(reset_counter) = 100000) then
Phynrst <= '1';
end if;
if (unsigned(reset_counter) = 110000) then
phy_ok <= '1';
end if;
end if;
end process;
debouncer: process(Mainck, Main_nrst)
begin
if (Main_nrst = '0') then
debounced_button <= '0';
stable_counter <= (others => '0');
prev_button <= '0';
elsif (Mainck'event AND Mainck = '1') then
if (s_button = prev_button) then
-- stable for 80mS
if (unsigned(stable_counter) = x"3fffff") then
stable_counter <= (others => '0');
debounced_button <= s_button;
else
stable_counter <= std_logic_vector(unsigned(stable_counter) + 1);
end if;
else
stable_counter <= (others => '0');
end if;
prev_button <= s_button;
end if;
end process;
trigger: process(Mainck, Main_nrst)
begin
if (Main_nrst = '0') then
txrq <= '0';
prev_debounced_button <= '0';
elsif (Mainck'event and Mainck = '1') then
if (phy_ok = '1' and debounced_button = '1' and prev_debounced_button = '0' and s_tx_run = '0') then
txrq <= '1';
elsif (s_tx_run = '1') then
txrq <= '0';
end if;
prev_debounced_button <= debounced_button;
end if;
end process;
sync_Mainck: process(Mainck, Main_nrst)
begin
if (Main_nrst = '0') then
s_button <= '0';
s_tx_run <= '0';
s1_button <= '0';
s1_tx_run <= '0';
elsif (Mainck'event AND Mainck = '1') then
-- s1_txrq <= txrq;
-- s_txrq <= s1_txrq;
s1_button <= Button;
s_button <= s1_button;
s1_tx_run <= tx_run;
s_tx_run <= s1_tx_run;
end if;
end process;
sync_Txck: process(Txck, Main_nrst)
begin
if (Main_nrst = '0') then
s_txrq <= '0';
s1_txrq <= '0';
elsif (Txck'event and Txck = '1') then
s1_txrq <= txrq;
s_txrq <= s1_txrq;
end if;
end process;
ethtransmitter: process(Txck, Main_nrst)
begin
if (Main_nrst = '0') then
state <= (others => '0');
tx_run <= '0' ;
Led0 <= '0';
Txen <= '0';
Tx0 <= '0';
Tx1 <= '0';
Tx2 <= '0';
Tx3 <= '0';
elsif(Txck'event AND Txck = '0') then
if(s_txrq = '1' and tx_run = '0') then
tx_run <= '1';
state <= (others => '0');
Led0 <= '1';
end if;
if(tx_run = '1') then
if(unsigned(state) < 15) then --15
Txen <= '1';
Tx0 <= '1';
Tx1 <= '0';
Tx2 <= '1';
Tx3 <= '0';
elsif (unsigned(state) = 15 ) then --16
Tx0 <= '1';
Tx1 <= '0';
Tx2 <= '1';
Tx3 <= '1';
elsif (unsigned(state) > 15 AND unsigned(state) < (15+13)) then --12
Tx0 <= '1';
Tx1 <= '1';
Tx2 <= '1';
Tx3 <= '1';
elsif (unsigned(state) = (15+13)) then --7
Tx0 <= '1';
Tx1 <= '0';
Tx2 <= '0';
Tx3 <= '0'; --12+129 orig --12+4 -- 5 is discarded by atl1e
elsif (unsigned(state) > (15+12) AND unsigned(state) < (15 + 13 + 10)) then
Tx0 <= '0';
Tx1 <= '0';
Tx2 <= '0';
Tx3 <= '0';
elsif (unsigned(state) < (15 + 13 + 10 + 10)) then -- IFS
Txen <= '0';
else
Led0 <= '0';
tx_run <= '0';
end if;
state <= std_logic_vector(unsigned(state) + 1);
end if; -- tx_run
end if; -- ck
end process;
end Behavioral;
| gpl-3.0 | 1a7ca54a539e858983c751666c7875ab | 0.51721 | 3.137277 | false | false | false | false |
keyru/hdl-make | tests/counter/top/cyclone3_sk/vhdl/cyclone3_top.vhd | 2 | 1,398 | ----------------------------------------------------------------------
-- Design : Counter VHDL top module, Altera CycloneIII Starter Kit
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cyclone3_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(3 downto 0)
);
end cyclone3_top;
----------------------------------------------------------------------
architecture structure of cyclone3_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= not clear_i;
s_count <= not count_i;
led_o(3 downto 0) <= not s_Q(7 downto 4);
end architecture structure;
-----------------------------------------------------------------------
| gpl-3.0 | 69883a94edf1454b981ff595671182dd | 0.470672 | 3.915966 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/cs8900a/vhdl_source/cs8900a_bus.vhd | 1 | 7,546 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the bus-behavior of the CS8900A chip.
-- It is based on a dual ported memory, which can be read/written
-- from the cartridge port, as well as from the other CPU as I/O
-- device. This allows the software to emulate the functionality
-- of the link, while this hardware block only implements how the
-- chip behaves as seen from the cartrige port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity cs8900a_bus is
port (
clock : in std_logic;
reset : in std_logic;
bus_addr : in std_logic_vector(3 downto 0);
bus_write : in std_logic;
bus_read : in std_logic;
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
pp_addr : out unsigned(11 downto 0);
pp_write : out std_logic;
pp_read : out std_logic;
pp_tx_data : out std_logic; -- put
pp_rx_data : out std_logic; -- get
pp_wdata : out std_logic_vector(15 downto 0);
pp_rdata : in std_logic_vector(15 downto 0);
pp_new_rx_pkt : in std_logic );
end cs8900a_bus;
architecture gideon of cs8900a_bus is
-- The 8900A chip is accessed in WORDs, using alternately
-- even and odd bytes. Only PacketPage access in I/O mode
-- is supported.
constant c_rx_tx_data_0 : std_logic_vector(3 downto 1) := "000"; -- R/W
constant c_rx_tx_data_1 : std_logic_vector(3 downto 1) := "001"; -- R/W
constant c_tx_command : std_logic_vector(3 downto 1) := "010"; -- W
constant c_tx_length : std_logic_vector(3 downto 1) := "011"; -- W
constant c_isq : std_logic_vector(3 downto 1) := "100"; -- R
constant c_packet_page_pointer : std_logic_vector(3 downto 1) := "101"; -- R/W
constant c_packet_page_data_0 : std_logic_vector(3 downto 1) := "110"; -- R/W
constant c_packet_page_data_1 : std_logic_vector(3 downto 1) := "111"; -- R/W
constant c_lo_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0000"; -- R/W
constant c_hi_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0001"; -- R/W
constant c_lo_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0010"; -- R/W
constant c_hi_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0011"; -- R/W
constant c_lo_packet_page_pointer : std_logic_vector(3 downto 0) := "1010"; -- R/W
constant c_hi_packet_page_pointer : std_logic_vector(3 downto 0) := "1011"; -- R/W
constant c_lo_packet_page_data_0 : std_logic_vector(3 downto 0) := "1100"; -- R/W
constant c_hi_packet_page_data_0 : std_logic_vector(3 downto 0) := "1101"; -- R/W
constant c_lo_packet_page_data_1 : std_logic_vector(3 downto 0) := "1110"; -- R/W
constant c_hi_packet_page_data_1 : std_logic_vector(3 downto 0) := "1111"; -- R/W
signal packet_page_pointer : unsigned(11 downto 1);
signal packet_page_auto_inc : std_logic;
signal word_buffer : std_logic_vector(15 downto 0);
signal rx_count : integer range 0 to 2;
begin
pp_wdata <= word_buffer;
process(clock)
variable v_3bit_addr : std_logic_vector(3 downto 1);
begin
if rising_edge(clock) then
-- handle writes
pp_write <= '0';
pp_read <= '0';
pp_rx_data <= '0';
pp_tx_data <= '0';
pp_addr <= packet_page_pointer & '0';
v_3bit_addr := bus_addr(3 downto 1);
-- determine pp_addr for reads (default, will be overwritten by writes)
if bus_addr(3 downto 2)="00" then
case rx_count is
when 0 =>
pp_addr <= X"400";
when 1 =>
pp_addr <= X"402";
when others =>
pp_addr <= X"404";
end case;
if bus_read='1' and bus_addr(0)='1' then -- read from odd address
if rx_count /= 2 then
rx_count <= rx_count + 1;
pp_read <= '1';
else
pp_rx_data <= '1'; -- pop
end if;
end if;
end if;
if bus_write='1' then
if bus_addr(0)='0' then
word_buffer(7 downto 0) <= bus_wdata;
else
word_buffer(15 downto 8) <= bus_wdata;
case v_3bit_addr is
when c_rx_tx_data_0 | c_rx_tx_data_1 =>
pp_tx_data <= '1';
pp_write <= '1';
pp_addr <= X"A00";
when c_tx_command =>
pp_addr <= X"144";
pp_write <= '1';
when c_tx_length =>
pp_addr <= X"146";
pp_write <= '1';
when c_packet_page_pointer =>
packet_page_pointer <= unsigned(word_buffer(packet_page_pointer'range));
packet_page_auto_inc <= word_buffer(15);
when c_packet_page_data_0 | c_packet_page_data_1 =>
pp_write <= '1';
if packet_page_auto_inc='1' then
packet_page_pointer <= packet_page_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
if pp_new_tx_pkt='1' then
rx_count <= 0;
end if;
if reset='1' then
packet_page_pointer <= (others => '0');
packet_page_auto_inc <= '0';
end if;
end if;
end process;
-- determine output byte (combinatorial, since it's easy!)
with bus_addr select bus_rdata <=
pp_rdata(7 downto 0) when c_lo_rx_tx_data_0 | c_lo_rx_tx_data_1 | c_lo_packet_page_data_0 | c_lo_packet_page_data_1,
pp_rdata(15 downto 8) when c_hi_rx_tx_data_0 | c_hi_rx_tx_data_1 | c_hi_packet_page_data_0 | c_hi_packet_page_data_1,
std_logic_vector(packet_page_pointer(7 downto 1)) & '0' when c_lo_packet_page_pointer,
packet_page_auto_inc & "011" & std_logic_vector(packet_page_pointer(11 downto 8)) when c_hi_packet_page_pointer,
X"00" when others;
end;
| gpl-3.0 | 5f377d8fc5d1def7c181faf1a8207b99 | 0.456798 | 3.83825 | false | false | false | false |
chiggs/nvc | test/regress/toplevel1.vhd | 5 | 414 | entity toplevel1 is
generic (
WIDTH : integer := 6 );
port (
x : in bit_vector(WIDTH - 1 downto 0);
y : out bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of toplevel1 is
begin
y <= x after 1 ns;
process is
begin
assert x'length = 6;
assert y'length = 6;
assert x = "000000";
wait;
end process;
end architecture;
| gpl-3.0 | 64caf54a7ea76585ca9c403d5e7ee0ae | 0.55314 | 3.798165 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502/vhdl_source/alu.vhd | 1 | 4,815 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
generic (
support_bcd : boolean := true );
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic;
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
d_in : in std_logic;
data_a : in std_logic_vector(7 downto 0);
data_b : in std_logic_vector(7 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
data_out : out std_logic_vector(7 downto 0));
end alu;
architecture gideon of alu is
signal data_out_i : std_logic_vector(7 downto 0) := X"FF";
signal zero : std_logic;
signal sum_c : std_logic;
signal sum_n : std_logic;
signal sum_z : std_logic;
signal sum_v : std_logic;
signal sum_result : std_logic_vector(7 downto 0) := X"FF";
signal oper4 : std_logic_vector(3 downto 0);
begin
-- ORA $nn AND $nn EOR $nn ADC $nn STA $nn LDA $nn CMP $nn SBC $nn
with oper4 select data_out_i <=
data_a or data_b when "1000",
data_a and data_b when "1001",
data_a xor data_b when "1010",
sum_result when "1011" | "1110" | "1111",
data_b when others;
zero <= '1' when data_out_i = X"00" else '0';
sum: process(data_a, data_b, c_in, operation, d_in)
variable b : std_logic_vector(7 downto 0);
variable sum_l : std_logic_vector(4 downto 0);
variable sum_h : std_logic_vector(4 downto 0);
begin
-- for subtraction invert second operand
if operation(2)='1' then -- invert b
b := not data_b;
else
b := data_b;
end if;
-- sum_l(4) = carry of lower end, carry in is masked to '1' for CMP
sum_l := ('0' & data_a(3 downto 0)) + ('0' & b(3 downto 0)) + (c_in or not operation(0));
sum_h := ('0' & data_a(7 downto 4)) + ('0' & b(7 downto 4)) + sum_l(4);
if sum_l(3 downto 0)="0000" and sum_h(3 downto 0)="0000" then
sum_z <= '1';
else
sum_z <= '0';
end if;
sum_n <= sum_h(3);
sum_c <= sum_h(4);
sum_v <= (sum_h(3) xor data_a(7)) and (sum_h(3) xor data_b(7) xor operation(2));
-- fix up in decimal mode (not for CMP!)
if d_in='1' and support_bcd then
if operation(2)='0' then -- ADC
sum_h := ('0' & data_a(7 downto 4)) + ('0' & b(7 downto 4));
if sum_l(4) = '1' or sum_l(3 downto 2)="11" or sum_l(3 downto 1)="101" then -- >9 (10-11, 12-15)
sum_l := sum_l + ('0' & X"6");
sum_l(4) := '1';
end if;
-- negative when sum_h + sum_l(4) = 8
sum_h := sum_h + sum_l(4);
sum_n <= sum_h(3);
if sum_h(4) = '1' or sum_h(3 downto 2)="11" or sum_h(3 downto 1)="101" then --
sum_h := sum_h + 6;
sum_c <= '1';
end if;
-- carry and overflow are output after fix
-- sum_c <= sum_h(4);
-- sum_v <= (sum_h(3) xor data_a(7)) and (sum_h(3) xor data_b(7) xor operation(2));
elsif operation(0)='1' then -- SBC
-- flags are not adjusted in subtract mode
if sum_l(4) = '0' then
sum_l := sum_l - 6;
end if;
if sum_h(4) = '0' then
sum_h := sum_h - 6;
end if;
end if;
end if;
sum_result <= sum_h(3 downto 0) & sum_l(3 downto 0);
end process;
oper4 <= enable & operation;
with oper4 select c_out <=
sum_c when "1011" | "1111" | "1110",
c_in when others;
with oper4 select z_out <=
sum_z when "1011" | "1111" | "1110",
zero when "1000" | "1001" | "1010" | "1101",
z_in when others;
with oper4 select n_out <=
sum_n when "1011" | "1111",
data_out_i(7) when "1000" | "1001" | "1010" | "1101" | "1110",
n_in when others;
with oper4 select v_out <=
sum_v when "1011" | "1111",
v_in when others;
data_out <= data_out_i;
end gideon; | gpl-3.0 | c154b088b07080d0f5669b374bb25d4e | 0.435514 | 3.336798 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_source/packet_generator.vhd | 1 | 3,833 | -------------------------------------------------------------------------------
-- Title : packet_generator
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This is a module just to test the hardware
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity packet_generator is
port (
clock : in std_logic; -- 50 MHz RMII clock
reset : in std_logic;
eth_tx_data : out std_logic_vector(7 downto 0);
eth_tx_sof : out std_logic;
eth_tx_eof : out std_logic;
eth_tx_valid : out std_logic;
eth_tx_ready : in std_logic );
end entity;
architecture rtl of packet_generator is
signal delay : integer range 0 to 50000000;
signal byte_count : integer range 0 to 63;
type t_state is (idle, transmit);
signal state : t_state;
signal valid_i : std_logic;
signal eof : std_logic;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant c_packet : t_byte_array := (
X"00", X"22", X"15", X"32", X"BA", X"48", -- dest mac to desktop PC
X"00", X"01", X"23", X"45", X"67", X"89", -- source mac from local PHY
X"08", X"00", -- ethernet frame
-- IP
X"45", X"00", -- standard IP frame
X"00", X"30", -- total length = 20 + 8 + 20 = 48
X"12", X"34", -- ID
X"00", X"00", -- flags & fragment offset
X"20", X"11", -- TTL = 32, protocol = UDP
X"05", X"DA", -- checksum
X"C0", X"A8", X"00", X"F5", -- 192.168.0.245 (source)
X"C0", X"A8", X"00", X"6A", -- 192.168.0.106 (dest)
-- UDP
X"27", X"10", X"4E", X"20", --- port 10000 to 20000
X"00", X"1C", -- length
X"00", X"00", -- checksum
-- Payload
X"48", X"65", X"78", X"3A",
X"30", X"31", X"32", X"33", X"34", X"35", X"36", X"37",
X"38", X"39", X"41", X"42", X"43", X"44", X"45", X"46"
);
begin
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
byte_count <= 0;
eof <= '0';
if delay = 50000000 then
state <= transmit;
delay <= 0;
else
delay <= delay + 1;
end if;
when transmit =>
if valid_i = '0' or eth_tx_ready = '1' then
if eof = '1' then
valid_i <= '0';
state <= idle;
else
eth_tx_data <= c_packet(byte_count);
if byte_count = 0 then
eth_tx_sof <= '1';
else
eth_tx_sof <= '0';
end if;
if byte_count = c_packet'right then
eof <= '1';
else
eof <= '0';
end if;
valid_i <= '1';
byte_count <= byte_count + 1;
end if;
end if;
end case;
if reset='1' then
eth_tx_sof <= '0';
valid_i <= '0';
eof <= '0';
delay <= 0;
byte_count <= 0;
state <= idle;
end if;
end if;
end process;
eth_tx_valid <= valid_i;
eth_tx_eof <= eof;
end architecture;
| gpl-3.0 | 911d64271e8bbf8ad7219b17372a51c5 | 0.38586 | 3.959711 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/c1581_startup_tc.vhd | 1 | 9,373 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_bfm_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.c1541_pkg.all;
use work.tl_string_util_pkg.all;
use work.iec_bus_bfm_pkg.all;
entity c1581_startup_tc is
end;
architecture tc of c1581_startup_tc is
signal irq : std_logic;
constant c_wd177x_command : unsigned(11 downto 0) := X"100";
constant c_wd177x_track : unsigned(11 downto 0) := X"101";
constant c_wd177x_sector : unsigned(11 downto 0) := X"102";
constant c_wd177x_datareg : unsigned(11 downto 0) := X"103";
constant c_wd177x_status_clear : unsigned(11 downto 0) := X"104";
constant c_wd177x_status_set : unsigned(11 downto 0) := X"105";
constant c_wd177x_irq_ack : unsigned(11 downto 0) := X"106";
constant c_wd177x_dma_mode : unsigned(11 downto 0) := X"107";
constant c_wd177x_dma_addr : unsigned(11 downto 0) := X"108"; -- DWORD
constant c_wd177x_dma_len : unsigned(11 downto 0) := X"10C"; -- WORD
begin
i_harness: entity work.harness_c1581
port map (
io_irq => irq
);
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
bind_iec_bus_bfm("iec_bfm", bfm);
load_memory("../../../roms/1581-rom.318045-02.bin", dram, X"00008000");
load_memory("../../../roms/sounds.bin", dram, X"00010000");
wait for 20 us;
io_write(io, c_drvreg_power, X"01");
wait for 20 us;
io_write(io, c_drvreg_reset, X"00");
wait for 2500 ms;
iec_drf(bfm);
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait for 20 ms;
io_write(io, c_drvreg_inserted, X"01");
io_write(io, c_drvreg_diskchng, X"01");
wait for 200 ms;
iec_send_atn(bfm, X"28"); -- Drive 8, Listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_send_message(bfm, "N:AAP,01"); -- Format!
wait for 1000 ms;
wait;
end process;
-- Type Command 7 6 5 4 3 2 1 0
-- -------------------------------------------------------
-- I Restore 0 0 0 0 h v r1 r0
-- I Seek 0 0 0 1 h v r1 r0
-- I Step 0 0 1 u h v r1 r0
-- I Step in 0 1 0 u h v r1 r0
-- I Step out 0 1 1 u h v r1 r0
-- II Read sector 1 0 0 m h/s e 0/c 0
-- II Write sector 1 0 1 m h/s e p/c a
-- III Read address 1 1 0 0 h/0 e 0 0
-- III Read track 1 1 1 0 h/0 e 0 0
-- III Write track 1 1 1 1 h/0 e p/0 0
-- IV Force interrupt 1 1 0 1 i3 i2 i1 i0
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable cmd : std_logic_vector(7 downto 0);
variable byte : std_logic_vector(7 downto 0);
variable track : natural := 0;
variable sector : natural := 0;
variable dir : std_logic := '1';
variable side : std_logic := '0';
procedure do_step(update : std_logic) is
begin
if dir = '0' then
if track < 80 then
track := track + 1;
end if;
else
if track > 0 then
track := track - 1;
end if;
end if;
if update = '1' then
io_read(io, c_wd177x_track, byte);
if dir = '0' then
byte := std_logic_vector(unsigned(byte) + 1);
else
byte := std_logic_vector(unsigned(byte) - 1);
end if;
io_write(io, c_wd177x_track, byte);
end if;
end procedure;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
while true loop
wait until irq = '1';
io_read(io, c_wd177x_command, cmd);
report "Command: " & hstr(cmd);
wait for 50 us;
if cmd(7 downto 4) = "0000" then
report "WD1770 Command: Restore";
io_write(io, c_wd177x_track, X"00"); -- set track to zero
track := 0;
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 4) = "0001" then
io_read(io, c_wd177x_datareg, byte);
report "WD1770 Command: Seek: Track = " & integer'image(to_integer(unsigned(byte)));
io_write(io, c_wd177x_track, byte);
track := to_integer(unsigned(byte));
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "001" then
report "WD1770 Command: Step.";
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "010" then
report "WD1770 Command: Step In.";
dir := '1';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "011" then
report "WD1770 Command: Step Out.";
dir := '0';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "100" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Read Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"0000C000" ); -- read a piece of the ROM for now
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"01"); -- read
-- data transfer, so we are not yet done
elsif cmd(7 downto 5) = "101" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Write Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"02"); -- write
-- data transfer, so we are not yet done
elsif cmd(7 downto 4) = "1100" then
report "WD1770 Command: Read Address.";
write_memory_8(dram, X"00020000", std_logic_vector(to_unsigned(track, 8)) );
write_memory_8(dram, X"00020001", X"00" ); -- side (!!)
write_memory_8(dram, X"00020002", std_logic_vector(to_unsigned(sector, 8)) );
write_memory_8(dram, X"00020003", X"02" ); -- sector length = 512
write_memory_8(dram, X"00020004", X"F9" ); -- CRC1
write_memory_8(dram, X"00020005", X"5E" ); -- CRC2
io_write_32(io, c_wd177x_dma_addr, X"00020000" );
io_write(io, c_wd177x_dma_len, X"06");
io_write(io, c_wd177x_dma_len+1, X"00"); -- transfer 6 bytes
io_write(io, c_wd177x_dma_mode, X"01"); -- read
elsif cmd(7 downto 4) = "1110" then
report "WD1770 Command: Read Track (not implemented).";
elsif cmd(7 downto 4) = "1111" then
report "WD1770 Command: Write Track.";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"6A");
io_write(io, c_wd177x_dma_len+1, X"18"); -- 6250 bytes
io_write(io, c_wd177x_dma_mode, X"02"); -- write
elsif cmd(7 downto 4) = "1101" then
io_write(io, c_wd177x_dma_mode, X"00"); -- stop
io_write(io, c_wd177x_status_clear, X"01");
end if;
io_write(io, c_wd177x_irq_ack, X"00");
end loop;
end process;
end architecture;
| gpl-3.0 | bb7bfb1a411cb9bdc0236b6be87e117c | 0.479462 | 3.357092 | false | false | false | false |
chiggs/nvc | test/regress/slice2.vhd | 6 | 854 | entity slice2 is
end entity;
architecture test of slice2 is
procedure set_it(signal v : out bit_vector(7 downto 0);
x, y : in integer;
k : in bit_vector) is
begin
v(x downto y) <= k;
end procedure;
procedure set_it2(signal v : out bit_vector;
x, y : in integer;
k : in bit_vector) is
begin
v(x downto y) <= k;
end procedure;
signal vec : bit_vector(7 downto 0);
begin
process is
begin
set_it(vec, 3, 0, X"a");
wait for 1 ns;
assert vec = X"0a";
set_it(vec, 4, 1, X"f");
wait for 1 ns;
assert vec = X"1e";
set_it2(vec, 7, 4, X"f");
wait for 1 ns;
assert vec = X"fe";
wait;
end process;
end architecture;
| gpl-3.0 | 1fe0f42abd218c105057041d8354b51b | 0.474239 | 3.528926 | false | false | false | false |
chiggs/nvc | test/parse/error.vhd | 4 | 846 | architecture a of e is
begin
bad syntax;
x <= 2; x <= 1 + 2; -- Recovery
some more bad syntax;
x <= 2; x <= 1 + 2; -- Recovery
process
begin
end; -- Missing "process"
x <= 2; x <= 1 + 2; -- Recovery
foo: process is
begin
end process bar; -- Label does not match
process is
begin
end process bar; -- No initial label
b: block is
function "+" return boolean is
begin
my_if: if x > 5 then
null;
end if blah; -- Label does not match
x <= 2; x <= 1 + 2; -- Recovery
end function "-"; -- Label does not match
begin
end block;
end architecture;
| gpl-3.0 | 7c4e606715db31918abeff1967142ff8 | 0.416076 | 4.752809 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/proc_interrupt.vhd | 1 | 2,992 | library ieee;
use ieee.std_logic_1164.all;
entity proc_interrupt is
port (
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
irq_n : in std_logic;
nmi_n : in std_logic;
i_flag : in std_logic;
nmi_done : in std_logic;
reset_done : in std_logic;
interrupt : out std_logic;
vect_sel : out std_logic_vector(2 downto 1) );
end proc_interrupt;
architecture gideon of proc_interrupt is
signal irq_c : std_logic := '1';
signal irq_d1 : std_logic := '0';
signal nmi_c : std_logic := '0';
signal nmi_d1 : std_logic := '0';
signal nmi_d2 : std_logic := '0';
signal nmi_act : std_logic := '0';
signal nmi_act_comb : std_logic := '0';
signal vect_h : std_logic_vector(2 downto 1) := "10";
signal resetting : std_logic := '1';
-- 21
-- NMI 1 01-
-- RESET 1 10-
-- IRQ 1 11-
function calc_vec_addr(rst, irq, nmi : std_logic) return std_logic_vector is
variable v : std_logic_vector(2 downto 1);
begin
if rst='1' then
v := "10";
elsif nmi='1' then
v := "01";
else
v := "11";
end if;
return v;
end function;
begin
vect_sel <= vect_h;
interrupt <= (irq_d1 or nmi_act_comb);
irq_d1 <= not irq_c and not i_flag; -- Visual6502: INTP
-- For NMI we need to further investigate
-- http://visual6502.org/JSSim/expert.html?nmi0=13&nmi1=14&a=0000&d=78085828eaea4c&logmore=rdy,ir,State,irq,nmi,~IRQP,NMIP,882,INTG
-- Node 882 seems functionally equivalent to ~IRQP
process(clock)
begin
if rising_edge(clock) then
nmi_c <= not nmi_n;
-- synchronization flipflop (near PAD)
if clock_en='1' then
irq_c <= irq_n; -- in Visual6502 irq_c is called ~IRQP
end if;
if clock_en='1' then
nmi_d1 <= nmi_c;
end if;
end if;
end process;
vect_h <= calc_vec_addr(resetting, irq_d1, nmi_act_comb);
nmi_act_comb <= (nmi_d1 and not nmi_d2) or nmi_act;
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
nmi_d2 <= nmi_d1;
if nmi_done = '1' then
nmi_act <= '0';
elsif nmi_d2 = '0' and nmi_d1 = '1' then -- edge
nmi_act <= '1';
end if;
if reset_done = '1' then
resetting <= '0';
end if;
end if;
if reset='1' then
nmi_act <= '0';
resetting <= '1';
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 4398487eb7f8237a64e6bc87206d868f | 0.46357 | 3.528302 | false | false | false | false |
fpgaddicted/5bit-shift-register-structural- | decoder_states.vhd | 1 | 3,352 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:59:22 04/09/2017
-- Design Name:
-- Module Name: decoder_states - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity decoder_states is
Port ( op : in STD_LOGIC_VECTOR (3 downto 0);
data_o : buffer STD_LOGIC_VECTOR (0 to 7);
anode_s : in STD_LOGIC_VECTOR (3 downto 0));
end decoder_states;
architecture Behavioral of decoder_states is
begin
process (op,anode_s,data_o)
begin
case anode_s is
when "0111" =>
case op is
when "0000" => data_o <= "11100011"; -- L
when "0001" => data_o <= "01001001"; -- S
when "0010" => data_o <= "01001001"; -- S
when "0011" => data_o <= "11000001"; -- b
when "0100" => data_o <= "11000001"; -- b
when "0101" => data_o <= "11100101"; -- c
when "0110" => data_o <= "11100101"; -- c
when "0111" => data_o <= "11010001"; -- h
when "1000" => data_o <= "11100101"; -- c
when others => data_o <= "11111110"; -- blank
end case;
when "1011" =>
case op is
when "0000" => data_o <= "11000101"; -- o
when "0001" => data_o <= "11110101"; -- r
when "0010" => data_o <= "11100011"; -- L
when "0011" => data_o <= "11110101"; --
when "0100" => data_o <= "11110101";
when "0101" => data_o <= "11000101";
when "0110" => data_o <= "11000101";
when "0111" => data_o <= "11000101";
when "1000" => data_o <= "10011111";
when others => data_o <= "11111110"; -- blank
end case;
when "1101" =>
case op is
when "0000" => data_o <= "00000101"; -- a
when "0001" => data_o <= "11110011"; -- l
when "0010" => data_o <= "11100011"; -- L
when "0011" => data_o <= "11110010"; -- l.
when "0100" => data_o <= "11110010"; -- l.
when "0101" => data_o <= "11111111";
when "0110" => data_o <= "11111111";
when "0111" => data_o <= "11110011";
when "1000" => data_o <= "11110101";
when others => data_o <= "11111110"; -- blank
end case;
when others =>
case op is
when "0000" => data_o <= "10000101"; --d
when "0001" => data_o <= "11111111"; -- blank
when "0010" => data_o <= "11111111"; -- blank
when "0011" => data_o <= "11110101"; -- r
when "0100" => data_o <= "11100011"; --L
when "0101" => data_o <= "10011111"; --1
when "0110" => data_o <= "00100101"; --2
when "0111" => data_o <= "10000101"; --d
when "1000" => data_o <= "11111111"; --blank
when others => data_o <= "11111110"; -- blank
end case;
end case;
end process;
end Behavioral;
| gpl-3.0 | 9ef6da549010ba12f09d7e31312dfe46 | 0.503878 | 3.379032 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_host_controller.vhd | 2 | 8,088 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_host_controller
-- Date:2015-01-18
-- Author: Gideon
-- Description:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.usb_pkg.all;
use work.usb_cmd_pkg.all;
entity usb_host_controller is
generic (
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
ulpi_nxt : in std_logic;
ulpi_dir : in std_logic;
ulpi_stp : out std_logic;
ulpi_data : inout std_logic_vector(7 downto 0);
--
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp );
end entity;
architecture arch of usb_host_controller is
signal nano_addr : unsigned(7 downto 0);
signal nano_write : std_logic;
signal nano_read : std_logic;
signal nano_wdata : std_logic_vector(15 downto 0);
signal nano_rdata : std_logic_vector(15 downto 0);
signal nano_stall : std_logic := '0';
signal reg_read : std_logic := '0';
signal reg_write : std_logic := '0';
signal reg_ack : std_logic;
signal reg_address : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
signal reg_rdata : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal speed : std_logic_vector(1 downto 0) := "10";
signal do_chirp : std_logic;
signal chirp_data : std_logic;
signal sof_enable : std_logic;
signal operational : std_logic;
signal connected : std_logic;
signal buf_address : unsigned(10 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal usb_tx_req : t_usb_tx_req;
signal usb_tx_resp : t_usb_tx_resp;
signal usb_rx : t_usb_rx;
signal usb_cmd_req : t_usb_cmd_req;
signal usb_cmd_resp : t_usb_cmd_resp;
signal io_data_rdata : std_logic_vector(7 downto 0);
signal io_data_en : std_logic;
signal io_data_ack : std_logic;
signal io_reg_req : t_io_req;
signal io_reg_resp : t_io_resp;
signal io_nano_req : t_io_req;
signal io_nano_resp : t_io_resp;
signal io_data_req : t_io_req;
signal io_data_resp : t_io_resp;
signal io_usb_reg_req : t_io_req;
signal io_usb_reg_resp : t_io_resp;
begin
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 12,
g_range_hi => 13,
g_ports => 3 )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp,
reqs(0) => io_reg_req,
reqs(1) => io_nano_req,
reqs(2) => io_data_req,
resps(0) => io_reg_resp,
resps(1) => io_nano_resp,
resps(2) => io_data_resp );
i_bridge: entity work.io_bus_bridge
generic map (
g_addr_width => 4 )
port map (
clock_a => sys_clock,
reset_a => sys_reset,
req_a => io_reg_req,
resp_a => io_reg_resp,
clock_b => clock,
reset_b => reset,
req_b => io_usb_reg_req,
resp_b => io_usb_reg_resp );
i_intf: entity work.usb_host_interface
generic map (
g_simulation => g_simulation )
port map (
clock => clock,
reset => reset,
usb_rx => usb_rx,
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp,
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_rdata => reg_rdata,
reg_ack => reg_ack,
do_chirp => do_chirp,
chirp_data => chirp_data,
status => status,
speed => speed,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_dir => ulpi_dir,
ulpi_data => ulpi_data );
i_seq: entity work.host_sequencer
port map (
clock => clock,
reset => reset,
buf_address => buf_address,
buf_en => buf_en,
buf_we => buf_we,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
sof_enable => sof_enable,
speed => speed,
usb_cmd_req => usb_cmd_req,
usb_cmd_resp => usb_cmd_resp,
usb_rx => usb_rx,
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp );
i_mem: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => 11,
g_storage => "block" )
port map (
a_clock => clock,
a_address => buf_address,
a_rdata => buf_rdata,
a_wdata => buf_wdata,
a_en => buf_en,
a_we => buf_we,
b_clock => sys_clock,
b_address => io_data_req.address(10 downto 0),
b_rdata => io_data_rdata,
b_wdata => io_data_req.data,
b_en => io_data_en,
b_we => io_data_req.write );
process(sys_clock)
begin
if rising_edge(sys_clock) then
io_data_ack <= io_data_req.read or io_data_req.write;
end if;
end process;
io_data_en <= io_data_req.read or io_data_req.write;
io_data_resp.data <= io_data_rdata when io_data_ack='1' else X"00";
io_data_resp.ack <= io_data_ack;
io_data_resp.irq <= '0';
i_nano_io: entity work.nano_minimal_io
generic map (
g_support_suspend => false )
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => nano_stall,
reg_read => reg_read,
reg_write => reg_write,
reg_ack => reg_ack,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_rdata => reg_rdata,
status => status,
do_chirp => do_chirp,
chirp_data => chirp_data,
connected => connected,
operational => operational,
suspended => open,
sof_enable => sof_enable,
speed => speed );
i_cmd_io: entity work.usb_cmd_io
port map (
clock => clock,
reset => reset,
io_req => io_usb_reg_req,
io_resp => io_usb_reg_resp,
-- status (maybe only temporary)
connected => connected,
operational => operational,
speed => speed,
cmd_req => usb_cmd_req,
cmd_resp => usb_cmd_resp );
i_nano: entity work.nano
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => nano_stall,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => io_nano_req,
sys_io_resp => io_nano_resp );
end arch;
| gpl-3.0 | 35909ad28542b4a64d6432c2844b94bf | 0.465381 | 3.516522 | false | false | false | false |
chiggs/nvc | test/regress/shift2.vhd | 3 | 3,807 | entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100") ror -6 = "11001"
report "ror -6 is broken" severity error;
assert bit_vector'("11100") ror -5 = "11100"
report "ror -5 is broken" severity error;
assert bit_vector'("11100") ror -4 = "01110"
report "ror -4 is broken" severity error;
assert bit_vector'("11100") ror -3 = "00111"
report "ror -3 is broken" severity error;
assert bit_vector'("11100") ror -2 = "10011"
report "ror -2 is broken" severity error;
assert bit_vector'("11100") ror -1 = "11001"
report "ror -1 is broken" severity error;
assert bit_vector'("11100") ror 0 = "11100"
report "ror 0 is broken" severity error;
assert bit_vector'("11100") ror 1 = "01110"
report "ror 1 is broken" severity error;
assert bit_vector'("11100") ror 2 = "00111"
report "ror 2 is broken" severity error;
assert bit_vector'("11100") ror 3 = "10011"
report "ror 3 is broken" severity error;
assert bit_vector'("11100") ror 4 = "11001"
report "ror 4 is broken" severity error;
assert bit_vector'("11100" ror 5) = "11100"
report "ror 5 is broken" severity error;
assert bit_vector'("11100") ror 6 = "01110"
report "ror 6 is broken" severity error;
assert bit_vector'("11100") ror 7 = "00111"
report "ror 7 is broken" severity error;
assert bit_vector'("11100") ror 8 = "10011"
report "ror 8 is broken" severity error;
-- ROL
assert bit_vector'("11100") rol -8 = "10011"
report "rol -8 is broken" severity error;
assert bit_vector'("11100") rol -7 = "00111"
report "rol -7 is broken" severity error;
assert bit_vector'("11100") rol -6 = "01110"
report "rol -6 is broken" severity error;
assert bit_vector'("11100" rol -5) = "11100"
report "rol -5 is broken" severity error;
assert bit_vector'("11100") rol -4 = "11001"
report "rol -4 is broken" severity error;
assert bit_vector'("11100") rol -3 = "10011"
report "rol -3 is broken" severity error;
assert bit_vector'("11100") rol -2 = "00111"
report "rol -2 is broken" severity error;
assert bit_vector'("11100") rol -1 = "01110"
report "rol -1 is broken" severity error;
assert bit_vector'("11100") rol 0 = "11100"
report "rol 0 is broken" severity error;
assert bit_vector'("11100") rol 1 = "11001"
report "rol 1 is broken" severity error;
assert bit_vector'("11100") rol 2 = "10011"
report "rol 2 is broken" severity error;
assert bit_vector'("11100") rol 3 = "00111"
report "rol 3 is broken" severity error;
assert bit_vector'("11100") rol 4 = "01110"
report "rol 4 is broken" severity error;
assert bit_vector'("11100") rol 5 = "11100"
report "rol 5 is broken" severity error;
assert bit_vector'("11100") rol 6 = "11001"
report "rol 6 is broken" severity error;
assert bit_vector'("11100") rol 7 = "10011"
report "rol 7 is broken" severity error;
assert bit_vector'("11100") rol 8 = "00111"
report "rol 8 is broken" severity error;
end architecture;
| gpl-3.0 | 20537bc19dc407c23a5e8ea42b8b4107 | 0.554768 | 3.872838 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_source/eth_transmit.vhd | 1 | 9,212 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : eth_transmit
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Filter block for ethernet frames
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.block_bus_pkg.all;
use work.mem_bus_pkg.all;
entity eth_transmit is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"12" );
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic;
-- interface to memory (read)
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
----
eth_clock : in std_logic;
eth_reset : in std_logic;
eth_tx_data : out std_logic_vector(7 downto 0);
eth_tx_sof : out std_logic := '0';
eth_tx_eof : out std_logic;
eth_tx_valid : out std_logic;
eth_tx_ready : in std_logic );
end entity;
architecture gideon of eth_transmit is
type t_state is (idle, wait_mem, copy);
signal state : t_state;
signal trigger : std_logic;
signal trigger_sent : std_logic;
signal wr_en : std_logic;
signal wr_din : std_logic_vector(8 downto 0) := (others => '0');
signal wr_full : std_logic := '0';
signal busy : std_logic;
signal start : std_logic;
signal done : std_logic;
-- memory signals
signal sw_addr : std_logic_vector(25 downto 0);
signal sw_length : std_logic_vector(11 downto 0);
signal down_count : unsigned(11 downto 0);
signal up_count : unsigned(11 downto 0);
signal offset : unsigned(1 downto 0) := (others => '0');
signal mem_addr : unsigned(25 downto 2) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0);
signal read_req : std_logic;
-- signals in eth_clock domain
signal eth_rd_next : std_logic;
signal eth_rd_dout : std_logic_vector(8 downto 0);
signal eth_rd_valid : std_logic;
signal eth_trigger : std_logic;
signal eth_streaming: std_logic;
begin
-- 9 bit wide fifo; 8 data bits and 1 control bit: eof
i_fifo: entity work.async_fifo_ft
generic map (
--g_fast => true,
g_data_width => 9,
g_depth_bits => 10
)
port map (
wr_clock => clock,
wr_reset => reset,
wr_en => wr_en,
wr_din => wr_din,
wr_full => wr_full,
rd_clock => eth_clock,
rd_reset => eth_reset,
rd_next => eth_rd_next,
rd_dout => eth_rd_dout,
rd_valid => eth_rd_valid
);
eth_rd_next <= eth_tx_ready and eth_rd_valid and eth_streaming;
eth_tx_valid <= eth_rd_valid and eth_streaming;
eth_tx_data <= eth_rd_dout(7 downto 0);
eth_tx_eof <= eth_rd_dout(8);
i_sync : entity work.pulse_synchronizer
port map (
clock_in => clock,
pulse_in => trigger,
clock_out => eth_clock,
pulse_out => eth_trigger
);
process(eth_clock)
variable pkts : natural range 0 to 15;
begin
if rising_edge(eth_clock) then
if eth_rd_next = '1' and eth_rd_dout(8) = '1' then -- eof
pkts := pkts - 1;
if pkts = 0 then
eth_streaming <= '0';
end if;
end if;
if eth_trigger = '1' then
pkts := pkts + 1;
eth_streaming <= '1';
end if;
if eth_reset = '1' then
pkts := 0;
eth_streaming <= '0';
end if;
end if;
end process;
--- interface to ethernet clock domain is a fifo and a trigger:
-- trigger is given when end of packet is pushed into the fifo, OR when the 512th byte of a packet is pushed in the fifo.
-- From the software point of view, the interface is simple. There is a busy flag, when clear, the software writes
-- the address to read from, and the length, and the copying into the fifo begins. When the copy is completed, the busy
-- flag is reset and IRQ is raised.
process(clock)
alias local_addr : unsigned(3 downto 0) is io_req.address(3 downto 0);
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
start <= '0';
if io_req.write = '1' then
io_resp.ack <= '1';
case local_addr is
when X"0" =>
sw_addr(7 downto 0) <= io_req.data;
when X"1" =>
sw_addr(15 downto 8) <= io_req.data;
when X"2" =>
sw_addr(23 downto 16) <= io_req.data;
when X"3" =>
sw_addr(25 downto 24) <= io_req.data(1 downto 0);
when X"4" =>
sw_length(7 downto 0) <= io_req.data;
when X"5" =>
sw_length(11 downto 8) <= io_req.data(3 downto 0);
when X"8" =>
start <= '1';
busy <= '1';
when X"9" =>
io_irq <= '0';
when others =>
null;
end case;
end if;
if done = '1' then
busy <= '0';
io_irq <= '1';
end if;
if io_req.read = '1' then
io_resp.ack <= '1';
case local_addr is
when X"A" =>
io_resp.data(0) <= busy;
when others =>
null;
end case;
end if;
if reset = '1' then
busy <= '0';
io_irq <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
trigger <= '0';
done <= '0';
case state is
when idle =>
if wr_full = '0' then
wr_en <= '0';
end if;
mem_addr <= unsigned(sw_addr(25 downto 2));
down_count <= unsigned(sw_length);
up_count <= (others => '0');
offset <= unsigned(sw_addr(1 downto 0));
trigger_sent <= '0';
if start = '1' then
read_req <= '1';
state <= wait_mem;
end if;
when wait_mem =>
if wr_full = '0' then
wr_en <= '0';
end if;
if mem_resp.rack = '1' and mem_resp.rack_tag = g_mem_tag then
read_req <= '0';
mem_addr <= mem_addr + 1;
end if;
if mem_resp.dack_tag = g_mem_tag then
mem_data <= mem_resp.data;
state <= copy;
end if;
when copy =>
if wr_full = '0' then
wr_din(7 downto 0) <= mem_data(7+8*to_integer(offset) downto 8*to_integer(offset));
wr_en <= '1';
if offset = 3 then
read_req <= '1';
state <= wait_mem;
end if;
offset <= offset + 1;
if down_count = 1 then
wr_din(8) <= '1';
read_req <= '0';
done <= '1';
state <= idle;
trigger <= not trigger_sent;
else
wr_din(8) <= '0';
end if;
if up_count = 800 then -- this level has to be insanely high because of the insanely slow memory interface
trigger <= '1';
trigger_sent <= '1';
end if;
down_count <= down_count - 1;
up_count <= up_count + 1;
end if;
end case;
if reset = '1' then
read_req <= '0';
state <= idle;
end if;
end if;
end process;
mem_req.request <= read_req;
mem_req.data <= mem_data;
mem_req.address <= mem_addr & "00";
mem_req.read_writen <= '1';
mem_req.byte_en <= (others => '1');
mem_req.tag <= g_mem_tag;
end architecture;
| gpl-3.0 | 42bdfeeca20e643c241e9de2b2f58f0f | 0.423686 | 4.077911 | false | false | false | false |
ringof/radiofist_audio | ipcore_dir/dcm_6/simulation/timing/dcm_6_tb.vhd | 1 | 6,568 | -- file: dcm_6_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity dcm_6_tb is
end dcm_6_tb;
architecture test of dcm_6_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component dcm_6_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : dcm_6_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET);
-- Freq Check
end test;
| mit | 2321dcac28db66b2c07ca74610409d75 | 0.636267 | 4.22108 | false | false | false | false |
chiggs/nvc | test/simp/args.vhd | 5 | 466 | entity args is
end entity;
architecture a of args is
function func(x, y : in integer) return integer is
begin
return x + y;
end function;
procedure proc(x, y : in integer) is
begin
end procedure;
begin
process is
variable a, b, c : integer;
begin
c := func(x => a, y => b);
c := func(a, y => b);
c := func(y => b, x => a);
proc(y => b, x => a);
end process;
end architecture;
| gpl-3.0 | 990c4e6597c74502c786d605758a9d3a | 0.521459 | 3.477612 | false | false | false | false |
bgunebakan/toyrobot | Trigger_generator.vhd | 1 | 1,883 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:38:29 12/18/2014
-- Design Name:
-- Module Name: Trigger_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Trigger_generator is
Port ( clk : in STD_LOGIC;
Trigger : out STD_LOGIC);
end Trigger_generator;
architecture Behavioral of Trigger_generator is
component Counter is
generic(n: POSITIVE := 10);
Port(clk: in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
Counter_output : out STD_LOGIC_VECTOR(n-1 downto 0));
end component;
signal resetCounter : STD_LOGIC;
signal outputCounter : STD_LOGIC_VECTOR(23 downto 0);
begin
trigg: Counter generic map (24) port map(clk,'1',resetCounter,outputCounter);
process(clk)
constant ms250 : STD_LOGIC_VECTOR(23 downto 0) := "101111101011110000100000";
constant ms250And100us: STD_LOGIC_VECTOR(23 downto 0):="101111101100111110101000";
begin
if(outputCounter > ms250 and outputCounter < ms250And100us) then
trigger <= '1';
else
trigger <='0';
end if;
if(outputCounter = ms250And100us or outputCounter = "XXXXXXXXXXXXXXXXXXXXXXXX") then
resetCounter <= '0';
else
resetCounter <='1';
end if;
end process;
end Behavioral;
| gpl-2.0 | fcfca3b2e0895561a2f14582436cf646 | 0.633563 | 3.827236 | false | false | false | false |
chiggs/nvc | test/regress/ieee2.vhd | 4 | 1,075 | library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : out std_logic;
cnt : inout integer );
end entity;
architecture test of sub is
signal clk_i : bit := '0';
signal clk_std : std_logic;
begin
clk_i <= not clk_i after 1 ns;
clk_std <= to_stdulogic(clk_i);
clk <= clk_std;
process (clk_std) is
begin
if rising_edge(clk_std) then
cnt <= cnt + 1;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ieee2 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of ieee2 is
signal cnt : integer := 0;
signal clk : std_logic;
begin
sub_i: entity work.sub port map ( clk, cnt );
process (clk) is
begin
if rising_edge(clk) then
report "clock!";
end if;
end process;
process is
begin
wait for 10 ns;
report integer'image(cnt);
assert cnt = 5;
wait;
end process;
end architecture;
| gpl-3.0 | aaf177d453e3ccb1a6e96f0bc111c686 | 0.532093 | 3.758741 | false | false | false | false |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/sp_diode_arc.vhdl | 15 | 663 | -- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE SPICE_Diode_Model OF sp_Diode IS
terminal unnamed_net2 : electrical;
BEGIN
-- Architecture statement part
CS1 : ENTITY CURRENT_SOURCE(voltage_dependend)
GENERIC MAP (
N => N,
VT => VT,
ISS => ISS)
PORT MAP ( LT => unnamed_net2,
RT => kathode);
VD_CAP : ENTITY VOLTAGE_DEPENDEND_CAPACITOR
GENERIC MAP (
PB => PB,
M => M,
VT => VT,
ISS => ISS,
TT => TT,
CJ0 => CJ0)
PORT MAP ( LT => kathode,
RT => unnamed_net2);
RES : ENTITY RESISTOR
GENERIC MAP (
r => RS)
PORT MAP ( RT => anode,
LT => unnamed_net2);
END ARCHITECTURE;
| gpl-2.0 | ce8fc908229551f0287fb7db5728d2b4 | 0.61086 | 2.920705 | false | false | false | false |
chiggs/nvc | test/sem/signal.vhd | 4 | 852 | entity e is
port (
p : in bit );
end entity;
architecture a of e is
signal v : bit_vector(1 to 3);
signal x, y, z : bit;
begin
process is
begin
(x, y, z) <= v; -- OK
(x, y, z) <= x; -- Error
(x, y, z) <= "101"; -- Error
('1', y, z) <= v; -- Error
(others => x) <= v; -- Error
(p, y, z) <= v; -- Error
end process;
(x, y, z) <= v; -- OK
(x, y, z) <= x; -- Error
('1', y, z) <= v; -- Error
(others => x) <= v; -- Error
(p, y, z) <= v; -- Error
process is
variable i : integer;
begin
(v(i), v(1), v(2)) <= v; -- Error
end process;
end architecture;
| gpl-3.0 | e62f51f8e763eeea16e63e6f5a354042 | 0.325117 | 3.394422 | false | false | false | false |
trondd/mkjpeg | design/quantizer/ROMR.vhd | 2 | 5,447 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : ROMR
-- Design : EV_JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMR.VHD
-- Created : Wed Mar 19 21:09 2009
--
--------------------------------------------------------------------------------
--
-- Description : Reciprocal of 1/X where X is 1..255
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity ROMR is
generic
(
ROMADDR_W : INTEGER := 8;
ROMDATA_W : INTEGER := 16
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMR;
architecture RTL of ROMR is
constant CK : integer := 256*256;
type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER range 0 to 2**ROMDATA_W-1;
constant rom : ROMQ_TYPE :=
(
0,
65535,
32768,
21845,
16384,
13107,
10923,
9362,
8192,
7282,
6554,
5958,
5461,
5041,
4681,
4369,
4096,
3855,
3641,
3449,
3277,
3121,
2979,
2849,
2731,
2621,
2521,
2427,
2341,
2260,
2185,
2114,
2048,
1986,
1928,
1872,
1820,
1771,
1725,
1680,
1638,
1598,
1560,
1524,
1489,
1456,
1425,
1394,
1365,
1337,
1311,
1285,
1260,
1237,
1214,
1192,
1170,
1150,
1130,
1111,
1092,
1074,
1057,
1040,
1024,
1008,
993,
978,
964,
950,
936,
923,
910,
898,
886,
874,
862,
851,
840,
830,
819,
809,
799,
790,
780,
771,
762,
753,
745,
736,
728,
720,
712,
705,
697,
690,
683,
676,
669,
662,
655,
649,
643,
636,
630,
624,
618,
612,
607,
601,
596,
590,
585,
580,
575,
570,
565,
560,
555,
551,
546,
542,
537,
533,
529,
524,
520,
516,
512,
508,
504,
500,
496,
493,
489,
485,
482,
478,
475,
471,
468,
465,
462,
458,
455,
452,
449,
446,
443,
440,
437,
434,
431,
428,
426,
423,
420,
417,
415,
412,
410,
407,
405,
402,
400,
397,
395,
392,
390,
388,
386,
383,
381,
379,
377,
374,
372,
370,
368,
366,
364,
362,
360,
358,
356,
354,
352,
350,
349,
347,
345,
343,
341,
340,
338,
336,
334,
333,
331,
329,
328,
326,
324,
323,
321,
320,
318,
317,
315,
314,
312,
311,
309,
308,
306,
305,
303,
302,
301,
299,
298,
297,
295,
294,
293,
291,
290,
289,
287,
286,
285,
284,
282,
281,
280,
279,
278,
277,
275,
274,
273,
272,
271,
270,
269,
267,
266,
265,
264,
263,
262,
261,
260,
259,
258,
257
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
| lgpl-3.0 | 67e8691ac10a79faa94702e18562ac86 | 0.271342 | 4.542952 | false | false | false | false |
chiggs/nvc | test/regress/elab12.vhd | 5 | 863 | entity sub is
generic (
WIDTH : integer );
port (
x : in bit;
y : out bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
begin
y <= (WIDTH - 1 downto 0 => x);
end architecture;
-------------------------------------------------------------------------------
entity elab12 is
end entity;
architecture test of elab12 is
signal x1, x2 : bit;
signal y1 : bit_vector(3 downto 0);
signal y2 : bit_vector(4 downto 0);
begin
sub2_i: entity work.sub
generic map ( 5 )
port map ( x2, y2 );
sub1_i: entity work.sub
generic map ( 4 )
port map ( x1, y1 );
process is
begin
x1 <= '0';
x2 <= '1';
wait for 1 ns;
assert y1 = "0000";
assert y2 = "11111";
wait;
end process;
end architecture;
| gpl-3.0 | 5482d6e28e104df292c7f442787d9d20 | 0.479722 | 3.719828 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/virtual_jtag.vhd | 2 | 4,026 | -- virtual_jtag.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity virtual_jtag is
port (
tdi : out std_logic; -- jtag.tdi
tdo : in std_logic := '0'; -- .tdo
ir_in : out std_logic_vector(3 downto 0); -- .ir_in
ir_out : in std_logic_vector(3 downto 0) := (others => '0'); -- .ir_out
virtual_state_cdr : out std_logic; -- .virtual_state_cdr
virtual_state_sdr : out std_logic; -- .virtual_state_sdr
virtual_state_e1dr : out std_logic; -- .virtual_state_e1dr
virtual_state_pdr : out std_logic; -- .virtual_state_pdr
virtual_state_e2dr : out std_logic; -- .virtual_state_e2dr
virtual_state_udr : out std_logic; -- .virtual_state_udr
virtual_state_cir : out std_logic; -- .virtual_state_cir
virtual_state_uir : out std_logic; -- .virtual_state_uir
tck : out std_logic -- tck.clk
);
end entity virtual_jtag;
architecture rtl of virtual_jtag is
component sld_virtual_jtag is
generic (
sld_auto_instance_index : string := "YES";
sld_instance_index : integer := 0;
sld_ir_width : integer := 1
);
port (
tdi : out std_logic; -- tdi
tdo : in std_logic := 'X'; -- tdo
ir_in : out std_logic_vector(3 downto 0); -- ir_in
ir_out : in std_logic_vector(3 downto 0) := (others => 'X'); -- ir_out
virtual_state_cdr : out std_logic; -- virtual_state_cdr
virtual_state_sdr : out std_logic; -- virtual_state_sdr
virtual_state_e1dr : out std_logic; -- virtual_state_e1dr
virtual_state_pdr : out std_logic; -- virtual_state_pdr
virtual_state_e2dr : out std_logic; -- virtual_state_e2dr
virtual_state_udr : out std_logic; -- virtual_state_udr
virtual_state_cir : out std_logic; -- virtual_state_cir
virtual_state_uir : out std_logic; -- virtual_state_uir
tck : out std_logic -- clk
);
end component sld_virtual_jtag;
begin
virtual_jtag_0 : component sld_virtual_jtag
generic map (
sld_auto_instance_index => "YES",
sld_instance_index => 0,
sld_ir_width => 4
)
port map (
tdi => tdi, -- jtag.tdi
tdo => tdo, -- .tdo
ir_in => ir_in, -- .ir_in
ir_out => ir_out, -- .ir_out
virtual_state_cdr => virtual_state_cdr, -- .virtual_state_cdr
virtual_state_sdr => virtual_state_sdr, -- .virtual_state_sdr
virtual_state_e1dr => virtual_state_e1dr, -- .virtual_state_e1dr
virtual_state_pdr => virtual_state_pdr, -- .virtual_state_pdr
virtual_state_e2dr => virtual_state_e2dr, -- .virtual_state_e2dr
virtual_state_udr => virtual_state_udr, -- .virtual_state_udr
virtual_state_cir => virtual_state_cir, -- .virtual_state_cir
virtual_state_uir => virtual_state_uir, -- .virtual_state_uir
tck => tck -- tck.clk
);
end architecture rtl; -- of virtual_jtag
| gpl-3.0 | 28477f84db34a0da69b64fdc9b65c1d7 | 0.444858 | 3.776735 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/core_address_decoder.vhd | 2 | 3,076 | ----------------------------------------------------------------------------------------------
--
-- Input file : core_address_decoder.vhd
-- Design name : core_address_decoder
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Wishbone adapter for the MB-Lite microprocessor
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity core_address_decoder is generic
(
G_NUM_SLAVES : positive := CFG_NUM_SLAVES;
G_MEMORY_MAP : memory_map_type := CFG_MEMORY_MAP
);
port
(
m_dmem_i : out dmem_in_type;
s_dmem_o : out dmem_out_array_type(G_NUM_SLAVES - 1 downto 0);
m_dmem_o : in dmem_out_type;
s_dmem_i : in dmem_in_array_type(G_NUM_SLAVES - 1 downto 0);
clk_i : std_logic
);
end core_address_decoder;
architecture arch of core_address_decoder is
-- Decodes the address based on the memory map. Returns "1" if 0 or 1 slave is attached.
function decode(adr : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(G_NUM_SLAVES - 1 downto 0);
begin
if G_NUM_SLAVES > 1 and notx(adr) then
for i in G_NUM_SLAVES - 1 downto 0 loop
if (adr >= G_MEMORY_MAP(i) and adr < G_MEMORY_MAP(i+1)) then
result(i) := '1';
else
result(i) := '0';
end if;
end loop;
else
result := (others => '1');
end if;
return result;
end function;
function demux(dmem_i : dmem_in_array_type; ce, r_ce : std_logic_vector) return dmem_in_type is
variable dmem : dmem_in_type;
begin
dmem := dmem_i(0);
if notx(ce) then
for i in G_NUM_SLAVES - 1 downto 0 loop
if ce(i) = '1' then
dmem.ena_i := dmem_i(i).ena_i;
end if;
if r_ce(i) = '1' then
dmem.dat_i := dmem_i(i).dat_i;
end if;
end loop;
end if;
return dmem;
end function;
signal r_ce, ce : std_logic_vector(G_NUM_SLAVES - 1 downto 0) := (others => '1');
begin
ce <= decode(m_dmem_o.adr_o);
m_dmem_i <= demux(s_dmem_i, ce, r_ce);
CON: for i in G_NUM_SLAVES-1 downto 0 generate
begin
s_dmem_o(i).dat_o <= m_dmem_o.dat_o;
s_dmem_o(i).adr_o <= m_dmem_o.adr_o;
s_dmem_o(i).sel_o <= m_dmem_o.sel_o;
s_dmem_o(i).we_o <= m_dmem_o.we_o and ce(i);
s_dmem_o(i).ena_o <= m_dmem_o.ena_o and ce(i);
end generate;
process(clk_i)
begin
if rising_edge(clk_i) then
r_ce <= ce;
end if;
end process;
end arch;
| gpl-3.0 | 35c064339488b26ddfe5dc92981598dc | 0.503576 | 3.429208 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/c1541_drive.vhd | 1 | 12,266 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity c1541_drive is
generic (
g_big_endian : boolean;
g_audio_tag : std_logic_vector(7 downto 0) := X"01";
g_floppy_tag : std_logic_vector(7 downto 0) := X"02";
g_cpu_tag : std_logic_vector(7 downto 0) := X"04";
g_audio : boolean := true;
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
drive_stop : in std_logic := '0';
-- timing
tick_16MHz : in std_logic;
tick_4MHz : in std_logic;
tick_1kHz : in std_logic;
-- slave port on io bus
io_req : in t_io_req;
io_resp : out t_io_resp;
-- master port on memory bus
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
iec_reset_n : in std_logic := '1';
c64_reset_n : in std_logic := '1';
-- Debug port
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
-- Parallel cable pins
track_is_0 : out std_logic; -- conflicts on PA0 when parallel cable is used
via1_port_a_o : out std_logic_vector(7 downto 0);
via1_port_a_i : in std_logic_vector(7 downto 0);
via1_port_a_t : out std_logic_vector(7 downto 0);
via1_ca2_o : out std_logic;
via1_ca2_i : in std_logic;
via1_ca2_t : out std_logic;
via1_cb1_o : out std_logic;
via1_cb1_i : in std_logic;
via1_cb1_t : out std_logic;
-- LED
act_led_n : out std_logic;
motor_led_n : out std_logic;
dirty_led_n : out std_logic;
-- audio out
audio_sample : out signed(12 downto 0) );
end c1541_drive;
architecture structural of c1541_drive is
signal tick_16M_i : std_logic;
signal cia_rising : std_logic;
signal cpu_clock_en : std_logic;
signal iec_reset_o : std_logic;
signal do_track_out : std_logic;
signal do_track_in : std_logic;
signal do_head_bang : std_logic;
signal en_hum : std_logic;
signal en_slip : std_logic;
signal use_c64_reset : std_logic;
signal floppy_inserted : std_logic := '0';
signal bank_is_ram : std_logic_vector(7 downto 1);
signal power : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal track : unsigned(6 downto 0);
signal drive_address : std_logic_vector(1 downto 0) := "00";
signal write_prot_n : std_logic := '1';
signal drv_reset : std_logic := '1';
signal disk_rdata : std_logic_vector(7 downto 0);
signal disk_wdata : std_logic_vector(7 downto 0);
signal drive_stop_i : std_logic;
signal stop_on_freeze : std_logic;
signal mem_req_cpu : t_mem_req;
signal mem_resp_cpu : t_mem_resp;
signal mem_req_flop : t_mem_req;
signal mem_resp_flop : t_mem_resp;
signal mem_req_snd : t_mem_req := c_mem_req_init;
signal mem_resp_snd : t_mem_resp;
signal mem_req_8 : t_mem_req := c_mem_req_init;
signal mem_resp_8 : t_mem_resp;
signal mem_busy : std_logic;
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_param : t_io_req;
signal io_resp_param : t_io_resp;
signal io_req_dirty : t_io_req;
signal io_resp_dirty : t_io_resp;
signal count : unsigned(7 downto 0) := X"00";
signal led_intensity : unsigned(1 downto 0);
begin
i_splitter: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 3
)
port map(
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_dirty,
reqs(2) => io_req_param,
resps(0) => io_resp_regs,
resps(1) => io_resp_dirty,
resps(2) => io_resp_param
);
i_timing: entity work.c1541_timing
port map (
clock => clock,
reset => reset,
tick_4MHz => tick_4MHz,
mem_busy => mem_busy,
use_c64_reset=> use_c64_reset,
c64_reset_n => c64_reset_n,
iec_reset_n => iec_reset_n,
iec_reset_o => iec_reset_o,
power => power,
drive_stop => drive_stop_i,
cia_rising => cia_rising,
cpu_clock_en => cpu_clock_en ); -- 1 MHz
drive_stop_i <= drive_stop and stop_on_freeze;
tick_16M_i <= tick_16MHz and not drive_stop_i;
i_cpu: entity work.cpu_part_1541
generic map (
g_tag => g_cpu_tag,
g_ram_base => g_ram_base )
port map (
clock => clock,
falling => cpu_clock_en,
rising => cia_rising,
reset => drv_reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- trace data
debug_data => debug_data,
debug_valid => debug_valid,
-- configuration
bank_is_ram => bank_is_ram,
-- memory interface
mem_req => mem_req_cpu,
mem_resp => mem_resp_cpu,
mem_busy => mem_busy,
-- drive pins
power => power,
drive_address => drive_address,
write_prot_n => write_prot_n,
motor_on => motor_on,
mode => mode,
step => step,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
drv_rdata => disk_rdata,
drv_wdata => disk_wdata,
-- Parallel cable pins
via1_port_a_o => via1_port_a_o,
via1_port_a_i => via1_port_a_i,
via1_port_a_t => via1_port_a_t,
via1_ca2_o => via1_ca2_o,
via1_ca2_i => via1_ca2_i,
via1_ca2_t => via1_ca2_t,
via1_cb1_o => via1_cb1_o,
via1_cb1_i => via1_cb1_i,
via1_cb1_t => via1_cb1_t,
-- other
act_led => act_led_n );
i_flop: entity work.floppy
generic map (
g_big_endian => g_big_endian,
g_tag => g_floppy_tag )
port map (
clock => clock,
reset => drv_reset,
tick_16MHz => tick_16M_i,
-- signals from MOS 6522 VIA
stepper_en => motor_on,
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
read_data => disk_rdata,
write_data => disk_wdata,
track => track,
track_is_0 => track_is_0,
---
io_req_param => io_req_param,
io_resp_param => io_resp_param,
io_req_dirty => io_req_dirty,
io_resp_dirty => io_resp_dirty,
---
floppy_inserted => floppy_inserted,
do_track_out => do_track_out,
do_track_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
dirty_led_n => dirty_led_n,
---
mem_req => mem_req_flop,
mem_resp => mem_resp_flop );
r_snd: if g_audio generate
i_snd: entity work.floppy_sound
generic map (
g_tag => g_audio_tag,
sound_base => g_audio_base(27 downto 16),
motor_hum_addr => X"0000",
flop_slip_addr => X"1200",
track_in_addr => X"2400",
track_out_addr => X"2C00",
head_bang_addr => X"3480",
motor_len => 4410,
track_in_len => X"0800", -- ~100 ms;
track_out_len => X"0880", -- ~100 ms;
head_bang_len => X"0880" ) -- ~100 ms;
port map (
clock => clock,
reset => drv_reset,
tick_4MHz => tick_4MHz,
do_trk_out => do_track_out,
do_trk_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
-- memory interface
mem_req => mem_req_snd,
mem_resp => mem_resp_snd,
-- audio
sample_out => audio_sample );
end generate;
i_regs: entity work.drive_registers
port map (
clock => clock,
reset => reset,
tick_1kHz => tick_1kHz,
io_req => io_req_regs,
io_resp => io_resp_regs,
iec_reset_o => iec_reset_o,
use_c64_reset => use_c64_reset,
power => power,
drv_reset => drv_reset,
drive_address => drive_address,
floppy_inserted => floppy_inserted,
write_prot_n => write_prot_n,
bank_is_ram => bank_is_ram,
stop_on_freeze => stop_on_freeze,
track => track,
mode => mode,
motor_on => motor_on );
-- memory arbitration
i_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 3,
g_registered => false )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_flop,
reqs(1) => mem_req_cpu,
reqs(2) => mem_req_snd,
resps(0) => mem_resp_flop,
resps(1) => mem_resp_cpu,
resps(2) => mem_resp_snd,
req => mem_req_8,
resp => mem_resp_8 );
i_conv32: entity work.mem_to_mem32(route_through)
generic map (
g_big_endian => g_big_endian )
port map(
clock => clock,
reset => reset,
mem_req_8 => mem_req_8,
mem_resp_8 => mem_resp_8,
mem_req_32 => mem_req,
mem_resp_32 => mem_resp );
process(clock)
variable led_int : unsigned(7 downto 0);
begin
if rising_edge(clock) then
count <= count + 1;
if count=X"00" then
motor_led_n <= '0'; -- on
end if;
led_int := led_intensity & led_intensity & led_intensity & led_intensity;
if count=led_int then
motor_led_n <= '1'; -- off
end if;
end if;
end process;
led_intensity <= "00" when power='0' else
"01" when floppy_inserted='0' else
"10" when motor_on='0' else
"11";
end architecture;
| gpl-3.0 | bc94bc678858080c83aefcbec0fd7743 | 0.453367 | 3.404385 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/nano_minimal_io.vhd | 1 | 8,821 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.usb_pkg.all;
entity nano_minimal_io is
generic (
g_support_suspend : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
stall : out std_logic;
-- Register access
reg_read : out std_logic := '0';
reg_write : out std_logic := '0';
reg_ack : in std_logic;
reg_address : out std_logic_vector(5 downto 0) := (others => '0');
reg_wdata : out std_logic_vector(7 downto 0) := X"00";
reg_rdata : in std_logic_vector(7 downto 0);
status : in std_logic_vector(7 downto 0);
-- Low level
do_chirp : out std_logic;
chirp_data : out std_logic;
-- Functional Level
cmd_response : in std_logic_vector(15 downto 0) := X"0BAD";
frame_count : in unsigned(15 downto 0) := (others => '0');
mem_ctrl_ready : in std_logic := '0';
connected : out std_logic; -- '1' when a USB device is connected
operational : out std_logic; -- '1' when a USB device is successfully reset
suspended : out std_logic; -- '1' when the USB bus is in the suspended state
sof_enable : out std_logic; -- '1' when SOFs shall be generated
sof_tick : in std_logic := '0';
interrupt_out : out std_logic := '0';
speed : out std_logic_vector(1 downto 0) ); -- speed indicator of current link
end entity;
architecture gideon of nano_minimal_io is
signal stall_i : std_logic := '0';
signal ulpi_access : std_logic;
signal filter_cnt : unsigned(7 downto 0);
signal filter_st1 : std_logic;
signal filter_cnt2 : unsigned(8 downto 0);
signal bus_low : std_logic := '0';
signal speed_i : std_logic_vector(1 downto 0);
signal reset_filter_st1 : std_logic;
signal disconn : std_logic;
signal disconn_latched : std_logic;
signal sof_tick_latch : std_logic;
begin
disconn <= '1' when (status(5 downto 4) = "10") or (bus_low = '1' and speed_i(1)='0') else '0';
speed <= speed_i;
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
-- filter for chirp detection
if reset_filter_st1 = '1' then
filter_cnt <= (others => '0');
filter_st1 <= '0';
elsif status(1) = '0' then
filter_cnt <= (others => '0');
else -- status(1) = '1'
filter_cnt <= filter_cnt + 1;
if filter_cnt = 255 then
filter_st1 <= '1';
end if;
end if;
-- filter for disconnect detection
if status(1 downto 0) = "00" then
filter_cnt2 <= filter_cnt2 + 1;
if filter_cnt2 = 511 then
bus_low <= '1';
end if;
else
filter_cnt2 <= (others => '0');
bus_low <= '0';
end if;
-- register access defaults
if reg_ack='1' then
reg_write <= '0';
reg_read <= '0';
stall_i <= '0';
end if;
interrupt_out <= '0';
reset_filter_st1 <= '0';
if io_write='1' then
reg_address <= std_logic_vector(io_addr(5 downto 0));
case adhi is
-- set registers
when X"2" =>
case adlo is
when X"0" =>
do_chirp <= '1';
when X"1" =>
chirp_data <= '1';
when X"2" =>
connected <= '1';
when X"3" =>
operational <= '1';
when X"4" =>
suspended <= '1';
when X"6" =>
speed_i <= io_wdata(1 downto 0);
when X"7" =>
sof_enable <= '1';
when X"8" =>
interrupt_out <= '1';
when X"9" =>
reset_filter_st1 <= '1';
when others =>
null;
end case;
-- clear registers
when X"3" =>
case adlo is
when X"0" =>
do_chirp <= '0';
when X"1" =>
chirp_data <= '0';
when X"2" =>
connected <= '0';
when X"3" =>
operational <= '0';
when X"4" =>
suspended <= '0';
when X"7" =>
sof_enable <= '0';
when X"E" =>
disconn_latched <= '0';
when X"C" =>
sof_tick_latch <= '0';
when others =>
null;
end case;
when X"C"|X"D"|X"E"|X"F" =>
reg_wdata <= io_wdata(7 downto 0);
reg_write <= '1';
stall_i <= '1';
when others =>
null;
end case;
end if;
if sof_tick = '1' then
sof_tick_latch <= '1';
end if;
if io_read = '1' then
reg_address <= std_logic_vector(io_addr(5 downto 0));
if io_addr(7 downto 6) = "10" then
reg_read <= '1';
stall_i <= '1';
end if;
end if;
if disconn='1' then
disconn_latched <= '1';
end if;
if reset='1' then
do_chirp <= '0';
chirp_data <= '0';
connected <= '0';
operational <= '0';
suspended <= '0';
sof_enable <= '0';
disconn_latched <= '0';
filter_st1 <= '0';
reg_read <= '0';
reg_write <= '0';
stall_i <= '0';
speed_i <= "01";
end if;
end if;
end process;
ulpi_access <= io_addr(7);
stall <= stall_i and not reg_ack; -- stall right away, and continue right away also when the data is returned
-- process( reg_rdata, io_addr, status, disconn_latched, filter_st1, mem_ctrl_ready, frame_count, sof_tick_latch)
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
io_rdata <= (others => '0');
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
case adhi is
when X"3" =>
case adlo is
when X"9" =>
io_rdata(15) <= filter_st1;
when X"B" =>
io_rdata <= std_logic_vector(frame_count);
when X"C" =>
io_rdata(15) <= sof_tick_latch;
when X"D" =>
io_rdata(15) <= mem_ctrl_ready;
when X"E" =>
io_rdata(15) <= disconn_latched;
when X"F" =>
io_rdata(7 downto 0) <= status;
when others =>
null;
end case;
when X"6" =>
case adlo is
when X"4" =>
io_rdata <= cmd_response;
when others =>
null;
end case;
when X"8"|X"9"|X"A"|X"B" =>
io_rdata <= X"00" & reg_rdata;
when others =>
null;
end case;
end if;
end process;
end architecture;
| gpl-3.0 | 7afed83c7c3b2eb3225babfaca730c52 | 0.390772 | 4.230695 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/testbench/ddr2_ctrl_tb.vhd | 1 | 8,004 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 32 bit (single beat), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
entity ddr2_ctrl_tb is
end entity;
architecture tb of ddr2_ctrl_tb is
signal ref_clock : std_logic := '1';
signal ref_reset : std_logic := '0';
signal clock : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_req_32;
signal resp : t_mem_resp_32;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal correct : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CLKn : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_ODT : std_logic := '0';
signal SDRAM_DM : std_logic := '0';
signal SDRAM_DQS : std_logic := '0';
signal SDRAM_A : std_logic_vector(13 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CLKn : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_ODT : std_logic := '0';
signal logic_A : std_logic_vector(13 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
constant g_in_delay : time := 0.3 ns;
begin
ref_clock <= not ref_clock after 10 ns; -- 50 MHz reference clock
ref_reset <= '1', '0' after 100 ns;
i_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_mut: entity work.ddr2_ctrl
port map (
ref_clock => ref_clock,
ref_reset => ref_reset,
sys_clock_o => clock,
sys_reset_o => reset,
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CLKn => logic_CLKn,
SDRAM_CKE => logic_CKE,
SDRAM_ODT => logic_ODT,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_A => logic_A,
SDRAM_BA => logic_BA,
SDRAM_DM => SDRAM_DM,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS
);
SDRAM_A <= transport logic_A after 11.5 ns;
SDRAM_CLK <= transport logic_CLK after 11.5 ns;
SDRAM_CLKn <= transport logic_CLKn after 11.5 ns;
SDRAM_CKE <= transport logic_CKE after 11.5 ns;
SDRAM_CSn <= transport logic_CSn after 11.5 ns;
SDRAM_RASn <= transport logic_RASn after 11.5 ns;
SDRAM_CASn <= transport logic_CASn after 11.5 ns;
SDRAM_WEn <= transport logic_WEn after 11.5 ns;
SDRAM_ODT <= transport logic_ODT after 11.5 ns;
p_test: process
begin
req <= c_mem_req_32_init;
wait until reset='0';
wait for 2 us;
wait until clock='1';
req.read_writen <= '1'; -- read
req.read_writen <= '0'; -- write
req.request <= '1';
req.data <= X"44332211";
req.byte_en <= "0111";
req.tag <= X"34";
while true loop
wait until clock='1';
if resp.rack='1' then
if req.read_writen = '0' then
req.address <= req.address + 4;
end if;
req.read_writen <= not req.read_writen;
end if;
end loop;
wait;
end process;
process(SDRAM_CLK)
variable delay : integer := -10;
begin
if rising_edge(SDRAM_CLK) then
if SDRAM_CSn = '0' and
SDRAM_RASn = '1' and
SDRAM_CASn = '0' and
SDRAM_WEn = '1' then -- read!
delay := 7;
end if;
end if;
delay := delay - 1;
case delay is
when 0 =>
SDRAM_DQ <= transport X"22" after g_in_delay;
when -1 =>
SDRAM_DQ <= transport X"33" after g_in_delay;
when -2 =>
SDRAM_DQ <= transport X"44" after g_in_delay;
when -3 =>
SDRAM_DQ <= transport X"55" after g_in_delay;
when others =>
SDRAM_DQ <= transport "ZZZZZZZZ" after g_in_delay;
end case;
end process;
p_io: process
variable io : p_io_bus_bfm_object;
variable data : std_logic_vector(7 downto 0);
constant c_mr : std_logic_vector(13 downto 0) :=
'0' & -- reserved
'0' & -- normal PD
"001" & -- Write recovery = 2;
'0' & -- DLL reset = 0
'0' & -- normal mode (non-test)
"011" & -- CAS latency = 3
'0' & -- sequential burst mode
"010"; -- burst len = 4
constant c_cmd_inactive : std_logic_vector(3 downto 0) := "1111";
constant c_cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant c_cmd_active : std_logic_vector(3 downto 0) := "0011";
constant c_cmd_read : std_logic_vector(3 downto 0) := "0101";
constant c_cmd_write : std_logic_vector(3 downto 0) := "0100";
constant c_cmd_bterm : std_logic_vector(3 downto 0) := "0110";
constant c_cmd_precharge : std_logic_vector(3 downto 0) := "0010";
constant c_cmd_refresh : std_logic_vector(3 downto 0) := "0001";
constant c_cmd_mode_reg : std_logic_vector(3 downto 0) := "0000";
begin
wait until reset='0';
bind_io_bus_bfm("io_bfm", io);
wait for 1 us;
io_write(io, X"0C", X"01"); -- enable clock
io_write(io, X"00", X"00");
io_write(io, X"01", X"04");
io_write(io, X"02", X"0" & c_cmd_precharge);
io_write(io, X"00", c_mr(7 downto 0));
io_write(io, X"01", "00" & c_mr(13 downto 8));
io_write(io, X"02", X"0" & c_cmd_mode_reg);
for i in 1 to 80 loop
io_write(io, X"09", X"35"); -- make a step on the read clock
wait for 16*7 ns;
end loop;
wait;
end process;
p_check: process(clock)
begin
if rising_edge(clock) then
if resp.dack_tag = X"34" then
if resp.data = X"55443322" then
correct <= '1';
else
correct <= '0';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 | d51f864fb3e80cc13d727f0ffc178158 | 0.47039 | 3.67156 | false | false | false | false |
armandas/Plong | controller.vhd | 3 | 2,853 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity controller is
port(
clk, not_reset: in std_logic;
data_in: in std_logic;
clk_out: out std_logic;
ps_control: out std_logic;
gamepad: out std_logic_vector(7 downto 0)
);
end controller;
architecture arch of controller is
constant DELAY: integer := 15625; -- 3.2kHz
signal counter, counter_next: std_logic_vector(13 downto 0);
-- counts from 0 to 4 @ 3.2kHz,
-- clk_out uses MSB to output 800Hz signal
-- sampling should be done when quad_counter = 3
signal quad_counter, quad_counter_next: std_logic_vector(1 downto 0);
signal ps_counter, ps_counter_next: std_logic_vector(3 downto 0);
signal register_1, register_1_next: std_logic_vector(7 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
counter <= (others => '0');
quad_counter <= (others => '0');
ps_counter <= (others => '0');
register_1 <= (others => '1');
elsif falling_edge(clk) then
counter <= counter_next;
quad_counter <= quad_counter_next;
ps_counter <= ps_counter_next;
register_1 <= register_1_next;
end if;
end process;
counter_next <= (counter + 1) when counter < DELAY else
(others => '0');
quad_counter_next <= (quad_counter + 1) when counter = 0 else
quad_counter;
ps_counter_next <= (others => '0') when (ps_counter = 8 and
quad_counter = 1) else
(ps_counter + 1) when (quad_counter = 1 and
counter = 0) else ps_counter;
register_1_next(0) <= data_in when (ps_counter = 0 and quad_counter = 1) else register_1(0);
register_1_next(1) <= data_in when (ps_counter = 1 and quad_counter = 1) else register_1(1);
register_1_next(2) <= data_in when (ps_counter = 2 and quad_counter = 1) else register_1(2);
register_1_next(3) <= data_in when (ps_counter = 3 and quad_counter = 1) else register_1(3);
register_1_next(4) <= data_in when (ps_counter = 4 and quad_counter = 1) else register_1(4);
register_1_next(5) <= data_in when (ps_counter = 5 and quad_counter = 1) else register_1(5);
register_1_next(6) <= data_in when (ps_counter = 6 and quad_counter = 1) else register_1(6);
register_1_next(7) <= data_in when (ps_counter = 7 and quad_counter = 1) else register_1(7);
-- outputs pulses of one clock cycle length at a rate of 100Hz
gamepad <= (not register_1) when (ps_counter = 8 and counter = 0) else (others => '0');
clk_out <= (not quad_counter(1));
ps_control <= (not quad_counter(1)) when ps_counter = 8 else '1';
end arch; | bsd-2-clause | 0da35c201b1b88c384d18b248724e983 | 0.582545 | 3.492044 | false | false | false | false |
fpgaddicted/5bit-shift-register-structural- | prescaler_FSM.vhd | 1 | 2,190 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:48:55 04/10/2017
-- Design Name:
-- Module Name: dynamic_clk - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity prescaler_FSM is
Port ( clk : in STD_LOGIC;
toggle : in STD_LOGIC;
reset : in STD_LOGIC;
clk_state : out STD_LOGIC_VECTOR (1 downto 0));
end prescaler_FSM;
architecture behavioral of prescaler_FSM is
type control is (clk1,clk2,clk3,clk4);
signal next_state :control;
begin
FSM:process (clk, reset ,next_state, toggle)
begin
if reset ='1' then
next_state <= clk1;
elsif (clk' event and clk ='1') then
case next_state is
when clk1 =>
if toggle = '1' then
next_state <= clk2;
else
next_state <= clk1;
clk_state <= "00";
end if;
--------------------------------------
when clk2 =>
if toggle = '1' then
next_state <= clk3;
else
next_state <= clk2;
clk_state <= "01";
end if;
--------------------------------------
when clk3 =>
if toggle = '1' then
next_state <= clk4;
else
next_state <= clk3;
clk_state <= "10";
end if;
------------------------------------
when clk4 =>
if toggle = '1' then
next_state <= clk1;
else
next_state <= clk4;
clk_state <= "11";
end if;
end case;
end if;
end process FSM;
end behavioral;
| gpl-3.0 | fd14b022a437143d0efdb227a2f75e49 | 0.485388 | 3.762887 | false | false | false | false |
ringof/radiofist_audio | sinc3_filter.vhd | 1 | 1,894 | -- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See LICENCE.txt for details
--
-- Implementation is derived from p. 17 of Texas Instruments SBAA094
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity sinc3_filter is
port (
reset : in STD_LOGIC;
din : in STD_LOGIC;
in_clk : in STD_LOGIC;
out_clk : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (24 downto 0)
);
end sinc3_filter;
architecture RTL of sinc3_filter is
signal DN0, DN1, DN3, DN5 : STD_LOGIC_VECTOR(24 downto 0);
signal CN1, CN2, CN3, CN4 : STD_LOGIC_VECTOR(24 downto 0);
signal DELTA1 : STD_LOGIC_VECTOR(24 downto 0);
begin
-- process to clock in the sigma-delta bit stream into the first
-- integrator of filter
-- Clocked at orignal sample frequency
sd_stream_in : process(din, in_clk, reset)
begin
if reset = '1' then
DELTA1 <= (others => '0');
elsif rising_edge(in_clk) then
if din = '1' then
DELTA1 <= DELTA1 + 1;
end if;
end if;
end process;
-- process to move data and apply integration through
-- the successive two integrators of filter
-- Clocked at original sample frequency
sd_integration : process(in_clk, reset)
begin
if reset = '1' then
CN1 <= (others => '0');
CN2 <= (others => '0');
elsif rising_edge(in_clk) then
CN1 <= CN1 + DELTA1;
CN2 <= CN2 + CN1;
end if;
end process;
-- process to decimate and move data through the three differentiators
-- Clock at downsampling frequency
sd_differentiation : process(reset, out_clk)
begin
if reset = '1' then
DN0 <= (others => '0');
DN1 <= (others => '0');
DN3 <= (others => '0');
DN5 <= (others => '0');
elsif rising_edge(out_clk) then
DN0 <= CN2;
DN1 <= DN0;
DN3 <= CN3;
DN5 <= CN4;
end if;
end process;
-- Differentiation functions for filter
CN3 <= DN0 - DN1;
CN4 <= CN3 - DN3;
dout <= CN4 - DN5;
end RTL;
| mit | 50e6727318b48a7b6111d283a3691f03 | 0.653643 | 2.826866 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/standard/cb20/synthesis/cb20_gpio_block_0_avalon_slave_0_translator.vhd | 1 | 14,661 | -- cb20_gpio_block_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 4;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(3 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_gpio_block_0_avalon_slave_0_translator;
architecture rtl of cb20_gpio_block_0_avalon_slave_0_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(3 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
gpio_block_0_avalon_slave_0_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_gpio_block_0_avalon_slave_0_translator
| apache-2.0 | 44a20c11ad27de8e317b845b57820919 | 0.429711 | 4.335009 | false | false | false | false |
chiggs/nvc | test/perf/arraycase.vhd | 5 | 1,448 | entity arraycase is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of arraycase is
constant LOOPS : integer := 100;
begin
process is
variable vec : unsigned(15 downto 0) := (others => '0');
variable a, b, c, d, e, f : natural;
begin
for l in 1 to LOOPS loop
for i in 0 to integer'((2 ** 16) - 1) loop
vec := vec + X"0001";
case vec is
when X"0005" | X"ac3d" | X"9141" | X"2562" | X"0001" =>
a := a + 1;
when X"5101" | X"bbbb" | X"cccc" | X"dddd" =>
b := b + 1;
when X"0000" | X"ffff" =>
c := c + 1;
when X"2510" | X"1510" | X"babc" | X"aaad" | X"1591" =>
d := d + 1;
when X"9151" | X"abfd" | X"ab41" =>
e := e + 1;
when X"1111" | X"9150" =>
f := f + 1;
when others =>
null;
end case;
wait for 1 ns;
end loop;
end loop;
report integer'image(a) & " " & integer'image(b) & " "
& integer'image(c) & " " & integer'image(d) & " "
& integer'image(e) & " " & integer'image(f);
wait;
end process;
end architecture;
| gpl-3.0 | 7d5279c1d5b52b8248386fd52f4e580e | 0.395718 | 3.656566 | false | false | false | false |
fpgaddicted/5bit-shift-register-structural- | variable_clock.vhd | 1 | 2,237 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:28:39 04/11/2017
-- Design Name:
-- Module Name: variable_clock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clk_controller is
Port ( clk : in STD_LOGIC;
toggle : in STD_LOGIC;
reset : in STD_LOGIC;
clk_o : out STD_LOGIC);
end clk_controller;
architecture PORTMAP of clk_controller is
COMPONENT prescaler_FSM IS
PORT(
clk : in STD_LOGIC;
toggle : in STD_LOGIC;
reset : in STD_LOGIC;
clk_state : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT quad_prescaler IS
PORT(
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC;
control : in STD_LOGIC_VECTOR(1 downto 0);
reset : in STD_LOGIC);
END COMPONENT;
COMPONENT debounce IS
PORT (
clk : in STD_LOGIC;
button : in STD_LOGIC;
result : out STD_LOGIC);
END COMPONENT;
signal operation : std_logic_vector(1 downto 0);
signal i_c : std_logic;
signal tp: std_logic;
begin
debounceP : debounce PORT MAP(
clk => clk,
button => toggle,
result => tp
);
FSM : prescaler_FSM PORT MAP(
toggle => tp,
reset => reset,
clk => clk,
clk_state => operation
);
clk_div : quad_prescaler PORT MAP(
clk_in => clk,
clk_out => i_c,
reset => reset,
control => operation
);
clk_o <= i_c;
end PORTMAP;
| gpl-3.0 | f311763253542ca230bedee954d3b51d | 0.52481 | 3.87695 | false | false | false | false |
chiggs/nvc | lib/std/env.vhd | 4 | 1,318 | --
-- Environment package for VHDL-2008
--
-- This is also compiled into the NVC library for use with earlier standards
--
package env is
procedure stop(status : integer);
procedure stop;
procedure finish(status : integer);
procedure finish;
function resolution_limit return delay_length;
end package;
package body env is
procedure stop_impl(finish, have_status : boolean; status : integer) is
procedure nvc_env_stop(finish, have_status : boolean; status : integer);
attribute foreign of nvc_env_stop : procedure is "_nvc_env_stop";
begin
nvc_env_stop(finish, have_status, status);
end procedure;
procedure stop(status : integer) is
begin
stop_impl(finish => false, have_status => true, status => status);
end procedure;
procedure stop is
begin
stop_impl(finish => false, have_status => false, status => 0);
end procedure;
procedure finish(status : integer) is
begin
stop_impl(finish => true, have_status => true, status => status);
end procedure;
procedure finish is
begin
stop_impl(finish => true, have_status => false, status => 0);
end procedure;
function resolution_limit return delay_length is
begin
return fs;
end function;
end package body;
| gpl-3.0 | 5e155f1e8ba02dd1db01619dec208026 | 0.657056 | 4.237942 | false | false | false | false |
trondd/mkjpeg | design/huffman/Huffman.vhd | 2 | 18,848 | -------------------------------------------------------------------------------
-- File Name : Huffman.vhd
--
-- Project : JPEG_ENC
--
-- Module : Huffman
--
-- Content : Huffman Encoder
--
-- Description : Huffman encoder core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity Huffman is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
huf_sm_settings : in T_SM_SETTINGS;
-- HOST IF
sof : in std_logic;
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
-- RLE
rle_buf_sel : out std_logic;
rd_en : out std_logic;
runlength : in std_logic_vector(3 downto 0);
VLI_size : in std_logic_vector(3 downto 0);
VLI : in std_logic_vector(11 downto 0);
d_val : in std_logic;
rle_fifo_empty : in std_logic;
-- Byte Stuffer
bs_buf_sel : in std_logic;
bs_fifo_empty : out std_logic;
bs_rd_req : in std_logic;
bs_packed_byte : out std_logic_vector(7 downto 0)
);
end entity Huffman;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of Huffman is
type T_STATE is (IDLE, RUN_VLC, RUN_VLI, PAD);
constant C_M : integer := 23;
constant BLK_SIZE : integer := 64;
signal state : T_STATE;
signal rle_buf_sel_s : std_logic;
signal first_rle_word : std_logic;
signal word_reg : unsigned(C_M-1 downto 0);
signal bit_ptr : unsigned(4 downto 0);
signal num_fifo_wrs : unsigned(1 downto 0);
signal VLI_ext : unsigned(15 downto 0);
signal VLI_ext_size : unsigned(4 downto 0);
signal ready_HFW : std_logic;
signal fifo_wbyte : std_logic_vector(7 downto 0);
signal fifo_wrt_cnt : unsigned(1 downto 0);
signal fifo_wren : std_logic;
signal last_block : std_logic;
signal image_area_size : unsigned(31 downto 0);
signal block_cnt : unsigned(27 downto 0);
signal VLC_size : unsigned(4 downto 0);
signal VLC : unsigned(15 downto 0);
signal VLC_DC_size : std_logic_vector(3 downto 0);
signal VLC_DC : unsigned(8 downto 0);
signal VLC_AC_size : unsigned(4 downto 0);
signal VLC_AC : unsigned(15 downto 0);
signal vlc_vld : std_logic;
signal d_val_d1 : std_logic;
signal d_val_d2 : std_logic;
signal d_val_d3 : std_logic;
signal d_val_d4 : std_logic;
signal VLI_size_d : std_logic_vector(3 downto 0);
signal VLI_d : std_logic_vector(11 downto 0);
signal VLI_size_d1 : std_logic_vector(3 downto 0);
signal VLI_d1 : std_logic_vector(11 downto 0);
signal HFW_running : std_logic;
signal runlength_r : std_logic_vector(3 downto 0);
signal VLI_size_r : std_logic_vector(3 downto 0);
signal VLI_r : std_logic_vector(11 downto 0);
signal rd_en_s : std_logic;
signal pad_byte : std_logic_vector(7 downto 0);
signal pad_reg : std_logic;
signal VLC_CR_DC_size : std_logic_vector(3 downto 0);
signal VLC_CR_DC : unsigned(10 downto 0);
signal VLC_CR_AC_size : unsigned(4 downto 0);
signal VLC_CR_AC : unsigned(15 downto 0);
signal start_pb_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
rle_buf_sel <= rle_buf_sel_s;
rd_en <= rd_en_s;
vlc_vld <= rd_en_s;
-------------------------------------------------------------------
-- latch FIFO Q
-------------------------------------------------------------------
p_latch_fifo : process(CLK, RST)
begin
if RST = '1' then
VLI_size_r <= (others => '0');
VLI_r <= (others => '0');
elsif CLK'event and CLK = '1' then
if d_val = '1' then
VLI_size_r <= VLI_size;
VLI_r <= VLI;
end if;
end if;
end process;
-------------------------------------------------------------------
-- DC_ROM Luminance
-------------------------------------------------------------------
U_DC_ROM : entity work.DC_ROM
port map
(
CLK => CLK,
RST => RST,
VLI_size => VLI_size,
VLC_DC_size => VLC_DC_size,
VLC_DC => VLC_DC
);
-------------------------------------------------------------------
-- AC_ROM Luminance
-------------------------------------------------------------------
U_AC_ROM : entity work.AC_ROM
port map
(
CLK => CLK,
RST => RST,
runlength => runlength,
VLI_size => VLI_size,
VLC_AC_size => VLC_AC_size,
VLC_AC => VLC_AC
);
-------------------------------------------------------------------
-- DC_ROM Chrominance
-------------------------------------------------------------------
U_DC_CR_ROM : entity work.DC_CR_ROM
port map
(
CLK => CLK,
RST => RST,
VLI_size => VLI_size,
VLC_DC_size => VLC_CR_DC_size,
VLC_DC => VLC_CR_DC
);
-------------------------------------------------------------------
-- AC_ROM Chrominance
-------------------------------------------------------------------
U_AC_CR_ROM : entity work.AC_CR_ROM
port map
(
CLK => CLK,
RST => RST,
runlength => runlength,
VLI_size => VLI_size,
VLC_AC_size => VLC_CR_AC_size,
VLC_AC => VLC_CR_AC
);
-------------------------------------------------------------------
-- Double Fifo
-------------------------------------------------------------------
U_DoubleFifo : entity work.DoubleFifo
port map
(
CLK => CLK,
RST => RST,
-- HUFFMAN
data_in => fifo_wbyte,
wren => fifo_wren,
-- BYTE STUFFER
buf_sel => bs_buf_sel,
rd_req => bs_rd_req,
fifo_empty => bs_fifo_empty,
data_out => bs_packed_byte
);
-------------------------------------------------------------------
-- RLE buf_sel
-------------------------------------------------------------------
p_rle_buf_sel : process(CLK, RST)
begin
if RST = '1' then
rle_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
rle_buf_sel_s <= not rle_buf_sel_s;
end if;
end if;
end process;
-------------------------------------------------------------------
-- mux for DC/AC ROM Luminance/Chrominance
-------------------------------------------------------------------
p_mux : process(CLK, RST)
begin
if RST = '1' then
VLC_size <= (others => '0');
VLC <= (others => '0');
elsif CLK'event and CLK = '1' then
-- DC
if first_rle_word = '1' then
-- luminance
if huf_sm_settings.cmp_idx < 2 then
VLC_size <= unsigned('0' & VLC_DC_size);
VLC <= resize(VLC_DC, VLC'length);
-- chrominance
else
VLC_size <= unsigned('0' & VLC_CR_DC_size);
VLC <= resize(VLC_CR_DC, VLC'length);
end if;
-- AC
else
-- luminance
if huf_sm_settings.cmp_idx < 2 then
VLC_size <= VLC_AC_size;
VLC <= VLC_AC;
-- chrominance
else
VLC_size <= VLC_CR_AC_size;
VLC <= VLC_CR_AC;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- Block Counter / Last Block detector
-------------------------------------------------------------------
p_blk_cnt : process(CLK, RST)
begin
if RST = '1' then
image_area_size <= (others => '0');
last_block <= '0';
elsif CLK'event and CLK = '1' then
image_area_size <= unsigned(img_size_x)*unsigned(img_size_y);
if sof = '1' then
block_cnt <= (others => '0');
elsif start_pb = '1' then
block_cnt <= block_cnt + 1;
end if;
if block_cnt = image_area_size(31 downto 5) then
last_block <= '1';
else
last_block <= '0';
end if;
end if;
end process;
VLI_ext <= unsigned("0000" & VLI_d1);
VLI_ext_size <= unsigned('0' & VLI_size_d1);
-------------------------------------------------------------------
-- delay line
-------------------------------------------------------------------
p_vli_dly : process(CLK, RST)
begin
if RST = '1' then
VLI_d <= (others => '0');
VLI_size_d <= (others => '0');
VLI_d1 <= (others => '0');
VLI_size_d1 <= (others => '0');
d_val_d1 <= '0';
d_val_d2 <= '0';
d_val_d3 <= '0';
d_val_d4 <= '0';
elsif CLK'event and CLK = '1' then
VLI_d1 <= VLI_r;
VLI_size_d1 <= VLI_size_r;
VLI_d <= VLI_d1;
VLI_size_d <= VLI_size_d1;
d_val_d1 <= d_val;
d_val_d2 <= d_val_d1;
d_val_d3 <= d_val_d2;
d_val_d4 <= d_val_d3;
end if;
end process;
-------------------------------------------------------------------
-- HandleFifoWrites
-------------------------------------------------------------------
p_HandleFifoWrites : process(CLK, RST)
begin
if RST = '1' then
ready_HFW <= '0';
fifo_wrt_cnt <= (others => '0');
fifo_wren <= '0';
fifo_wbyte <= (others => '0');
rd_en_s <= '0';
start_pb_d1 <= '0';
elsif CLK'event and CLK = '1' then
fifo_wren <= '0';
ready_HFW <= '0';
rd_en_s <= '0';
start_pb_d1 <= start_pb;
if start_pb_d1 = '1' then
rd_en_s <= '1' and not rle_fifo_empty;
end if;
if HFW_running = '1' and ready_HFW = '0' then
-- there is no at least one integer byte to write this time
if num_fifo_wrs = 0 then
ready_HFW <= '1';
if state = RUN_VLI then
rd_en_s <= '1' and not rle_fifo_empty;
end if;
-- single byte write to FIFO
else
fifo_wrt_cnt <= fifo_wrt_cnt + 1;
fifo_wren <= '1';
-- last byte write
if fifo_wrt_cnt + 1 = num_fifo_wrs then
ready_HFW <= '1';
if state = RUN_VLI then
rd_en_s <= '1' and not rle_fifo_empty;
end if;
fifo_wrt_cnt <= (others => '0');
end if;
end if;
end if;
case fifo_wrt_cnt is
when "00" =>
fifo_wbyte <= std_logic_vector(word_reg(C_M-1 downto C_M-8));
when "01" =>
fifo_wbyte <= std_logic_vector(word_reg(C_M-8-1 downto C_M-16));
when others =>
fifo_wbyte <= (others => '0');
end case;
if pad_reg = '1' then
fifo_wbyte <= pad_byte;
end if;
end if;
end process;
-- divide by 8
num_fifo_wrs <= bit_ptr(4 downto 3);
-------------------------------------------------------------------
-- Variable Length Processor FSM
-------------------------------------------------------------------
p_vlp : process(CLK, RST)
begin
if RST = '1' then
ready_pb <= '0';
first_rle_word <= '0';
state <= IDLE;
word_reg <= (others => '0');
bit_ptr <= (others => '0');
HFW_running <= '0';
pad_reg <= '0';
pad_byte <= (others => '0');
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
case state is
when IDLE =>
if start_pb = '1' then
first_rle_word <= '1';
state <= RUN_VLC;
end if;
when RUN_VLC =>
-- data valid DC or data valid AC
if (d_val_d1 = '1' and first_rle_word = '1') or
(d_val = '1' and first_rle_word = '0') then
for i in 0 to C_M-1 loop
if i < to_integer(VLC_size) then
word_reg(C_M-1-to_integer(bit_ptr)-i) <= VLC(to_integer(VLC_size)-1-i);
end if;
end loop;
bit_ptr <= bit_ptr + resize(VLC_size,bit_ptr'length);
-- HandleFifoWrites
HFW_running <= '1';
-- HandleFifoWrites completed
elsif HFW_running = '1' and
(num_fifo_wrs = 0 or fifo_wrt_cnt + 1 = num_fifo_wrs) then
-- shift word reg left to skip bytes already written to FIFO
word_reg <= shift_left(word_reg, to_integer(num_fifo_wrs & "000"));
-- adjust bit pointer after some bytes were written to FIFO
-- modulo 8 operation
bit_ptr <= bit_ptr - (num_fifo_wrs & "000");
HFW_running <= '0';
first_rle_word <= '0';
state <= RUN_VLI;
end if;
when RUN_VLI =>
if HFW_running = '0' then
for i in 0 to C_M-1 loop
if i < to_integer(VLI_ext_size) then
word_reg(C_M-1-to_integer(bit_ptr)-i)
<= VLI_ext(to_integer(VLI_ext_size)-1-i);
end if;
end loop;
bit_ptr <= bit_ptr + resize(VLI_ext_size,bit_ptr'length);
-- HandleFifoWrites
HFW_running <= '1';
-- HandleFifoWrites completed
elsif HFW_running = '1' and
(num_fifo_wrs = 0 or fifo_wrt_cnt + 1 = num_fifo_wrs) then
-- shift word reg left to skip bytes already written to FIFO
word_reg <= shift_left(word_reg, to_integer(num_fifo_wrs & "000"));
-- adjust bit pointer after some bytes were written to FIFO
-- modulo 8 operation
bit_ptr <= bit_ptr - (num_fifo_wrs & "000");
HFW_running <= '0';
-- end of block
if rle_fifo_empty = '1' then
-- end of segment
if bit_ptr - (num_fifo_wrs & "000") /= 0 and last_block = '1' then
state <= PAD;
else
ready_pb <= '1';
state <= IDLE;
end if;
else
state <= RUN_VLC;
end if;
end if;
-- end of segment which requires bit padding
when PAD =>
if HFW_running = '0' then
-- 1's bit padding to integer number of bytes
for i in 0 to 7 loop
if i < bit_ptr then
pad_byte(7-i) <= word_reg(C_M-1-i);
else
pad_byte(7-i) <= '1';
end if;
end loop;
pad_reg <= '1';
bit_ptr <= to_unsigned(8, bit_ptr'length);
-- HandleFifoWrites
HFW_running <= '1';
elsif HFW_running = '1' and
(num_fifo_wrs = 0 or fifo_wrt_cnt + 1 = num_fifo_wrs) then
bit_ptr <= (others => '0');
HFW_running <= '0';
pad_reg <= '0';
ready_pb <= '1';
state <= IDLE;
end if;
when others =>
end case;
if sof = '1' then
bit_ptr <= (others => '0');
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | 3f8ea86df2284d0a756a80695e6faf5c | 0.356643 | 4.390403 | false | false | false | false |
trondd/mkjpeg | design/quantizer/r_divider.vhd | 2 | 4,244 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : Divider using reciprocal table --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : R_DIVIDER.VHD --
-- Created : Wed 18-03-2009 --
-- --
--------------------------------------------------------------------------------
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- MAIN DIVIDER top level
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity r_divider is
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(11 downto 0);
d : in STD_LOGIC_VECTOR(7 downto 0);
q : out STD_LOGIC_VECTOR(11 downto 0)
) ;
end r_divider ;
architecture rtl of r_divider is
signal romr_datao : std_logic_vector(15 downto 0);
signal romr_addr : std_logic_vector(7 downto 0);
signal dividend : signed(11 downto 0);
signal dividend_d1 : unsigned(11 downto 0);
signal reciprocal : unsigned(15 downto 0);
signal mult_out : unsigned(27 downto 0);
signal mult_out_s : signed(11 downto 0);
signal signbit : std_logic;
signal signbit_d1 : std_logic;
signal signbit_d2 : std_logic;
signal signbit_d3 : std_logic;
signal round : std_logic;
begin
U_ROMR : entity work.ROMR
generic map
(
ROMADDR_W => 8,
ROMDATA_W => 16
)
port map
(
addr => romr_addr,
clk => CLK,
datao => romr_datao
);
romr_addr <= d;
reciprocal <= unsigned(romr_datao);
dividend <= signed(a);
signbit <= dividend(dividend'high);
rdiv : process(clk,rst)
begin
if rst = '1' then
mult_out <= (others => '0');
mult_out_s <= (others => '0');
dividend_d1 <= (others => '0');
q <= (others => '0');
signbit_d1 <= '0';
signbit_d2 <= '0';
signbit_d3 <= '0';
round <= '0';
elsif clk = '1' and clk'event then
signbit_d1 <= signbit;
signbit_d2 <= signbit_d1;
signbit_d3 <= signbit_d2;
if signbit = '1' then
dividend_d1 <= unsigned(0-dividend);
else
dividend_d1 <= unsigned(dividend);
end if;
mult_out <= dividend_d1 * reciprocal;
if signbit_d2 = '0' then
mult_out_s <= resize(signed(mult_out(27 downto 16)),mult_out_s'length);
else
mult_out_s <= resize(0-signed(mult_out(27 downto 16)),mult_out_s'length);
end if;
round <= mult_out(15);
if signbit_d3 = '0' then
if round = '1' then
q <= std_logic_vector(mult_out_s + 1);
else
q <= std_logic_vector(mult_out_s);
end if;
else
if round = '1' then
q <= std_logic_vector(mult_out_s - 1);
else
q <= std_logic_vector(mult_out_s);
end if;
end if;
end if;
end process;
end rtl;
| lgpl-3.0 | 035da9ed8dd02db3104cf0b349272ef0 | 0.349434 | 4.689503 | false | false | false | false |
mkreider/cocotb2 | examples/wb/hdl/cocotb_prio2.vhd | 2 | 2,741 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.prio_pkg.all;
entity cocotb_prio2 is
port (
clk : in std_logic;
reset_n : in std_logic;
clk2 : in std_logic;
reset_n2 : in std_logic;
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_datrd : out std_logic_vector(31 downto 0);
wbs_datwr : in std_logic_vector(31 downto 0);
--wbs_stall : out std_logic;
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbm_cyc : out std_logic;
wbm_stb : out std_logic;
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_datrd : in std_logic_vector(31 downto 0);
wbm_datwr : out std_logic_vector(31 downto 0);
wbm_err : in std_logic;
wbm_stall : in std_logic;
wbm_ack : in std_logic;
ts_out : out std_logic_vector(63 downto 0);
ts_valid_out : out std_logic;
en_in : in std_logic
);
end entity;
architecture rtl of cocotb_prio2 is
signal s_master_out : t_wishbone_master_out;
signal s_slave_out : t_wishbone_slave_out;
signal s_master_in : t_wishbone_master_in;
signal s_slave_in : t_wishbone_slave_in;
begin
-- in from TB Slave to DUT Master
wbm_we <= s_master_out.we;
wbm_stb <= s_master_out.stb;
wbm_datwr <= s_master_out.dat;
wbm_adr <= s_master_out.adr;
wbm_sel <= s_master_out.sel;
wbm_cyc <= s_master_out.cyc;
-- out from DUT Master to TB Slave
s_master_in.dat <= wbm_datrd;
s_master_in.ack <= wbm_ack;
s_master_in.stall <= wbm_stall;
s_master_in.err <= wbm_err;
-- in from TB Master to DUT Slave
s_slave_in.we <= wbs_we;
s_slave_in.stb <= wbs_stb;
s_slave_in.dat <= wbs_datwr;
s_slave_in.adr <= wbs_adr;
s_slave_in.sel <= wbs_sel ;
s_slave_in.cyc <= wbs_cyc;
-- out from TB Master to DUT Slave
wbs_datrd <= s_slave_out.dat;
wbs_ack <= s_slave_out.ack;
wbs_err <= s_slave_out.err;
--wbs_stall <= s_slave_out.stall;
dut : queue_unit
generic map(
g_depth => 32,
g_words => 8
)
port map(
clk_i => clk,
rst_n_i => reset_n,
master_o => s_master_out,
master_i => s_master_in,
slave_i => s_slave_in,
slave_o => s_slave_out,
ts_o => ts_out,
ts_valid_o => ts_valid_out
);
end architecture;
| bsd-3-clause | e4d884a3d7ebcba3e3a3cf6c994f5a4e | 0.556001 | 2.858186 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/sigma_delta_dac/vhdl_source/pdm_with_volume.vhd | 1 | 4,711 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity pdm_with_volume is
generic (
g_width : positive := 12;
g_invert : boolean := false;
g_use_mid_only : boolean := true;
g_left_shift : natural := 1 );
port (
clock : in std_logic;
reset : in std_logic;
volume : in std_logic_vector(3 downto 0) := X"F";
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end entity;
architecture gideon of pdm_with_volume is
signal dac_in_scaled : signed(g_width-1 downto g_left_shift);
signal converted : unsigned(g_width downto g_left_shift);
signal out_i : std_logic;
signal accu : unsigned(converted'range);
signal divider : integer range 0 to 15;
signal pattern : std_logic_vector(15 downto 0);
type t_patterns is array(0 to 15) of std_logic_vector(15 downto 0);
-- constant c_patterns : t_patterns := (
-- 0 => X"FF00", -- 8 ones and 8 zeros (off, but you may hear the unbalance)
-- 1 => X"FF80", -- 9 ones and 7 zeros
-- 2 => X"FFC0", -- 10 ones and 6 zeros
-- 3 => X"FFE0", -- 11 ones and 5 zeros
-- 4 => X"FFF0", -- 12 ones and 4 zeros
-- 5 => X"FFF8", -- 13 ones and 3 zeros
-- 6 => X"FFFC", -- 14 ones and 2 zeros
-- 7 => X"FFFE", -- 15 ones and 1 zero
-- 8 => X"FFFF", -- 16 ones and 0 zeros
-- 9 => X"FF08", -- experimental 8 ones 7 zeros (short '1')
-- 10 => X"F88F", -- experimental 9 ones 6 zeros (short '1')
-- 11 => X"FC0F", -- 10 ones and 6 zeros shifted
-- 12 => X"FE0F", -- 11 ones and 5 zeros shifted
-- 13 => X"FF0F", -- 12 ones and 4 zeros shifted
-- 14 => X"FF8F", -- 13 ones and 3 zeros shifted
-- 15 => X"FFCF" -- 14 ones and 2 zeros shifted
-- );
constant c_patterns : t_patterns := (
1 => "1111000010001111", -- 9 ones and 7 zeros (single one separate)
2 => "1111100000001111", -- 9 ones and 7 zeros (one extended)
3 => "1111100010001111", -- 10 ones and 6 zeros (single one separate)
4 => "1111100000011111", -- 10 ones and 6 zeros (one extended)
5 => "1111110000011111", -- 11 ones and 5 zeros
6 => "1111110000111111", -- 12 ones and 4 zeros
7 => "1111111000111111", -- 13 ones and 3 zeros
8 => "1111111001111111", -- 14 ones and 2 zeros
9 => "1111111101111111", -- 15 ones and 1 zero
10 => "1111111111111111", -- 16 ones and 0 zeros
others => "1111000000001111" -- 8 ones and 8 zeros (off, but you may hear the unbalance)
);
begin
dac_in_scaled <= left_scale(dac_in, g_left_shift);
converted <= (not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high downto g_left_shift))) when g_use_mid_only else
(not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high-1 downto g_left_shift))) & '0';
process(clock)
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
variable a_new : unsigned(accu'range);
variable carry : std_logic;
begin
if rising_edge(clock) then
if divider = 15 then
if out_i = '0' then
pattern <= c_patterns(to_integer(unsigned(volume)));
else
pattern <= not c_patterns(to_integer(unsigned(volume)));
end if;
divider <= 0;
sum_with_carry(accu, converted, a_new, carry);
accu <= a_new;
if g_invert then
out_i <= not carry;
else
out_i <= carry;
end if;
else
divider <= divider + 1;
pattern <= '0' & pattern(pattern'high downto 1);
end if;
if reset='1' then
out_i <= not out_i;
accu <= (others => '0');
pattern <= X"5555";
end if;
end if;
end process;
dac_out <= pattern(0);
end gideon;
| gpl-3.0 | 50619e8f9d58b614f9febfd6953d34e8 | 0.516026 | 3.604438 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/harness_c1541.vhd | 1 | 4,409 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1541 is
end harness_c1541;
architecture harness of harness_c1541 is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal iec_atn : std_logic;
signal iec_atn_o : std_logic;
signal iec_atn_i : std_logic;
signal iec_data : std_logic;
signal iec_data_o : std_logic;
signal iec_data_i : std_logic;
signal iec_clk : std_logic;
signal iec_clk_o : std_logic;
signal iec_clk_i : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal act_led_n : std_logic;
signal audio_sample : signed(12 downto 0);
signal tick_16MHz : std_logic := '0';
signal tick_4MHz : std_logic := '0';
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 1000 ns;
process
begin
--wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '0';
--wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '0';
--wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '0';
--wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '1';
end process;
-- process(clock)
-- variable count : integer := 0;
-- begin
-- if rising_edge(clock) then
-- cpu_clock_en <= '0';
-- drv_clock_en <= '0';
--
-- case count is
-- when 0 | 12 | 25 | 37 =>
-- drv_clock_en <= '1';
-- count := count + 1;
-- when 49 =>
-- cpu_clock_en <= '1';
-- count := 0;
-- when others =>
-- count := count + 1;
-- end case;
-- end if;
-- end process;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_drive: entity work.c1541_drive
generic map (
g_big_endian => false,
g_audio => true,
g_audio_base => X"0010000",
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
-- timing
tick_16MHz => tick_16MHz,
tick_4MHz => tick_4MHz,
-- slave port on io bus
io_req => io_req,
io_resp => io_resp,
-- master port on memory bus
mem_req => mem_req,
mem_resp => mem_resp,
via1_port_a_i => X"FF",
via1_ca2_i => '1',
via1_cb1_i => '1',
-- serial bus pins
atn_o => iec_atn_o, -- open drain
atn_i => iec_atn_i,
clk_o => iec_clk_o, -- open drain
clk_i => iec_clk_i,
data_o => iec_data_o, -- open drain
data_i => iec_data_i,
-- LED
act_led_n => act_led_n,
-- audio out
audio_sample => audio_sample );
iec_atn <= '0' when iec_atn_o='0' else 'Z';
iec_atn_i <= '0' when iec_atn='0' else '1';
iec_clk <= '0' when iec_clk_o='0' else 'Z';
iec_clk_i <= '0' when iec_clk='0' else '1';
iec_data <= '0' when iec_data_o='0' else 'Z';
iec_data_i <= '0' when iec_data='0' else '1';
i_memory: entity work.mem_bus_slave_bfm
generic map(
g_name => "dram",
g_latency => 2
)
port map(
clock => clock,
req => mem_req,
resp => mem_resp
);
end harness;
| gpl-3.0 | a4e7e9723b8b293b207c5ae17b80230f | 0.437287 | 3.305097 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/ulpi_rx.vhd | 1 | 9,166 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_support_split : boolean := true;
g_support_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
crc_sync : out std_logic;
crc_dvalid : out std_logic;
data_crc : in std_logic_vector(15 downto 0);
status : in std_logic_vector(7 downto 0);
usb_rx : out t_usb_rx );
end ulpi_rx;
architecture gideon of ulpi_rx is
type t_state is (idle, token0, token1, token2, check_token, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(18 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_tvalid : std_logic;
signal crc_sync_i : std_logic;
signal rx_valid_d : std_logic;
signal pid : std_logic_vector(3 downto 0);
signal valid_token : std_logic;
signal valid_split : std_logic;
signal valid_handsh : std_logic;
signal valid_packet : std_logic;
signal data_valid : std_logic;
signal data_start : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal error : std_logic;
signal error_code : std_logic_vector(3 downto 0);
signal rx_data_d1 : std_logic_vector(7 downto 0);
signal rx_data_d2 : std_logic_vector(7 downto 0);
signal rx_valid_d1 : std_logic;
signal rx_valid_d2 : std_logic;
signal recv_d : std_logic_vector(1 to 3);
--signal ipd_counter : unsigned(tx_holdoff_delay'range) := (others => '0'); -- interpacket delay
begin
usb_rx.token <= vector_to_token(token_i(18 downto 8));
usb_rx.split_token <= vector_to_split_token(token_i(18 downto 0));
usb_rx.pid <= pid;
usb_rx.valid_token <= valid_token;
usb_rx.valid_split <= valid_split;
usb_rx.valid_handsh <= valid_handsh;
usb_rx.valid_packet <= valid_packet;
usb_rx.data_valid <= data_valid and rx_valid_d2;
usb_rx.data_start <= data_start;
usb_rx.data <= data_out;
usb_rx.error <= error;
usb_rx.error_code <= error_code(2 downto 0);
usb_rx.receiving <= rx_store or recv_d(1) or recv_d(2) or recv_d(3) or status(4);
process(clock)
begin
if rising_edge(clock) then
error <= '0';
error_code <= X"0";
data_start <= '0';
valid_token <= '0';
valid_split <= '0';
valid_packet <= '0';
valid_handsh <= '0';
-- if rx_store = '1' then -- reset interpacket delay counter for transmit
-- tx_holdoff <= '1';
-- ipd_counter <= tx_holdoff_delay;
-- else
-- if ipd_counter = 0 then
-- tx_holdoff <= '0';
-- else
-- ipd_counter <= ipd_counter - 1;
-- end if;
-- end if;
recv_d <= rx_store & recv_d(1 to 2);
rx_data_d1 <= rx_data;
if data_valid='1' then
rx_data_d2 <= rx_data_d1;
data_out <= rx_data_d2;
rx_valid_d1 <= '1';
rx_valid_d2 <= rx_valid_d1;
end if;
data_valid <= '0';
rx_valid_d <= rx_valid;
case state is
when idle =>
rx_valid_d1 <= '0';
rx_valid_d2 <= '0';
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_support_token then
state <= token1;
else
error <= '1';
error_code <= X"1"; -- unsupported token
end if;
elsif is_split(rx_data(3 downto 0)) then
if g_support_split then
state <= token0;
else
error <= '1';
error_code <= X"1"; -- unsupported token
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
error_code <= X"2"; -- error in PID
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
error_code <= X"3"; -- handshake expected, data received
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token0 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token1;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
error_code <= X"4"; -- truncated token
state <= resync;
end if;
when token1 =>
if rx_store='1' then
token_i(15 downto 8) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
error_code <= X"4"; -- truncated token
state <= resync;
end if;
when token2 =>
if rx_store='1' then
token_i(18 downto 16) <= rx_data(2 downto 0);
state <= check_token;
end if;
when data =>
data_valid <= rx_store;
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
error_code <= X"5"; -- data CRC error
end if;
state <= idle;
when check_token =>
if token_crc = "11001" then
if is_split(pid) then
valid_split <= '1';
else
valid_token <= '1';
end if;
else
error <= '1';
error_code <= X"6"; -- token CRC error
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
end if;
end if;
end process;
r_token: if g_support_token or g_support_split generate
i_token_crc: entity work.token_crc_check
port map (
clock => clock,
sync => crc_sync_i,
valid => crc_tvalid,
data_in => rx_data,
crc => token_crc );
end generate;
crc_sync_i <= (rx_valid and rx_store) when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
crc_tvalid <= rx_store when (state = token0) or (state = token1) or (state = token2) else '0';
crc_sync <= crc_sync_i;
end gideon;
| gpl-3.0 | 8de8aefbadc5ba1c6c4034981c02cb65 | 0.401811 | 4.225911 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_altmemddr_0_phy_alt_mem_phy_seq.vhd | 2 | 648,595 | --
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package nios_altmemddr_0_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end nios_altmemddr_0_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package nios_altmemddr_0_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "nios_altmemddr_0_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end nios_altmemddr_0_phy_alt_mem_phy_record_pkg;
--
package body nios_altmemddr_0_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 9;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END nios_altmemddr_0_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package nios_altmemddr_0_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "nios_altmemddr_0_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end nios_altmemddr_0_phy_alt_mem_phy_addr_cmd_pkg;
--
package body nios_altmemddr_0_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end nios_altmemddr_0_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package nios_altmemddr_0_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end nios_altmemddr_0_phy_alt_mem_phy_iram_addr_pkg;
--
package body nios_altmemddr_0_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END nios_altmemddr_0_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.nios_altmemddr_0_phy_alt_mem_phy_constants_pkg.all;
--
package nios_altmemddr_0_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "nios_altmemddr_0_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end nios_altmemddr_0_phy_alt_mem_phy_regs_pkg;
--
package body nios_altmemddr_0_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end nios_altmemddr_0_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_record_pkg.all;
--
entity nios_altmemddr_0_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.nios_altmemddr_0_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.nios_altmemddr_0_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.nios_altmemddr_0_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of nios_altmemddr_0_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "nios_altmemddr_0_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity nios_altmemddr_0_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.nios_altmemddr_0_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of nios_altmemddr_0_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "nios_altmemddr_0_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 10;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
ac_state <= s_0;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_record_pkg.all;
--
entity nios_altmemddr_0_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of nios_altmemddr_0_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.nios_altmemddr_0_phy_alt_mem_phy_iram_ram;
--
entity nios_altmemddr_0_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.nios_altmemddr_0_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of nios_altmemddr_0_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "nios_altmemddr_0_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity nios_altmemddr_0_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.nios_altmemddr_0_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.nios_altmemddr_0_phy_alt_mem_phy_constants_pkg.all;
--
entity nios_altmemddr_0_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of nios_altmemddr_0_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "nios_altmemddr_0_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity nios_altmemddr_0_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.nios_altmemddr_0_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of nios_altmemddr_0_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "nios_altmemddr_0_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.nios_altmemddr_0_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity nios_altmemddr_0_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.nios_altmemddr_0_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of nios_altmemddr_0_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "nios_altmemddr_0_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity nios_altmemddr_0_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.nios_altmemddr_0_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.nios_altmemddr_0_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.nios_altmemddr_0_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.nios_altmemddr_0_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.nios_altmemddr_0_phy_alt_mem_phy_admin;
--
use work.nios_altmemddr_0_phy_alt_mem_phy_mmi;
--
use work.nios_altmemddr_0_phy_alt_mem_phy_iram;
--
use work.nios_altmemddr_0_phy_alt_mem_phy_dgrb;
--
use work.nios_altmemddr_0_phy_alt_mem_phy_dgwb;
--
use work.nios_altmemddr_0_phy_alt_mem_phy_ctrl;
--
architecture struct of nios_altmemddr_0_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "nios_altmemddr_0_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity nios_altmemddr_0_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity nios_altmemddr_0_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity nios_altmemddr_0_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity nios_altmemddr_0_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity nios_altmemddr_0_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity nios_altmemddr_0_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
| gpl-3.0 | 6a6c38df710b2c534cd103e2c4438686 | 0.442089 | 4.4225 | false | false | false | false |
bgunebakan/toyrobot | TopDesign.vhd | 1 | 3,420 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:11:22 12/18/2014
-- Design Name:
-- Module Name: TopDesign - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TopDesign is
Port ( pulse_pin : in STD_LOGIC;
Trigger_pin : out STD_LOGIC;
clk : in STD_LOGIC;
topselDispA : out STD_LOGIC;
topselDispB : out STD_LOGIC;
topselDispC : out STD_LOGIC;
topselDispD : out STD_LOGIC;
topsegA : out STD_LOGIC;
topsegB : out STD_LOGIC;
topsegC : out STD_LOGIC;
topsegD : out STD_LOGIC;
topsegE : out STD_LOGIC;
topsegF : out STD_LOGIC;
topsegG : out STD_LOGIC);
end TopDesign;
architecture Behavioral of TopDesign is
component Range_sensor
port(
fpgaclk : in STD_LOGIC;
triggerOut : out STD_LOGIC;
pulse: in STD_LOGIC;
meters: out STD_LOGIC_VECTOR(3 DOWNTO 0);
decimeters : out STD_LOGIC_VECTOR(3 DOWNTO 0);
centimeters : out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
component segmentdriver
Port(
display_A: in STD_LOGIC_VECTOR (3 DOWNTO 0);
display_B: in STD_LOGIC_VECTOR (3 DOWNTO 0);
display_C: in STD_LOGIC_VECTOR (3 DOWNTO 0);
display_D: in STD_LOGIC_VECTOR (3 DOWNTO 0);
segA: out STD_LOGIC;
segB: out STD_LOGIC;
segC: out STD_LOGIC;
segD: out STD_LOGIC;
segE: out STD_LOGIC;
segF: out STD_LOGIC;
segG: out STD_LOGIC;
select_Display_A: out STD_LOGIC;
select_Display_B: out STD_LOGIC;
select_Display_C: out STD_LOGIC;
select_Display_D: out STD_LOGIC;
clk: in STD_LOGIC
);
end component;
SIGNAL Ai : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Bi : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Ci : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Di : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sensor_meters :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sensor_decimeters :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sensor_centimeters :STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
uut2: segmentDriver PORT MAP(
display_A=>Ai,
display_B=>Bi,
display_C=>Ci,
display_D=>Di,
segA => topsegA,
segB => topsegB,
segC => topsegC,
segD => topsegD,
segE => topsegE,
segF => topsegF,
segG => topsegG,
select_Display_A => topselDispA,
select_Display_B => topselDispB,
select_Display_C => topselDispC,
select_Display_D => topselDispD,
clk => clk
);
uut4: Range_sensor PORT MAP(
fpgaclk => clk,
triggerOut => Trigger_pin,
pulse => pulse_pin,
meters => sensor_meters,
decimeters=> sensor_decimeters,
centimeters=> sensor_centimeters
);
Ai <= sensor_centimeters;
Bi <= sensor_decimeters;
Ci <= sensor_meters;
Di <="0000";
end Behavioral;
| gpl-2.0 | 6a1f7dfeaf538a24b06cd6a42381155b | 0.618129 | 3.152074 | false | false | false | false |
armandas/Plong | plong.vhd | 1 | 2,928 | library ieee;
use ieee.std_logic_1164.all;
entity plong is
port (
clk, not_reset: in std_logic;
nes_data_1: in std_logic;
nes_data_2: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(2 downto 0);
speaker: out std_logic;
nes_clk_out: out std_logic;
nes_ps_control: out std_logic
);
end plong;
architecture arch of plong is
signal rgb_reg, rgb_next: std_logic_vector(2 downto 0);
signal video_on: std_logic;
signal px_x, px_y: std_logic_vector(9 downto 0);
signal ball_bounced, ball_missed: std_logic;
signal nes_start: std_logic;
signal nes1_start, nes1_up, nes1_down,
nes2_start, nes2_up, nes2_down: std_logic;
begin
process (clk, not_reset)
begin
if clk'event and clk = '0' then
rgb_reg <= rgb_next;
end if;
end process;
-- instantiate VGA Synchronization circuit
vga_sync_unit:
entity work.vga(sync)
port map(
clk => clk, not_reset => not_reset,
hsync => hsync, vsync => vsync,
video_on => video_on,
pixel_x => px_x, pixel_y => px_y
);
graphics_unit:
entity work.graphics(dispatcher)
port map(
clk => clk, not_reset => not_reset,
nes1_up => nes1_up, nes1_down => nes1_down,
nes2_up => nes2_up, nes2_down => nes2_down,
nes_start => nes_start,
px_x => px_x, px_y => px_y,
video_on => video_on,
rgb_stream => rgb_next,
ball_bounced => ball_bounced,
ball_missed => ball_missed
);
nes_start <= (nes1_start or nes2_start);
sound:
entity work.player(behaviour)
port map(
clk => clk, not_reset => not_reset,
bump_sound => ball_bounced, miss_sound => ball_missed,
speaker => speaker
);
NES_controller1:
entity work.controller(arch)
port map(
clk => clk, not_reset => not_reset,
data_in => nes_data_1,
clk_out => nes_clk_out,
ps_control => nes_ps_control,
gamepad(0) => open, gamepad(1) => open,
gamepad(2) => open, gamepad(3) => nes1_start,
gamepad(4) => nes1_up, gamepad(5) => nes1_down,
gamepad(6) => open, gamepad(7) => open
);
NES_controller2:
entity work.controller(arch)
port map(
clk => clk, not_reset => not_reset,
data_in => nes_data_2,
clk_out => open,
ps_control => open,
gamepad(0) => open, gamepad(1) => open,
gamepad(2) => open, gamepad(3) => nes2_start,
gamepad(4) => nes2_up, gamepad(5) => nes2_down,
gamepad(6) => open, gamepad(7) => open
);
rgb <= rgb_reg;
end arch;
| bsd-2-clause | 108b1923d54136a663405b0e002d8574 | 0.512637 | 3.440658 | false | false | false | false |
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