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int64 137
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stringlengths 137
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stringclasses 15
values | hash
stringlengths 32
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float64 0.25
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float64 1.51
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bool 1
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classes | has_no_keywords
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class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
chiggs/nvc | test/sem/record.vhd | 1 | 2,681 | package p is
type r1 is record -- OK
x : integer;
y : integer;
end record;
type r2 is record -- Error
x, x : integer;
end record;
type r3;
type r3 is record -- Error
x : r3;
end record;
type r4 is record
x, y, z : integer;
end record;
type r5 is record
x : r1;
y : integer;
end record;
type r1_vec is array (integer range <>) of r1;
type r6 is record
x : r1_vec; -- Error
end record;
end package;
package body p is
procedure p1 is
variable v1 : r1 := (1, 2);
variable v2 : r4 := (1, 2); -- Error
variable v3 : r1 := (1, v1); -- Error
variable v4 : r1 := (x => 1, y => 2);
variable v5 : r1 := (x => 1); -- Error
variable v6 : r1 := (x => 1, y => 2, q => 1); -- Error
variable v7 : r1 := (x => 1, y => v1); -- Error
variable v8 : r1 := (others => 9);
variable v9 : r1 := (x => 1, others => 2);
variable v10 : r1 := (x => 1, x => 2, y => 3); -- Error
variable v11 : r1 := (1, x => 4, y => 2); -- Error
variable v12 : r1 := (1, y => 4);
variable v13 : r1;
begin
end procedure;
procedure p2 is
variable v1 : r1;
variable v2 : r5;
begin
v1.x := 2;
v1.y := v1.x + 5;
v2.x.x := 3;
end procedure;
procedure p3 is
variable a1 : r1_vec; -- Error
begin
end procedure;
procedure p4 is
variable a2 : r1_vec(0 to 3); -- OK
begin
a2(2).x := 5; -- OK
a2(1).f := 2; -- Error
a2(0).x := a2(1).y; -- OK
end procedure;
procedure p5 is
subtype r1_sub is r1; -- OK
variable a : r1_sub; -- OK
begin
a.x := 5; -- OK
a.y := a.x + 2; -- OK
a.z := 2; -- Error
end procedure;
procedure p6 is
subtype r1_bad is r1(1 to 3); -- Error
begin
end procedure;
procedure p7 is
type rec is record
vec : bit_vector(1 to 3);
end record;
variable a : rec;
begin
assert a.vec'length = 3; -- OK
end procedure;
procedure p8 is
function make_r1 return r1 is
begin
return (x => 1, y => 2);
end function;
begin
assert make_r1.x = 1; -- OK
assert make_r1.z = 2; -- Error
end procedure;
end package body;
| gpl-3.0 | 98bff1d0cd2886d42097ab4999cf6dbb | 0.420739 | 3.495437 | false | false | false | false |
armandas/Arcade | level_info.vhd | 2 | 2,903 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity level_info is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
level: in std_logic_vector(8 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end level_info;
architecture display of level_info is
constant WIDTH: integer := 48;
constant HEIGHT: integer := 8;
signal font_addr: std_logic_vector(8 downto 0);
signal font_data: std_logic_vector(0 to 7);
signal font_pixel: std_logic;
signal text_font_addr: std_logic_vector(8 downto 0);
signal number_font_addr: std_logic_vector(8 downto 0);
signal text_enable: std_logic;
signal number_enable: std_logic;
signal bcd: std_logic_vector(3 downto 0);
signal bcd0, bcd1, bcd2: std_logic_vector(3 downto 0);
begin
text_enable <= '1' when (px_x >= 0 and
px_x < WIDTH and
px_y >= 0 and
px_y < HEIGHT) else
'0';
-- +16 and +40 used to right-align the level with score
number_enable <= '1' when (px_x >= WIDTH + 16 and
px_x < WIDTH + 40 and
px_y >= 0 and
px_y < HEIGHT) else
'0';
with px_x(9 downto 3) select
text_font_addr <= "101100000" when "0000000", -- L
"100101000" when "0000001", -- E
"110110000" when "0000010", -- V
"100101000" when "0000011", -- E
"101100000" when "0000100", -- L
"000000000" when others; -- space
bcd <= bcd0 when px_x(9 downto 3) = 10 else
bcd1 when px_x(9 downto 3) = 9 else
bcd2 when px_x(9 downto 3) = 8 else
(others => '0');
-- numbers start at memory location 128
-- '1' starts at 136, '2' at 144 and so on
-- bcd is multiplied by 8 to get the right digit
number_font_addr <= conv_std_logic_vector(128, 9) + (bcd & "000");
font_addr <= px_y(2 downto 0) + text_font_addr when text_enable = '1' else
px_y(2 downto 0) + number_font_addr when number_enable = '1' else
(others => '0');
font_pixel <= font_data(conv_integer(px_x(2 downto 0)));
rgb_pixel <= "111" when font_pixel = '1' else "000";
bin_to_bcd:
entity work.bin2bcd(behaviour)
generic map(N_BIN => 9)
port map(
clk => clk, not_reset => not_reset,
binary_in => level,
bcd0 => bcd0, bcd1 => bcd1, bcd2 => bcd2,
bcd3 => open, bcd4 => open
);
codepage:
entity work.codepage_rom(content)
port map(addr => font_addr, data => font_data);
end display;
| bsd-2-clause | 9061b63b08eddd4567e9c72acd70f480 | 0.522907 | 3.646985 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/watchdog/cb20/synthesis/cb20_gpio_block_0_avalon_slave_0_translator.vhd | 1 | 14,661 | -- cb20_gpio_block_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 4;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(3 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_gpio_block_0_avalon_slave_0_translator;
architecture rtl of cb20_gpio_block_0_avalon_slave_0_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(3 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
gpio_block_0_avalon_slave_0_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_gpio_block_0_avalon_slave_0_translator
| apache-2.0 | 656cfe8cc404b7aba1139cf29146be12 | 0.429711 | 4.335009 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_sim/token_crc_tb.vhd | 2 | 1,527 | -------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_tb is
end token_crc_tb;
architecture tb of token_crc_tb is
signal clock : std_logic := '0';
signal token_in : std_logic_vector(10 downto 0);
signal crc : std_logic_vector(4 downto 0);
signal total : std_logic_vector(15 downto 0);
begin
i_mut: entity work.usb1_token_crc
port map (
clock => clock,
sync => '1',
token_in => token_in,
crc => crc );
clock <= not clock after 10 ns;
p_test: process
begin
token_in <= "0001" & "0000001"; -- EP=1 / ADDR=1
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "111" & X"FB";
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "000" & X"01";
wait;
end process;
total <= crc & token_in;
end tb;
| gpl-3.0 | 5081a63117825895aab61410a650cffd | 0.413229 | 4.375358 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/free_queue/vhdl_sim/free_queue_tb.vhd | 1 | 6,253 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : free_queue_tb
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Quick test bench for free queue
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.block_bus_pkg.all;
entity free_queue_tb is
end entity;
architecture test of free_queue_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal alloc_req : std_logic := '0';
signal alloc_resp : t_alloc_resp;
signal used_req : t_used_req := c_used_req_init;
signal used_resp : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_irq : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.free_queue
port map (
clock => clock,
reset => reset,
alloc_req => alloc_req,
alloc_resp => alloc_resp,
used_req => used_req,
used_resp => used_resp,
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq
);
i_bfm: entity work.io_bus_bfm
generic map ("io")
port map (
clock => clock,
req => io_req,
resp => io_resp
);
process
variable io : p_io_bus_bfm_object;
variable v_id : integer;
variable data : std_logic_vector(7 downto 0);
variable data16 : std_logic_vector(15 downto 0);
procedure io_write_long(variable io : inout p_io_bus_bfm_object; addr : natural; data : std_logic_vector(31 downto 0)) is
begin
io_write(io, to_unsigned(addr+0, 20), data(07 downto 00));
io_write(io, to_unsigned(addr+1, 20), data(15 downto 08));
io_write(io, to_unsigned(addr+2, 20), data(23 downto 16));
io_write(io, to_unsigned(addr+3, 20), data(31 downto 24));
end procedure;
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : natural; data : std_logic_vector(7 downto 0)) is
begin
io_write(io, to_unsigned(addr, 20), data);
end procedure;
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : natural; data : out std_logic_vector(7 downto 0)) is
begin
io_read(io, to_unsigned(addr, 20), data);
end procedure;
procedure io_read_word(variable io : inout p_io_bus_bfm_object; addr : natural; data : out std_logic_vector(15 downto 0)) is
begin
io_read(io, to_unsigned(addr, 20), data(7 downto 0));
io_read(io, to_unsigned(addr+1, 20), data(15 downto 8));
end procedure;
procedure alloc is
begin
wait until clock = '1';
alloc_req <= '1';
wait until clock = '1';
while alloc_resp.done = '0' loop
wait until clock = '1';
end loop;
alloc_req <= '0';
end procedure;
procedure free(id : natural) is
begin
io_write(io, 4, std_logic_vector(to_unsigned(id, 8)));
end procedure;
procedure reset_queue is
begin
io_write(io, 14, X"01");
end procedure;
procedure used(id : natural; size: unsigned(11 downto 0)) is
begin
wait until clock = '1';
used_req.request <= '1';
used_req.id <= to_unsigned(id, 8);
used_req.bytes <= size;
wait until clock = '1';
while used_resp = '0' loop
wait until clock = '1';
end loop;
used_req.request <= '0';
end procedure;
begin
wait until reset = '0';
bind_io_bus_bfm("io", io);
io_write_long(io, 0, X"12345678");
free(17);
alloc;
v_id := to_integer(alloc_resp.id);
assert(v_id = 17) report "Unexpected ID";
assert(to_integer(alloc_resp.address) = (16#2345600# + v_id * 1536)) report "Unexpected address";
used(v_id, X"ABC");
wait until io_irq = '1';
io_read(io, 15, data);
assert data(0) = '1' report "Expected an allocated block to be available";
io_read(io, 8, data);
assert data = X"11" report "Expected allocated block to have ID 11";
io_read_word(io, 10, data16);
assert data16 = X"0ABC" report "Expected length to be 0xABC";
io_write(io, 15, X"00"); -- pop!
io_read(io, 15, data);
assert data(0) = '0' report "Expected no more allocated blocks to be available";
free(0); --add free block 00
alloc;
v_id := to_integer(alloc_resp.id);
assert(v_id = 0) report "Unexpected ID";
assert(to_integer(alloc_resp.address) = (16#2345600# + v_id * 1536)) report "Unexpected address";
alloc;
assert(alloc_resp.error = '1') report "Allocation should now fail";
-- check reset
free(55); --add free block
reset_queue;
alloc;
assert(alloc_resp.error = '1') report "Allocation should now fail";
--for i in 0 to 130 loop -- deliberately overwrite as depth = 128
for i in 0 to 126 loop
free(i);
end loop;
alloc; -- 0
alloc; -- 1
alloc; -- 2
alloc; -- 3
alloc; -- 4
v_id := to_integer(alloc_resp.id);
assert(v_id = 4) report "Unexpected ID";
for i in 0 to 4 loop
free(i);
end loop;
alloc; -- 5
alloc; -- 6
alloc; -- 7
alloc; -- 8
alloc; -- 9
v_id := to_integer(alloc_resp.id);
assert(v_id = 9) report "Unexpected ID";
wait;
end process;
end architecture;
| gpl-3.0 | ab0a1977de72413ff400ff11f7bf7bce | 0.504398 | 3.791995 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_source/rmii_transceiver.vhd | 1 | 9,545 | -------------------------------------------------------------------------------
-- Title : rmii_transceiver
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Receiver / transmitter for RMII
-- TODO: Implement 10 Mbps mode
--
-- NOTE: The receive stream will include the FCS, and also an
-- additional byte, which indicates the correctness of the FCS.
-- This byte will be FF when correct and 00 when incorrect. It
-- coincides with eof. So CRC checking is done, CRC stripping is
-- not. The transmit path appends CRC after receiving the last
-- byte through the stream bus (thus after eof).
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rmii_transceiver is
port (
clock : in std_logic; -- 50 MHz reference clock
reset : in std_logic;
rmii_crs_dv : in std_logic;
rmii_rxd : in std_logic_vector(1 downto 0);
rmii_tx_en : out std_logic;
rmii_txd : out std_logic_vector(1 downto 0);
-- stream bus alike interface to MAC
eth_rx_data : out std_logic_vector(7 downto 0);
eth_rx_sof : out std_logic;
eth_rx_eof : out std_logic;
eth_rx_valid : out std_logic;
eth_tx_data : in std_logic_vector(7 downto 0);
eth_tx_eof : in std_logic;
eth_tx_valid : in std_logic;
eth_tx_ready : out std_logic;
-- Mode switch
ten_meg_mode : in std_logic );
end entity;
architecture rtl of rmii_transceiver is
type t_state is (idle, preamble, data0, data1, data2, data3, crc, gap);
signal rx_state : t_state;
signal tx_state : t_state;
signal crs_dv : std_logic;
signal rxd : std_logic_vector(1 downto 0);
signal rx_valid : std_logic;
signal rx_first : std_logic;
signal rx_end : std_logic;
signal rx_shift : std_logic_vector(7 downto 0) := (others => '0');
signal bad_carrier : std_logic;
signal rx_crc_sync : std_logic;
signal rx_crc_dav : std_logic;
signal rx_crc_data : std_logic_vector(3 downto 0) := (others => '0');
signal rx_crc : std_logic_vector(31 downto 0);
signal crc_ok : std_logic;
signal tx_count : natural range 0 to 63;
signal tx_crc_dav : std_logic;
signal tx_crc_sync : std_logic;
signal tx_crc_data : std_logic_vector(1 downto 0);
signal tx_crc : std_logic_vector(31 downto 0);
begin
p_receive: process(clock)
begin
if rising_edge(clock) then
-- synchronize
crs_dv <= rmii_crs_dv;
rxd <= rmii_rxd;
bad_carrier <= '0';
rx_valid <= '0';
rx_end <= '0';
rx_crc_dav <= '0';
eth_rx_valid <= '0';
if rx_valid = '1' or rx_end = '1' then
eth_rx_eof <= rx_end;
eth_rx_sof <= rx_first;
if rx_end = '1' then
eth_rx_data <= (others => crc_ok);
else
eth_rx_data <= rx_shift;
end if;
eth_rx_valid <= '1';
rx_first <= '0';
end if;
case rx_state is
when idle =>
if crs_dv = '1' then
if rxd = "01" then
rx_state <= preamble;
elsif rxd = "10" then
bad_carrier <= '1';
end if;
end if;
when preamble =>
rx_first <= '1';
if crs_dv = '0' then
rx_state <= idle;
else -- dv = 1
if rxd = "11" then
rx_state <= data0;
elsif rxd = "01" then
rx_state <= preamble;
else
bad_carrier <= '1';
rx_state <= idle;
end if;
end if;
when data0 => -- crs_dv = CRS
rx_shift(1 downto 0) <= rxd;
rx_state <= data1;
when data1 => -- crs_dv = DV
rx_shift(3 downto 2) <= rxd;
rx_state <= data2;
if crs_dv = '0' then
rx_end <= '1';
rx_state <= idle;
else
rx_crc_dav <= '1';
rx_crc_data <= rxd & rx_shift(1 downto 0);
end if;
when data2 => -- crs_dv = CRS
rx_shift(5 downto 4) <= rxd;
rx_state <= data3;
when data3 => -- crs_dv = DV
rx_shift(7 downto 6) <= rxd;
rx_crc_dav <= '1';
rx_crc_data <= rxd & rx_shift(5 downto 4);
rx_state <= data0;
rx_valid <= '1';
when others =>
null;
end case;
if reset='1' then
eth_rx_sof <= '0';
eth_rx_eof <= '0';
eth_rx_data <= (others => '0');
rx_first <= '0';
rx_state <= idle;
end if;
end if;
end process;
rx_crc_sync <= '1' when rx_state = preamble else '0';
i_receive_crc: entity work.crc32
generic map (
g_data_width => 4
)
port map(
clock => clock,
clock_en => '1',
sync => rx_crc_sync,
data => rx_crc_data,
data_valid => rx_crc_dav,
crc => rx_crc
);
crc_ok <= '1' when (rx_crc = X"2144DF1C") else '0';
p_transmit: process(clock)
begin
if rising_edge(clock) then
case tx_state is
when idle =>
rmii_tx_en <= '0';
rmii_txd <= "00";
if eth_tx_valid = '1' then
tx_state <= preamble;
tx_count <= 13;
end if;
when preamble =>
rmii_tx_en <= '1';
if tx_count = 0 then
rmii_txd <= "11";
tx_state <= data0;
else
rmii_txd <= "01";
tx_count <= tx_count - 1;
end if;
when data0 =>
if eth_tx_valid = '0' then
tx_state <= idle;
rmii_tx_en <= '0';
rmii_txd <= "00";
else
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(1 downto 0);
tx_state <= data1;
end if;
when data1 =>
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(3 downto 2);
tx_state <= data2;
when data2 =>
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(5 downto 4);
tx_state <= data3;
when data3 =>
tx_count <= 15;
rmii_tx_en <= '1';
rmii_txd <= eth_tx_data(7 downto 6);
if eth_tx_eof = '1' then
tx_state <= crc;
else
tx_state <= data0;
end if;
when crc =>
rmii_tx_en <= '1';
rmii_txd <= tx_crc(31 - tx_count*2 downto 30 - tx_count*2);
if tx_count = 0 then
tx_count <= 63;
tx_state <= gap;
else
tx_count <= tx_count - 1;
end if;
when gap =>
rmii_tx_en <= '0';
rmii_txd <= "00";
if tx_count = 0 then
tx_state <= idle;
else
tx_count <= tx_count - 1;
end if;
when others =>
null;
end case;
if reset='1' then
rmii_tx_en <= '0';
rmii_txd <= "00";
tx_state <= idle;
end if;
end if;
end process;
eth_tx_ready <= '1' when tx_state = data3 else '0';
tx_crc_sync <= '1' when tx_state = preamble else '0';
with tx_state select tx_crc_data <=
eth_tx_data(1 downto 0) when data0,
eth_tx_data(3 downto 2) when data1,
eth_tx_data(5 downto 4) when data2,
eth_tx_data(7 downto 6) when data3,
"00" when others;
with tx_state select tx_crc_dav <=
'1' when data0 | data1 | data2 | data3,
'0' when others;
i_transmit_crc: entity work.crc32
generic map (
g_data_width => 2
)
port map(
clock => clock,
clock_en => '1',
sync => tx_crc_sync,
data => tx_crc_data,
data_valid => tx_crc_dav,
crc => tx_crc
);
end architecture;
| gpl-3.0 | 5f80a89c60789a73afbfa8bf8fbfa21a | 0.394866 | 4.159041 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/async_fifo/vhdl_source/async_fifo_ft.vhd | 1 | 12,675 | -------------------------------------------------------------------------------
-- Title : asynchronous fall-through fifo
-- Author : Gideon Zweijtzer ([email protected])
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer of data between 2 clock domains
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gray_code_pkg.all;
entity async_fifo_ft is
generic(
g_fast : boolean := true;
g_data_width : integer := 36;
g_depth_bits : integer := 9 -- depth = 2^depth_bits (9 == 512 words)
);
port (
-- write port signals (synchronized to write clock)
wr_clock : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_din : in std_logic_vector(g_data_width-1 downto 0);
wr_full : out std_logic;
-- read port signals (synchronized to read clock)
rd_clock : in std_logic;
rd_reset : in std_logic;
rd_next : in std_logic;
rd_dout : out std_logic_vector(g_data_width-1 downto 0);
rd_valid : out std_logic );
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of async_fifo_ft : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of async_fifo_ft : entity is true;
---------------------------------------------------------------------------
end entity;
architecture rtl of async_fifo_ft is
function iif(condition : boolean; if_true : std_logic; if_false : std_logic) return std_logic is
begin
if condition then
return if_true;
else
return if_false;
end if;
end function;
constant c_edge : std_logic := iif(g_fast, '0', '1');
---------------------------------------------------------------------------
-- constants
---------------------------------------------------------------------------
constant c_depth : natural := 2 ** g_depth_bits;
---------------------------------------------------------------------------
-- storage memory for the data
---------------------------------------------------------------------------
type t_mem is array (0 to c_depth-1) of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem;
-- ---------------------------------------------------------------------------
-- -- synthesis attributes to for ram style
-- ---------------------------------------------------------------------------
-- -- Xilinx and Altera attributes
-- attribute ram_style : string;
-- attribute ramstyle : string;
-- attribute ram_style of mem : signal is g_storage;
-- attribute ramstyle of mem : signal is g_storage;
---------------------------------------------------------------------------
-- All signals (internal and external) are prefixed with rd or wr.
-- This indicates the clock-domain in which they are generated and used.
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
signal aclr : std_logic;
signal aclr_wr : std_logic_vector(2 downto 0);
signal aclr_rd : std_logic_vector(2 downto 0);
signal rd_reset_i : std_logic;
signal wr_reset_i : std_logic;
---------------------------------------------------------------------------
-- Read and write pointers, both in both domains.
---------------------------------------------------------------------------
signal wr_head : unsigned(g_depth_bits-1 downto 0) := (others => '0');
signal wr_head_next : unsigned(g_depth_bits-1 downto 0) := (others => '0');
signal wr_tail : unsigned(g_depth_bits-1 downto 0) := (others => '0');
signal rd_tail : unsigned(g_depth_bits-1 downto 0) := (others => '0');
signal rd_tail_next : unsigned(g_depth_bits-1 downto 0) := (others => '0');
signal rd_head : unsigned(g_depth_bits-1 downto 0) := (others => '0');
---------------------------------------------------------------------------
-- temporaries
---------------------------------------------------------------------------
signal wr_head_gray_tig_src : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal rd_head_gray_tig_dst : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal rd_head_gray : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal rd_tail_gray_tig_src : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_tail_gray_tig_dst : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_tail_gray : t_gray(g_depth_bits-1 downto 0) := (others => '0');
---------------------------------------------------------------------------
-- internal flags
---------------------------------------------------------------------------
signal rd_empty_i : std_logic;
signal wr_full_i : std_logic;
signal rd_en_filt : std_logic;
signal wr_en_filt : std_logic;
begin
---------------------------------------------------------------------------
-- reset generation
---------------------------------------------------------------------------
aclr <= wr_reset or rd_reset;
process(wr_clock, aclr)
begin
if aclr = '1' then
aclr_wr <= (others => '0');
elsif rising_edge(wr_clock) then
aclr_wr <= '1' & aclr_wr(2 downto 1);
end if;
end process;
wr_reset_i <= not aclr_wr(0);
process(rd_clock, aclr)
begin
if aclr = '1' then
aclr_rd <= (others => '0');
elsif rising_edge(rd_clock) then
aclr_rd <= '1' & aclr_rd(2 downto 1);
end if;
end process;
rd_reset_i <= not aclr_rd(0);
---------------------------------------------------------------------------
-- filtered read and write enable
---------------------------------------------------------------------------
rd_en_filt <= rd_next and not rd_empty_i;
wr_en_filt <= wr_en and not wr_full_i;
---------------------------------------------------------------------------
-- write data process
---------------------------------------------------------------------------
process(wr_en_filt, wr_head)
begin
wr_head_next <= wr_head;
if wr_en_filt = '1' then
wr_head_next <= wr_head + 1;
end if;
end process;
p_write : process(wr_clock)
begin
if rising_edge(wr_clock) then
if wr_en_filt = '1' then
mem(to_integer(wr_head)) <= wr_din;
end if;
if wr_reset_i = '1' then
wr_head <= (others => '0');
else
wr_head <= wr_head_next;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- read data process
---------------------------------------------------------------------------
process(rd_en_filt, rd_tail)
begin
rd_tail_next <= rd_tail;
if rd_en_filt = '1' then
rd_tail_next <= rd_tail + 1;
end if;
end process;
p_read : process(rd_clock)
begin
if rising_edge(rd_clock) then
rd_dout <= mem(to_integer(unsigned(rd_tail_next)));
if rd_reset_i = '1' then
rd_tail <= (others => '0');
else
rd_tail <= rd_tail_next;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- synchronize pointers to the other side
---------------------------------------------------------------------------
p_wr_sync: process(wr_clock)
begin
if rising_edge(wr_clock) then
-- second flop. We are now stable
wr_tail_gray <= wr_tail_gray_tig_dst;
-- conversion to binary may infer a longer xor chain, so we use a whole clock cycle here.
wr_tail <= to_unsigned(wr_tail_gray);
end if;
if wr_clock'event and wr_clock = c_edge then
-- conversion from binary to gray is very fast (one xor), so we will win some time
-- by using the falling edge (if c_edge = '0')
wr_head_gray_tig_src <= to_gray(wr_head);
-- two synchronization flipflops after one another is good for metastability
-- but bad for latency, so we use a falling edge flop for the first stage (if c_edge = '0')
wr_tail_gray_tig_dst <= rd_tail_gray_tig_src;
end if;
end process;
p_rd_sync: process(rd_clock)
begin
if rising_edge(rd_clock) then
-- second flop. We are now stable
rd_head_gray <= rd_head_gray_tig_dst;
-- conversion to binary may infer a longer xor chain, so we use a whole clock cycle here.
rd_head <= to_unsigned(rd_head_gray);
end if;
if rd_clock'event and rd_clock = c_edge then
-- two synchronization flipflops after one another is good for metastability
-- but bad for latency, so we use a falling edge flop for the first stage (if c_edge = '0')
rd_head_gray_tig_dst <= wr_head_gray_tig_src;
-- conversion from binary to gray is very fast (one xor), so we will win some time
-- by using the falling edge (if c_edge = '0')
rd_tail_gray_tig_src <= to_gray(rd_tail);
end if;
end process;
---------------------------------------------------------------------------
-- read empty generation
---------------------------------------------------------------------------
p_proc_read_count : process (rd_clock)
variable v_next_count : unsigned(rd_head'range);
begin
if rising_edge(rd_clock) then
v_next_count := rd_head - rd_tail_next;
if v_next_count = 0 then
rd_empty_i <= '1';
else
rd_empty_i <= '0';
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if rd_reset_i = '1' then
rd_empty_i <= '1';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write full generation
---------------------------------------------------------------------------
p_proc_write_count : process (wr_clock, wr_reset_i)
variable v_next_count : unsigned(wr_tail'range);
begin
if rising_edge(wr_clock) then
v_next_count := wr_head_next - wr_tail;
if signed(v_next_count) = -1 then
wr_full_i <= '1';
else
wr_full_i <= '0';
end if;
end if;
-------------------------------------------------------------------
-- asynchronous reset
-------------------------------------------------------------------
if wr_reset_i = '1' then
wr_full_i <= '1';
end if;
end process;
---------------------------------------------------------------------------
-- fifo status output signals
---------------------------------------------------------------------------
rd_valid <= not rd_empty_i;
wr_full <= wr_full_i;
end rtl;
| gpl-3.0 | 33cd67a978074a2828e7590c9a6ed369 | 0.385404 | 4.88816 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/nios.vhd | 1 | 82,379 | -- nios.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios is
port (
clk50_clk : in std_logic := '0'; -- clk50.clk
io_ack : in std_logic := '0'; -- io.ack
io_rdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .rdata
io_read : out std_logic; -- .read
io_wdata : out std_logic_vector(7 downto 0); -- .wdata
io_write : out std_logic; -- .write
io_address : out std_logic_vector(19 downto 0); -- .address
io_irq : in std_logic := '0'; -- .irq
mem32_address : in std_logic_vector(25 downto 0) := (others => '0'); -- mem32.address
mem32_direction : in std_logic := '0'; -- .direction
mem32_byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- .byte_en
mem32_wdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .wdata
mem32_request : in std_logic := '0'; -- .request
mem32_tag : in std_logic_vector(7 downto 0) := (others => '0'); -- .tag
mem32_dack_tag : out std_logic_vector(7 downto 0); -- .dack_tag
mem32_rdata : out std_logic_vector(31 downto 0); -- .rdata
mem32_rack : out std_logic; -- .rack
mem32_rack_tag : out std_logic_vector(7 downto 0); -- .rack_tag
memory_mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
memory_mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
memory_mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck
memory_mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
memory_mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
memory_mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
memory_mem_dm : out std_logic_vector(0 downto 0); -- .mem_dm
memory_mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
memory_mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
memory_mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dq
memory_mem_dqs : inout std_logic_vector(0 downto 0) := (others => '0'); -- .mem_dqs
memory_mem_dqs_n : inout std_logic_vector(0 downto 0) := (others => '0'); -- .mem_dqs_n
memory_mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
oct_rzqin : in std_logic := '0'; -- oct.rzqin
pio_in_port : in std_logic_vector(31 downto 0) := (others => '0'); -- pio.in_port
pio_out_port : out std_logic_vector(31 downto 0); -- .out_port
reset_reset_n : in std_logic := '0'; -- reset.reset_n
status_local_init_done : out std_logic; -- status.local_init_done
status_local_cal_success : out std_logic; -- .local_cal_success
status_local_cal_fail : out std_logic; -- .local_cal_fail
sys_clock_clk : out std_logic; -- sys_clock.clk
sys_reset_reset_n : out std_logic -- sys_reset.reset_n
);
end entity nios;
architecture rtl of nios is
component avalon_to_io_bridge is
port (
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
avs_ready : out std_logic; -- waitrequest_n
avs_readdata : out std_logic_vector(7 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
clock : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
avs_irq : out std_logic -- irq
);
end component avalon_to_io_bridge;
component mem32_to_avalon_bridge is
port (
reset : in std_logic := 'X'; -- reset
clock : in std_logic := 'X'; -- clk
memreq_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
memreq_read_writen : in std_logic := 'X'; -- direction
memreq_byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byte_en
memreq_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
memreq_request : in std_logic := 'X'; -- request
memreq_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- tag
memresp_dack_tag : out std_logic_vector(7 downto 0); -- dack_tag
memresp_data : out std_logic_vector(31 downto 0); -- rdata
memresp_rack : out std_logic; -- rack
memresp_rack_tag : out std_logic_vector(7 downto 0); -- rack_tag
avm_read : out std_logic; -- read
avm_write : out std_logic; -- write
avm_address : out std_logic_vector(25 downto 0); -- address
avm_writedata : out std_logic_vector(31 downto 0); -- writedata
avm_byte_enable : out std_logic_vector(3 downto 0); -- byteenable
avm_ready : in std_logic := 'X'; -- waitrequest_n
avm_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
avm_readdatavalid : in std_logic := 'X' -- readdatavalid
);
end component mem32_to_avalon_bridge;
component nios_mem_if_ddr2_emif_0 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(13 downto 0); -- mem_a
mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(0 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(31 downto 0); -- readdata
avl_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X' -- rzqin
);
end component nios_mem_if_ddr2_emif_0;
component nios_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(28 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(28 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component nios_nios2_gen2_0;
component nios_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
out_port : out std_logic_vector(31 downto 0); -- export
irq : out std_logic -- irq
);
end component nios_pio_0;
component nios_mm_interconnect_0 is
port (
mem_if_ddr2_emif_0_afi_clk_clk : in std_logic := 'X'; -- clk
mem32_to_avalon_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
mem_if_ddr2_emif_0_soft_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
mem32_to_avalon_0_avalon_master_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
mem32_to_avalon_0_avalon_master_waitrequest : out std_logic; -- waitrequest
mem32_to_avalon_0_avalon_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
mem32_to_avalon_0_avalon_master_read : in std_logic := 'X'; -- read
mem32_to_avalon_0_avalon_master_readdata : out std_logic_vector(31 downto 0); -- readdata
mem32_to_avalon_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid
mem32_to_avalon_0_avalon_master_write : in std_logic := 'X'; -- write
mem32_to_avalon_0_avalon_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_address : in std_logic_vector(28 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(28 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
io_bridge_0_avalon_slave_0_address : out std_logic_vector(19 downto 0); -- address
io_bridge_0_avalon_slave_0_write : out std_logic; -- write
io_bridge_0_avalon_slave_0_read : out std_logic; -- read
io_bridge_0_avalon_slave_0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
io_bridge_0_avalon_slave_0_writedata : out std_logic_vector(7 downto 0); -- writedata
io_bridge_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
io_bridge_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
mem_if_ddr2_emif_0_avl_address : out std_logic_vector(23 downto 0); -- address
mem_if_ddr2_emif_0_avl_write : out std_logic; -- write
mem_if_ddr2_emif_0_avl_read : out std_logic; -- read
mem_if_ddr2_emif_0_avl_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
mem_if_ddr2_emif_0_avl_writedata : out std_logic_vector(31 downto 0); -- writedata
mem_if_ddr2_emif_0_avl_beginbursttransfer : out std_logic; -- beginbursttransfer
mem_if_ddr2_emif_0_avl_burstcount : out std_logic_vector(2 downto 0); -- burstcount
mem_if_ddr2_emif_0_avl_byteenable : out std_logic_vector(3 downto 0); -- byteenable
mem_if_ddr2_emif_0_avl_readdatavalid : in std_logic := 'X'; -- readdatavalid
mem_if_ddr2_emif_0_avl_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
pio_0_s1_address : out std_logic_vector(2 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic -- chipselect
);
end component nios_mm_interconnect_0;
component nios_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component nios_irq_mapper;
component nios_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component nios_rst_controller;
component nios_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component nios_rst_controller_001;
component nios_rst_controller_002 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component nios_rst_controller_002;
signal mem_if_ddr2_emif_0_afi_clk_clk : std_logic; -- mem_if_ddr2_emif_0:afi_clk -> [sys_clock_clk, io_bridge_0:clock, irq_mapper:clk, mem32_to_avalon_0:clock, mm_interconnect_0:mem_if_ddr2_emif_0_afi_clk_clk, nios2_gen2_0:clk, pio_0:clk, rst_controller:clk, rst_controller_001:clk, rst_controller_002:clk]
signal mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:mem32_to_avalon_0_avalon_master_waitrequest -> mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest:in
signal mem32_to_avalon_0_avalon_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:mem32_to_avalon_0_avalon_master_readdata -> mem32_to_avalon_0:avm_readdata
signal mem32_to_avalon_0_avalon_master_read : std_logic; -- mem32_to_avalon_0:avm_read -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_read
signal mem32_to_avalon_0_avalon_master_address : std_logic_vector(25 downto 0); -- mem32_to_avalon_0:avm_address -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_address
signal mem32_to_avalon_0_avalon_master_byteenable : std_logic_vector(3 downto 0); -- mem32_to_avalon_0:avm_byte_enable -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_byteenable
signal mem32_to_avalon_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:mem32_to_avalon_0_avalon_master_readdatavalid -> mem32_to_avalon_0:avm_readdatavalid
signal mem32_to_avalon_0_avalon_master_write : std_logic; -- mem32_to_avalon_0:avm_write -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_write
signal mem32_to_avalon_0_avalon_master_writedata : std_logic_vector(31 downto 0); -- mem32_to_avalon_0:avm_writedata -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_writedata
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(28 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(28 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_mem_if_ddr2_emif_0_avl_beginbursttransfer : std_logic; -- mm_interconnect_0:mem_if_ddr2_emif_0_avl_beginbursttransfer -> mem_if_ddr2_emif_0:avl_burstbegin
signal mm_interconnect_0_mem_if_ddr2_emif_0_avl_readdata : std_logic_vector(31 downto 0); -- mem_if_ddr2_emif_0:avl_rdata -> mm_interconnect_0:mem_if_ddr2_emif_0_avl_readdata
signal mem_if_ddr2_emif_0_avl_waitrequest : std_logic; -- mem_if_ddr2_emif_0:avl_ready -> mem_if_ddr2_emif_0_avl_waitrequest:in
signal mm_interconnect_0_mem_if_ddr2_emif_0_avl_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:mem_if_ddr2_emif_0_avl_address -> mem_if_ddr2_emif_0:avl_addr
signal mm_interconnect_0_mem_if_ddr2_emif_0_avl_read : std_logic; -- mm_interconnect_0:mem_if_ddr2_emif_0_avl_read -> mem_if_ddr2_emif_0:avl_read_req
signal mm_interconnect_0_mem_if_ddr2_emif_0_avl_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:mem_if_ddr2_emif_0_avl_byteenable -> mem_if_ddr2_emif_0:avl_be
signal mm_interconnect_0_mem_if_ddr2_emif_0_avl_readdatavalid : std_logic; -- mem_if_ddr2_emif_0:avl_rdata_valid -> mm_interconnect_0:mem_if_ddr2_emif_0_avl_readdatavalid
signal mm_interconnect_0_mem_if_ddr2_emif_0_avl_write : std_logic; -- mm_interconnect_0:mem_if_ddr2_emif_0_avl_write -> mem_if_ddr2_emif_0:avl_write_req
signal mm_interconnect_0_mem_if_ddr2_emif_0_avl_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:mem_if_ddr2_emif_0_avl_writedata -> mem_if_ddr2_emif_0:avl_wdata
signal mm_interconnect_0_mem_if_ddr2_emif_0_avl_burstcount : std_logic_vector(2 downto 0); -- mm_interconnect_0:mem_if_ddr2_emif_0_avl_burstcount -> mem_if_ddr2_emif_0:avl_size
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata : std_logic_vector(7 downto 0); -- io_bridge_0:avs_readdata -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdata
signal io_bridge_0_avalon_slave_0_waitrequest : std_logic; -- io_bridge_0:avs_ready -> io_bridge_0_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_address : std_logic_vector(19 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_address -> io_bridge_0:avs_address
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_read -> io_bridge_0:avs_read
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid : std_logic; -- io_bridge_0:avs_readdatavalid -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_write -> io_bridge_0:avs_write
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_writedata -> io_bridge_0:avs_writedata
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal irq_mapper_receiver0_irq : std_logic; -- io_bridge_0:avs_irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- pio_0:irq -> irq_mapper:receiver1_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [io_bridge_0:reset, mem32_to_avalon_0:reset, mm_interconnect_0:mem32_to_avalon_0_reset_reset_bridge_in_reset_reset, rst_controller_reset_out_reset:in]
signal mem_if_ddr2_emif_0_afi_reset_reset : std_logic; -- mem_if_ddr2_emif_0:afi_reset_n -> mem_if_ddr2_emif_0_afi_reset_reset:in
signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> rst_controller:reset_in1
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, rst_controller_001_reset_out_reset:in]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [nios2_gen2_0:reset_req, rst_translator:reset_req_in]
signal rst_controller_002_reset_out_reset : std_logic; -- rst_controller_002:reset_out -> [mm_interconnect_0:mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_0:mem_if_ddr2_emif_0_soft_reset_reset_bridge_in_reset_reset]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> rst_controller_002:reset_in0
signal mem32_to_avalon_0_avalon_master_inv : std_logic; -- mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest:inv -> mem32_to_avalon_0:avm_ready
signal mm_interconnect_0_mem_if_ddr2_emif_0_avl_inv : std_logic; -- mem_if_ddr2_emif_0_avl_waitrequest:inv -> mm_interconnect_0:mem_if_ddr2_emif_0_avl_waitrequest
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_inv : std_logic; -- io_bridge_0_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:io_bridge_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [sys_reset_reset_n, pio_0:reset_n]
signal mem_if_ddr2_emif_0_afi_reset_reset_ports_inv : std_logic; -- mem_if_ddr2_emif_0_afi_reset_reset:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> nios2_gen2_0:reset_n
begin
io_bridge_0 : component avalon_to_io_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
avs_ready => io_bridge_0_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => mem_if_ddr2_emif_0_afi_clk_clk, -- clock.clk
io_ack => io_ack, -- io.ack
io_rdata => io_rdata, -- .rdata
io_read => io_read, -- .read
io_wdata => io_wdata, -- .wdata
io_write => io_write, -- .write
io_address => io_address, -- .address
io_irq => io_irq, -- .irq
avs_irq => irq_mapper_receiver0_irq -- irq.irq
);
mem32_to_avalon_0 : component mem32_to_avalon_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
clock => mem_if_ddr2_emif_0_afi_clk_clk, -- clock.clk
memreq_address => mem32_address, -- mem32_slave.address
memreq_read_writen => mem32_direction, -- .direction
memreq_byte_en => mem32_byte_en, -- .byte_en
memreq_data => mem32_wdata, -- .wdata
memreq_request => mem32_request, -- .request
memreq_tag => mem32_tag, -- .tag
memresp_dack_tag => mem32_dack_tag, -- .dack_tag
memresp_data => mem32_rdata, -- .rdata
memresp_rack => mem32_rack, -- .rack
memresp_rack_tag => mem32_rack_tag, -- .rack_tag
avm_read => mem32_to_avalon_0_avalon_master_read, -- avalon_master.read
avm_write => mem32_to_avalon_0_avalon_master_write, -- .write
avm_address => mem32_to_avalon_0_avalon_master_address, -- .address
avm_writedata => mem32_to_avalon_0_avalon_master_writedata, -- .writedata
avm_byte_enable => mem32_to_avalon_0_avalon_master_byteenable, -- .byteenable
avm_ready => mem32_to_avalon_0_avalon_master_inv, -- .waitrequest_n
avm_readdata => mem32_to_avalon_0_avalon_master_readdata, -- .readdata
avm_readdatavalid => mem32_to_avalon_0_avalon_master_readdatavalid -- .readdatavalid
);
mem_if_ddr2_emif_0 : component nios_mem_if_ddr2_emif_0
port map (
pll_ref_clk => clk50_clk, -- pll_ref_clk.clk
global_reset_n => reset_reset_n, -- global_reset.reset_n
soft_reset_n => reset_reset_n, -- soft_reset.reset_n
afi_clk => mem_if_ddr2_emif_0_afi_clk_clk, -- afi_clk.clk
afi_half_clk => open, -- afi_half_clk.clk
afi_reset_n => mem_if_ddr2_emif_0_afi_reset_reset, -- afi_reset.reset_n
afi_reset_export_n => open, -- afi_reset_export.reset_n
mem_a => memory_mem_a, -- memory.mem_a
mem_ba => memory_mem_ba, -- .mem_ba
mem_ck => memory_mem_ck, -- .mem_ck
mem_ck_n => memory_mem_ck_n, -- .mem_ck_n
mem_cke => memory_mem_cke, -- .mem_cke
mem_cs_n => memory_mem_cs_n, -- .mem_cs_n
mem_dm => memory_mem_dm, -- .mem_dm
mem_ras_n => memory_mem_ras_n, -- .mem_ras_n
mem_cas_n => memory_mem_cas_n, -- .mem_cas_n
mem_we_n => memory_mem_we_n, -- .mem_we_n
mem_dq => memory_mem_dq, -- .mem_dq
mem_dqs => memory_mem_dqs, -- .mem_dqs
mem_dqs_n => memory_mem_dqs_n, -- .mem_dqs_n
mem_odt => memory_mem_odt, -- .mem_odt
avl_ready => mem_if_ddr2_emif_0_avl_waitrequest, -- avl.waitrequest_n
avl_burstbegin => mm_interconnect_0_mem_if_ddr2_emif_0_avl_beginbursttransfer, -- .beginbursttransfer
avl_addr => mm_interconnect_0_mem_if_ddr2_emif_0_avl_address, -- .address
avl_rdata_valid => mm_interconnect_0_mem_if_ddr2_emif_0_avl_readdatavalid, -- .readdatavalid
avl_rdata => mm_interconnect_0_mem_if_ddr2_emif_0_avl_readdata, -- .readdata
avl_wdata => mm_interconnect_0_mem_if_ddr2_emif_0_avl_writedata, -- .writedata
avl_be => mm_interconnect_0_mem_if_ddr2_emif_0_avl_byteenable, -- .byteenable
avl_read_req => mm_interconnect_0_mem_if_ddr2_emif_0_avl_read, -- .read
avl_write_req => mm_interconnect_0_mem_if_ddr2_emif_0_avl_write, -- .write
avl_size => mm_interconnect_0_mem_if_ddr2_emif_0_avl_burstcount, -- .burstcount
local_init_done => status_local_init_done, -- status.local_init_done
local_cal_success => status_local_cal_success, -- .local_cal_success
local_cal_fail => status_local_cal_fail, -- .local_cal_fail
oct_rzqin => oct_rzqin -- oct.rzqin
);
nios2_gen2_0 : component nios_nios2_gen2_0
port map (
clk => mem_if_ddr2_emif_0_afi_clk_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
pio_0 : component nios_pio_0
port map (
clk => mem_if_ddr2_emif_0_afi_clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
in_port => pio_in_port, -- external_connection.export
out_port => pio_out_port, -- .export
irq => irq_mapper_receiver1_irq -- irq.irq
);
mm_interconnect_0 : component nios_mm_interconnect_0
port map (
mem_if_ddr2_emif_0_afi_clk_clk => mem_if_ddr2_emif_0_afi_clk_clk, -- mem_if_ddr2_emif_0_afi_clk.clk
mem32_to_avalon_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- mem32_to_avalon_0_reset_reset_bridge_in_reset.reset
mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset => rst_controller_002_reset_out_reset, -- mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset.reset
mem_if_ddr2_emif_0_soft_reset_reset_bridge_in_reset_reset => rst_controller_002_reset_out_reset, -- mem_if_ddr2_emif_0_soft_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
mem32_to_avalon_0_avalon_master_address => mem32_to_avalon_0_avalon_master_address, -- mem32_to_avalon_0_avalon_master.address
mem32_to_avalon_0_avalon_master_waitrequest => mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest, -- .waitrequest
mem32_to_avalon_0_avalon_master_byteenable => mem32_to_avalon_0_avalon_master_byteenable, -- .byteenable
mem32_to_avalon_0_avalon_master_read => mem32_to_avalon_0_avalon_master_read, -- .read
mem32_to_avalon_0_avalon_master_readdata => mem32_to_avalon_0_avalon_master_readdata, -- .readdata
mem32_to_avalon_0_avalon_master_readdatavalid => mem32_to_avalon_0_avalon_master_readdatavalid, -- .readdatavalid
mem32_to_avalon_0_avalon_master_write => mem32_to_avalon_0_avalon_master_write, -- .write
mem32_to_avalon_0_avalon_master_writedata => mem32_to_avalon_0_avalon_master_writedata, -- .writedata
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
io_bridge_0_avalon_slave_0_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- io_bridge_0_avalon_slave_0.address
io_bridge_0_avalon_slave_0_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
io_bridge_0_avalon_slave_0_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- .read
io_bridge_0_avalon_slave_0_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
io_bridge_0_avalon_slave_0_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
io_bridge_0_avalon_slave_0_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
io_bridge_0_avalon_slave_0_waitrequest => mm_interconnect_0_io_bridge_0_avalon_slave_0_inv, -- .waitrequest
mem_if_ddr2_emif_0_avl_address => mm_interconnect_0_mem_if_ddr2_emif_0_avl_address, -- mem_if_ddr2_emif_0_avl.address
mem_if_ddr2_emif_0_avl_write => mm_interconnect_0_mem_if_ddr2_emif_0_avl_write, -- .write
mem_if_ddr2_emif_0_avl_read => mm_interconnect_0_mem_if_ddr2_emif_0_avl_read, -- .read
mem_if_ddr2_emif_0_avl_readdata => mm_interconnect_0_mem_if_ddr2_emif_0_avl_readdata, -- .readdata
mem_if_ddr2_emif_0_avl_writedata => mm_interconnect_0_mem_if_ddr2_emif_0_avl_writedata, -- .writedata
mem_if_ddr2_emif_0_avl_beginbursttransfer => mm_interconnect_0_mem_if_ddr2_emif_0_avl_beginbursttransfer, -- .beginbursttransfer
mem_if_ddr2_emif_0_avl_burstcount => mm_interconnect_0_mem_if_ddr2_emif_0_avl_burstcount, -- .burstcount
mem_if_ddr2_emif_0_avl_byteenable => mm_interconnect_0_mem_if_ddr2_emif_0_avl_byteenable, -- .byteenable
mem_if_ddr2_emif_0_avl_readdatavalid => mm_interconnect_0_mem_if_ddr2_emif_0_avl_readdatavalid, -- .readdatavalid
mem_if_ddr2_emif_0_avl_waitrequest => mm_interconnect_0_mem_if_ddr2_emif_0_avl_inv, -- .waitrequest
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect -- .chipselect
);
irq_mapper : component nios_irq_mapper
port map (
clk => mem_if_ddr2_emif_0_afi_clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component nios_rst_controller
generic map (
NUM_RESET_INPUTS => 2,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => mem_if_ddr2_emif_0_afi_reset_reset_ports_inv, -- reset_in0.reset
reset_in1 => nios2_gen2_0_debug_reset_request_reset, -- reset_in1.reset
clk => mem_if_ddr2_emif_0_afi_clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component nios_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => mem_if_ddr2_emif_0_afi_reset_reset_ports_inv, -- reset_in0.reset
clk => mem_if_ddr2_emif_0_afi_clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component nios_rst_controller_002
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => mem_if_ddr2_emif_0_afi_clk_clk, -- clk.clk
reset_out => rst_controller_002_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mem32_to_avalon_0_avalon_master_inv <= not mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest;
mm_interconnect_0_mem_if_ddr2_emif_0_avl_inv <= not mem_if_ddr2_emif_0_avl_waitrequest;
mm_interconnect_0_io_bridge_0_avalon_slave_0_inv <= not io_bridge_0_avalon_slave_0_waitrequest;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
mem_if_ddr2_emif_0_afi_reset_reset_ports_inv <= not mem_if_ddr2_emif_0_afi_reset_reset;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
sys_clock_clk <= mem_if_ddr2_emif_0_afi_clk_clk;
sys_reset_reset_n <= rst_controller_reset_out_reset_ports_inv;
end architecture rtl; -- of nios
| gpl-3.0 | 777aa27deb2b6bf39908411882f6d91f | 0.448003 | 3.723345 | false | false | false | false |
trondd/mkjpeg | design/huffman/AC_CR_ROM.vhd | 2 | 34,115 | -------------------------------------------------------------------------------
-- File Name : AC_CR_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_CR_ROM
--
-- Content : AC_CR_ROM Chrominance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090329: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity AC_CR_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
runlength : in std_logic_vector(3 downto 0);
VLI_size : in std_logic_vector(3 downto 0);
VLC_AC_size : out unsigned(4 downto 0);
VLC_AC : out unsigned(15 downto 0)
);
end entity AC_CR_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of AC_CR_ROM is
signal rom_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
rom_addr <= runlength & VLI_size;
-------------------------------------------------------------------
-- AC-ROM
-------------------------------------------------------------------
p_AC_CR_ROM : process(CLK, RST)
begin
if RST = '1' then
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
elsif CLK'event and CLK = '1' then
case runlength is
when X"0" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("00", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("01", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(3, VLC_AC_size'length);
VLC_AC <= resize("100", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1010", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111000", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110110", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110100", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"1" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11110110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110101", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110110", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110101", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001000", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001001", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001010", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001011", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"2" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"3" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111000", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"4" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"5" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"6" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"7" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"8" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111000", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111001", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111011", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111100", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111101", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111110", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111111", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"9" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110111", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000001", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000010", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000011", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"A" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001010", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001011", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001100", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001101", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001110", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001111", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010000", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010001", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"B" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010010", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010011", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010100", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010101", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010110", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010111", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011000", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011001", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011010", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"C" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011011", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011100", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011101", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011110", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011111", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100000", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100001", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100010", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100011", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"D" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100100", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100101", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100111", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101001", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101010", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101011", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101100", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"E" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(14, VLC_AC_size'length);
VLC_AC <= resize("11111111100000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101101", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"F" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111010", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when others =>
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | e58d41b37691e6650222fd217360d96e | 0.435556 | 3.923519 | false | false | false | false |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/voltage_source.vhdl | 15 | 415 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY VOLTAGE_SOURCE IS
GENERIC ( amplitude : REAL := 2.0;
offset : REAL := 1.2;
width : REAL := 0.002;
period : REAL := 0.005;
k : REAL := 100.0 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY VOLTAGE_SOURCE;
| gpl-2.0 | 7d5ec86723011059a70e93c20a2dbfab | 0.645783 | 2.881944 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/watchdog/cb20/synthesis/cb20_gpio_block_0.vhd | 1 | 3,970 | -- cb20_gpio_block_0.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_0 is
generic (
number_of_gpios : integer := 9;
unique_id : std_logic_vector(31 downto 0) := "00010010011100000101000000000001"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- avalon_slave_0.readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => '0'); -- .address
isl_avs_read : in std_logic := '0'; -- .read
isl_avs_write : in std_logic := '0'; -- .write
osl_avs_waitrequest : out std_logic; -- .waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
isl_clk : in std_logic := '0'; -- clock_sink.clk
isl_reset_n : in std_logic := '0'; -- reset_sink.reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => '0') -- conduit_end.export
);
end entity cb20_gpio_block_0;
architecture rtl of cb20_gpio_block_0 is
component avalon_gpio_interface is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => 'X') -- export
);
end component avalon_gpio_interface;
begin
number_of_gpios_check : if number_of_gpios /= 9 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
unique_id_check : if unique_id /= "00010010011100000101000000000001" generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
gpio_block_0 : component avalon_gpio_interface
generic map (
number_of_gpios => 9,
unique_id => "00010010011100000101000000000001"
)
port map (
oslv_avs_read_data => oslv_avs_read_data, -- avalon_slave_0.readdata
islv_avs_address => islv_avs_address, -- .address
isl_avs_read => isl_avs_read, -- .read
isl_avs_write => isl_avs_write, -- .write
osl_avs_waitrequest => osl_avs_waitrequest, -- .waitrequest
islv_avs_write_data => islv_avs_write_data, -- .writedata
islv_avs_byteenable => islv_avs_byteenable, -- .byteenable
isl_clk => isl_clk, -- clock_sink.clk
isl_reset_n => isl_reset_n, -- reset_sink.reset_n
oslv_gpios => oslv_gpios -- conduit_end.export
);
end architecture rtl; -- of cb20_gpio_block_0
| apache-2.0 | fe380d373d9dda8a6efeede480dec1ca | 0.522166 | 3.538324 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_sim/tb_ulpi_rx.vhd | 2 | 3,144 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_rx is
end entity;
architecture tb of tb_ulpi_rx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal pid : std_logic_vector(3 downto 0);
signal valid_token : std_logic;
signal token : std_logic_vector(10 downto 0);
signal valid_packet : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_valid : std_logic;
signal data_start : std_logic;
signal error : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_rx: entity work.usb1_ulpi_rx
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => pid,
valid_token => valid_token,
token => token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => error );
process
procedure packet(pkt : t_std_logic_8_vector) is
begin
for i in pkt'range loop
wait until clock='1';
rx_data <= pkt(i);
rx_valid <= '1';
rx_store <= '1';
if i = pkt'right then
rx_last <= '1';
else
rx_last <= '0';
end if;
end loop;
wait until clock='1';
rx_valid <= '0';
rx_last <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
end procedure packet;
begin
wait until reset='0';
wait until clock='1';
packet((X"A5", X"63", X"A9"));
packet((X"4B", X"00", X"00")); -- data1, length=0, crc = 0000
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- good crc
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"03", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- bad crc
packet((0=>X"D2")); -- good handshake
packet((0=>X"C3")); -- bad handshake (wrong pid data)
packet((0=>X"A5")); -- bad handshake (wrong pid token)
wait;
end process;
end tb;
| gpl-3.0 | 6dfbb379a193d15a1a4b56ec45cc6007 | 0.436069 | 3.536558 | false | false | false | false |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/spice_cs_arc.vhdl | 15 | 244 | ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
| gpl-2.0 | 8adc759e6007697d2eeb4e56206ad8a0 | 0.663934 | 3.05 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/reu.vhd | 1 | 18,932 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reu_pkg.all;
use work.mem_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.slot_bus_pkg.all;
-- Standard: 433 LUT/148 FF
-- Extended: 564 LUT/195 FF
entity reu is
generic (
g_ram_tag : std_logic_vector(7 downto 0) := X"10";
g_extended : boolean := true;
g_ram_base : unsigned(27 downto 0) := X"1000000" ); -- second (=upper 16M)
port (
clock : in std_logic;
reset : in std_logic;
-- register interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
write_ff00 : in std_logic;
-- system interface
phi2_tick : in std_logic := '0';
reu_dma_n : out std_logic := '1';
size_ctrl : in std_logic_vector(2 downto 0) := "001";
enable : in std_logic;
inhibit : in std_logic; -- to pause a transfer, because Ultimate menu is active
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp );
end reu;
-- The REU is actually really simple.
-- There are 4 modes of operation, and 4 active states:
-- r = reu read, w = reu write, R = c64 read, W = c64 write
-- Copy from c64 to reu (00): Rw
-- Copy from reu to c64 (01): rW
-- Swap (10): rRwW (RrWw or rRWw or RrwW or rRwW)
-- Verify (11): rR (Rr or rR)
-- The smallest implementation is very likely when only one bit is needed to select between
-- transition options, and reducing the total number of transitions makes sense too.
architecture gideon of reu is
type t_state is (idle, do_read_c64, use_data, do_write_c64, do_read_reu, do_write_reu, reu_write_done, check_end, delay);
signal state : t_state;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
signal io_wdatau : unsigned(7 downto 0);
signal io_rdata : std_logic_vector(7 downto 0);
signal io_write : std_logic;
signal io_read : std_logic;
signal c64_base : unsigned(15 downto 0) := (others => '0');
signal reu_base : unsigned(23 downto 0) := (others => '0');
signal length_reg : unsigned(23 downto 0) := (others => '1');
signal c64_addr : unsigned(15 downto 0) := (others => '0');
signal reu_addr : unsigned(23 downto 0) := (others => '0');
signal count : unsigned(23 downto 0) := (others => '1');
signal c64_req : std_logic;
signal c64_rack : std_logic;
signal c64_dack : std_logic;
signal reu_req : std_logic;
signal reu_rack : std_logic;
signal reu_dack : std_logic;
signal glob_rwn : std_logic;
signal masked_reu_addr : unsigned(23 downto 0);
signal mask : unsigned(7 downto 0);
signal c64_read_reg : std_logic_vector(7 downto 0) := (others => '0');
signal reu_read_reg : std_logic_vector(7 downto 0) := (others => '0');
signal verify_error : std_logic;
signal trans_done : std_logic;
signal irq_pend : std_logic;
signal reserved : std_logic_vector(2 downto 0);
type t_control is record
irq_en : std_logic;
irq_done : std_logic;
irq_error : std_logic;
fix_reu : std_logic;
fix_c64 : std_logic;
end record;
type t_command is record
execute : std_logic;
autoload : std_logic;
ff00 : std_logic;
mode : std_logic_vector(1 downto 0);
end record;
constant c_control_def : t_control := (others => '0');
constant c_command_def : t_command := (
mode => "00",
execute => '0',
ff00 => '1',
autoload => '0' );
signal control : t_control;
signal command : t_command;
-- signals for extended mode
signal rate_div : unsigned(7 downto 0) := (others => '0');
signal start_delay : unsigned(7 downto 0) := (others => '0');
signal ext_count : unsigned(7 downto 0) := (others => '0');
begin
with size_ctrl select mask <=
"00000001" when "000",
"00000011" when "001",
"00000111" when "010",
"00001111" when "011",
"00011111" when "100",
"00111111" when "101",
"01111111" when "110",
"11111111" when others;
masked_reu_addr(23 downto 19) <= (reu_base(23 downto 19) and mask(7 downto 3)) when not g_extended else
(reu_addr(23 downto 19) and mask(7 downto 3));
masked_reu_addr(18 downto 16) <= (reu_addr(18 downto 16) and mask(2 downto 0));
masked_reu_addr(15 downto 0) <= reu_addr(15 downto 0);
reu_rack <= '1' when mem_resp.rack_tag = g_ram_tag else '0';
reu_dack <= '1' when mem_resp.dack_tag = g_ram_tag else '0';
io_wdatau <= unsigned(slot_req.data);
-- fill mem request structure
mem_req.tag <= g_ram_tag;
mem_req.request <= reu_req;
mem_req.address <= g_ram_base(25 downto 24) & masked_reu_addr;
mem_req.read_writen <= glob_rwn;
mem_req.data <= c64_read_reg;
mem_req.size <= "00"; -- 1 byte at a time
-- fill dma request structure
dma_req.request <= c64_req;
dma_req.address <= c64_addr;
dma_req.read_writen <= glob_rwn;
dma_req.data <= reu_read_reg;
c64_rack <= dma_resp.rack;
c64_dack <= dma_resp.dack;
p_main: process(clock)
procedure next_address is
begin
if control.fix_c64='0' then
c64_addr <= c64_addr + 1;
end if;
if control.fix_reu='0' then
reu_addr <= reu_addr + 1;
end if;
if (count(15 downto 0) = 1 and not g_extended) or
(count = 1 and g_extended) then
trans_done <= '1';
else
count <= count - 1;
end if;
end procedure;
procedure transfer_end is
begin
if command.autoload='1' then
c64_addr <= c64_base;
reu_addr <= reu_base(reu_addr'range);
if g_extended then
count <= length_reg;
else
count(15 downto 0) <= length_reg(15 downto 0);
end if;
end if;
command.ff00 <= '1'; -- reset to default state
state <= idle;
end procedure;
procedure dispatch is
begin
glob_rwn <= '1'; -- we're going to read.
case command.mode is
when c_mode_toreu => -- C64 to REU
c64_req <= '1';
state <= do_read_c64;
when others => -- in all other cases, read reu first
reu_req <= '1';
state <= do_read_reu;
end case;
end procedure;
variable r: unsigned(7 downto 0);
begin
if rising_edge(clock) then
r := "000" & slot_req.io_address(4 downto 0);
if io_write='1' then --$DF00-$DF1F, decoded below in a concurrent statement
case r is
when c_c64base_l => c64_base(7 downto 0) <= io_wdatau;
c64_addr <= c64_base(15 downto 8) & io_wdatau; -- half autoload bug
when c_c64base_h => c64_base(15 downto 8) <= io_wdatau;
c64_addr <= io_wdatau & c64_base(7 downto 0); -- half autoload bug
when c_reubase_l => reu_base(7 downto 0) <= io_wdatau;
reu_addr(15 downto 0) <= reu_base(15 downto 8) & io_wdatau; -- half autoload bug
when c_reubase_m => reu_base(15 downto 8) <= io_wdatau;
reu_addr(15 downto 0) <= io_wdatau & reu_base(7 downto 0); -- half autoload bug
when c_reubase_h => reu_base(23 downto 16) <= io_wdatau;
reu_addr(23 downto 16) <= io_wdatau;
when c_translen_l => length_reg(7 downto 0) <= io_wdatau;
count(15 downto 0) <= length_reg(15 downto 8) & io_wdatau; -- half autoload bug
when c_translen_h => length_reg(15 downto 8) <= io_wdatau;
count(15 downto 0) <= io_wdatau & length_reg(7 downto 0); -- half autoload bug
when c_irqmask =>
control.irq_en <= io_wdatau(7);
control.irq_done <= io_wdatau(6);
control.irq_error <= io_wdatau(5);
when c_control =>
control.fix_reu <= io_wdatau(6);
control.fix_c64 <= io_wdatau(7);
when c_command =>
command.execute <= io_wdatau(7);
reserved(2) <= io_wdatau(6);
command.autoload <= io_wdatau(5);
command.ff00 <= io_wdatau(4);
reserved(1) <= io_wdatau(3);
reserved(0) <= io_wdatau(2);
command.mode <= slot_req.data(1 downto 0);
when others =>
null;
end case;
end if;
-- extended registers
if io_write='1' and g_extended then --$DF00-$DF1F, decoded below in a concurrent statement
case r is
when c_start_delay =>
start_delay <= io_wdatau;
when c_rate_div =>
rate_div <= io_wdatau;
when c_translen_x =>
length_reg(23 downto 16) <= io_wdatau;
count(23 downto 16) <= io_wdatau;
when others =>
null;
end case;
end if;
-- clear on read flags
if io_read='1' then
if r = c_status then
verify_error <= '0';
trans_done <= '0';
end if;
end if;
case state is
when idle =>
reu_dma_n <= '1';
glob_rwn <= '1';
ext_count <= start_delay;
if command.execute='1' then
if (command.ff00='0' and write_ff00='1') or
(command.ff00='1') then
verify_error <= '0';
trans_done <= '0';
command.execute <= '0';
if g_extended then
state <= delay;
else
dispatch;
reu_dma_n <= '0';
end if;
end if;
end if;
when delay =>
if ext_count = 0 then
dispatch;
reu_dma_n <= '0';
elsif phi2_tick='1' then
ext_count <= ext_count - 1;
end if;
when do_read_reu =>
if reu_rack='1' then
reu_req <= '0';
end if;
if reu_dack='1' then
reu_read_reg <= mem_resp.data;
state <= use_data;
end if;
when use_data =>
if inhibit = '0' then
case command.mode is
when c_mode_swap | c_mode_verify =>
c64_req <= '1';
glob_rwn <= '1';
state <= do_read_c64;
when others =>
c64_req <= '1';
glob_rwn <= '0';
state <= do_write_c64;
end case;
end if;
when do_write_c64 =>
if c64_rack='1' then
c64_req <= '0';
next_address;
state <= check_end;
end if;
when do_read_c64 =>
if c64_rack='1' then
c64_req <= '0';
end if;
if c64_dack='1' then
c64_read_reg <= dma_resp.data;
case command.mode is
when c_mode_verify =>
if dma_resp.data /= reu_read_reg then
verify_error <= '1';
state <= idle;
else
next_address;
state <= check_end;
end if;
when others =>
reu_req <= '1';
glob_rwn <= '0';
state <= do_write_reu;
end case;
end if;
when do_write_reu =>
if reu_rack='1' then
reu_req <= '0';
state <= reu_write_done;
end if;
when reu_write_done =>
case command.mode is
when c_mode_swap =>
if inhibit = '0' then
c64_req <= '1';
glob_rwn <= '0';
state <= do_write_c64;
end if;
when others =>
next_address;
state <= check_end;
end case;
when check_end =>
ext_count <= rate_div;
if trans_done='1' then
transfer_end;
elsif g_extended then
state <= delay;
elsif inhibit = '0' then
dispatch;
end if;
when others =>
null;
end case;
if reset='1' then
reu_req <= '0';
c64_req <= '0';
glob_rwn <= '1';
control <= c_control_def;
command <= c_command_def;
state <= idle;
reserved <= (others => '0');
verify_error <= '0';
trans_done <= '0';
reu_dma_n <= '1';
c64_base <= (others => '0');
reu_base <= (others => '0');
length_reg <= X"00FFFF";
c64_addr <= (others => '0');
reu_addr <= (others => '0');
count <= (others => '1');
rate_div <= (others => '0');
start_delay <= (others => '0');
rate_div <= (others => '0');
ext_count <= (others => '0');
end if;
end if;
end process;
p_read: process(slot_req, control, command, count, c64_addr, reu_addr, verify_error, trans_done, irq_pend,
c64_base, reu_base, length_reg, reserved, mask, start_delay, rate_div)
variable r: unsigned(7 downto 0);
begin
io_rdata <= X"FF";
r := "000" & slot_req.bus_address(4 downto 0);
case r is
when c_status =>
io_rdata(7) <= irq_pend;
io_rdata(6) <= trans_done;
io_rdata(5) <= verify_error;
io_rdata(4) <= mask(1); -- for 256k and larger, this is set to '1'.
io_rdata(3 downto 0) <= X"0"; -- version
when c_command =>
io_rdata(7) <= command.execute;
io_rdata(6) <= reserved(2);
io_rdata(5) <= command.autoload;
io_rdata(4) <= command.ff00;
io_rdata(3 downto 2) <= reserved(1 downto 0);
io_rdata(1 downto 0) <= command.mode;
when c_irqmask =>
io_rdata(7) <= control.irq_en;
io_rdata(6) <= control.irq_done;
io_rdata(5) <= control.irq_error;
when c_control =>
io_rdata(7) <= control.fix_c64;
io_rdata(6) <= control.fix_reu;
when c_c64base_l => io_rdata <= std_logic_vector(c64_addr(7 downto 0));
when c_c64base_h => io_rdata <= std_logic_vector(c64_addr(15 downto 8));
when c_reubase_l => io_rdata <= std_logic_vector(reu_addr(7 downto 0));
when c_reubase_m => io_rdata <= std_logic_vector(reu_addr(15 downto 8));
when c_reubase_h =>
if g_extended then
io_rdata <= std_logic_vector(reu_addr(23 downto 16));
else
io_rdata <= "11111" & std_logic_vector(reu_addr(18 downto 16)); -- maximum 19 bits
end if;
when c_translen_l => io_rdata <= std_logic_vector(count(7 downto 0));
when c_translen_h => io_rdata <= std_logic_vector(count(15 downto 8));
when c_size_read => if g_extended then io_rdata <= std_logic_vector(mask); end if;
when c_start_delay => if g_extended then io_rdata <= std_logic_vector(start_delay); end if;
when c_rate_div => if g_extended then io_rdata <= std_logic_vector(rate_div); end if;
when others =>
null;
end case;
end process;
irq_pend <= control.irq_en and ((control.irq_done and trans_done) or (control.irq_error and verify_error));
slot_resp.nmi <= '0';
slot_resp.irq <= irq_pend;
slot_resp.data <= io_rdata;
slot_resp.reg_output <= enable when slot_req.bus_address(8 downto 5)=X"8" and
slot_req.bus_address(4 downto 3)/="11" and
(state = idle)
else '0';
io_write <= (enable and slot_req.io_write) when slot_req.io_address(8 downto 5)=X"8" else '0';
io_read <= (enable and slot_req.io_read) when slot_req.io_address(8 downto 5)=X"8" else '0';
end gideon;
| gpl-3.0 | cfae9bc125fbe201efc07b3b53394d87 | 0.433763 | 3.954878 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/token_crc.vhd | 2 | 1,838 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc is
port (
clock : in std_logic;
token_in : in std_logic_vector(10 downto 0);
crc : out std_logic_vector(4 downto 0) );
end token_crc;
architecture Gideon of token_crc is
-- CRC-5 = x5 + x2 + 1
constant polynom : std_logic_vector(4 downto 0) := "00101";
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
tmp := (others => '1');
for i in token_in'reverse_range loop -- LSB first!
d := tmp(tmp'high) xor token_in(i); -- loop xor
tmp := tmp(tmp'high-1 downto 0) & '0'; -- cyclic shift
if d = '1' then -- if highest bit was '1' then apply polynom
tmp := tmp xor polynom;
end if;
tmp(0) := d;
end loop;
for i in tmp'range loop -- reverse
crc(crc'high-i) <= not tmp(i);
end loop;
end if;
end process;
end Gideon;
| gpl-3.0 | 20d1921cd7fc7b3b71ef763e03ec29a0 | 0.401523 | 4.549505 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/drive_registers.vhd | 1 | 7,128 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.c1541_pkg.all;
entity drive_registers is
generic (
g_clock_freq : natural := 50_000_000;
g_multi_mode : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
tick_1kHz : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
iec_reset_o : in std_logic;
use_c64_reset : out std_logic;
power : out std_logic;
drv_reset : out std_logic;
drive_address : out std_logic_vector(1 downto 0);
floppy_inserted : out std_logic;
disk_change_n : out std_logic;
force_ready : out std_logic;
write_prot_n : out std_logic;
bank_is_ram : out std_logic_vector(7 downto 1);
stop_on_freeze : out std_logic;
drive_type : out natural range 0 to 2;
do_snd_insert : out std_logic;
do_snd_remove : out std_logic;
track : in unsigned(6 downto 0);
side : in std_logic := '0';
mode : in std_logic;
motor_on : in std_logic );
end;
architecture rtl of drive_registers is
signal power_i : std_logic;
signal drv_reset_i : std_logic;
signal use_c64_reset_i : std_logic;
signal drive_address_i : std_logic_vector(1 downto 0);
signal sensor_i : std_logic;
signal bank_is_ram_i : std_logic_vector(7 downto 1);
signal inserted_i : std_logic;
signal disk_change_i : std_logic;
signal force_ready_i : std_logic;
signal stop_when_frozen : std_logic;
signal drive_type_i : std_logic_vector(1 downto 0);
signal write_delay : unsigned(10 downto 0); -- max 2047 = 2 sec
signal write_busy : std_logic;
signal manual_write : std_logic;
begin
p_reg: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
manual_write <= '0';
do_snd_insert <= '0';
do_snd_remove <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_drvreg_power =>
power_i <= io_req.data(0);
when c_drvreg_reset =>
drv_reset_i <= io_req.data(0);
use_c64_reset_i <= io_req.data(1);
stop_when_frozen <= io_req.data(2);
when c_drvreg_address =>
drive_address_i <= io_req.data(1 downto 0);
when c_drvreg_sensor =>
sensor_i <= io_req.data(0);
when c_drvreg_inserted =>
inserted_i <= io_req.data(0);
when c_drvreg_rammap =>
bank_is_ram_i <= io_req.data(7 downto 1);
when c_drvreg_man_write =>
manual_write <= '1';
when c_drvreg_diskchng =>
disk_change_i <= io_req.data(0);
force_ready_i <= io_req.data(1);
when c_drvreg_drivetype =>
if g_multi_mode then
drive_type_i <= io_req.data(1 downto 0);
end if;
when c_drvreg_sound =>
do_snd_insert <= io_req.data(0);
do_snd_remove <= io_req.data(1);
when others =>
null;
end case;
end if; -- write
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_drvreg_power =>
io_resp.data(0) <= power_i;
when c_drvreg_reset =>
io_resp.data(0) <= drv_reset_i;
io_resp.data(1) <= use_c64_reset_i;
io_resp.data(2) <= stop_when_frozen;
when c_drvreg_address =>
io_resp.data(1 downto 0) <= drive_address_i;
when c_drvreg_sensor =>
io_resp.data(0) <= sensor_i;
when c_drvreg_inserted =>
io_resp.data(0) <= inserted_i;
when c_drvreg_rammap =>
io_resp.data <= bank_is_ram_i & '0';
when c_drvreg_diskchng =>
io_resp.data(0) <= disk_change_i;
io_resp.data(1) <= force_ready_i;
when c_drvreg_drivetype =>
if g_multi_mode then
io_resp.data(1 downto 0) <= drive_type_i;
end if;
when c_drvreg_track =>
io_resp.data(6 downto 0) <= std_logic_vector(track(6 downto 0));
when c_drvreg_side =>
io_resp.data(0) <= side;
when c_drvreg_status =>
io_resp.data(0) <= motor_on;
io_resp.data(1) <= not mode; -- mode is '0' when writing
io_resp.data(2) <= write_busy;
when others =>
null;
end case;
end if; -- read
drv_reset <= drv_reset_i or iec_reset_o;
if reset='1' then
power_i <= '0';
drv_reset_i <= '1';
drive_address_i <= (others => '0');
sensor_i <= '0';
bank_is_ram_i <= (others => '0');
inserted_i <= '0';
disk_change_i <= '0';
use_c64_reset_i <= '1';
stop_when_frozen <= '1';
force_ready_i <= '0';
drive_type_i <= "00";
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if drv_reset_i = '1' then
write_busy <= '0';
write_delay <= (others => '0');
elsif (mode = '0' and motor_on = '1') or manual_write = '1' then
write_busy <= '1';
write_delay <= (others => '1');
elsif write_delay = 0 then
write_busy <= '0';
elsif tick_1kHz = '1' then
write_delay <= write_delay - 1;
end if;
end if;
end process;
power <= power_i;
drive_address <= drive_address_i;
floppy_inserted <= inserted_i;
disk_change_n <= not disk_change_i;
write_prot_n <= sensor_i;
bank_is_ram <= bank_is_ram_i;
use_c64_reset <= use_c64_reset_i;
stop_on_freeze <= stop_when_frozen;
force_ready <= force_ready_i;
drive_type <= to_integer(unsigned(drive_type_i));
end architecture;
| gpl-3.0 | 0f08307121c940380621cb261d03d250 | 0.43757 | 3.716371 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/vhdl_bfm/dram_8.vhd | 2 | 5,044 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : DRAM model
-------------------------------------------------------------------------------
-- File : dram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple DRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_string_util_pkg.all;
entity dram_8 is
generic (
g_cas_latency : positive := 3;
g_burst_len_r : positive := 4;
g_burst_len_w : positive := 4;
g_column_bits : positive := 10;
g_row_bits : positive := 13;
g_bank_bits : positive := 2 );
port (
CLK : in std_logic;
CKE : in std_logic;
A : in std_logic_vector(g_row_bits-1 downto 0);
BA : in std_logic_vector(g_bank_bits-1 downto 0);
CSn : in std_logic;
RASn : in std_logic;
CASn : in std_logic;
WEn : in std_logic;
DQM : in std_logic;
DQ : inout std_logic_vector(7 downto 0) );
end entity;
architecture bfm of dram_8 is
signal command : std_logic_vector(2 downto 0);
constant c_banks : integer := 2 ** g_bank_bits;
type t_row_array is array(0 to c_banks-1) of std_logic_vector(g_row_bits-1 downto 0);
signal bank_rows : t_row_array;
signal bank : integer;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal r_queue : t_byte_array(0 to g_cas_latency + g_burst_len_r) := (others => (others => 'Z'));
-- constant c_col : integer := 0;
-- constant c_bank : integer := g_column_bits;
-- constant c_row : integer := g_column_bits + g_bank_bits;
shared variable mem_array : t_byte_array(0 to 16#FFFFFF#) := (others => X"33");
begin
command <= WEn & CASn & RASn;
bank <= to_integer(unsigned(BA));
DQ <= transport r_queue(0) after 6 ns;
process(CLK)
variable raddr : natural := 0;
variable waddr : natural := 0;
variable more_writes : integer := 0;
function map_address(bank_bits : std_logic_vector(g_bank_bits-1 downto 0);
row_bits : std_logic_vector(g_row_bits-1 downto 0);
col_bits : std_logic_vector(g_column_bits-1 downto 0) ) return integer is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
ret(g_column_bits-1 downto 0) := col_bits;
ret(g_column_bits+g_bank_bits-1 downto g_column_bits) := bank_bits;
ret(g_column_bits+g_bank_bits+g_row_bits-1 downto g_column_bits+g_bank_bits) := row_bits;
return to_integer(unsigned(ret(23 downto 0)));
end function;
begin
if rising_edge(CLK) then
if CKE='1' then
r_queue <= r_queue(1 to r_queue'high) & ("ZZZZZZZZ");
if more_writes > 0 then
waddr := waddr + 1;
if (waddr mod g_burst_len_w) = 0 then
waddr := waddr - g_burst_len_w;
end if;
if DQM='0' then
mem_array(waddr) := DQ;
end if;
more_writes := more_writes - 1;
end if;
if CSn='0' then
case command is
when "110" => -- RAS, register bank address
bank_rows(bank) <= A(g_row_bits-1 downto 0);
when "101" => -- CAS, start read burst
raddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
for i in 0 to g_burst_len_r-1 loop
r_queue(g_cas_latency-1 + i) <= mem_array(raddr);
raddr := raddr + 1;
if (raddr mod g_burst_len_r) = 0 then
raddr := raddr - g_burst_len_r;
end if;
end loop;
when "001" => -- CAS & WE, start write burst
waddr := map_address(BA, bank_rows(bank), A(g_column_bits-1 downto 0));
more_writes := g_burst_len_w - 1;
if DQM='0' then
mem_array(waddr) := DQ;
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
end bfm;
| gpl-3.0 | 126ece175d93cdeb1e9e3f1d4331b31b | 0.444489 | 3.888975 | false | false | false | false |
chiggs/nvc | test/sem/issue162.vhd | 5 | 1,143 | package ambiguous is
end package;
package body ambiguous is
procedure proc(arg1 : integer;
arg2 : boolean := false) is
begin
end procedure;
procedure proc(arg2 : boolean := false) is
begin
end procedure;
procedure calling_proc is
begin
proc; -- Works
proc(false); -- Works
proc(1, false); -- Works
proc(arg1 => 1, arg2 => true); -- Works
proc(arg2 => true); -- Adding the named argument cause error on ambiguous call
end procedure;
function fun(arg1 : integer;
arg2 : boolean := false) return integer is
begin
return 1;
end function;
function fun(arg2 : boolean := false) return integer is
begin
return 0;
end function;
function calling_fun_works(arg2 : boolean := false) return integer is
begin
-- Works
assert fun(true) = 0;
assert fun(1, true) = 0;
assert fun(arg1 => 1, arg2 => true) = 0;
return 0;
end function;
function calling_fun(arg2 : boolean := false) return integer is
begin
return fun(arg2 => true); -- Adding named argument cause error on ambiguous call
end function;
end package body;
| gpl-3.0 | e7a937b62e547c30699b471a6b592dd3 | 0.63867 | 3.901024 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/std/sram_4en.vhd | 2 | 2,971 | ----------------------------------------------------------------------------------------------
--
-- Input file : sram_4en.vhd
-- Design name : sram_4en
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Single Port Synchronous Random Access Memory with 4 write enable
-- ports.
-- Architecture 'arch' : Default implementation
-- Architecture 'arch2' : Alternative implementation
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.std_Pkg.all;
entity sram_4en is generic
(
WIDTH : positive := 32;
SIZE : positive := 16
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic_vector(WIDTH/8 - 1 downto 0);
ena_i : in std_logic;
clk_i : in std_logic
);
end sram_4en;
-- Although this memory is very easy to use in conjunction with Modelsims mem load, it is not
-- supported by many devices (although it comes straight from the library. Many devices give
-- cryptic synthesization errors on this implementation, so it is not the default.
architecture arch2 of sram_4en is
type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
type sel_type is array(WIDTH/8 - 1 downto 0) of std_logic_vector(7 downto 0);
signal ram: ram_type;
signal di: sel_type;
begin
process(wre_i, dat_i, adr_i)
begin
for i in 0 to WIDTH/8 - 1 loop
if wre_i(i) = '1' then
di(i) <= dat_i((i+1)*8 - 1 downto i*8);
else
di(i) <= ram(my_conv_integer(adr_i))((i+1)*8 - 1 downto i*8);
end if;
end loop;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if ena_i = '1' then
ram(my_conv_integer(adr_i)) <= di(3) & di(2) & di(1) & di(0);
dat_o <= di(3) & di(2) & di(1) & di(0);
end if;
end if;
end process;
end arch2;
-- Less convenient but very general memory block with four separate write
-- enable signals. (4x8 bit)
architecture arch of sram_4en is
begin
mem: for i in 0 to WIDTH/8 - 1 generate
mem : sram generic map
(
WIDTH => 8,
SIZE => SIZE
)
port map
(
dat_o => dat_o((i+1)*8 - 1 downto i*8),
dat_i => dat_i((i+1)*8 - 1 downto i*8),
adr_i => adr_i,
wre_i => wre_i(i),
ena_i => ena_i,
clk_i => clk_i
);
end generate;
end arch;
| gpl-3.0 | b7c6d913437973fc73176f9bb9e32d0b | 0.513295 | 3.636475 | false | false | false | false |
markusC64/1541ultimate2 | fpga/devices/vhdl_source/microwire_eeprom.vhd | 1 | 9,355 | --------------------------------------------------------------------------------
-- Entity: microwire_eeprom
-- Date:2018-08-13
-- Author: gideon
--
-- Description: Emulation of ST M93C86 Microwire EEPROM.
-- The I/O interface enables the software to read/write directly to
-- the 2K embedded memory. The range is 4K. The lower 2K give access
-- to the "dirty" bit register. The upper 2K is memory.
-- This emulation supports multiple write, continuous read as well
-- as single and full erase operations. It does support the status
-- output, however, the output is not gated with the select input.
-- When used as a standalone, data_out shall be tristated when SEL
-- is 0.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity microwire_eeprom is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
-- microwire bus
sel_in : in std_logic;
clk_in : in std_logic;
data_in : in std_logic;
data_out : out std_logic );
end entity;
architecture arch of microwire_eeprom is
type t_state is (idle, selected, instruction, decode, collect_data, wait_deselect, execute, write2, error, fill, reading );
signal state : t_state;
signal sel_c : std_logic;
signal sel_d : std_logic;
signal dat_c : std_logic;
signal dat_d : std_logic;
signal clk_c : std_logic;
signal clk_d : std_logic;
signal clk_d2 : std_logic;
signal mem_io_rdata : std_logic_vector(7 downto 0);
signal mem_io_en : std_logic;
signal mem_io_en_d : std_logic;
signal mem_rdata : std_logic_vector(7 downto 0);
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_en : std_logic;
signal mem_en_d : std_logic := '0';
signal mem_we : std_logic;
signal mem_address : unsigned(10 downto 0);
signal count : integer range 0 to 15;
signal write_enable : std_logic;
signal instr : std_logic_vector(11 downto 0);
signal data_word : std_logic_vector(15 downto 0);
signal dirty : std_logic;
begin
mem_io_en <= io_req.address(11) and (io_req.read or io_req.write);
i_mem: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => 11
)
port map(
a_clock => clock,
a_address => io_req.address(10 downto 0),
a_rdata => mem_io_rdata,
a_wdata => io_req.data,
a_en => mem_io_en,
a_we => io_req.write,
b_clock => clock,
b_address => mem_address,
b_rdata => mem_rdata,
b_wdata => mem_wdata,
b_en => mem_en,
b_we => mem_we
);
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
mem_io_en_d <= mem_io_en;
if mem_io_en_d = '1' then
io_resp.ack <= '1';
io_resp.data <= mem_io_rdata;
elsif io_req.read = '1' and io_req.address(11) = '0' then -- registers
io_resp.data(0) <= dirty;
io_resp.ack <= '1';
elsif io_req.write = '1' and io_req.address(11) = '0' then -- registers
dirty <= '0';
io_resp.ack <= '1';
end if;
if mem_we = '1' then
dirty <= '1';
end if;
sel_c <= sel_in;
sel_d <= sel_c;
dat_c <= data_in;
dat_d <= dat_c;
clk_c <= clk_in;
clk_d <= clk_c;
clk_d2 <= clk_d;
mem_en <= '0';
mem_we <= '0';
mem_en_d <= mem_en;
case state is
when idle =>
count <= 11;
data_out <= '1'; -- ready
data_word <= (others => '1');
if sel_d = '1' then
state <= selected;
end if;
when selected =>
if sel_d = '0' then
state <= idle;
elsif clk_d = '1' and clk_d2 = '0' then -- rising edge
if dat_d = '1' then
state <= instruction;
else
state <= error;
end if;
end if;
when instruction =>
if sel_d = '0' then
state <= idle;
elsif clk_d = '1' and clk_d2 = '0' then -- rising edge
instr <= instr(instr'high-1 downto 0) & dat_d;
if count = 0 then
state <= decode;
else
count <= count - 1;
end if;
end if;
when decode =>
count <= 15;
if instr(11 downto 10) = "01" then -- WRITE
state <= collect_data;
elsif instr(11 downto 8) = "0001" then -- WRALL
state <= collect_data;
elsif instr(11 downto 10) = "10" then -- READ
mem_address <= unsigned(instr(9 downto 0)) & '0';
mem_en <= '1';
state <= reading;
else
state <= wait_deselect;
end if;
when collect_data =>
if sel_d = '0' then
state <= idle;
elsif clk_d = '1' and clk_d2 = '0' then -- rising edge
data_word <= data_word(14 downto 0) & dat_d;
if count = 0 then
state <= wait_deselect;
else
count <= count - 1;
end if;
end if;
when wait_deselect =>
if clk_d = '1' and clk_d2 = '0' then -- rising edge
state <= error;
elsif sel_d = '0' then
state <= execute;
end if;
when execute =>
data_out <= '0';
if instr(10) = '1' then -- WRITE or ERASE single
mem_address <= unsigned(instr(9 downto 0)) & '0';
mem_wdata <= data_word(15 downto 8);
mem_en <= '1';
mem_we <= write_enable;
state <= write2;
elsif instr(11 downto 8) = "0011" then -- WREN
write_enable <= '1';
state <= idle;
elsif instr(11 downto 8) = "0000" then -- WRDIS
write_enable <= '0';
state <= idle;
elsif instr(11 downto 8) = "0010" then -- ERAL
mem_address <= (others => '0');
state <= fill;
elsif instr(11 downto 8) = "0001" then -- WRALL
mem_address <= (others => '0');
state <= fill;
else
state <= idle;
end if;
when error =>
if sel_d = '0' then
state <= idle;
end if;
when fill =>
mem_en <= '1';
mem_we <= write_enable;
if mem_address(0) = '1' then
mem_wdata <= data_word(7 downto 0);
else
mem_wdata <= data_word(15 downto 8);
end if;
if signed(mem_address) = -1 then
state <= idle;
else
mem_address <= mem_address + 1;
end if;
when write2 =>
mem_en <= '1';
mem_we <= write_enable;
mem_wdata <= data_word(7 downto 0);
mem_address(0) <= '1';
state <= idle;
when reading =>
if mem_en_d = '1' then
data_word(7 downto 0) <= mem_rdata;
count <= 7;
end if;
if sel_d = '0' then
state <= idle;
elsif clk_d = '1' and clk_d2 = '0' then -- rising edge
data_out <= data_word(count);
if count = 0 then
mem_address <= mem_address + 1;
mem_en <= '1';
else
count <= count - 1;
end if;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
write_enable <= '0';
count <= 0;
dirty <= '0';
mem_address <= (others => '0');
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 6272d83ad54d284914c7bfdc81951c4c | 0.401283 | 4.248411 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/c1581_drive.vhd | 1 | 11,133 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity c1581_drive is
generic (
g_big_endian : boolean;
g_audio_tag : std_logic_vector(7 downto 0) := X"01";
g_disk_tag : std_logic_vector(7 downto 0) := X"02";
g_cpu_tag : std_logic_vector(7 downto 0) := X"04";
g_audio : boolean := true;
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
drive_stop : in std_logic := '0';
-- timing
tick_4MHz : in std_logic;
tick_1KHz : in std_logic;
-- slave port on io bus
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic;
-- master port on memory bus
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
fast_clk_o : out std_logic; -- open drain
fast_clk_i : in std_logic;
-- Misc
iec_reset_n : in std_logic := '1';
c64_reset_n : in std_logic := '1';
-- LED
act_led_n : out std_logic;
power_led_n : out std_logic;
motor_led_n : out std_logic;
-- audio out
audio_sample : out signed(12 downto 0) := (others => '0'));
end entity;
architecture structural of c1581_drive is
signal cpu_clock_en : std_logic;
signal iec_reset_o : std_logic;
signal do_track_out : std_logic := '0';
signal do_track_in : std_logic := '0';
signal do_head_bang : std_logic := '0';
signal en_hum : std_logic := '0';
signal en_slip : std_logic := '0';
signal use_c64_reset : std_logic;
signal floppy_inserted : std_logic := '0';
signal force_ready : std_logic;
signal power : std_logic;
signal motor_on : std_logic;
signal side_0 : std_logic;
signal cur_track : unsigned(6 downto 0) := (others => '1');
signal drive_address : std_logic_vector(1 downto 0) := "00";
signal write_prot_n : std_logic := '1';
signal disk_change_n : std_logic := '1';
signal rdy_n : std_logic := '1';
signal drv_reset : std_logic := '1';
signal drive_stop_i : std_logic;
signal stop_on_freeze : std_logic;
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_dirty : t_io_req;
signal io_resp_dirty : t_io_resp;
signal io_req_param : t_io_req;
signal io_resp_param : t_io_resp;
signal io_req_wd : t_io_req;
signal io_resp_wd : t_io_resp;
signal mem_req_cpu : t_mem_req;
signal mem_resp_cpu : t_mem_resp;
signal mem_req_disk : t_mem_req;
signal mem_resp_disk : t_mem_resp;
signal mem_req_snd : t_mem_req := c_mem_req_init;
signal mem_resp_snd : t_mem_resp;
signal mem_req_8 : t_mem_req := c_mem_req_init;
signal mem_resp_8 : t_mem_resp;
signal mem_busy : std_logic;
signal count : unsigned(7 downto 0) := X"00";
signal led_intensity : unsigned(1 downto 0);
begin
-- IO bus split
i_splitter: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 4
)
port map(
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_dirty,
reqs(2) => io_req_param,
reqs(3) => io_req_wd,
resps(0) => io_resp_regs,
resps(1) => io_resp_dirty,
resps(2) => io_resp_param,
resps(3) => io_resp_wd
);
i_dummy_dirty: entity work.io_dummy
port map (
clock => clock,
io_req => io_req_dirty,
io_resp => io_resp_dirty
);
i_dummy_param: entity work.io_dummy
port map (
clock => clock,
io_req => io_req_param,
io_resp => io_resp_param
);
i_timing: entity work.c1541_timing
port map (
clock => clock,
reset => reset,
tick_4MHz => tick_4MHz,
two_MHz_mode => '1',
mem_busy => mem_busy,
use_c64_reset=> use_c64_reset,
c64_reset_n => c64_reset_n,
iec_reset_n => iec_reset_n,
iec_reset_o => iec_reset_o,
power => power,
drive_stop => drive_stop_i,
cpu_clock_en => cpu_clock_en ); -- 2 MHz
drive_stop_i <= drive_stop and stop_on_freeze;
i_cpu: entity work.cpu_part_1581
generic map (
g_cpu_tag => g_cpu_tag,
g_disk_tag => g_disk_tag,
g_ram_base => g_ram_base )
port map (
clock => clock,
falling => cpu_clock_en,
reset => drv_reset,
tick_1kHz => tick_1kHz,
tick_4MHz => tick_4MHz,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
fast_clk_o => fast_clk_o, -- open drain
fast_clk_i => fast_clk_i,
-- memory interface
mem_req_cpu => mem_req_cpu,
mem_resp_cpu => mem_resp_cpu,
mem_req_disk => mem_req_disk,
mem_resp_disk => mem_resp_disk,
mem_busy => mem_busy,
-- i/o interface to wd177x
io_req => io_req_wd,
io_resp => io_resp_wd,
io_irq => io_irq,
-- stepper interface
do_track_out => do_track_out,
do_track_in => do_track_in,
-- drive pins
power => power,
drive_address => drive_address,
write_prot_n => write_prot_n,
motor_on => motor_on,
rdy_n => rdy_n,
disk_change_n => disk_change_n,
side_0 => side_0,
cur_track => cur_track,
-- other
power_led => power_led_n,
act_led => act_led_n );
rdy_n <= not (motor_on and floppy_inserted) and not force_ready; -- should have a delay
-- Bare minimum drive mechanics.. :-D
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
cur_track <= (others => '0');
elsif do_track_in = '1' and cur_track /= 83 then
cur_track <= cur_track + 1;
elsif do_track_out = '1' and cur_track /= 0 then
cur_track <= cur_track - 1;
end if;
end if;
end process;
r_snd: if g_audio generate
begin
en_hum <= motor_on and not floppy_inserted;
en_slip <= motor_on and floppy_inserted;
i_snd: entity work.floppy_sound
generic map (
g_tag => g_audio_tag,
sound_base => g_audio_base(26 downto 15),
motor_hum_addr => X"0000",
flop_slip_addr => X"1200",
track_in_addr => X"2400",
track_out_addr => X"2C00",
head_bang_addr => X"3480",
motor_len => 4410,
track_in_len => X"0800", -- ~100 ms;
track_out_len => X"0880", -- ~100 ms;
head_bang_len => X"0880" ) -- ~100 ms;
port map (
clock => clock,
reset => drv_reset,
tick_4MHz => tick_4MHz,
do_trk_out => do_track_out,
do_trk_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
-- memory interface
mem_req => mem_req_snd,
mem_resp => mem_resp_snd,
-- audio
sample_out => audio_sample );
end generate;
i_regs: entity work.drive_registers
port map (
clock => clock,
reset => reset,
tick_1kHz => tick_1kHz,
io_req => io_req_regs,
io_resp => io_resp_regs,
iec_reset_o => iec_reset_o,
use_c64_reset => use_c64_reset,
power => power,
drv_reset => drv_reset,
drive_address => drive_address,
floppy_inserted => floppy_inserted,
disk_change_n => disk_change_n,
force_ready => force_ready,
write_prot_n => write_prot_n,
stop_on_freeze => stop_on_freeze,
track => cur_track,
mode => side_0,
motor_on => motor_on );
-- memory arbitration
i_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 3,
g_registered => false )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_cpu,
reqs(1) => mem_req_disk,
reqs(2) => mem_req_snd,
resps(0) => mem_resp_cpu,
resps(1) => mem_resp_disk,
resps(2) => mem_resp_snd,
req => mem_req_8,
resp => mem_resp_8 );
i_conv32: entity work.mem_to_mem32(route_through)
generic map (
g_big_endian => g_big_endian )
port map(
clock => clock,
reset => reset,
mem_req_8 => mem_req_8,
mem_resp_8 => mem_resp_8,
mem_req_32 => mem_req,
mem_resp_32 => mem_resp );
process(clock)
variable led_int : unsigned(7 downto 0);
begin
if rising_edge(clock) then
count <= count + 1;
if count=X"00" then
motor_led_n <= '0'; -- on
end if;
led_int := led_intensity & led_intensity & led_intensity & led_intensity;
if count=led_int then
motor_led_n <= '1'; -- off
end if;
end if;
end process;
led_intensity <= "00" when power='0' else
"01" when floppy_inserted='0' else
"10" when motor_on='0' else
"11";
end architecture;
| gpl-3.0 | 60a1d528bf2032fa57a31a6772cd42ff | 0.453427 | 3.408757 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/token_crc_19.vhd | 2 | 1,790 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_19 is
port (
clock : in std_logic;
token_in : in std_logic_vector(18 downto 0);
crc : out std_logic_vector(4 downto 0) );
end token_crc_19;
architecture Gideon of token_crc_19 is
-- CRC-5 = x5 + x2 + 1
constant polynom : std_logic_vector(4 downto 0) := "00101";
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
tmp := (others => '1');
L1: for i in token_in'reverse_range loop -- LSB first!
d := token_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & '0';
if d = '1' then
tmp := tmp xor polynom;
end if;
tmp(0) := d;
end loop;
for i in tmp'range loop -- reverse and invert
crc(crc'high-i) <= not(tmp(i));
end loop;
end if;
end process;
end Gideon;
| gpl-3.0 | 1ac8cccaa9b6e0b0931dbbf9e9eb3705 | 0.393855 | 4.497487 | false | false | false | false |
trondd/mkjpeg | design/common/JPEG_PKG.vhd | 1 | 2,508 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : JPEG_PKG
-- Design : JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : JPEG_PKG.VHD
-- Created : Sat Mar 7 2009
--
--------------------------------------------------------------------------------
--
-- Description : Package for JPEG core
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package JPEG_PKG is
-- do not change, constant
constant C_HDR_SIZE : integer := 623;
-- warning! this parameter heavily affects memory size required
-- if expected image width is known change this parameter to match this
-- otherwise some onchip RAM will be wasted and never used
constant C_MAX_LINE_WIDTH : integer := 2048;
-- memory/performance tradeoff
-- 8 extra lines highest performance
-- 0 extra lines lowest area
constant C_EXTRA_LINES : integer := 8; -- from 0 to 8
-- 24 bit format RGB/YCbCr 888 bits
-- 16 bit format RGB/YCbCr 565 bits
constant C_PIXEL_BITS : integer := 24;
-- 0 = RGB
-- 1 = YUV/YCbCr
constant C_YUV_INPUT : std_logic := '0';
type T_SM_SETTINGS is record
x_cnt : unsigned(15 downto 0);
y_cnt : unsigned(15 downto 0);
cmp_idx : unsigned(2 downto 0);
end record;
constant C_SM_SETTINGS : T_SM_SETTINGS :=
(
(others => '0'),
(others => '0'),
(others => '0')
);
function log2(n : natural) return natural;
end package JPEG_PKG;
package body JPEG_PKG is
-----------------------------------------------------------------------------
function log2(n : natural)
return natural is
begin
for i in 0 to 31 loop
if (2**i) >= n then
return i;
end if;
end loop;
return 32;
end log2;
-----------------------------------------------------------------------------
end package body JPEG_PKG; | lgpl-3.0 | 4f11c76199da76a5b1b7562e777b85b6 | 0.394737 | 5.026052 | false | false | false | false |
armandas/Arcade | plong_graphics.vhd | 1 | 15,386 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity plong_graphics is
port(
clk, not_reset: in std_logic;
nes1_up, nes1_down: in std_logic;
nes2_up, nes2_down: in std_logic;
nes1_start, nes2_start: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
video_on: in std_logic;
rgb_stream: out std_logic_vector(2 downto 0);
ball_bounced: out std_logic;
ball_missed: out std_logic
);
end plong_graphics;
architecture dispatcher of plong_graphics is
constant SCREEN_WIDTH: integer := 640;
constant SCREEN_HEIGHT: integer := 480;
type game_states is (start, waiting, playing, game_over);
signal state, state_next: game_states;
type counter_storage is array(0 to 3) of std_logic_vector(17 downto 0);
constant COUNTER_VALUES: counter_storage :=
(
"110010110111001101", -- 208333
"101000101100001011", -- 166667
"100001111010001001", -- 138889
"011101000100001000" -- 119048
);
-- counters to determine ball control frequency
signal ball_control_counter,
ball_control_counter_next: std_logic_vector(17 downto 0);
signal ball_control_value: integer;
-- counts how many times the ball hits the bar
-- used to determine ball speed
signal bounce_counter, bounce_counter_next: std_logic_vector(7 downto 0);
constant MIDDLE_LINE_POS: integer := SCREEN_WIDTH / 2;
signal middle_line_on: std_logic;
signal middle_line_rgb: std_logic_vector(2 downto 0);
signal score_1, score_1_next: std_logic_vector(5 downto 0);
signal score_2, score_2_next: std_logic_vector(5 downto 0);
signal score_on: std_logic;
signal current_score: std_logic_vector(5 downto 0);
signal score_font_addr: std_logic_vector(8 downto 0);
-- message format is "PLAYER p WINS!"
-- where p is replaced by player_id
signal message_on, player_id_on: std_logic;
signal message_font_addr, player_id_font_addr: std_logic_vector(8 downto 0);
signal font_addr: std_logic_vector(8 downto 0);
signal font_data: std_logic_vector(0 to 7);
signal font_pixel: std_logic;
signal font_rgb: std_logic_vector(2 downto 0);
constant BALL_SIZE: integer := 16; -- ball is square
signal ball_enable: std_logic;
signal ball_addr: std_logic_vector(3 downto 0);
signal ball_px_addr: std_logic_vector(3 downto 0);
signal ball_data: std_logic_vector(0 to BALL_SIZE - 1);
signal ball_pixel: std_logic;
signal ball_rgb: std_logic_vector(2 downto 0);
signal ball_x, ball_x_next: std_logic_vector(9 downto 0);
signal ball_y, ball_y_next: std_logic_vector(9 downto 0);
signal ball_h_dir, ball_h_dir_next, ball_v_dir, ball_v_dir_next: std_logic;
signal ball_bounce, ball_miss: std_logic;
constant BAR_1_POS: integer := 20;
constant BAR_2_POS: integer := 600;
constant BAR_WIDTH: integer := 20;
constant BAR_HEIGHT: integer := 64;
signal bar_pos: integer;
signal bar_addr: std_logic_vector(5 downto 0);
signal bar_data: std_logic_vector(0 to BAR_WIDTH - 1);
signal bar_pixel: std_logic;
signal bar_rgb: std_logic_vector(2 downto 0);
signal bar_1_y, bar_1_y_next,
bar_2_y, bar_2_y_next: std_logic_vector(9 downto 0);
signal ball_on, bar_on: std_logic;
signal nes_start: std_logic;
begin
process(state, ball_x, nes_start, score_1, score_2)
begin
state_next <= state;
ball_enable <= '0';
ball_miss <= '0';
score_1_next <= score_1;
score_2_next <= score_2;
case state is
when start =>
score_1_next <= (others => '0');
score_2_next <= (others => '0');
state_next <= waiting;
when waiting =>
ball_enable <= '0';
if score_1 = 7 or score_2 = 7 then
state_next <= game_over;
elsif nes_start = '1' then
state_next <= playing;
end if;
when playing =>
ball_enable <= '1';
if ball_x = 0 then
-- player 2 wins
score_2_next <= score_2 + 1;
state_next <= waiting;
ball_miss <= '1';
elsif ball_x = SCREEN_WIDTH - BALL_SIZE then
-- player 1 wins
score_1_next <= score_1 + 1;
state_next <= waiting;
ball_miss <= '1';
end if;
when game_over =>
if nes_start = '1' then
state_next <= start;
end if;
end case;
end process;
process(clk, not_reset)
begin
if not_reset = '0' then
state <= start;
ball_x <= (others => '0');
ball_y <= (others => '0');
bar_1_y <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BAR_HEIGHT / 2, 10);
bar_2_y <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BAR_HEIGHT / 2, 10);
ball_h_dir <= '0';
ball_v_dir <= '0';
bounce_counter <= (others => '0');
ball_control_counter <= (others => '0');
score_1 <= (others => '0');
score_2 <= (others => '0');
elsif clk'event and clk = '0' then
state <= state_next;
ball_x <= ball_x_next;
ball_y <= ball_y_next;
bar_1_y <= bar_1_y_next;
bar_2_y <= bar_2_y_next;
ball_h_dir <= ball_h_dir_next;
ball_v_dir <= ball_v_dir_next;
bounce_counter <= bounce_counter_next;
ball_control_counter <= ball_control_counter_next;
score_1 <= score_1_next;
score_2 <= score_2_next;
end if;
end process;
nes_start <= (nes1_start or nes2_start);
score_on <= '1' when px_y(9 downto 3) = 1 and
(px_x(9 downto 3) = 42 or px_x(9 downto 3) = 37) else
'0';
current_score <= score_1 when px_x < 320 else score_2;
-- numbers start at memory location 128
-- '1' starts at 136, '2' at 144 and so on
score_font_addr <= conv_std_logic_vector(128, 9) +
(current_score(2 downto 0) & current_score(5 downto 3));
player_id_on <= '1' when state = game_over and px_y(9 downto 3) = 29 and
(px_x(9 downto 3) = 19 or px_x(9 downto 3) = 59) else
'0';
-- player_id will display either 1 or 2
player_id_font_addr <= "010001000" when px_x < 320 else "010010000";
message_on <= '1' when state = game_over and
-- message on player_1's side
((score_1 > score_2 and
px_x(9 downto 3) >= 12 and
px_x(9 downto 3) < 26 and
px_y(9 downto 3) = 29) or
-- message on player_2's side
(score_2 > score_1 and
px_x(9 downto 3) >= 52 and
px_x(9 downto 3) < 66 and
px_y(9 downto 3) = 29)) else
'0';
with px_x(9 downto 3) select
message_font_addr <= "110000000" when "0110100"|"0001100", -- P
"101100000" when "0110101"|"0001101", -- L
"100001000" when "0110110"|"0001110", -- A
"111001000" when "0110111"|"0001111", -- Y
"100101000" when "0111000"|"0010000", -- E
"110010000" when "0111001"|"0010001", -- R
"111100000" when "0111011"|"0010011", -- not visible
"110111000" when "0111101"|"0010101", -- W
"101111000" when "0111110"|"0010110", -- O
"101110000" when "0111111"|"0010111", -- N
"000001000" when "1000000"|"0011000", -- !
"000000000" when others;
-- font address mutltiplexer
font_addr <= px_y(2 downto 0) + score_font_addr when score_on = '1' else
px_y(2 downto 0) + player_id_font_addr when player_id_on = '1' else
px_y(2 downto 0) + message_font_addr when message_on = '1' else
(others => '0');
font_pixel <= font_data(conv_integer(px_x(2 downto 0)));
font_rgb <= "000" when font_pixel = '1' else "111";
direction_control: process(
ball_control_counter,
ball_x, ball_y,
ball_h_dir, ball_v_dir,
ball_h_dir_next, ball_v_dir_next,
bar_1_y, bar_2_y
)
begin
ball_h_dir_next <= ball_h_dir;
ball_v_dir_next <= ball_v_dir;
ball_bounce <= '0';
--
-- BEWARE! Looks like ball_bounce signal is generated twice
-- due to slower clock! Too lazy to fix now :D
--
if ball_control_counter = 0 then
if ball_x = bar_1_pos + BAR_WIDTH and
ball_y + BALL_SIZE > bar_1_y and
ball_y < bar_1_y + BAR_HEIGHT then
ball_h_dir_next <= '1';
ball_bounce <= '1';
elsif ball_x + BALL_SIZE = bar_2_pos and
ball_y + BALL_SIZE > bar_2_y and
ball_y < bar_2_y + BAR_HEIGHT then
ball_h_dir_next <= '0';
ball_bounce <= '1';
elsif ball_x < bar_1_pos + BAR_WIDTH and
ball_x + BALL_SIZE > bar_1_pos then
if ball_y + BALL_SIZE = bar_1_y then
ball_v_dir_next <= '0';
elsif ball_y = bar_1_y + BAR_HEIGHT then
ball_v_dir_next <= '1';
end if;
elsif ball_x + BALL_SIZE > bar_2_pos and
ball_x < bar_2_pos + BAR_WIDTH then
if ball_y + BALL_SIZE = bar_2_y then
ball_v_dir_next <= '0';
elsif ball_y = bar_2_y + BAR_HEIGHT then
ball_v_dir_next <= '1';
end if;
end if;
if ball_y = 0 then
ball_v_dir_next <= '1';
elsif ball_y = SCREEN_HEIGHT - BALL_SIZE then
ball_v_dir_next <= '0';
end if;
end if;
end process;
bounce_counter_next <= bounce_counter + 1 when ball_bounce = '1' else
(others => '0') when ball_miss = '1' else
bounce_counter;
ball_control_value <= 0 when bounce_counter < 4 else
1 when bounce_counter < 15 else
2 when bounce_counter < 25 else
3;
ball_control_counter_next <= ball_control_counter + 1 when ball_control_counter < COUNTER_VALUES(ball_control_value) else
(others => '0');
ball_control: process(
ball_control_counter,
ball_x, ball_y,
ball_x_next, ball_y_next,
ball_h_dir, ball_v_dir,
ball_enable
)
begin
ball_x_next <= ball_x;
ball_y_next <= ball_y;
if ball_enable = '1' then
if ball_control_counter = 0 then
if ball_h_dir = '1' then
ball_x_next <= ball_x + 1;
else
ball_x_next <= ball_x - 1;
end if;
if ball_v_dir = '1' then
ball_y_next <= ball_y + 1;
else
ball_y_next <= ball_y - 1;
end if;
end if;
else
ball_x_next <= conv_std_logic_vector(SCREEN_WIDTH / 2 - BALL_SIZE / 2, 10);
ball_y_next <= conv_std_logic_vector(SCREEN_HEIGHT / 2 - BALL_SIZE / 2, 10);
end if;
end process;
bar_control: process(
bar_1_y, bar_2_y,
nes1_up, nes1_down,
nes2_up, nes2_down
)
begin
bar_1_y_next <= bar_1_y;
bar_2_y_next <= bar_2_y;
if nes1_up = '1' then
if bar_1_y > 0 then
bar_1_y_next <= bar_1_y - 1;
end if;
elsif nes1_down = '1' then
if bar_1_y < SCREEN_HEIGHT - BAR_HEIGHT - 1 then
bar_1_y_next <= bar_1_y + 1;
end if;
end if;
if nes2_up = '1' then
if bar_2_y > 0 then
bar_2_y_next <= bar_2_y - 1;
end if;
elsif nes2_down = '1' then
if bar_2_y < SCREEN_HEIGHT - BAR_HEIGHT - 1 then
bar_2_y_next <= bar_2_y + 1;
end if;
end if;
end process;
middle_line_on <= '1' when px_x = MIDDLE_LINE_POS else '0';
middle_line_rgb <= "000" when px_y(0) = '1' else "111";
ball_on <= '1' when px_x >= ball_x and
px_x < (ball_x + BALL_SIZE) and
px_y >= ball_y and
px_y < (ball_y + BALL_SIZE) else
'0';
-- whether bar_1 or bar_2 is on
bar_on <= '1' when (px_x >= BAR_1_POS and
px_x < BAR_1_POS + BAR_WIDTH and
px_y >= bar_1_y and
px_y < bar_1_y + BAR_HEIGHT) or
(px_x >= BAR_2_POS and
px_x < BAR_2_POS + BAR_WIDTH and
px_y >= bar_2_y and
px_y < bar_2_y + BAR_HEIGHT) else
'0';
ball_addr <= px_y(3 downto 0) - ball_y(3 downto 0);
ball_px_addr <= px_x(3 downto 0) - ball_x(3 downto 0);
ball_pixel <= ball_data(conv_integer(ball_px_addr));
ball_rgb <= "000" when ball_pixel = '1' else "111";
bar_addr <= (px_y(5 downto 0) - bar_1_y(5 downto 0)) when px_x < 320 else
(px_y(5 downto 0) - bar_2_y(5 downto 0));
bar_pos <= BAR_1_POS when px_x < 320 else BAR_2_POS;
bar_pixel <= bar_data(conv_integer(px_x - bar_pos));
bar_rgb <= "000" when bar_pixel = '1' else "111";
process(
ball_on, bar_on,
ball_rgb, bar_rgb,
score_on, message_on, font_rgb,
middle_line_on, middle_line_rgb,
video_on
)
begin
if video_on = '1' then
if bar_on = '1' then
rgb_stream <= bar_rgb;
elsif ball_on = '1' then
rgb_stream <= ball_rgb;
elsif middle_line_on = '1' then
rgb_stream <= middle_line_rgb;
-- scores and messages share rgb stream
elsif score_on = '1' or message_on = '1' then
rgb_stream <= font_rgb;
else
-- background is white
rgb_stream <= "111";
end if;
else
-- blank screen
rgb_stream <= "000";
end if;
end process;
ball_unit:
entity work.ball_rom(content)
port map(addr => ball_addr, data => ball_data);
bar_unit:
entity work.bar_rom(content)
port map(clk => clk, addr => bar_addr, data => bar_data);
font_unit:
entity work.codepage_rom(content)
port map(addr => font_addr, data => font_data);
ball_bounced <= ball_bounce;
ball_missed <= ball_miss;
end dispatcher;
| bsd-2-clause | e8133531f9660af8e67e1aae4e8294d6 | 0.492721 | 3.589827 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio/lp_filter2.vhd | 1 | 3,002 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2016 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity lp_filter is
port (
clock : in std_logic;
reset : in std_logic;
signal_in : in signed(17 downto 0);
high_pass : out signed(17 downto 0);
band_pass : out signed(17 downto 0);
low_pass : out signed(17 downto 0);
error_out : out std_logic;
valid_out : out std_logic );
end entity;
architecture dsvf of lp_filter is
--signal filter_q : signed(signal_in'range);
--signal filter_f : signed(signal_in'range);
signal input_sc : signed(signal_in'range);
signal reg_a : signed(25 downto 0);
signal reg_b : signed(25 downto 0);
begin
--filter_q <= to_signed(65536 + 16384, filter_q'length); -- 92682
--filter_f <= to_signed( 64, filter_f'length);
input_sc <= signal_in; -- shift_right(signal_in, 1);
process(clock)
variable af, vq, lp, hp, hpf, bp : signed(25 downto 0);
function mult2_24 (xa, xb : signed(17 downto 0)) return signed is
variable result : signed(35 downto 0);
begin
result := xa * xb;
return result(33 downto 8);
end function;
begin
if rising_edge(clock) then
-- af := mult2_24(filter_f, reg_a(25 downto 8)); -- 26 bit
-- *64 in 2_16 format is actually shifting to the right by (16-6=) 10 bits
af := shift_right(reg_a, 10);
lp := af + reg_b; -- 26 bit
-- vq := mult2_24(filter_q, reg_a(25 downto 8)); -- 26 bit
-- * 65536+16384 = *1.125 = addition with its shifted self.
vq := reg_a + shift_right(reg_a, 2);
hp := (input_sc & X"00") - vq - lp;
-- hpf := mult2_24(filter_f, hp(25 downto 8));
hpf := shift_right(hp, 10);
bp := hpf + reg_a;
reg_a <= bp;
reg_b <= lp;
low_pass <= lp(25 downto 8);
band_pass <= bp(25 downto 8);
high_pass <= hp(25 downto 8);
valid_out <= '1';
if reset = '1' then
reg_a <= (others => '0');
reg_b <= (others => '0');
valid_out <= '0';
end if;
end if;
end process;
error_out <= '0';
end dsvf;
| gpl-3.0 | c5a802a65dc2c962bc6c8ad4ce75af37 | 0.464357 | 3.8 | false | false | false | false |
chiggs/nvc | test/sem/array.vhd | 1 | 10,057 | package p is
type int_array is array (integer range <>) of integer;
type ten_ints is array (1 to 10) of integer;
end package;
entity e is
end entity;
use work.p.all;
architecture a of e is
-- All these declarations are OK
signal x : int_array(1 to 5);
signal y : ten_ints;
signal z : int_array(1 to 3) := ( 0, 1, 2 );
signal m : int_array(1 to 3) := ( 1 to 3 => 0 );
alias a : int_array(2 to 3) is x(2 to 3);
begin
process is
-- Positional elements cannot follow named
variable e : int_array(1 to 2) := (
0 => 1, 2 );
begin
end process;
process is
-- Others element must be last
variable e : ten_ints := ( others => 5, 1 => 2 );
begin
end process;
process is
-- Only one others element
variable e : ten_ints := ( others => 5, others => 2 );
begin
end process;
process is
-- Single element aggregates must be named
variable a : int_array(0 to 0) := ( 0 => 1 );
variable b : int_array(0 to 0) := ( 1 ); -- Error
begin
end process;
process is
variable a : integer;
begin
x(0) <= 1; -- OK
x <= ( others => 2 ); -- OK
x <= 1; -- RHS not array
a := x(0); -- OK
a := x; -- LHS not array
end process;
process is
variable b : boolean;
begin
b := z = m; -- OK
b := z /= m; -- OK
b := z = y; -- Different types
end process;
process is
begin
x(1 to 3) <= z;
x(1 to 2) <= z(1 to 2);
x(x'range) <= (others => 0);
end process;
process is
begin
a(2) <= 4; -- OK
y(2) <= 1; -- OK
end process;
process is
type int2d is array (1 to 10, 1 to 4) of integer;
variable w : int2d := ( 1 => ( 1, 2, 3, 4 ),
2 => ( others => 5 ),
others => ( others => 0 ) );
begin
w(2, 4) := 6;
w(6) := 6; -- Too few indices
w(6, 7, 2) := 2; -- Too many indices
end process;
process is
type letter is (A, B, C);
type larray is array (letter) of integer;
variable w : larray;
begin
w(A) := 2; -- OK
w(5) := 66; -- Wrong index type
end process;
process is
variable n : int_array(1 to 3) := ( 0, 1 => 1, others => 2 ); -- Error
begin
end process;
process is
variable x : integer;
constant c : integer := 3;
variable y : int_array(1 to 3);
begin
y := ( 1 => 2, 2 => 3, x => 5 ); -- Error
y := ( 1 => 2, 2 => 3, c => 5 ); -- OK
end process;
process is
variable x : integer;
variable y : int_array(3 downto 0);
begin
x(1 to 3) := (others => 4); -- Error
y(1 to 3) := (others => 4); -- Error
assert y = (others => 4); -- Error
end process;
process is
subtype five_ints is ten_ints(1 to 4);
variable x : five_ints;
begin
x(1 to 3) := (1, 2, 3); -- OK
x(2) := 1; -- OK
x(3 downto 1) := (others => '0'); -- Error
assert x(2) = 5; -- OK
end process;
process is
function foo(size: integer) return int_array is
subtype rtype is int_array(size-1 downto 0);
variable result: rtype;
begin
assert result(0) = 1;
return result;
end;
begin
end process;
process is
function plus(A, B: int_array) return int_array is
variable BV, sum: int_array(A'left downto 0);
begin
return sum;
end;
begin
end process;
process is
subtype int4_t is int_array(1 to 4);
type foo_t is array (integer'left to 10) of integer;
variable v : int_array(foo_t'range);
variable u : foo_t;
begin
assert int4_t'length = 4;
assert foo_t'length = 50;
end process;
process is
subtype a_to_c is character range 'a' to 'c';
type abc_ints is array (a_to_c) of integer;
variable v : abc_ints;
begin
assert abc_ints'length = 3;
v('b') := 2;
end process;
process is
type bit_map is array (bit) of integer;
variable b : bit_map := ( '0' => 5, '1' => 6 );
type bit_map2 is array (bit, 0 to 1) of integer;
variable c : bit_map2 := (
'0' => (0 => 0, 1 => 1),
'1' => (0 => 2, 1 => 3) );
begin
b('0') := 6;
c('1', 1) := 5;
end process;
process is
constant c : ten_ints := (ten_ints'range => 5);
variable v : ten_ints;
begin
v := (v'range => 6); -- OK
end process;
process is
type mybit is ('0', '1');
type bit_map is array (bit range '0' to '1') of integer;
variable v : bit_map;
variable b : bit;
begin
v(b) := 1; -- OK
end process;
process is
begin
assert x'length(1) = 5; -- OK
end process;
process is
type bad is array (integer range <>) of int_array; -- Error
begin
end process;
process is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := ( (0, 1, 2), (0, 1, 2) ); -- OK
constant d : int2d := ( (0, 1), (5, 6, 7) ); -- OK (at sem)
constant e : int2d := ( (0, 1), (others => 2) ); -- Error
begin
end process;
process is
variable b1 : bit_vector(7 downto 0);
begin
b1 := b1 sll 1;
b1 := b1 srl 2;
b1 := b1 sla 0;
b1 := b1 sra 1;
b1 := b1 rol 6;
b1 := b1 ror 1;
end process;
process is
variable i : integer;
alias xi is x(1 to i); -- Error
alias zi : integer is z(i); -- Error
alias xx : integer is x(1 to 2); -- Error
begin
end process;
process is
variable i : integer;
begin
i(6) := 2; -- Error
end process;
process is
constant c : integer := -1;
type bad_range is array (-1 to -5) of integer; -- Error
type ok_range is array(c to -5) of integer; -- OK
begin
end process;
process is
subtype bad_sub1 is int_array(1 to 3, 2 to 5); -- Error
begin
end process;
process is
type element is array (integer range 0 to 1) of bit_vector( 0 to 1);
begin
end process;
process is
type ten_ten_ints is array (1 to 10) of ten_ints;
type int2d is array (natural range <>, natural range <>) of integer;
variable t1, t2 : ten_ten_ints;
variable m1, m2 : int2d(1 to 3, 1 to 3);
begin
assert t1 = t2; -- OK
assert t1 /= t2; -- OK
assert t1 < t2; -- OK
assert t1 > t2; -- OK
assert m1 = m2; -- OK
assert m1 < m2; -- Error
end process;
process is
subtype num_array is int_array; -- OK
subtype bad_array is not_here; -- Error
variable a1 : num_array(1 to 3); -- OK
variable a2 : num_array; -- Error
begin
end process;
process is
constant k : integer := 5;
type a is array (k) of integer; -- Error
variable v : a; -- Error
begin
end process;
process is
type ibv is array (boolean range <>) of integer;
variable a : ibv(false to true);
begin
a(false) := 1; -- OK
a(4) := 2; -- Error
a(false to false) := (others => 1); -- OK
end process;
process is
subtype r is integer range 1 to 3;
begin
x(r'range) <= (others => 1);
x(r) <= (others => 1);
end process;
process is
subtype str is string;
constant x : str := "hello"; -- OK
begin
end process;
process is
type barry2d is array (boolean range <>, boolean range <>)
of integer;
variable b : barry2d(false to true, false to true);
type ibarray2d is array (integer range <>, boolean range <>)
of integer;
variable ib : ibarray2d(1 to 5, false to true);
begin
b(barry2d'left(1), barry2d'left(2)) := 5; -- OK
ib(integer'(5), boolean'(true)) := 1; -- OK
ib(ibarray2d'left(1), ibarray2d'left(2)) := 5; -- OK
end process;
process is
type enum1 is (m1, m2, m3, m4, m5);
type abase is array (enum1 range <>) of boolean;
subtype a1 is abase(enum1 range m1 to m5);
variable V1 : A1;
begin
assert v1 = (false, false, false); -- OK
end process;
process is
variable x : int_array(1 to 3);
begin
x := (1 | 2 to 3 => 5); -- OK
end process;
process is
variable b : bit_vector(1 to 3); -- OK
begin
b := "1fe"; -- Error
end process;
issue86: block is
type integer_vector is array (natural range <>) of integer;
subtype ElementType is integer ;
subtype ArrayofElementType is integer_vector;
function inside0 (constant E : ElementType;
constant A : in ArrayofElementType) return boolean is
begin
for i in A'range loop -- OK (issue #86)
if E = A(i) then
return TRUE;
end if ;
end loop ;
return FALSE ;
end function inside0;
begin
end block;
end architecture;
| gpl-3.0 | 39e29fe3bebbe105d494c816ef36ffb8 | 0.465646 | 3.76949 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/harness_c1581.vhd | 1 | 3,892 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1581 is
port (
io_irq : out std_logic );
end entity;
architecture harness of harness_c1581 is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal iec_atn : std_logic;
signal iec_atn_o : std_logic;
signal iec_atn_i : std_logic;
signal iec_data : std_logic;
signal iec_data_o : std_logic;
signal iec_data_i : std_logic;
signal iec_clk : std_logic;
signal iec_clk_o : std_logic;
signal iec_clk_i : std_logic;
signal iec_fclk_o : std_logic;
signal iec_fclk_i : std_logic;
signal iec_fclk : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal act_led_n : std_logic;
signal audio_sample : signed(12 downto 0);
signal tick_4MHz : std_logic := '0';
begin
clock <= not clock after 25 ns;
reset <= '1', '0' after 1000 ns;
process
begin
wait until clock = '1'; tick_4MHz <= '0';
wait until clock = '1'; tick_4MHz <= '0';
wait until clock = '1'; tick_4MHz <= '0';
wait until clock = '1'; tick_4MHz <= '0';
wait until clock = '1'; tick_4MHz <= '1';
end process;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_drive: entity work.c1581_drive
generic map (
g_big_endian => false,
g_audio => false,
g_audio_base => X"0010000",
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
-- timing
tick_4MHz => tick_4MHz,
-- slave port on io bus
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq,
-- master port on memory bus
mem_req => mem_req,
mem_resp => mem_resp,
-- serial bus pins
atn_o => iec_atn_o, -- open drain
atn_i => iec_atn_i,
clk_o => iec_clk_o, -- open drain
clk_i => iec_clk_i,
data_o => iec_data_o, -- open drain
data_i => iec_data_i,
fast_clk_o => iec_fclk_o, -- open drain
fast_clk_i => iec_fclk_i,
-- LED
act_led_n => act_led_n,
-- audio out
audio_sample => audio_sample );
iec_atn <= '0' when iec_atn_o='0' else 'Z';
iec_atn_i <= '0' when iec_atn='0' else '1';
iec_clk <= '0' when iec_clk_o='0' else 'Z';
iec_clk_i <= '0' when iec_clk='0' else '1';
iec_data <= '0' when iec_data_o='0' else 'Z';
iec_data_i <= '0' when iec_data='0' else '1';
iec_fclk <= '0' when iec_fclk_o='0' else 'Z';
iec_fclk_i <= '0' when iec_fclk='0' else '1';
i_memory: entity work.mem_bus_32_slave_bfm
generic map(
g_name => "dram",
g_latency => 2
)
port map(
clock => clock,
req => mem_req,
resp => mem_resp
);
iec_bfm: entity work.iec_bus_bfm
generic map ("iec_bfm")
port map (
iec_clock => iec_clk,
iec_data => iec_data,
iec_atn => iec_atn,
iec_srq => iec_fclk );
end harness;
| gpl-3.0 | f55ec1fa319e3175c5e74e350aa2554b | 0.463001 | 3.306712 | false | false | false | false |
cfelton/musicbox_simple | m_musicbox.vhd | 1 | 674,407 | -- File: m_musicbox.vhd
-- Generated by MyHDL 0.9dev
-- Date: Tue Dec 30 11:42:04 2014
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_09.all;
entity m_musicbox is
port (
clock: in std_logic;
reset: in std_logic;
note: out signed (14 downto 0);
nv: out std_logic
);
end entity m_musicbox;
-- module to generate a "tone".
--
-- Port Map
-- --------
-- clock : circuit synchronous clock
-- reset : circult reset
-- note : digital signal for the note
-- nv : note valid strobe
architecture MyHDL of m_musicbox is
constant ticks_per_fs: integer := 1042;
constant Nsmp: integer := 12000;
signal noteidx: unsigned(13 downto 0);
signal sample_rate_cnt: unsigned(10 downto 0);
begin
M_MUSICBOX_RTL: process (clock, reset) is
begin
if (reset = '0') then
sample_rate_cnt <= to_unsigned(1, 11);
note <= to_signed(0, 15);
noteidx <= to_unsigned(0, 14);
nv <= '0';
elsif rising_edge(clock) then
if (sample_rate_cnt = ticks_per_fs) then
sample_rate_cnt <= to_unsigned(1, 11);
case to_integer(noteidx) is
when 0 => note <= "000000000000000";
when 1 => note <= "001010100000010";
when 2 => note <= "010010110011010";
when 3 => note <= "010111010000111";
when 4 => note <= "010111010000110";
when 5 => note <= "010011010100001";
when 6 => note <= "001100111100011";
when 7 => note <= "000110010000011";
when 8 => note <= "000001010111001";
when 9 => note <= "111111110011011";
when 10 => note <= "000010001001010";
when 11 => note <= "000111110011011";
when 12 => note <= "001111001101111";
when 13 => note <= "010110010000011";
when 14 => note <= "011010110011010";
when 15 => note <= "011011010100001";
when 16 => note <= "010111010000110";
when 17 => note <= "001111010000111";
when 18 => note <= "000100111100011";
when 19 => note <= "111010100000010";
when 20 => note <= "110010001001010";
when 21 => note <= "101101011111110";
when 22 => note <= "101101001100110";
when 23 => note <= "110000101111001";
when 24 => note <= "110110100110001";
when 25 => note <= "111100101011111";
when 26 => note <= "000000111010011";
when 27 => note <= "000001101111101";
when 28 => note <= "111110101000111";
when 29 => note <= "111000001100101";
when 30 => note <= "110000000000000";
when 31 => note <= "101000001100101";
when 32 => note <= "100010111011010";
when 33 => note <= "100001101111101";
when 34 => note <= "100101001100110";
when 35 => note <= "101100101011111";
when 36 => note <= "110110100110001";
when 37 => note <= "000000101111001";
when 38 => note <= "001000111010011";
when 39 => note <= "001101011111110";
when 40 => note <= "001101110110110";
when 41 => note <= "001010100000010";
when 42 => note <= "000100111100011";
when 43 => note <= "111111010000111";
when 44 => note <= "111011100011001";
when 45 => note <= "111011010100001";
when 46 => note <= "111111000101101";
when 47 => note <= "000110010000011";
when 48 => note <= "001111001101111";
when 49 => note <= "010111110011011";
when 50 => note <= "011101110110110";
when 51 => note <= "011111110011011";
when 52 => note <= "011101000100110";
when 53 => note <= "010110010000011";
when 54 => note <= "001100111100011";
when 55 => note <= "000011010100001";
when 56 => note <= "111011100011001";
when 57 => note <= "110111010000111";
when 58 => note <= "110111000101101";
when 59 => note <= "111010100000010";
when 60 => note <= "000000000000000";
when 61 => note <= "000101011111110";
when 62 => note <= "001000111010011";
when 63 => note <= "001000101111001";
when 64 => note <= "000100011100111";
when 65 => note <= "111100101011111";
when 66 => note <= "110011000011101";
when 67 => note <= "101001101111101";
when 68 => note <= "100010111011010";
when 69 => note <= "100000001100101";
when 70 => note <= "100010001001010";
when 71 => note <= "101000001100101";
when 72 => note <= "110000110010001";
when 73 => note <= "111001101111101";
when 74 => note <= "000000111010011";
when 75 => note <= "000100101011111";
when 76 => note <= "000100011100111";
when 77 => note <= "000000101111001";
when 78 => note <= "111011000011101";
when 79 => note <= "110101011111110";
when 80 => note <= "110010001001010";
when 81 => note <= "110010100000010";
when 82 => note <= "110111000101101";
when 83 => note <= "111111010000111";
when 84 => note <= "001001011001111";
when 85 => note <= "010011010100001";
when 86 => note <= "011010110011010";
when 87 => note <= "011110010000011";
when 88 => note <= "011101000100110";
when 89 => note <= "010111110011011";
when 90 => note <= "010000000000000";
when 91 => note <= "000111110011011";
when 92 => note <= "000001010111001";
when 93 => note <= "111110010000011";
when 94 => note <= "111111000101101";
when 95 => note <= "000011010100001";
when 96 => note <= "001001011001111";
when 97 => note <= "001111010000111";
when 98 => note <= "010010110011010";
when 99 => note <= "010010100000010";
when 100 => note <= "001101110110110";
when 101 => note <= "000101011111110";
when 102 => note <= "111011000011101";
when 103 => note <= "110000101111001";
when 104 => note <= "101000101111010";
when 105 => note <= "100100101011111";
when 106 => note <= "100101001100110";
when 107 => note <= "101001101111101";
when 108 => note <= "110000110010001";
when 109 => note <= "111000001100101";
when 110 => note <= "111101110110110";
when 111 => note <= "000000001100101";
when 112 => note <= "111110101000111";
when 113 => note <= "111001101111101";
when 114 => note <= "110011000011101";
when 115 => note <= "101100101011111";
when 116 => note <= "101000101111010";
when 117 => note <= "101000101111001";
when 118 => note <= "101101001100110";
when 119 => note <= "110101011111110";
when 120 => note <= "000000000000000";
when 121 => note <= "001010100000010";
when 122 => note <= "010010110011010";
when 123 => note <= "010111010000111";
when 124 => note <= "010111010000110";
when 125 => note <= "010011010100001";
when 126 => note <= "001100111100011";
when 127 => note <= "000110010000011";
when 128 => note <= "000001010111001";
when 129 => note <= "111111110011011";
when 130 => note <= "000010001001010";
when 131 => note <= "000111110011011";
when 132 => note <= "001111001101111";
when 133 => note <= "010110010000011";
when 134 => note <= "011010110011010";
when 135 => note <= "011011010100001";
when 136 => note <= "010111010000110";
when 137 => note <= "001111010000111";
when 138 => note <= "000100111100011";
when 139 => note <= "111010100000010";
when 140 => note <= "110010001001010";
when 141 => note <= "101101011111110";
when 142 => note <= "101101001100110";
when 143 => note <= "110000101111001";
when 144 => note <= "110110100110001";
when 145 => note <= "111100101011111";
when 146 => note <= "000000111010011";
when 147 => note <= "000001101111101";
when 148 => note <= "111110101000111";
when 149 => note <= "111000001100101";
when 150 => note <= "110000000000000";
when 151 => note <= "101000001100101";
when 152 => note <= "100010111011010";
when 153 => note <= "100001101111101";
when 154 => note <= "100101001100110";
when 155 => note <= "101100101011111";
when 156 => note <= "110110100110001";
when 157 => note <= "000000101111001";
when 158 => note <= "001000111010011";
when 159 => note <= "001101011111110";
when 160 => note <= "001101110110110";
when 161 => note <= "001010100000010";
when 162 => note <= "000100111100011";
when 163 => note <= "111111010000111";
when 164 => note <= "111011100011001";
when 165 => note <= "111011010100001";
when 166 => note <= "111111000101101";
when 167 => note <= "000110010000011";
when 168 => note <= "001111001101111";
when 169 => note <= "010111110011011";
when 170 => note <= "011101110110110";
when 171 => note <= "011111110011011";
when 172 => note <= "011101000100110";
when 173 => note <= "010110010000011";
when 174 => note <= "001100111100011";
when 175 => note <= "000011010100001";
when 176 => note <= "111011100011001";
when 177 => note <= "110111010000111";
when 178 => note <= "110111000101101";
when 179 => note <= "111010100000010";
when 180 => note <= "000000000000000";
when 181 => note <= "000101011111110";
when 182 => note <= "001000111010011";
when 183 => note <= "001000101111001";
when 184 => note <= "000100011100111";
when 185 => note <= "111100101011111";
when 186 => note <= "110011000011101";
when 187 => note <= "101001101111101";
when 188 => note <= "100010111011010";
when 189 => note <= "100000001100101";
when 190 => note <= "100010001001010";
when 191 => note <= "101000001100101";
when 192 => note <= "110000110010001";
when 193 => note <= "111001101111101";
when 194 => note <= "000000111010011";
when 195 => note <= "000100101011111";
when 196 => note <= "000100011100111";
when 197 => note <= "000000101111001";
when 198 => note <= "111011000011101";
when 199 => note <= "110101011111110";
when 200 => note <= "110010001001010";
when 201 => note <= "110010100000010";
when 202 => note <= "110111000101101";
when 203 => note <= "111111010000111";
when 204 => note <= "001001011001111";
when 205 => note <= "010011010100001";
when 206 => note <= "011010110011010";
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when 11966 => note <= "011010110011010";
when 11967 => note <= "011110010000011";
when 11968 => note <= "011101000100110";
when 11969 => note <= "010111110011011";
when 11970 => note <= "010000000000000";
when 11971 => note <= "000111110011011";
when 11972 => note <= "000001010111001";
when 11973 => note <= "111110010000011";
when 11974 => note <= "111111000101101";
when 11975 => note <= "000011010100001";
when 11976 => note <= "001001011001111";
when 11977 => note <= "001111010000111";
when 11978 => note <= "010010110011010";
when 11979 => note <= "010010100000010";
when 11980 => note <= "001101110110110";
when 11981 => note <= "000101011111110";
when 11982 => note <= "111011000011101";
when 11983 => note <= "110000101111001";
when 11984 => note <= "101000101111010";
when 11985 => note <= "100100101011111";
when 11986 => note <= "100101001100110";
when 11987 => note <= "101001101111101";
when 11988 => note <= "110000110010001";
when 11989 => note <= "111000001100101";
when 11990 => note <= "111101110110110";
when 11991 => note <= "000000001100101";
when 11992 => note <= "111110101000111";
when 11993 => note <= "111001101111101";
when 11994 => note <= "110011000011101";
when 11995 => note <= "101100101011111";
when 11996 => note <= "101000101111010";
when 11997 => note <= "101000101111001";
when 11998 => note <= "101101001100110";
when others => note <= "110101011111110";
end case;
nv <= '1';
noteidx <= (noteidx + 1) when (signed(resize(noteidx, 15)) < (Nsmp - 1)) else to_unsigned(0, 14);
else
sample_rate_cnt <= (sample_rate_cnt + 1);
nv <= '0';
end if;
end if;
end process M_MUSICBOX_RTL;
end architecture MyHDL;
| mit | a8cf76f18dba9df47fb179629b04e0bd | 0.483067 | 5.141081 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/core.vhd | 2 | 4,787 | ----------------------------------------------------------------------------------------------
--
-- Input file : core.vhd
-- Design name : core
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Top level entity of the integer unit
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
entity core is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
imem_o : out imem_out_type;
dmem_o : out dmem_out_type;
imem_i : in imem_in_type;
dmem_i : in dmem_in_type;
int_i : in std_logic;
int_o : out std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end core;
architecture arch of core is
signal fetch_i : fetch_in_type;
signal fetch_o : fetch_out_type;
signal decode_i : decode_in_type;
signal decode_o : decode_out_type;
signal gprf_o : gprf_out_type;
signal exec_i : execute_in_type;
signal exec_o : execute_out_type;
signal mem_i : mem_in_type;
signal mem_o : mem_out_type;
signal ena_i : std_logic;
-- signal fetch_ena_i : std_logic;
-- signal rest_ena_i : std_logic;
begin
-- fetch_ena_i <= dmem_i.ena_i;
-- rest_ena_i <= dmem_i.ena_i and fetch_o.inst_valid;
ena_i <= dmem_i.ena_i and imem_i.ena_i;
fetch_i.hazard <= decode_o.hazard;
fetch_i.branch <= exec_o.branch;
fetch_i.branch_target <= exec_o.alu_result(CFG_IMEM_SIZE - 1 downto 0);
fetch0 : fetch port map
(
fetch_o => fetch_o,
imem_o => imem_o,
fetch_i => fetch_i,
imem_i => imem_i,
rst_i => rst_i,
ena_i => ena_i,
clk_i => clk_i
);
decode_i.program_counter <= fetch_o.program_counter;
decode_i.instruction <= fetch_o.instruction;
decode_i.inst_valid <= fetch_o.inst_valid;
decode_i.ctrl_wrb <= mem_o.ctrl_wrb;
decode_i.ctrl_mem_wrb <= mem_o.ctrl_mem_wrb;
decode_i.mem_result <= dmem_i.dat_i;
decode_i.alu_result <= mem_o.alu_result;
decode_i.interrupt <= int_i;
decode_i.interrupt_enable <= exec_o.interrupt_enable;
decode_i.flush_id <= exec_o.flush_id;
int_o <= decode_o.int_ack;
decode0: decode generic map
(
G_INTERRUPT => G_INTERRUPT,
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL,
G_DEBUG => G_DEBUG
)
port map
(
decode_o => decode_o,
decode_i => decode_i,
gprf_o => gprf_o,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
exec_i.fwd_dec <= decode_o.fwd_dec;
exec_i.fwd_dec_result <= decode_o.fwd_dec_result;
exec_i.dat_a <= gprf_o.dat_a_o;
exec_i.dat_b <= gprf_o.dat_b_o;
exec_i.dat_d <= gprf_o.dat_d_o;
exec_i.reg_a <= decode_o.reg_a;
exec_i.reg_b <= decode_o.reg_b;
exec_i.imm <= decode_o.imm;
exec_i.program_counter <= decode_o.program_counter;
exec_i.ctrl_wrb <= decode_o.ctrl_wrb;
exec_i.ctrl_mem <= decode_o.ctrl_mem;
exec_i.ctrl_ex <= decode_o.ctrl_ex;
exec_i.fwd_mem <= mem_o.ctrl_wrb;
exec_i.mem_result <= dmem_i.dat_i;
exec_i.alu_result <= mem_o.alu_result;
exec_i.ctrl_mem_wrb <= mem_o.ctrl_mem_wrb;
execute0 : execute generic map
(
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL
)
port map
(
exec_o => exec_o,
exec_i => exec_i,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
mem_i.alu_result <= exec_o.alu_result;
mem_i.program_counter <= exec_o.program_counter;
mem_i.branch <= exec_o.branch;
mem_i.dat_d <= exec_o.dat_d;
mem_i.ctrl_wrb <= exec_o.ctrl_wrb;
mem_i.ctrl_mem <= exec_o.ctrl_mem;
mem_i.mem_result <= dmem_i.dat_i;
mem0 : mem port map
(
mem_o => mem_o,
dmem_o => dmem_o,
mem_i => mem_i,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
end arch;
| gpl-3.0 | 865600d36dcd7be84aa5cee53ff4dcd3 | 0.490077 | 3.078457 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/all_carts_v4.vhd | 1 | 39,605 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity all_carts_v4 is
generic (
g_kernal_base : std_logic_vector(27 downto 0) := X"0EC8000"; -- multiple of 32K
g_rom_base : std_logic_vector(27 downto 0) := X"0F00000"; -- multiple of 1M
g_georam_base : std_logic_vector(27 downto 0) := X"1000000"; -- Shared with reu
g_ram_base : std_logic_vector(27 downto 0) := X"0EF0000" ); -- multiple of 64K
port (
clock : in std_logic;
reset : in std_logic;
RST_in : in std_logic;
c64_reset : in std_logic;
kernal_enable : in std_logic;
kernal_16k : in std_logic;
kernal_area : in std_logic;
freeze_trig : in std_logic; -- goes '1' when the button has been pressed and we're waiting to enter the freezer
freeze_act : in std_logic; -- goes '1' when we need to switch in the cartridge for freeze mode
unfreeze : out std_logic; -- indicates the freeze logic to switch back to non-freeze mode.
cart_active : out std_logic; -- indicates that the cartridge is active
cart_kill : in std_logic;
cart_logic : in std_logic_vector(4 downto 0); -- 1 out of 32 logic emulations
cart_force : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp := c_slot_resp_init;
epyx_timeout : in std_logic;
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
mem_addr : out unsigned(25 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
sense : in std_logic;
CART_LEDn : out std_logic;
size_ctrl : in std_logic_vector(2 downto 0) := "001" );
end all_carts_v4;
architecture gideon of all_carts_v4 is
signal reset_in : std_logic;
signal ext_bank : std_logic_vector(18 downto 16);
signal bank_bits : std_logic_vector(15 downto 13);
signal mode_bits : std_logic_vector(2 downto 0);
signal ef_write : std_logic_vector(2 downto 0);
signal ef_write_addr : std_logic_vector(21 downto 0);
signal georam_bank : std_logic_vector(15 downto 0);
-- signal rom_enable : std_logic;
signal freeze_act_d : std_logic;
signal cart_en : std_logic;
signal do_io2 : std_logic;
signal allow_bank : std_logic;
signal hold_nmi : std_logic;
signal cart_logic_d : std_logic_vector(cart_logic'range) := (others => '0');
signal mem_addr_i : std_logic_vector(27 downto 0);
constant c_none : std_logic_vector(4 downto 0) := "00000";
constant c_8k : std_logic_vector(4 downto 0) := "00001";
constant c_16k : std_logic_vector(4 downto 0) := "00010";
constant c_16k_umax : std_logic_vector(4 downto 0) := "00011";
constant c_fc3 : std_logic_vector(4 downto 0) := "00100";
constant c_ss5 : std_logic_vector(4 downto 0) := "00101";
constant c_retro : std_logic_vector(4 downto 0) := "00110";
constant c_action : std_logic_vector(4 downto 0) := "00111";
constant c_system3 : std_logic_vector(4 downto 0) := "01000";
constant c_domark : std_logic_vector(4 downto 0) := "01001";
constant c_ocean128 : std_logic_vector(4 downto 0) := "01010";
constant c_ocean256 : std_logic_vector(4 downto 0) := "01011";
constant c_easy_flash : std_logic_vector(4 downto 0) := "01100";
constant c_epyx : std_logic_vector(4 downto 0) := "01110";
constant c_kcs : std_logic_vector(4 downto 0) := "10000";
constant c_fc : std_logic_vector(4 downto 0) := "10001";
constant c_comal80 : std_logic_vector(4 downto 0) := "10010";
constant c_sbasic : std_logic_vector(4 downto 0) := "10011";
constant c_westermann : std_logic_vector(4 downto 0) := "10100";
constant c_georam : std_logic_vector(4 downto 0) := "10101";
constant c_bbasic : std_logic_vector(4 downto 0) := "10110";
constant c_pagefox : std_logic_vector(4 downto 0) := "10111";
constant c_128 : std_logic_vector(4 downto 0) := "11000";
constant c_fc3plus : std_logic_vector(4 downto 0) := "11001";
constant c_comal80pakma : std_logic_vector(4 downto 0) := "11010";
constant c_supergames : std_logic_vector(4 downto 0) := "11011";
constant c_nordic : std_logic_vector(4 downto 0) := "11100";
constant c_serve_rom_rr : std_logic_vector(0 to 7) := "11011111";
constant c_serve_io_rr : std_logic_vector(0 to 7) := "10101111";
-- alias
signal slot_addr : std_logic_vector(15 downto 0);
signal slot_rwn : std_logic;
signal io_read : std_logic;
signal io_write : std_logic;
signal io_addr : std_logic_vector(8 downto 0);
signal io_wdata : std_logic_vector(7 downto 0);
signal georam_mask : std_logic_vector(15 downto 0);
begin
with size_ctrl select georam_mask <=
"0000000111111111" when "000",
"0000001111111111" when "001",
"0000011111111111" when "010",
"0000111111111111" when "011",
"0001111111111111" when "100",
"0011111111111111" when "101",
"0111111111111111" when "110",
"1111111111111111" when others;
serve_enable <= cart_en or kernal_enable;
cart_active <= cart_en;
slot_addr <= std_logic_vector(slot_req.bus_address);
slot_rwn <= slot_req.bus_rwn;
io_write <= slot_req.io_write;
io_read <= slot_req.io_read;
io_addr <= std_logic_vector(slot_req.io_address(8 downto 0));
io_wdata <= slot_req.data;
process(clock)
begin
if rising_edge(clock) then
reset_in <= reset or RST_in or c64_reset;
freeze_act_d <= freeze_act;
unfreeze <= '0';
-- control register
if reset_in='1' then
cart_logic_d <= cart_logic; -- activate change of mode!
mode_bits <= (others => '0');
bank_bits <= (others => '0');
ext_bank <= (others => '0');
georam_bank <= (others => '0');
ef_write <= (others => '0');
ef_write_addr <= (others => '0');
allow_bank <= '0';
do_io2 <= '1';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '0';
elsif freeze_act='1' and freeze_act_d='0' then
bank_bits <= (others => '0');
mode_bits <= (others => '0');
--allow_bank <= '0';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '1';
elsif cart_en = '0' then
cart_logic_d <= cart_logic; -- activate change of mode!
end if;
if cart_force = '1' then
cart_logic_d <= cart_logic; -- activate change of mode!
end if;
serve_vic <= '0';
case cart_logic_d is
when c_fc3 =>
-- unfreeze <= '0';
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
bank_bits <= io_wdata(1 downto 0) & '0';
mode_bits <= '0' & io_wdata(4) & io_wdata(5);
unfreeze <= '1';
cart_en <= not io_wdata(7);
hold_nmi <= not io_wdata(6);
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
else
game_n <= mode_bits(0);
exrom_n <= mode_bits(1);
end if;
if mode_bits(1 downto 0)="10" then
serve_vic <= '1';
end if;
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
irq_n <= '1';
nmi_n <= not(freeze_trig or freeze_act or hold_nmi);
when c_fc3plus =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
bank_bits <= io_wdata(1 downto 0) & '0';
ext_bank <= '0' & io_wdata(3 downto 2);
mode_bits <= '0' & io_wdata(4) & io_wdata(5);
unfreeze <= '1';
cart_en <= not io_wdata(7);
hold_nmi <= not io_wdata(6);
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
else
game_n <= mode_bits(0);
exrom_n <= mode_bits(1);
end if;
if mode_bits(1 downto 0)="10" then
serve_vic <= '1';
end if;
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
irq_n <= '1';
nmi_n <= not(freeze_trig or freeze_act or hold_nmi);
when c_action =>
if io_write='1' and io_addr(8) = '0' and cart_en='1' then
bank_bits <= io_wdata(7) & io_wdata(4 downto 3);
mode_bits <= io_wdata(5) & io_wdata(1 downto 0);
unfreeze <= io_wdata(6);
cart_en <= not io_wdata(2);
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
else
game_n <= not mode_bits(0);
exrom_n <= mode_bits(1);
serve_io1 <= c_serve_io_rr(to_integer(unsigned(mode_bits)));
serve_io2 <= c_serve_io_rr(to_integer(unsigned(mode_bits))) and do_io2;
serve_rom <= c_serve_rom_rr(to_integer(unsigned(mode_bits)));
end if;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_retro =>
if io_write='1' and io_addr(8 downto 1) = X"00" and cart_en='1' then -- DE00/DE01
if io_addr(0)='0' then
bank_bits <= io_wdata(7) & io_wdata(4 downto 3);
mode_bits <= io_wdata(5) & io_wdata(1 downto 0);
unfreeze <= io_wdata(6);
cart_en <= not io_wdata(2);
else
if io_wdata(6)='1' then
do_io2 <= '0';
end if;
if io_wdata(1)='1' then
allow_bank <= '1';
end if;
end if;
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
else
game_n <= not mode_bits(0);
exrom_n <= mode_bits(1);
serve_io1 <= c_serve_io_rr(to_integer(unsigned(mode_bits)));
serve_io2 <= c_serve_io_rr(to_integer(unsigned(mode_bits))) and do_io2;
serve_rom <= c_serve_rom_rr(to_integer(unsigned(mode_bits)));
end if;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_nordic =>
if io_write='1' and io_addr(8) = '0' and cart_en='1' then
bank_bits <= io_wdata(7) & io_wdata(4 downto 3);
mode_bits <= io_wdata(5) & io_wdata(1 downto 0);
unfreeze <= io_wdata(6);
cart_en <= not io_wdata(2);
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
else
if mode_bits(2 downto 0)="110" then
game_n <= '0';
-- Switch to Ultimax mode for writes to address A000-BFFF (disable C64 RAM write)
exrom_n <= slot_addr(15) and not slot_addr(14) and slot_addr(13) and not slot_rwn;
else
game_n <= not mode_bits(0);
exrom_n <= mode_bits(1);
end if;
serve_io1 <= c_serve_io_rr(to_integer(unsigned(mode_bits)));
serve_io2 <= c_serve_io_rr(to_integer(unsigned(mode_bits))) and do_io2;
serve_rom <= c_serve_rom_rr(to_integer(unsigned(mode_bits)));
end if;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_easy_flash =>
if io_write='1' and io_addr(8)='0' and cart_en='1' then -- DExx
if io_addr(3 downto 0)="0000" then -- DE00
ext_bank <= io_wdata(5 downto 3);
bank_bits <= io_wdata(2 downto 0);
end if;
if io_addr(3 downto 0)="0010" then -- DE02
mode_bits <= io_wdata(2 downto 0); -- LED not implemented
end if;
if io_addr(3 downto 0)="1001" then -- DE09
ef_write <= "000";
end if;
if io_addr(3 downto 0)="1000" then -- DE08
case ef_write is
when "000" =>
if io_wdata(7 downto 0) = X"65" then
ef_write <= "001";
end if;
when "001" =>
if io_wdata(7 downto 0) = X"66" then
ef_write <= "010";
else
ef_write <= "000";
end if;
when "010" =>
if io_wdata(7 downto 0) = X"77" then
ef_write <= "011";
else
ef_write <= "000";
end if;
when "011" =>
ef_write_addr(7 downto 0) <= io_wdata(7 downto 0);
ef_write <= "100";
when "100" =>
ef_write_addr(12 downto 8) <= io_wdata(4 downto 0);
ef_write_addr(19) <= io_wdata(5);
ef_write <= "101";
when "101" =>
ef_write_addr(18 downto 13) <= io_wdata(5 downto 0);
ef_write <= "110";
when others =>
ef_write <= "000";
end case;
end if;
end if;
game_n <= not (mode_bits(0) or not mode_bits(2));
exrom_n <= not mode_bits(1);
serve_rom <= '1';
serve_io1 <= '1'; -- write registers only, no reads
serve_io2 <= '1'; -- RAM
irq_n <= '1';
nmi_n <= '1';
when c_ss5 =>
if io_write='1' and io_addr(8) = '0' and cart_en='1' then -- DE00-DEFF
bank_bits <= io_wdata(4) & io_wdata(2) & '0';
mode_bits <= io_wdata(3) & io_wdata(1) & io_wdata(0);
unfreeze <= not io_wdata(0);
cart_en <= not io_wdata(3);
end if;
game_n <= mode_bits(0);
exrom_n <= not mode_bits(1);
serve_io1 <= cart_en;
serve_io2 <= '0';
serve_rom <= cart_en;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_8k =>
if io_write='1' and io_addr(8 downto 0) = "111111111" then -- DFFF
if cart_en='1' and io_wdata(7 downto 6) = "01" then
cart_en <= '0'; -- permanent off
end if;
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- for EPYX test
irq_n <= '1';
nmi_n <= '1';
when c_16k =>
if io_write='1' and io_addr(8 downto 0) = "111111111" then -- DFFF
if cart_en='1' and io_wdata(7 downto 6) = "01" then
cart_en <= '0'; -- permanent off
end if;
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_16k_umax =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' and io_wdata(7 downto 6) = "01" then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_vic <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_128 =>
game_n <= '1';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
irq_n <= '1';
nmi_n <= '1';
serve_vic <= '1';
when c_ocean128 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= io_wdata(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_domark =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= '0' & io_wdata(4 downto 3);
mode_bits(0) <= io_wdata(7);
-- if io_wdata(7 downto 5) /= "000" then -- permanent off
-- cart_en <= '0';
-- end if;
cart_en <= not (io_wdata(7) or io_wdata(6) or io_wdata(5));
end if;
game_n <= '1';
exrom_n <= mode_bits(0);
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean256 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= "00" & io_wdata(3);
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_system3 => -- 16K, only 8K used?
if (io_write='1' or io_read='1') and io_addr(8)='0' then -- DE00 range
bank_bits <= io_addr(2 downto 0);
ext_bank <= io_addr(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_comal80 => -- 64K, 4x16K banks
if io_write='1' and io_addr(8)='0' then -- DE00-DEFF
bank_bits <= io_wdata(1 downto 0) & '0';
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_comal80pakma =>
if io_write='1' and io_addr(8)='0' then -- DE00-DEFF
bank_bits <= io_wdata(1 downto 0) & '0';
ext_bank <= "00" & io_wdata(2);
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_supergames =>
if io_write='1' and io_addr(8)='1' and mode_bits(1) = '0' then -- DF00-DFFF
bank_bits <= io_wdata(1 downto 0) & '0';
mode_bits(1 downto 0) <= io_wdata(3 downto 2);
end if;
if mode_bits(1 downto 0) = "11" then -- Mostly to visualize
cart_en <= '0';
end if;
game_n <= mode_bits(0);
exrom_n <= mode_bits(0);
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_sbasic => -- 16K, upper 8k enabled by writing to DExx
-- and disabled by reading
if io_write='1' and io_addr(8)='0' then
mode_bits(0) <= '1';
elsif io_read='1' and io_addr(8)='0' then
mode_bits(0) <= '0';
end if;
game_n <= not mode_bits(0);
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_westermann => -- 16K, upper 8k disabled by reading to DFxx
-- and disabled by reading
if io_read='1' and io_addr(8)='1' then
mode_bits(0) <= '1';
end if;
game_n <= mode_bits(0);
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_pagefox => -- 16K, upper 8k disabled by reading to DFxx
-- and disabled by reading
if io_write='1' and io_addr(8 downto 7) = "01" then
mode_bits(0) <= io_wdata(4);
bank_bits <= io_wdata(3 downto 1);
end if;
game_n <= mode_bits(0);
exrom_n <= mode_bits(0);
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_georam =>
if io_write='1' and io_addr(8 downto 7) = "11" then
if io_addr(0) = '0' then
georam_bank(5 downto 0) <= io_wdata(5 downto 0) and georam_mask(5 downto 0);
georam_bank(15 downto 14) <= io_wdata(7 downto 6) and georam_mask(15 downto 14);
else
georam_bank(13 downto 6) <= io_wdata(7 downto 0) and georam_mask(13 downto 6);
end if;
end if;
game_n <= '1';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
irq_n <= '1';
nmi_n <= '1';
when c_bbasic =>
if io_write='1' and io_addr(8)='0' then
mode_bits(0) <= '0';
elsif io_read='1' and io_addr(8)='0' then
mode_bits(0) <= '1';
end if;
if mode_bits(0)='1' then
game_n <= '0';
exrom_n <= '0';
elsif slot_addr(15)='1' and not(slot_addr(14 downto 13) = "10") then
game_n <= '0';
exrom_n <= '1';
else
game_n <= '1';
exrom_n <= '1';
end if;
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_epyx =>
game_n <= '1';
exrom_n <= epyx_timeout;
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- rom visible df00-dfff
irq_n <= '1';
nmi_n <= '1';
when c_kcs =>
-- M1 M0 Ga Act | M1 M0 Ex Ga | M2 M1 M0 Recoded
---------------------+--------------------------+-----------------
-- x x x Reset | 0 0 0 0 (reset:16K) | 0 0 0 16K
-- x x x Freeze | 1 1 1 0 (freeze) | 0 1 0 UmaxF
-- x x x R:DE00 | 1 0 0 1 (8K mode) | 0 0 1 8K
-- x x x R:DE02 | 1 0 1 1 (off1) | 0 1 1 Off1
-- x x x W:DE80 | 0 0 0 0 (reset:16K) | 0 0 0 16K
-- 0 x 0 W:DE0x | 0 1 1 0 (Ultimax) | 1 1 0 UmaxS
-- 0 x 1 W:DE0x | 0 1 1 1 (Off2) | 1 1 1 Off2
-- 1 1 x W:DE00 | 0 0 0 0 (reset:16K) | 0 0 0 16K
-- 1 1 x W:DE02 | 1 0 0 1 (8K mode) | 0 0 1 8K
--
-- 0 0 0 0 16K
-- 0 1 0 0 ?
-- 0 0 1 0 ?
-- 0 1 1 0 Ultimax
--
-- 0 0 0 1 ?
-- 0 1 0 1 ?
-- 0 0 1 1 ?
-- 0 1 1 1 Off2
-- mode_bit(0) -> ULTIMAX
-- mode_bit(1) -> 16K Mode
-- io1 read
if io_read='1' and io_addr(8) = '0' then -- DE00-DEFF
mode_bits(0) <= '1'; -- When read and addr bit 1=0 : 8k GAME mode
mode_bits(1) <= io_addr(1); -- When read and addr bit 1=1 : Cartridge disabled mode
mode_bits(2) <= '0';
end if;
-- io1 write
if io_write='1' and io_addr(8 downto 7) = "01" then -- DE80-DEFF
mode_bits <= "000"; -- 16K mode
end if;
if io_write='1' and io_addr(8 downto 7) = "00" then -- DE00-DE7F
-- if in 16K 000 / UmaxS 110 / Off2 111
if mode_bits = "000" then -- 16K
mode_bits <= "110";
elsif mode_bits = "010" or mode_bits = "111" then -- Freeze of Off2
mode_bits <= "000"; -- When addr bit 1=0 : 16k GAME mode
mode_bits(0) <= io_addr(1); -- When addr bit 1=1 : 8k GAME mode
end if;
end if;
-- io2 read
if io_read='1' and io_addr(8 downto 7) = "11" then -- DF80-DFFF
unfreeze <= '1'; -- When read : release freeze
end if;
-- on freeze
if freeze_act='1' then
mode_bits <= "010";
end if;
game_n <= mode_bits(0);
exrom_n <= mode_bits(1);
serve_io1 <= '1';
serve_io2 <= '1';
serve_rom <= '1';
serve_vic <= mode_bits(1);
nmi_n <= not(freeze_trig or freeze_act);
when c_fc =>
-- io1 access
if io_read='1' and io_addr(8) = '0' then -- DE00-DEFF
game_n <= '1'; -- Cartridge disabled mode
exrom_n <= '1';
unfreeze <= '1';
end if;
if io_write='1' and io_addr(8) = '0' then -- DE00-DEFF
game_n <= '1'; -- Cartridge disabled mode
exrom_n <= '1';
unfreeze <= '1';
end if;
-- io2 access
if io_read='1' and io_addr(8) = '1' then -- DF00-DFFF
game_n <= '0'; -- 16K GAME mode
exrom_n <= '0';
unfreeze <= '1';
end if;
if io_write='1' and io_addr(8) = '1' then -- DF00-DFFF
game_n <= '0'; -- 16K GAME mode
exrom_n <= '0';
unfreeze <= '1';
end if;
-- on freeze
if freeze_trig='1' then
game_n <= '0'; -- ULTIMAX mode
exrom_n <= '1';
end if;
-- on reset/init
if reset_in='1' then
game_n <= '0'; -- 16K GAME mode
exrom_n <= '0';
unfreeze <= '1';
end if;
serve_io1 <= '1';
serve_io2 <= '1';
serve_rom <= '1';
nmi_n <= not(freeze_trig or freeze_act);
when others =>
game_n <= '1';
exrom_n <= '1';
serve_rom <= '0';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
end case;
if cart_kill='1' then
cart_en <= '0';
hold_nmi <= '0';
end if;
end if;
end process;
CART_LEDn <= not cart_en;
-- determine address
process(cart_logic_d, slot_addr, mode_bits, bank_bits, ext_bank, do_io2, allow_bank,
kernal_area, kernal_16k, georam_bank, sense, ef_write, ef_write_addr)
begin
mem_addr_i <= g_rom_base;
-- defaults
-- 64K, 8K banks, no writes
mem_addr_i(15 downto 0) <= bank_bits(15 downto 13) & slot_addr(12 downto 0);
allow_write <= '0';
case cart_logic_d is
when c_retro =>
-- 64K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 16) & bank_bits(15 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 16) & "000" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then--and mode_bits(1 downto 0)/="10" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_action =>
-- 8K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 15) & "00" & slot_addr(12 downto 0);
end if;
if slot_addr(15 downto 13)="100" then -- and mode_bits(1 downto 0)="11" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_nordic =>
-- 8K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 15) & "00" & slot_addr(12 downto 0);
end if;
if slot_addr(15 downto 13)="100" then -- and mode_bits(1 downto 0)="11" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
if mode_bits(2 downto 0) ="110" then
if slot_addr(15 downto 13)="100" then
mem_addr_i <= g_rom_base(27 downto 15) & bank_bits(14 downto 13) & slot_addr(12 downto 0);
allow_write <= '0';
end if;
if slot_addr(15 downto 13)="101" then
mem_addr_i <= g_ram_base(27 downto 15) & "00" & slot_addr(12 downto 0);
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
mem_addr_i <= g_ram_base(27 downto 15) & "00" & slot_addr(12 downto 0);
end if;
end if;
when c_easy_flash =>
-- Little RAM
if slot_addr(15 downto 8)=X"DF" then
mem_addr_i <= g_ram_base(27 downto 8) & slot_addr(7 downto 0);
allow_write <= '1';
else
if slot_addr(15 downto 0)=X"DE07" and ef_write = "110" then
mem_addr_i <= g_rom_base(27 downto 20) & ef_write_addr(19 downto 0);
allow_write <= '1';
else
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
end if;
end if;
when c_fc3 | c_comal80 | c_fc3plus | c_comal80pakma | c_supergames =>
mem_addr_i(17 downto 0) <= ext_bank(17 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0); -- 16K banks
when c_ss5 =>
if mode_bits(1 downto 0)="00" then
if slot_addr(15 downto 13)="100" then
allow_write <= '1';
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(15 downto 14) & slot_addr(12 downto 0);
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
when c_8k | c_epyx =>
mem_addr_i(27 downto 13) <= g_rom_base(27 downto 13);
mem_addr_i(12 downto 0) <= slot_addr(12 downto 0);
when c_16k | c_16k_umax =>
mem_addr_i(27 downto 14) <= g_rom_base(27 downto 14);
mem_addr_i(13 downto 0) <= slot_addr(13 downto 0);
when c_128 =>
mem_addr_i(27 downto 15) <= g_rom_base(27 downto 15);
mem_addr_i(14 downto 0) <= slot_addr(14 downto 0);
when c_ocean128 | c_system3 | c_domark | c_ocean256 =>
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
-- when c_ocean256 =>
-- mem_addr_i(18 downto 0) <= ext_bank & bank_bits & slot_addr(12 downto 0);
-- mem_addr_i(19) <= slot_addr(13); -- map banks 16-31 to $A000. (second 128K)
when c_kcs =>
-- io2 ram access
if slot_addr(15 downto 8) = X"DF" then
mem_addr_i <= g_ram_base(27 downto 7) & slot_addr(6 downto 0);
allow_write <= '1';
else
-- rom access
mem_addr_i <= g_rom_base(27 downto 14) & slot_addr(13 downto 0);
end if;
when c_fc | c_westermann =>
-- rom access
mem_addr_i <= g_rom_base(27 downto 14) & slot_addr(13 downto 0);
when c_sbasic =>
-- rom access
mem_addr_i <= g_rom_base(27 downto 13) & slot_addr(12 downto 0);
mem_addr_i(19) <= slot_addr(13);
when c_bbasic =>
-- rom access
if slot_addr(15 downto 13)="100" then
mem_addr_i <= g_rom_base(27 downto 15) & "00" & slot_addr(12 downto 0);
elsif slot_addr(15 downto 13)="101" then
mem_addr_i <= g_rom_base(27 downto 15) & "01" & slot_addr(12 downto 0);
elsif slot_addr(15 downto 13)="111" then
mem_addr_i <= g_rom_base(27 downto 15) & "10" & slot_addr(12 downto 0);
end if;
when c_georam =>
if slot_addr(15 downto 8)=X"DE" then
mem_addr_i <= g_georam_base(27 downto 24) & georam_bank(15 downto 0) & slot_addr(7 downto 0);
allow_write <= '1';
end if;
when c_pagefox =>
if bank_bits(15) = '0' then
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(14) & bank_bits(13) & slot_addr(13 downto 0);
elsif bank_bits(14) = '0' then
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(13) & slot_addr(13 downto 0);
if slot_addr(15 downto 14)="10" then
allow_write <= '1';
end if;
end if;
when others =>
null;
end case;
if kernal_area='1' then
if kernal_16k='0' then
mem_addr_i <= g_kernal_base(27 downto 14) & slot_addr(12 downto 0) & '0';
else
mem_addr_i <= g_rom_base(27 downto 15) & (not sense) & slot_addr(12 downto 0) & '0';
end if;
end if;
end process;
mem_addr <= unsigned(mem_addr_i(mem_addr'range));
slot_resp.data(7) <= bank_bits(15);
slot_resp.data(6) <= '1';
slot_resp.data(5) <= '0';
slot_resp.data(4) <= bank_bits(14);
slot_resp.data(3) <= bank_bits(13);
slot_resp.data(2) <= '0'; -- freeze button pressed
slot_resp.data(1) <= allow_bank; -- '1'; -- allow bank bit stuck at '1' for 1541U
slot_resp.data(0) <= '0';
slot_resp.reg_output <= '1' when (slot_addr(8 downto 1)="00000000") and (cart_logic_d = c_retro) else '0';
end gideon;
| gpl-3.0 | efc838ff7f88685b2fa4600cacef9a21 | 0.405252 | 3.629158 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/floppy_param_mem.vhd | 1 | 3,154 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Parameter memory
-------------------------------------------------------------------------------
-- File : floppy.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.endianness_pkg.all;
use work.io_bus_pkg.all;
entity floppy_param_mem is
generic (
g_big_endian : boolean );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
track : in unsigned(6 downto 0);
side : in std_logic := '0';
bit_time : out unsigned(9 downto 0);
track_start : out std_logic_vector(25 downto 0);
max_offset : out std_logic_vector(13 downto 0) );
end floppy_param_mem;
architecture gideon of floppy_param_mem is
signal toggle : std_logic;
signal param_addr : std_logic_vector(8 downto 0);
signal param_data : std_logic_vector(31 downto 0);
signal ram_data : std_logic_vector(31 downto 0);
signal cpu_ram_en : std_logic;
signal cpu_ram_en_d : std_logic;
signal cpu_rdata : std_logic_vector(7 downto 0);
begin
cpu_ram_en <= io_req.read or io_req.write;
cpu_ram_en_d <= cpu_ram_en when rising_edge(clock);
io_resp.ack <= cpu_ram_en_d;
io_resp.data <= cpu_rdata when cpu_ram_en_d = '1' else X"00";
ram: RAMB16_S9_S36
port map (
CLKA => clock,
SSRA => reset,
ENA => cpu_ram_en,
WEA => io_req.write,
ADDRA => std_logic_vector(io_req.address(10 downto 0)),
DIA => io_req.data,
DIPA => "0",
DOA => cpu_rdata,
DOPA => open,
CLKB => clock,
SSRB => reset,
ENB => '1',
WEB => '0',
ADDRB => param_addr,
DIB => X"00000000",
DIPB => X"0",
DOB => ram_data,
DOPB => open );
param_addr <= side & std_logic_vector(track) & toggle;
param_data <= byte_swap(ram_data, g_big_endian);
process(clock)
begin
if rising_edge(clock) then
if toggle='1' then -- even addresses (one clock later)
track_start <= param_data(track_start'range);
else
max_offset <= param_data(max_offset'range);
bit_time <= unsigned(param_data(bit_time'high+16 downto 16));
end if;
if reset='1' then
toggle <= '0';
else
toggle <= not toggle;
end if;
end if;
end process;
end gideon;
| gpl-3.0 | ef915655a5c1604ec0bf8f2bbac2bcc7 | 0.478123 | 3.688889 | false | false | false | false |
markusC64/1541ultimate2 | fpga/devices/vhdl_sim/amd_flash_tb.vhd | 1 | 4,544 | --------------------------------------------------------------------------------
-- Entity: amd_flash_tb
-- Date:2018-08-14
-- Author: gideon
--
-- Description: Testbench for EEPROM
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.tl_string_util_pkg.all;
entity amd_flash_tb is
end entity;
architecture test of amd_flash_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_irq : std_logic;
signal allow_write : std_logic;
signal address : unsigned(19 downto 0) := (others => '0');
signal wdata : std_logic_vector(7 downto 0) := X"00";
signal write : std_logic := '0';
signal read : std_logic := '0';
signal rdata : std_logic_vector(7 downto 0);
signal rdata_valid : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.amd_flash
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq,
allow_write => allow_write,
address => address(18 downto 0),
wdata => wdata,
write => write,
read => read,
rdata => rdata,
rdata_valid => rdata_valid
);
i_bfm: entity work.io_bus_bfm
generic map(
g_name => "io"
)
port map(
clock => clock,
req => io_req,
resp => io_resp
);
p_test: process
procedure wr(ad : unsigned(19 downto 0); data: std_logic_vector(7 downto 0)) is
begin
wait until clock = '1';
address <= ad;
wdata <= data;
wait for 100 ns;
wait until clock = '1';
write <= '1';
wait until clock = '1';
write <= '0';
end procedure;
procedure rd(ad : unsigned(19 downto 0); data: out std_logic_vector(7 downto 0)) is
begin
wait until clock = '1';
address <= ad;
wdata <= X"FF";
wait for 100 ns;
wait until clock = '1';
data := rdata;
read <= '1';
wait until clock = '1';
read <= '0';
end procedure;
variable d : std_logic_vector(7 downto 0);
variable io : p_io_bus_bfm_object;
begin
wait until reset = '0';
wait for 1 us;
bind_io_bus_bfm("io", io);
wr(X"05555", X"AA");
wr(X"02AAA", X"55");
wr(X"05555", X"90");
rd(X"00000", d);
report "Read: " & hstr(d);
wr(X"05555", X"AA");
wr(X"02AAA", X"55");
wr(X"05555", X"90");
rd(X"00001", d);
report "Read: " & hstr(d);
io_read(io, X"00000", d);
assert d = X"00" report "Expected no erase" severity error;
io_read(io, X"00001", d);
assert d = X"00" report "Expected no dirty" severity error;
wr(X"05555", X"AA");
wr(X"02AAA", X"55");
wr(X"05555", X"A0");
wr(X"01234", X"55");
io_read(io, X"00000", d);
assert d = X"00" report "Expected no erase" severity error;
io_read(io, X"00001", d);
assert d = X"01" report "Expected dirty" severity error;
wait for 50 ns;
wr(X"05555", X"AA");
wr(X"02AAA", X"55");
wr(X"05555", X"80");
wr(X"05555", X"AA");
wr(X"02AAA", X"55");
wr(X"10000", X"30");
io_read(io, X"00000", d);
assert d = X"02" report "Expected single erase" severity error;
wait for 50 ns;
rd(X"00000", d);
rd(X"00000", d);
rd(X"00000", d);
rd(X"00000", d);
io_write(io, X"00000", X"00");
io_read(io, X"00000", d);
assert d = X"00" report "Expected no erase" severity error;
rd(X"00000", d);
rd(X"00000", d);
wait for 50 ns;
wr(X"05555", X"AA");
wr(X"02AAA", X"55");
wr(X"05555", X"80");
wr(X"05555", X"AA");
wr(X"02AAA", X"55");
wr(X"05555", X"10");
io_read(io, X"00000", d);
assert d = X"FF" report "Expected full erase" severity error;
wait;
end process;
end architecture;
| gpl-3.0 | 5d2611334fde45f2d038267ccf4f45dc | 0.466109 | 3.432024 | false | false | false | false |
nussbrot/AdvPT | tpl/wb_reg_no_rst_notify.tpl.vhd | 2 | 7,030 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, %TPL_YEAR% All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project : %TPL_PROJECT%
-- File : %TPL_VHDLFILE%
-- Created : %TPL_DATE%
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--*
--* @short Wishbone register module
--* Auto-generated by '%TPL_SCRIPT%' based on '%TPL_TPLFILE%'
--*
--* Needed Libraries and Packages:
--* @li ieee.std_logic_1164 standard multi-value logic package
--* @li ieee.numeric_std
--*
--* @author %TPL_USER%
--* @date 30.06.2016
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- %TPL_DATE% %TPL_USER%: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
%TPL_LIBRARY%
-------------------------------------------------------------------------------
ENTITY %TPL_MODULE% IS
GENERIC (
g_addr_bits : INTEGER := %TPL_WBSIZE%);
PORT (
-- Wishbone interface
clk : IN STD_LOGIC;
i_wb_cyc : IN STD_LOGIC;
i_wb_stb : IN STD_LOGIC;
i_wb_we : IN STD_LOGIC;
i_wb_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wb_addr : IN STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
i_wb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_ack : OUT STD_LOGIC;
o_wb_rty : OUT STD_LOGIC;
o_wb_err : OUT STD_LOGIC;
-- Custom ports
%TPL_PORTS%
);
END ENTITY %TPL_MODULE%;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF %TPL_MODULE% IS
-----------------------------------------------------------------------------
-- Procedures
-----------------------------------------------------------------------------
%TPL_PROCEDURES%
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
%TPL_CONSTANTS%
-----------------------------------------------------------------------------
-- WB interface signals
-----------------------------------------------------------------------------
SIGNAL s_wb_ack : STD_LOGIC;
SIGNAL s_wb_err : STD_LOGIC;
SIGNAL s_wb_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_data : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_int_we : STD_LOGIC_VECTOR(i_wb_sel'RANGE);
SIGNAL s_int_trd : STD_LOGIC;
SIGNAL s_int_twr : STD_LOGIC;
SIGNAL s_int_addr_valid : STD_LOGIC;
SIGNAL s_int_data_rb : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_wb_data : STD_LOGIC_VECTOR(o_wb_data'RANGE);
TYPE t_wb_state IS (e_idle, e_delay, e_ack);
SIGNAL s_wb_state : t_wb_state := e_idle;
-----------------------------------------------------------------------------
-- Custom registers
-----------------------------------------------------------------------------
%TPL_REGISTER_SIGNALS%
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
--* purpose : Wishbone Bus Control
--* type : sequential, rising edge, no reset
wb_ctrl : PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
s_wb_ack <= '0';
s_wb_err <= '0';
s_int_data <= i_wb_data;
s_int_addr <= s_wb_addr;
s_int_we <= (OTHERS => '0');
s_int_trd <= '0';
s_int_twr <= '0';
CASE s_wb_state IS
WHEN e_idle =>
-- check if anyone requests access
IF (i_wb_cyc = '1' AND i_wb_stb = '1') THEN
-- ack is delayed because we need 3 cycles
IF (i_wb_we = '1') THEN
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
s_int_we <= i_wb_sel;
s_int_twr <= '1';
ELSE
IF c_has_read_notifies THEN
s_wb_state <= e_delay;
s_int_trd <= '1';
ELSE
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
END IF;
END IF;
END IF;
WHEN e_delay =>
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
WHEN e_ack =>
s_wb_state <= e_idle;
END CASE;
s_wb_data <= s_int_data_rb;
END IF;
END PROCESS wb_ctrl;
s_wb_addr <= UNSIGNED(i_wb_addr);
o_wb_data <= s_wb_data;
o_wb_ack <= s_wb_ack;
o_wb_err <= s_wb_err;
o_wb_rty <= '0';
-----------------------------------------------------------------------------
-- WB address validation
WITH to_integer(s_wb_addr) SELECT
s_int_addr_valid <=
%TPL_ADDR_VALIDATION%
'0' WHEN OTHERS;
-----------------------------------------------------------------------------
--* purpose : register access
--* type : sequential, rising edge, high active synchronous reset
reg_access : PROCESS (clk)
BEGIN -- PROCESS reg_access
IF rising_edge(clk) THEN
-- default values / clear trigger signals
%TPL_REG_DEFAULT%
-- WRITE registers
CASE to_integer(s_int_addr) IS
%TPL_SIG_WR%
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS reg_access;
-----------------------------------------------------------------------------
p_comb_read_mux : PROCESS(s_wb_addr, %TPL_SENS_LIST%)
%TPL_VAR_DEC%
-- helper to ease template generation
PROCEDURE set(
l_input : STD_LOGIC_VECTOR(31 DOWNTO 0);
l_mask : STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
BEGIN
s_int_data_rb <= l_input AND l_mask;
END PROCEDURE;
BEGIN
-- READ registers assignments
%TPL_VAR_RD%
-- WB output data multiplexer
CASE to_integer(s_wb_addr) IS
%TPL_CASE_OUT%
WHEN OTHERS => set((OTHERS => '0'), (OTHERS => '1'));
END CASE;
END PROCESS p_comb_read_mux;
-----------------------------------------------------------------------------
-- output mappings
%TPL_PORT_SIG_OUT%
END ARCHITECTURE rtl;
| mit | 8ff044e669cad9875afe4e71e74cecae | 0.423755 | 4.063584 | false | false | false | false |
xiadz/oscilloscope | src/single_debouncer.vhd | 1 | 1,068 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 15:03:57 05/24/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity single_debouncer is
generic (
n : natural := 5000
);
port (
nrst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic
);
end single_debouncer;
architecture behavioral of single_debouncer is
signal counter: natural range 0 to n := 0;
signal output2: std_logic := '0';
begin
output <= output2;
process (clk, nrst) is
begin
if nrst = '0' then
counter <= 0;
output2 <= '0';
elsif rising_edge (clk) then
if counter >= n then
if output2 /= input then
output2 <= input;
counter <= 0;
end if;
else
counter <= counter + 1;
end if;
end if;
end process;
end behavioral;
| mit | 67157e237656ee92aa476db1e39b9b01 | 0.476592 | 4.238095 | false | false | false | false |
armandas/Plong | vga_sync.vhd | 1 | 3,384 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga is
port(
clk, not_reset: in std_logic;
hsync, vsync: out std_logic;
video_on: out std_logic;
pixel_x, pixel_y: out std_logic_vector (9 downto 0)
);
end vga;
architecture sync of vga is
-- VGA 640x480 sync parameters
constant HD: integer := 640; -- horizontal display area
constant HF: integer := 16; -- h. front porch
constant HB: integer := 48; -- h. back porch
constant HR: integer := 96; -- h. retrace
constant VD: integer := 480; -- vertical display area
constant VF: integer := 11; -- v. front porch
constant VB: integer := 31; -- v. back porch
constant VR: integer := 2; -- v. retrace
-- mod-2 counter
signal mod2, mod2_next: std_logic;
-- sync counters
signal v_count, v_count_next: std_logic_vector(9 downto 0);
signal h_count, h_count_next: std_logic_vector(9 downto 0);
-- output buffer
signal v_sync, h_sync: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signal
signal h_end, v_end, pixel_tick: std_logic;
begin
process(clk, not_reset)
begin
if not_reset = '0' then
mod2 <= '0';
v_count <= (others => '0');
h_count <= (others => '0');
v_sync <= '0';
h_sync <= '0';
elsif clk'event and clk = '0' then
mod2 <= mod2_next;
v_count <= v_count_next;
h_count <= h_count_next;
v_sync <= v_sync_next;
h_sync <= h_sync_next;
end if;
end process;
-- mod-2 circuit to generate 25 MHz enable tick
mod2_next <= not mod2;
-- 25 MHz pixel tick
pixel_tick <= '1' when mod2 = '1' else '0';
-- end of counters (799 and 524 pixels)
h_end <= '1' when h_count = (HD + HF + HB + HR - 1) else '0';
v_end <= '1' when v_count = (VD + VF + VB + VR - 1) else '0';
-- mod-800 horizontal sync counter
process(h_count, h_end, pixel_tick)
begin
if pixel_tick = '1' then
if h_end = '1' then
h_count_next <= (others => '0');
else
h_count_next <= h_count + 1;
end if;
else
h_count_next <= h_count;
end if;
end process;
-- mod-524 vertical sync counter
process(v_count, h_end, v_end, pixel_tick)
begin
if pixel_tick = '1' and h_end = '1' then
if v_end = '1' then
v_count_next <= (others => '0');
else
v_count_next <= v_count + 1;
end if;
else
v_count_next <= v_count;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <= '1' when (h_count >= (HD + HF)) and
(h_count <= (HD + HF + HR - 1)) else
'0';
v_sync_next <= '1' when (v_count >= (VD + VF)) and
(v_count <= (VD + VF + VR - 1)) else
'0';
-- video on/off
video_on <= '1' when (h_count < HD) and (v_count < VD) else '0';
-- output signal
hsync <= h_sync;
vsync <= v_sync;
pixel_x <= h_count;
pixel_y <= v_count;
end sync;
| bsd-2-clause | 645841fb465665448f216c6e2501d1a0 | 0.495272 | 3.453061 | false | false | false | false |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_source/sid_mapper.vhd | 1 | 6,218 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_mapper is
port (
clock : in std_logic;
reset : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
control : in t_sid_control;
sid_addr : out unsigned(7 downto 0);
sid_wren : out std_logic;
sid_wdata : out std_logic_vector(7 downto 0);
sid_rdata : in std_logic_vector(7 downto 0) );
end sid_mapper;
architecture mapping of sid_mapper is
signal sid_wren_l : std_logic;
signal sid_wren_r : std_logic;
signal sid_wren_d : std_logic;
signal sid_addr_l : unsigned(7 downto 0);
signal sid_addr_r : unsigned(7 downto 0);
signal sid_addr_d : unsigned(7 downto 0);
signal sid_wdata_l : std_logic_vector(7 downto 0);
signal sid_wdata_d : std_logic_vector(7 downto 0);
begin
slot_resp.data <= sid_rdata;
sid_wren <= sid_wren_l or sid_wren_d;
sid_addr <= sid_addr_d when sid_wren_d='1' else sid_addr_l;
sid_wdata <= sid_wdata_l; -- should work, but it's not neat!
process(clock)
begin
if rising_edge(clock) then
sid_wren_l <= '0';
sid_wren_r <= '0';
sid_wren_d <= sid_wren_r;
sid_addr_d <= sid_addr_r;
sid_wdata_l <= slot_req.data;
sid_wdata_d <= sid_wdata_l;
if slot_req.io_write='1' then
sid_addr_l <= slot_req.io_address(7 downto 0);
sid_addr_r <= slot_req.io_address(7 downto 0);
else
sid_addr_l <= slot_req.bus_address(7 downto 0);
sid_addr_r <= slot_req.bus_address(7 downto 0);
end if;
-- check for left channel access
if control.enable_left='1' then
if slot_req.bus_write='1' then
if control.snoop_left='1' and slot_req.bus_address(15 downto 12)=X"D" then
if control.extend_left='1' then
if slot_req.bus_address(11 downto 7)=control.base_left(11 downto 7) then
sid_addr_l(7) <= '0';
sid_wren_l <= '1';
end if;
else -- just 3 voices
if slot_req.bus_address(11 downto 5)=control.base_left(11 downto 5) then
sid_wren_l <= '1';
sid_addr_l(7 downto 5) <= "000"; -- truncated address
end if;
end if;
end if;
elsif slot_req.io_write='1' then
if control.snoop_left='0' then
if control.extend_left='1' and slot_req.io_address(8 downto 7)=control.base_left(8 downto 7) then
sid_addr_l(7) <= '0';
sid_wren_l <= '1';
elsif control.extend_left='0' and slot_req.io_address(8 downto 5)=control.base_left(8 downto 5) then
sid_addr_l(7 downto 5) <= "000";
sid_wren_l <= '1';
end if;
end if;
end if;
end if;
-- check for right channel access
if control.enable_right='1' then
if slot_req.bus_write='1' then
if control.snoop_right='1' and slot_req.bus_address(15 downto 12)=X"D" then
if control.extend_right='1' then
if slot_req.bus_address(11 downto 7)=control.base_right(11 downto 7) then
sid_addr_r(7) <= '1';
sid_wren_r <= '1';
end if;
else -- just 3 voices
if slot_req.bus_address(11 downto 5)=control.base_right(11 downto 5) then
sid_wren_r <= '1';
sid_addr_r(7 downto 5) <= "100"; -- truncated address
end if;
end if;
end if;
elsif slot_req.io_write='1' then
if control.snoop_right='0' then
if control.extend_right='1' and slot_req.io_address(8 downto 7)=control.base_right(8 downto 7) then
sid_addr_r(7) <= '1';
sid_wren_r <= '1';
elsif control.extend_right='0' and slot_req.io_address(8 downto 5)=control.base_right(8 downto 5) then
sid_addr_r(7 downto 5) <= "100";
sid_wren_r <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
slot_resp.nmi <= '0';
slot_resp.irq <= '0';
slot_resp.reg_output <= '0';
end mapping;
-- Mapping options are as follows:
-- STD $D400-$D41F: Snoop='1' Base=$40. Extend='0' (bit 11...5 are significant)
-- STD $D500-$D51F: Snoop='1' Base=$50. Extend='0'
-- STD $DE00-$DE1F: Snoop='0' Base=$E0. Extend='0' (bit 8...5 are significant)
-- STD $DF00-$DF1F: Snoop='0' Base=$F0. Extend='0'
-- EXT $DF80-$DFFF: Snoop='0' Base=$F8. Extend='1' (bit 8...7 are significant)
-- EXT $D600-$D67F: Snoop='1' Base=$60. Extend='1' (bit 11..7 are significant)
-- .. etc
| gpl-3.0 | 60c32452a0cb347b2f701364f016ec3f | 0.456095 | 3.847772 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio/vhdl_sim/generic_mixer_tb.vhd | 1 | 2,935 | --------------------------------------------------------------------------------
-- Entity: generic_mixer_tb
-- Date:2018-08-02
-- Author: gideon
--
-- Description: Testbench for generic mixer
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.audio_type_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
entity generic_mixer_tb is
end entity;
architecture tb of generic_mixer_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal start : std_logic;
signal sys_clock : std_logic;
signal req : t_io_req;
signal resp : t_io_resp;
signal inputs : t_audio_array(0 to 7);
signal out_L : t_audio;
signal out_R : t_audio;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_gains : t_byte_array(0 to 15) := ( X"80", X"00",
X"00", X"80",
X"80", X"00",
X"00", X"80",
X"80", X"00",
X"00", X"80",
X"01", X"00",
X"00", X"80" );
begin
inputs <= ( 0 => to_signed(-5, 18),
1 => to_signed(6, 18),
2 => to_signed(-7, 18),
3 => to_signed(8, 18),
4 => to_signed(-9, 18),
5 => "011111111111111111",
6 => "100000000000000000",
7 => to_signed(12, 18) );
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.generic_mixer
generic map(
g_num_sources => inputs'length
)
port map(
clock => clock,
reset => reset,
start => start,
sys_clock => clock,
req => req,
resp => resp,
inputs => inputs,
out_L => out_L,
out_R => out_R
);
i_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bus"
)
port map(
clock => clock,
req => req,
resp => resp
);
p_test: process
variable io : p_io_bus_bfm_object;
begin
start <= '0';
wait for 1 ns;
bind_io_bus_bfm("io_bus", io);
wait until reset = '0';
for i in 0 to 15 loop
io_write(io, to_unsigned(i, 20), c_gains(i));
end loop;
wait until clock = '1';
start <= '1';
wait until clock = '1';
start <= '0';
wait;
end process;
end architecture;
| gpl-3.0 | 456930421fe558c7d34fa6de63886d80 | 0.39523 | 4.031593 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/vhdl_sim/mb_model_tb.vhd | 2 | 2,882 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mb_model_tb is
end entity;
architecture test of mb_model_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(31 downto 0);
signal io_write : std_logic;
signal io_read : std_logic;
signal io_byte_en : std_logic_vector(3 downto 0);
signal io_wdata : std_logic_vector(31 downto 0);
signal io_rdata : std_logic_vector(31 downto 0) := (others => 'Z');
signal io_ack : std_logic := '0';
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
model: entity work.mb_model
port map (
clock => clock,
reset => reset,
io_addr => io_addr,
io_byte_en=> io_byte_en,
io_write => io_write,
io_read => io_read,
io_wdata => io_wdata,
io_rdata => io_rdata,
io_ack => io_ack );
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
io_ack <= '0';
if io_write = '1' then
io_ack <= '1';
case io_addr(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := io_wdata(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(io_addr) & " dropped";
end case;
elsif io_read = '1' then
io_ack <= '1';
case io_addr(19 downto 0) is
when X"0000C" => -- Capabilities
io_rdata <= X"00000002";
when X"00012" => -- UART_FLAGS
io_rdata <= X"40404040";
when X"2000A" => -- 1541_A memmap
io_rdata <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
io_rdata <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(io_addr) & " dropped";
io_rdata <= X"00000000";
end case;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | c9b2a9e7841da2503edc420924e22460 | 0.459403 | 3.873656 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/cia_registers.vhd | 1 | 30,333 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cia_pkg.all;
-- synthesis translate_off
use work.tl_string_util_pkg.all;
-- synthesis translate_on
entity cia_registers is
generic (
g_unit_name : string := "6526";
g_report : boolean := false );
port (
clock : in std_logic;
falling : in std_logic;
reset : in std_logic;
addr : in unsigned(3 downto 0);
wen : in std_logic;
ren : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
turbo_en : in std_logic := '0';
wait_state : out std_logic;
-- PLD interface
pld_inhibit : in std_logic := '0';
pld_write : out std_logic;
pld_wdata : out std_logic_vector(7 downto 0);
pld_waddr : out std_logic;
pld_state : out std_logic_vector(15 downto 0);
-- pio --
port_a_o : out std_logic_vector(7 downto 0);
port_a_t : out std_logic_vector(7 downto 0);
port_a_i : in std_logic_vector(7 downto 0);
port_b_o : out std_logic_vector(7 downto 0);
port_b_t : out std_logic_vector(7 downto 0);
port_b_i : in std_logic_vector(7 downto 0);
-- serial pin
sp_o : out std_logic;
sp_i : in std_logic;
sp_t : out std_logic;
cnt_i : in std_logic;
cnt_o : out std_logic;
cnt_t : out std_logic;
tod_pin : in std_logic;
pc_o : out std_logic;
flag_i : in std_logic;
irq : out std_logic );
end cia_registers;
architecture Gideon of cia_registers is
signal pio_i : pio_t := pio_default;
signal timer_a_i : timer_t := timer_default;
signal timer_b_i : timer_t := timer_default;
signal tod_i : tod_t;
signal tod_copy : time_t;
signal tod_latch : std_logic;
signal tod_stop : std_logic;
signal tod_tick : std_logic;
signal irq_mask : std_logic_vector(4 downto 0);
signal irq_mask_r : std_logic_vector(4 downto 0);
signal irq_flags_r : std_logic_vector(4 downto 0);
signal irq_flags : std_logic_vector(4 downto 0);
signal irq_events : std_logic_vector(4 downto 0);
signal irq_out : std_logic;
signal irq_bit : std_logic;
signal irq_ack : std_logic;
signal irq_ack_d : std_logic := '0';
signal timer_a_reg : std_logic_vector(15 downto 0);
signal timer_a_in : std_logic_vector(15 downto 0);
signal timer_b_reg : std_logic_vector(15 downto 0);
signal timer_b_in : std_logic_vector(15 downto 0);
alias timer_a_evnt : std_logic is irq_events(0);
alias timer_b_evnt : std_logic is irq_events(1);
alias alarm_event : std_logic is irq_events(2);
alias serial_event : std_logic is irq_events(3);
alias flag_event : std_logic is irq_events(4);
signal timer_a_count : std_logic_vector(15 downto 0);
signal timer_b_count : std_logic_vector(15 downto 0);
signal timer_a_out : std_logic;
signal timer_b_out : std_logic;
signal timer_a_stop : std_logic;
signal timer_b_stop : std_logic;
signal timer_a_set_t : std_logic;
signal timer_b_set_t : std_logic;
signal cnt_out : std_logic;
signal sp_out : std_logic;
signal sr_buffer : std_logic_vector(7 downto 0);
signal spmode : std_logic;
signal flag_c : std_logic;
signal flag_d1 : std_logic;
signal flag_d2 : std_logic;
signal flag_d3 : std_logic;
signal ICR : std_logic_vector(7 downto 0);
signal cycle : natural := 0;
signal icr_modify : std_logic := '0';
signal pld_write_i : std_logic;
signal pld_wdata_i : std_logic_vector(7 downto 0);
signal pld_waddr_i : std_logic;
begin
irq <= irq_out;
process(clock)
variable v_data_out : std_logic_vector(7 downto 0);
variable flag_event_pre : std_logic := '0';
begin
if rising_edge(clock) then
if tod_latch='1' then
tod_copy <= tod_i.tod;
end if;
-- synthesis translate_off
if falling = '1' then
cycle <= cycle + 1;
end if;
-- synthesis translate_on
-- Interrupt logic
if falling = '1' then
-- by default ICR is not being modified
icr_modify <= '0';
-- keeping the mask register
irq_mask_r <= irq_mask;
-- keeping the flags in a register
irq_flags_r <= irq_flags;
if irq_ack = '1' then
irq_flags_r <= (others => '0');
end if;
if irq_ack_d = '1' then
irq_flags_r(1) <= '0'; -- Timer B fix
end if;
-- the actual IRQ output
if irq_ack = '1' then
irq_out <= '0';
elsif (irq_flags and irq_mask) /= "00000" then
irq_out <= '1';
end if;
irq_ack_d <= irq_ack;
-- the IRQ bit (MSB of ICR)
if (irq_flags and irq_mask) /= "00000" then
irq_bit <= '1';
elsif irq_ack = '1' or irq_ack_d = '1' then
irq_bit <= '0';
end if;
end if;
-- Time Of Day
if tod_tick='1' and falling='1' then
do_tod_tick(tod_i.tod);
end if;
-- PC output --
if falling='1' then
pc_o <= '1';
timer_a_i.load <= '0';
timer_b_i.load <= '0';
timer_a_reg <= timer_a_in;
timer_b_reg <= timer_b_in;
end if;
if timer_a_stop = '1' then timer_a_i.run <= '0'; end if;
if timer_b_stop = '1' then timer_b_i.run <= '0'; end if;
-- Writes --
if falling = '1' then
wait_state <= '0';
end if;
if wen='1' and falling = '1' then
-- synthesis translate_off
assert not g_report
report "Writing |" & g_unit_name & "| Reg |" & hstr(addr) & "| in cycle |" & integer'image(cycle) & "| to |" & hstr(data_in)
severity note;
-- synthesis translate_on
case addr is
when X"0" => -- PRA
pio_i.pra <= data_in;
when X"1" => -- PRB
pio_i.prb <= data_in;
pc_o <= '0';
when X"2" => -- DDRA
pio_i.ddra <= data_in;
when X"3" => -- DDRB
pio_i.ddrb <= data_in;
when X"4" => -- TA LO
when X"5" => -- TA HI
if timer_a_i.run = '0' then
timer_a_i.load <= '1';
end if;
when X"6" => -- TB LO
when X"7" => -- TB HI
if timer_b_i.run = '0' then
timer_b_i.load <= '1';
end if;
when X"8" => -- TOD 10ths
if tod_i.alarm_set='1' then
tod_i.alarm.tenths <= unsigned(data_in(3 downto 0));
else
tod_i.tod.tenths <= unsigned(data_in(3 downto 0));
tod_stop <= '0';
end if;
when X"9" => -- TOD SEC
if tod_i.alarm_set='1' then
tod_i.alarm.sech <= unsigned(data_in(6 downto 4));
tod_i.alarm.secl <= unsigned(data_in(3 downto 0));
else
tod_i.tod.sech <= unsigned(data_in(6 downto 4));
tod_i.tod.secl <= unsigned(data_in(3 downto 0));
end if;
when X"A" => -- TOD MIN
if tod_i.alarm_set='1' then
tod_i.alarm.minh <= unsigned(data_in(6 downto 4));
tod_i.alarm.minl <= unsigned(data_in(3 downto 0));
else
tod_i.tod.minh <= unsigned(data_in(6 downto 4));
tod_i.tod.minl <= unsigned(data_in(3 downto 0));
end if;
when X"B" => -- TOD HR
if tod_i.alarm_set='1' then
tod_i.alarm.pm <= data_in(7);
tod_i.alarm.hr <= unsigned(data_in(4 downto 0));
else
tod_stop <= '1';
-- What an idiocracy!
if data_in(4 downto 0) = "10010" then
tod_i.tod.pm <= not data_in(7);
else
tod_i.tod.pm <= data_in(7);
end if;
tod_i.tod.hr <= unsigned(data_in(4 downto 0));
end if;
when X"C" => -- SDR
when X"D" => -- ICR
if data_in(7)='0' then -- clear immediately
irq_mask_r <= irq_mask and not data_in(4 downto 0);
elsif data_in(7)='1' then -- set
irq_mask_r <= irq_mask or data_in(4 downto 0);
end if;
icr_modify <= '1';
when X"E" => -- CRA
timer_a_i.run <= data_in(0); -- '1' = run, one-shot underrun clears this bit
timer_a_i.pbon <= data_in(1); -- '1' forces ouput to PB6
timer_a_i.outmode <= data_in(2); -- '1' = toggle, '0' = pulse
timer_a_i.runmode <= data_in(3); -- '1' = one shot, '0' = cont
timer_a_i.load <= data_in(4); -- pulse
timer_a_i.inmode <= '0' & data_in(5); -- '1' = CNT(r), '0' = PHI2
spmode <= data_in(6); -- '1' = output
tod_i.freq_sel <= data_in(7); -- '1' = 50 Hz
wait_state <= turbo_en;
when X"F" => -- CRB
timer_b_i.run <= data_in(0); -- '1' = run, one-shot underrun clears this bit
timer_b_i.pbon <= data_in(1); -- '1' forces ouput to PB6
timer_b_i.outmode <= data_in(2); -- '1' = toggle, '0' = pulse
timer_b_i.runmode <= data_in(3); -- '1' = one shot, '0' = cont
timer_b_i.load <= data_in(4); -- pulse
timer_b_i.inmode <= data_in(6 downto 5); -- '01' = CNT(r), '00' = PHI2
-- '10' = timer_a underflow, '11' = underflow with CNT=high
tod_i.alarm_set <= data_in(7); -- '1' = alarm set, '0' = time set
wait_state <= turbo_en;
when others =>
null;
end case;
end if;
-- Reads --
v_data_out := X"FF";
case addr is
when X"0" => -- PRA
v_data_out := port_a_i;
when X"1" => -- PRB
v_data_out := port_b_i;
if ren='1' and falling='1' then
pc_o <= '0';
end if;
when X"2" => -- DDRA
v_data_out := pio_i.ddra;
when X"3" => -- DDRB
v_data_out := pio_i.ddrb;
when X"4" => -- TA LO
v_data_out := timer_a_count(7 downto 0);
when X"5" => -- TA HI
v_data_out := timer_a_count(15 downto 8);
when X"6" => -- TB LO
v_data_out := timer_b_count(7 downto 0);
when X"7" => -- TB HI
v_data_out := timer_b_count(15 downto 8);
when X"8" => -- TOD 10ths
v_data_out := X"0" & std_logic_vector(tod_copy.tenths);
if ren='1' and falling='1' then
tod_latch <= '1';
end if;
when X"9" => -- TOD SEC
v_data_out := '0' & std_logic_vector(tod_copy.sech & tod_copy.secl);
when X"A" => -- TOD MIN
v_data_out := '0' & std_logic_vector(tod_copy.minh & tod_copy.minl);
when X"B" => -- TOD HR
v_data_out := tod_copy.pm & "00" & std_logic_vector(tod_copy.hr);
if ren='1' and falling = '1' then
tod_latch <= '0';
end if;
when X"C" => -- SDR
v_data_out := sr_buffer;
when X"D" => -- ICR
v_data_out := irq_bit & "00" & (irq_flags or irq_events);
when X"E" => -- CRA
v_data_out(0) := timer_a_i.run; -- '1' = run, one-shot underrun clears this bit
v_data_out(1) := timer_a_i.pbon ; -- '1' forces ouput to PB6
v_data_out(2) := timer_a_i.outmode; -- '1' = toggle, '0' = pulse
v_data_out(3) := timer_a_i.runmode; -- '1' = one shot, '0' = cont
v_data_out(4) := '0';
v_data_out(5) := timer_a_i.inmode(0); -- '1' = CNT(r), '0' = PHI2
v_data_out(6) := spmode; -- '1' = output
v_data_out(7) := tod_i.freq_sel ; -- '1' = 50 Hz
when X"F" => -- CRB
v_data_out(0) := timer_b_i.run; -- '1' = run, one-shot underrun clears this bit
v_data_out(1) := timer_b_i.pbon ; -- '1' forces ouput to PB7
v_data_out(2) := timer_b_i.outmode; -- '1' = toggle, '0' = pulse
v_data_out(3) := timer_b_i.runmode; -- '1' = one shot, '0' = cont
v_data_out(4) := '0';
v_data_out(6 downto 5) := timer_b_i.inmode ; -- '01' = CNT(r), '00' = PHI2
-- '10' = timer_a underflow, '11' = underflow with CNT=high
v_data_out(7) := tod_i.alarm_set ; -- '1' = alarm set, '0' = time set
when others =>
null;
end case;
data_out <= v_data_out;
-- synthesis translate_off
assert not (g_report and falling = '1' and ren = '1')
report "Reading |" & g_unit_name & "| Reg |" & hstr(addr) & "| in cycle |" & integer'image(cycle) & "| val|" & hstr(v_data_out)
severity note;
-- synthesis translate_on
flag_c <= flag_i; -- synchronization flop
flag_d1 <= flag_c; -- flop 2; output is stable
flag_d2 <= flag_d1; -- flop 3: for edge detection
flag_d3 <= flag_d2; -- flop 4: for filtering
if flag_d3 = '1' and flag_d2 = '0' and flag_d1 = '0' then -- falling edge, minimum of two clock cycles low
flag_event_pre := '1';
end if;
if falling = '1' then
flag_event <= flag_event_pre;
flag_event_pre := '0';
end if;
if reset='1' then
flag_c <= '1'; -- resets avoid shift register
flag_d1 <= '1'; -- resets avoid shift register
flag_d2 <= '1'; -- resets avoid shift register
flag_d3 <= '1'; -- resets avoid shift register
spmode <= '0';
pc_o <= '1';
tod_latch <= '1';
tod_stop <= '1';
pio_i <= pio_default;
tod_i <= tod_default;
timer_a_i <= timer_default;
timer_b_i <= timer_default;
irq_ack_d <= '0';
irq_mask_r <= (others => '0');
irq_flags_r <= (others => '0');
irq_out <= '0';
irq_bit <= '0';
flag_event <= '0';
timer_a_reg <= (others => '1');
timer_b_reg <= (others => '1');
wait_state <= '0';
end if;
end if;
end process;
-- PLD data output
--process(wen, falling, addr, data_in, pio_i)
process(clock)
begin
if rising_edge(clock) then
pld_write_i <= '0';
pld_wdata_i <= (others => '1');
pld_waddr_i <= '0';
if wen='1' and falling = '1' then
case addr is
when X"0" => -- PRA
pld_write_i <= '1';
pld_wdata_i <= data_in or not pio_i.ddra;
pld_waddr_i <= '0'; -- Port A
when X"1" => -- PRB
pld_write_i <= '1';
pld_wdata_i <= data_in or not pio_i.ddrb;
pld_waddr_i <= '1'; -- Port B
when X"2" => -- DDRA
pld_write_i <= '1';
pld_wdata_i <= pio_i.pra or not data_in;
pld_waddr_i <= '0'; -- Port A
when X"3" => -- DDRB
pld_write_i <= '1';
pld_wdata_i <= pio_i.prb or not data_in;
pld_waddr_i <= '1'; -- Port B
when others =>
null;
end case;
end if;
if reset = '1' then
pld_state <= X"FFFF";
elsif pld_write_i = '1' then
if pld_waddr_i = '0' then
pld_state(7 downto 0) <= pld_wdata_i;
else
pld_state(15 downto 8) <= pld_wdata_i;
end if;
end if;
end if;
end process;
pld_write <= pld_write_i and not pld_inhibit;
pld_wdata <= pld_wdata_i;
pld_waddr <= pld_waddr_i;
-- write through of ta
process(addr, wen, data_in, timer_a_reg)
begin
timer_a_in <= timer_a_reg;
if addr = X"4" and wen = '1' then
timer_a_in(7 downto 0) <= data_in;
end if;
if addr = X"5" and wen = '1' then
timer_a_in(15 downto 8) <= data_in;
end if;
end process;
-- write through of tb
process(addr, wen, data_in, timer_b_reg)
begin
timer_b_in <= timer_b_reg;
if addr = X"6" and wen = '1' then
timer_b_in(7 downto 0) <= data_in;
end if;
if addr = X"7" and wen = '1' then
timer_b_in(15 downto 8) <= data_in;
end if;
end process;
-- write through of irq_mask, if and only if icr_modify is true
process(addr, wen, data_in, irq_mask_r, icr_modify)
begin
irq_mask <= irq_mask_r;
if addr = X"D" and wen = '1' and icr_modify = '1' then
if data_in(7)='0' then -- clear immediately
irq_mask <= irq_mask_r and not data_in(4 downto 0);
elsif data_in(7)='1' then -- set
irq_mask <= irq_mask_r or data_in(4 downto 0);
end if;
end if;
end process;
irq_ack <= '1' when addr = X"D" and ren = '1' else '0';
irq_flags <= irq_flags_r or irq_events;
ICR <= irq_bit & "00" & irq_flags;
-- combinatoric signal that indicates that the timer is about to start. Needed to set toggle to '1'.
timer_a_set_t <= '1' when (addr = X"E" and data_in(0) = '1' and wen = '1' and timer_a_i.run = '0') else '0';
timer_b_set_t <= '1' when (addr = X"F" and data_in(0) = '1' and wen = '1' and timer_b_i.run = '0') else '0';
-- Implement tod pin synchronization, edge detect and programmable prescaler
-- In addition, implement alarm compare logic with edge detect for event generation
b_tod: block
signal tod_c, tod_d : std_logic := '0';
signal tod_pre : unsigned(2 downto 0);
signal alarm_equal : boolean;
signal alarm_equal_d: boolean;
begin
-- alarm --
alarm_equal <= (tod_i.alarm = tod_i.tod);
--alarm_event <= '1' when alarm_equal else '0';
p_tod: process(clock)
begin
if rising_edge(clock) then
if falling = '1' then
tod_c <= tod_pin;
tod_d <= tod_c;
tod_tick <= '0';
if tod_stop = '0' then
if tod_c = '1' and tod_d = '0' then
-- if (tod_pre = "100" and tod_i.freq_sel='1') or
-- (tod_pre = "101" and tod_i.freq_sel='0') then
-- tod_pre <= "000";
-- tod_tick <= '1';
-- else
-- tod_pre <= tod_pre + 1;
-- end if;
if tod_pre = "000" then
tod_tick <='1';
tod_pre <= "10" & not tod_i.freq_sel;
else
tod_pre <= tod_pre - 1;
end if;
end if;
else
tod_pre <= "10" & not tod_i.freq_sel;
-- tod_pre <= "000";
end if;
-- alarm --
alarm_equal_d <= alarm_equal;
alarm_event <= '0';
if alarm_equal and not alarm_equal_d then
alarm_event <= '1';
end if;
end if;
if reset='1' then
tod_pre <= "000";
tod_tick <= '0';
alarm_event <= '0';
end if;
end if;
end process;
end block;
-- PIO Out select --
port_a_o <= pio_i.pra;
port_b_o(5 downto 0) <= pio_i.prb(5 downto 0);
port_b_o(6) <= pio_i.prb(6) when timer_a_i.pbon='0' else timer_a_out;
port_b_o(7) <= pio_i.prb(7) when timer_b_i.pbon='0' else timer_b_out;
port_a_t <= pio_i.ddra;
port_b_t(5 downto 0) <= pio_i.ddrb(5 downto 0);
port_b_t(6) <= pio_i.ddrb(6) or timer_a_i.pbon;
port_b_t(7) <= pio_i.ddrb(7) or timer_b_i.pbon;
-- Timer A
tmr_a: entity work.cia_timer
port map (
clock => clock,
reset => reset,
prescale_en => falling,
timer_ctrl => timer_a_i,
timer_set_t => timer_a_set_t,
timer_in => timer_a_in,
cnt => cnt_i,
othr_tmr_ev => '0',
timer_out => timer_a_out,
timer_stop => timer_a_stop,
timer_event => timer_a_evnt,
timer_count => timer_a_count );
-- Timer B
tmr_b: entity work.cia_timer
port map (
clock => clock,
reset => reset,
prescale_en => falling,
timer_ctrl => timer_b_i,
timer_set_t => timer_b_set_t,
timer_in => timer_b_in,
cnt => cnt_i,
othr_tmr_ev => timer_a_evnt,
timer_out => timer_b_out,
timer_stop => timer_b_stop,
timer_event => timer_b_evnt,
timer_count => timer_b_count );
ser: block
signal bit_cnt : integer range 0 to 7;
signal sr_shift : std_logic_vector(7 downto 0);
signal transmitting : std_logic := '0';
signal cnt_d1, cnt_d2, cnt_c : std_logic;
signal spmode_d : std_logic;
signal sr_dav : std_logic;
signal timer_a_evnt_d1 : std_logic := '0';
signal timer_a_evnt_d2 : std_logic := '0';
signal transmit_event : std_logic := '0';
signal transmit_event_d1: std_logic := '0';
signal receive_event : std_logic := '0';
signal receive_event_d1 : std_logic := '0';
begin
process(clock)
begin
if rising_edge(clock) then
if falling = '1' then
cnt_c <= cnt_i;
cnt_d1 <= cnt_c;
cnt_d2 <= cnt_d1;
spmode_d <= spmode;
receive_event <= '0';
transmit_event <= '0';
timer_a_evnt_d1 <= timer_a_evnt and transmitting;
timer_a_evnt_d2 <= timer_a_evnt_d1;
if spmode = '1' then -- output
if timer_a_evnt_d2='1' then
cnt_out <= not cnt_out;
if cnt_out='1' then -- was '1' -> falling edge
sp_out <= sr_shift(7);
sr_shift <= sr_shift(6 downto 0) & '0';
if bit_cnt = 0 then
transmit_event <= '1';
end if;
else
if bit_cnt=0 then
if sr_dav='1' then
sr_dav <= '0';
bit_cnt <= 7;
sr_shift <= sr_buffer;
transmitting <= '1';
else
transmitting <= '0';
end if;
else
bit_cnt <= bit_cnt - 1;
end if;
end if;
elsif sr_dav = '1' and transmitting = '0' then
sr_dav <= '0';
bit_cnt <= 7;
sr_shift <= sr_buffer;
transmitting <= '1';
end if;
else -- input mode
cnt_out <= '1';
if cnt_d2='0' and cnt_d1='1' then
sr_shift <= sr_shift(6 downto 0) & sp_i;
if bit_cnt = 0 then
bit_cnt <= 7;
receive_event <= '1';
else
bit_cnt <= bit_cnt - 1;
end if;
end if;
end if;
if wen='1' and addr=X"C" then
sr_dav <= '1';
sr_buffer <= data_in;
elsif receive_event = '1' then
sr_buffer <= sr_shift;
-- elsif wen='1' and addr=X"E" then
-- if transmitting='1' and data_in(6)='0' and spmode='1' then -- switching to input while transmitting
-- sr_buffer <= not sr_shift; -- ?
-- end if;
end if;
-- when switching to read mode, we assume there are 8 bits coming
if spmode='0' and spmode_d='1' then
sr_dav <= '0';
bit_cnt <= 7;
transmitting <= '0';
end if;
transmit_event_d1 <= transmit_event;
--transmit_event_d2 <= transmit_event_d1;
receive_event_d1 <= receive_event;
--receive_event_d2 <= receive_event_d1;
end if;
if reset='1' then
cnt_out <= '1';
sp_out <= '0';
bit_cnt <= 7;
transmitting <= '0';
sr_dav <= '0';
sr_shift <= (others => '0');
sr_buffer <= (others => '0');
transmit_event <= '0';
transmit_event_d1 <= '0';
receive_event <= '0';
receive_event_d1 <= '0';
end if;
end if;
end process;
serial_event <= receive_event_d1 or transmit_event_d1 or
'0';
-- (spmode and not spmode_d and not sr_dav) or -- when switching to output, and there is no data in the buffer
-- (not spmode and spmode_d and transmitting); -- when switching to input, and we are still in the transmit state
end block ser;
-- open drain
cnt_o <= '0';
sp_o <= '0';
cnt_t <= spmode and not cnt_out;
sp_t <= spmode and not sp_out;
end Gideon;
| gpl-3.0 | 199dc0ef19cc80d0a0309ba425f73693 | 0.390268 | 3.854257 | false | false | false | false |
mkreider/cocotb2 | tests/designs/viterbi_decoder_axi4s/src/dec_viterbi.vhd | 2 | 12,298 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Viterbi decoder top entity, connecting all decoder units.
--! @author Markus Fehrenz
--! @date 2011/12/05
--!
--! @details
--! The AXI std_logic_vector input is mapped to an internal information type.
--! Further the correct output order is handled.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
use dec_viterbi.pkg_components.all;
use dec_viterbi.pkg_trellis.all;
entity dec_viterbi is
port(
--
-- The core only uses AXI4-Stream interfaces,
-- based on AMBA4 AXI4-Stream Protocol with restrictions according to
-- Xilinx Migration, described in Xilinx AXI Reference UG761 (v13.3).
--
aclk : in std_logic;
-- Synchronous reset, active low.
aresetn : in std_logic;
--
-- Slave (input) data signals
-- Delivers the parity LLR values, one byte per LLR value.
--
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic_vector(31 downto 0);
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
--
-- Master (output) data signals
-- Delivers the decoded systematic (payload) bits.
--
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic;
m_axis_output_tlast : out std_logic;
m_axis_output_tready : in std_logic;
--
-- Slave (input) configuration signals
-- Configures window length and acquisition length.
--
s_axis_ctrl_tvalid : in std_logic;
s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
s_axis_ctrl_tlast : in std_logic;
s_axis_ctrl_tready : out std_logic
);
end entity dec_viterbi;
architecture rtl of dec_viterbi is
alias clk is aclk;
signal rst : std_logic;
-- split tdata into input array
signal input : t_input_block;
-- buffer signals
signal buffer_tdata : std_logic_vector(31 downto 0);
signal buffer_tvalid : std_logic;
signal buffer_tlast : std_logic;
-- branch signals
signal branch_tvalid : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
signal branch_tdata : t_branch;
signal branch_tlast : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
signal branch_tready : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
-- acs signals
signal acs_tvalid : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
signal acs_tlast : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
signal acs_tready : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
signal acs_dec_tdata : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
signal acs_prob_tdata : t_node;
-- ram signals
signal ram_tready : std_logic;
signal ram_tvalid, ram_tlast, ram_window_tuser, ram_last_tuser : std_logic_vector(1 downto 0);
signal ram_tdata : t_ram_rd_data;
-- traceback signals
signal traceback_tvalid, traceback_tdata : std_logic_vector(1 downto 0);
signal traceback_tready, traceback_tlast : std_logic_vector(1 downto 0);
signal traceback_last_tuser : std_logic_vector(1 downto 0);
-- reorder signals
signal reorder_tready, reorder_tvalid : std_logic_vector(1 downto 0);
signal reorder_tdata, reorder_tlast : std_logic_vector(1 downto 0);
signal reorder_last_tuser : std_logic_vector(1 downto 0);
-- output signals
signal output_tready : std_logic_vector(1 downto 0);
signal current_active : integer range 1 downto 0;
begin
--
-- There is always one byte of data for each LLR value, even though each
-- LLR value is represented with BW_LLR_INPUT bits. Hence, only
-- BW_LLR_INPUT bits are extracted from the byte.
--
gen_input_assignment: for i in NUMBER_PARITY_BITS - 1 downto 0 generate
begin
input(i) <= signed(buffer_tdata(8 * i + BW_LLR_INPUT - 1 downto 8 * i));
end generate gen_input_assignment;
rst <= not aresetn;
------------------------------
--- Portmapping components ---
------------------------------
-------------------------------------
-- AXI4S input buffer
--------------------------------------
inst_axi4s_buffer: axi4s_buffer
generic map(
DATA_WIDTH => 32
)
port map(
clk => clk,
rst => rst,
input => s_axis_input_tdata,
input_valid => s_axis_input_tvalid,
input_last => s_axis_input_tlast,
input_accept => s_axis_input_tready,
output => buffer_tdata,
output_valid => buffer_tvalid,
output_last => buffer_tlast,
output_accept => branch_tready(0)
);
-------------------------------------
-- Branch metric unit
--------------------------------------
gen_branch_distance : for i in NUMBER_BRANCH_UNITS - 1 downto 0 generate
begin
inst_branch_distance : branch_distance
generic map(
EDGE_WEIGHT => std_logic_vector(to_unsigned(i, NUMBER_PARITY_BITS))
)
port map(
clk => clk,
rst => rst,
s_axis_input_tvalid => buffer_tvalid,
s_axis_input_tdata => input,
s_axis_input_tlast => buffer_tlast,
s_axis_input_tready => branch_tready(i),
m_axis_output_tvalid => branch_tvalid(i),
m_axis_output_tdata => branch_tdata(i),
m_axis_output_tlast => branch_tlast(i),
m_axis_output_tready => acs_tready(0)
);
end generate gen_branch_distance;
-------------------------------------
-- ACS unit (path metric calculation)
--------------------------------------
gen_acs : for i in 0 to NUMBER_TRELLIS_STATES - 1 generate
signal inbranch_tdata_low : std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
signal inbranch_tdata_high : std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
signal inprev_tdata_low : std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
signal inprev_tdata_high : std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
begin
inbranch_tdata_low <= branch_tdata(to_integer(unsigned(TRANSITIONS(i)(0))));
inbranch_tdata_high <= branch_tdata(to_integer(unsigned(TRANSITIONS(i)(1))));
inprev_tdata_low <= acs_prob_tdata(to_integer(unsigned(PREVIOUS_STATES(i)(0))));
inprev_tdata_high <= acs_prob_tdata(to_integer(unsigned(PREVIOUS_STATES(i)(1))));
inst_acs : acs
generic map(
initialize_value => INITIALIZE_TRELLIS(i)
)
port map(
clk => clk,
rst => rst,
s_axis_inbranch_tvalid => branch_tvalid(0),
s_axis_inbranch_tdata_low => inbranch_tdata_low,
s_axis_inbranch_tdata_high => inbranch_tdata_high,
s_axis_inbranch_tlast => branch_tlast(0),
s_axis_inbranch_tready => acs_tready(i),
s_axis_inprev_tvalid => '1',
s_axis_inprev_tdata_low => inprev_tdata_low,
s_axis_inprev_tdata_high => inprev_tdata_high,
s_axis_inprev_tready => open,
m_axis_outprob_tvalid => open,
m_axis_outprob_tdata => acs_prob_tdata(i),
m_axis_outprob_tready => '1',
m_axis_outdec_tvalid => acs_tvalid(i),
m_axis_outdec_tdata => acs_dec_tdata(i),
m_axis_outdec_tlast => acs_tlast(i),
m_axis_outdec_tready => ram_tready
);
end generate gen_acs;
-------------------------------
-- Traceback
-------------------------------
inst_ram_ctrl : ram_ctrl
port map (
clk => clk,
rst => rst,
s_axis_input_tvalid => acs_tvalid(0),
s_axis_input_tdata => acs_dec_tdata,
s_axis_input_tlast => acs_tlast(0),
s_axis_input_tready => ram_tready,
m_axis_output_tvalid => ram_tvalid,
m_axis_output_tdata => ram_tdata,
m_axis_output_tlast => ram_tlast,
m_axis_output_tready => traceback_tready,
m_axis_output_window_tuser => ram_window_tuser,
m_axis_output_last_tuser => ram_last_tuser,
s_axis_ctrl_tvalid => s_axis_ctrl_tvalid,
s_axis_ctrl_tdata => s_axis_ctrl_tdata,
s_axis_ctrl_tready => s_axis_ctrl_tready
);
gen_inst_trellis_traceback : for i in 1 downto 0 generate
begin
inst_trellis_traceback : trellis_traceback
port map(
clk => clk,
rst => rst,
s_axis_input_tvalid => ram_tvalid(i),
s_axis_input_tdata => ram_tdata(i),
s_axis_input_tlast => ram_tlast(i),
s_axis_input_tready => traceback_tready(i),
s_axis_input_window_tuser => ram_window_tuser(i),
s_axis_input_last_tuser => ram_last_tuser(i),
m_axis_output_tvalid => traceback_tvalid(i),
m_axis_output_tdata => traceback_tdata(i),
m_axis_output_tlast => traceback_tlast(i),
m_axis_output_last_tuser => traceback_last_tuser(i),
m_axis_output_tready => reorder_tready(i)
);
end generate gen_inst_trellis_traceback;
-------------------------------
-- Reverse output order
-------------------------------
gen_inst_reorder : for i in 1 downto 0 generate
begin
inst_reorder : reorder
port map(
clk => clk,
rst => rst,
s_axis_input_tvalid => traceback_tvalid(i),
s_axis_input_tdata => traceback_tdata(i),
s_axis_input_tlast => traceback_tlast(i),
s_axis_input_last_tuser => traceback_last_tuser(i),
s_axis_input_tready => reorder_tready(i),
m_axis_output_tvalid => reorder_tvalid(i),
m_axis_output_tdata => reorder_tdata(i),
m_axis_output_tlast => reorder_tlast(i),
m_axis_output_last_tuser => reorder_last_tuser(i),
m_axis_output_tready => output_tready(i)
);
end generate gen_inst_reorder;
------------------------------
-- Recursive codes handling --
------------------------------
gen_inst_recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
signal reorder_recursion_tvalid : std_logic;
signal reorder_recursion_tdata : std_logic;
signal reorder_recursion_tlast : std_logic;
signal recursion_tready : std_logic;
begin
inst_recursion : recursion
port map(
clk => clk,
rst => rst,
s_axis_input_tvalid => reorder_recursion_tvalid,
s_axis_input_tdata => reorder_recursion_tdata,
s_axis_input_tlast => reorder_recursion_tlast,
s_axis_input_tready => recursion_tready,
m_axis_output_tvalid => m_axis_output_tvalid,
m_axis_output_tdata => m_axis_output_tdata,
m_axis_output_tlast => m_axis_output_tlast,
m_axis_output_tready => m_axis_output_tready
);
-------------------------------
-- Output interface handling
-------------------------------
reorder_recursion_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
'0';
reorder_recursion_tdata <= reorder_tdata(0) when current_active = 0 else
reorder_tdata(1);
reorder_recursion_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
'0';
output_tready(0) <= '1' when (current_active = 0) and m_axis_output_tready = '1' else
'0';
output_tready(1) <= '1' when (current_active = 1) and m_axis_output_tready = '1' else
'0';
end generate gen_inst_recursion;
no_recursion: if FEEDBACK_POLYNOMIAL = 0 generate
-------------------------------
-- Output interface handling
-------------------------------
m_axis_output_tdata <= reorder_tdata(0) when current_active = 0 else
reorder_tdata(1);
m_axis_output_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
'0';
m_axis_output_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
'0';
output_tready(0) <= '1' when (current_active = 0) and m_axis_output_tready = '1' else
'0';
output_tready(1) <= '1' when (current_active = 1) and m_axis_output_tready = '1' else
'0';
end generate no_recursion;
recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
begin
end generate recursion;
-- Check and merge reordering outputs and block if necessary.
pr_reorder_tready : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
current_active <= 0;
else
if reorder_tvalid(current_active) = '1' and m_axis_output_tready = '1' and reorder_last_tuser(current_active) = '1' then
current_active <= 1 - current_active;
end if;
end if;
end if;
end process pr_reorder_tready;
end architecture rtl;
| bsd-3-clause | 692914f2d1113c3c70563605317842df | 0.617336 | 3.186836 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/video/vhdl_source/char_generator_peripheral.vhd | 1 | 6,519 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_peripheral.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_peripheral is
generic (
g_color_ram : boolean := false;
g_screen_size : natural := 11 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
pix_clock : in std_logic;
pix_reset : in std_logic;
data_enable : in std_logic := '1';
h_count : in unsigned(11 downto 0);
v_count : in unsigned(11 downto 0);
pixel_active : out std_logic;
pixel_opaque : out std_logic;
pixel_data : out unsigned(3 downto 0) );
end entity;
architecture structural of char_generator_peripheral is
signal control : t_chargen_control;
signal screen_addr : unsigned(g_screen_size-1 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal color_data : std_logic_vector(7 downto 0) := X"0F";
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
signal io_req_regs : t_io_req := c_io_req_init;
signal io_req_regs_p : t_io_req := c_io_req_init;
signal io_req_scr : t_io_req := c_io_req_init;
signal io_req_color : t_io_req := c_io_req_init;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_resp_regs_p : t_io_resp := c_io_resp_init;
signal io_resp_scr : t_io_resp := c_io_resp_init;
signal io_resp_color : t_io_resp := c_io_resp_init;
begin
overlay_on <= control.overlay_on;
-- allocate 32K for character memory
-- allocate 32K for color memory
-- allocate another space for registers
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => g_screen_size,
g_range_hi => g_screen_size+1,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- size=15: xxx0000, size=11: xxx0000
reqs(1) => io_req_scr, -- size=15: xxx8000, size=11: xxx0800
reqs(2) => io_req_color, -- size=15: xx10000, size=11: xxx1000
resps(0) => io_resp_regs,
resps(1) => io_resp_scr,
resps(2) => io_resp_color );
i_bridge: entity work.io_bus_bridge2
generic map (
g_addr_width => 20
)
port map(
clock_a => clock,
reset_a => reset,
req_a => io_req_regs,
resp_a => io_resp_regs,
clock_b => pix_clock,
reset_b => pix_reset,
req_b => io_req_regs_p,
resp_b => io_resp_regs_p );
i_regs: entity work.char_generator_regs
port map (
clock => pix_clock,
reset => pix_reset,
io_req => io_req_regs_p,
io_resp => io_resp_regs_p,
keyb_row => keyb_row,
keyb_col => keyb_col,
control => control );
i_timing: entity work.char_generator_slave
generic map (
g_screen_size => g_screen_size )
port map (
clock => pix_clock,
reset => pix_reset,
data_enable => data_enable,
h_count => h_count,
v_count => v_count,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
color_data => color_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_opaque => pixel_opaque,
pixel_data => pixel_data );
i_rom: entity work.char_generator_rom
port map (
clock => pix_clock,
enable => '1',
address => char_addr,
data => char_data );
-- process(pix_clock)
-- begin
-- if rising_edge(pix_clock) then
-- screen_data <= std_logic_vector(screen_addr(7 downto 0));
-- color_data <= std_logic_vector(screen_addr(10 downto 3));
-- end if;
-- end process;
i_screen: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"20",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => screen_Data,
b_clock => clock,
b_req => io_req_scr,
b_resp => io_resp_scr );
r_color: if g_color_ram generate
i_color: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"0F",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => color_data,
b_clock => clock,
b_req => io_req_color,
b_resp => io_resp_color );
end generate;
end structural;
| gpl-3.0 | 9dcdd29a915863a3a98422d1fa4d6915 | 0.44562 | 3.703977 | false | false | false | false |
markusC64/1541ultimate2 | fpga/devices/vhdl_source/amd_flash.vhd | 1 | 7,167 | --------------------------------------------------------------------------------
-- Entity: amd_flash
-- Date:2018-08-12
-- Author: gideon
--
-- Description: Emulation of AMD flash, in this case 29F040 (512K)
-- This is a behavioral model of a Flash chip. It does not store the actual data
-- The 'allow_write' signal tells the client of this model to store the data
-- into the array. Erase functions will need to be performed by software to
-- modify the array accordingly. For this purpose, the erase byte can be polled
-- and cleared by software. A non-zero value indicates the sector that needs
-- to be erased. One bit for each sector. When 'FF' a chip-erase is requested.
-- In case of a pending erase, the rdata indicates whether the erase is done.
-- When rdata_valid is active, the client should forward the rdata from this
-- module, rather than the data from the array.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity amd_flash is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic;
allow_write : out std_logic;
-- flash bus
address : in unsigned(18 downto 0);
wdata : in std_logic_vector(7 downto 0);
write : in std_logic;
read : in std_logic;
rdata : out std_logic_vector(7 downto 0);
rdata_valid : out std_logic );
end entity;
architecture arch of amd_flash is
type t_state is (idle, prot1, prot2, program, erase1, erase2, erase3, erasing, suspend, auto_select);
signal state : t_state;
signal toggle : std_logic;
signal dirty : std_logic;
signal erase_sectors : std_logic_vector(7 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.read = '1' then
io_resp.ack <= '1';
if io_req.address(0) = '0' then
io_resp.data <= erase_sectors;
else
io_resp.data(0) <= dirty;
end if;
elsif io_req.write = '1' then
io_resp.ack <= '1';
erase_sectors <= X"00";
io_irq <= '0';
dirty <= '0';
end if;
if write = '1' then
if wdata = X"F0" then
allow_write <= '0';
state <= idle;
else
case state is
when idle =>
if address(14 downto 0) = "101010101010101" and wdata = X"AA" then
state <= prot1;
end if;
when prot1 =>
if address(14 downto 0) = "010101010101010" and wdata = X"55" then
state <= prot2;
else
state <= idle;
end if;
when prot2 =>
if address(14 downto 0) = "101010101010101" then
case wdata is
when X"90" =>
state <= auto_select;
when X"A0" =>
allow_write <= '1';
state <= program;
when X"80" =>
state <= erase1;
when others =>
state <= idle;
end case;
else
state <= idle;
end if;
when program =>
allow_write <= '0';
dirty <= '1';
state <= idle;
when erase1 =>
if address(14 downto 0) = "101010101010101" and wdata = X"AA" then
state <= erase2;
else
state <= idle;
end if;
when erase2 =>
if address(14 downto 0) = "010101010101010" and wdata = X"55" then
state <= erase3;
else
state <= idle;
end if;
when erase3 =>
if address(14 downto 0) = "101010101010101" and wdata = X"10" then
erase_sectors <= (others => '1');
state <= erasing;
io_irq <= '1';
elsif wdata = X"30" then
erase_sectors(to_integer(address(18 downto 16))) <= '1';
state <= erasing;
io_irq <= '1';
else
state <= idle;
end if;
when erasing =>
if wdata = X"B0" then
state <= suspend;
end if;
when suspend =>
if wdata = X"30" then
state <= erasing;
end if;
when others =>
null;
end case;
end if;
elsif read = '1' then
case state is
when idle | prot1 | prot2 | auto_select | erase1 | erase2 | erase3 =>
state <= idle;
toggle <= '0';
when erasing =>
toggle <= not toggle;
when others =>
null;
end case;
end if;
if state = erasing and erase_sectors = X"00" then
state <= idle;
end if;
if reset = '1' then
state <= idle;
allow_write <= '0';
erase_sectors <= (others => '0');
io_irq <= '0';
toggle <= '0';
dirty <= '0';
end if;
end if;
end process;
process(state, address, toggle)
begin
rdata_valid <= '0';
rdata <= X"00";
case state is
when erasing =>
rdata_valid <= '1';
rdata <= '0' & toggle & "000000";
when auto_select =>
rdata_valid <= '1';
if address(7 downto 0) = X"00" then
rdata <= X"01";
elsif address(7 downto 0) = X"01" then
rdata <= X"A4";
end if;
when others =>
null;
end case;
end process;
end architecture;
| gpl-3.0 | cb23900fbbe922f82d125c0e0d1aec22 | 0.386354 | 4.994425 | false | false | false | false |
trondd/mkjpeg | tb/vhdl/DCT_TROM.vhd | 2 | 5,924 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT_TROM.VHD
-- Created : Sun Aug 27 18:09 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT quantizer matrix
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity DCT_TROM is
generic
(
ROMADDR_W : INTEGER := 9;
ROMDATA_W : INTEGER := 8
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end DCT_TROM;
architecture RTL of DCT_TROM is
type DCT_TROM_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER;
constant rom : DCT_TROM_TYPE :=
-- (
-- 16,11,10,16,24,40,51,61,
-- 12,12,14,19,26,58,60,55,
-- 14,13,16,24,40,57,69,56,
-- 14,17,22,29,51,87,80,62,
-- 18,22,37,56,68,109,103,77,
-- 24,35,55,64,81,104,113,92,
-- 49,64,78,87,103,121,120,101,
-- 72,92,95,98,112,100,103,99);
(
-280, 48, -20, 16, -26, 46, -42, 27,
45, 12, -34, -31, 11, -1, 16, -44,
-5, -63, -34, 36, 24, -27, 6, 1,
-12, 12, -8, 34, 5, 2, -12, 5,
22, -18, 15, 9, 12, -5, 1, -11,
1, 10, 6, 12, -15, -11, -5, -10,
5, -16, -4, 10, -1, -11, -5, -11,
-9, 11, 5, -3, -14, 4, 0, 0,
-213, -110, -78, 38, 32, 2, -1, -9,
28, 62, -7, -7, 22, -11, 5, 7,
85, -21, 33, -28, -37, 36, -11, 5,
-34, -18, 2, -24, 8, -12, -11, -8,
-13, 8, 39, -63, 27, 0, 1, -4,
-32, -4, -8, 24, -22, 11, 20, -4,
-12, 8, 43, 41, -16, -12, 4, -10,
-11, 14, 15, 7, -11, 9, -32, 0,
-225, 10, 25, 18, -30, 18, -14, 7,
44, -13, -93, -7, 20, -7, 5, -11,
-88, -53, 6, 36, 2, 1, 22, 2,
-46, -10, 17, 23, 16, 32, -7, 8,
66, 46, -10, -3, -17, 4, -5, -5,
-51, -18, -9, 6, 37, 15, 23, -4,
-21, 22, 44, 49, 25, 21, 1, -12,
25, 12, -5, -2, -19, -8, -15, 0,
390, -97, -41, -15, 20, 6, 0, 12,
4, -62, 21, -5, -31, -7, -3, -20,
-352, 44, 27, 36, 35, 6, 5, 10,
33, 48, 48, 14, -8, 14, 10, -9,
-95, 108, 5, 1, -11, -23, -20, 1,
54, -7, -43, -32, -15, 3, 9, 3,
-42, 57, -32, -19, -4, 6, 5, -3,
23, -31, -22, -1, 19, 24, 22, 1,
-14, 148, 70, 67, 54, 30, 2, -10,
76, 20, 20, -39, 14, -10, -8, -11,
-86, -65, -15, -33, -33, -38, -2, 10,
61, 20, 50, 18, -15, -25, -23, 2,
11, -3, 12, 12, 15, 8, -18, -5,
-13, -14, -13, 16, 34, 15, -22, -18,
-8, -13, -3, 11, 19, 26, 9, -5,
1, 1, 2, -9, -11, 2, 7, 0,
-317, -9, 63, 17, 10, -26, 1, -11,
159, -41, -29, 42, -3, 21, 11, 1,
-6, -13, -18, 9, -19, 5, 15, 7,
-8, -9, -11, 16, -4, -1, -12, -3,
1, 15, -1, 3, -13, -8, 5, -1,
-9, 3, 2, 5, 7, -6, 12, -11,
-3, 1, -6, 1, -5, -4, 9, 6,
3, 7, 7, 3, -3, -5, -2, 0,
-404, 148, 70, 67, 54, 30, 2, -10,
76, 20, 20, -39, 14, -10, -8, -11,
-86, -65, -15, -33, -33, -38, -2, 10,
61, 20, 50, 18, -15, -25, -23, 2,
11, -3, 12, 12, 15, 8, -18, -5,
-13, -14, -13, 16, 34, 15, -22, -18,
-8, -13, -3, 11, 19, 26, 9, -5,
1, 1, 2, -9, -11, 2, 7, 0,
-404, 148, 70, 67, 54, 30, 2, -10,
76, 20, 20, -39, 14, -10, -8, -11,
-86, -65, -15, -33, -33, -38, -2, 10,
61, 20, 50, 18, -15, -25, -23, 2,
11, -3, 12, 12, 15, 8, -18, -5,
-13, -14, -13, 16, 34, 15, -22, -18,
-8, -13, -3, 11, 19, 26, 9, -5,
1, 1, 2, -9, -11, 2, 7, 0
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_SIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
| lgpl-3.0 | 0b396000e1b159d94e2f055c59d29765 | 0.270257 | 2.575652 | false | false | false | false |
asicguy/crash | fpga/src/toplevel/zedboard.vhd | 2 | 63,749 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: zc706.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Toplevel file for Zedboard.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity zedboard is
port (
-- ARM Connections
MIO : inout std_logic_vector(53 downto 0);
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB_pin : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRP : inout std_logic;
DDR_VRN : inout std_logic;
-- USRP DDR Interface
RX_DATA_CLK_N : in std_logic;
RX_DATA_CLK_P : in std_logic;
RX_DATA_N : in std_logic_vector(6 downto 0);
RX_DATA_P : in std_logic_vector(6 downto 0);
TX_DATA_N : out std_logic_vector(7 downto 0);
TX_DATA_P : out std_logic_vector(7 downto 0);
SPARE : out std_logic;
UART_TX : out std_logic);
end entity;
architecture RTL of zedboard is
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component zedboard_ps is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_ext_slave_conn_0_M_AXI_AWADDR_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_AWVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_AWREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_WDATA_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_WSTRB_pin : out std_logic_vector(3 downto 0);
axi_ext_slave_conn_0_M_AXI_WVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_WREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_BRESP_pin : in std_logic_vector(1 downto 0);
axi_ext_slave_conn_0_M_AXI_BVALID_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_BREADY_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_ARADDR_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_ARVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_ARREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_RDATA_pin : in std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_RRESP_pin : in std_logic_vector(1 downto 0);
axi_ext_slave_conn_0_M_AXI_RVALID_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_RREADY_pin : out std_logic;
processing_system7_0_IRQ_F2P_pin : in std_logic_vector(15 downto 0);
processing_system7_0_FCLK_CLK0_pin : out std_logic;
processing_system7_0_FCLK_RESET0_N_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_AWADDR_pin : in std_logic_vector(31 downto 0);
axi_ext_master_conn_0_S_AXI_AWLEN_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_AWSIZE_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_AWBURST_pin : in std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_AWCACHE_pin : in std_logic_vector(3 downto 0);
axi_ext_master_conn_0_S_AXI_AWPROT_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_AWVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_AWREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_WDATA_pin : in std_logic_vector(63 downto 0);
axi_ext_master_conn_0_S_AXI_WSTRB_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_WLAST_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_WVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_WREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_BRESP_pin : out std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_BVALID_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_BREADY_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_ARADDR_pin : in std_logic_vector(31 downto 0);
axi_ext_master_conn_0_S_AXI_ARLEN_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_ARSIZE_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_ARBURST_pin : in std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_ARCACHE_pin : in std_logic_vector(3 downto 0);
axi_ext_master_conn_0_S_AXI_ARPROT_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_ARVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_ARREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RDATA_pin : out std_logic_vector(63 downto 0);
axi_ext_master_conn_0_S_AXI_RRESP_pin : out std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_RLAST_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RVALID_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RREADY_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_AWUSER_pin : in std_logic_vector(4 downto 0);
axi_ext_master_conn_0_S_AXI_ARUSER_pin : in std_logic_vector(4 downto 0));
end component;
component ps_pl_interface is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff");
port (
-- AXIS Stream Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- AXI-Lite Slave bus for access to control & status registers
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI ACP Bus to interface with processor system
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
-- Interrupt on successfully completed AXI ACP writes
irq : out std_logic;
-- Global reset for all accelerators
rst_glb_n : out std_logic;
-- Accelerator interfaces
-- Note: Master & Slave 0 are not listed as the Datamover componeent
-- uses both.
-- Accelerator 1
-- Accelerator 1
axis_master_1_tvalid : in std_logic;
axis_master_1_tready : out std_logic;
axis_master_1_tdata : in std_logic_vector(63 downto 0);
axis_master_1_tdest : in std_logic_vector(2 downto 0);
axis_master_1_tlast : in std_logic;
axis_master_1_irq : in std_logic;
axis_slave_1_tvalid : out std_logic;
axis_slave_1_tready : in std_logic;
axis_slave_1_tdata : out std_logic_vector(63 downto 0);
axis_slave_1_tid : out std_logic_vector(2 downto 0);
axis_slave_1_tlast : out std_logic;
axis_slave_1_irq : in std_logic;
status_1_addr : out std_logic_vector(7 downto 0);
status_1_data : in std_logic_vector(31 downto 0);
status_1_stb : out std_logic;
ctrl_1_addr : out std_logic_vector(7 downto 0);
ctrl_1_data : out std_logic_vector(31 downto 0);
ctrl_1_stb : out std_logic;
-- Accelerator 2
axis_master_2_tvalid : in std_logic;
axis_master_2_tready : out std_logic;
axis_master_2_tdata : in std_logic_vector(63 downto 0);
axis_master_2_tdest : in std_logic_vector(2 downto 0);
axis_master_2_tlast : in std_logic;
axis_master_2_irq : in std_logic;
axis_slave_2_tvalid : out std_logic;
axis_slave_2_tready : in std_logic;
axis_slave_2_tdata : out std_logic_vector(63 downto 0);
axis_slave_2_tid : out std_logic_vector(2 downto 0);
axis_slave_2_tlast : out std_logic;
axis_slave_2_irq : in std_logic;
status_2_addr : out std_logic_vector(7 downto 0);
status_2_data : in std_logic_vector(31 downto 0);
status_2_stb : out std_logic;
ctrl_2_addr : out std_logic_vector(7 downto 0);
ctrl_2_data : out std_logic_vector(31 downto 0);
ctrl_2_stb : out std_logic;
-- Accelerator 3
axis_master_3_tvalid : in std_logic;
axis_master_3_tready : out std_logic;
axis_master_3_tdata : in std_logic_vector(63 downto 0);
axis_master_3_tdest : in std_logic_vector(2 downto 0);
axis_master_3_tlast : in std_logic;
axis_master_3_irq : in std_logic;
axis_slave_3_tvalid : out std_logic;
axis_slave_3_tready : in std_logic;
axis_slave_3_tdata : out std_logic_vector(63 downto 0);
axis_slave_3_tid : out std_logic_vector(2 downto 0);
axis_slave_3_tlast : out std_logic;
axis_slave_3_irq : in std_logic;
status_3_addr : out std_logic_vector(7 downto 0);
status_3_data : in std_logic_vector(31 downto 0);
status_3_stb : out std_logic;
ctrl_3_addr : out std_logic_vector(7 downto 0);
ctrl_3_data : out std_logic_vector(31 downto 0);
ctrl_3_stb : out std_logic;
-- Accelerator 4
axis_master_4_tvalid : in std_logic;
axis_master_4_tready : out std_logic;
axis_master_4_tdata : in std_logic_vector(63 downto 0);
axis_master_4_tdest : in std_logic_vector(2 downto 0);
axis_master_4_tlast : in std_logic;
axis_master_4_irq : in std_logic;
axis_slave_4_tvalid : out std_logic;
axis_slave_4_tready : in std_logic;
axis_slave_4_tdata : out std_logic_vector(63 downto 0);
axis_slave_4_tid : out std_logic_vector(2 downto 0);
axis_slave_4_tlast : out std_logic;
axis_slave_4_irq : in std_logic;
status_4_addr : out std_logic_vector(7 downto 0);
status_4_data : in std_logic_vector(31 downto 0);
status_4_stb : out std_logic;
ctrl_4_addr : out std_logic_vector(7 downto 0);
ctrl_4_data : out std_logic_vector(31 downto 0);
ctrl_4_stb : out std_logic;
-- Accelerator 5
axis_master_5_tvalid : in std_logic;
axis_master_5_tready : out std_logic;
axis_master_5_tdata : in std_logic_vector(63 downto 0);
axis_master_5_tdest : in std_logic_vector(2 downto 0);
axis_master_5_tlast : in std_logic;
axis_master_5_irq : in std_logic;
axis_slave_5_tvalid : out std_logic;
axis_slave_5_tready : in std_logic;
axis_slave_5_tdata : out std_logic_vector(63 downto 0);
axis_slave_5_tid : out std_logic_vector(2 downto 0);
axis_slave_5_tlast : out std_logic;
axis_slave_5_irq : in std_logic;
status_5_addr : out std_logic_vector(7 downto 0);
status_5_data : in std_logic_vector(31 downto 0);
status_5_stb : out std_logic;
ctrl_5_addr : out std_logic_vector(7 downto 0);
ctrl_5_data : out std_logic_vector(31 downto 0);
ctrl_5_stb : out std_logic;
-- Accelerator 6
axis_master_6_tvalid : in std_logic;
axis_master_6_tready : out std_logic;
axis_master_6_tdata : in std_logic_vector(63 downto 0);
axis_master_6_tdest : in std_logic_vector(2 downto 0);
axis_master_6_tlast : in std_logic;
axis_master_6_irq : in std_logic;
axis_slave_6_tvalid : out std_logic;
axis_slave_6_tready : in std_logic;
axis_slave_6_tdata : out std_logic_vector(63 downto 0);
axis_slave_6_tid : out std_logic_vector(2 downto 0);
axis_slave_6_tlast : out std_logic;
axis_slave_6_irq : in std_logic;
status_6_addr : out std_logic_vector(7 downto 0);
status_6_data : in std_logic_vector(31 downto 0);
status_6_stb : out std_logic;
ctrl_6_addr : out std_logic_vector(7 downto 0);
ctrl_6_data : out std_logic_vector(31 downto 0);
ctrl_6_stb : out std_logic;
-- Accelerator 7
axis_master_7_tvalid : in std_logic;
axis_master_7_tready : out std_logic;
axis_master_7_tdata : in std_logic_vector(63 downto 0);
axis_master_7_tdest : in std_logic_vector(2 downto 0);
axis_master_7_tlast : in std_logic;
axis_master_7_irq : in std_logic;
axis_slave_7_tvalid : out std_logic;
axis_slave_7_tready : in std_logic;
axis_slave_7_tdata : out std_logic_vector(63 downto 0);
axis_slave_7_tid : out std_logic_vector(2 downto 0);
axis_slave_7_tlast : out std_logic;
axis_slave_7_irq : in std_logic;
status_7_addr : out std_logic_vector(7 downto 0);
status_7_data : in std_logic_vector(31 downto 0);
status_7_stb : out std_logic;
ctrl_7_addr : out std_logic_vector(7 downto 0);
ctrl_7_data : out std_logic_vector(31 downto 0);
ctrl_7_stb : out std_logic);
end component;
component usrp_ddr_intf_axis is
generic (
DDR_CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface
BAUD : integer := 115200); -- UART baud rate
port (
-- USRP Interface
UART_TX : out std_logic; -- UART
RX_DATA_CLK_N : in std_logic; -- Receive data clock (N)
RX_DATA_CLK_P : in std_logic; -- Receive data clock (P)
RX_DATA_N : in std_logic_vector(6 downto 0); -- Receive data (N)
RX_DATA_P : in std_logic_vector(6 downto 0); -- Receive data (N)
TX_DATA_N : out std_logic_vector(7 downto 0); -- Transmit data (N)
TX_DATA_P : out std_logic_vector(7 downto 0); -- Transmit data (P)
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (DAC / TX Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (ADC / RX Data)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
rx_enable_aux : in std_logic;
tx_enable_aux : in std_logic);
end component;
component spectrum_sense is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Time Domain / FFT Input)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (Frequency Domain / FFT Output)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Strobes when threshold exceeded
-- Sideband signals
threshold_not_exceeded : out std_logic;
threshold_not_exceeded_stb : out std_logic;
threshold_exceeded : out std_logic;
threshold_exceeded_stb : out std_logic);
end component;
component bpsk_mod is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Binary Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used (TODO: maybe use for near empty input FIFO?)
-- AXIS Stream Master Interface (Modulated complex samples)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
trigger_stb : in std_logic);
end component;
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
signal clk : std_logic;
signal rst_n : std_logic;
signal S_AXI_AWADDR : std_logic_vector(31 downto 0);
signal S_AXI_AWVALID : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WDATA : std_logic_vector(31 downto 0);
signal S_AXI_WSTRB : std_logic_vector(3 downto 0);
signal S_AXI_WVALID : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BRESP : std_logic_vector(1 downto 0);
signal S_AXI_BVALID : std_logic;
signal S_AXI_BREADY : std_logic;
signal S_AXI_ARADDR : std_logic_vector(31 downto 0);
signal S_AXI_ARVALID : std_logic;
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RDATA : std_logic_vector(31 downto 0);
signal S_AXI_RRESP : std_logic_vector(1 downto 0);
signal S_AXI_RVALID : std_logic;
signal S_AXI_RREADY : std_logic;
signal M_AXI_AWADDR : std_logic_vector(31 downto 0);
signal M_AXI_AWPROT : std_logic_vector(2 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_AWREADY : std_logic;
signal M_AXI_WDATA : std_logic_vector(63 downto 0);
signal M_AXI_WSTRB : std_logic_vector(7 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_WREADY : std_logic;
signal M_AXI_BRESP : std_logic_vector(1 downto 0);
signal M_AXI_BVALID : std_logic;
signal M_AXI_BREADY : std_logic;
signal M_AXI_AWLEN : std_logic_vector(7 downto 0);
signal M_AXI_AWSIZE : std_logic_vector(2 downto 0);
signal M_AXI_AWBURST : std_logic_vector(1 downto 0);
signal M_AXI_AWCACHE : std_logic_vector(3 downto 0);
signal M_AXI_AWUSER : std_logic_vector(4 downto 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_ARADDR : std_logic_vector(31 downto 0);
signal M_AXI_ARPROT : std_logic_vector(2 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_ARREADY : std_logic;
signal M_AXI_RDATA : std_logic_vector(63 downto 0);
signal M_AXI_RRESP : std_logic_vector(1 downto 0);
signal M_AXI_RVALID : std_logic;
signal M_AXI_RREADY : std_logic;
signal M_AXI_RLAST : std_logic;
signal M_AXI_ARCACHE : std_logic_vector(3 downto 0);
signal M_AXI_ARUSER : std_logic_vector(4 downto 0);
signal M_AXI_ARLEN : std_logic_vector(7 downto 0);
signal M_AXI_ARBURST : std_logic_vector(1 downto 0);
signal M_AXI_ARSIZE : std_logic_vector(2 downto 0);
signal processing_system7_0_IRQ_F2P_pin : std_logic_vector(15 downto 0);
signal irq : std_logic;
signal rst_glb_n : std_logic;
signal axis_master_1_tvalid : std_logic;
signal axis_master_1_tready : std_logic;
signal axis_master_1_tdata : std_logic_vector(63 downto 0);
signal axis_master_1_tdest : std_logic_vector(2 downto 0);
signal axis_master_1_tlast : std_logic;
signal axis_master_1_irq : std_logic;
signal axis_slave_1_tvalid : std_logic;
signal axis_slave_1_tready : std_logic;
signal axis_slave_1_tdata : std_logic_vector(63 downto 0);
signal axis_slave_1_tid : std_logic_vector(2 downto 0);
signal axis_slave_1_tlast : std_logic;
signal axis_slave_1_irq : std_logic;
signal status_1_addr : std_logic_vector(7 downto 0);
signal status_1_data : std_logic_vector(31 downto 0);
signal status_1_stb : std_logic;
signal ctrl_1_addr : std_logic_vector(7 downto 0);
signal ctrl_1_data : std_logic_vector(31 downto 0);
signal ctrl_1_stb : std_logic;
signal axis_master_2_tvalid : std_logic;
signal axis_master_2_tready : std_logic;
signal axis_master_2_tdata : std_logic_vector(63 downto 0);
signal axis_master_2_tdest : std_logic_vector(2 downto 0);
signal axis_master_2_tlast : std_logic;
signal axis_master_2_irq : std_logic;
signal axis_slave_2_tvalid : std_logic;
signal axis_slave_2_tready : std_logic;
signal axis_slave_2_tdata : std_logic_vector(63 downto 0);
signal axis_slave_2_tid : std_logic_vector(2 downto 0);
signal axis_slave_2_tlast : std_logic;
signal axis_slave_2_irq : std_logic;
signal status_2_addr : std_logic_vector(7 downto 0);
signal status_2_data : std_logic_vector(31 downto 0);
signal status_2_stb : std_logic;
signal ctrl_2_addr : std_logic_vector(7 downto 0);
signal ctrl_2_data : std_logic_vector(31 downto 0);
signal ctrl_2_stb : std_logic;
signal axis_master_3_tvalid : std_logic;
signal axis_master_3_tready : std_logic;
signal axis_master_3_tdata : std_logic_vector(63 downto 0);
signal axis_master_3_tdest : std_logic_vector(2 downto 0);
signal axis_master_3_tlast : std_logic;
signal axis_master_3_irq : std_logic;
signal axis_slave_3_tvalid : std_logic;
signal axis_slave_3_tready : std_logic;
signal axis_slave_3_tdata : std_logic_vector(63 downto 0);
signal axis_slave_3_tid : std_logic_vector(2 downto 0);
signal axis_slave_3_tlast : std_logic;
signal axis_slave_3_irq : std_logic;
signal status_3_addr : std_logic_vector(7 downto 0);
signal status_3_data : std_logic_vector(31 downto 0);
signal status_3_stb : std_logic;
signal ctrl_3_addr : std_logic_vector(7 downto 0);
signal ctrl_3_data : std_logic_vector(31 downto 0);
signal ctrl_3_stb : std_logic;
signal axis_master_4_tvalid : std_logic;
signal axis_master_4_tready : std_logic;
signal axis_master_4_tdata : std_logic_vector(63 downto 0);
signal axis_master_4_tdest : std_logic_vector(2 downto 0);
signal axis_master_4_tlast : std_logic;
signal axis_master_4_irq : std_logic;
signal axis_slave_4_tvalid : std_logic;
signal axis_slave_4_tready : std_logic;
signal axis_slave_4_tdata : std_logic_vector(63 downto 0);
signal axis_slave_4_tid : std_logic_vector(2 downto 0);
signal axis_slave_4_tlast : std_logic;
signal axis_slave_4_irq : std_logic;
signal status_4_addr : std_logic_vector(7 downto 0);
signal status_4_data : std_logic_vector(31 downto 0);
signal status_4_stb : std_logic;
signal ctrl_4_addr : std_logic_vector(7 downto 0);
signal ctrl_4_data : std_logic_vector(31 downto 0);
signal ctrl_4_stb : std_logic;
signal axis_master_5_tvalid : std_logic;
signal axis_master_5_tready : std_logic;
signal axis_master_5_tdata : std_logic_vector(63 downto 0);
signal axis_master_5_tdest : std_logic_vector(2 downto 0);
signal axis_master_5_tlast : std_logic;
signal axis_master_5_irq : std_logic;
signal axis_slave_5_tvalid : std_logic;
signal axis_slave_5_tready : std_logic;
signal axis_slave_5_tdata : std_logic_vector(63 downto 0);
signal axis_slave_5_tid : std_logic_vector(2 downto 0);
signal axis_slave_5_tlast : std_logic;
signal axis_slave_5_irq : std_logic;
signal status_5_addr : std_logic_vector(7 downto 0);
signal status_5_data : std_logic_vector(31 downto 0);
signal status_5_stb : std_logic;
signal ctrl_5_addr : std_logic_vector(7 downto 0);
signal ctrl_5_data : std_logic_vector(31 downto 0);
signal ctrl_5_stb : std_logic;
signal axis_master_6_tvalid : std_logic;
signal axis_master_6_tready : std_logic;
signal axis_master_6_tdata : std_logic_vector(63 downto 0);
signal axis_master_6_tdest : std_logic_vector(2 downto 0);
signal axis_master_6_tlast : std_logic;
signal axis_master_6_irq : std_logic;
signal axis_slave_6_tvalid : std_logic;
signal axis_slave_6_tready : std_logic;
signal axis_slave_6_tdata : std_logic_vector(63 downto 0);
signal axis_slave_6_tid : std_logic_vector(2 downto 0);
signal axis_slave_6_tlast : std_logic;
signal axis_slave_6_irq : std_logic;
signal status_6_addr : std_logic_vector(7 downto 0);
signal status_6_data : std_logic_vector(31 downto 0);
signal status_6_stb : std_logic;
signal ctrl_6_addr : std_logic_vector(7 downto 0);
signal ctrl_6_data : std_logic_vector(31 downto 0);
signal ctrl_6_stb : std_logic;
signal axis_master_7_tvalid : std_logic;
signal axis_master_7_tready : std_logic;
signal axis_master_7_tdata : std_logic_vector(63 downto 0);
signal axis_master_7_tdest : std_logic_vector(2 downto 0);
signal axis_master_7_tlast : std_logic;
signal axis_master_7_irq : std_logic;
signal axis_slave_7_tvalid : std_logic;
signal axis_slave_7_tready : std_logic;
signal axis_slave_7_tdata : std_logic_vector(63 downto 0);
signal axis_slave_7_tid : std_logic_vector(2 downto 0);
signal axis_slave_7_tlast : std_logic;
signal axis_slave_7_irq : std_logic;
signal status_7_addr : std_logic_vector(7 downto 0);
signal status_7_data : std_logic_vector(31 downto 0);
signal status_7_stb : std_logic;
signal ctrl_7_addr : std_logic_vector(7 downto 0);
signal ctrl_7_data : std_logic_vector(31 downto 0);
signal ctrl_7_stb : std_logic;
signal rx_enable_aux : std_logic;
signal tx_enable_aux : std_logic;
signal threshold_not_exceeded : std_logic;
signal threshold_not_exceeded_stb : std_logic;
signal threshold_exceeded : std_logic;
signal threshold_exceeded_stb : std_logic;
signal trigger_stb : std_logic;
begin
inst_zedboard_ps : zedboard_ps
port map (
processing_system7_0_MIO => MIO,
processing_system7_0_PS_SRSTB_pin => PS_SRSTB,
processing_system7_0_PS_CLK_pin => PS_CLK,
processing_system7_0_PS_PORB_pin => PS_PORB,
processing_system7_0_DDR_Clk => DDR_Clk,
processing_system7_0_DDR_Clk_n => DDR_Clk_n,
processing_system7_0_DDR_CKE => DDR_CKE,
processing_system7_0_DDR_CS_n => DDR_CS_n,
processing_system7_0_DDR_RAS_n => DDR_RAS_n,
processing_system7_0_DDR_CAS_n => DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => DDR_BankAddr,
processing_system7_0_DDR_Addr => DDR_Addr,
processing_system7_0_DDR_ODT => DDR_ODT,
processing_system7_0_DDR_DRSTB => DDR_DRSTB,
processing_system7_0_DDR_DQ => DDR_DQ,
processing_system7_0_DDR_DM => DDR_DM,
processing_system7_0_DDR_DQS => DDR_DQS,
processing_system7_0_DDR_DQS_n => DDR_DQS_n,
processing_system7_0_DDR_VRN => DDR_VRN,
processing_system7_0_DDR_VRP => DDR_VRP,
axi_ext_slave_conn_0_M_AXI_AWADDR_pin => S_AXI_AWADDR,
axi_ext_slave_conn_0_M_AXI_AWVALID_pin => S_AXI_AWVALID,
axi_ext_slave_conn_0_M_AXI_AWREADY_pin => S_AXI_AWREADY,
axi_ext_slave_conn_0_M_AXI_WDATA_pin => S_AXI_WDATA,
axi_ext_slave_conn_0_M_AXI_WSTRB_pin => S_AXI_WSTRB,
axi_ext_slave_conn_0_M_AXI_WVALID_pin => S_AXI_WVALID,
axi_ext_slave_conn_0_M_AXI_WREADY_pin => S_AXI_WREADY,
axi_ext_slave_conn_0_M_AXI_BRESP_pin => S_AXI_BRESP,
axi_ext_slave_conn_0_M_AXI_BVALID_pin => S_AXI_BVALID,
axi_ext_slave_conn_0_M_AXI_BREADY_pin => S_AXI_BREADY,
axi_ext_slave_conn_0_M_AXI_ARADDR_pin => S_AXI_ARADDR,
axi_ext_slave_conn_0_M_AXI_ARVALID_pin => S_AXI_ARVALID,
axi_ext_slave_conn_0_M_AXI_ARREADY_pin => S_AXI_ARREADY,
axi_ext_slave_conn_0_M_AXI_RDATA_pin => S_AXI_RDATA,
axi_ext_slave_conn_0_M_AXI_RRESP_pin => S_AXI_RRESP,
axi_ext_slave_conn_0_M_AXI_RVALID_pin => S_AXI_RVALID,
axi_ext_slave_conn_0_M_AXI_RREADY_pin => S_AXI_RREADY,
processing_system7_0_IRQ_F2P_pin => processing_system7_0_IRQ_F2P_pin,
processing_system7_0_FCLK_CLK0_pin => clk,
processing_system7_0_FCLK_RESET0_N_pin => rst_n,
axi_ext_master_conn_0_S_AXI_AWADDR_pin => M_AXI_AWADDR,
axi_ext_master_conn_0_S_AXI_AWLEN_pin => M_AXI_AWLEN,
axi_ext_master_conn_0_S_AXI_AWSIZE_pin => M_AXI_AWSIZE,
axi_ext_master_conn_0_S_AXI_AWBURST_pin => M_AXI_AWBURST,
axi_ext_master_conn_0_S_AXI_AWCACHE_pin => M_AXI_AWCACHE,
axi_ext_master_conn_0_S_AXI_AWPROT_pin => M_AXI_AWPROT,
axi_ext_master_conn_0_S_AXI_AWVALID_pin => M_AXI_AWVALID,
axi_ext_master_conn_0_S_AXI_AWREADY_pin => M_AXI_AWREADY,
axi_ext_master_conn_0_S_AXI_WDATA_pin => M_AXI_WDATA,
axi_ext_master_conn_0_S_AXI_WSTRB_pin => M_AXI_WSTRB,
axi_ext_master_conn_0_S_AXI_WLAST_pin => M_AXI_WLAST,
axi_ext_master_conn_0_S_AXI_WVALID_pin => M_AXI_WVALID,
axi_ext_master_conn_0_S_AXI_WREADY_pin => M_AXI_WREADY,
axi_ext_master_conn_0_S_AXI_BRESP_pin => M_AXI_BRESP,
axi_ext_master_conn_0_S_AXI_BVALID_pin => M_AXI_BVALID,
axi_ext_master_conn_0_S_AXI_BREADY_pin => M_AXI_BREADY,
axi_ext_master_conn_0_S_AXI_ARADDR_pin => M_AXI_ARADDR,
axi_ext_master_conn_0_S_AXI_ARLEN_pin => M_AXI_ARLEN,
axi_ext_master_conn_0_S_AXI_ARSIZE_pin => M_AXI_ARSIZE,
axi_ext_master_conn_0_S_AXI_ARBURST_pin => M_AXI_ARBURST,
axi_ext_master_conn_0_S_AXI_ARCACHE_pin => M_AXI_ARCACHE,
axi_ext_master_conn_0_S_AXI_ARPROT_pin => M_AXI_ARPROT,
axi_ext_master_conn_0_S_AXI_ARVALID_pin => M_AXI_ARVALID,
axi_ext_master_conn_0_S_AXI_ARREADY_pin => M_AXI_ARREADY,
axi_ext_master_conn_0_S_AXI_RDATA_pin => M_AXI_RDATA,
axi_ext_master_conn_0_S_AXI_RRESP_pin => M_AXI_RRESP,
axi_ext_master_conn_0_S_AXI_RLAST_pin => M_AXI_RLAST,
axi_ext_master_conn_0_S_AXI_RVALID_pin => M_AXI_RVALID,
axi_ext_master_conn_0_S_AXI_RREADY_pin => M_AXI_RREADY,
axi_ext_master_conn_0_S_AXI_AWUSER_pin => M_AXI_AWUSER,
axi_ext_master_conn_0_S_AXI_ARUSER_pin => M_AXI_ARUSER);
processing_system7_0_IRQ_F2P_pin(15) <= irq;
inst_ps_pl_interface : ps_pl_interface
generic map (
C_BASEADDR => x"40000000",
C_HIGHADDR => x"4001ffff")
port map (
clk => clk,
rst_n => rst_n,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWUSER => M_AXI_AWUSER,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARUSER => M_AXI_ARUSER,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARSIZE => M_AXI_ARSIZE,
irq => irq,
rst_glb_n => rst_glb_n,
-- Note: Master 0 & Slave 0 interfaces are occupied by the
-- datamover component internally.
axis_master_1_tvalid => axis_master_1_tvalid,
axis_master_1_tready => axis_master_1_tready,
axis_master_1_tdata => axis_master_1_tdata,
axis_master_1_tdest => axis_master_1_tdest,
axis_master_1_tlast => axis_master_1_tlast,
axis_master_1_irq => axis_master_1_irq,
axis_slave_1_tvalid => axis_slave_1_tvalid,
axis_slave_1_tready => axis_slave_1_tready,
axis_slave_1_tdata => axis_slave_1_tdata,
axis_slave_1_tid => axis_slave_1_tid,
axis_slave_1_tlast => axis_slave_1_tlast,
axis_slave_1_irq => axis_slave_1_irq,
status_1_addr => status_1_addr,
status_1_data => status_1_data,
status_1_stb => status_1_stb,
ctrl_1_addr => ctrl_1_addr,
ctrl_1_data => ctrl_1_data,
ctrl_1_stb => ctrl_1_stb,
axis_master_2_tvalid => axis_master_2_tvalid,
axis_master_2_tready => axis_master_2_tready,
axis_master_2_tdata => axis_master_2_tdata,
axis_master_2_tdest => axis_master_2_tdest,
axis_master_2_tlast => axis_master_2_tlast,
axis_master_2_irq => axis_master_2_irq,
axis_slave_2_tvalid => axis_slave_2_tvalid,
axis_slave_2_tready => axis_slave_2_tready,
axis_slave_2_tdata => axis_slave_2_tdata,
axis_slave_2_tid => axis_slave_2_tid,
axis_slave_2_tlast => axis_slave_2_tlast,
axis_slave_2_irq => axis_slave_2_irq,
status_2_addr => status_2_addr,
status_2_data => status_2_data,
status_2_stb => status_2_stb,
ctrl_2_addr => ctrl_2_addr,
ctrl_2_data => ctrl_2_data,
ctrl_2_stb => ctrl_2_stb,
axis_master_3_tvalid => axis_master_3_tvalid,
axis_master_3_tready => axis_master_3_tready,
axis_master_3_tdata => axis_master_3_tdata,
axis_master_3_tdest => axis_master_3_tdest,
axis_master_3_tlast => axis_master_3_tlast,
axis_master_3_irq => axis_master_3_irq,
axis_slave_3_tvalid => axis_slave_3_tvalid,
axis_slave_3_tready => axis_slave_3_tready,
axis_slave_3_tdata => axis_slave_3_tdata,
axis_slave_3_tid => axis_slave_3_tid,
axis_slave_3_tlast => axis_slave_3_tlast,
axis_slave_3_irq => axis_slave_3_irq,
status_3_addr => status_3_addr,
status_3_data => status_3_data,
status_3_stb => status_3_stb,
ctrl_3_addr => ctrl_3_addr,
ctrl_3_data => ctrl_3_data,
ctrl_3_stb => ctrl_3_stb,
axis_master_4_tvalid => axis_master_4_tvalid,
axis_master_4_tready => axis_master_4_tready,
axis_master_4_tdata => axis_master_4_tdata,
axis_master_4_tdest => axis_master_4_tdest,
axis_master_4_tlast => axis_master_4_tlast,
axis_master_4_irq => axis_master_4_irq,
axis_slave_4_tvalid => axis_slave_4_tvalid,
axis_slave_4_tready => axis_slave_4_tready,
axis_slave_4_tdata => axis_slave_4_tdata,
axis_slave_4_tid => axis_slave_4_tid,
axis_slave_4_tlast => axis_slave_4_tlast,
axis_slave_4_irq => axis_slave_4_irq,
status_4_addr => status_4_addr,
status_4_data => status_4_data,
status_4_stb => status_4_stb,
ctrl_4_addr => ctrl_4_addr,
ctrl_4_data => ctrl_4_data,
ctrl_4_stb => ctrl_4_stb,
axis_master_5_tvalid => axis_master_5_tvalid,
axis_master_5_tready => axis_master_5_tready,
axis_master_5_tdata => axis_master_5_tdata,
axis_master_5_tdest => axis_master_5_tdest,
axis_master_5_tlast => axis_master_5_tlast,
axis_master_5_irq => axis_master_5_irq,
axis_slave_5_tvalid => axis_slave_5_tvalid,
axis_slave_5_tready => axis_slave_5_tready,
axis_slave_5_tdata => axis_slave_5_tdata,
axis_slave_5_tid => axis_slave_5_tid,
axis_slave_5_tlast => axis_slave_5_tlast,
axis_slave_5_irq => axis_slave_5_irq,
status_5_addr => status_5_addr,
status_5_data => status_5_data,
status_5_stb => status_5_stb,
ctrl_5_addr => ctrl_5_addr,
ctrl_5_data => ctrl_5_data,
ctrl_5_stb => ctrl_5_stb,
axis_master_6_tvalid => axis_master_6_tvalid,
axis_master_6_tready => axis_master_6_tready,
axis_master_6_tdata => axis_master_6_tdata,
axis_master_6_tdest => axis_master_6_tdest,
axis_master_6_tlast => axis_master_6_tlast,
axis_master_6_irq => axis_master_6_irq,
axis_slave_6_tvalid => axis_slave_6_tvalid,
axis_slave_6_tready => axis_slave_6_tready,
axis_slave_6_tdata => axis_slave_6_tdata,
axis_slave_6_tid => axis_slave_6_tid,
axis_slave_6_tlast => axis_slave_6_tlast,
axis_slave_6_irq => axis_slave_6_irq,
status_6_addr => status_6_addr,
status_6_data => status_6_data,
status_6_stb => status_6_stb,
ctrl_6_addr => ctrl_6_addr,
ctrl_6_data => ctrl_6_data,
ctrl_6_stb => ctrl_6_stb,
axis_master_7_tvalid => axis_master_7_tvalid,
axis_master_7_tready => axis_master_7_tready,
axis_master_7_tdata => axis_master_7_tdata,
axis_master_7_tdest => axis_master_7_tdest,
axis_master_7_tlast => axis_master_7_tlast,
axis_master_7_irq => axis_master_7_irq,
axis_slave_7_tvalid => axis_slave_7_tvalid,
axis_slave_7_tready => axis_slave_7_tready,
axis_slave_7_tdata => axis_slave_7_tdata,
axis_slave_7_tid => axis_slave_7_tid,
axis_slave_7_tlast => axis_slave_7_tlast,
axis_slave_7_irq => axis_slave_7_irq,
status_7_addr => status_7_addr,
status_7_data => status_7_data,
status_7_stb => status_7_stb,
ctrl_7_addr => ctrl_7_addr,
ctrl_7_data => ctrl_7_data,
ctrl_7_stb => ctrl_7_stb);
-- Accelerator 1
inst_usrp_ddr_intf_axis : usrp_ddr_intf_axis
generic map (
DDR_CLOCK_FREQ => 100e6,
BAUD => 115200)
port map (
UART_TX => UART_TX,
RX_DATA_CLK_N => RX_DATA_CLK_N,
RX_DATA_CLK_P => RX_DATA_CLK_P,
RX_DATA_N => RX_DATA_N,
RX_DATA_P => RX_DATA_P,
TX_DATA_N => TX_DATA_N,
TX_DATA_P => TX_DATA_P,
clk => clk,
rst_n => rst_glb_n,
status_addr => status_1_addr,
status_data => status_1_data,
status_stb => status_1_stb,
ctrl_addr => ctrl_1_addr,
ctrl_data => ctrl_1_data,
ctrl_stb => ctrl_1_stb,
axis_slave_tvalid => axis_slave_1_tvalid,
axis_slave_tready => axis_slave_1_tready,
axis_slave_tdata => axis_slave_1_tdata,
axis_slave_tid => axis_slave_1_tid,
axis_slave_tlast => axis_slave_1_tlast,
axis_slave_irq => axis_slave_1_irq,
axis_master_tvalid => axis_master_1_tvalid,
axis_master_tready => axis_master_1_tready,
axis_master_tdata => axis_master_1_tdata,
axis_master_tdest => axis_master_1_tdest,
axis_master_tlast => axis_master_1_tlast,
axis_master_irq => axis_master_1_irq,
rx_enable_aux => rx_enable_aux,
tx_enable_aux => tx_enable_aux);
rx_enable_aux <= '0';
tx_enable_aux <= threshold_exceeded OR threshold_not_exceeded;
-- Accelerator 2
inst_spectrum_sense : spectrum_sense
port map (
clk => clk,
rst_n => rst_glb_n,
status_addr => status_2_addr,
status_data => status_2_data,
status_stb => status_2_stb,
ctrl_addr => ctrl_2_addr,
ctrl_data => ctrl_2_data,
ctrl_stb => ctrl_2_stb,
axis_slave_tvalid => axis_slave_2_tvalid,
axis_slave_tready => axis_slave_2_tready,
axis_slave_tdata => axis_slave_2_tdata,
axis_slave_tid => axis_slave_2_tid,
axis_slave_tlast => axis_slave_2_tlast,
axis_slave_irq => axis_slave_2_irq,
axis_master_tvalid => axis_master_2_tvalid,
axis_master_tready => axis_master_2_tready,
axis_master_tdata => axis_master_2_tdata,
axis_master_tdest => axis_master_2_tdest,
axis_master_tlast => axis_master_2_tlast,
axis_master_irq => axis_master_2_irq,
threshold_not_exceeded => threshold_not_exceeded,
threshold_not_exceeded_stb => threshold_not_exceeded_stb,
threshold_exceeded => threshold_exceeded,
threshold_exceeded_stb => threshold_exceeded_stb);
-- Accelerator 3
inst_bpsk_mod : bpsk_mod
port map (
clk => clk,
rst_n => rst_glb_n,
status_addr => status_3_addr,
status_data => status_3_data,
status_stb => status_3_stb,
ctrl_addr => ctrl_3_addr,
ctrl_data => ctrl_3_data,
ctrl_stb => ctrl_3_stb,
axis_slave_tvalid => axis_slave_3_tvalid,
axis_slave_tready => axis_slave_3_tready,
axis_slave_tdata => axis_slave_3_tdata,
axis_slave_tid => axis_slave_3_tid,
axis_slave_tlast => axis_slave_3_tlast,
axis_slave_irq => axis_slave_3_irq,
axis_master_tvalid => axis_master_3_tvalid,
axis_master_tready => axis_master_3_tready,
axis_master_tdata => axis_master_3_tdata,
axis_master_tdest => axis_master_3_tdest,
axis_master_tlast => axis_master_3_tlast,
axis_master_irq => axis_master_3_irq,
trigger_stb => trigger_stb);
-- The output of either threshold trigger is controlled by control registers, so ORing them is
-- not an issue as only one should be active at a time.
trigger_stb <= threshold_exceeded_stb OR threshold_not_exceeded_stb;
-- Unused Accelerators
axis_slave_4_tready <= '0';
axis_slave_4_irq <= '0';
axis_master_4_tvalid <= '0';
axis_master_4_tdata <= x"0000000000000000";
axis_master_4_tdest <= "000";
axis_master_4_tlast <= '0';
axis_master_4_irq <= '0';
status_4_data <= x"00000000";
axis_slave_5_tready <= '0';
axis_slave_5_irq <= '0';
axis_master_5_tvalid <= '0';
axis_master_5_tdata <= x"0000000000000000";
axis_master_5_tdest <= "000";
axis_master_5_tlast <= '0';
axis_master_5_irq <= '0';
status_5_data <= x"00000000";
axis_slave_6_tready <= '0';
axis_slave_6_irq <= '0';
axis_master_6_tvalid <= '0';
axis_master_6_tdata <= x"0000000000000000";
axis_master_6_tdest <= "000";
axis_master_6_tlast <= '0';
axis_master_6_irq <= '0';
status_6_data <= x"00000000";
axis_slave_7_tready <= '0';
axis_slave_7_irq <= '0';
axis_master_7_tvalid <= '0';
axis_master_7_tdata <= x"0000000000000000";
axis_master_7_tdest <= "000";
axis_master_7_tlast <= '0';
axis_master_7_irq <= '0';
status_7_data <= x"00000000";
SPARE <= 'Z';
end architecture; | gpl-3.0 | 1eba7f977dc49120f63430af84e3d268 | 0.465482 | 3.809094 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/free_queue/vhdl_source/free_queue.vhd | 1 | 11,524 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : free_queue
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: A simple source of free memory blocks. Software provides, hardware uses.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.block_bus_pkg.all;
entity free_queue is
generic (
g_store_size : boolean := true;
g_block_size : natural := 1536 );
port (
clock : in std_logic;
reset : in std_logic;
-- free block interface
alloc_req : in std_logic;
alloc_resp : out t_alloc_resp;
used_req : in t_used_req;
used_resp : out std_logic;
-- io interface for local cpu
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic );
end entity;
architecture gideon of free_queue is
function iif(c : boolean; t : natural; f : natural) return natural is
begin
if c then return t; else return f; end if;
end function iif;
constant c_mem_width : natural := iif(g_store_size, 20, 8);
type t_state is (idle, calc_offset, calc_addr, allocating, popping);
signal state : t_state;
signal next_state : t_state;
signal alloc_resp_c : t_alloc_resp;
signal alloc_resp_i : t_alloc_resp;
signal offset_c : unsigned(23 downto 0);
signal offset_r : unsigned(offset_c'range);
signal used_head : unsigned(6 downto 0);
signal used_tail : unsigned(6 downto 0);
signal free_head : unsigned(6 downto 0);
signal free_tail : unsigned(6 downto 0);
signal used_head_next : unsigned(6 downto 0);
signal used_tail_next : unsigned(6 downto 0);
signal free_head_next : unsigned(6 downto 0);
signal free_tail_next : unsigned(6 downto 0);
signal table_addr : unsigned(7 downto 0);
signal table_rdata : std_logic_vector(19 downto 0) := (others => '0');
signal table_wdata : std_logic_vector(19 downto 0) := (others => '0');
signal table_en : std_logic;
signal table_we : std_logic;
signal sw_insert : std_logic;
signal sw_done : std_logic;
signal sw_addr : std_logic_vector(25 downto 0) := (others => '0');
signal sw_id : std_logic_vector(7 downto 0) := (others => '0');
signal sw_pop : std_logic;
signal sw_pop_valid : std_logic;
signal sw_pop_id : std_logic_vector(7 downto 0) := (others => '0');
signal sw_pop_size : std_logic_vector(11 downto 0) := (others => '0');
signal used_valid : std_logic;
signal soft_reset : std_logic;
signal free_full : std_logic;
begin
io_irq <= used_valid;
process(clock)
alias local_addr : unsigned(3 downto 0) is io_req.address(3 downto 0);
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if sw_done = '1' then
sw_insert <= '0';
sw_pop <= '0';
end if;
-- fall through logic
if used_valid = '0' then
if sw_pop_valid = '1' then
sw_pop_id <= table_rdata(7 downto 0);
if g_store_size then
sw_pop_size <= table_rdata(19 downto 8);
end if;
used_valid <= '1';
sw_pop <= '0';
end if;
if (used_head /= used_tail) and sw_pop = '0' then
sw_pop <= '1';
end if;
end if;
soft_reset <= '0';
if io_req.write = '1' then
io_resp.ack <= '1';
case local_addr is
when X"0" =>
null;
when X"1" =>
sw_addr(15 downto 8) <= io_req.data;
when X"2" =>
sw_addr(23 downto 16) <= io_req.data;
when X"3" =>
sw_addr(25 downto 24) <= io_req.data(1 downto 0);
when X"4" => -- free / insert
sw_id <= io_req.data;
sw_insert <= '1';
when X"F" =>
used_valid <= '0';
when X"E" =>
soft_reset <= '1';
when others =>
null;
end case;
end if;
if io_req.read = '1' then
io_resp.ack <= '1';
case local_addr is
-- when X"0" =>
-- io_resp.data <= '0' & std_logic_vector(used_head);
-- when X"1" =>
-- io_resp.data <= '0' & std_logic_vector(used_tail);
-- when X"2" =>
-- io_resp.data <= '0' & std_logic_vector(free_head);
-- when X"3" =>
-- io_resp.data <= '0' & std_logic_vector(free_tail);
when X"4" =>
io_resp.data(0) <= sw_insert;
io_resp.data(1) <= free_full;
when X"8" =>
io_resp.data <= sw_pop_id;
when X"A" =>
io_resp.data <= sw_pop_size(7 downto 0);
when X"B" =>
io_resp.data <= X"0" & sw_pop_size(11 downto 8);
when X"F" =>
io_resp.data(0) <= used_valid;
when others =>
null;
end case;
end if;
if reset = '1' then
sw_insert <= '0';
sw_pop <= '0';
used_valid <= '0';
end if;
end if;
end process;
-- Important note:
-- This 'RAM' makes up two small FIFOs, so there are four pointers and two areas.
-- One area is for free blocks; the other for allocated blocks. Number of free
-- blocks is now limited to 128.
i_table: entity work.spram
generic map (
g_width_bits => c_mem_width,
g_depth_bits => 8,
g_read_first => true
)
port map (
clock => clock,
address => table_addr,
rdata => table_rdata(c_mem_width-1 downto 0),
wdata => table_wdata(c_mem_width-1 downto 0),
en => table_en,
we => table_we
);
-- i_table: entity work.spram_freequeue
-- port map (
-- address => std_logic_vector(table_addr),
-- clock => clock,
-- data => table_wdata(c_mem_width-1 downto 0),
-- rden => table_en,
-- wren => table_we,
-- q => table_rdata(c_mem_width-1 downto 0)
-- );
alloc_resp <= alloc_resp_i;
process(alloc_req, alloc_resp_i, state, sw_insert, sw_pop, sw_id, sw_addr, used_req,
free_head, free_tail, used_head, used_tail, offset_r, table_rdata, free_full)
begin
next_state <= state;
alloc_resp_c <= alloc_resp_i;
table_addr <= (others => 'X');
table_wdata <= (others => '0');
table_we <= '0';
table_en <= '0';
free_head_next <= free_head;
free_tail_next <= free_tail;
used_head_next <= used_head;
used_tail_next <= used_tail;
used_resp <= '0';
sw_done <= '0';
sw_pop_valid <= '0';
alloc_resp_c.done <= '0';
offset_c <= offset_r;
if g_store_size then
table_wdata(19 downto 8) <= std_logic_vector(used_req.bytes);
end if;
if (free_head + 1) = free_tail then
free_full <= '1';
else
free_full <= '0';
end if;
case state is
when idle =>
if sw_insert = '1' then
-- Push into Free area
table_addr <= '0' & free_head;
table_wdata(7 downto 0) <= sw_id;
if free_full = '0' then
table_we <= '1';
table_en <= '1';
free_head_next <= free_head + 1;
end if;
sw_done <= '1';
elsif used_req.request = '1' then
-- Push into Used Area
table_addr <= '1' & used_head;
table_wdata(7 downto 0) <= std_logic_vector(used_req.id);
table_we <= '1';
table_en <= '1';
used_resp <= '1';
used_head_next <= used_head + 1;
elsif alloc_req = '1' and alloc_resp_i.done = '0' then
-- Pop from Free area
table_addr <= '0' & free_tail;
table_en <= '1';
if free_tail = free_head then
alloc_resp_c.error <= '1';
alloc_resp_c.done <= '1';
else
next_state <= allocating;
end if;
elsif sw_pop = '1' then
-- Pop from Used area
table_addr <= '1' & used_tail;
table_en <= '1';
if used_tail /= used_head then
next_state <= popping;
end if;
end if;
when allocating =>
free_tail_next <= free_tail + 1;
alloc_resp_c.id <= unsigned(table_rdata(7 downto 0));
next_state <= calc_offset;
when calc_offset =>
offset_c <= to_unsigned(g_block_size, 16) * alloc_resp_i.id;
next_state <= calc_addr;
when calc_addr =>
alloc_resp_c.address <= unsigned(sw_addr) + offset_r;
alloc_resp_c.done <= '1';
alloc_resp_c.error <= '0';
next_state <= idle;
when popping =>
used_tail_next <= used_tail + 1;
sw_pop_valid <= '1';
next_state <= idle;
end case;
end process;
process(clock)
begin
if rising_edge(clock) then
alloc_resp_i <= alloc_resp_c;
offset_r <= offset_c;
free_tail <= free_tail_next;
free_head <= free_head_next;
used_tail <= used_tail_next;
used_head <= used_head_next;
state <= next_state;
if reset = '1' or soft_reset = '1' then
state <= idle;
alloc_resp_i <= c_alloc_resp_init;
used_tail <= (others => '0');
used_head <= (others => '0');
free_tail <= (others => '0');
free_head <= (others => '0');
end if;
end if;
end process;
end architecture;
-- WAS: free_queue 287 (110) 193 (71) 0 (0) 8704 3 0 0 0 100 0 94 (35) 36 (9) 157 (65)
-- ID: free_queue 182 (181) 121 (121) 0 (0) 2048 1 0 0 0 101 0 61 (60) 24 (24) 97 (97)
-- ID+SIZE: free_queue 196 (195) 133 (133) 0 (0) 5120 1 0 0 0 101 0 63 (62) 32 (32) 101 (101)
-- size: only 14 cells more!
| gpl-3.0 | f1d502ff9d2ce1c5337996867376f8e0 | 0.439431 | 3.772177 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/floppy_stream.vhd | 1 | 10,007 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library work;
--use work.floppy_emu_pkg.all;
entity floppy_stream is
port (
clock : in std_logic;
reset : in std_logic;
tick_16MHz : in std_logic;
-- data from memory
mem_rdata : in std_logic_vector(7 downto 0);
do_read : out std_logic;
do_write : out std_logic;
do_advance : out std_logic;
-- info about the head
track : out unsigned(6 downto 0);
track_is_0 : out std_logic;
do_head_bang : out std_logic;
do_track_out : out std_logic;
do_track_in : out std_logic;
-- control i/o
floppy_inserted : in std_logic;
stepper_en : in std_logic;
motor_on : in std_logic;
sync : out std_logic;
mode : in std_logic;
write_prot_n : in std_logic;
step : in std_logic_vector(1 downto 0);
byte_ready : out std_logic;
rate_ctrl : in std_logic_vector(1 downto 0);
bit_time : in unsigned(9 downto 0); -- in steps of 10 ns
-- data to drive CPU
read_data : out std_logic_vector(7 downto 0) );
end floppy_stream;
architecture gideon of floppy_stream is
signal bit_tick : std_logic;
signal bit_timer : unsigned(8 downto 0);
signal bit_carry : std_logic;
signal mem_bit_cnt : unsigned(2 downto 0);
signal rd_bit_cnt : unsigned(2 downto 0) := "000";
signal mem_shift : std_logic_vector(7 downto 0);
signal rd_shift : std_logic_vector(9 downto 0) := (others => '0');
signal sync_i : std_logic;
signal byte_rdy_i : std_logic_vector(3 downto 0);
alias mem_rd_bit : std_logic is mem_shift(7);
signal track_i : unsigned(6 downto 0);
signal mode_d : std_logic;
signal write_delay : integer range 0 to 3;
signal random_bit : std_logic;
signal byte_ready_cnt : natural range 0 to 127 := 0;
-- resample
signal transition_pulse : std_logic;
signal cnt16 : unsigned(3 downto 0);
signal sampl : unsigned(3 downto 0);
signal rd_shift_pulse : std_logic;
signal rd_shift_data : std_logic;
signal rd_shift_phase : std_logic;
signal rd_shift_phase_d : std_logic;
-- weak bit implementation
signal random_data : std_logic_vector(15 downto 0);
signal random_trans : std_logic;
begin
p_clock_div: process(clock)
begin
if rising_edge(clock) then
bit_tick <= '0';
if bit_timer = 0 then
bit_tick <= motor_on;
bit_carry <= not bit_carry and bit_time(0); -- toggle if bit 0 is set
if bit_carry='1' then
bit_timer <= bit_time(9 downto 1);
else
bit_timer <= bit_time(9 downto 1) - 1;
end if;
else
bit_timer <= bit_timer - 1;
end if;
if reset='1' then
bit_timer <= to_unsigned(10, bit_timer'length);
bit_carry <= '0';
end if;
end if;
end process;
i_noise: entity work.noise_generator
generic map (
g_type => "Galois",
g_polynom => X"1020",
g_seed => X"569A"
)
port map (
clock => clock,
enable => tick_16MHz,
reset => reset,
q => random_data );
-- stream from memory
p_stream: process(clock)
variable history : std_logic_vector(4 downto 0) := "11111";
begin
if rising_edge(clock) then
do_read <= '0';
if bit_tick='1' then
random_bit <= '0';
history := history(3 downto 0) & mem_rd_bit;
if history = "00000" then -- something weird can happen now:
random_bit <= '1'; --random_data(2) and random_data(7) and random_data(11) and random_data(12); -- 1/16
end if;
mem_bit_cnt <= mem_bit_cnt + 1;
if mem_bit_cnt="000" then
mem_shift <= mem_rdata;
do_read <= mode; --'1'; does not pulse when in write mode
else
mem_shift <= mem_shift(6 downto 0) & '1';
end if;
end if;
if reset='1' then
mem_shift <= (others => '1');
mem_bit_cnt <= "000";
random_bit <= '0';
end if;
end if;
end process;
-- Pulse from the floppy (a one-clock pulse that happens only when data is '1')
random_trans <= '1' when random_data(10 downto 0) = "10010010101" else '0';
-- These pulses only in read mode
transition_pulse <= mode and ((bit_tick and mem_rd_bit) or (random_trans and random_bit));
p_resample: process(clock)
begin
if rising_edge(clock) then
if transition_pulse = '1' or reset = '1' then
cnt16 <= "00" & unsigned(rate_ctrl);
elsif tick_16MHz = '1' then
if cnt16 = X"F" then
cnt16 <= "00" & unsigned(rate_ctrl);
else
cnt16 <= cnt16 + 1;
end if;
end if;
rd_shift_pulse <= '0';
if transition_pulse = '1' or reset = '1' then
sampl <= (others => '0');
elsif tick_16MHz = '1' and cnt16 = X"F" then
if sampl(1 downto 0) = "01" then
rd_shift_pulse <= '1';
end if;
sampl <= sampl + 1;
end if;
end if;
end process;
rd_shift_data <= sampl(3) nor sampl(2);
rd_shift_phase <= not sampl(1);
-- parallelize stream and generate sync
-- and handle writes
p_reading: process(clock)
variable s : std_logic;
begin
if rising_edge(clock) then
if rd_shift = "1111111111" and mode='1' then
s := '0';
else
s := '1';
end if;
sync_i <= s;
do_advance <= '0';
do_write <= '0';
mode_d <= mode;
if mode_d='1' and mode='0' then -- going to write
write_delay <= 1;
-- do_advance <= '1';
end if;
if rd_shift_pulse = '1' then
rd_shift <= rd_shift(8 downto 0) & rd_shift_data;
rd_bit_cnt <= rd_bit_cnt + 1;
end if;
if s = '0' then
rd_bit_cnt <= "000";
end if;
rd_shift_phase_d <= rd_shift_phase;
if (rd_bit_cnt="111") and (rd_shift_phase='1') and (rd_shift_phase_d='0') then
byte_ready <= '0';
byte_ready_cnt <= 127; -- 8 us!
if mode = '0' then -- if writing
if write_delay = 0 then
if write_prot_n = '1' and floppy_inserted = '1' then
do_write <= '1';
else
do_advance <= '1';
end if;
else
write_delay <= write_delay - 1;
do_advance <= '1';
end if;
end if;
elsif byte_ready_cnt = 0 then
byte_ready <= '1';
elsif tick_16MHz = '1' then
byte_ready_cnt <= byte_ready_cnt - 1;
end if;
end if;
end process;
p_move: process(clock)
variable st : std_logic_vector(3 downto 0);
begin
if rising_edge(clock) then
do_track_in <= '0';
do_track_out <= '0';
do_head_bang <= '0';
if stepper_en='1' then
st := std_logic_vector(track_i(1 downto 0)) & step;
case st is
when "0001" | "0110" | "1011" | "1100" => -- up
do_track_in <= '1';
if track_i /= 83 then
track_i <= track_i + 1;
end if;
when "0011" | "0100" | "1001" | "1110" => -- down
do_track_out <= '1';
if track_i /= 0 then
track_i <= track_i - 1;
end if;
when others =>
null;
end case;
end if;
if reset='1' then
track_i <= "0000000";
end if;
end if;
end process;
-- outputs
sync <= sync_i;
read_data <= rd_shift(7 downto 0);
-- byte_ready <= byte_rdy_i;
track <= track_i;
track_is_0 <= '1' when track_i = "0000000" else '0';
end gideon;
| gpl-3.0 | 5ef21b8ccbc7e670ac8201d15e59e064 | 0.426402 | 4.087827 | false | false | false | false |
xiadz/oscilloscope | src/trace_pixgen.vhd | 1 | 6,938 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 20:16:43 05/22/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity trace_pixgen is
port (
nrst : in std_logic;
clk108 : in std_logic;
segment : in integer range 0 to 15;
segment_change : in std_logic;
subsegment : in integer range 0 to 3;
subsegment_change : in std_logic;
line : in integer range 0 to 15;
line_change : in std_logic;
column : in integer range 0 to 1279;
column_change : in std_logic;
page_change : in std_logic;
active_pixgen_source : in PIXGEN_SOURCE_T;
currently_read_screen_segment : in natural range 0 to 13;
currently_read_screen_column : in natural range 0 to 1279;
time_resolution : in integer range 0 to 15;
is_reading_active : in std_logic;
doutb : in std_logic_vector (8 downto 0);
addrb : out std_logic_vector (12 downto 0);
vout : out std_logic_vector (7 downto 0)
);
end trace_pixgen;
architecture behavioral of trace_pixgen is
signal position_div_3 : integer range 0 to 5973;
signal position_mod_3 : integer range 0 to 2;
signal delayed_active_pixgen_source : PIXGEN_SOURCE_T;
signal delayed_subsegment : integer range 0 to 3;
signal delayed_position_mod_3 : integer range 0 to 2;
signal delayed_line : integer range 0 to 15;
signal position_div_3_on_beginning_segment : integer range 0 to 5973;
signal position_mod_3_on_beginning_segment : integer range 0 to 2;
signal currently_inside_reading_zone : std_logic;
begin
-- Computing current position
process (nrst, clk108, position_mod_3, position_div_3) is
variable incremented_position_div_3 : integer range 0 to 5973;
variable incremented_position_mod_3 : integer range 0 to 2;
begin
if position_mod_3 = 2 then
incremented_position_div_3 := position_div_3 + 1;
incremented_position_mod_3 := 0;
else
incremented_position_div_3 := position_div_3;
incremented_position_mod_3 := position_mod_3 + 1;
end if;
if nrst = '0' then
position_div_3 <= 0;
position_mod_3 <= 0;
currently_inside_reading_zone <= '0';
elsif rising_edge (clk108) then
if currently_read_screen_segment = 0 and currently_read_screen_column = 0 then
currently_inside_reading_zone <= '0';
else
if time_resolution >= 10 or is_reading_active = '0' then
if segment = currently_read_screen_segment and
column - currently_read_screen_column < 6 and
column - currently_read_screen_column >= 0 then
currently_inside_reading_zone <= '1';
else
currently_inside_reading_zone <= '0';
end if;
elsif time_resolution >= 7 then
if segment = currently_read_screen_segment then
currently_inside_reading_zone <= '1';
else
currently_inside_reading_zone <= '0';
end if;
else
currently_inside_reading_zone <= '0';
end if;
end if;
if active_pixgen_source = TRACE_PIXGEN_T then
if page_change = '1' then
position_div_3 <= 0;
position_mod_3 <= 0;
position_div_3_on_beginning_segment <= 0;
position_mod_3_on_beginning_segment <= 0;
elsif segment_change = '1' then
position_div_3 <= incremented_position_div_3;
position_mod_3 <= incremented_position_mod_3;
position_div_3_on_beginning_segment <= incremented_position_div_3;
position_mod_3_on_beginning_segment <= incremented_position_mod_3;
elsif line_change = '1' then
position_div_3 <= position_div_3_on_beginning_segment;
position_mod_3 <= position_mod_3_on_beginning_segment;
else
position_div_3 <= incremented_position_div_3;
position_mod_3 <= incremented_position_mod_3;
end if;
end if;
end if;
end process;
addrb <= std_logic_vector (to_unsigned (position_div_3, 13));
delayed_active_pixgen_source <= active_pixgen_source when rising_edge (clk108);
delayed_subsegment <= subsegment when rising_edge (clk108);
delayed_position_mod_3 <= position_mod_3 when rising_edge (clk108);
delayed_line <= line when rising_edge (clk108);
process (nrst, delayed_active_pixgen_source, delayed_subsegment, delayed_position_mod_3, delayed_line, currently_inside_reading_zone) is
begin
if nrst = '0' or delayed_active_pixgen_source /= TRACE_PIXGEN_T then
vout <= "00000000";
else
if currently_inside_reading_zone = '1' then
vout <= "10010010";
elsif delayed_subsegment = 0 then
-- red
if delayed_line = 15 then
vout <= "11100000";
elsif doutb (3 * delayed_position_mod_3) = '1' then
vout <= "11100000";
else
vout <= "00000000";
end if;
elsif delayed_subsegment = 1 then
-- green
if delayed_line = 15 then
vout <= "00011100";
elsif doutb (3 * delayed_position_mod_3 + 1) = '1' then
vout <= "00011100";
else
vout <= "00000000";
end if;
elsif delayed_subsegment = 2 then
-- blue
if delayed_line = 15 then
vout <= "00000011";
elsif doutb (3 * delayed_position_mod_3 + 2) = '1' then
vout <= "00000011";
else
vout <= "00000000";
end if;
else
vout <= "00000000";
end if;
end if;
end process;
end behavioral;
| mit | 11704b7fe0667571f34e78f86dbac012 | 0.493082 | 4.543549 | false | false | false | false |
fpgaddicted/5bit-shift-register-structural- | debounce.vhd | 1 | 1,785 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:37:54 04/11/2017
-- Design Name:
-- Module Name: debounce - logic
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY debounce IS
GENERIC(
counter_size : INTEGER := 20); --counter size (19 bits gives 10.5ms with 50MHz clock)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END debounce;
ARCHITECTURE logic OF debounce IS
SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set : STD_LOGIC; --sync reset to zero
SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
BEGIN
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
If(counter_set = '1') THEN --reset counter because input is changing
counter_out <= (OTHERS => '0');
ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
counter_out <= counter_out + 1;
ELSE --stable input time is met
result <= flipflops(1);
END IF;
END IF;
END PROCESS;
END logic; | gpl-3.0 | e8e6e736783a9d638b80ec77bb2e6b5a | 0.546218 | 3.949115 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/extender/vhdl_source/extender_u64.vhd | 1 | 5,623 | --------------------------------------------------------------------------------
-- Entity: extender
-- Date:2017-04-22
-- Author: Gideon
--
-- Description: This unit is meant to fit in an external PLD for I/O extension
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity extender_u64 is
port (
reset_n : in std_logic;
data : inout std_logic_vector(7 downto 0);
read : in std_logic;
write : in std_logic;
address : in unsigned(2 downto 0);
cia1_pa : inout std_logic_vector(7 downto 0);
cia1_pb : inout std_logic_vector(7 downto 0);
cia2_pa : inout std_logic_vector(7 downto 0);
cia2_pb : inout std_logic_vector(7 downto 0);
lightpen : out std_logic
);
end entity;
architecture arch of extender_u64 is
signal cia1_pa_t : std_logic_vector(7 downto 0) := (others => '0');
signal cia1_pa_o : std_logic_vector(7 downto 0) := (others => '0');
signal cia1_pb_t : std_logic_vector(7 downto 0) := (others => '0');
signal cia1_pb_o : std_logic_vector(7 downto 0) := (others => '0');
signal cia2_pa_t : std_logic_vector(7 downto 0) := (others => '0');
signal cia2_pa_o : std_logic_vector(7 downto 0) := (others => '0');
signal cia2_pb_t : std_logic_vector(7 downto 0) := (others => '0');
signal cia2_pb_o : std_logic_vector(7 downto 0) := (others => '0');
signal read_data : std_logic_vector(7 downto 0);
signal read_2pa : std_logic_vector(7 downto 0);
begin
-- CIA1 Port A and B have pull ups on the board (joy / keyboard: read pin)
-- CIA2 Port A:
-- 0: VA14 (should read '1' when input, else read output)
-- 1: VA15 (should read '1' when input, else read output)
-- 2: UserPort pin (needs pull up), read actual pin
-- 3: ATN Out (should read '1' when input, else read output)
-- 4: CLOCK Out (should read '1' when input, else read output)
-- 5: DATA Out (should read '1' when input, else read output)
-- 6: CLOCK In - connected to CLK pin of IEC bus, reads the correct value
-- 7: DATA In - connected to DATA pin of IEC bus, reads the correct value
-- CIA2 Port B:
-- 0: UserPort pin (needs pull up, read pin)
-- 1: UserPort pin (needs pull up, read pin)
-- 2: UserPort pin (needs pull up, read pin)
-- 3: UserPort pin (needs pull up, read pin)
-- 4: UserPort pin (needs pull up, read pin)
-- 5: UserPort pin (needs pull up, read pin)
-- 6: UserPort pin (needs pull up, read pin)
-- 7: UserPort pin (needs pull up, read pin)
read_2pa(0) <= cia2_pa_o(0) or not cia2_pa_t(0);
read_2pa(1) <= cia2_pa_o(1) or not cia2_pa_t(1);
read_2pa(2) <= cia2_pa(2);
read_2pa(3) <= cia2_pa_o(3) or not cia2_pa_t(3);
read_2pa(4) <= cia2_pa_o(4) or not cia2_pa_t(4);
read_2pa(5) <= cia2_pa_o(5) or not cia2_pa_t(5);
read_2pa(6) <= cia2_pa(6);
read_2pa(7) <= cia2_pa(7);
process(cia1_pa, cia1_pb, cia2_pa, read_2pa, address)
begin
case address is
when "000" =>
read_data <= cia1_pa;
when "001" =>
read_data <= cia1_pb;
-- when "010" =>
-- read_data <= cia1_pa_t;
-- when "011" =>
-- read_data <= cia1_pb_t;
when "100" =>
read_data <= read_2pa;
when "101" =>
read_data <= cia2_pa;
-- when "110" =>
-- read_data <= cia2_pa_t;
-- when "111" =>
-- read_data <= cia2_pb_t;
when others =>
read_data <= X"FF";
end case;
end process;
data <= read_data when read = '0' else "ZZZZZZZZ";
process(write, reset_n)
begin
if reset_n = '0' then
cia1_pa_t <= (others => '0');
cia1_pa_o <= (others => '0');
cia1_pb_t <= (others => '0');
cia1_pb_o <= (others => '0');
cia2_pa_t <= (others => '0');
cia2_pa_o <= (others => '0');
cia2_pb_t <= (others => '0');
cia2_pb_o <= (others => '0');
elsif rising_edge(write) then
case address is
when "000" => -- CIA1 PA
cia1_pa_o <= data;
when "001" => -- CIA1 PB
cia1_pb_o <= data;
when "010" => -- CIA1 PA DDR
cia1_pa_t <= data;
when "011" => -- CIA1 PB DDR
cia1_pb_t(5 downto 0) <= data(5 downto 0); -- we never drive the B ports, bit 6 and 7, the FPGA does
when "100" => -- CIA2 PA
cia2_pa_o <= data;
when "101" => -- CIA2 PB
cia2_pb_o <= data;
when "110" => -- CIA2 PA DDR
cia2_pa_t <= data;
when "111" => -- CIA2 PB DDR
cia2_pb_t(5 downto 0) <= data(5 downto 0); -- we never drive the B ports, bit 6 and 7, the FPGA does
when others =>
null;
end case;
end if;
end process;
r1: for i in 0 to 7 generate
cia1_pa(i) <= '0' when cia1_pa_o(i) = '0' and cia1_pa_t(i) = '1' else 'Z';
cia1_pb(i) <= '0' when cia1_pb_o(i) = '0' and cia1_pb_t(i) = '1' else 'Z';
end generate;
-- cia2_pa <= "ZZZZZZZZ";
cia2_pb <= "ZZZZZZZZ";
r2: for i in 0 to 7 generate
cia2_pa(i) <= cia2_pa_o(i) when cia2_pa_t(i) = '1' else 'Z';
-- cia2_pb(i) <= '0' when cia2_pb_o(i) = '0' and cia2_pb_t(i) = '1' else 'Z';
end generate;
lightpen <= cia1_pb(4);
end architecture;
| gpl-3.0 | 3e49637ecd9d3050a5610ebf1b00aa4d | 0.503112 | 3.08956 | false | false | false | false |
chiggs/nvc | test/parse/bitstring.vhd | 3 | 307 | package bitstring is
constant x : t := X"1234";
constant y : t := O"1234";
constant z : t := X"ab";
constant b : t := B"101";
constant c : t := x"f";
constant d : t := X"a_b";
end package;
package bitstring_error is
constant e1 : t := O"9"; -- Error
end package;
| gpl-3.0 | 51f533ca447dbf788827dc1a91feef9c | 0.52443 | 3.10101 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/slot_timing.vhd | 1 | 5,804 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slot_timing is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
PHI2 : in std_logic;
BA : in std_logic;
serve_vic : in std_logic;
serve_enable : in std_logic;
serve_inhibit : in std_logic;
timing_addr : in unsigned(2 downto 0) := "000";
edge_recover : in std_logic;
allow_serve : out std_logic;
phi2_tick : out std_logic;
phi2_fall : out std_logic;
phi2_recovered : out std_logic;
clock_det : out std_logic;
vic_cycle : out std_logic;
inhibit : out std_logic;
do_sample_addr : out std_logic;
do_probe_end : out std_logic;
do_sample_io : out std_logic;
do_io_event : out std_logic );
end slot_timing;
architecture gideon of slot_timing is
signal phi2_c : std_logic;
signal phi2_d : std_logic;
signal ba_c : std_logic;
signal phase_h : integer range 0 to 63 := 0;
signal phase_l : integer range 0 to 63 := 0;
signal allow_tick_h : boolean := true;
signal allow_tick_l : boolean := true;
signal phi2_falling : std_logic;
signal ba_hist : std_logic_vector(3 downto 0) := (others => '0');
signal phi2_rec_i : std_logic := '0';
signal phi2_tick_i : std_logic;
signal serve_en_i : std_logic := '0';
signal off_cnt : integer range 0 to 7;
constant c_memdelay : integer := 5;
constant c_sample : integer := 6;
constant c_probe_end : integer := 11;
constant c_sample_vic : integer := 10;
constant c_io : integer := 19;
attribute register_duplication : string;
attribute register_duplication of ba_c : signal is "no";
attribute register_duplication of phi2_c : signal is "no";
begin
vic_cycle <= '1' when (ba_hist = "0000") else '0';
phi2_recovered <= phi2_rec_i;
phi2_tick <= phi2_tick_i;
phi2_fall <= phi2_d and not phi2_c;
process(clock)
begin
if rising_edge(clock) then
ba_c <= BA;
phi2_c <= PHI2;
phi2_d <= phi2_c;
phi2_tick_i <= '0';
-- Off counter, to allow software to gracefully quit
if serve_enable='1' and serve_inhibit='0' then
off_cnt <= 7;
serve_en_i <= '1';
elsif off_cnt = 0 then
serve_en_i <= '0';
elsif phi2_tick_i='1' and ba_c='1' then
off_cnt <= off_cnt - 1;
serve_en_i <= '1';
end if;
-- if (phi2_rec_i='0' and allow_tick_h) or
-- (phi2_rec_i='1' and allow_tick_l) then
-- phi2_rec_i <= PHI2;
-- end if;
-- related to rising edge
-- if then -- rising edge
if ((edge_recover = '1') and (phase_l = 24)) or
((edge_recover = '0') and phi2_d='0' and phi2_c='1' and allow_tick_h) then
ba_hist <= ba_hist(2 downto 0) & ba_c;
phi2_tick_i <= '1';
phi2_rec_i <= '1';
phase_h <= 0;
clock_det <= '1';
allow_tick_h <= false; -- filter
elsif phase_h = 63 then
clock_det <= '0';
else
phase_h <= phase_h + 1;
end if;
if phase_h = 46 then -- max 1.06 MHz
allow_tick_h <= true;
end if;
-- related to falling edge
phi2_falling <= '0';
if phi2_d='1' and phi2_c='0' and allow_tick_l then -- falling edge
phi2_falling <= '1';
phi2_rec_i <= '0';
phase_l <= 0;
allow_tick_l <= false; -- filter
elsif phase_l /= 63 then
phase_l <= phase_l + 1;
end if;
if phase_l = 46 then -- max 1.06 MHz
allow_tick_l <= true;
end if;
do_io_event <= phi2_falling;
-- timing pulses
if phase_h = 0 then
inhibit <= serve_en_i;
elsif phase_h = c_sample then
inhibit <= '0';
end if;
do_sample_addr <= '0';
if phase_h = timing_addr then
do_sample_addr <= '1';
end if;
do_probe_end <= '0';
if phase_h = c_probe_end then
do_probe_end <= '1';
end if;
if serve_vic='1' then
if phase_l = (c_sample_vic - c_memdelay) then
inhibit <= serve_en_i;
elsif phase_l = (c_sample_vic - 1) then
do_sample_addr <= '1';
end if;
end if;
if phase_l = c_sample_vic then
inhibit <= '0';
end if;
do_sample_io <= '0';
if phase_h = c_io - 1 then
do_sample_io <= '1';
end if;
if reset='1' then
allow_tick_h <= true;
allow_tick_l <= true;
phase_h <= 63;
phase_l <= 63;
inhibit <= '0';
clock_det <= '0';
end if;
end if;
end process;
allow_serve <= serve_en_i;
end gideon;
| gpl-3.0 | 7d9165d4bf67dffe135751f44a507b73 | 0.429187 | 3.710997 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_source/slot_bus_pkg.vhd | 1 | 2,502 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package slot_bus_pkg is
type t_slot_req is record
bus_address : unsigned(15 downto 0); -- for async reads and direct bus writes
bus_rwn : std_logic; -- for async reads and writes
bus_write : std_logic; -- Qualified write condition after setup
io_address : unsigned(15 downto 0); -- for late reads/writes
io_read : std_logic;
io_read_early : std_logic;
io_write : std_logic;
late_write : std_logic;
data : std_logic_vector(7 downto 0);
rom_access : std_logic; -- synchronized version of ROML and ROMH combined
sample_io : std_logic; -- timing signal, pulses when IO lines and address should be stable
end record;
type t_slot_resp is record
data : std_logic_vector(7 downto 0);
reg_output : std_logic;
irq : std_logic;
nmi : std_logic;
end record;
constant c_slot_req_init : t_slot_req := (
bus_address => X"0000",
bus_rwn => '1',
bus_write => '0',
io_read_early => '0',
io_address => X"0000",
io_read => '0',
io_write => '0',
late_write => '0',
rom_access => '0',
sample_io => '0',
data => X"00" );
constant c_slot_resp_init : t_slot_resp := (
data => X"00",
reg_output => '0',
irq => '0',
nmi => '0' );
type t_slot_req_array is array(natural range <>) of t_slot_req;
type t_slot_resp_array is array(natural range <>) of t_slot_resp;
function or_reduce(ar: t_slot_resp_array) return t_slot_resp;
end package;
package body slot_bus_pkg is
function or_reduce(ar: t_slot_resp_array) return t_slot_resp is
variable ret : t_slot_resp;
begin
ret := c_slot_resp_init;
for i in ar'range loop
ret.reg_output := ret.reg_output or ar(i).reg_output;
if ar(i).reg_output='1' then
ret.data := ret.data or ar(i).data;
end if;
ret.irq := ret.irq or ar(i).irq;
ret.nmi := ret.nmi or ar(i).nmi;
end loop;
return ret;
end function or_reduce;
end package body;
| gpl-3.0 | 1933c47a717c51abb4feb912fb49d689 | 0.498002 | 3.674009 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_c5/nios/nios_inst.vhd | 1 | 7,793 | component nios is
port (
clk50_clk : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
mem32_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
mem32_direction : in std_logic := 'X'; -- direction
mem32_byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byte_en
mem32_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
mem32_request : in std_logic := 'X'; -- request
mem32_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- tag
mem32_dack_tag : out std_logic_vector(7 downto 0); -- dack_tag
mem32_rdata : out std_logic_vector(31 downto 0); -- rdata
mem32_rack : out std_logic; -- rack
mem32_rack_tag : out std_logic_vector(7 downto 0); -- rack_tag
memory_mem_a : out std_logic_vector(13 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
memory_mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
memory_mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
memory_mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
memory_mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
memory_mem_dm : out std_logic_vector(0 downto 0); -- mem_dm
memory_mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
memory_mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
memory_mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
oct_rzqin : in std_logic := 'X'; -- rzqin
pio_in_port : in std_logic_vector(31 downto 0) := (others => 'X'); -- in_port
pio_out_port : out std_logic_vector(31 downto 0); -- out_port
reset_reset_n : in std_logic := 'X'; -- reset_n
status_local_init_done : out std_logic; -- local_init_done
status_local_cal_success : out std_logic; -- local_cal_success
status_local_cal_fail : out std_logic; -- local_cal_fail
sys_clock_clk : out std_logic; -- clk
sys_reset_reset_n : out std_logic -- reset_n
);
end component nios;
u0 : component nios
port map (
clk50_clk => CONNECTED_TO_clk50_clk, -- clk50.clk
io_ack => CONNECTED_TO_io_ack, -- io.ack
io_rdata => CONNECTED_TO_io_rdata, -- .rdata
io_read => CONNECTED_TO_io_read, -- .read
io_wdata => CONNECTED_TO_io_wdata, -- .wdata
io_write => CONNECTED_TO_io_write, -- .write
io_address => CONNECTED_TO_io_address, -- .address
io_irq => CONNECTED_TO_io_irq, -- .irq
mem32_address => CONNECTED_TO_mem32_address, -- mem32.address
mem32_direction => CONNECTED_TO_mem32_direction, -- .direction
mem32_byte_en => CONNECTED_TO_mem32_byte_en, -- .byte_en
mem32_wdata => CONNECTED_TO_mem32_wdata, -- .wdata
mem32_request => CONNECTED_TO_mem32_request, -- .request
mem32_tag => CONNECTED_TO_mem32_tag, -- .tag
mem32_dack_tag => CONNECTED_TO_mem32_dack_tag, -- .dack_tag
mem32_rdata => CONNECTED_TO_mem32_rdata, -- .rdata
mem32_rack => CONNECTED_TO_mem32_rack, -- .rack
mem32_rack_tag => CONNECTED_TO_mem32_rack_tag, -- .rack_tag
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.rzqin
pio_in_port => CONNECTED_TO_pio_in_port, -- pio.in_port
pio_out_port => CONNECTED_TO_pio_out_port, -- .out_port
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
status_local_init_done => CONNECTED_TO_status_local_init_done, -- status.local_init_done
status_local_cal_success => CONNECTED_TO_status_local_cal_success, -- .local_cal_success
status_local_cal_fail => CONNECTED_TO_status_local_cal_fail, -- .local_cal_fail
sys_clock_clk => CONNECTED_TO_sys_clock_clk, -- sys_clock.clk
sys_reset_reset_n => CONNECTED_TO_sys_reset_reset_n -- sys_reset.reset_n
);
| gpl-3.0 | 6ebb09912a4a4da4c369020f8294f8ea | 0.42243 | 3.646701 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/xilinx_primitives/RAMB16_S9_S18.vhd | 1 | 11,228 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : RAMB16_S9_S18
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Altera wrapper
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity RAMB16_S9_S18 is
generic (
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000";
INIT_B : bit_vector := X"000000000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "READ_FIRST";
WRITE_MODE_B : string := "READ_FIRST"
);
port (
DOA : out std_logic_vector(7 downto 0);
DOB : out std_logic_vector(15 downto 0);
DOPA : out std_logic_vector(0 downto 0);
DOPB : out std_logic_vector(1 downto 0);
ADDRA : in std_logic_vector(10 downto 0);
ADDRB : in std_logic_vector(9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(7 downto 0);
DIB : in std_logic_vector(15 downto 0);
DIPA : in std_logic_vector(0 downto 0);
DIPB : in std_logic_vector(1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end entity;
architecture wrapper of RAMB16_S9_S18 is
signal wren_a : std_logic;
signal wren_b : std_logic;
begin
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 2048,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 11,
widthad_b => 10,
width_a => 8,
width_b => 16,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => ADDRA,
address_b => ADDRB,
clock0 => CLKA,
clock1 => CLKB,
data_a => DIA,
data_b => DIB,
rden_a => ENA,
rden_b => ENB,
wren_a => wren_a,
wren_b => wren_b,
q_a => DOA,
q_b => DOB );
wren_a <= WEA and ENA;
wren_b <= WEB and ENB;
end architecture;
| gpl-3.0 | d496525d623b573510363ca522773182 | 0.664232 | 5.291235 | false | false | false | false |
keyru/hdl-make | tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd | 2 | 1,403 | ----------------------------------------------------------
-- Design : Simple testbench for an 8-bit VHDL counter
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity counter_tb is -- entity declaration
end counter_tb;
-----------------------------------------------------------------------
architecture testbench of counter_tb is
component counter
port(
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal t_clock: std_logic;
signal t_clear: std_logic;
signal t_count: std_logic;
signal t_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter port map (t_clock, t_clear, t_count, t_Q);
process
begin
t_clock <= '0'; -- clock cycle is 10 ns
wait for 5 ns;
t_clock <= '1';
wait for 5 ns;
end process;
process
begin
t_clear <= '1'; -- start counting
t_count <= '1';
wait for 50 ns;
t_clear <= '0'; -- clear output
wait for 1000 ns;
report "Testbench of Adder completed successfully!"
severity note;
wait;
end process;
end testbench;
----------------------------------------------------------------
| gpl-3.0 | 9f4ff20cb9102290cfcff314d15e52a1 | 0.466857 | 3.941011 | false | true | false | false |
markusC64/1541ultimate2 | fpga/devices/vhdl_sim/microwire_eeprom_tb.vhd | 1 | 3,853 | --------------------------------------------------------------------------------
-- Entity: microwire_eeprom_tb
-- Date:2018-08-14
-- Author: gideon
--
-- Description: Testbench for EEPROM
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
entity microwire_eeprom_tb is
end entity;
architecture test of microwire_eeprom_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal sel_in : std_logic := '0';
signal clk_in : std_logic := '0';
signal data_in : std_logic := '0';
signal data_out : std_logic := '0';
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.microwire_eeprom
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
sel_in => sel_in,
clk_in => clk_in,
data_in => data_in,
data_out => data_out
);
i_bfm: entity work.io_bus_bfm
generic map(
g_name => "io"
)
port map(
clock => clock,
req => io_req,
resp => io_resp
);
p_test: process
procedure command(opcode : std_logic_vector(1 downto 0); address : unsigned;
data : std_logic_vector; extra_clocks : natural := 0) is
begin
clk_in <= '0';
data_in <= '1';
wait for 500 ns;
sel_in <= '1';
wait for 200 ns;
if data_out /= '1' then
wait until data_out = '1';
end if;
wait for 200 ns;
clk_in <= '1';
wait for 500 ns;
clk_in <= '0';
for i in opcode'range loop
data_in <= opcode(i);
wait for 500 ns;
clk_in <= '1';
wait for 500 ns;
clk_in <= '0';
end loop;
for i in address'range loop
data_in <= address(i);
wait for 500 ns;
clk_in <= '1';
wait for 500 ns;
clk_in <= '0';
end loop;
for i in data'range loop
data_in <= data(i);
wait for 500 ns;
clk_in <= '1';
wait for 500 ns;
clk_in <= '0';
end loop;
data_in <= '1';
for i in 1 to extra_clocks loop
wait for 500 ns;
clk_in <= '1';
wait for 500 ns;
clk_in <= '0';
end loop;
sel_in <= '0';
wait for 500 ns;
end procedure;
constant c_no_data : std_logic_vector(-1 downto 0) := (others => '0');
begin
wait until reset = '0';
wait for 1 us;
command("00", "1100000000", c_no_data); -- write enable
command("01", "0000000001", X"1234"); -- write
command("10", "0000000000", c_no_data, 64); -- read
command("00", "0100000000", X"5678"); -- write all
command("00", "1000001011", c_no_data); -- erase all
command("01", "0000010001", X"1234"); -- write
command("11", "0000010001", c_no_data); -- erase one
report "Invalid writes";
command("01", "000000000", X"3456"); -- invalid write, as address is too short
command("01", "00000000000", X"3456"); -- invalid write, as address is too long
command("00", "0000000000", c_no_data); -- write disable
wait;
end process;
end architecture;
| gpl-3.0 | 58558eb4d8e485291059855a21fe7bea | 0.440696 | 3.984488 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_sim/mblite_simu_wrapped.vhd | 1 | 9,132 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
library std;
use std.textio.all;
entity mblite_simu_wrapped is
end entity;
architecture test of mblite_simu_wrapped is
signal clock : std_logic := '0';
signal reset : std_logic;
signal mb_reset : std_logic := '1';
signal mem_req : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp : t_mem_resp_32;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_busy : std_logic;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
signal irqs : std_logic_vector(7 downto 0) := X"00";
signal plaag_interrupt : std_logic := '0';
signal invalidate : std_logic := '0';
signal inv_addr : std_logic_vector(31 downto 0) := X"00003FFC";
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 4194303) := (1024 => X"00000000", others => X"F0000000"); -- 16MB
signal last_char : std_logic_vector(7 downto 0);
constant g_latency : natural := 1;
signal pipe : t_mem_req_32_array(0 to g_latency-1) := (others => c_mem_req_32_init);
signal isr, yield, leave1, leave2 : std_logic := '0';
signal task : std_logic_vector(7 downto 0) := X"FF";
signal curTCB, save, restore, critical : std_logic_vector(31 downto 0) := (others => 'X');
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
mb_reset <= '1', '0' after 2 us;
--plaag_interrupt <= transport '0', '1' after 25 ms, '0' after 30 ms;
i_core: entity work.mblite_wrapper
generic map (
g_icache => false,
g_dcache => false,
g_tag_i => X"0A",
g_tag_d => X"0B"
)
port map (
clock => clock,
reset => reset,
irq_i => irq_i,
irq_o => irq_o,
mb_reset => mb_reset,
disable_i => '0',
disable_d => '0',
invalidate => invalidate,
inv_addr => inv_addr,
io_req => io_req,
io_resp => io_resp,
io_busy => io_busy,
mem_req => mem_req,
mem_resp => mem_resp
);
process
begin
wait until reset='0';
wait until clock='1';
wait until clock='1';
while true loop
invalidate <= '0';
wait until clock='1';
invalidate <= '0';
wait until clock='1';
wait until clock='1';
end loop;
end process;
-- IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
variable irqdiv : natural := 50000;
variable irqdiv2 : natural := 60000;
variable not_ready : natural := 3;
begin
if rising_edge(clock) then
if irqdiv = 0 then
irqs(0) <= '1';
irqdiv := 400000;
else
irqdiv := irqdiv - 1;
end if;
-- if irqdiv2 = 0 then
-- irqs(2) <= '1';
-- irqdiv2 := 97127;
-- else
-- irqdiv2 := irqdiv2 - 1;
-- end if;
io_resp <= c_io_resp_init;
leave1 <= '0';
leave2 <= '0';
if io_req.write = '1' then
io_resp.ack <= '1';
case io_req.address is
when X"00028" => -- enter IRQ
isr <= '1';
when X"00029" => -- enter yield
yield <= '1';
when X"0002A" => -- leave
isr <= '0';
yield <= '0';
if io_req.data(1) = '1' then
leave1 <= '1'; -- with IRQ ON
else
leave2 <= '1'; -- with IRQ OFF
end if;
when X"00000" => -- interrupt
null;
when X"60304" => -- profiler
null;
when X"60305" => -- profiler
task <= io_req.data;
null;
when X"00004" => -- interupt ack
irqs <= irqs and not io_req.data;
when X"00010" => -- UART_DATA
not_ready := 500;
byte := io_req.data;
char := character'val(to_integer(unsigned(byte)));
last_char <= byte;
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
null;
-- report "I/O write to " & hstr(io_req.address) & " dropped";
end case;
end if;
if io_req.read = '1' then
io_resp.ack <= '1';
case io_req.address is
when X"00005" => -- IRQ Flags
io_resp.data <= irqs;
when X"0000C" => -- Capabilities 11D447B9
io_resp.data <= X"11";
when X"0000D" => -- Capabilities 11D447B9
io_resp.data <= X"D4";
when X"0000E" => -- Capabilities 11D447B9
io_resp.data <= X"47";
when X"0000F" => -- Capabilities 11D447B9
io_resp.data <= X"99";
when X"00012" => -- UART_FLAGS
if not_ready > 0 then
io_resp.data <= X"50";
not_ready := not_ready - 1;
else
io_resp.data <= X"40";
end if;
when X"2000A" => -- 1541_A memmap
io_resp.data <= X"3F";
when X"2000B" => -- 1541_A audiomap
io_resp.data <= X"3E";
when others =>
-- report "I/O read to " & hstr(io_req.address) & " dropped";
io_resp.data <= X"00";
end case;
end if;
irqs(7) <= plaag_interrupt;
if reset = '1' then
irqs <= X"00";
end if;
end if;
end process;
-- memory
process(clock)
variable addr : natural;
begin
if rising_edge(clock) then
mem_resp <= c_mem_resp_32_init;
pipe(g_latency-1) <= c_mem_req_32_init;
if mem_req.request = '1' and mem_resp.rack = '0' then
mem_resp.rack <= '1';
mem_resp.rack_tag <= mem_req.tag;
pipe(g_latency-1) <= mem_req;
assert mem_req.address(1 downto 0) = "00" report "Lower address bits are non-zero!" severity warning;
if mem_req.read_writen = '0' then
case to_integer(mem_req.address) is
when 16|20 =>
report "Write to illegal address!"
severity warning;
-- when 16#16d20# =>
-- report "Debug: Writing Current TCB to " & hstr(mem_req.data);
-- curTCB <= mem_req.data;
---- when 16#16954# =>
---- critical <= mem_req.data;
-- when 16#FFC# =>
-- report "Debug: Save context, TCB = " & hstr(mem_req.data);
-- save <= mem_req.data;
-- when 16#FF8# =>
-- report "Debug: Restore context, TCB = " & hstr(mem_req.data);
-- restore <= mem_req.data;
when others =>
end case;
end if;
end if;
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
mem_resp.dack_tag <= (others => '0');
mem_resp.data <= (others => '0');
if pipe(0).request='1' then
addr := to_integer(pipe(0).address(21 downto 2));
if pipe(0).read_writen='1' then
mem_resp.dack_tag <= pipe(0).tag;
mem_resp.data <= memory(addr);
else
for i in 0 to 3 loop
if pipe(0).byte_en(i)='1' then
memory(addr)(i*8+7 downto i*8) := pipe(0).data(i*8+7 downto i*8);
end if;
end loop;
end if;
end if;
end if;
end process;
irq_i <= '1' when irqs /= X"00" else '0';
end architecture;
| gpl-3.0 | d1841155528876de1fe0f8fbd62f235a | 0.430245 | 3.890925 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/ulpi_bus.vhd | 1 | 8,708 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
operational : in std_logic := '1';
-- chirp interface
do_chirp : in std_logic := '0';
chirp_data : in std_logic := '0';
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
-- for the tracer
rx_cmd : out std_logic;
rx_ourdata : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of ulpi_bus : entity is "yes";
end ulpi_bus;
architecture gideon of ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_stp_d1 : std_logic; -- for signaltap only
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
signal bus_has_our_data : std_logic;
type t_state is ( idle, chirp, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1 and operational;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d3;
rx_cmd <= rx_status_i;
rx_ourdata <= not ulpi_dir_d1 and ulpi_nxt_d1; -- next = 1 and dir = 0, same delay as rx_data (1)
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
ulpi_stp_d1 <= ulpi_stop;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif do_chirp='1' then
if ULPI_DIR='0' then
ulpi_last <= '0';
state <= chirp;
end if;
ulpi_data_out <= X"40"; -- PIDless packet
elsif tx_valid = '1' and tx_start = '1' then
if ULPI_DIR='0' then
ulpi_last <= tx_last;
state <= transmit;
end if;
ulpi_data_out <= tx_data;
end if;
when chirp =>
if ULPI_NXT = '1' then
if do_chirp = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= (others => chirp_data);
end if;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_DIR='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
elsif ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
when writing_data =>
if ULPI_DIR='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
elsif ULPI_NXT='1' then
ulpi_data_out <= X"00";
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '1';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write, bus_has_our_data)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start; -- first byte is transferred to register
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and bus_has_our_data and tx_valid and not ulpi_last; -- phy accepted this data.
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when bus_has_our_data = '1' else (others => 'Z');
bus_has_our_data <= '1' when ULPI_DIR='0' and ulpi_dir_d1='0' else '0';
end gideon;
| gpl-3.0 | 83f0c823d4307df5bb7398999e8da252 | 0.441203 | 3.776236 | false | false | false | false |
xiadz/oscilloscope | ipcore_dir/trace_memory.vhd | 1 | 5,789 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file trace_memory.vhd when simulating
-- the core, trace_memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY trace_memory IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END trace_memory;
ARCHITECTURE trace_memory_a OF trace_memory IS
-- synthesis translate_off
COMPONENT wrapped_trace_memory
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_trace_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v6_1(behavioral)
GENERIC MAP (
c_addra_width => 13,
c_addrb_width => 13,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 1,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 1,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 5974,
c_read_depth_b => 5974,
c_read_width_a => 9,
c_read_width_b => 9,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 5974,
c_write_depth_b => 5974,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 9,
c_write_width_b => 9,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_trace_memory
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => rstb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END trace_memory_a;
| mit | cafe8bf81969c85304d65be2d58503b8 | 0.536017 | 3.935418 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/altera/avalon_usb.vhd | 1 | 3,875 | --------------------------------------------------------------------------------
-- Entity: avalon_usb
-- Date:2016-11-03
-- Author: Gideon
--
-- Description: AvalonMM wrapper around usb peripheral for use in QSYS
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity avalon_usb is
port (
sys_clock : in std_logic;
sys_reset : in std_logic;
-- 8 bits Avalon bus interface
avs_read : in std_logic;
avs_write : in std_logic;
avs_address : in std_logic_vector(12 downto 0);
avs_writedata : in std_logic_vector(7 downto 0);
avs_ready : out std_logic;
avs_readdata : out std_logic_vector(7 downto 0);
avs_readdatavalid : out std_logic;
avs_irq : out std_logic;
-- Memory master port for DMA
avm_read : out std_logic;
avm_write : out std_logic;
avm_address : out std_logic_vector(25 downto 0);
avm_writedata : out std_logic_vector(31 downto 0);
avm_byteenable : out std_logic_vector(3 downto 0);
avm_ready : in std_logic;
avm_readdata : in std_logic_vector(31 downto 0);
avm_readdatavalid : in std_logic;
-- Conduit with ULPI signals
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
ulpi_nxt : in std_logic;
ulpi_dir : in std_logic;
ulpi_stp : out std_logic;
ulpi_data : inout std_logic_vector(7 downto 0));
end entity;
architecture arch of avalon_usb is
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
begin
i_bridge: entity work.avalon_to_io_bridge
port map (
clock => sys_clock,
reset => sys_reset,
avs_read => avs_read,
avs_write => avs_write,
avs_address(19 downto 13) => "0000000",
avs_address(12 downto 0) => avs_address,
avs_writedata => avs_writedata,
avs_ready => avs_ready,
avs_readdata => avs_readdata,
avs_readdatavalid => avs_readdatavalid,
avs_irq => open,
io_read => io_req.read,
io_write => io_req.write,
unsigned(io_address) => io_req.address,
io_wdata => io_req.data,
io_rdata => io_resp.data,
io_ack => io_resp.ack,
io_irq => '0'
);
i_wrapped: entity work.usb_host_nano
generic map(
g_big_endian => false,
g_tag => X"01",
g_simulation => false
)
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ulpi_nxt => ulpi_nxt,
ulpi_dir => ulpi_dir,
ulpi_stp => ulpi_stp,
ulpi_data => ulpi_data,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_mem_req => mem_req,
sys_mem_resp => mem_resp,
sys_io_req => io_req,
sys_io_resp => io_resp,
sys_irq => avs_irq
);
avm_read <= mem_req.read_writen and mem_req.request;
avm_write <= not mem_req.read_writen and mem_req.request;
avm_address <= std_logic_vector(mem_req.address);
avm_byteenable <= mem_req.byte_en;
avm_writedata <= mem_req.data;
mem_resp.data <= avm_readdata;
mem_resp.dack_tag <= X"01" when avm_readdatavalid='1' else X"00";
mem_resp.rack_tag <= X"01" when avm_ready='1' else X"00";
mem_resp.rack <= avm_ready;
end arch;
| gpl-3.0 | 55f9fb1137e79a951b858a6519b9d147 | 0.498581 | 3.571429 | false | false | false | false |
asicguy/crash | fpga/src/common/debounce.vhd | 2 | 3,388 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: debounce.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Debounces input by sampling the input single twice
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity debounce is
generic (
CLOCK_FREQ : integer := 100e6; -- Clock frequency (Hz)
SAMPLE_TIME : integer := 10); -- Time between debounce samples (millseconds)
port (
clk : in std_logic; -- Clock
reset : in std_logic; -- Active high reset
input_async : in std_logic; -- Asynchronous input to debounce
input_sync : out std_logic); -- Debounced synchronous input
end entity;
architecture RTL of debounce is
-----------------------------------------------------------------------------
-- Constants Declaration
-----------------------------------------------------------------------------
constant DEBOUNCE_PERIOD : integer := integer((real(SAMPLE_TIME)/(1.0/real(CLOCK_FREQ)))/1.0e3);
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
signal debounce_cnt : integer range 0 to DEBOUNCE_PERIOD-1;
signal input_async_meta1 : std_logic;
signal input_async_meta2 : std_logic;
signal input_async_samp1 : std_logic;
signal input_async_samp2 : std_logic;
begin
proc_debounce : process(clk,reset)
begin
if (reset = '1') then
debounce_cnt <= 0;
input_async_meta1 <= '0';
input_async_meta2 <= '0';
input_async_samp1 <= '0';
input_async_samp2 <= '0';
input_sync <= '0';
else
if rising_edge(clk) then
-- Synchronizer
input_async_meta1 <= input_async;
input_async_meta2 <= input_async_meta1;
-- Debounce sampling
if (debounce_cnt = DEBOUNCE_PERIOD-1) then
input_async_samp1 <= input_async_meta2;
input_async_samp2 <= input_async_samp1;
debounce_cnt <= 0;
else
debounce_cnt <= debounce_cnt + 1;
end if;
-- Only update output on stable input
if (input_async_samp1 = '1' AND input_async_samp2 = '1') then
input_sync <= '1';
elsif (input_async_samp1 = '0' AND input_async_samp2 = '0') then
input_sync <= '0';
end if;
end if;
end if;
end process;
end architecture; | gpl-3.0 | c279d1171abe85a6b7ecda2a06fc369b | 0.531287 | 4.235 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/command_interface/vhdl_source/command_protocol.vhd | 1 | 14,452 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.command_if_pkg.all;
entity command_protocol is
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req; -- we get a 2K range
io_resp : out t_io_resp;
io_irq : out std_logic;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
write_ff00 : in std_logic := '0';
-- block memory
address : out unsigned(10 downto 0);
rdata : in std_logic_vector(7 downto 0);
wdata : out std_logic_vector(7 downto 0);
en : out std_logic;
we : out std_logic );
end entity;
-- How does the protocol work?
-- The Ultimate software initializes the command and response buffers that the C64 can write to.
-- Each buffer has a start address, an end address, and a current read/write pointer as seen
-- from the C64 side.
-- The C64 can write into the command buffer and set a handshake flag. The 1541U software
-- triggers on the flag, and reads the write pointer, copies the command, and stores the
-- result and status in their respective buffers, and sets the respective handshake flags back
-- to the C64. The buffers on the ultimate side are direct mapped; on the C64 side, each
-- buffer has its own data register. One bidirectional register (on the C64 side) acts as
-- handshake register. Command queueing is not supported.
-- Protocol:
-- There are 4 states:
-- 00: Ultimate is ready and waiting for new command
-- 01: C64 has written data into the Ultimate command buffer, and the Ultimate is processing it
-- 11: Ultimate has processed the command and replied with data/status. This is not the last data.
-- 10: Ultimate has processed the command and replied with data/status. This is the last data.
-- The status register (seen by the C64) holds the following bits:
-- Bit 7: Response data available
-- Bit 6: Status data available
-- Bit 5..4: State
-- Bit 3: Error flag (write 1 to clear)
-- Bit 2: Abort flag set (cleared by Ultimate software)
-- Bit 1: Data accepted bit set (cleared by Ultimate software)
-- Bit 0: New command (set when new command is written, should NOT be used by C64)
architecture gideon of command_protocol is
signal enabled : std_logic;
signal slot_base : unsigned(6 downto 1);
signal do_write : std_logic;
signal trigger : std_logic;
signal freeze_i : std_logic;
signal irq_mask : std_logic_vector(2 downto 0);
signal command_pointer : unsigned(10 downto 0);
signal response_pointer : unsigned(10 downto 0);
signal status_pointer : unsigned(10 downto 0);
signal command_length : unsigned(10 downto 0);
signal response_length : unsigned(10 downto 0);
signal status_length : unsigned(10 downto 0);
-- signal response_valid : std_logic;
-- signal status_valid : std_logic;
signal rdata_resp : std_logic_vector(7 downto 0);
signal rdata_stat : std_logic_vector(7 downto 0);
signal bus_id : std_logic_vector(7 downto 0) := X"00";
signal slot_status : std_logic_vector(7 downto 0);
alias response_valid : std_logic is slot_status(7);
alias status_valid : std_logic is slot_status(6);
alias state : std_logic_vector(1 downto 0) is slot_status(5 downto 4);
alias error_busy : std_logic is slot_status(3);
alias handshake_in : std_logic_vector(2 downto 0) is slot_status(2 downto 0);
begin
-- assert false report integer'image(to_integer(c_cmd_if_command_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_response_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_status_buffer_end)) severity warning;
--
command_length <= command_pointer - c_cmd_if_command_buffer_addr;
with slot_req.bus_address(2 downto 0) select slot_resp.data <=
slot_status when c_cif_slot_control,
X"C9" when c_cif_slot_command,
rdata_resp when c_cif_slot_response,
rdata_stat when c_cif_slot_status,
bus_id when c_cif_bus_id,
X"FF" when others;
rdata_resp <= rdata when response_valid='1' else X"00";
rdata_stat <= rdata when status_valid='1' else X"00";
slot_resp.reg_output <= enabled when slot_req.bus_address(8 downto 3) = slot_base else '0';
slot_resp.irq <= '0';
slot_resp.nmi <= '0';
-- signals to RAM
en <= enabled;
we <= do_write;
wdata <= slot_req.data;
address <= command_pointer when do_write='1' else
response_pointer when slot_req.bus_address(0)='0' else
status_pointer;
do_write <= '1' when slot_req.io_write='1' and slot_req.io_address(8 downto 0) = (slot_base & c_cif_slot_command) else '0';
p_control: process(clock)
procedure reset_response is
begin
response_pointer <= c_cmd_if_response_buffer_addr;
status_pointer <= c_cmd_if_status_buffer_addr;
end procedure;
begin
if rising_edge(clock) then
if (response_pointer - c_cmd_if_response_buffer_addr) < response_length then
response_valid <= state(1) and not handshake_in(2); -- Only in data state when abort is not set
else
response_valid <= '0';
end if;
if (status_pointer - c_cmd_if_status_buffer_addr) < status_length then
status_valid <= state(1) and not handshake_in(2); -- Only in data state when abort is not set
else
status_valid <= '0';
end if;
if (slot_req.io_address(8 downto 3) = slot_base) and (enabled = '1') then
if slot_req.io_write='1' then
case slot_req.io_address(2 downto 0) is
when c_cif_slot_command =>
if command_pointer /= c_cmd_if_command_buffer_end then
command_pointer <= command_pointer + 1;
end if;
when c_cif_slot_control =>
if slot_req.data(3)='1' then
error_busy <= '0';
end if;
if slot_req.data(0)='1' then
freeze_i <= slot_req.data(7);
trigger <= slot_req.data(6);
if state = "00" then
state <= "01";
handshake_in(0) <= '1';
else
error_busy <= '1';
end if;
end if;
if slot_req.data(1)='1' and state(1) = '1' then -- data accept
handshake_in(1) <= state(0); -- data accepted, only ultimate can clear it, only data more
state(1) <= '0'; -- either goes to idle, or back to wait for software
end if;
if slot_req.data(2)='1' then
handshake_in(2) <= '1'; -- abort, only ultimate can clear it.
end if;
when others =>
null;
end case;
elsif slot_req.io_read='1' then
case slot_req.io_address(2 downto 0) is
when c_cif_slot_response =>
if response_pointer /= c_cmd_if_response_buffer_end then
response_pointer <= response_pointer + 1;
end if;
when c_cif_slot_status =>
if status_pointer /= c_cmd_if_status_buffer_end then
status_pointer <= status_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
if write_ff00 = '1' and trigger = '1' then
freeze_i <= '1';
trigger <= '0';
end if;
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
slot_base <= unsigned(io_req.data(slot_base'range));
when c_cif_io_slot_enable =>
if io_req.data(7) = '0' then
enabled <= io_req.data(0);
else
bus_id(4 downto 0) <= io_req.data(4 downto 0); -- max 31 (valid: 4-30)
end if;
when c_cif_io_handshake_out =>
if io_req.data(0)='1' then -- reset
handshake_in(0) <= '0';
command_pointer <= c_cmd_if_command_buffer_addr;
end if;
if io_req.data(1)='1' then -- data seen
handshake_in(1) <= '0';
end if;
if io_req.data(2)='1' then -- abort bit
handshake_in(2) <= '0';
end if;
if io_req.data(4)='1' then -- validate data
trigger <= '0';
freeze_i <= '0';
state(1) <= '1';
state(0) <= io_req.data(5); -- more bit
reset_response;
end if;
if io_req.data(7)='1' then
freeze_i <= '0';
trigger <= '0';
reset_response;
state <= "00";
end if;
when c_cif_io_status_length =>
status_pointer <= c_cmd_if_status_buffer_addr;
status_length(7 downto 0) <= unsigned(io_req.data); -- FIXME
when c_cif_io_response_len_l =>
response_pointer <= c_cmd_if_response_buffer_addr;
response_length(7 downto 0) <= unsigned(io_req.data);
when c_cif_io_response_len_h =>
response_length(10 downto 8) <= unsigned(io_req.data(2 downto 0));
when c_cif_io_irq_mask =>
irq_mask <= io_req.data(2 downto 0);
when c_cif_io_irq_mask_set =>
irq_mask <= irq_mask or io_req.data(2 downto 0);
when c_cif_io_irq_mask_clear =>
irq_mask <= irq_mask and not io_req.data(2 downto 0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
io_resp.data(slot_base'range) <= std_logic_vector(slot_base);
when c_cif_io_slot_enable =>
io_resp.data(0) <= enabled;
when c_cif_io_handshake_out =>
io_resp.data(7) <= freeze_i;
io_resp.data(6) <= trigger;
io_resp.data(5 downto 4) <= state;
when c_cif_io_handshake_in =>
io_resp.data <= slot_status;
when c_cif_io_command_start =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_addr(10 downto 3));
when c_cif_io_command_end =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_end(10 downto 3));
when c_cif_io_response_start =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_addr(10 downto 3));
when c_cif_io_response_end =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_end(10 downto 3));
when c_cif_io_status_start =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_addr(10 downto 3));
when c_cif_io_status_end =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_end(10 downto 3));
when c_cif_io_status_length =>
io_resp.data <= std_logic_vector(status_pointer(7 downto 0)); -- fixme
when c_cif_io_response_len_l =>
io_resp.data <= std_logic_vector(response_pointer(7 downto 0));
when c_cif_io_response_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(response_pointer(10 downto 8));
when c_cif_io_command_len_l =>
io_resp.data <= std_logic_vector(command_length(7 downto 0));
when c_cif_io_command_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(command_length(10 downto 8));
when c_cif_io_irq_mask =>
io_resp.data(2 downto 0) <= irq_mask;
when others =>
null;
end case;
end if;
if reset='1' then
command_pointer <= c_cmd_if_command_buffer_addr;
reset_response;
response_length <= (others => '0');
status_length <= (others => '0');
irq_mask <= "111";
handshake_in <= "000";
state <= "00";
enabled <= '0';
error_busy <= '0';
slot_base <= (others => '0');
freeze_i <= '0';
trigger <= '0';
end if;
end if;
end process;
io_irq <= '1' when (handshake_in and not irq_mask) /= "000" else '0';
freeze <= freeze_i;
end architecture;
| gpl-3.0 | 57db50c130c7725ae3b5432ac1af0f99 | 0.493634 | 3.995576 | false | false | false | false |
xiadz/oscilloscope | src/n_cycles_delayer.vhd | 1 | 1,491 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 17:31:43 05/22/2011
--
-- Description: This entity delays given signal of width signal_width by n clock cycles.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity n_cycles_delayer is
generic (
n : integer range 2 to 1024;
signal_width : integer range 1 to 1024
);
port (
nrst : in std_logic;
clk : in std_logic;
input : in std_logic_vector (signal_width - 1 downto 0);
output : out std_logic_vector (signal_width - 1 downto 0)
);
end n_cycles_delayer;
architecture behavioral of n_cycles_delayer is
type delay_array_t is array (n - 1 downto 0) of std_logic_vector (signal_width - 1 downto 0);
signal delay_array: delay_array_t ;--:= (others => (others => '0'));
begin
output <= delay_array (n - 1);
process (clk, nrst) is
variable i : integer range 0 to n - 2;
begin
if nrst = '0' then
for i in 0 to n - 1 loop
delay_array (i) <= (others => '0');
end loop;
elsif rising_edge (clk) then
delay_array (0) <= input;
for i in 0 to (n - 2) loop
delay_array (i + 1) <= delay_array (i);
end loop;
end if;
end process;
end architecture behavioral;
| mit | 2a5d8d9e882c028eafafb2c2d5ee3b61 | 0.499665 | 4.02973 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_source/io_to_dma_bridge.vhd | 1 | 1,805 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.dma_bus_pkg.all;
entity io_to_dma_bridge is
generic (
g_ignore_stop : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
c64_stopped : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp );
end entity;
architecture rtl of io_to_dma_bridge is
signal dma_req_i : t_dma_req := c_dma_req_init;
begin
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if dma_resp.rack='1' then
dma_req_i.request <= '0';
if dma_req_i.read_writen='0' then -- was write
io_resp.ack <= '1';
end if;
end if;
if dma_resp.dack='1' then
io_resp.data <= dma_resp.data;
io_resp.ack <= '1';
end if;
if io_req.write='1' or io_req.read = '1' then
dma_req_i.address <= io_req.address(15 downto 0);
dma_req_i.read_writen <= io_req.read;
dma_req_i.data <= io_req.data;
if c64_stopped='1' or g_ignore_stop then
dma_req_i.request <= '1';
else
io_resp.ack <= '1';
end if;
end if;
if reset='1' then
dma_req_i.request <= '0';
end if;
end if;
end process;
dma_req <= dma_req_i;
end architecture;
| gpl-3.0 | ebe9279698b27f832eca40b877aa0c7a | 0.441551 | 3.464491 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_sim/tb_ulpi_interface.vhd | 2 | 2,483 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_interface is
end entity;
architecture tb of tb_ulpi_interface is
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.usb1_ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
-- fifo interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_command => rx_command,
rx_last => rx_last,
rx_valid => rx_valid );
i_bfm: entity work.usb1_ulpi_phy_bfm
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
p_test: process
procedure tx_packet(invec : t_std_logic_8_vector; last : boolean) is
begin
wait until clock='1';
tx_start <= '1';
for i in invec'range loop
tx_data <= invec(i);
tx_valid <= '1';
if i = invec'right and last then
tx_last <= '1';
else
tx_last <= '0';
end if;
wait until clock='1';
tx_start <= '0';
while tx_next = '0' loop
wait until clock='1';
end loop;
end loop;
tx_valid <= '0';
end procedure;
begin
wait for 500 ns;
tx_packet((X"40", X"01", X"02", X"03", X"04"), true);
wait for 300 ns;
tx_packet((X"81", X"15"), true);
wait for 300 ns;
tx_packet((0 => X"C2"), false);
wait;
end process;
end tb;
| gpl-3.0 | ad05511c63c59cc0a8dfb43f007aae86 | 0.448248 | 3.733835 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/iec_interface/vhdl_source/iec_processor_io.vhd | 1 | 8,959 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 260/111/136/1
library work;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity iec_processor_io is
port (
clock : in std_logic;
reset : in std_logic;
tick : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
irq : out std_logic;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
end iec_processor_io;
architecture structural of iec_processor_io is
signal proc_reset : std_logic;
signal enable : std_logic;
-- irq
signal irq_event : std_logic;
signal irq_enable : std_logic;
signal irq_status : std_logic;
-- instruction ram interface
signal instr_addr : unsigned(8 downto 0);
signal instr_en : std_logic;
signal instr_data : std_logic_vector(31 downto 0);
-- software fifo interface
signal up_fifo_get : std_logic;
signal up_fifo_put : std_logic;
signal up_fifo_din : std_logic_vector(8 downto 0);
signal up_fifo_dout : std_logic_vector(8 downto 0);
signal up_fifo_empty : std_logic;
signal up_fifo_full : std_logic;
signal up_fifo_count : integer range 0 to 2048;
signal down_fifo_flush : std_logic;
signal down_fifo_empty : std_logic;
signal down_fifo_full : std_logic;
signal down_fifo_release : std_logic;
signal down_fifo_get : std_logic;
signal down_fifo_put : std_logic;
signal down_fifo_din : std_logic_vector(9 downto 0);
signal down_fifo_dout : std_logic_vector(9 downto 0);
signal down_dav : std_logic;
signal down_space : std_logic;
signal ram_en : std_logic;
signal ram_rdata : std_logic_vector(7 downto 0);
signal ram_sel : std_logic;
signal reg_rdata : std_logic_vector(7 downto 0);
begin
i_proc: entity work.iec_processor
port map (
clock => clock,
reset => proc_reset,
tick => tick,
-- instruction ram interface
instr_addr => instr_addr,
instr_en => instr_en,
instr_data => instr_data(29 downto 0),
-- software fifo interface
up_fifo_put => up_fifo_put,
up_fifo_din => up_fifo_din,
up_fifo_full => up_fifo_full,
down_fifo_empty => down_fifo_empty,
down_fifo_get => down_fifo_get,
down_fifo_dout => down_fifo_dout,
down_fifo_flush => down_fifo_flush,
down_fifo_release => down_fifo_release,
irq_event => irq_event,
clk_o => clk_o,
clk_i => clk_i,
data_o => data_o,
data_i => data_i,
atn_o => atn_o,
atn_i => atn_i,
srq_o => srq_o,
srq_i => srq_i );
i_ram: RAMB16_S9_S36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST" )
port map (
DOA => ram_rdata,
ADDRA => std_logic_vector(req.address(10 downto 0)),
CLKA => clock,
DIA => req.data,
DIPA => "0",
ENA => ram_en,
SSRA => '0',
WEA => req.write,
DOB(31 downto 24) => instr_data(7 downto 0), -- CPU is big endian
DOB(23 downto 16) => instr_data(15 downto 8),
DOB(15 downto 8) => instr_data(23 downto 16),
DOB(7 downto 0) => instr_data(31 downto 24),
ADDRB => std_logic_vector(instr_addr),
CLKB => clock,
DIB => X"00000000",
DIPB => X"0",
ENB => instr_en,
SSRB => '0',
WEB => '0' );
i_up_fifo: entity work.sync_fifo
generic map (
g_depth => 2048,
g_data_width => 9,
g_threshold => 500,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => up_fifo_get,
wr_en => up_fifo_put,
din => up_fifo_din,
dout => up_fifo_dout,
flush => proc_reset,
full => up_fifo_full,
almost_full => open,
empty => up_fifo_empty,
count => up_fifo_count );
i_down_fifo: entity work.srl_fifo
generic map (
Width => 10,
Depth => 15, -- 15 is the maximum
Threshold => 13 )
port map (
clock => clock,
reset => proc_reset,
GetElement => down_fifo_get,
PutElement => down_fifo_put,
FlushFifo => down_fifo_flush,
DataIn => down_fifo_din,
DataOut => down_fifo_dout,
SpaceInFifo => down_space,
AlmostFull => open,
DataInFifo => down_dav);
down_fifo_empty <= not down_dav;
down_fifo_full <= not down_space;
process(clock)
-- variable value : unsigned(15 downto 0);
begin
if rising_edge(clock) then
down_fifo_release <= '0';
ram_sel <= '0';
reg_rdata <= (others => '0');
proc_reset <= not enable;
resp.ack <= '0';
-- value := to_unsigned(up_fifo_count, 16);
if req.read='1' then
resp.ack <= '1'; -- data handled outside clocked process if ram
ram_sel <= req.address(11);
case req.address(3 downto 0) is
when X"0" =>
reg_rdata <= X"25"; -- version
when X"1" =>
reg_rdata(0) <= down_fifo_empty;
reg_rdata(1) <= down_fifo_full or down_fifo_flush;
when X"2" =>
reg_rdata(0) <= up_fifo_empty;
reg_rdata(1) <= up_fifo_full;
reg_rdata(7) <= up_fifo_dout(8);
when X"6"|X"8"|X"9"|X"A"|X"B" =>
reg_rdata <= up_fifo_dout(7 downto 0);
when X"7" =>
reg_rdata <= "0000000" & up_fifo_dout(8);
when X"C" =>
reg_rdata <= "0000000" & irq_status;
-- when X"E" =>
-- reg_rdata <= std_logic_vector(value(7 downto 0));
--
-- when X"F" =>
-- reg_rdata <= std_logic_vector(value(15 downto 8));
--
when others => null;
end case;
elsif req.write='1' then
resp.ack <= '1'; -- data handled outside clocked process if ram
if req.address(11)='0' then
case req.address(3 downto 0) is
when X"3" =>
proc_reset <= '1';
enable <= req.data(0);
when X"C" =>
irq_status <= '0';
irq_enable <= req.data(0);
when X"D" =>
down_fifo_release <= '1';
when others =>
null;
end case;
end if;
end if;
if irq_event='1' then
irq_status <= '1';
end if;
irq <= irq_enable and irq_status;
if reset='1' then
proc_reset <= '1';
enable <= '0';
end if;
end if;
end process;
resp.data <= ram_rdata when ram_sel='1' else reg_rdata;
down_fifo_put <= '1' when req.write='1' and req.address(11)='0' and req.address(3 downto 2) = "10" else '0';
up_fifo_get <= '1' when req.read='1' and req.address(11)='0' and ((req.address(3 downto 0) = "0110") or (req.address(3 downto 2) = "10")) else '0';
down_fifo_din <= std_logic_vector(req.address(1 downto 0)) & req.data;
ram_en <= (req.write or req.read) and req.address(11);
end structural;
| gpl-3.0 | 49de4d860cc8bf4d7f39f3944c0903cd | 0.437884 | 3.853333 | false | false | false | false |
asicguy/crash | fpga/src/toplevel/zc702.vhd | 2 | 63,731 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: zc706.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Toplevel file for ZC702.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity zc702 is
port (
-- ARM Connections
MIO : inout std_logic_vector(53 downto 0);
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB_pin : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRP : inout std_logic;
DDR_VRN : inout std_logic;
-- USRP DDR Interface
RX_DATA_CLK_N : in std_logic;
RX_DATA_CLK_P : in std_logic;
RX_DATA_N : in std_logic_vector(6 downto 0);
RX_DATA_P : in std_logic_vector(6 downto 0);
TX_DATA_N : out std_logic_vector(7 downto 0);
TX_DATA_P : out std_logic_vector(7 downto 0);
SPARE : out std_logic;
UART_TX : out std_logic);
end entity;
architecture RTL of zc702 is
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component zc702_ps is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_ext_slave_conn_0_M_AXI_AWADDR_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_AWVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_AWREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_WDATA_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_WSTRB_pin : out std_logic_vector(3 downto 0);
axi_ext_slave_conn_0_M_AXI_WVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_WREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_BRESP_pin : in std_logic_vector(1 downto 0);
axi_ext_slave_conn_0_M_AXI_BVALID_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_BREADY_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_ARADDR_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_ARVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_ARREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_RDATA_pin : in std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_RRESP_pin : in std_logic_vector(1 downto 0);
axi_ext_slave_conn_0_M_AXI_RVALID_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_RREADY_pin : out std_logic;
processing_system7_0_IRQ_F2P_pin : in std_logic_vector(15 downto 0);
processing_system7_0_FCLK_CLK0_pin : out std_logic;
processing_system7_0_FCLK_RESET0_N_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_AWADDR_pin : in std_logic_vector(31 downto 0);
axi_ext_master_conn_0_S_AXI_AWLEN_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_AWSIZE_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_AWBURST_pin : in std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_AWCACHE_pin : in std_logic_vector(3 downto 0);
axi_ext_master_conn_0_S_AXI_AWPROT_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_AWVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_AWREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_WDATA_pin : in std_logic_vector(63 downto 0);
axi_ext_master_conn_0_S_AXI_WSTRB_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_WLAST_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_WVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_WREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_BRESP_pin : out std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_BVALID_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_BREADY_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_ARADDR_pin : in std_logic_vector(31 downto 0);
axi_ext_master_conn_0_S_AXI_ARLEN_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_ARSIZE_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_ARBURST_pin : in std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_ARCACHE_pin : in std_logic_vector(3 downto 0);
axi_ext_master_conn_0_S_AXI_ARPROT_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_ARVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_ARREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RDATA_pin : out std_logic_vector(63 downto 0);
axi_ext_master_conn_0_S_AXI_RRESP_pin : out std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_RLAST_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RVALID_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RREADY_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_AWUSER_pin : in std_logic_vector(4 downto 0);
axi_ext_master_conn_0_S_AXI_ARUSER_pin : in std_logic_vector(4 downto 0));
end component;
component ps_pl_interface is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff");
port (
-- AXIS Stream Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- AXI-Lite Slave bus for access to control & status registers
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI ACP Bus to interface with processor system
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
-- Interrupt on successfully completed AXI ACP writes
irq : out std_logic;
-- Global reset for all accelerators
rst_glb_n : out std_logic;
-- Accelerator interfaces
-- Note: Master & Slave 0 are not listed as the Datamover componeent
-- uses both.
-- Accelerator 1
-- Accelerator 1
axis_master_1_tvalid : in std_logic;
axis_master_1_tready : out std_logic;
axis_master_1_tdata : in std_logic_vector(63 downto 0);
axis_master_1_tdest : in std_logic_vector(2 downto 0);
axis_master_1_tlast : in std_logic;
axis_master_1_irq : in std_logic;
axis_slave_1_tvalid : out std_logic;
axis_slave_1_tready : in std_logic;
axis_slave_1_tdata : out std_logic_vector(63 downto 0);
axis_slave_1_tid : out std_logic_vector(2 downto 0);
axis_slave_1_tlast : out std_logic;
axis_slave_1_irq : in std_logic;
status_1_addr : out std_logic_vector(7 downto 0);
status_1_data : in std_logic_vector(31 downto 0);
status_1_stb : out std_logic;
ctrl_1_addr : out std_logic_vector(7 downto 0);
ctrl_1_data : out std_logic_vector(31 downto 0);
ctrl_1_stb : out std_logic;
-- Accelerator 2
axis_master_2_tvalid : in std_logic;
axis_master_2_tready : out std_logic;
axis_master_2_tdata : in std_logic_vector(63 downto 0);
axis_master_2_tdest : in std_logic_vector(2 downto 0);
axis_master_2_tlast : in std_logic;
axis_master_2_irq : in std_logic;
axis_slave_2_tvalid : out std_logic;
axis_slave_2_tready : in std_logic;
axis_slave_2_tdata : out std_logic_vector(63 downto 0);
axis_slave_2_tid : out std_logic_vector(2 downto 0);
axis_slave_2_tlast : out std_logic;
axis_slave_2_irq : in std_logic;
status_2_addr : out std_logic_vector(7 downto 0);
status_2_data : in std_logic_vector(31 downto 0);
status_2_stb : out std_logic;
ctrl_2_addr : out std_logic_vector(7 downto 0);
ctrl_2_data : out std_logic_vector(31 downto 0);
ctrl_2_stb : out std_logic;
-- Accelerator 3
axis_master_3_tvalid : in std_logic;
axis_master_3_tready : out std_logic;
axis_master_3_tdata : in std_logic_vector(63 downto 0);
axis_master_3_tdest : in std_logic_vector(2 downto 0);
axis_master_3_tlast : in std_logic;
axis_master_3_irq : in std_logic;
axis_slave_3_tvalid : out std_logic;
axis_slave_3_tready : in std_logic;
axis_slave_3_tdata : out std_logic_vector(63 downto 0);
axis_slave_3_tid : out std_logic_vector(2 downto 0);
axis_slave_3_tlast : out std_logic;
axis_slave_3_irq : in std_logic;
status_3_addr : out std_logic_vector(7 downto 0);
status_3_data : in std_logic_vector(31 downto 0);
status_3_stb : out std_logic;
ctrl_3_addr : out std_logic_vector(7 downto 0);
ctrl_3_data : out std_logic_vector(31 downto 0);
ctrl_3_stb : out std_logic;
-- Accelerator 4
axis_master_4_tvalid : in std_logic;
axis_master_4_tready : out std_logic;
axis_master_4_tdata : in std_logic_vector(63 downto 0);
axis_master_4_tdest : in std_logic_vector(2 downto 0);
axis_master_4_tlast : in std_logic;
axis_master_4_irq : in std_logic;
axis_slave_4_tvalid : out std_logic;
axis_slave_4_tready : in std_logic;
axis_slave_4_tdata : out std_logic_vector(63 downto 0);
axis_slave_4_tid : out std_logic_vector(2 downto 0);
axis_slave_4_tlast : out std_logic;
axis_slave_4_irq : in std_logic;
status_4_addr : out std_logic_vector(7 downto 0);
status_4_data : in std_logic_vector(31 downto 0);
status_4_stb : out std_logic;
ctrl_4_addr : out std_logic_vector(7 downto 0);
ctrl_4_data : out std_logic_vector(31 downto 0);
ctrl_4_stb : out std_logic;
-- Accelerator 5
axis_master_5_tvalid : in std_logic;
axis_master_5_tready : out std_logic;
axis_master_5_tdata : in std_logic_vector(63 downto 0);
axis_master_5_tdest : in std_logic_vector(2 downto 0);
axis_master_5_tlast : in std_logic;
axis_master_5_irq : in std_logic;
axis_slave_5_tvalid : out std_logic;
axis_slave_5_tready : in std_logic;
axis_slave_5_tdata : out std_logic_vector(63 downto 0);
axis_slave_5_tid : out std_logic_vector(2 downto 0);
axis_slave_5_tlast : out std_logic;
axis_slave_5_irq : in std_logic;
status_5_addr : out std_logic_vector(7 downto 0);
status_5_data : in std_logic_vector(31 downto 0);
status_5_stb : out std_logic;
ctrl_5_addr : out std_logic_vector(7 downto 0);
ctrl_5_data : out std_logic_vector(31 downto 0);
ctrl_5_stb : out std_logic;
-- Accelerator 6
axis_master_6_tvalid : in std_logic;
axis_master_6_tready : out std_logic;
axis_master_6_tdata : in std_logic_vector(63 downto 0);
axis_master_6_tdest : in std_logic_vector(2 downto 0);
axis_master_6_tlast : in std_logic;
axis_master_6_irq : in std_logic;
axis_slave_6_tvalid : out std_logic;
axis_slave_6_tready : in std_logic;
axis_slave_6_tdata : out std_logic_vector(63 downto 0);
axis_slave_6_tid : out std_logic_vector(2 downto 0);
axis_slave_6_tlast : out std_logic;
axis_slave_6_irq : in std_logic;
status_6_addr : out std_logic_vector(7 downto 0);
status_6_data : in std_logic_vector(31 downto 0);
status_6_stb : out std_logic;
ctrl_6_addr : out std_logic_vector(7 downto 0);
ctrl_6_data : out std_logic_vector(31 downto 0);
ctrl_6_stb : out std_logic;
-- Accelerator 7
axis_master_7_tvalid : in std_logic;
axis_master_7_tready : out std_logic;
axis_master_7_tdata : in std_logic_vector(63 downto 0);
axis_master_7_tdest : in std_logic_vector(2 downto 0);
axis_master_7_tlast : in std_logic;
axis_master_7_irq : in std_logic;
axis_slave_7_tvalid : out std_logic;
axis_slave_7_tready : in std_logic;
axis_slave_7_tdata : out std_logic_vector(63 downto 0);
axis_slave_7_tid : out std_logic_vector(2 downto 0);
axis_slave_7_tlast : out std_logic;
axis_slave_7_irq : in std_logic;
status_7_addr : out std_logic_vector(7 downto 0);
status_7_data : in std_logic_vector(31 downto 0);
status_7_stb : out std_logic;
ctrl_7_addr : out std_logic_vector(7 downto 0);
ctrl_7_data : out std_logic_vector(31 downto 0);
ctrl_7_stb : out std_logic);
end component;
component usrp_ddr_intf_axis is
generic (
DDR_CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface
BAUD : integer := 115200); -- UART baud rate
port (
-- USRP Interface
UART_TX : out std_logic; -- UART
RX_DATA_CLK_N : in std_logic; -- Receive data clock (N)
RX_DATA_CLK_P : in std_logic; -- Receive data clock (P)
RX_DATA_N : in std_logic_vector(6 downto 0); -- Receive data (N)
RX_DATA_P : in std_logic_vector(6 downto 0); -- Receive data (N)
TX_DATA_N : out std_logic_vector(7 downto 0); -- Transmit data (N)
TX_DATA_P : out std_logic_vector(7 downto 0); -- Transmit data (P)
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (DAC / TX Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (ADC / RX Data)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
rx_enable_aux : in std_logic;
tx_enable_aux : in std_logic);
end component;
component spectrum_sense is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Time Domain / FFT Input)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (Frequency Domain / FFT Output)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Strobes when threshold exceeded
-- Sideband signals
threshold_not_exceeded : out std_logic;
threshold_not_exceeded_stb : out std_logic;
threshold_exceeded : out std_logic;
threshold_exceeded_stb : out std_logic);
end component;
component bpsk_mod is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Binary Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used (TODO: maybe use for near empty input FIFO?)
-- AXIS Stream Master Interface (Modulated complex samples)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
trigger_stb : in std_logic);
end component;
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
signal clk : std_logic;
signal rst_n : std_logic;
signal S_AXI_AWADDR : std_logic_vector(31 downto 0);
signal S_AXI_AWVALID : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WDATA : std_logic_vector(31 downto 0);
signal S_AXI_WSTRB : std_logic_vector(3 downto 0);
signal S_AXI_WVALID : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BRESP : std_logic_vector(1 downto 0);
signal S_AXI_BVALID : std_logic;
signal S_AXI_BREADY : std_logic;
signal S_AXI_ARADDR : std_logic_vector(31 downto 0);
signal S_AXI_ARVALID : std_logic;
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RDATA : std_logic_vector(31 downto 0);
signal S_AXI_RRESP : std_logic_vector(1 downto 0);
signal S_AXI_RVALID : std_logic;
signal S_AXI_RREADY : std_logic;
signal M_AXI_AWADDR : std_logic_vector(31 downto 0);
signal M_AXI_AWPROT : std_logic_vector(2 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_AWREADY : std_logic;
signal M_AXI_WDATA : std_logic_vector(63 downto 0);
signal M_AXI_WSTRB : std_logic_vector(7 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_WREADY : std_logic;
signal M_AXI_BRESP : std_logic_vector(1 downto 0);
signal M_AXI_BVALID : std_logic;
signal M_AXI_BREADY : std_logic;
signal M_AXI_AWLEN : std_logic_vector(7 downto 0);
signal M_AXI_AWSIZE : std_logic_vector(2 downto 0);
signal M_AXI_AWBURST : std_logic_vector(1 downto 0);
signal M_AXI_AWCACHE : std_logic_vector(3 downto 0);
signal M_AXI_AWUSER : std_logic_vector(4 downto 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_ARADDR : std_logic_vector(31 downto 0);
signal M_AXI_ARPROT : std_logic_vector(2 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_ARREADY : std_logic;
signal M_AXI_RDATA : std_logic_vector(63 downto 0);
signal M_AXI_RRESP : std_logic_vector(1 downto 0);
signal M_AXI_RVALID : std_logic;
signal M_AXI_RREADY : std_logic;
signal M_AXI_RLAST : std_logic;
signal M_AXI_ARCACHE : std_logic_vector(3 downto 0);
signal M_AXI_ARUSER : std_logic_vector(4 downto 0);
signal M_AXI_ARLEN : std_logic_vector(7 downto 0);
signal M_AXI_ARBURST : std_logic_vector(1 downto 0);
signal M_AXI_ARSIZE : std_logic_vector(2 downto 0);
signal processing_system7_0_IRQ_F2P_pin : std_logic_vector(15 downto 0);
signal irq : std_logic;
signal rst_glb_n : std_logic;
signal axis_master_1_tvalid : std_logic;
signal axis_master_1_tready : std_logic;
signal axis_master_1_tdata : std_logic_vector(63 downto 0);
signal axis_master_1_tdest : std_logic_vector(2 downto 0);
signal axis_master_1_tlast : std_logic;
signal axis_master_1_irq : std_logic;
signal axis_slave_1_tvalid : std_logic;
signal axis_slave_1_tready : std_logic;
signal axis_slave_1_tdata : std_logic_vector(63 downto 0);
signal axis_slave_1_tid : std_logic_vector(2 downto 0);
signal axis_slave_1_tlast : std_logic;
signal axis_slave_1_irq : std_logic;
signal status_1_addr : std_logic_vector(7 downto 0);
signal status_1_data : std_logic_vector(31 downto 0);
signal status_1_stb : std_logic;
signal ctrl_1_addr : std_logic_vector(7 downto 0);
signal ctrl_1_data : std_logic_vector(31 downto 0);
signal ctrl_1_stb : std_logic;
signal axis_master_2_tvalid : std_logic;
signal axis_master_2_tready : std_logic;
signal axis_master_2_tdata : std_logic_vector(63 downto 0);
signal axis_master_2_tdest : std_logic_vector(2 downto 0);
signal axis_master_2_tlast : std_logic;
signal axis_master_2_irq : std_logic;
signal axis_slave_2_tvalid : std_logic;
signal axis_slave_2_tready : std_logic;
signal axis_slave_2_tdata : std_logic_vector(63 downto 0);
signal axis_slave_2_tid : std_logic_vector(2 downto 0);
signal axis_slave_2_tlast : std_logic;
signal axis_slave_2_irq : std_logic;
signal status_2_addr : std_logic_vector(7 downto 0);
signal status_2_data : std_logic_vector(31 downto 0);
signal status_2_stb : std_logic;
signal ctrl_2_addr : std_logic_vector(7 downto 0);
signal ctrl_2_data : std_logic_vector(31 downto 0);
signal ctrl_2_stb : std_logic;
signal axis_master_3_tvalid : std_logic;
signal axis_master_3_tready : std_logic;
signal axis_master_3_tdata : std_logic_vector(63 downto 0);
signal axis_master_3_tdest : std_logic_vector(2 downto 0);
signal axis_master_3_tlast : std_logic;
signal axis_master_3_irq : std_logic;
signal axis_slave_3_tvalid : std_logic;
signal axis_slave_3_tready : std_logic;
signal axis_slave_3_tdata : std_logic_vector(63 downto 0);
signal axis_slave_3_tid : std_logic_vector(2 downto 0);
signal axis_slave_3_tlast : std_logic;
signal axis_slave_3_irq : std_logic;
signal status_3_addr : std_logic_vector(7 downto 0);
signal status_3_data : std_logic_vector(31 downto 0);
signal status_3_stb : std_logic;
signal ctrl_3_addr : std_logic_vector(7 downto 0);
signal ctrl_3_data : std_logic_vector(31 downto 0);
signal ctrl_3_stb : std_logic;
signal axis_master_4_tvalid : std_logic;
signal axis_master_4_tready : std_logic;
signal axis_master_4_tdata : std_logic_vector(63 downto 0);
signal axis_master_4_tdest : std_logic_vector(2 downto 0);
signal axis_master_4_tlast : std_logic;
signal axis_master_4_irq : std_logic;
signal axis_slave_4_tvalid : std_logic;
signal axis_slave_4_tready : std_logic;
signal axis_slave_4_tdata : std_logic_vector(63 downto 0);
signal axis_slave_4_tid : std_logic_vector(2 downto 0);
signal axis_slave_4_tlast : std_logic;
signal axis_slave_4_irq : std_logic;
signal status_4_addr : std_logic_vector(7 downto 0);
signal status_4_data : std_logic_vector(31 downto 0);
signal status_4_stb : std_logic;
signal ctrl_4_addr : std_logic_vector(7 downto 0);
signal ctrl_4_data : std_logic_vector(31 downto 0);
signal ctrl_4_stb : std_logic;
signal axis_master_5_tvalid : std_logic;
signal axis_master_5_tready : std_logic;
signal axis_master_5_tdata : std_logic_vector(63 downto 0);
signal axis_master_5_tdest : std_logic_vector(2 downto 0);
signal axis_master_5_tlast : std_logic;
signal axis_master_5_irq : std_logic;
signal axis_slave_5_tvalid : std_logic;
signal axis_slave_5_tready : std_logic;
signal axis_slave_5_tdata : std_logic_vector(63 downto 0);
signal axis_slave_5_tid : std_logic_vector(2 downto 0);
signal axis_slave_5_tlast : std_logic;
signal axis_slave_5_irq : std_logic;
signal status_5_addr : std_logic_vector(7 downto 0);
signal status_5_data : std_logic_vector(31 downto 0);
signal status_5_stb : std_logic;
signal ctrl_5_addr : std_logic_vector(7 downto 0);
signal ctrl_5_data : std_logic_vector(31 downto 0);
signal ctrl_5_stb : std_logic;
signal axis_master_6_tvalid : std_logic;
signal axis_master_6_tready : std_logic;
signal axis_master_6_tdata : std_logic_vector(63 downto 0);
signal axis_master_6_tdest : std_logic_vector(2 downto 0);
signal axis_master_6_tlast : std_logic;
signal axis_master_6_irq : std_logic;
signal axis_slave_6_tvalid : std_logic;
signal axis_slave_6_tready : std_logic;
signal axis_slave_6_tdata : std_logic_vector(63 downto 0);
signal axis_slave_6_tid : std_logic_vector(2 downto 0);
signal axis_slave_6_tlast : std_logic;
signal axis_slave_6_irq : std_logic;
signal status_6_addr : std_logic_vector(7 downto 0);
signal status_6_data : std_logic_vector(31 downto 0);
signal status_6_stb : std_logic;
signal ctrl_6_addr : std_logic_vector(7 downto 0);
signal ctrl_6_data : std_logic_vector(31 downto 0);
signal ctrl_6_stb : std_logic;
signal axis_master_7_tvalid : std_logic;
signal axis_master_7_tready : std_logic;
signal axis_master_7_tdata : std_logic_vector(63 downto 0);
signal axis_master_7_tdest : std_logic_vector(2 downto 0);
signal axis_master_7_tlast : std_logic;
signal axis_master_7_irq : std_logic;
signal axis_slave_7_tvalid : std_logic;
signal axis_slave_7_tready : std_logic;
signal axis_slave_7_tdata : std_logic_vector(63 downto 0);
signal axis_slave_7_tid : std_logic_vector(2 downto 0);
signal axis_slave_7_tlast : std_logic;
signal axis_slave_7_irq : std_logic;
signal status_7_addr : std_logic_vector(7 downto 0);
signal status_7_data : std_logic_vector(31 downto 0);
signal status_7_stb : std_logic;
signal ctrl_7_addr : std_logic_vector(7 downto 0);
signal ctrl_7_data : std_logic_vector(31 downto 0);
signal ctrl_7_stb : std_logic;
signal rx_enable_aux : std_logic;
signal tx_enable_aux : std_logic;
signal threshold_not_exceeded : std_logic;
signal threshold_not_exceeded_stb : std_logic;
signal threshold_exceeded : std_logic;
signal threshold_exceeded_stb : std_logic;
signal trigger_stb : std_logic;
begin
inst_zc702_ps : zc702_ps
port map (
processing_system7_0_MIO => MIO,
processing_system7_0_PS_SRSTB_pin => PS_SRSTB,
processing_system7_0_PS_CLK_pin => PS_CLK,
processing_system7_0_PS_PORB_pin => PS_PORB,
processing_system7_0_DDR_Clk => DDR_Clk,
processing_system7_0_DDR_Clk_n => DDR_Clk_n,
processing_system7_0_DDR_CKE => DDR_CKE,
processing_system7_0_DDR_CS_n => DDR_CS_n,
processing_system7_0_DDR_RAS_n => DDR_RAS_n,
processing_system7_0_DDR_CAS_n => DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => DDR_BankAddr,
processing_system7_0_DDR_Addr => DDR_Addr,
processing_system7_0_DDR_ODT => DDR_ODT,
processing_system7_0_DDR_DRSTB => DDR_DRSTB,
processing_system7_0_DDR_DQ => DDR_DQ,
processing_system7_0_DDR_DM => DDR_DM,
processing_system7_0_DDR_DQS => DDR_DQS,
processing_system7_0_DDR_DQS_n => DDR_DQS_n,
processing_system7_0_DDR_VRN => DDR_VRN,
processing_system7_0_DDR_VRP => DDR_VRP,
axi_ext_slave_conn_0_M_AXI_AWADDR_pin => S_AXI_AWADDR,
axi_ext_slave_conn_0_M_AXI_AWVALID_pin => S_AXI_AWVALID,
axi_ext_slave_conn_0_M_AXI_AWREADY_pin => S_AXI_AWREADY,
axi_ext_slave_conn_0_M_AXI_WDATA_pin => S_AXI_WDATA,
axi_ext_slave_conn_0_M_AXI_WSTRB_pin => S_AXI_WSTRB,
axi_ext_slave_conn_0_M_AXI_WVALID_pin => S_AXI_WVALID,
axi_ext_slave_conn_0_M_AXI_WREADY_pin => S_AXI_WREADY,
axi_ext_slave_conn_0_M_AXI_BRESP_pin => S_AXI_BRESP,
axi_ext_slave_conn_0_M_AXI_BVALID_pin => S_AXI_BVALID,
axi_ext_slave_conn_0_M_AXI_BREADY_pin => S_AXI_BREADY,
axi_ext_slave_conn_0_M_AXI_ARADDR_pin => S_AXI_ARADDR,
axi_ext_slave_conn_0_M_AXI_ARVALID_pin => S_AXI_ARVALID,
axi_ext_slave_conn_0_M_AXI_ARREADY_pin => S_AXI_ARREADY,
axi_ext_slave_conn_0_M_AXI_RDATA_pin => S_AXI_RDATA,
axi_ext_slave_conn_0_M_AXI_RRESP_pin => S_AXI_RRESP,
axi_ext_slave_conn_0_M_AXI_RVALID_pin => S_AXI_RVALID,
axi_ext_slave_conn_0_M_AXI_RREADY_pin => S_AXI_RREADY,
processing_system7_0_IRQ_F2P_pin => processing_system7_0_IRQ_F2P_pin,
processing_system7_0_FCLK_CLK0_pin => clk,
processing_system7_0_FCLK_RESET0_N_pin => rst_n,
axi_ext_master_conn_0_S_AXI_AWADDR_pin => M_AXI_AWADDR,
axi_ext_master_conn_0_S_AXI_AWLEN_pin => M_AXI_AWLEN,
axi_ext_master_conn_0_S_AXI_AWSIZE_pin => M_AXI_AWSIZE,
axi_ext_master_conn_0_S_AXI_AWBURST_pin => M_AXI_AWBURST,
axi_ext_master_conn_0_S_AXI_AWCACHE_pin => M_AXI_AWCACHE,
axi_ext_master_conn_0_S_AXI_AWPROT_pin => M_AXI_AWPROT,
axi_ext_master_conn_0_S_AXI_AWVALID_pin => M_AXI_AWVALID,
axi_ext_master_conn_0_S_AXI_AWREADY_pin => M_AXI_AWREADY,
axi_ext_master_conn_0_S_AXI_WDATA_pin => M_AXI_WDATA,
axi_ext_master_conn_0_S_AXI_WSTRB_pin => M_AXI_WSTRB,
axi_ext_master_conn_0_S_AXI_WLAST_pin => M_AXI_WLAST,
axi_ext_master_conn_0_S_AXI_WVALID_pin => M_AXI_WVALID,
axi_ext_master_conn_0_S_AXI_WREADY_pin => M_AXI_WREADY,
axi_ext_master_conn_0_S_AXI_BRESP_pin => M_AXI_BRESP,
axi_ext_master_conn_0_S_AXI_BVALID_pin => M_AXI_BVALID,
axi_ext_master_conn_0_S_AXI_BREADY_pin => M_AXI_BREADY,
axi_ext_master_conn_0_S_AXI_ARADDR_pin => M_AXI_ARADDR,
axi_ext_master_conn_0_S_AXI_ARLEN_pin => M_AXI_ARLEN,
axi_ext_master_conn_0_S_AXI_ARSIZE_pin => M_AXI_ARSIZE,
axi_ext_master_conn_0_S_AXI_ARBURST_pin => M_AXI_ARBURST,
axi_ext_master_conn_0_S_AXI_ARCACHE_pin => M_AXI_ARCACHE,
axi_ext_master_conn_0_S_AXI_ARPROT_pin => M_AXI_ARPROT,
axi_ext_master_conn_0_S_AXI_ARVALID_pin => M_AXI_ARVALID,
axi_ext_master_conn_0_S_AXI_ARREADY_pin => M_AXI_ARREADY,
axi_ext_master_conn_0_S_AXI_RDATA_pin => M_AXI_RDATA,
axi_ext_master_conn_0_S_AXI_RRESP_pin => M_AXI_RRESP,
axi_ext_master_conn_0_S_AXI_RLAST_pin => M_AXI_RLAST,
axi_ext_master_conn_0_S_AXI_RVALID_pin => M_AXI_RVALID,
axi_ext_master_conn_0_S_AXI_RREADY_pin => M_AXI_RREADY,
axi_ext_master_conn_0_S_AXI_AWUSER_pin => M_AXI_AWUSER,
axi_ext_master_conn_0_S_AXI_ARUSER_pin => M_AXI_ARUSER);
processing_system7_0_IRQ_F2P_pin(15) <= irq;
inst_ps_pl_interface : ps_pl_interface
generic map (
C_BASEADDR => x"40000000",
C_HIGHADDR => x"4001ffff")
port map (
clk => clk,
rst_n => rst_n,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWUSER => M_AXI_AWUSER,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARUSER => M_AXI_ARUSER,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARSIZE => M_AXI_ARSIZE,
irq => irq,
rst_glb_n => rst_glb_n,
-- Note: Master 0 & Slave 0 interfaces are occupied by the
-- datamover component internally.
axis_master_1_tvalid => axis_master_1_tvalid,
axis_master_1_tready => axis_master_1_tready,
axis_master_1_tdata => axis_master_1_tdata,
axis_master_1_tdest => axis_master_1_tdest,
axis_master_1_tlast => axis_master_1_tlast,
axis_master_1_irq => axis_master_1_irq,
axis_slave_1_tvalid => axis_slave_1_tvalid,
axis_slave_1_tready => axis_slave_1_tready,
axis_slave_1_tdata => axis_slave_1_tdata,
axis_slave_1_tid => axis_slave_1_tid,
axis_slave_1_tlast => axis_slave_1_tlast,
axis_slave_1_irq => axis_slave_1_irq,
status_1_addr => status_1_addr,
status_1_data => status_1_data,
status_1_stb => status_1_stb,
ctrl_1_addr => ctrl_1_addr,
ctrl_1_data => ctrl_1_data,
ctrl_1_stb => ctrl_1_stb,
axis_master_2_tvalid => axis_master_2_tvalid,
axis_master_2_tready => axis_master_2_tready,
axis_master_2_tdata => axis_master_2_tdata,
axis_master_2_tdest => axis_master_2_tdest,
axis_master_2_tlast => axis_master_2_tlast,
axis_master_2_irq => axis_master_2_irq,
axis_slave_2_tvalid => axis_slave_2_tvalid,
axis_slave_2_tready => axis_slave_2_tready,
axis_slave_2_tdata => axis_slave_2_tdata,
axis_slave_2_tid => axis_slave_2_tid,
axis_slave_2_tlast => axis_slave_2_tlast,
axis_slave_2_irq => axis_slave_2_irq,
status_2_addr => status_2_addr,
status_2_data => status_2_data,
status_2_stb => status_2_stb,
ctrl_2_addr => ctrl_2_addr,
ctrl_2_data => ctrl_2_data,
ctrl_2_stb => ctrl_2_stb,
axis_master_3_tvalid => axis_master_3_tvalid,
axis_master_3_tready => axis_master_3_tready,
axis_master_3_tdata => axis_master_3_tdata,
axis_master_3_tdest => axis_master_3_tdest,
axis_master_3_tlast => axis_master_3_tlast,
axis_master_3_irq => axis_master_3_irq,
axis_slave_3_tvalid => axis_slave_3_tvalid,
axis_slave_3_tready => axis_slave_3_tready,
axis_slave_3_tdata => axis_slave_3_tdata,
axis_slave_3_tid => axis_slave_3_tid,
axis_slave_3_tlast => axis_slave_3_tlast,
axis_slave_3_irq => axis_slave_3_irq,
status_3_addr => status_3_addr,
status_3_data => status_3_data,
status_3_stb => status_3_stb,
ctrl_3_addr => ctrl_3_addr,
ctrl_3_data => ctrl_3_data,
ctrl_3_stb => ctrl_3_stb,
axis_master_4_tvalid => axis_master_4_tvalid,
axis_master_4_tready => axis_master_4_tready,
axis_master_4_tdata => axis_master_4_tdata,
axis_master_4_tdest => axis_master_4_tdest,
axis_master_4_tlast => axis_master_4_tlast,
axis_master_4_irq => axis_master_4_irq,
axis_slave_4_tvalid => axis_slave_4_tvalid,
axis_slave_4_tready => axis_slave_4_tready,
axis_slave_4_tdata => axis_slave_4_tdata,
axis_slave_4_tid => axis_slave_4_tid,
axis_slave_4_tlast => axis_slave_4_tlast,
axis_slave_4_irq => axis_slave_4_irq,
status_4_addr => status_4_addr,
status_4_data => status_4_data,
status_4_stb => status_4_stb,
ctrl_4_addr => ctrl_4_addr,
ctrl_4_data => ctrl_4_data,
ctrl_4_stb => ctrl_4_stb,
axis_master_5_tvalid => axis_master_5_tvalid,
axis_master_5_tready => axis_master_5_tready,
axis_master_5_tdata => axis_master_5_tdata,
axis_master_5_tdest => axis_master_5_tdest,
axis_master_5_tlast => axis_master_5_tlast,
axis_master_5_irq => axis_master_5_irq,
axis_slave_5_tvalid => axis_slave_5_tvalid,
axis_slave_5_tready => axis_slave_5_tready,
axis_slave_5_tdata => axis_slave_5_tdata,
axis_slave_5_tid => axis_slave_5_tid,
axis_slave_5_tlast => axis_slave_5_tlast,
axis_slave_5_irq => axis_slave_5_irq,
status_5_addr => status_5_addr,
status_5_data => status_5_data,
status_5_stb => status_5_stb,
ctrl_5_addr => ctrl_5_addr,
ctrl_5_data => ctrl_5_data,
ctrl_5_stb => ctrl_5_stb,
axis_master_6_tvalid => axis_master_6_tvalid,
axis_master_6_tready => axis_master_6_tready,
axis_master_6_tdata => axis_master_6_tdata,
axis_master_6_tdest => axis_master_6_tdest,
axis_master_6_tlast => axis_master_6_tlast,
axis_master_6_irq => axis_master_6_irq,
axis_slave_6_tvalid => axis_slave_6_tvalid,
axis_slave_6_tready => axis_slave_6_tready,
axis_slave_6_tdata => axis_slave_6_tdata,
axis_slave_6_tid => axis_slave_6_tid,
axis_slave_6_tlast => axis_slave_6_tlast,
axis_slave_6_irq => axis_slave_6_irq,
status_6_addr => status_6_addr,
status_6_data => status_6_data,
status_6_stb => status_6_stb,
ctrl_6_addr => ctrl_6_addr,
ctrl_6_data => ctrl_6_data,
ctrl_6_stb => ctrl_6_stb,
axis_master_7_tvalid => axis_master_7_tvalid,
axis_master_7_tready => axis_master_7_tready,
axis_master_7_tdata => axis_master_7_tdata,
axis_master_7_tdest => axis_master_7_tdest,
axis_master_7_tlast => axis_master_7_tlast,
axis_master_7_irq => axis_master_7_irq,
axis_slave_7_tvalid => axis_slave_7_tvalid,
axis_slave_7_tready => axis_slave_7_tready,
axis_slave_7_tdata => axis_slave_7_tdata,
axis_slave_7_tid => axis_slave_7_tid,
axis_slave_7_tlast => axis_slave_7_tlast,
axis_slave_7_irq => axis_slave_7_irq,
status_7_addr => status_7_addr,
status_7_data => status_7_data,
status_7_stb => status_7_stb,
ctrl_7_addr => ctrl_7_addr,
ctrl_7_data => ctrl_7_data,
ctrl_7_stb => ctrl_7_stb);
-- Accelerator 1
inst_usrp_ddr_intf_axis : usrp_ddr_intf_axis
generic map (
DDR_CLOCK_FREQ => 100e6,
BAUD => 115200)
port map (
UART_TX => UART_TX,
RX_DATA_CLK_N => RX_DATA_CLK_N,
RX_DATA_CLK_P => RX_DATA_CLK_P,
RX_DATA_N => RX_DATA_N,
RX_DATA_P => RX_DATA_P,
TX_DATA_N => TX_DATA_N,
TX_DATA_P => TX_DATA_P,
clk => clk,
rst_n => rst_glb_n,
status_addr => status_1_addr,
status_data => status_1_data,
status_stb => status_1_stb,
ctrl_addr => ctrl_1_addr,
ctrl_data => ctrl_1_data,
ctrl_stb => ctrl_1_stb,
axis_slave_tvalid => axis_slave_1_tvalid,
axis_slave_tready => axis_slave_1_tready,
axis_slave_tdata => axis_slave_1_tdata,
axis_slave_tid => axis_slave_1_tid,
axis_slave_tlast => axis_slave_1_tlast,
axis_slave_irq => axis_slave_1_irq,
axis_master_tvalid => axis_master_1_tvalid,
axis_master_tready => axis_master_1_tready,
axis_master_tdata => axis_master_1_tdata,
axis_master_tdest => axis_master_1_tdest,
axis_master_tlast => axis_master_1_tlast,
axis_master_irq => axis_master_1_irq,
rx_enable_aux => rx_enable_aux,
tx_enable_aux => tx_enable_aux);
rx_enable_aux <= '0';
tx_enable_aux <= threshold_exceeded OR threshold_not_exceeded;
-- Accelerator 2
inst_spectrum_sense : spectrum_sense
port map (
clk => clk,
rst_n => rst_glb_n,
status_addr => status_2_addr,
status_data => status_2_data,
status_stb => status_2_stb,
ctrl_addr => ctrl_2_addr,
ctrl_data => ctrl_2_data,
ctrl_stb => ctrl_2_stb,
axis_slave_tvalid => axis_slave_2_tvalid,
axis_slave_tready => axis_slave_2_tready,
axis_slave_tdata => axis_slave_2_tdata,
axis_slave_tid => axis_slave_2_tid,
axis_slave_tlast => axis_slave_2_tlast,
axis_slave_irq => axis_slave_2_irq,
axis_master_tvalid => axis_master_2_tvalid,
axis_master_tready => axis_master_2_tready,
axis_master_tdata => axis_master_2_tdata,
axis_master_tdest => axis_master_2_tdest,
axis_master_tlast => axis_master_2_tlast,
axis_master_irq => axis_master_2_irq,
threshold_not_exceeded => threshold_not_exceeded,
threshold_not_exceeded_stb => threshold_not_exceeded_stb,
threshold_exceeded => threshold_exceeded,
threshold_exceeded_stb => threshold_exceeded_stb);
-- Accelerator 3
inst_bpsk_mod : bpsk_mod
port map (
clk => clk,
rst_n => rst_glb_n,
status_addr => status_3_addr,
status_data => status_3_data,
status_stb => status_3_stb,
ctrl_addr => ctrl_3_addr,
ctrl_data => ctrl_3_data,
ctrl_stb => ctrl_3_stb,
axis_slave_tvalid => axis_slave_3_tvalid,
axis_slave_tready => axis_slave_3_tready,
axis_slave_tdata => axis_slave_3_tdata,
axis_slave_tid => axis_slave_3_tid,
axis_slave_tlast => axis_slave_3_tlast,
axis_slave_irq => axis_slave_3_irq,
axis_master_tvalid => axis_master_3_tvalid,
axis_master_tready => axis_master_3_tready,
axis_master_tdata => axis_master_3_tdata,
axis_master_tdest => axis_master_3_tdest,
axis_master_tlast => axis_master_3_tlast,
axis_master_irq => axis_master_3_irq,
trigger_stb => trigger_stb);
-- The output of either threshold trigger is controlled by control registers, so ORing them is
-- not an issue as only one should be active at a time.
trigger_stb <= threshold_exceeded_stb OR threshold_not_exceeded_stb;
-- Unused Accelerators
axis_slave_4_tready <= '0';
axis_slave_4_irq <= '0';
axis_master_4_tvalid <= '0';
axis_master_4_tdata <= x"0000000000000000";
axis_master_4_tdest <= "000";
axis_master_4_tlast <= '0';
axis_master_4_irq <= '0';
status_4_data <= x"00000000";
axis_slave_5_tready <= '0';
axis_slave_5_irq <= '0';
axis_master_5_tvalid <= '0';
axis_master_5_tdata <= x"0000000000000000";
axis_master_5_tdest <= "000";
axis_master_5_tlast <= '0';
axis_master_5_irq <= '0';
status_5_data <= x"00000000";
axis_slave_6_tready <= '0';
axis_slave_6_irq <= '0';
axis_master_6_tvalid <= '0';
axis_master_6_tdata <= x"0000000000000000";
axis_master_6_tdest <= "000";
axis_master_6_tlast <= '0';
axis_master_6_irq <= '0';
status_6_data <= x"00000000";
axis_slave_7_tready <= '0';
axis_slave_7_irq <= '0';
axis_master_7_tvalid <= '0';
axis_master_7_tdata <= x"0000000000000000";
axis_master_7_tdest <= "000";
axis_master_7_tlast <= '0';
axis_master_7_irq <= '0';
status_7_data <= x"00000000";
SPARE <= 'Z';
end architecture; | gpl-3.0 | 768d182e75be3c74cc804850f5614aa0 | 0.465331 | 3.807564 | false | false | false | false |
chiggs/nvc | test/regress/func6.vhd | 5 | 825 | entity func6 is
end entity;
architecture test of func6 is
function flip(x : bit_vector(3 downto 0)) return bit_vector is
variable r : bit_vector(3 downto 0);
begin
r(0) := x(3);
r(1) := x(2);
r(2) := x(1);
r(3) := x(0);
return r;
end function;
function flipu(x : bit_vector) return bit_vector is
begin
return flip(x);
end function;
function flipu2(x : bit_vector) return bit_vector is
begin
return flip(x(3 downto 0));
end function;
begin
process is
variable b : bit_vector(3 downto 0);
begin
assert flip("1010") = "0101";
b := "1100";
assert flip(b) = "0011";
assert flipu(b) = "0011";
assert flipu2(b) = "0011";
wait;
end process;
end architecture;
| gpl-3.0 | ed384027d2ed2f0c28eeae09291f9ede | 0.541818 | 3.451883 | false | false | false | false |
chiggs/nvc | test/regress/issue56.vhd | 5 | 372 | entity issue56 is
generic (
x : integer := 5;
y : bit_vector := "110" );
port (
pi : in integer := 2;
po : out bit );
end entity;
architecture test of issue56 is
begin
process is
begin
assert x = 5;
assert y = "110";
assert pi = 2;
wait;
end process;
po <= '1';
end architecture;
| gpl-3.0 | d80a0edef632d15dc5493724e672453f | 0.489247 | 3.757576 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/video/vhdl_source/char_generator_regs.vhd | 1 | 4,477 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator Registers
-------------------------------------------------------------------------------
-- File : char_generator_regs.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Registers for the character generator
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_regs is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
keyb_row : in std_logic_vector(7 downto 0);
keyb_col : inout std_logic_vector(7 downto 0);
control : out t_chargen_control );
end entity;
architecture gideon of char_generator_regs is
signal control_i : t_chargen_control := c_chargen_control_init;
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_chargen_line_clocks_hi =>
control_i.clocks_per_line(10 downto 8) <= unsigned(io_req.data(2 downto 0));
when c_chargen_line_clocks_lo =>
control_i.clocks_per_line(7 downto 0) <= unsigned(io_req.data);
when c_chargen_char_width =>
control_i.char_width <= unsigned(io_req.data(2 downto 0));
when c_chargen_char_height =>
control_i.char_height <= unsigned(io_req.data(4 downto 0));
control_i.stretch_y <= io_req.data(7);
when c_chargen_chars_per_line =>
control_i.chars_per_line <= unsigned(io_req.data);
when c_chargen_active_lines =>
control_i.active_lines <= unsigned(io_req.data(5 downto 0));
when c_chargen_x_on_hi =>
control_i.x_on(11 downto 8) <= unsigned(io_req.data(3 downto 0));
when c_chargen_x_on_lo =>
control_i.x_on(7 downto 0) <= unsigned(io_req.data);
when c_chargen_y_on_hi =>
control_i.y_on(11 downto 8) <= unsigned(io_req.data(3 downto 0));
when c_chargen_y_on_lo =>
control_i.y_on(7 downto 0) <= unsigned(io_req.data);
when c_chargen_pointer_hi =>
control_i.pointer(14 downto 8) <= unsigned(io_req.data(6 downto 0));
when c_chargen_pointer_lo =>
control_i.pointer(7 downto 0) <= unsigned(io_req.data);
when c_chargen_perform_sync =>
control_i.perform_sync <= io_req.data(0);
when c_chargen_transparency =>
control_i.transparent <= io_req.data(3 downto 0);
control_i.overlay_on <= io_req.data(7);
when c_chargen_keyb_col =>
keyb_col <= io_req.data;
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_chargen_keyb_row =>
io_resp.data <= keyb_row;
when c_chargen_keyb_col =>
io_resp.data <= keyb_col;
when others =>
null;
end case;
end if;
if reset='1' then
-- control_i <= c_chargen_control_init;
keyb_col <= (others => '1');
end if;
end if;
end process;
control <= control_i;
end gideon;
| gpl-3.0 | b5b194018a480d05b06050192083c85a | 0.427742 | 4.239583 | false | false | false | false |
armandas/Plong | player.vhd | 1 | 4,497 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity player is
port(
clk, not_reset: in std_logic;
bump_sound, miss_sound: in std_logic;
speaker: out std_logic
);
end player;
architecture behaviour of player is
signal pitch: std_logic_vector(18 downto 0);
signal duration: std_logic_vector(25 downto 0);
signal volume: std_logic_vector(2 downto 0);
signal enable: std_logic;
signal d_counter, d_counter_next: std_logic_vector(25 downto 0);
signal note, note_next: std_logic_vector(8 downto 0);
signal note_addr, note_addr_next: std_logic_vector(1 downto 0);
signal change_note: std_logic;
-- data source for tunes
signal source, source_next: std_logic;
-- container for current data selected by multiplexer
signal data: std_logic_vector(8 downto 0);
-- data containers for use with ROMs. Add more as needed.
signal data_1, data_2: std_logic_vector(8 downto 0);
type state_type is (off, playing);
signal state, state_next: state_type;
signal start: std_logic;
begin
process(clk, not_reset)
begin
if not_reset = '0' then
state <= off;
source <= '0';
note_addr <= (others => '0');
note <= (others => '0');
d_counter <= (others => '0');
elsif clk'event and clk = '1' then
state <= state_next;
source <= source_next;
note_addr <= note_addr_next;
note <= note_next;
d_counter <= d_counter_next;
end if;
end process;
process(state, start, enable, duration, d_counter, note_addr, change_note)
begin
state_next <= state;
note_addr_next <= note_addr;
case state is
when off =>
note_addr_next <= (others => '0');
if start = '1' then
state_next <= playing;
end if;
when playing =>
if duration = 0 then
state_next <= off;
elsif change_note = '1' then
note_addr_next <= note_addr + 1;
end if;
end case;
end process;
enable <= '1' when state = playing else '0';
change_note <= '1' when d_counter = duration else '0';
d_counter_next <= d_counter + 1 when (enable = '1' and
d_counter < duration) else
(others => '0');
with note(8 downto 6) select
pitch <= "1101110111110010001" when "001", -- 110 Hz
"0110111011111001000" when "010", -- 220 Hz
"0011011101111100100" when "011", -- 440 Hz
"0001101110111110010" when "100", -- 880 Hz
"0000110111011111001" when "101", -- 1760 Hz
"0000011011101111100" when "110", -- 3520 Hz
"0000001101110111110" when "111", -- 7040 Hz
"0000000000000000000" when others;
with note(5 downto 3) select
duration <= "00000010111110101111000010" when "001", -- 1/64
"00000101111101011110000100" when "010", -- 1/32
"00001011111010111100001000" when "011", -- 1/16
"00010111110101111000010000" when "100", -- 1/8
"00101111101011110000100000" when "101", -- 1/4
"01011111010111100001000000" when "110", -- 1/2
"10111110101111000010000000" when "111", -- 1/1
"00000000000000000000000000" when others;
volume <= note(2 downto 0);
start <= '1' when (bump_sound = '1' or miss_sound = '1') else '0';
-- data source
source_next <= '0' when bump_sound = '1' else
'1' when miss_sound = '1' else
source;
data <= data_1 when source = '0' else data_2;
note_next <= data;
bump:
entity work.bump_sound(content)
port map(
addr => note_addr,
data => data_1
);
miss:
entity work.lost_ball_sound(content)
port map(
addr => note_addr,
data => data_2
);
sounds:
entity work.sounds(generator)
port map(
clk => clk, not_reset => not_reset,
enable => enable,
period => pitch,
volume => volume,
speaker => speaker
);
end behaviour; | bsd-2-clause | f96ed7674c5ce2c5d1555cb8d02129ce | 0.52813 | 4.066004 | false | false | false | false |
trondd/mkjpeg | design/BufFifo/SUB_FIFO.vhd | 2 | 3,661 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library WORK;
entity SUB_FIFO is
generic (
DATA_WIDTH : INTEGER := 12;
ADDR_WIDTH : INTEGER := 2
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
rinc : in STD_LOGIC;
winc : in STD_LOGIC;
fullo : out STD_LOGIC;
emptyo : out STD_LOGIC;
count : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
ramwaddr : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
ramenw : out STD_LOGIC;
ramraddr : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
ramenr : out STD_LOGIC
);
end SUB_FIFO;
architecture RTL of SUB_FIFO is
signal raddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
signal waddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
signal count_reg : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal rd_en_reg : STD_LOGIC;
signal wr_en_reg : STD_LOGIC;
signal empty_reg : STD_LOGIC;
signal full_reg : STD_LOGIC;
constant ZEROS_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0');
constant ONES_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
begin
ramwaddr <= waddr_reg;
ramenw <= wr_en_reg;
ramraddr <= raddr_reg;
ramenr <= '1';
emptyo <= empty_reg;
fullo <= full_reg;
rd_en_reg <= (rinc and not empty_reg);
wr_en_reg <= (winc and not full_reg);
count <= count_reg;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
empty_reg <= '1';
else
if count_reg = ZEROS_C or
(count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then
empty_reg <= '1';
else
empty_reg <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
full_reg <= '0';
else
if count_reg = 2**ADDR_WIDTH or
(count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then
full_reg <= '1';
else
full_reg <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
raddr_reg <= (others => '0');
else
if rd_en_reg = '1' then
raddr_reg <= raddr_reg + '1';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
waddr_reg <= (others => '0');
else
if wr_en_reg = '1' then
waddr_reg <= waddr_reg + '1';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
count_reg <= (others => '0');
else
if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then
if rd_en_reg = '1' then
count_reg <= count_reg - '1';
else
count_reg <= count_reg + '1';
end if;
end if;
end if;
end if;
end process;
end RTL;
| lgpl-3.0 | e5a95e08914d05767d341f5d8a8fea3b | 0.449331 | 3.571707 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/core_Pkg.vhd | 1 | 18,655 | ----------------------------------------------------------------------------------------------
--
-- Input file : core_Pkg.vhd
-- Design name : core_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with components and type definitions for the interface
-- of the components
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.std_Pkg.all;
use mblite.config_Pkg.all;
package core_Pkg is
constant C_8_ZEROS : std_logic_vector ( 7 downto 0) := (others => '0');
constant C_16_ZEROS : std_logic_vector (15 downto 0) := (others => '0');
constant C_24_ZEROS : std_logic_vector (23 downto 0) := (others => '0');
constant C_32_ZEROS : std_logic_vector (31 downto 0) := (others => '0');
----------------------------------------------------------------------------------------------
-- TYPES USED IN MB-LITE
----------------------------------------------------------------------------------------------
type alu_operation is (ALU_ADD, ALU_OR, ALU_AND, ALU_XOR, ALU_SHIFT, ALU_SEXT8, ALU_SEXT16, ALU_MUL, ALU_BS, ALU_PEQ);
type src_type_a is (ALU_SRC_REGA, ALU_SRC_NOT_REGA, ALU_SRC_PC, ALU_SRC_SPR);
type src_type_b is (ALU_SRC_REGB, ALU_SRC_NOT_REGB, ALU_SRC_IMM, ALU_SRC_NOT_IMM);
type carry_type is (CARRY_ZERO, CARRY_ONE, CARRY_ALU, CARRY_ARITH);
type carry_keep_type is (CARRY_NOT_KEEP, CARRY_KEEP);
type branch_condition is (NOP, BNC, BEQ, BNE, BLT, BLE, BGT, BGE);
type transfer_size is (WORD, HALFWORD, BYTE);
type msr_update is (NOP, LOAD_MSR, MSR_SET, MSR_CLR, MSR_SET_I, MSR_CLR_I);
type ctrl_execution is record
alu_op : alu_operation;
alu_src_a : src_type_a;
alu_src_b : src_type_b;
compare_op : std_logic;
operation : std_logic_vector(1 downto 0);
carry : carry_type;
carry_keep : carry_keep_type;
branch_cond : branch_condition;
delay : std_logic;
msr_op : msr_update;
end record;
type ctrl_memory is record
mem_write : std_logic;
mem_read : std_logic;
transfer_size : transfer_size;
end record;
type ctrl_memory_writeback_type is record
mem_read : std_logic;
transfer_size : transfer_size;
end record;
type forward_type is record
reg_d : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
reg_write : std_logic;
end record;
type imem_in_type is record
dat_i : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
ena_i : std_logic;
end record;
type imem_out_type is record
adr_o : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
ena_o : std_logic;
end record;
type fetch_in_type is record
hazard : std_logic;
branch : std_logic;
branch_target : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
end record;
type fetch_out_type is record
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
inst_valid : std_logic;
end record;
type gprf_out_type is record
dat_a_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_b_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
end record;
type decode_in_type is record
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
inst_valid : std_logic;
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
interrupt : std_logic;
interrupt_enable: std_logic;
flush_id : std_logic;
end record;
type decode_out_type is record
reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
imm : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
hazard : std_logic;
ctrl_ex : ctrl_execution;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
fwd_dec : forward_type;
int_ack : std_logic;
end record;
type gprf_in_type is record
adr_a_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
adr_b_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
adr_d_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_w_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
adr_w_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
wre_i : std_logic;
end record;
type execute_out_type is record
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
branch : std_logic;
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
flush_id : std_logic;
interrupt_enable: std_logic;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
end record;
type execute_in_type is record
reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
imm : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
fwd_dec : forward_type;
fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
fwd_mem : forward_type;
ctrl_ex : ctrl_execution;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
end record;
type mem_in_type is record
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
branch : std_logic;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
end record;
type mem_out_type is record
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
end record;
type dmem_in_type is record
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
ena_i : std_logic;
end record;
type dmem_out_type is record
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
sel_o : std_logic_vector(3 downto 0);
we_o : std_logic;
ena_o : std_logic;
end record;
type dmem_in_array_type is array(natural range <>) of dmem_in_type;
type dmem_out_array_type is array(natural range <>) of dmem_out_type;
-- WB-master inputs from the wb-slaves
type wb_mst_in_type is record
clk_i : std_logic; -- master clock input
rst_i : std_logic; -- synchronous active high reset
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus input
ack_i : std_logic; -- buscycle acknowledge input
int_i : std_logic; -- interrupt request input
end record;
-- WB-master outputs to the wb-slaves
type wb_mst_out_type is record
adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus output
we_o : std_logic; -- write enable output
stb_o : std_logic; -- strobe signals
sel_o : std_logic_vector(3 downto 0); -- select output array
cyc_o : std_logic; -- valid BUS cycle output
end record;
-- WB-slave inputs, from the WB-master
type wb_slv_in_type is record
clk_i : std_logic; -- master clock input
rst_i : std_logic; -- synchronous active high reset
adr_i : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- Databus input
we_i : std_logic; -- Write enable input
stb_i : std_logic; -- strobe signals / core select signal
sel_i : std_logic_vector(3 downto 0); -- select output array
cyc_i : std_logic; -- valid BUS cycle input
end record;
-- WB-slave outputs to the WB-master
type wb_slv_out_type is record
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- Databus output
ack_o : std_logic; -- Bus cycle acknowledge output
int_o : std_logic; -- interrupt request output
end record;
----------------------------------------------------------------------------------------------
-- COMPONENTS USED IN MB-LITE
----------------------------------------------------------------------------------------------
component core
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
imem_o : out imem_out_type;
dmem_o : out dmem_out_type;
imem_i : in imem_in_type;
dmem_i : in dmem_in_type;
int_i : in std_logic;
int_o : out std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component core_wb
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
imem_o : out imem_out_type;
wb_o : out wb_mst_out_type;
imem_i : in imem_in_type;
wb_i : in wb_mst_in_type
);
end component;
component core_wb_adapter
port (
dmem_i : out dmem_in_type;
wb_o : out wb_mst_out_type;
dmem_o : in dmem_out_type;
wb_i : in wb_mst_in_type
);
end component;
component core_wb_async_adapter
port (
dmem_i : out dmem_in_type;
wb_o : out wb_mst_out_type;
dmem_o : in dmem_out_type;
wb_i : in wb_mst_in_type
);
end component;
component fetch
port (
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
imem_i : in imem_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component decode
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component gprf
port (
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component execute
generic (
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port (
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component mem
port (
mem_o : out mem_out_type;
dmem_o : out dmem_out_type;
mem_i : in mem_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component core_address_decoder
generic (
G_NUM_SLAVES : positive := CFG_NUM_SLAVES
);
port (
m_dmem_i : out dmem_in_type;
s_dmem_o : out dmem_out_array_type;
m_dmem_o : in dmem_out_type;
s_dmem_i : in dmem_in_array_type;
clk_i : in std_logic
);
end component;
----------------------------------------------------------------------------------------------
-- FUNCTIONS USED IN MB-LITE
----------------------------------------------------------------------------------------------
function select_register_data (reg_dat, wb_dat : std_logic_vector; write : std_logic) return std_logic_vector;
function forward_condition (reg_write : std_logic; reg_a, reg_d : std_logic_vector) return std_logic;
function align_mem_load (data : std_logic_vector; size : transfer_size; address : std_logic_vector) return std_logic_vector;
function align_mem_store (data : std_logic_vector; size : transfer_size) return std_logic_vector;
function decode_mem_store (address : std_logic_vector(1 downto 0); size : transfer_size) return std_logic_vector;
end core_Pkg;
package body core_Pkg is
-- This function select the register value:
-- A) zero
-- B) bypass value read from register file
-- C) value from register file
function select_register_data (reg_dat, wb_dat : std_logic_vector; write : std_logic) return std_logic_vector is
variable tmp : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
if CFG_REG_FWD_WRB = true and write = '1' then
tmp := wb_dat;
else
tmp := reg_dat;
end if;
return tmp;
end select_register_data;
-- This function checks if a forwarding condition is met. The condition is met of register A and D match
-- and the signal needs to be written back to the register file.
function forward_condition (reg_write : std_logic; reg_a, reg_d : std_logic_vector ) return std_logic is
begin
return reg_write and compare(reg_a, reg_d);
end forward_condition;
-- This function aligns the memory load operation (Big endian decoding).
function align_mem_load (data : std_logic_vector; size : transfer_size; address : std_logic_vector ) return std_logic_vector is
begin
case size is
when byte =>
case address(1 downto 0) is
when "00" => return C_24_ZEROS & data(31 downto 24);
when "01" => return C_24_ZEROS & data(23 downto 16);
when "10" => return C_24_ZEROS & data(15 downto 8);
when "11" => return C_24_ZEROS & data( 7 downto 0);
when others => return C_32_ZEROS;
end case;
when halfword =>
case address(1 downto 0) is
when "00" => return C_16_ZEROS & data(31 downto 16);
when "10" => return C_16_ZEROS & data(15 downto 0);
when others => return C_32_ZEROS;
end case;
when others =>
return data;
end case;
end align_mem_load;
-- This function repeats the operand to all positions in a memory store operation.
function align_mem_store (data : std_logic_vector; size : transfer_size) return std_logic_vector is
begin
case size is
when byte => return data( 7 downto 0) & data( 7 downto 0) & data(7 downto 0) & data(7 downto 0);
when halfword => return data(15 downto 0) & data(15 downto 0);
when others => return data;
end case;
end align_mem_store;
-- This function selects the correct bytes for memory writes (Big endian encoding).
function decode_mem_store (address : std_logic_vector(1 downto 0); size : transfer_size) return std_logic_vector is
begin
case size is
when BYTE =>
case address is
when "00" => return "1000";
when "01" => return "0100";
when "10" => return "0010";
when "11" => return "0001";
when others => return "0000";
end case;
when HALFWORD =>
case address is
-- Big endian encoding
when "10" => return "0011";
when "00" => return "1100";
when others => return "0000";
end case;
when others =>
return "1111";
end case;
end decode_mem_store;
end core_Pkg; | gpl-3.0 | 0183730159860a894a72469855354ee6 | 0.510533 | 3.863119 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/sampler/vhdl_source/sampler_pkg.vhd | 1 | 3,629 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sampler_pkg is
type t_sample_state is (idle, playing, finished, fetch1, fetch2);
type t_sample_mode is (mono8, mono16);
type t_voice_state is record
state : t_sample_state;
position : unsigned(23 downto 0);
divider : unsigned(15 downto 0);
prescale : integer range 0 to 15;
sample_out : signed(15 downto 0);
end record;
constant c_voice_state_init : t_voice_state := (
state => idle,
position => to_unsigned(0, 24),
divider => to_unsigned(0, 16),
prescale => 0,
sample_out => to_signed(0, 16) );
type t_voice_control is record
enable : boolean;
repeat : boolean;
interrupt : boolean;
interleave : boolean;
mode : t_sample_mode;
start_addr : unsigned(25 downto 0);
repeat_a : unsigned(23 downto 0);
repeat_b : unsigned(23 downto 0);
length : unsigned(23 downto 0);
rate : unsigned(15 downto 0);
volume : unsigned(5 downto 0);
pan : unsigned(3 downto 0); -- 0000 = left, 1111 = right
end record;
constant c_voice_control_init : t_voice_control := (
enable => false,
repeat => false,
interrupt => false,
interleave => false,
mode => mono8,
start_addr => to_unsigned(16*1024*1024, 26),
repeat_a => to_unsigned(32768, 24),
repeat_b => to_unsigned(49152, 24),
length => to_unsigned(65536, 24),
rate => to_unsigned(283, 16),
volume => to_unsigned(63, 6),
pan => X"7" );
type t_voice_control_array is array(natural range <>) of t_voice_control;
type t_voice_state_array is array(natural range <>) of t_voice_state;
type t_voice_sample_array is array(natural range <>) of signed(15 downto 0);
type t_sample_byte_array is array(natural range <>) of signed(7 downto 0);
constant c_sample_control : unsigned(4 downto 0) := '0' & X"0";
constant c_sample_volume : unsigned(4 downto 0) := '0' & X"1";
constant c_sample_pan : unsigned(4 downto 0) := '0' & X"2";
constant c_sample_start_addr_h : unsigned(4 downto 0) := '0' & X"4";
constant c_sample_start_addr_mh : unsigned(4 downto 0) := '0' & X"5";
constant c_sample_start_addr_ml : unsigned(4 downto 0) := '0' & X"6";
constant c_sample_start_addr_l : unsigned(4 downto 0) := '0' & X"7";
constant c_sample_length_h : unsigned(4 downto 0) := '0' & X"9";
constant c_sample_length_m : unsigned(4 downto 0) := '0' & X"A";
constant c_sample_length_l : unsigned(4 downto 0) := '0' & X"B";
constant c_sample_rate_h : unsigned(4 downto 0) := '0' & X"E";
constant c_sample_rate_l : unsigned(4 downto 0) := '0' & X"F";
constant c_sample_rep_a_pos_h : unsigned(4 downto 0) := '1' & X"1";
constant c_sample_rep_a_pos_m : unsigned(4 downto 0) := '1' & X"2";
constant c_sample_rep_a_pos_l : unsigned(4 downto 0) := '1' & X"3";
constant c_sample_rep_b_pos_h : unsigned(4 downto 0) := '1' & X"5";
constant c_sample_rep_b_pos_m : unsigned(4 downto 0) := '1' & X"6";
constant c_sample_rep_b_pos_l : unsigned(4 downto 0) := '1' & X"7";
constant c_sample_clear_irq : unsigned(4 downto 0) := '1' & X"F";
end package;
| gpl-3.0 | 2002b15fa7873308250a9cb02e7d8db4 | 0.539267 | 3.317185 | false | false | false | false |
nussbrot/AdvPT | wb_test/src/vhdl/wb_traffic_supervision.vhd | 2 | 2,345 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2017 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used AND/OR copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY wb_traffic_supervision IS
GENERIC (
g_priority : INTEGER;
g_tot_priority : INTEGER);
PORT (
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC := '1';
i_bg : IN STD_LOGIC; -- bus grant
i_ce : IN STD_LOGIC; -- clock enable
o_traffic_limit : OUT STD_LOGIC);
END ENTITY wb_traffic_supervision;
ARCHITECTURE rtl OF wb_traffic_supervision IS
SIGNAL s_shreg : STD_LOGIC_VECTOR(g_tot_priority - 1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL s_cntr : INTEGER RANGE 0 TO g_tot_priority;
BEGIN -- rtl
-- purpose: holds information of usage of latest cycles
-- type : sequential, no reset, rising clock edge
sh_reg : PROCESS (clk)
BEGIN -- process shreg
IF (clk'EVENT AND clk = '1') THEN
IF (i_ce = '1') THEN
s_shreg <= s_shreg(g_tot_priority - 2 DOWNTO 0) & i_bg;
END IF;
END IF;
END PROCESS sh_reg;
-- purpose: keeps track of used cycles
-- type : sequential, rising edge, mixed type reset
counter : PROCESS (clk, rst_n)
BEGIN -- process counter
IF (rst_n = '0') THEN
s_cntr <= 0;
o_traffic_limit <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (i_ce = '1') THEN
IF ((i_bg = '1') AND (s_shreg(g_tot_priority - 1) /= '1')) THEN
s_cntr <= s_cntr + 1;
if (s_cntr = g_priority - 1) THEN
o_traffic_limit <= '1';
END IF;
ELSIF ((i_bg = '0') AND (s_shreg(g_tot_priority - 1) = '1')) THEN
s_cntr <= s_cntr - 1;
IF (s_cntr = g_priority) THEN
o_traffic_limit <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS counter;
END ARCHITECTURE rtl;
| mit | 6d20d4854ceade3513e1a37f8ae6803c | 0.537313 | 3.602151 | false | false | false | false |
xiadz/oscilloscope | src/display.vhd | 1 | 9,187 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 15:58:36 05/22/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity oscilloscope_display is
port (
nrst : in std_logic;
clk108 : in std_logic;
is_reading_active : in std_logic;
trigger_event : in TRIGGER_EVENT_T;
red_enable : in std_logic;
green_enable : in std_logic;
blue_enable : in std_logic;
continue_after_reading : in std_logic;
time_resolution : in integer range 0 to 15;
currently_read_screen_segment : in natural range 0 to 13;
currently_read_screen_column : in natural range 0 to 1279;
addrb : out std_logic_vector (12 downto 0);
doutb : in std_logic_vector (8 downto 0);
vout : out std_logic_vector (7 downto 0);
vsync : out std_logic;
hsync : out std_logic
);
end oscilloscope_display;
architecture behavioral of oscilloscope_display is
signal vga_cntl_line_change : std_logic;
signal vga_cntl_page_change : std_logic;
signal vga_cntl_column : integer range 0 to 1279;
signal vga_cntl_column_change : std_logic;
signal vga_cntl_vblank : std_logic;
signal vga_cntl_hsync : std_logic;
signal vga_cntl_vsync : std_logic;
signal scr_pos_segment : integer range 0 to 15;
signal scr_pos_segment_change : std_logic;
signal scr_pos_subsegment : integer range 0 to 3;
signal scr_pos_subsegment_change : std_logic;
signal scr_pos_line : integer range 0 to 15;
signal scr_pos_out_line_change : std_logic;
signal scr_pos_out_column : integer range 0 to 1279;
signal scr_pos_out_column_mod_8 : integer range 0 to 7;
signal scr_pos_out_column_div_8 : integer range 0 to 159;
signal scr_pos_column_change : std_logic;
signal scr_pos_out_page_change : std_logic;
signal scr_pos_active_pixgen_source : PIXGEN_SOURCE_T;
signal scr_pos_out_column_mod_8_delayed : integer range 0 to 7;
signal scr_pos_line_delayed : integer range 0 to 15;
signal scr_pos_active_pixgen_source_delayed_1 : PIXGEN_SOURCE_T;
signal scr_pos_active_pixgen_source_delayed_2 : PIXGEN_SOURCE_T;
signal time_base_char : short_character;
signal settings_char : short_character;
signal char_rom_mux_char_pixel : std_logic;
signal trace_vout : std_logic_vector (7 downto 0);
signal time_base_vout : std_logic_vector (7 downto 0);
signal settings_vout : std_logic_vector (7 downto 0);
begin
vga_controller_1280_1024: entity work.vga_controller_1280_1024
port map (
nrst => nrst,
clk108 => clk108,
hsync => vga_cntl_hsync,
vsync => vga_cntl_vsync,
vblank => vga_cntl_vblank,
line_change => vga_cntl_line_change,
page_change => vga_cntl_page_change,
column => vga_cntl_column,
column_change => vga_cntl_column_change
);
screen_position_gen: entity work.screen_position_gen
port map (
nrst => nrst,
clk108 => clk108,
vblank => vga_cntl_vblank,
in_line_change => vga_cntl_line_change,
in_page_change => vga_cntl_page_change,
in_column => vga_cntl_column,
in_column_change => vga_cntl_column_change,
segment => scr_pos_segment,
segment_change => scr_pos_segment_change,
subsegment => scr_pos_subsegment,
subsegment_change => scr_pos_subsegment_change,
line => scr_pos_line,
out_line_change => scr_pos_out_line_change,
out_column => scr_pos_out_column,
out_column_mod_8 => scr_pos_out_column_mod_8,
out_column_div_8 => scr_pos_out_column_div_8,
out_column_change => scr_pos_column_change,
out_page_change => scr_pos_out_page_change,
active_pixgen_source => scr_pos_active_pixgen_source
);
trace_pixgen: entity work.trace_pixgen
port map (
nrst => nrst,
clk108 => clk108,
segment => scr_pos_segment,
segment_change => scr_pos_segment_change,
subsegment => scr_pos_subsegment,
subsegment_change => scr_pos_subsegment_change,
line => scr_pos_line,
line_change => scr_pos_out_line_change,
column => scr_pos_out_column,
column_change => scr_pos_column_change,
page_change => scr_pos_out_page_change,
active_pixgen_source => scr_pos_active_pixgen_source,
currently_read_screen_segment => currently_read_screen_segment,
currently_read_screen_column => currently_read_screen_column,
time_resolution => time_resolution,
is_reading_active => is_reading_active,
doutb => doutb,
addrb => addrb,
vout => trace_vout
);
scr_pos_out_column_mod_8_delayed <= scr_pos_out_column_mod_8 when rising_edge (clk108);
scr_pos_line_delayed <= scr_pos_line when rising_edge (clk108);
scr_pos_active_pixgen_source_delayed_1 <= scr_pos_active_pixgen_source when rising_edge (clk108);
scr_pos_active_pixgen_source_delayed_2 <= scr_pos_active_pixgen_source_delayed_1 when rising_edge (clk108);
char_rom_mux: entity work.char_rom_mux
port map (
nrst => nrst,
clk108 => clk108,
active_pixgen_source => scr_pos_active_pixgen_source_delayed_1,
char_pos_x => scr_pos_out_column_mod_8_delayed,
char_pos_y => scr_pos_line_delayed,
time_base_char => time_base_char,
settings_char => settings_char,
char_pixel => char_rom_mux_char_pixel
);
time_base_pixgen: entity work.time_base_pixgen
port map (
nrst => nrst,
clk108 => clk108,
segment => scr_pos_segment,
segment_change => scr_pos_segment_change,
subsegment => scr_pos_subsegment,
subsegment_change => scr_pos_subsegment_change,
line => scr_pos_line,
line_change => scr_pos_out_line_change,
column => scr_pos_out_column,
column_change => scr_pos_column_change,
page_change => scr_pos_out_page_change,
active_pixgen_source => scr_pos_active_pixgen_source,
char => time_base_char,
char_pixel => char_rom_mux_char_pixel,
vout => time_base_vout
);
settings_pixgen: entity work.settings_pixgen
port map (
nrst => nrst,
clk108 => clk108,
segment => scr_pos_segment,
segment_change => scr_pos_segment_change,
subsegment => scr_pos_subsegment,
subsegment_change => scr_pos_subsegment_change,
line => scr_pos_line,
line_change => scr_pos_out_line_change,
column => scr_pos_out_column,
column_div_8 => scr_pos_out_column_div_8,
column_mod_8 => scr_pos_out_column_mod_8,
column_change => scr_pos_column_change,
page_change => scr_pos_out_page_change,
active_pixgen_source => scr_pos_active_pixgen_source,
is_reading_active => is_reading_active,
trigger_event => trigger_event,
red_enable => red_enable,
green_enable => green_enable,
blue_enable => blue_enable,
continue_after_reading => continue_after_reading,
time_resolution => time_resolution,
char => settings_char,
char_pixel => char_rom_mux_char_pixel,
vout => settings_vout
);
pixgen_mux: entity work.pixgen_mux
port map (
nrst => nrst,
clk108 => clk108,
trace_vout => trace_vout,
time_base_vout => time_base_vout,
settings_vout => settings_vout,
active_pixgen_source => scr_pos_active_pixgen_source_delayed_2,
vout => vout
);
vga_sync_signals_4_delay: entity work.n_cycles_delayer
generic map (
n => 4,
signal_width => 2
)
port map (
nrst => nrst,
clk => clk108,
input(0) => vga_cntl_hsync,
input(1) => vga_cntl_vsync,
output(0) => hsync,
output(1) => vsync
);
end behavioral;
| mit | f54db41c14cb130b731d40f6eed31a18 | 0.536192 | 3.914359 | false | false | false | false |
ringof/radiofist_audio | testbench/tb_adc_fir_lowpass.vhd | 1 | 1,907 | -- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See licence.txt for details
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_adc_fir_lowpass IS
END tb_adc_fir_lowpass;
ARCHITECTURE behavior OF tb_adc_fir_lowpass IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fir_filter
PORT(
sclr : IN std_logic;
clk : IN std_logic;
nd : IN std_logic;
rfd : OUT std_logic;
rdy : OUT std_logic;
data_valid : OUT std_logic;
din : IN std_logic_vector(24 downto 0);
dout : OUT std_logic_vector(40 downto 0)
);
END COMPONENT;
--Inputs
signal sclr : std_logic := '0';
signal clk : std_logic := '0';
signal nd : std_logic := '0';
signal din : std_logic_vector(24 downto 0) := (others => '0');
--Outputs
signal rfd : std_logic;
signal rdy : std_logic;
signal data_valid : std_logic;
signal dout : std_logic_vector(40 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fir_filter PORT MAP (
sclr => sclr,
clk => clk,
nd => nd,
rfd => rfd,
rdy => rdy,
data_valid => data_valid,
din => din,
dout => dout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
sclr <= '1';
nd <= '1';
wait for clk_period*10;
sclr <= '0';
-- insert stimulus here
wait for clk_period*10;
din <= (others => '0');
wait for clk_period*10;
din <= (others => '1');
wait;
end process;
END;
| mit | 05e96ca6db9e198e8dcac2090a9156cd | 0.563713 | 3.442238 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/srl_fifo.vhd | 1 | 3,351 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Fifo Using SRL16
-------------------------------------------------------------------------------
-- File : srl_fifo.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Altera wrapper to make the "SRL" fifo available to Altera tools.. Obviously
-- it does not use any SRL, but just BRAM!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
entity srl_fifo is
generic (Width : integer := 32;
Depth : integer := 15; -- 15 is the maximum
Threshold : integer := 13);
port (
clock : in std_logic;
reset : in std_logic;
GetElement : in std_logic;
PutElement : in std_logic;
FlushFifo : in std_logic;
DataIn : in std_logic_vector(Width-1 downto 0);
DataOut : out std_logic_vector(Width-1 downto 0);
SpaceInFifo : out std_logic;
AlmostFull : out std_logic;
DataInFifo : out std_logic);
end srl_fifo;
architecture Altera of srl_fifo is
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
almost_full_value : NATURAL;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (Width-1 DOWNTO 0);
rdreq : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
almost_full : OUT STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (Width-1 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
signal full : std_logic;
signal empty : std_logic;
signal sclr : std_logic;
BEGIN
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "ON",
almost_full_value => Threshold,
intended_device_family => "Cyclone IV E",
lpm_numwords => Depth,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => Width,
lpm_widthu => 4,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => DataIn,
rdreq => GetElement,
sclr => sclr,
wrreq => PutElement,
almost_full => AlmostFull,
empty => empty,
full => full,
q => DataOut,
usedw => open );
SpaceInFifo <= not full;
DataInFifo <= not empty;
sclr <= reset or FlushFifo;
end Altera;
| gpl-3.0 | 373b685088a0c18b90cd656c334ff93e | 0.462548 | 4.403417 | false | false | false | false |
chiggs/nvc | test/regress/wait3.vhd | 5 | 426 | entity wait3 is
end entity;
architecture test of wait3 is
signal x, y : bit;
begin
proc_a: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
assert y = '1';
wait;
end process;
proc_b: process is
begin
wait on x;
assert x = '1';
assert now = 1 ns;
y <= '1';
wait;
end process;
end architecture;
| gpl-3.0 | 6a01fb6fd4e91114aa0afedef2943c3d | 0.476526 | 3.736842 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/sync_fifo/vhdl_sim/sync_fifo_tb.vhd | 1 | 3,961 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : sync_fifo_tb
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Quick test bench for sync fifo
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_fifo_tb is
end entity;
architecture test of sync_fifo_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal rd_en : std_logic;
signal rd_en_d : std_logic;
signal wr_en : std_logic;
signal din : std_logic_vector(7 downto 0);
signal dout : std_logic_vector(7 downto 0);
signal flush : std_logic;
signal full : std_logic;
signal almost_full : std_logic;
signal empty : std_logic;
signal valid : std_logic;
signal count : integer range 0 to 15;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_fifo: entity work.sync_fifo
generic map (
g_depth => 15,
g_data_width => 8,
g_threshold => 12,
g_fall_through => false
)
port map (
clock => clock,
reset => reset,
rd_en => rd_en,
wr_en => wr_en,
din => din,
dout => dout,
flush => flush,
full => full,
almost_full => almost_full,
empty => empty,
valid => valid,
count => count
);
process
begin
din <= X"00";
flush <= '0';
wr_en <= '0';
wait until reset = '0';
for i in 1 to 20 loop
wait until clock = '1';
wait until clock = '1';
while full = '1' loop
wait until clock = '1';
end loop;
wr_en <= '1';
din <= std_logic_vector(to_unsigned(i, 8));
wait until clock = '1';
wr_en <= '0';
end loop;
wait until clock = '1';
for i in 21 to 50 loop
while full = '1' loop
wait until clock = '1';
end loop;
wr_en <= '1';
din <= std_logic_vector(to_unsigned(i, 8));
wait until clock = '1';
wr_en <= '0';
end loop;
wait until empty = '1';
for i in 51 to 60 loop
wait until clock = '1';
wait until clock = '1';
wr_en <= '1';
din <= std_logic_vector(to_unsigned(i, 8));
wait until clock = '1';
wr_en <= '0';
end loop;
wait;
end process;
process
begin
rd_en <= '0';
wait until reset = '0';
wait until full = '1';
wait until clock = '1';
wait until clock = '1';
for i in 1 to 5 loop
wait until clock = '1';
wait until clock = '1';
wait until clock = '1';
rd_en <= '1';
wait until clock = '1';
rd_en <= '0';
end loop;
rd_en <= '1';
wait;
end process;
process(clock)
variable expect : natural := 0;
begin
if rising_edge(clock) then
rd_en_d <= rd_en;
elsif falling_edge(clock) then
if rd_en_d = '1' and valid = '1' then
expect := expect + 1;
assert dout = std_logic_vector(to_unsigned(expect, 8)) report "Unexpected data" severity error;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | ed955d0b0b0fcccba550aa6b56d36c6b | 0.415804 | 4.240899 | false | false | false | false |
chiggs/nvc | test/regress/issue111.vhd | 5 | 1,265 | entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architecture rtl of test is
begin
ADD_GEN: for I in 0 to 7 generate
L: if I=0 generate--failure is here
U0: entity work.t1
port map(A(I),B(I),'0',D(I));
end generate L;
U: if I>0 generate
UX: entity work.t1
port map(A(I),B(I),C(I-1),D(I));
end generate U;
end generate ADD_GEN;
end rtl;
entity issue111 is
end entity;
architecture test of issue111 is
signal A, B, C : bit_vector(7 downto 0);
signal D : bit_vector(7 downto 0);
begin
uut: entity work.test
port map (
A => A,
B => B,
C => C,
D => D );
process is
begin
wait for 1 ns;
assert D = X"00";
A <= X"ff";
wait for 1 ns;
assert D = X"00";
B <= X"0f";
C <= X"0c";
wait for 1 ns;
assert D = X"08";
wait;
end process;
end architecture;
| gpl-3.0 | c00061eba8f6afe1ff72128c6abb44af | 0.479051 | 3.235294 | false | true | false | false |
markusC64/1541ultimate2 | fpga/ip/nano_cpu/vhdl_source/nano_alu.vhd | 2 | 2,524 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_alu is
port (
clock : in std_logic;
reset : in std_logic;
value_in : in unsigned(15 downto 0);
ext_in : in unsigned(15 downto 0);
alu_oper : in std_logic_vector(15 downto 13);
update_accu : in std_logic;
update_flag : in std_logic;
accu : out unsigned(15 downto 0);
z : out boolean;
n : out boolean;
c : out boolean );
end entity;
architecture gideon of nano_alu is
signal accu_i : unsigned(15 downto 0) := (others => '0');
signal alu_out : unsigned(15 downto 0);
signal alu_z : boolean;
signal alu_n : boolean;
signal carry : std_logic;
signal c_flag : std_logic;
signal add_oper2: unsigned(15 downto 0);
signal add_res : unsigned(17 downto 0);
signal upd_carry: boolean;
begin
with alu_oper select carry <=
'0' when c_alu_add,
'1' when c_alu_sub,
c_flag when c_alu_addc,
'0' when others;
with alu_oper select upd_carry <=
true when c_alu_add,
true when c_alu_sub,
true when c_alu_addc,
false when others;
add_oper2 <= value_in when alu_oper(13)='0' else not value_in;
add_res <= ('0' & accu_i & '1') + ('0' & add_oper2 & carry);
with alu_oper select alu_out <=
value_in when c_alu_load,
value_in or accu_i when c_alu_or,
value_in and accu_i when c_alu_and,
value_in xor accu_i when c_alu_xor,
add_res(16 downto 1) when c_alu_add,
add_res(16 downto 1) when c_alu_sub,
add_res(16 downto 1) when c_alu_addc,
ext_in when others;
alu_z <= (alu_out = 0);
alu_n <= (alu_out(15)='1');
process(clock)
begin
if rising_edge(clock) then
if update_accu='1' then
accu_i <= alu_out;
end if;
if update_flag='1' then
z <= alu_z;
n <= alu_n;
if upd_carry then
c_flag <= add_res(17);
end if;
end if;
if reset='1' then
c_flag <= '0';
end if;
end if;
end process;
accu <= accu_i;
c <= (c_flag = '1');
end architecture;
| gpl-3.0 | 791513ba3ac0a88f578229cb4700b834 | 0.488114 | 3.429348 | false | false | false | false |
chiggs/nvc | test/regress/agg4.vhd | 5 | 829 | entity agg4 is
end entity;
architecture test of agg4 is
type int_array is array (integer range <>) of integer;
procedure fill(a : out int_array; x : in integer) is
alias aa : int_array(1 to a'length) is a;
begin
aa := (1 to a'length => x);
end procedure;
procedure fill2(a : out int_array; y : in integer) is
begin
assert a'length = 1;
a := (a'left => y);
end procedure;
begin
process is
variable v : int_array(1 to 3);
variable w : int_array(5 to 5);
begin
v := (1 to 3 => 7);
assert v = (7, 7, 7);
v := (1 => 6, 2 to 3 => 5);
assert v = (6, 5, 5);
fill(v, 8);
assert v = (8, 8, 8);
fill2(w, 6);
assert w = (5 => 6);
wait;
end process;
end architecture;
| gpl-3.0 | 56f9b6383f05e71b77fa7a543891e4dd | 0.496984 | 3.316 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/video/vhdl_source/char_generator_pkg.vhd | 1 | 4,665 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_pkg.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Definitions for the video character generator
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package char_generator_pkg is
type t_chargen_control is record
clocks_per_line : unsigned(11 downto 0);
char_width : unsigned(2 downto 0);
char_height : unsigned(4 downto 0);
chars_per_line : unsigned(7 downto 0);
active_lines : unsigned(5 downto 0);
x_on : unsigned(11 downto 0);
y_on : unsigned(11 downto 0);
pointer : unsigned(14 downto 0);
perform_sync : std_logic;
overlay_on : std_logic;
stretch_y : std_logic;
transparent : std_logic_vector(3 downto 0);
end record;
constant c_chargen_control_init : t_chargen_control := (
clocks_per_line => to_unsigned(672, 12),
char_width => to_unsigned(0, 3),
char_height => to_unsigned(9, 5),
chars_per_line => to_unsigned(60, 8),
active_lines => to_unsigned(30, 6),
x_on => to_unsigned(15, 12),
y_on => to_unsigned(6, 12),
pointer => to_unsigned(0, 15),
perform_sync => '0',
overlay_on => '0',
stretch_y => '0',
transparent => X"5" );
-- 640x225 (80x25 => 8x9 chars, in 45 C64 chars width)
constant c_chargen_control_init_orig : t_chargen_control := (
clocks_per_line => to_unsigned(896, 12),
char_width => to_unsigned(0, 3),
char_height => to_unsigned(8, 5),
chars_per_line => to_unsigned(80, 8),
active_lines => to_unsigned(25, 6),
x_on => to_unsigned(190, 12),
y_on => to_unsigned(46, 12),
pointer => to_unsigned(0, 15),
overlay_on => '0',
stretch_y => '0',
perform_sync => '0',
transparent => X"5" );
-- 480x200 (80x25 => 6x8 chars, in 45 C64 chars width)
constant c_chargen_control_init_480 : t_chargen_control := (
clocks_per_line => to_unsigned(672, 12),
char_width => to_unsigned(6, 3),
char_height => to_unsigned(8, 5),
chars_per_line => to_unsigned(80, 8),
active_lines => to_unsigned(25, 6),
x_on => to_unsigned(142, 12),
y_on => to_unsigned(48, 12),
pointer => to_unsigned(0, 15),
overlay_on => '0',
stretch_y => '0',
perform_sync => '0',
transparent => X"5" );
constant c_chargen_line_clocks_hi : unsigned(3 downto 0) := X"0";
constant c_chargen_line_clocks_lo : unsigned(3 downto 0) := X"1";
constant c_chargen_char_width : unsigned(3 downto 0) := X"2";
constant c_chargen_char_height : unsigned(3 downto 0) := X"3";
constant c_chargen_chars_per_line : unsigned(3 downto 0) := X"4";
constant c_chargen_active_lines : unsigned(3 downto 0) := X"5";
constant c_chargen_x_on_hi : unsigned(3 downto 0) := X"6";
constant c_chargen_x_on_lo : unsigned(3 downto 0) := X"7";
constant c_chargen_y_on_hi : unsigned(3 downto 0) := X"8";
constant c_chargen_y_on_lo : unsigned(3 downto 0) := X"9";
constant c_chargen_pointer_hi : unsigned(3 downto 0) := X"A";
constant c_chargen_pointer_lo : unsigned(3 downto 0) := X"B";
constant c_chargen_perform_sync : unsigned(3 downto 0) := X"C";
constant c_chargen_transparency : unsigned(3 downto 0) := X"D";
constant c_chargen_keyb_row : unsigned(3 downto 0) := X"E";
constant c_chargen_keyb_col : unsigned(3 downto 0) := X"F";
end package;
| gpl-3.0 | a48b1dd30d9c3d706ffeba0de9f15f48 | 0.457878 | 3.826907 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_source/usb1_bus_reset.vhd | 2 | 13,036 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
entity usb1_bus_reset is
generic (
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
reset_done : out std_logic;
sof_enable : out std_logic;
scan_enable : out std_logic;
speed : out std_logic_vector(1 downto 0);
abort : out std_logic;
-- status
status : in std_logic_vector(7 downto 0);
usb_busy : out std_logic;
-- command response interface
cmd_empty : in std_logic;
cmd_data : in std_logic_vector(7 downto 0);
cmd_get : out std_logic;
resp_full : in std_logic;
resp_put : out std_logic;
resp_data : out std_logic_vector(8 downto 0);
-- register interface
reg_read : out std_logic;
reg_write : out std_logic;
reg_rdata : in std_logic_vector(7 downto 0);
reg_wdata : out std_logic_vector(7 downto 0);
reg_address : out std_logic_vector(5 downto 0);
reg_ack : in std_logic;
send_packet : out std_logic;
user_data : out std_logic_vector(7 downto 0);
user_last : out std_logic;
user_valid : out std_logic );
end usb1_bus_reset;
architecture functional of usb1_bus_reset is
type t_state is (idle, start_reset, set_se0, listen_chirp,
wait_chirp_end, setup_chirp, hub_chirp_k, hub_chirp_j,
reset_end, reset_finished,
user_reg_read, user_reg_write, user_write_2, send_resp );
type t_int_bool_array is array(boolean) of integer;
constant c_reset_times : t_int_bool_array := (false => 60000*15, true => 2097); -- 4194303
constant c_latest_chirp : t_int_bool_array := (false => 80000, true => 400); -- not used anymore, as we don't wait for the device chirp to end
constant c_stop_chirp : t_int_bool_array := (false => 20000, true => 100);
constant c_chirp_jk : t_int_bool_array := (false => 3000, true => 20);
constant c_filter_times : t_int_bool_array := (false => 255, true => 10);
signal state : t_state;
signal speed_i : std_logic_vector(1 downto 0);
signal low_speed : std_logic;
signal disable_hs : std_logic;
signal t0_expired : std_logic;
signal t2_expired : std_logic := '0';
signal timer_0 : integer range 0 to 4194303; -- ~ 70 ms
signal timer_1 : integer range 0 to 8191; -- ~ 136 us
signal timer_2 : integer range 0 to 31 := 31; -- 500 ns
signal stop_chirp : std_logic;
signal reset_done_i : std_logic;
signal latest_chirp_start : std_logic;
signal cmd_valid : std_logic;
signal cmd_get_i : std_logic;
signal debug : std_logic;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
begin
speed <= speed_i;
reset_done <= reset_done_i;
cmd_get <= cmd_get_i;
cmd_get_i <= '1' when cmd_empty='0' and cmd_valid='0' and (state=idle or state=user_reg_write)
else '0';
p_reset: process(clock)
begin
if rising_edge(clock) then
if timer_0 = 0 then
t0_expired <= '1';
else
timer_0 <= timer_0 - 1;
end if;
if timer_0 = c_stop_chirp(g_simulation) then
stop_chirp <= '1';
end if;
if timer_0 = c_latest_chirp(g_simulation) then
latest_chirp_start <= '1';
end if;
if timer_2 = 0 then
t2_expired <= '1';
else
timer_2 <= timer_2 - 1;
end if;
cmd_valid <= cmd_get_i;
resp_put <= '0';
abort <= '0';
case state is
when idle =>
reg_address <= cmd_data(5 downto 0);
if cmd_valid = '1' then
case cmd_data(7 downto 6) is
when "00" =>
debug <= '0';
case cmd_data(3 downto 0) is
when c_cmd_get_status =>
resp_data <= "0" & status;
state <= send_resp;
when c_cmd_get_done =>
resp_data <= X"00" & reset_done_i;
state <= send_resp;
when c_cmd_get_speed =>
resp_data <= "0000000" & speed_i;
state <= send_resp;
when c_cmd_do_reset_hs =>
disable_hs <= '0';
state <= start_reset;
when c_cmd_do_reset_fs =>
disable_hs <= '1';
state <= start_reset;
when c_cmd_disable_host =>
reset_done_i <= '0';
when c_cmd_abort =>
abort <= '1';
when c_cmd_sof_enable =>
sof_enable <= '1';
when c_cmd_sof_disable =>
sof_enable <= '0';
when c_cmd_set_busy =>
usb_busy <= '1';
when c_cmd_clear_busy =>
usb_busy <= '0';
when c_cmd_disable_scan =>
scan_enable <= '0';
when c_cmd_enable_scan =>
scan_enable <= '1';
when c_cmd_set_debug =>
debug <= '1';
when others =>
if debug='1' then
resp_data <= '0' & X"AB";
else
resp_data <= '0' & X"AA";
end if;
state <= send_resp;
end case;
when "11" =>
state <= user_reg_write;
when "10" =>
reg_read <= '1';
state <= user_reg_read;
when others =>
null;
end case;
end if;
when user_reg_read =>
if reg_ack = '1' then
reg_read <= '0';
resp_data <= "1" & reg_rdata;
state <= send_resp;
end if;
when user_reg_write =>
if cmd_valid = '1' then
reg_wdata <= cmd_data;
reg_write <= '1';
state <= user_write_2;
end if;
when user_write_2 =>
if reg_ack = '1' then
reg_write <= '0';
state <= idle;
end if;
when send_resp =>
if resp_full = '0' then
resp_put <= '1';
state <= idle;
end if;
when start_reset =>
timer_0 <= c_reset_times(g_simulation);
latest_chirp_start <= '0';
t0_expired <= '0';
stop_chirp <= '0';
reset_done_i <= '0';
low_speed <= '0';
if status(5 downto 2) /= "0011" then
speed_i <= "11"; -- not powered or rx active
state <= idle;
else
if status(1)='1' then
low_speed <= '1';
speed_i <= "00"; -- Low speed
else
speed_i <= "01"; -- assume FS
end if;
state <= set_se0;
end if;
when set_se0 =>
reg_address <= std_logic_vector(to_unsigned(4, reg_address'length));
reg_write <= '1';
reg_wdata <= X"50";
timer_1 <= c_filter_times(g_simulation); -- reset timer 1 (4.25 �s)
if reg_ack = '1' then
reg_write <= '0';
if low_speed='1' or disable_hs='1' then
state <= reset_end;
else
state <= listen_chirp;
end if;
end if;
when listen_chirp =>
if t0_expired='1' then
state <= reset_end; -- no chirp detected
elsif status(1)='0' then
timer_1 <= c_filter_times(g_simulation); -- reset timer
elsif timer_1 = 0 then -- chirp detected
speed_i <= "10"; -- HS!
state <= setup_chirp; -- Let's be RUDE and just send our chirp back -- wait_chirp_end;
timer_1 <= 2 * c_chirp_jk(g_simulation);
else
timer_1 <= timer_1 - 1;
end if;
when wait_chirp_end =>
if t0_expired='1' then
speed_i <= "11"; -- error
state <= reset_end;
elsif status(1)='0' then
if timer_1 = 0 then
if latest_chirp_start = '1' then
speed_i <= "11";
state <= reset_end;
else
state <= setup_chirp;
end if;
else
timer_1 <= timer_1 - 1;
end if;
else
timer_1 <= 2 * c_chirp_jk(g_simulation); -- reset timer
end if;
when setup_chirp =>
timer_1 <= c_chirp_jk(g_simulation);
send_packet <= '1';
state <= hub_chirp_k;
when hub_chirp_k =>
user_data <= X"00";
user_valid <= '1';
user_last <= '0';
send_packet <= '0';
if timer_1 = 0 then
if stop_chirp = '1' then
state <= reset_end;
user_last <= '1'; -- data is still 0
else
user_data <= X"FF";
state <= hub_chirp_j;
timer_1 <= c_chirp_jk(g_simulation);
end if;
else
timer_1 <= timer_1 - 1;
end if;
when hub_chirp_j =>
if timer_1 = 0 then
timer_1 <= c_chirp_jk(g_simulation);
user_data <= X"00";
state <= hub_chirp_k;
else
timer_1 <= timer_1 - 1;
end if;
when reset_end =>
user_valid <= '0';
user_last <= '0';
if t0_expired = '1' then
reg_address <= std_logic_vector(to_unsigned(4, reg_address'length));
reg_write <= '1';
reg_wdata <= map_speed(speed_i) or X"20"; -- reset bit set
state <= reset_finished;
end if;
when reset_finished =>
if reg_ack='1' then
reg_write <= '0';
reset_done_i <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
disable_hs <= '0';
speed_i <= "11"; -- error or uninitialized
state <= idle;
reset_done_i <= '0';
sof_enable <= '0';
scan_enable <= '1';
user_data <= X"00";
user_last <= '0';
user_valid <= '0';
send_packet <= '0';
reg_read <= '0';
reg_write <= '0';
reg_wdata <= X"00";
reg_address <= (others => '0');
resp_data <= (others => '0');
timer_2 <= 31;
t2_expired <= '0';
low_speed <= '0';
stop_chirp <= '0';
latest_chirp_start <= '0';
usb_busy <= '0';
debug <= '0';
end if;
end if;
end process;
end functional;
| gpl-3.0 | 696dce201d810eb32645c97cfc2951e0 | 0.38016 | 4.325921 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/testbench/mem_io_synth.vhd | 1 | 4,323 | --------------------------------------------------------------------------------
-- Entity: mem_io_synth
-- Date:2016-07-17
-- Author: Gideon
--
-- Description: Testbench for altera io for ddr
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_io_synth is
port (
ref_clock : in std_logic := '0';
ref_reset : in std_logic;
sys_clock : out std_logic;
sys_reset : out std_logic;
write_data : out std_logic_vector(15 downto 0);
read_data : out std_logic_vector(15 downto 0);
do_read : out std_logic;
rdata_valid : out std_logic;
mode : in std_logic_vector(1 downto 0) := "00";
measurement : out std_logic_vector(11 downto 0);
SDRAM_CLK : inout std_logic := 'Z';
SDRAM_CLKn : inout std_logic := 'Z';
SDRAM_A : out std_logic_vector(7 downto 0);
SDRAM_DQ : inout std_logic_vector(3 downto 0);
SDRAM_DQS : inout std_logic );
end entity;
architecture arch of mem_io_synth is
signal sys_clock_i : std_logic;
signal sys_reset_i : std_logic;
signal phasecounterselect : std_logic_vector(2 downto 0) := (others => '0');
signal phasestep : std_logic := '0';
signal phaseupdown : std_logic := '0';
signal phasedone : std_logic := '0';
signal addr_first : std_logic_vector(7 downto 0) := X"00";
signal addr_second : std_logic_vector(7 downto 0) := X"00";
signal wdata : std_logic_vector(15 downto 0) := X"0000";
signal wdata_oe : std_logic;
signal counter : unsigned(4 downto 0) := (others => '0');
begin
i_mut: entity work.mem_io
port map (
ref_clock => ref_clock,
ref_reset => ref_reset,
sys_clock => sys_clock_i,
sys_reset => sys_reset_i,
phasecounterselect => phasecounterselect,
phasestep => phasestep,
phaseupdown => phaseupdown,
phasedone => phasedone,
mode => mode,
measurement => measurement,
addr_first => addr_first,
addr_second => addr_second,
wdata => wdata,
wdata_oe => wdata_oe,
rdata => read_data,
mem_clk_p => SDRAM_CLK,
mem_clk_n => SDRAM_CLKn,
mem_addr => SDRAM_A,
mem_dq => SDRAM_DQ,
mem_dqs => SDRAM_DQS
);
process(sys_clock_i, phasedone)
begin
if rising_edge(sys_clock_i) then
counter <= counter + 1;
wdata_oe <= '0';
addr_first <= (others => '1');
addr_second <= (others => '1');
do_read <= '0';
rdata_valid <= '0';
case counter is
when "01101" =>
addr_first(7) <= '0';
addr_first(5) <= '0'; -- write
when "01110" =>
wdata <= wdata(0) & wdata(15 downto 1);
wdata_oe <= '1';
when "01111" =>
addr_first(7) <= '0';
addr_first(6) <= '0'; -- row
when "10000" =>
addr_first(7) <= '0';
addr_first(4) <= '0'; -- read
do_read <= '1';
when "10100" =>
rdata_valid <= '1';
when "10111" =>
phasecounterselect <= "101"; -- read clock
phasestep <= '1';
when "01100" =>
phasecounterselect <= "110"; -- measure
phasestep <= '1';
when others =>
null;
end case;
if sys_reset_i = '1' then
phasestep <= '0';
wdata <= X"B769";
end if;
end if;
if phasedone = '0' then
phasestep <= '0';
end if;
end process;
sys_clock <= sys_clock_i;
sys_reset <= sys_reset_i;
write_data <= wdata;
end arch;
| gpl-3.0 | 35449977f8dc3434f94ff4a36ac36d71 | 0.430719 | 4.086011 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/nios.vhd | 1 | 71,734 | -- nios.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios is
port (
altmemddr_0_auxfull_clk : out std_logic; -- altmemddr_0_auxfull.clk
altmemddr_0_auxhalf_clk : out std_logic; -- altmemddr_0_auxhalf.clk
clk50_clk : in std_logic := '0'; -- clk50.clk
io_ack : in std_logic := '0'; -- io.ack
io_rdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .rdata
io_read : out std_logic; -- .read
io_wdata : out std_logic_vector(7 downto 0); -- .wdata
io_write : out std_logic; -- .write
io_address : out std_logic_vector(19 downto 0); -- .address
io_irq : in std_logic := '0'; -- .irq
mem32_address : in std_logic_vector(25 downto 0) := (others => '0'); -- mem32.address
mem32_direction : in std_logic := '0'; -- .direction
mem32_byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- .byte_en
mem32_wdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .wdata
mem32_request : in std_logic := '0'; -- .request
mem32_tag : in std_logic_vector(7 downto 0) := (others => '0'); -- .tag
mem32_dack_tag : out std_logic_vector(7 downto 0); -- .dack_tag
mem32_rdata : out std_logic_vector(31 downto 0); -- .rdata
mem32_rack : out std_logic; -- .rack
mem32_rack_tag : out std_logic_vector(7 downto 0); -- .rack_tag
mem_external_local_refresh_ack : out std_logic; -- mem_external.local_refresh_ack
mem_external_local_init_done : out std_logic; -- .local_init_done
mem_external_reset_phy_clk_n : out std_logic; -- .reset_phy_clk_n
memory_mem_odt : out std_logic_vector(0 downto 0); -- memory.mem_odt
memory_mem_clk : inout std_logic_vector(0 downto 0) := (others => '0'); -- .mem_clk
memory_mem_clk_n : inout std_logic_vector(0 downto 0) := (others => '0'); -- .mem_clk_n
memory_mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
memory_mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
memory_mem_addr : out std_logic_vector(13 downto 0); -- .mem_addr
memory_mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
memory_mem_ras_n : out std_logic; -- .mem_ras_n
memory_mem_cas_n : out std_logic; -- .mem_cas_n
memory_mem_we_n : out std_logic; -- .mem_we_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dq
memory_mem_dqs : inout std_logic_vector(0 downto 0) := (others => '0'); -- .mem_dqs
memory_mem_dm : out std_logic_vector(0 downto 0); -- .mem_dm
pio_in_port : in std_logic_vector(31 downto 0) := (others => '0'); -- pio.in_port
pio_out_port : out std_logic_vector(31 downto 0); -- .out_port
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sys_clock_clk : out std_logic; -- sys_clock.clk
sys_reset_reset_n : out std_logic -- sys_reset.reset_n
);
end entity nios;
architecture rtl of nios is
component nios_altmemddr_0 is
port (
local_address : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
local_write_req : in std_logic := 'X'; -- write
local_read_req : in std_logic := 'X'; -- read
local_burstbegin : in std_logic := 'X'; -- beginbursttransfer
local_ready : out std_logic; -- waitrequest_n
local_rdata : out std_logic_vector(31 downto 0); -- readdata
local_rdata_valid : out std_logic; -- readdatavalid
local_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
local_be : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
local_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_refresh_ack : out std_logic; -- export
local_init_done : out std_logic; -- export
reset_phy_clk_n : out std_logic; -- export
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
mem_clk : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_clk
mem_clk_n : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_clk_n
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_addr : out std_logic_vector(13 downto 0); -- mem_addr
mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
mem_ras_n : out std_logic; -- mem_ras_n
mem_cas_n : out std_logic; -- mem_cas_n
mem_we_n : out std_logic; -- mem_we_n
mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqs
mem_dm : out std_logic_vector(0 downto 0); -- mem_dm
pll_ref_clk : in std_logic := 'X'; -- clk
soft_reset_n : in std_logic := 'X'; -- reset_n
global_reset_n : in std_logic := 'X'; -- reset_n
reset_request_n : out std_logic; -- reset_n
phy_clk : out std_logic; -- clk
aux_full_rate_clk : out std_logic; -- clk
aux_half_rate_clk : out std_logic -- clk
);
end component nios_altmemddr_0;
component avalon_to_io_bridge is
port (
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
avs_ready : out std_logic; -- waitrequest_n
avs_readdata : out std_logic_vector(7 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
clock : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
avs_irq : out std_logic -- irq
);
end component avalon_to_io_bridge;
component mem32_to_avalon_bridge is
port (
reset : in std_logic := 'X'; -- reset
clock : in std_logic := 'X'; -- clk
memreq_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
memreq_read_writen : in std_logic := 'X'; -- direction
memreq_byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byte_en
memreq_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
memreq_request : in std_logic := 'X'; -- request
memreq_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- tag
memresp_dack_tag : out std_logic_vector(7 downto 0); -- dack_tag
memresp_data : out std_logic_vector(31 downto 0); -- rdata
memresp_rack : out std_logic; -- rack
memresp_rack_tag : out std_logic_vector(7 downto 0); -- rack_tag
avm_read : out std_logic; -- read
avm_write : out std_logic; -- write
avm_address : out std_logic_vector(25 downto 0); -- address
avm_writedata : out std_logic_vector(31 downto 0); -- writedata
avm_byte_enable : out std_logic_vector(3 downto 0); -- byteenable
avm_ready : in std_logic := 'X'; -- waitrequest_n
avm_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
avm_readdatavalid : in std_logic := 'X' -- readdatavalid
);
end component mem32_to_avalon_bridge;
component nios_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(28 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(28 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component nios_nios2_gen2_0;
component nios_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
out_port : out std_logic_vector(31 downto 0); -- export
irq : out std_logic -- irq
);
end component nios_pio_0;
component nios_mm_interconnect_0 is
port (
altmemddr_0_sysclk_clk : in std_logic := 'X'; -- clk
mem32_to_avalon_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
mem32_to_avalon_0_avalon_master_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
mem32_to_avalon_0_avalon_master_waitrequest : out std_logic; -- waitrequest
mem32_to_avalon_0_avalon_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
mem32_to_avalon_0_avalon_master_read : in std_logic := 'X'; -- read
mem32_to_avalon_0_avalon_master_readdata : out std_logic_vector(31 downto 0); -- readdata
mem32_to_avalon_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid
mem32_to_avalon_0_avalon_master_write : in std_logic := 'X'; -- write
mem32_to_avalon_0_avalon_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_address : in std_logic_vector(28 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(28 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
altmemddr_0_s1_address : out std_logic_vector(23 downto 0); -- address
altmemddr_0_s1_write : out std_logic; -- write
altmemddr_0_s1_read : out std_logic; -- read
altmemddr_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altmemddr_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
altmemddr_0_s1_beginbursttransfer : out std_logic; -- beginbursttransfer
altmemddr_0_s1_burstcount : out std_logic_vector(2 downto 0); -- burstcount
altmemddr_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
altmemddr_0_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid
altmemddr_0_s1_waitrequest : in std_logic := 'X'; -- waitrequest
io_bridge_0_avalon_slave_0_address : out std_logic_vector(19 downto 0); -- address
io_bridge_0_avalon_slave_0_write : out std_logic; -- write
io_bridge_0_avalon_slave_0_read : out std_logic; -- read
io_bridge_0_avalon_slave_0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
io_bridge_0_avalon_slave_0_writedata : out std_logic_vector(7 downto 0); -- writedata
io_bridge_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
io_bridge_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
pio_0_s1_address : out std_logic_vector(2 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic -- chipselect
);
end component nios_mm_interconnect_0;
component nios_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component nios_irq_mapper;
component nios_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component nios_rst_controller;
component nios_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component nios_rst_controller_001;
signal altmemddr_0_sysclk_clk : std_logic; -- altmemddr_0:phy_clk -> [sys_clock_clk, io_bridge_0:clock, irq_mapper:clk, mem32_to_avalon_0:clock, mm_interconnect_0:altmemddr_0_sysclk_clk, nios2_gen2_0:clk, pio_0:clk, rst_controller:clk, rst_controller_001:clk]
signal mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:mem32_to_avalon_0_avalon_master_waitrequest -> mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest:in
signal mem32_to_avalon_0_avalon_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:mem32_to_avalon_0_avalon_master_readdata -> mem32_to_avalon_0:avm_readdata
signal mem32_to_avalon_0_avalon_master_read : std_logic; -- mem32_to_avalon_0:avm_read -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_read
signal mem32_to_avalon_0_avalon_master_address : std_logic_vector(25 downto 0); -- mem32_to_avalon_0:avm_address -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_address
signal mem32_to_avalon_0_avalon_master_byteenable : std_logic_vector(3 downto 0); -- mem32_to_avalon_0:avm_byte_enable -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_byteenable
signal mem32_to_avalon_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:mem32_to_avalon_0_avalon_master_readdatavalid -> mem32_to_avalon_0:avm_readdatavalid
signal mem32_to_avalon_0_avalon_master_write : std_logic; -- mem32_to_avalon_0:avm_write -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_write
signal mem32_to_avalon_0_avalon_master_writedata : std_logic_vector(31 downto 0); -- mem32_to_avalon_0:avm_writedata -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_writedata
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(28 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(28 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_altmemddr_0_s1_beginbursttransfer : std_logic; -- mm_interconnect_0:altmemddr_0_s1_beginbursttransfer -> altmemddr_0:local_burstbegin
signal mm_interconnect_0_altmemddr_0_s1_readdata : std_logic_vector(31 downto 0); -- altmemddr_0:local_rdata -> mm_interconnect_0:altmemddr_0_s1_readdata
signal altmemddr_0_s1_waitrequest : std_logic; -- altmemddr_0:local_ready -> altmemddr_0_s1_waitrequest:in
signal mm_interconnect_0_altmemddr_0_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:altmemddr_0_s1_address -> altmemddr_0:local_address
signal mm_interconnect_0_altmemddr_0_s1_read : std_logic; -- mm_interconnect_0:altmemddr_0_s1_read -> altmemddr_0:local_read_req
signal mm_interconnect_0_altmemddr_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:altmemddr_0_s1_byteenable -> altmemddr_0:local_be
signal mm_interconnect_0_altmemddr_0_s1_readdatavalid : std_logic; -- altmemddr_0:local_rdata_valid -> mm_interconnect_0:altmemddr_0_s1_readdatavalid
signal mm_interconnect_0_altmemddr_0_s1_write : std_logic; -- mm_interconnect_0:altmemddr_0_s1_write -> altmemddr_0:local_write_req
signal mm_interconnect_0_altmemddr_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altmemddr_0_s1_writedata -> altmemddr_0:local_wdata
signal mm_interconnect_0_altmemddr_0_s1_burstcount : std_logic_vector(2 downto 0); -- mm_interconnect_0:altmemddr_0_s1_burstcount -> altmemddr_0:local_size
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata : std_logic_vector(7 downto 0); -- io_bridge_0:avs_readdata -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdata
signal io_bridge_0_avalon_slave_0_waitrequest : std_logic; -- io_bridge_0:avs_ready -> io_bridge_0_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_address : std_logic_vector(19 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_address -> io_bridge_0:avs_address
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_read -> io_bridge_0:avs_read
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid : std_logic; -- io_bridge_0:avs_readdatavalid -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_write -> io_bridge_0:avs_write
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_writedata -> io_bridge_0:avs_writedata
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal irq_mapper_receiver0_irq : std_logic; -- io_bridge_0:avs_irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- pio_0:irq -> irq_mapper:receiver1_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [io_bridge_0:reset, mem32_to_avalon_0:reset, mm_interconnect_0:mem32_to_avalon_0_reset_reset_bridge_in_reset_reset, rst_controller_reset_out_reset:in]
signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> rst_controller:reset_in0
signal altmemddr_0_reset_request_n_reset : std_logic; -- altmemddr_0:reset_request_n -> altmemddr_0_reset_request_n_reset:in
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, rst_controller_001_reset_out_reset:in]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [nios2_gen2_0:reset_req, rst_translator:reset_req_in]
signal mem32_to_avalon_0_avalon_master_inv : std_logic; -- mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest:inv -> mem32_to_avalon_0:avm_ready
signal mm_interconnect_0_altmemddr_0_s1_inv : std_logic; -- altmemddr_0_s1_waitrequest:inv -> mm_interconnect_0:altmemddr_0_s1_waitrequest
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_inv : std_logic; -- io_bridge_0_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:io_bridge_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [sys_reset_reset_n, pio_0:reset_n]
signal altmemddr_0_reset_request_n_reset_ports_inv : std_logic; -- altmemddr_0_reset_request_n_reset:inv -> [rst_controller:reset_in1, rst_controller_001:reset_in0]
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> nios2_gen2_0:reset_n
begin
altmemddr_0 : component nios_altmemddr_0
port map (
local_address => mm_interconnect_0_altmemddr_0_s1_address, -- s1.address
local_write_req => mm_interconnect_0_altmemddr_0_s1_write, -- .write
local_read_req => mm_interconnect_0_altmemddr_0_s1_read, -- .read
local_burstbegin => mm_interconnect_0_altmemddr_0_s1_beginbursttransfer, -- .beginbursttransfer
local_ready => altmemddr_0_s1_waitrequest, -- .waitrequest_n
local_rdata => mm_interconnect_0_altmemddr_0_s1_readdata, -- .readdata
local_rdata_valid => mm_interconnect_0_altmemddr_0_s1_readdatavalid, -- .readdatavalid
local_wdata => mm_interconnect_0_altmemddr_0_s1_writedata, -- .writedata
local_be => mm_interconnect_0_altmemddr_0_s1_byteenable, -- .byteenable
local_size => mm_interconnect_0_altmemddr_0_s1_burstcount, -- .burstcount
local_refresh_ack => mem_external_local_refresh_ack, -- external_connection.export
local_init_done => mem_external_local_init_done, -- .export
reset_phy_clk_n => mem_external_reset_phy_clk_n, -- .export
mem_odt => memory_mem_odt, -- memory.mem_odt
mem_clk => memory_mem_clk, -- .mem_clk
mem_clk_n => memory_mem_clk_n, -- .mem_clk_n
mem_cs_n => memory_mem_cs_n, -- .mem_cs_n
mem_cke => memory_mem_cke, -- .mem_cke
mem_addr => memory_mem_addr, -- .mem_addr
mem_ba => memory_mem_ba, -- .mem_ba
mem_ras_n => memory_mem_ras_n, -- .mem_ras_n
mem_cas_n => memory_mem_cas_n, -- .mem_cas_n
mem_we_n => memory_mem_we_n, -- .mem_we_n
mem_dq => memory_mem_dq, -- .mem_dq
mem_dqs => memory_mem_dqs, -- .mem_dqs
mem_dm => memory_mem_dm, -- .mem_dm
pll_ref_clk => clk50_clk, -- refclk.clk
soft_reset_n => reset_reset_n, -- soft_reset_n.reset_n
global_reset_n => reset_reset_n, -- global_reset_n.reset_n
reset_request_n => altmemddr_0_reset_request_n_reset, -- reset_request_n.reset_n
phy_clk => altmemddr_0_sysclk_clk, -- sysclk.clk
aux_full_rate_clk => altmemddr_0_auxfull_clk, -- auxfull.clk
aux_half_rate_clk => altmemddr_0_auxhalf_clk -- auxhalf.clk
);
io_bridge_0 : component avalon_to_io_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
avs_ready => io_bridge_0_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => altmemddr_0_sysclk_clk, -- clock.clk
io_ack => io_ack, -- io.ack
io_rdata => io_rdata, -- .rdata
io_read => io_read, -- .read
io_wdata => io_wdata, -- .wdata
io_write => io_write, -- .write
io_address => io_address, -- .address
io_irq => io_irq, -- .irq
avs_irq => irq_mapper_receiver0_irq -- irq.irq
);
mem32_to_avalon_0 : component mem32_to_avalon_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
clock => altmemddr_0_sysclk_clk, -- clock.clk
memreq_address => mem32_address, -- mem32_slave.address
memreq_read_writen => mem32_direction, -- .direction
memreq_byte_en => mem32_byte_en, -- .byte_en
memreq_data => mem32_wdata, -- .wdata
memreq_request => mem32_request, -- .request
memreq_tag => mem32_tag, -- .tag
memresp_dack_tag => mem32_dack_tag, -- .dack_tag
memresp_data => mem32_rdata, -- .rdata
memresp_rack => mem32_rack, -- .rack
memresp_rack_tag => mem32_rack_tag, -- .rack_tag
avm_read => mem32_to_avalon_0_avalon_master_read, -- avalon_master.read
avm_write => mem32_to_avalon_0_avalon_master_write, -- .write
avm_address => mem32_to_avalon_0_avalon_master_address, -- .address
avm_writedata => mem32_to_avalon_0_avalon_master_writedata, -- .writedata
avm_byte_enable => mem32_to_avalon_0_avalon_master_byteenable, -- .byteenable
avm_ready => mem32_to_avalon_0_avalon_master_inv, -- .waitrequest_n
avm_readdata => mem32_to_avalon_0_avalon_master_readdata, -- .readdata
avm_readdatavalid => mem32_to_avalon_0_avalon_master_readdatavalid -- .readdatavalid
);
nios2_gen2_0 : component nios_nios2_gen2_0
port map (
clk => altmemddr_0_sysclk_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
pio_0 : component nios_pio_0
port map (
clk => altmemddr_0_sysclk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
in_port => pio_in_port, -- external_connection.export
out_port => pio_out_port, -- .export
irq => irq_mapper_receiver1_irq -- irq.irq
);
mm_interconnect_0 : component nios_mm_interconnect_0
port map (
altmemddr_0_sysclk_clk => altmemddr_0_sysclk_clk, -- altmemddr_0_sysclk.clk
mem32_to_avalon_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- mem32_to_avalon_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
mem32_to_avalon_0_avalon_master_address => mem32_to_avalon_0_avalon_master_address, -- mem32_to_avalon_0_avalon_master.address
mem32_to_avalon_0_avalon_master_waitrequest => mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest, -- .waitrequest
mem32_to_avalon_0_avalon_master_byteenable => mem32_to_avalon_0_avalon_master_byteenable, -- .byteenable
mem32_to_avalon_0_avalon_master_read => mem32_to_avalon_0_avalon_master_read, -- .read
mem32_to_avalon_0_avalon_master_readdata => mem32_to_avalon_0_avalon_master_readdata, -- .readdata
mem32_to_avalon_0_avalon_master_readdatavalid => mem32_to_avalon_0_avalon_master_readdatavalid, -- .readdatavalid
mem32_to_avalon_0_avalon_master_write => mem32_to_avalon_0_avalon_master_write, -- .write
mem32_to_avalon_0_avalon_master_writedata => mem32_to_avalon_0_avalon_master_writedata, -- .writedata
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
altmemddr_0_s1_address => mm_interconnect_0_altmemddr_0_s1_address, -- altmemddr_0_s1.address
altmemddr_0_s1_write => mm_interconnect_0_altmemddr_0_s1_write, -- .write
altmemddr_0_s1_read => mm_interconnect_0_altmemddr_0_s1_read, -- .read
altmemddr_0_s1_readdata => mm_interconnect_0_altmemddr_0_s1_readdata, -- .readdata
altmemddr_0_s1_writedata => mm_interconnect_0_altmemddr_0_s1_writedata, -- .writedata
altmemddr_0_s1_beginbursttransfer => mm_interconnect_0_altmemddr_0_s1_beginbursttransfer, -- .beginbursttransfer
altmemddr_0_s1_burstcount => mm_interconnect_0_altmemddr_0_s1_burstcount, -- .burstcount
altmemddr_0_s1_byteenable => mm_interconnect_0_altmemddr_0_s1_byteenable, -- .byteenable
altmemddr_0_s1_readdatavalid => mm_interconnect_0_altmemddr_0_s1_readdatavalid, -- .readdatavalid
altmemddr_0_s1_waitrequest => mm_interconnect_0_altmemddr_0_s1_inv, -- .waitrequest
io_bridge_0_avalon_slave_0_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- io_bridge_0_avalon_slave_0.address
io_bridge_0_avalon_slave_0_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
io_bridge_0_avalon_slave_0_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- .read
io_bridge_0_avalon_slave_0_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
io_bridge_0_avalon_slave_0_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
io_bridge_0_avalon_slave_0_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
io_bridge_0_avalon_slave_0_waitrequest => mm_interconnect_0_io_bridge_0_avalon_slave_0_inv, -- .waitrequest
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect -- .chipselect
);
irq_mapper : component nios_irq_mapper
port map (
clk => altmemddr_0_sysclk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component nios_rst_controller
generic map (
NUM_RESET_INPUTS => 2,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
reset_in1 => altmemddr_0_reset_request_n_reset_ports_inv, -- reset_in1.reset
clk => altmemddr_0_sysclk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component nios_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => altmemddr_0_reset_request_n_reset_ports_inv, -- reset_in0.reset
clk => altmemddr_0_sysclk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
mem32_to_avalon_0_avalon_master_inv <= not mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest;
mm_interconnect_0_altmemddr_0_s1_inv <= not altmemddr_0_s1_waitrequest;
mm_interconnect_0_io_bridge_0_avalon_slave_0_inv <= not io_bridge_0_avalon_slave_0_waitrequest;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
altmemddr_0_reset_request_n_reset_ports_inv <= not altmemddr_0_reset_request_n_reset;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
sys_clock_clk <= altmemddr_0_sysclk_clk;
sys_reset_reset_n <= rst_controller_reset_out_reset_ports_inv;
end architecture rtl; -- of nios
| gpl-3.0 | 58b8a4e05eb2b1d9678c5a05b9d6a125 | 0.45698 | 3.759644 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_host_nano.vhd | 1 | 9,936 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_host_controller
-- Date:2015-02-12
-- Author: Gideon
-- Description: Top level of second generation USB controller with memory
-- interface.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.usb_pkg.all;
use work.usb_cmd_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host_nano is
generic (
g_big_endian : boolean;
g_incl_debug : boolean := false;
g_tag : std_logic_vector(7 downto 0) := X"05";
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
ulpi_nxt : in std_logic;
ulpi_dir : in std_logic;
ulpi_stp : out std_logic;
ulpi_data : inout std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
error_pulse : out std_logic;
--
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_mem_req : out t_mem_req_32;
sys_mem_resp: in t_mem_resp_32;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp;
sys_irq : out std_logic );
end entity;
architecture arch of usb_host_nano is
signal nano_addr : unsigned(7 downto 0);
signal nano_write : std_logic;
signal nano_read : std_logic;
signal nano_wdata : std_logic_vector(15 downto 0);
signal nano_rdata : std_logic_vector(15 downto 0);
signal nano_rdata_cmd : std_logic_vector(15 downto 0);
signal nano_stall : std_logic := '0';
signal reg_read : std_logic := '0';
signal reg_write : std_logic := '0';
signal reg_ack : std_logic;
signal reg_address : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
signal reg_rdata : std_logic_vector(7 downto 0);
-- cmd interface
signal cmd_addr : std_logic_vector(3 downto 0);
signal cmd_valid : std_logic;
signal cmd_write : std_logic;
signal cmd_wdata : std_logic_vector(15 downto 0);
signal cmd_ack : std_logic;
signal cmd_ready : std_logic;
signal status : std_logic_vector(7 downto 0);
signal speed : std_logic_vector(1 downto 0) := "10";
signal do_chirp : std_logic;
signal chirp_data : std_logic;
signal sof_enable : std_logic;
signal mem_ctrl_ready : std_logic;
signal buf_address : unsigned(10 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal sys_buf_addr : std_logic_vector(10 downto 2);
signal sys_buf_en : std_logic;
signal sys_buf_we : std_logic_vector(3 downto 0);
signal sys_buf_wdata : std_logic_vector(31 downto 0);
signal sys_buf_rdata : std_logic_vector(31 downto 0);
signal sys_buf_rdata_le: std_logic_vector(31 downto 0);
signal usb_tx_req : t_usb_tx_req;
signal usb_tx_resp : t_usb_tx_resp;
signal usb_rx : t_usb_rx;
signal usb_cmd_req : t_usb_cmd_req;
signal usb_cmd_resp : t_usb_cmd_resp;
signal frame_count : unsigned(15 downto 0);
signal sof_tick : std_logic;
signal interrupt : std_logic;
begin
i_intf: entity work.usb_host_interface
generic map (
g_simulation => g_simulation )
port map (
clock => clock,
reset => reset,
usb_rx => usb_rx,
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp,
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_rdata => reg_rdata,
reg_ack => reg_ack,
do_chirp => do_chirp,
chirp_data => chirp_data,
status => status,
speed => speed,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_dir => ulpi_dir,
ulpi_data => ulpi_data );
i_seq: entity work.host_sequencer
port map (
clock => clock,
reset => reset,
buf_address => buf_address,
buf_en => buf_en,
buf_we => buf_we,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
sof_enable => sof_enable,
sof_tick => sof_tick,
speed => speed,
frame_count => frame_count,
error_pulse => error_pulse,
usb_cmd_req => usb_cmd_req,
usb_cmd_resp => usb_cmd_resp,
usb_rx => usb_rx,
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp );
i_buf_ram: RAMB16BWE_S36_S9
port map (
CLKB => clock,
SSRB => reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => std_logic_vector(buf_address),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata,
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_buf_we,
ADDRA => sys_buf_addr,
DIA => sys_buf_wdata,
DIPA => "0000",
DOA => sys_buf_rdata_le );
sys_buf_rdata <= byte_swap(sys_buf_rdata_le, g_big_endian);
i_bridge_to_mem_ctrl: entity work.bridge_to_mem_ctrl
port map (
ulpi_clock => clock,
ulpi_reset => reset,
nano_addr => nano_addr,
nano_write => nano_write,
nano_wdata => nano_wdata,
sys_clock => sys_clock,
sys_reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack );
i_memctrl: entity work.usb_memory_ctrl
generic map (
g_big_endian => g_big_endian,
g_tag => g_tag )
port map (
clock => sys_clock,
reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack,
cmd_ready => cmd_ready,
-- BRAM interface
ram_addr => sys_buf_addr,
ram_en => sys_buf_en,
ram_we => sys_buf_we,
ram_wdata => sys_buf_wdata,
ram_rdata => sys_buf_rdata,
-- memory interface
mem_req => sys_mem_req,
mem_resp => sys_mem_resp );
i_sync: entity work.level_synchronizer
port map (
clock => clock,
reset => reset,
input => cmd_ready,
input_c => mem_ctrl_ready );
i_nano_io: entity work.nano_minimal_io
generic map (
g_support_suspend => false )
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => nano_stall,
reg_read => reg_read,
reg_write => reg_write,
reg_ack => reg_ack,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_rdata => reg_rdata,
cmd_response => nano_rdata_cmd,
status => status,
mem_ctrl_ready => mem_ctrl_ready,
frame_count => frame_count,
do_chirp => do_chirp,
chirp_data => chirp_data,
connected => open,
operational => open,
suspended => open,
sof_enable => sof_enable,
sof_tick => sof_tick,
speed => speed,
interrupt_out => interrupt );
i_sync2: entity work.pulse_synchronizer
port map (
clock_in => clock,
pulse_in => interrupt,
clock_out => sys_clock,
pulse_out => sys_irq );
i_cmd_io: entity work.usb_cmd_nano
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_wdata => nano_wdata,
io_rdata => nano_rdata_cmd,
cmd_req => usb_cmd_req,
cmd_resp => usb_cmd_resp );
i_debug: entity work.usb_debug
generic map (
g_enabled => g_incl_debug )
port map (
clock => clock,
reset => reset,
cmd_req => usb_cmd_req,
cmd_resp => usb_cmd_resp,
debug_data => debug_data,
debug_valid => debug_valid
);
i_nano: entity work.nano
generic map (
g_big_endian => g_big_endian )
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => nano_stall,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
end arch;
| gpl-3.0 | ae5a5e257a15179bc9dd829262c3797f | 0.483092 | 3.568966 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/shifter.vhd | 1 | 2,336 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shifter is
port (
operation : in std_logic_vector(2 downto 0);
bypass : in std_logic := '0';
c_in : in std_logic;
n_in : in std_logic;
z_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
c_out : out std_logic;
n_out : out std_logic;
z_out : out std_logic;
data_out : out std_logic_vector(7 downto 0) := X"00");
end shifter;
architecture gideon of shifter is
signal data_out_i : std_logic_vector(7 downto 0) := X"00";
signal zero : std_logic := '0';
constant c_asl : std_logic_vector(2 downto 0) := "000";
constant c_rol : std_logic_vector(2 downto 0) := "001";
constant c_lsr : std_logic_vector(2 downto 0) := "010";
constant c_ror : std_logic_vector(2 downto 0) := "011";
constant c_sta : std_logic_vector(2 downto 0) := "100";
constant c_lda : std_logic_vector(2 downto 0) := "101";
constant c_dec : std_logic_vector(2 downto 0) := "110";
constant c_inc : std_logic_vector(2 downto 0) := "111";
begin
-- ASL $nn ROL $nn LSR $nn ROR $nn STX $nn LDX $nn DEC $nn INC $nn
with operation select data_out_i <=
data_in(6 downto 0) & '0' when c_asl,
data_in(6 downto 0) & c_in when c_rol,
'0' & data_in(7 downto 1) when c_lsr,
c_in & data_in(7 downto 1) when c_ror,
std_logic_vector(unsigned(data_in) - 1) when c_dec,
std_logic_vector(unsigned(data_in) + 1) when c_inc,
data_in when others;
zero <= '1' when data_out_i = X"00" else '0';
with operation select c_out <=
data_in(7) when c_asl | c_rol,
data_in(0) when c_lsr | c_ror,
c_in when others;
with operation select z_out <=
zero when c_asl | c_rol | c_lsr | c_ror | c_lda | c_dec | c_inc,
z_in when others;
with operation select n_out <=
data_out_i(7) when c_asl | c_rol | c_lsr | c_ror | c_lda | c_dec | c_inc,
n_in when others;
data_out <= data_out_i when bypass = '0' else data_in;
end gideon;
| gpl-3.0 | b2539cd13382960d9a73cd21533df0e6 | 0.52012 | 3.045632 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/ultimate_fpga/vhdl_source/u2p_cia_lockstep.vhd | 1 | 30,306 | -------------------------------------------------------------------------------
-- Title : u2p_nios
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel based on the "solo" nios; without Altera DDR2 ctrl.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.my_math_pkg.all;
entity u2p_cia_lockstep is
port (
dummy : out std_logic;
-- slot side
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : inout std_logic;
SLOT_BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : out std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : in std_logic;
SLOT_ROMLn : in std_logic;
SLOT_IO1n : in std_logic;
SLOT_IO2n : in std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_DM : inout std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Misc
BOARD_REVn : in std_logic_vector(4 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_cia_lockstep is
function or_reduce(a: std_logic_vector) return std_logic is
variable o : std_logic;
begin
o := '0';
for i in a'range loop
o := o or a(i);
end loop;
return o;
end function;
component nios_solo is
port (
clk_clk : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component nios_solo;
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
signal por_n : std_logic;
signal ref_reset : std_logic;
signal por_count : unsigned(15 downto 0) := (others => '0');
signal led_n : std_logic_vector(0 to 3);
signal RSTn_out : std_logic;
signal irq_oc, nmi_oc, rst_oc, dma_oc, exrom_oc, game_oc : std_logic;
signal slot_addr_o : std_logic_vector(15 downto 0);
signal slot_addr_t : std_logic;
signal slot_data_o : std_logic_vector(7 downto 0);
signal slot_data_t : std_logic;
signal slot_rwn_o : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal eth_reset : std_logic;
signal ulpi_reset_req : std_logic;
signal button_i : std_logic_vector(2 downto 0);
signal buffer_en : std_logic;
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal is_idle : std_logic;
signal cpu_mem_req : t_mem_req_32;
signal cpu_mem_resp : t_mem_resp_32;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal uart_txd_from_logic : std_logic;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_scl_i : std_logic;
signal i2c_scl_o : std_logic;
signal mdio_o : std_logic;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
signal sw_iec_o : std_logic_vector(3 downto 0);
signal sw_iec_i : std_logic_vector(3 downto 0);
-- io buses
signal io_irq : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_u2p_req : t_io_req;
signal io_u2p_resp : t_io_resp;
signal io_req_new_io : t_io_req;
signal io_resp_new_io : t_io_resp;
signal io_req_remote : t_io_req;
signal io_resp_remote : t_io_resp;
signal io_req_ddr2 : t_io_req;
signal io_resp_ddr2 : t_io_resp;
-- audio
signal audio_speaker : signed(12 downto 0);
signal audio_left : signed(18 downto 0);
signal audio_right : signed(18 downto 0);
signal speaker_vol : std_logic_vector(3 downto 0);
begin
process(RMII_REFCLK)
begin
if rising_edge(RMII_REFCLK) then
if por_count = X"FFFF" then
por_n <= '1';
else
por_n <= '0';
por_count <= por_count + 1;
end if;
end if;
end process;
ref_reset <= not por_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => open );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => sys_reset,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => ulpi_reset_req,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
i_nios: nios_solo
port map (
clk_clk => sys_clock,
reset_reset_n => not sys_reset,
io_ack => io_resp.ack,
io_rdata => io_resp.data,
io_read => io_req.read,
io_wdata => io_req.data,
io_write => io_req.write,
unsigned(io_address) => io_req.address,
io_irq => io_irq,
io_u2p_ack => io_u2p_resp.ack,
io_u2p_rdata => io_u2p_resp.data,
io_u2p_read => io_u2p_req.read,
io_u2p_wdata => io_u2p_req.data,
io_u2p_write => io_u2p_req.write,
unsigned(io_u2p_address) => io_u2p_req.address,
io_u2p_irq => '0',
unsigned(mem_mem_req_address) => cpu_mem_req.address,
mem_mem_req_byte_en => cpu_mem_req.byte_en,
mem_mem_req_read_writen => cpu_mem_req.read_writen,
mem_mem_req_request => cpu_mem_req.request,
mem_mem_req_tag => cpu_mem_req.tag,
mem_mem_req_wdata => cpu_mem_req.data,
mem_mem_resp_dack_tag => cpu_mem_resp.dack_tag,
mem_mem_resp_data => cpu_mem_resp.data,
mem_mem_resp_rack_tag => cpu_mem_resp.rack_tag
);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 9,
g_ports => 3
)
port map (
clock => sys_clock,
req => io_u2p_req,
resp => io_u2p_resp,
reqs(0) => io_req_new_io,
reqs(1) => io_req_ddr2,
reqs(2) => io_req_remote,
resps(0) => io_resp_new_io,
resps(1) => io_resp_ddr2,
resps(2) => io_resp_remote
);
i_memphy: entity work.ddr2_ctrl
port map (
ref_clock => RMII_REFCLK,
ref_reset => ref_reset,
sys_clock_o => sys_clock,
sys_reset_o => sys_reset,
clock => sys_clock,
reset => sys_reset,
io_req => io_req_ddr2,
io_resp => io_resp_ddr2,
inhibit => memctrl_inhibit,
is_idle => is_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_ODT => SDRAM_ODT,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA(1 downto 0),
SDRAM_DM => SDRAM_DM,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS
);
i_remote: entity work.update_io
port map (
clock => sys_clock,
reset => sys_reset,
slow_clock => audio_clock,
slow_reset => audio_reset,
io_req => io_req_remote,
io_resp => io_resp_remote,
flash_selck => FLASH_SELCK,
flash_sel => FLASH_SEL
);
i_u2p_io: entity work.u2p_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_new_io,
io_resp => io_resp_new_io,
mdc => MDIO_CLK,
mdio_i => MDIO_DATA,
mdio_o => mdio_o,
i2c_scl_i => i2c_scl_i,
i2c_scl_o => i2c_scl_o,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
iec_i => sw_iec_i,
iec_o => sw_iec_o,
board_rev => not BOARD_REVn,
eth_irq_i => ETH_IRQn,
speaker_en => SPEAKER_ENABLE,
speaker_vol=> speaker_vol,
hub_reset_n=> HUB_RESETn,
ulpi_reset => ulpi_reset_req,
buffer_en => buffer_en
);
i2c_scl_i <= I2C_SCL and I2C_SCL_18;
i2c_sda_i <= I2C_SDA and I2C_SDA_18;
I2C_SCL <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA <= '0' when i2c_sda_o = '0' else 'Z';
I2C_SCL_18 <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA_18 <= '0' when i2c_sda_o = '0' else 'Z';
MDIO_DATA <= '0' when mdio_o = '0' else 'Z';
i_logic: entity work.ultimate_logic_32
generic map (
g_version => X"0D",
g_simulation => false,
g_ultimate2plus => true,
g_clock_freq => 62_500_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_microblaze => false,
g_big_endian => false,
g_icap => false,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => false,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => false,
g_hardware_iec => true,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => false,
g_analyzer => true,
g_profiler => false,
g_rmii => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
ext_io_req => io_req,
ext_io_resp => io_resp,
ext_mem_req => cpu_mem_req,
ext_mem_resp=> cpu_mem_resp,
cpu_irq => io_irq,
-- slot side
BUFFER_ENn => open,
VCC => SLOT_VCC,
phi2_i => SLOT_PHI2,
dotclk_i => SLOT_DOTCLK,
rstn_i => SLOT_RSTn,
rstn_o => RSTn_out,
slot_addr_o => slot_addr_o,
slot_addr_i => SLOT_ADDR,
slot_addr_t => slot_addr_t,
slot_data_o => slot_data_o,
slot_data_i => SLOT_DATA,
slot_data_t => slot_data_t,
rwn_i => SLOT_RWn,
rwn_o => slot_rwn_o,
exromn_i => SLOT_EXROMn,
exromn_o => exrom_oc,
gamen_i => SLOT_GAMEn,
gamen_o => game_oc,
irqn_i => SLOT_IRQn,
irqn_o => irq_oc,
nmin_i => SLOT_NMIn,
nmin_o => nmi_oc,
ba_i => SLOT_BA,
dman_o => dma_oc,
romhn_i => SLOT_ROMHn,
romln_i => SLOT_ROMLn,
io1n_i => SLOT_IO1n,
io2n_i => SLOT_IO2n,
-- local bus side
mem_inhibit => memctrl_inhibit,
mem_req => mem_req,
mem_resp => mem_resp,
-- Audio outputs
audio_speaker => audio_speaker,
audio_left => audio_left,
audio_right => audio_right,
speaker_vol => speaker_vol,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
MOTOR_LEDn => led_n(0),
DISK_ACTn => led_n(1),
CART_LEDn => led_n(2),
SDACT_LEDn => led_n(3),
-- Debug UART
UART_TXD => uart_txd_from_logic,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => open,
SD_CLK => open,
SD_MOSI => open,
SD_MISO => '1',
SD_CARDDETn => '1',
SD_DATA => open,
-- RTC Interface
RTC_CS => open,
RTC_SCK => open,
RTC_MOSI => open,
RTC_MISO => '1',
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Ethernet Interface (RMII)
eth_clock => RMII_REFCLK,
eth_reset => eth_reset,
rmii_crs_dv => RMII_CRS_DV,
rmii_rxd => RMII_RX_DATA,
rmii_tx_en => RMII_TX_EN,
rmii_txd => RMII_TX_DATA,
-- Buttons
BUTTON => button_i );
SLOT_RSTn <= '0' when RSTn_out = '0' else 'Z';
SLOT_ADDR <= slot_addr_o when slot_addr_t = '1' else (others => 'Z');
SLOT_DATA <= slot_data_o when slot_data_t = '1' else (others => 'Z');
SLOT_RWn <= slot_rwn_o when slot_addr_t = '1' else 'Z';
irq_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => irq_oc, oc_out => SLOT_IRQn);
nmi_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => nmi_oc, oc_out => SLOT_NMIn);
dma_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => dma_oc, oc_out => SLOT_DMAn);
exr_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => exrom_oc, oc_out => SLOT_EXROMn);
gam_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => game_oc, oc_out => SLOT_GAMEn);
LED_MOTORn <= led_n(0) xor sys_reset;
LED_DISKn <= led_n(1) xor sys_reset;
LED_CARTn <= led_n(2) xor sys_reset;
LED_SDACTn <= led_n(3) xor sys_reset;
IEC_SRQ_IN <= '0' when iec_srq_o = '0' or sw_iec_o(3) = '0' else 'Z';
IEC_ATN <= '0' when iec_atn_o = '0' or sw_iec_o(2) = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' or sw_iec_o(1) = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' or sw_iec_o(0) = '0' else 'Z';
sw_iec_i <= IEC_SRQ_IN & IEC_ATN & IEC_DATA & IEC_CLOCK;
button_i <= not BUTTON;
ULPI_RESET <= por_n;
UART_TXD <= uart_txd_from_logic; -- and uart_txd_from_qsys;
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_divider => 10,
g_width => audio_speaker'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => audio_speaker,
dac_out => SPEAKER_DATA );
b_audio: block
signal audio_get_sample : std_logic;
signal sys_get_sample : std_logic;
signal stream_out_data : std_logic_vector(23 downto 0);
signal stream_out_tag : std_logic_vector(0 downto 0);
signal stream_out_valid : std_logic;
signal stream_in_data : std_logic_vector(23 downto 0);
signal stream_in_tag : std_logic_vector(0 downto 0);
signal stream_in_ready : std_logic;
signal audio_left_filt : signed(17 downto 0);
signal audio_right_filt : signed(17 downto 0);
signal audio_audio_left : std_logic_vector(audio_left_filt'range);
signal audio_audio_right: std_logic_vector(audio_right_filt'range);
begin
i_filt_left: entity work.lp_filter
port map (
clock => sys_clock,
reset => sys_reset,
signal_in => audio_left(18 downto 1),
low_pass => audio_left_filt );
i_filt_right: entity work.lp_filter
port map (
clock => sys_clock,
reset => sys_reset,
signal_in => audio_right(18 downto 1),
low_pass => audio_right_filt );
i2s: entity work.i2s_serializer
port map (
clock => audio_clock,
reset => audio_reset,
i2s_out => AUDIO_SDO,
i2s_in => AUDIO_SDI,
i2s_bclk => AUDIO_BCLK,
i2s_fs => AUDIO_LRCLK,
stream_out_data => stream_out_data,
stream_out_tag => stream_out_tag,
stream_out_valid => stream_out_valid,
stream_in_data => stream_in_data,
stream_in_tag => stream_in_tag,
stream_in_valid => '1',
stream_in_ready => stream_in_ready );
AUDIO_MCLK <= audio_clock;
i_sync_get: entity work.pulse_synchronizer
port map (
clock_in => audio_clock,
pulse_in => audio_get_sample,
clock_out => sys_clock,
pulse_out => sys_get_sample
);
i_sync_left: entity work.synchronizer_gzw
generic map (
g_width => audio_left_filt'length,
g_fast => false
)
port map(
tx_clock => sys_clock,
tx_push => sys_get_sample,
tx_data => std_logic_vector(audio_left_filt),
tx_done => open,
rx_clock => audio_clock,
rx_new_data => open,
rx_data => audio_audio_left
);
i_sync_right: entity work.synchronizer_gzw
generic map (
g_width => audio_right_filt'length,
g_fast => false
)
port map(
tx_clock => sys_clock,
tx_push => sys_get_sample,
tx_data => std_logic_vector(audio_right_filt),
tx_done => open,
rx_clock => audio_clock,
rx_new_data => open,
rx_data => audio_audio_right
);
process(audio_clock)
begin
if rising_edge(audio_clock) then
audio_get_sample <= '0';
if stream_in_ready = '1' then
if stream_in_tag(0) = '0' then
stream_in_tag(0) <= '1';
stream_in_data <= std_logic_vector(left_scale(signed(audio_audio_right), 1)) & "0000000";
audio_get_sample <= '1';
else
stream_in_tag(0) <= '0';
stream_in_data <= std_logic_vector(left_scale(signed(audio_audio_left), 1)) & "0000000";
end if;
end if;
if audio_reset = '1' then
stream_in_tag(0) <= '1';
end if;
end if;
end process;
end block;
SLOT_BUFFER_ENn <= not buffer_en;
b_cia: block
signal cia2_port_a_i : std_logic_vector(7 downto 0) := X"FF";
signal cia2_port_a_o : std_logic_vector(7 downto 0) := X"FF";
signal cia2_port_a_t : std_logic_vector(7 downto 0) := X"FF";
signal cia2_port_b_i : std_logic_vector(7 downto 0) := X"FF";
signal cia2_port_b_o : std_logic_vector(7 downto 0) := X"FF";
signal cia2_port_b_t : std_logic_vector(7 downto 0) := X"FF";
signal cia2_sp_i : std_logic := '1';
signal cia2_sp_o : std_logic := '1';
signal cia2_sp_t : std_logic := '1';
signal cia2_cnt_i : std_logic := '1';
signal cia2_cnt_o : std_logic := '1';
signal cia2_cnt_t : std_logic := '1';
signal cia2_pc_o : std_logic := '1';
signal cia2_flag_i : std_logic := '1';
signal cia2_irq : std_logic;
signal cia2_clock : std_logic;
signal cia2_reset : std_logic;
signal cia2_read : std_logic;
signal cia2_write : std_logic;
signal cia2_rdata : std_logic_vector(7 downto 0);
signal bus_data_latch : std_logic_vector(7 downto 0);
signal read_d : std_logic;
signal read_error : std_logic;
signal nmi_error : std_logic;
begin
cia2_write <= '1' when SLOT_RWn = '0' and SLOT_ADDR(15 downto 8) = X"DD" and SLOT_PHI2 = '1' else '0';
cia2_read <= '1' when SLOT_RWn = '1' and SLOT_ADDR(15 downto 8) = X"DD" and SLOT_PHI2 = '1' else '0';
cia2_clock <= not SLOT_PHI2;
process(cia2_clock)
begin
if rising_edge(cia2_clock) then
cia2_reset <= not SLOT_RSTn;
bus_data_latch <= SLOT_DATA;
read_d <= cia2_read;
end if;
end process;
process(SLOT_PHI2)
begin
if rising_edge(SLOT_PHI2) then
if cia2_rdata /= bus_data_latch and read_d = '1' then
read_error <= '1';
else
read_error <= '0';
end if;
end if;
end process;
nmi_error <= cia2_irq xnor SLOT_NMIn;
dummy <= or_reduce(nmi_error & read_error & cia2_rdata);
i_cia2: entity work.cia_registers
generic map (
g_unit_name => "CIA_2" )
port map (
clock => cia2_clock,
rising => '0',
falling => '1',
reset => cia2_reset,
addr => unsigned(SLOT_ADDR(3 downto 0)),
wen => cia2_write,
ren => cia2_read,
data_out => cia2_rdata,
data_in => SLOT_DATA,
-- pio --
port_a_o => cia2_port_a_o,
port_a_t => cia2_port_a_t,
port_a_i => cia2_port_a_i,
port_b_o => cia2_port_b_o,
port_b_t => cia2_port_b_t,
port_b_i => cia2_port_b_i,
-- serial pin
sp_o => cia2_sp_o,
sp_i => cia2_sp_i,
sp_t => cia2_sp_t,
cnt_i => cia2_cnt_i,
cnt_o => cia2_cnt_o,
cnt_t => cia2_cnt_t,
tod_pin => '0',
pc_o => cia2_pc_o,
flag_i => cia2_flag_i,
irq => cia2_irq );
cia2_port_a_i(7) <= (cia2_port_a_o(7) or not cia2_port_a_t(7)) and IEC_DATA;
cia2_port_a_i(6) <= (cia2_port_a_o(6) or not cia2_port_a_t(6)) and IEC_CLOCK;
cia2_port_a_i(5) <= (cia2_port_a_o(5) or not cia2_port_a_t(5));
cia2_port_a_i(4) <= (cia2_port_a_o(4) or not cia2_port_a_t(4));
cia2_port_a_i(3) <= (cia2_port_a_o(3) or not cia2_port_a_t(3));
cia2_port_a_i(2) <= (cia2_port_a_o(2) or not cia2_port_a_t(2));
cia2_port_a_i(1) <= (cia2_port_a_o(1) or not cia2_port_a_t(1));
cia2_port_a_i(0) <= (cia2_port_a_o(0) or not cia2_port_a_t(0));
cia2_port_b_i <= cia2_port_b_o or not cia2_port_b_t;
cia2_cnt_i <= cia2_cnt_o or not cia2_cnt_t;
cia2_sp_i <= cia2_sp_o or not cia2_sp_t;
end block;
end architecture;
| gpl-3.0 | 05d7abe1b1ae00efb2d4df90410ff4f6 | 0.467498 | 3.290911 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio/i2s_serializer.vhd | 1 | 2,654 | -------------------------------------------------------------------------------
-- Title : i2s_serializer
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: I2S Serializer / Deserializer
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2s_serializer is
port (
clock : in std_logic; -- equals i2s_mclk
reset : in std_logic;
i2s_out : out std_logic;
i2s_in : in std_logic;
i2s_bclk : out std_logic;
i2s_fs : out std_logic;
sample_pulse : out std_logic;
left_sample_out : out std_logic_vector(23 downto 0);
right_sample_out : out std_logic_vector(23 downto 0);
left_sample_in : in std_logic_vector(23 downto 0);
right_sample_in : in std_logic_vector(23 downto 0) );
end entity;
architecture rtl of i2s_serializer is
signal bit_count : unsigned(7 downto 0);
signal shift_reg : std_logic_vector(31 downto 0) := (others => '0');
begin
-- mclk = 256*fs. bclk = 64*fs (32 bits per channel)
process(clock)
begin
if rising_edge(clock) then
bit_count <= bit_count + 1;
i2s_bclk <= bit_count(1);
i2s_fs <= bit_count(7);
sample_pulse <= '0';
if bit_count(1 downto 0) = "00" then
i2s_out <= shift_reg(shift_reg'left);
elsif bit_count(1 downto 0) = "10" then
shift_reg <= shift_reg(shift_reg'left-1 downto 0) & i2s_in;
end if;
case bit_count is
when X"7E" =>
left_sample_out <= shift_reg(shift_reg'left-2 downto shift_reg'left - 25);
when X"FE" =>
right_sample_out <= shift_reg(shift_reg'left-2 downto shift_reg'left - 25);
sample_pulse <= '1';
when X"02" =>
shift_reg <= left_sample_in & "0000000" & i2s_in;
when X"82" =>
shift_reg <= right_sample_in & "0000000" & i2s_in;
when others =>
null;
end case;
if reset='1' then
bit_count <= (others => '1');
i2s_out <= '0';
left_sample_out <= (others => '0');
right_sample_out <= (others => '0');
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 1851caed1e8549260c4f12fceadd4597 | 0.44951 | 3.868805 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/cpu_part_1541.vhd | 1 | 14,652 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity cpu_part_1541 is
generic (
g_tag : std_logic_vector(7 downto 0) := X"02";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
falling : in std_logic;
rising : in std_logic;
reset : in std_logic;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
mem_busy : out std_logic;
-- Debug port
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
-- configuration
bank_is_ram : in std_logic_vector(7 downto 1);
-- Parallel cable pins
via1_port_a_o : out std_logic_vector(7 downto 0);
via1_port_a_i : in std_logic_vector(7 downto 0);
via1_port_a_t : out std_logic_vector(7 downto 0);
via1_ca2_o : out std_logic;
via1_ca2_i : in std_logic;
via1_ca2_t : out std_logic;
via1_cb1_o : out std_logic;
via1_cb1_i : in std_logic;
via1_cb1_t : out std_logic;
-- drive pins
power : in std_logic;
drive_address : in std_logic_vector(1 downto 0);
motor_on : out std_logic;
mode : out std_logic;
write_prot_n : in std_logic;
step : out std_logic_vector(1 downto 0);
rate_ctrl : out std_logic_vector(1 downto 0);
byte_ready : in std_logic;
sync : in std_logic;
drv_rdata : in std_logic_vector(7 downto 0);
drv_wdata : out std_logic_vector(7 downto 0);
act_led : out std_logic );
end cpu_part_1541;
architecture structural of cpu_part_1541 is
signal soe : std_logic;
signal so_n : std_logic;
signal bank_is_ram_i : std_logic_vector(7 downto 0);
signal cpu_write : std_logic;
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_addr : std_logic_vector(16 downto 0);
signal cpu_irqn : std_logic;
signal ext_rdata : std_logic_vector(7 downto 0) := X"00";
signal io_rdata : std_logic_vector(7 downto 0);
signal via1_data : std_logic_vector(7 downto 0);
signal via2_data : std_logic_vector(7 downto 0);
signal via1_wen : std_logic;
signal via1_ren : std_logic;
signal via2_wen : std_logic;
signal via2_ren : std_logic;
signal via1_port_b_o : std_logic_vector(7 downto 0);
signal via1_port_b_t : std_logic_vector(7 downto 0);
signal via1_port_b_i : std_logic_vector(7 downto 0);
signal via1_ca1 : std_logic;
signal via1_cb2_o : std_logic;
signal via1_cb2_i : std_logic;
signal via1_cb2_t : std_logic;
signal via1_irq : std_logic;
signal via2_port_b_o : std_logic_vector(7 downto 0);
signal via2_port_b_t : std_logic_vector(7 downto 0);
signal via2_port_b_i : std_logic_vector(7 downto 0);
signal via2_ca2_o : std_logic;
signal via2_ca2_i : std_logic;
signal via2_ca2_t : std_logic;
signal via2_cb1_o : std_logic;
signal via2_cb1_i : std_logic;
signal via2_cb1_t : std_logic;
signal via2_cb2_o : std_logic;
signal via2_cb2_i : std_logic;
signal via2_cb2_t : std_logic;
signal via2_irq : std_logic;
signal io_select : std_logic;
signal cpu_clk_en : std_logic;
signal cpu_rising : std_logic;
type t_mem_state is (idle, newcycle, extcycle);
signal mem_state : t_mem_state;
-- "old" style signals
signal mem_request : std_logic;
signal mem_addr : unsigned(25 downto 0);
signal mem_rwn : std_logic;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
signal mem_wdata : std_logic_vector(7 downto 0);
begin
mem_req.request <= mem_request;
mem_req.address <= mem_addr;
mem_req.read_writen <= mem_rwn;
mem_req.data <= mem_wdata;
mem_req.tag <= g_tag;
mem_req.size <= "00"; -- 1 byte at a time
mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0';
cpu: entity work.cpu6502(cycle_exact)
port map (
cpu_clk => clock,
cpu_clk_en => cpu_clk_en,
cpu_reset => reset,
cpu_write => cpu_write,
cpu_wdata => cpu_wdata,
cpu_rdata => cpu_rdata,
cpu_addr => cpu_addr,
--cpu_pc => cpu_pc,
IRQn => cpu_irqn, -- IRQ interrupt (level sensitive)
NMIn => '1',
SOn => so_n );
-- Generate an output stream to debug internal operation of 1541 CPU
process(clock)
begin
if rising_edge(clock) then
debug_valid <= '0';
if cpu_clk_en = '1' then
debug_data <= '0' & atn_i & data_i & clk_i & sync & so_n & cpu_irqn & not cpu_write & cpu_rdata & cpu_addr(15 downto 0);
debug_valid <= '1';
if cpu_write = '1' then
debug_data(23 downto 16) <= cpu_wdata;
end if;
end if;
end if;
end process;
via1: entity work.via6522
port map (
clock => clock,
falling => cpu_clk_en,
rising => cpu_rising,
reset => reset,
addr => cpu_addr(3 downto 0),
wen => via1_wen,
ren => via1_ren,
data_in => cpu_wdata,
data_out => via1_data,
-- pio --
port_a_o => via1_port_a_o,
port_a_t => via1_port_a_t,
port_a_i => via1_port_a_i,
port_b_o => via1_port_b_o,
port_b_t => via1_port_b_t,
port_b_i => via1_port_b_i,
-- handshake pins
ca1_i => via1_ca1,
ca2_o => via1_ca2_o,
ca2_i => via1_ca2_i,
ca2_t => via1_ca2_t,
cb1_o => via1_cb1_o,
cb1_i => via1_cb1_i,
cb1_t => via1_cb1_t,
cb2_o => via1_cb2_o,
cb2_i => via1_cb2_i,
cb2_t => via1_cb2_t,
irq => via1_irq );
via2: entity work.via6522
port map (
clock => clock,
falling => cpu_clk_en,
rising => cpu_rising,
reset => reset,
addr => cpu_addr(3 downto 0),
wen => via2_wen,
ren => via2_ren,
data_in => cpu_wdata,
data_out => via2_data,
-- pio --
port_a_o => drv_wdata,
port_a_t => open,
port_a_i => drv_rdata,
port_b_o => via2_port_b_o,
port_b_t => via2_port_b_t,
port_b_i => via2_port_b_i,
-- handshake pins
ca1_i => so_n,
ca2_o => via2_ca2_o,
ca2_i => via2_ca2_i,
ca2_t => via2_ca2_t,
cb1_o => via2_cb1_o,
cb1_i => via2_cb1_i,
cb1_t => via2_cb1_t,
cb2_o => via2_cb2_o,
cb2_i => via2_cb2_i,
cb2_t => via2_cb2_t,
irq => via2_irq );
cpu_irqn <= not(via1_irq or via2_irq);
cpu_clk_en <= falling;
cpu_rising <= rising;
mem_busy <= '0' when mem_state = idle else '1';
bank_is_ram_i <= bank_is_ram & '0';
-- Fetch ROM byte
process(clock)
begin
if rising_edge(clock) then
mem_addr(25 downto 16) <= g_ram_base(25 downto 16);
case mem_state is
when idle =>
if cpu_clk_en = '1' then
mem_state <= newcycle;
end if;
when newcycle => -- we have a new address now
mem_addr(15 downto 0) <= unsigned(cpu_addr(15 downto 0));
io_select <= '0'; -- not active
-- Start by checking whether it is an extended RAM block
if bank_is_ram_i(to_integer(unsigned(cpu_addr(15 downto 13))))='1' then
mem_request <= '1';
mem_state <= extcycle;
elsif cpu_addr(15) = '1' then -- ROM Area, which is not overridden as RAM
if cpu_write = '0' then
mem_request <= '1';
mem_state <= extcycle;
else -- writing to rom -> ignore
mem_state <= idle;
end if;
-- It's not extended RAM, not ROM, so it must be internal RAM or I/O.
elsif cpu_addr(12 downto 11) = "00" then -- Internal RAM
mem_addr(14 downto 13) <= "00"; -- force mirroring for 2000-27FF, 4000-47FF and 6000-67FF.
mem_request <= '1';
mem_state <= extcycle;
else
io_select <= '1';
mem_state <= idle;
end if;
when extcycle =>
if mem_rack='1' then
mem_request <= '0';
if cpu_write='1' then
mem_state <= idle;
end if;
end if;
if mem_dack='1' and cpu_write='0' then -- only for reads
ext_rdata <= mem_resp.data;
mem_state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
io_select <= '0';
mem_request <= '0';
mem_state <= idle;
end if;
end if;
end process;
mem_rwn <= not cpu_write;
mem_wdata <= cpu_wdata;
-- address decoding and data muxing
with cpu_addr(12 downto 10) select io_rdata <=
via1_data when "110",
via2_data when "111",
X"FF" when others;
cpu_rdata <= io_rdata when io_select='1' else ext_rdata;
via1_wen <= '1' when cpu_write='1' and io_select='1' and cpu_addr(12 downto 10)="110" else '0';
via1_ren <= '1' when cpu_write='0' and io_select='1' and cpu_addr(12 downto 10)="110" else '0';
via2_wen <= '1' when cpu_write='1' and io_select='1' and cpu_addr(12 downto 10)="111" else '0';
via2_ren <= '1' when cpu_write='0' and io_select='1' and cpu_addr(12 downto 10)="111" else '0';
-- correctly attach the VIA pins to the outside world
via1_ca1 <= not atn_i;
via1_cb2_i <= via1_cb2_o or not via1_cb2_t;
-- Because Port B reads its own output when set to output, we do not need to consider the direction here
via1_port_b_i(7) <= not atn_i;
-- the following bits should read 0 when the jumper is closed (drive select = 0) or when driven low by the VIA itself
via1_port_b_i(6) <= drive_address(1); -- drive select
via1_port_b_i(5) <= drive_address(0); -- drive select;
via1_port_b_i(4) <= '1'; -- atn a - PUP
via1_port_b_i(3) <= '1'; -- clock out - PUP
via1_port_b_i(2) <= not (clk_i and (not (via1_port_b_o(3) or not via1_port_b_t(3))));
via1_port_b_i(1) <= '1'; -- data out - PUP
via1_port_b_i(0) <= not (data_i and (not (via1_port_b_o(1) or not via1_port_b_t(1))) and (not ((via1_port_b_o(4) or not via1_port_b_t(4)) xor (not atn_i))));
--auto_o <= not power or via1_port_b_i(4);
data_o <= not power or ((not (via1_port_b_o(1) or not via1_port_b_t(1))) and (not ((via1_port_b_o(4) or not via1_port_b_t(4)) xor (not atn_i))));
clk_o <= not power or (not (via1_port_b_o(3) or not via1_port_b_t(3)));
atn_o <= '1';
-- Do the same for VIA 2. Pin levels instead of output register.
via2_port_b_i(7) <= sync;
via2_port_b_i(6) <= '1'; --Density
via2_port_b_i(5) <= '1'; --Density
via2_port_b_i(4) <= write_prot_n;
via2_port_b_i(3) <= '1'; -- LED
via2_port_b_i(2) <= '1'; -- Motor
via2_port_b_i(1) <= '1'; -- Step
via2_port_b_i(0) <= '1'; -- Step
via2_cb1_i <= via2_cb1_o or not via2_cb1_t;
via2_cb2_i <= via2_cb2_o or not via2_cb2_t;
via2_ca2_i <= via2_ca2_o or not via2_ca2_t;
act_led <= not (via2_port_b_o(3) or not via2_port_b_t(3)) or not power;
mode <= via2_cb2_i;
step(0) <= via2_port_b_o(0) or not via2_port_b_t(0);
step(1) <= via2_port_b_o(1) or not via2_port_b_t(1);
motor_on <= (via2_port_b_o(2) or not via2_port_b_t(2)) and power;
rate_ctrl(0) <= via2_port_b_o(5) or not via2_port_b_t(5);
rate_ctrl(1) <= via2_port_b_o(6) or not via2_port_b_t(6);
soe <= via2_ca2_i;
so_n <= byte_ready or not soe;
end structural;
-- Original mapping:
-- 0000-07FF RAM
-- 0800-17FF open
-- 1800-1BFF VIA 1
-- 1C00-1FFF VIA 2
-- 2000-27FF RAM
-- 2800-37FF open
-- 3800-3BFF VIA 1
-- 3C00-3FFF VIA 2
-- 4000-47FF RAM
-- 4800-57FF open
-- 5800-5BFF VIA 1
-- 5C00-5FFF VIA 2
-- 6000-67FF RAM
-- 6800-77FF open
-- 7800-7BFF VIA 1
-- 7C00-7FFF VIA 2
-- 8000-BFFF ROM image (mirror)
-- C000-FFFF ROM image
| gpl-3.0 | c1d4cd2b2b94248167889c18e76b657e | 0.464305 | 3.221636 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/mm_startup_1541_tc.vhd | 1 | 10,493 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_bfm_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.c1541_pkg.all;
use work.tl_string_util_pkg.all;
use work.iec_bus_bfm_pkg.all;
entity mm_startup_1541_tc is
end;
architecture tc of mm_startup_1541_tc is
signal irq : std_logic;
constant c_wd177x_command : unsigned(15 downto 0) := X"1800";
constant c_wd177x_track : unsigned(15 downto 0) := X"1801";
constant c_wd177x_sector : unsigned(15 downto 0) := X"1802";
constant c_wd177x_datareg : unsigned(15 downto 0) := X"1803";
constant c_wd177x_status_clear : unsigned(15 downto 0) := X"1804";
constant c_wd177x_status_set : unsigned(15 downto 0) := X"1805";
constant c_wd177x_irq_ack : unsigned(15 downto 0) := X"1806";
constant c_wd177x_dma_mode : unsigned(15 downto 0) := X"1807";
constant c_wd177x_dma_addr : unsigned(15 downto 0) := X"1808"; -- DWORD
constant c_wd177x_dma_len : unsigned(15 downto 0) := X"180C"; -- WORD
constant c_param_ram : unsigned(15 downto 0) := X"1000";
begin
i_harness: entity work.harness_mm
port map (
io_irq => irq
);
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
variable value : unsigned(31 downto 0);
variable params : std_logic_vector(31 downto 0);
variable rotation_speed : natural;
variable bit_time : natural;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
bind_iec_bus_bfm("iec_bfm", bfm);
load_memory("../../../roms/1541.bin", dram, X"00008000");
load_memory("../../../roms/1541.bin", dram, X"0000C000");
-- load_memory("../../../roms/sounds.bin", dram, X"00000000");
load_memory("../../../disks/cpm.g71", dram, X"00100000" ); -- 1 MB offset
wait for 20 us;
io_write(io, c_drvreg_drivetype, X"00"); -- switch to 1541 mode
io_write(io, c_drvreg_power, X"01");
wait for 20 us;
io_write(io, c_drvreg_reset, X"00");
rotation_speed := (31250000 / 20);
for i in 0 to 34 loop
value := unsigned(read_memory_32(dram, std_logic_vector(to_unsigned(16#100000# + 12 + i*8, 32))));
value := value + X"00100000";
params(15 downto 0) := read_memory_16(dram, std_logic_vector(value));
value := value + 2;
bit_time := rotation_speed / to_integer(unsigned(params(15 downto 0)));
params(31 downto 16) := std_logic_vector(to_unsigned(bit_time, 16));
report "Track " & integer'image(i+1) & ": " & hstr(value) & " - " & hstr(params);
io_write_32(io, c_param_ram + 16*i, std_logic_vector(value) );
io_write_32(io, c_param_ram + 16*i + 4, params );
io_write_32(io, c_param_ram + 16*i + 12, params );
end loop;
wait for 1800 ms;
io_write(io, c_drvreg_inserted, X"01");
-- iec_drf(bfm);
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
iec_send_atn(bfm, X"5F", true); -- Drives, Untalk!
wait for 10 ms;
wait;
end process;
-- Type Command 7 6 5 4 3 2 1 0
-- -------------------------------------------------------
-- I Restore 0 0 0 0 h v r1 r0
-- I Seek 0 0 0 1 h v r1 r0
-- I Step 0 0 1 u h v r1 r0
-- I Step in 0 1 0 u h v r1 r0
-- I Step out 0 1 1 u h v r1 r0
-- II Read sector 1 0 0 m h/s e 0/c 0
-- II Write sector 1 0 1 m h/s e p/c a
-- III Read address 1 1 0 0 h/0 e 0 0
-- III Read track 1 1 1 0 h/0 e 0 0
-- III Write track 1 1 1 1 h/0 e p/0 0
-- IV Force interrupt 1 1 0 1 i3 i2 i1 i0
process
variable io : p_io_bus_bfm_object;
variable dram : h_mem_object;
variable cmd : std_logic_vector(7 downto 0);
variable byte : std_logic_vector(7 downto 0);
variable track : natural := 0;
variable sector : natural := 0;
variable dir : std_logic := '1';
variable side : std_logic := '0';
procedure do_step(update : std_logic) is
begin
if dir = '0' then
if track < 80 then
track := track + 1;
end if;
else
if track > 0 then
track := track - 1;
end if;
end if;
if update = '1' then
io_read(io, c_wd177x_track, byte);
if dir = '0' then
byte := std_logic_vector(unsigned(byte) + 1);
else
byte := std_logic_vector(unsigned(byte) - 1);
end if;
io_write(io, c_wd177x_track, byte);
end if;
end procedure;
begin
wait for 1 ns;
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("dram", dram);
while true loop
wait until irq = '1';
io_read(io, c_wd177x_command, cmd);
report "Command: " & hstr(cmd);
wait for 50 us;
if cmd(7 downto 4) = "0000" then
report "WD1770 Command: Restore";
io_write(io, c_wd177x_track, X"00"); -- set track to zero
track := 0;
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 4) = "0001" then
io_read(io, c_wd177x_datareg, byte);
report "WD1770 Command: Seek: Track = " & integer'image(to_integer(unsigned(byte)));
io_write(io, c_wd177x_track, byte);
track := to_integer(unsigned(byte));
-- no data transfer
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "001" then
report "WD1770 Command: Step.";
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "010" then
report "WD1770 Command: Step In.";
dir := '1';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "011" then
report "WD1770 Command: Step Out.";
dir := '0';
do_step(cmd(4));
io_write(io, c_wd177x_status_clear, X"01");
elsif cmd(7 downto 5) = "100" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Read Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"0000C000" ); -- read a piece of the ROM for now
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"01"); -- read
-- data transfer, so we are not yet done
elsif cmd(7 downto 5) = "101" then
io_read(io, c_wd177x_sector, byte);
sector := to_integer(unsigned(byte));
io_read(io, c_drvreg_status, byte);
side := byte(1);
report "WD1770 Command: Write Sector " & integer'image(sector) & " (Track: " & integer'image(track) & ", Side: " & std_logic'image(side) & ")";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"00");
io_write(io, c_wd177x_dma_len+1, X"02"); -- 0x200 = sector size
io_write(io, c_wd177x_dma_mode, X"02"); -- write
-- data transfer, so we are not yet done
elsif cmd(7 downto 4) = "1100" then
report "WD1770 Command: Read Address.";
write_memory_8(dram, X"00020000", std_logic_vector(to_unsigned(track, 8)) );
write_memory_8(dram, X"00020001", X"00" ); -- side (!!)
write_memory_8(dram, X"00020002", std_logic_vector(to_unsigned(sector, 8)) );
write_memory_8(dram, X"00020003", X"02" ); -- sector length = 512
write_memory_8(dram, X"00020004", X"F9" ); -- CRC1
write_memory_8(dram, X"00020005", X"5E" ); -- CRC2
io_write_32(io, c_wd177x_dma_addr, X"00020000" );
io_write(io, c_wd177x_dma_len, X"06");
io_write(io, c_wd177x_dma_len+1, X"00"); -- transfer 6 bytes
io_write(io, c_wd177x_dma_mode, X"01"); -- read
elsif cmd(7 downto 4) = "1110" then
report "WD1770 Command: Read Track (not implemented).";
elsif cmd(7 downto 4) = "1111" then
report "WD1770 Command: Write Track.";
io_write_32(io, c_wd177x_dma_addr, X"00010000" ); -- just write somewhere safe
io_write(io, c_wd177x_dma_len, X"6A");
io_write(io, c_wd177x_dma_len+1, X"18"); -- 6250 bytes
io_write(io, c_wd177x_dma_mode, X"02"); -- write
elsif cmd(7 downto 4) = "1101" then
io_write(io, c_wd177x_dma_mode, X"00"); -- stop
io_write(io, c_wd177x_status_clear, X"01");
end if;
io_write(io, c_wd177x_irq_ack, X"00");
end loop;
end process;
end architecture;
| gpl-3.0 | 57aef66af44cd1ed648143c220f6e913 | 0.486324 | 3.381566 | false | false | false | false |
ringof/radiofist_audio | core.vhd | 1 | 2,421 | -- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See LICENCE.txt for details
--
-- core module of project; most functionality is under this module
-- in the hierarchy; only signal conversion and debounce is
-- handled seperately in io_pads - both are under the top module
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity core is
port (
din : in STD_LOGIC;
dout : out STD_LOGIC;
clkin : in STD_LOGIC;
reset : in STD_LOGIC;
test : inout STD_LOGIC_VECTOR (7 downto 0)
);
end core;
architecture RTL of core is
component clock is
port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_6mhz : out STD_LOGIC
);
end component clock;
component sigma_delta_adc is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
comp : out STD_LOGIC;
one_bit_adc : out STD_LOGIC;
one_bit_dac : out STD_LOGIC
);
end component sigma_delta_adc;
component sinc3_filter is
port (
reset : in STD_LOGIC;
one_bit_adc_in : in STD_LOGIC;
clk : in STD_LOGIC;
decimation_clk : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (24 downto 0)
);
end component sinc3_filter;
component fir_filter_wrapper is
port (
din : in STD_LOGIC_VECTOR(23 downto 0);
dout : out STD_LOGIC(9 downto 0);
reset : in STD_LOGIC;
clk : in STD_LOGIC
);
end component fir_filter_wrapper;
component sigma_delta_dac is
port (
din : in STD_LOGIC_VECTOR(9 downto 0);
dout : out STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC
);
end component sigma_delta_dac;
signal one_bit_adc_i : STD_LOGIC;
signal decimation_clock_i : STD_LOGIC;
signal sinc3_filter_output : STD_LOGIC_VECTOR(24 downto 0);
begin
adc_clock : clock
port map(
clk_in => clk_in,
reset => reset,
clk_6mhz => clk_6mhz
);
sigma_delta_adc1 : sigma_delta_adc
port map(
clk => ADC_CLK,
reset => RESET,
comp => comp_out,
one_bit_adcc => one_bit_adc_i,
one_bit_dac => ADC_SD_DAC_OUT
);
sinc3_filter1 : sinc3_filter
port map(
reset => RESET,
one_bit_adc_in => one_bit_adc_i,
clk => ADC_CLK,
decimation_clk => decimation_clock_i,
output => sinc3_filter_output
);
adc_fir_lowpass : fir_filter_wrapper
port map(
din => sinc3_filter_output,
dout => open,
reset => RESET,
clk => decimation_clock_i
);
sigma_delta_dac1 : sigma_delta_dac
port map(
din => open,
dout => open,
reset => RESET,
clk => clk
);
end RTL;
| mit | 20c529be5e450a0b1d2dae3c34f867e9 | 0.650558 | 2.802083 | false | false | false | false |
jresendiz27/electronica | arquitectura/sumadorNBits/acarreoAnticipado/SumadorAcarreoAnticipado.vhdl | 2 | 1,028 | library ieee;
use ieee.std_logic_1164.all;
entity Prueba is
generic (numeroBits : integer :=4); --cantidad de bits
Port(
a: in std_logic_vector (numeroBits-1 downto 0);
b: in std_logic_vector (numeroBits-1 downto 0);
op : in std_logic;
s: out std_logic_vector (numeroBits-1 downto 0);
Cout: out std_logic);
end Prueba;
--eb(i) = b(i) xor op;
--c(0) = op;
--p(i) = a(i) or eb(i);
--g(i) = a(i) and eb(i);
--s(i) = p(i) or c(i);
--c(i+1) = c(i) and p(i) or g(i);
architecture A_Prueba of Prueba is
begin
process(a,b,op)
variable eb: std_logic_vector (numeroBits-1 downto 0);
variable p: std_logic_vector (numeroBits-1 downto 0);
variable g: std_logic_vector (numeroBits-1 downto 0);
variable c: std_logic_vector (numeroBits downto 0);
begin
C(0) := op;
for i in 0 to (numeroBits -1) loop
eb(i) := b(i) xor op;
p(i) := a(i) xor eb(i);
g(i) := a(i) and eb(i);
s(i) <= p(i) xor c(i);
c(i+1) := (c(i) and p(i)) or g(i);
end loop;
cout <= c(numeroBits);
--
end process;
end A_Prueba; | gpl-3.0 | 41fbdc21fa470cd84cdc9b2aa7323ca7 | 0.607004 | 2.325792 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/uart_lite/vhdl_source/rx.vhd | 1 | 2,850 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Serial Receiver: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rx is
generic (clks_per_bit : integer := 434); -- 115k2 @ 50 MHz
port (
clk : in std_logic;
reset : in std_logic;
tick : in std_logic;
rxd : in std_logic;
rxchar : out std_logic_vector(7 downto 0);
rx_ack : out std_logic );
end rx;
architecture gideon of rx is
signal bitcnt : integer range 0 to 8;
signal bitvec : std_logic_vector(8 downto 0);
signal timer : integer range 0 to clks_per_bit;
type state_t is (Idle, StartBit, Receiving);
signal state : state_t;
signal rxd_c : std_logic;
begin
process(clk, reset)
begin
if clk'event and clk='1' then
rxd_c <= rxd;
rx_ack <= '0';
if tick = '1' then
case state is
when Idle =>
if rxd_c = '0' then
timer <= (clks_per_bit / 2) - 1;
state <= startbit;
end if;
when StartBit =>
if rxd_c = '1' then
state <= Idle;
elsif timer = 0 then
timer <= clks_per_bit - 1;
state <= receiving;
bitcnt <= 8;
else
timer <= timer - 1;
end if;
when Receiving =>
if timer=0 then
timer <= clks_per_bit - 1;
bitvec <= rxd_c & bitvec(8 downto 1);
if bitcnt = 0 then
state <= Idle;
rx_ack <= '1';
else
bitcnt <= bitcnt - 1;
end if;
else
timer <= timer - 1;
end if;
end case;
end if;
end if;
if reset='1' then
state <= Idle;
bitcnt <= 0;
timer <= 0;
bitvec <= (others => '0');
end if;
end process;
rxchar <= bitvec(7 downto 0);
end gideon;
| gpl-3.0 | fcc66b49b020b65521aa95119eb94f06 | 0.348421 | 4.956522 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/c2n_playback/vhdl_source/c2n_playback_io.vhd | 1 | 8,706 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity c2n_playback_io is
generic (
g_clock_freq : natural := 50_000_000 );
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
c64_stopped : in std_logic;
generated_tick : out std_logic;
c2n_motor_in : in std_logic;
c2n_motor_out : out std_logic := '0'; -- not yet used
c2n_sense_in : in std_logic; -- not used
c2n_sense_out : out std_logic;
c2n_out_en_w : out std_logic;
c2n_out_en_r : out std_logic;
c2n_out_r : out std_logic;
c2n_out_w : out std_logic );
end c2n_playback_io;
architecture gideon of c2n_playback_io is
signal enabled : std_logic;
signal counter : unsigned(23 downto 0);
signal counter2 : unsigned(11 downto 0);
signal error : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
signal write_pulse : std_logic;
signal stream_en : std_logic;
type t_state is (idle, multi1, multi2, multi3, count_down);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
signal mode : std_logic;
signal sel : std_logic_vector(1 downto 0);
signal motor_en : std_logic;
signal speed_sel : std_logic;
signal tick_out : std_logic;
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
attribute register_duplication of motor_en : signal is "no";
begin
process(clock)
begin
if rising_edge(clock) then
-- c2n pin out and sync
stream_en <= enabled; --
motor_en <= c2n_motor_in;
if fifo_empty='1' and stream_en='1' then
error <= '1';
end if;
-- bus handling
resp <= c_io_resp_init;
fifo_flush <= '0';
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(3);
c2n_sense_out <= req.data(4);
speed_sel <= req.data(5);
sel <= req.data(7 downto 6);
end if;
elsif req.read='1' then
resp.ack <= '1';
resp.data <= status;
end if;
case state is
when idle =>
if stream_en='1' and fifo_empty='0' then
write_pulse <= '1';
if fifo_dout=X"00" then
if mode='1' then
state <= multi1;
else
counter <= to_unsigned(256*8, counter'length);
counter2 <= to_unsigned(256*4, counter2'length);
state <= count_down;
write_pulse <= '0'; -- not really a pulse
end if;
else
counter <= unsigned("0000000000000" & fifo_dout & "000");
counter2 <= unsigned("00" & fifo_dout & "00"); -- 12 bits
state <= count_down;
end if;
else
write_pulse <= '0';
end if;
when multi1 =>
if enabled = '0' then
state <= idle;
elsif stream_en='1' and fifo_empty='0' then
counter(7 downto 0) <= unsigned(fifo_dout);
counter2(6 downto 0) <= unsigned(fifo_dout(7 downto 1));
state <= multi2;
end if;
when multi2 =>
if enabled = '0' then
state <= idle;
elsif stream_en='1' and fifo_empty='0' then
counter(15 downto 8) <= unsigned(fifo_dout);
counter2(11 downto 7) <= unsigned(fifo_dout(4 downto 0));
if fifo_dout(7 downto 5) /= "000" then
counter2 <= (others => '1');
end if;
state <= multi3;
end if;
when multi3 =>
if enabled = '0' then
state <= idle;
elsif stream_en='1' and fifo_empty='0' then
counter(23 downto 16) <= unsigned(fifo_dout);
if fifo_dout /= X"00" then
counter2 <= (others => '1');
end if;
state <= count_down;
end if;
when count_down =>
if enabled = '0' then
state <= idle;
elsif tick_out='1' and stream_en='1' and c64_stopped='0' then
if (counter2 = 1) or (counter2 = 0) then
write_pulse <= '0';
else
counter2 <= counter2 - 1;
end if;
if (counter = 1) or (counter = 0) then
state <= idle;
else
counter <= counter - 1;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
enabled <= '0';
counter <= (others => '0');
error <= '0';
mode <= '0';
sel <= "00";
c2n_sense_out <= '0';
write_pulse <= '0';
end if;
end if;
end process;
fifo_write <= req.write and req.address(11); -- 0x800-0xFFF (2K)
fifo_read <= '0' when state = count_down else (stream_en and not fifo_empty);
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 1536,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => req.data,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= fifo_empty;
-- mode 0: no output
-- mode 1: negative pulse on read
-- mode 2: positive pulse on write
-- mode 3: no output
with sel select c2n_out_r <=
not write_pulse when "01", -- Load from tap
'1' when others;
c2n_out_en_r <= stream_en when (sel = "01") else '0';
c2n_out_en_w <= stream_en when (sel = "10") else '0';
with sel select c2n_out_w <=
write_pulse when "10", -- Write to Tape
'1' when others;
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when count_down,
"11" when others;
i_tape_speed: entity work.tape_speed_control
generic map (
g_clock_freq => g_clock_freq )
port map (
clock => clock,
reset => reset,
speed_sel => speed_sel,
motor_en => motor_en,
tick_out => tick_out
);
generated_tick <= tick_out;
end gideon;
| gpl-3.0 | b4736cbdea522394dad33159ce129bc6 | 0.426258 | 4.128023 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_v5.vhd | 1 | 16,254 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_pkg.all;
use work.cart_slot_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.command_if_pkg.all;
entity harness_v5 is
end harness_v5;
architecture tb of harness_v5 is
constant c_uart_divisor : natural := 434;
signal PHI2 : std_logic := '0';
signal RSTn : std_logic := 'H';
signal DOTCLK : std_logic := '1';
signal BUFFER_ENn : std_logic := '1';
signal BA : std_logic := '0';
signal DMAn : std_logic := '1';
signal EXROMn : std_logic;
signal GAMEn : std_logic;
signal ROMHn : std_logic := '1';
signal ROMLn : std_logic := '1';
signal IO1n : std_logic := '1';
signal IO2n : std_logic := '1';
signal IRQn : std_logic := '1';
signal NMIn : std_logic := '1';
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_DQM : std_logic;
signal LB_ADDR : std_logic_vector(14 downto 0);
signal LB_DATA : std_logic_vector(7 downto 0) := X"00";
signal logic_SDRAM_CSn : std_logic;
signal logic_SDRAM_RASn : std_logic;
signal logic_SDRAM_CASn : std_logic;
signal logic_SDRAM_WEn : std_logic;
signal logic_SDRAM_CKE : std_logic;
signal logic_SDRAM_CLK : std_logic;
signal logic_SDRAM_DQM : std_logic;
signal logic_LB_ADDR : std_logic_vector(14 downto 0);
signal PWM_OUT : std_logic_vector(1 downto 0);
signal IEC_ATN : std_logic := '1';
signal IEC_DATA : std_logic := '1';
signal IEC_CLOCK : std_logic := '1';
signal IEC_RESET : std_logic := '1';
signal IEC_SRQ_IN : std_logic := '1';
signal DISK_ACTn : std_logic; -- activity LED
signal CART_LEDn : std_logic;
signal SDACT_LEDn : std_logic;
signal MOTOR_LEDn : std_logic;
signal UART_TXD : std_logic;
signal UART_RXD : std_logic := '1';
signal SD_SSn : std_logic;
signal SD_CLK : std_logic;
signal SD_MOSI : std_logic;
signal SD_MISO : std_logic := '1';
signal SD_WP : std_logic := '1';
signal SD_CARDDETn : std_logic := '1';
signal BUTTON : std_logic_vector(2 downto 0) := "000";
signal SLOT_ADDR : std_logic_vector(15 downto 0);
signal SLOT_DATA : std_logic_vector(7 downto 0);
signal RWn : std_logic := '1';
signal CAS_MOTOR : std_logic := '1';
signal CAS_SENSE : std_logic := '0';
signal CAS_READ : std_logic := '0';
signal CAS_WRITE : std_logic := '0';
signal RTC_CS : std_logic;
signal RTC_SCK : std_logic;
signal RTC_MOSI : std_logic;
signal RTC_MISO : std_logic := '1';
signal FLASH_CSn : std_logic;
signal FLASH_SCK : std_logic;
signal FLASH_MOSI : std_logic;
signal FLASH_MISO : std_logic := '1';
signal ULPI_CLOCK : std_logic := '0';
signal ULPI_RESET : std_logic := '0';
signal ULPI_NXT : std_logic := '0';
signal ULPI_STP : std_logic;
signal ULPI_DIR : std_logic := '0';
signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H');
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic := '0';
signal sys_shifted : std_logic := '0';
signal rx_char : std_logic_vector(7 downto 0);
signal rx_char_d : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal tx_char : std_logic_vector(7 downto 0) := X"00";
signal tx_done : std_logic;
signal do_tx : std_logic := '0';
shared variable dram : h_mem_object;
shared variable ram : h_mem_object;
-- shared variable rom : h_mem_object;
-- shared variable bram : h_mem_object;
-- memory controller interconnect
signal memctrl_inhibit : std_logic := '0';
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal mem_req_cached : t_mem_burst_req;
signal mem_resp_cached : t_mem_burst_resp;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
-- cache monitoring
signal hit_count : unsigned(31 downto 0);
signal miss_count : unsigned(31 downto 0);
signal hit_ratio : real := 0.0;
begin
mut: entity work.ultimate_logic
generic map (
g_simulation => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_cartridge => true,
g_command_intf => true,
g_stereo_sid => true,
g_ram_expansion => true,
g_extended_reu => true,
g_hardware_iec => true,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
sys_clock => sys_clock,
sys_reset => sys_reset,
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- io bus for simulation
sim_io_req => io_req,
sim_io_resp => io_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_CLOCK => ULPI_CLOCK,
ULPI_RESET => ULPI_RESET,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Buttons
BUTTON => BUTTON );
i_cache: entity work.dm_cache
port map (
clock => sys_clock,
reset => sys_reset,
client_req => mem_req,
client_resp => mem_resp,
mem_req => mem_req_cached,
mem_resp => mem_resp_cached,
hit_count => hit_count,
miss_count => miss_count );
hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1);
i_memctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => '0', --memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req_cached,
resp => mem_resp_cached,
SDRAM_CSn => logic_SDRAM_CSn,
SDRAM_RASn => logic_SDRAM_RASn,
SDRAM_CASn => logic_SDRAM_CASn,
SDRAM_WEn => logic_SDRAM_WEn,
SDRAM_CKE => logic_SDRAM_CKE,
SDRAM_CLK => logic_SDRAM_CLK,
MEM_A => logic_LB_ADDR,
MEM_D => LB_DATA );
-- clock to out.. for data it is inside of the memory controller, because it's bidirectional
SDRAM_CSn <= transport logic_SDRAM_CSn after 4.9 ns;
SDRAM_RASn <= transport logic_SDRAM_RASn after 4.9 ns;
SDRAM_CASn <= transport logic_SDRAM_CASn after 4.9 ns;
SDRAM_WEn <= transport logic_SDRAM_WEn after 4.9 ns;
SDRAM_CKE <= transport logic_SDRAM_CKE after 4.9 ns;
SDRAM_CLK <= transport logic_SDRAM_CLK after 4.9 ns;
LB_ADDR <= transport logic_LB_ADDR after 4.9 ns;
sys_clock <= not sys_clock after 10 ns; -- 50 MHz
sys_reset <= '1', '0' after 100 ns;
sys_shifted <= transport sys_clock after 15 ns; -- 270 degrees
ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz
ULPI_RESET <= '1', '0' after 100 ns;
PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz
RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us;
i_ulpi_phy: entity work.ulpi_phy_bfm
generic map (
g_rx_interval => 100000 )
port map (
clock => ULPI_CLOCK,
reset => ULPI_RESET,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp );
process
begin
bind_mem_model("intram", ram);
bind_mem_model("dram", dram);
load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000");
-- 1st boot will try to load the 2nd bootloader and application from flash. In simulation this is a cumbersome
-- process. It would work with a good model of the serial spi flash, but since it is not included in the public
-- archive, you need to create a special boot image that just jumps to 0x20000 and load the application here to dram:
load_memory("../../software/ultimate/result/ultimate.bin", dram, X"00020000");
wait;
end process;
SLOT_DATA <= (others => 'H');
ROMHn <= '1';
ROMLn <= not PHI2 after 50 ns;
IO1n <= '1';
IO2n <= '1';
process
begin
SLOT_ADDR <= X"D400";
RWn <= '1';
while true loop
wait until PHI2 = '0';
--SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1);
SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1);
RWn <= '1';
wait until PHI2 = '0';
RWn <= '0';
end loop;
end process;
process
begin
BA <= '1';
for i in 0 to 100 loop
wait until PHI2='0';
end loop;
BA <= '0';
for i in 0 to 10 loop
wait until PHI2='0';
end loop;
end process;
dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => LB_ADDR(12 downto 0),
BA => LB_ADDR(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => LB_DATA);
i_rx: entity work.rx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
rxd => UART_TXD,
rxchar => rx_char,
rx_ack => rx_ack );
i_tx: entity work.tx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
dotx => do_tx,
txchar => tx_char,
done => tx_done,
txd => UART_RXD );
process(sys_clock)
begin
if rising_edge(sys_clock) then
if rx_ack='1' then
rx_char_d <= rx_char;
end if;
end if;
end process;
-- procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
-- procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
-- procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
-- procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
-- constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
-- constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
-- constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
-- constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
-- constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4";
-- constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
-- constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
-- constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
-- constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
-- constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
-- constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
process
variable io : p_io_bus_bfm_object;
begin
wait until sys_reset='0';
wait until sys_clock='1';
bind_io_bus_bfm("io_bfm", io);
io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset
io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro
io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset
io_write(io, X"44000" + c_cif_io_slot_base, X"7E");
io_write(io, X"44000" + c_cif_io_slot_enable, X"01");
wait for 6 us;
wait until sys_clock='1';
io_write(io, X"42002", X"42");
wait;
end process;
process
procedure send_char(i: std_logic_vector(7 downto 0)) is
begin
if tx_done /= '1' then
wait until tx_done = '1';
end if;
wait until sys_clock='1';
tx_char <= i;
do_tx <= '1';
wait until tx_done = '0';
wait until sys_clock='1';
do_tx <= '0';
end procedure;
procedure send_string(i : string) is
variable b : std_logic_vector(7 downto 0);
begin
for n in i'range loop
b := std_logic_vector(to_unsigned(character'pos(i(n)), 8));
send_char(b);
end loop;
send_char(X"0d");
send_char(X"0a");
end procedure;
begin
wait for 2 ms;
--send_string("wd 4005000 12345678");
send_string("run");
-- send_string("m 100000");
-- send_string("w 400000F 4");
wait;
end process;
-- check timing data
process(PHI2)
begin
if falling_edge(PHI2) then
assert SLOT_DATA'last_event >= 189 ns
report "Timing error on C64 bus."
severity error;
end if;
end process;
end tb;
| gpl-3.0 | 3bab2287c25e3fde9a356c0a6adf0901 | 0.51009 | 3.357571 | false | false | false | false |
chiggs/nvc | test/bounds/issue54.vhd | 4 | 442 | entity issue54 is
begin
end entity issue54;
architecture a of issue54 is
begin
p : process
variable v : bit_vector(7 downto 0) := (others => '0');
begin
v(3 downto 0) := (7 downto 4 => '1'); -- OK
v(7 downto 4) := (3 downto 0 => '1'); -- OK
v(7 downto 4) := (3 downto 0 => '1', others => '0'); -- Error
assert (v = (7 downto 0 => '1'));
wait;
end process p;
end architecture a;
| gpl-3.0 | 24b4fd186ae22428bead3cd85a9359de | 0.515837 | 3.25 | false | false | false | false |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/transitest_arc.vhdl | 15 | 1,201 | -- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- Architecture statement part
BJT1 : ENTITY BJT_transistor_simple(simple_arc)
GENERIC MAP (
NEL => 5.0)
PORT MAP ( Base => unnamed_net2,
Collector => unnamed_net5,
Emitter => unnamed_net1);
VS_base : ENTITY VOLTAGE_SOURCE(sinusodial)
GENERIC MAP (
amplitude => 1.0,
k => 150.0)
PORT MAP ( LT => unnamed_net3,
RT => unnamed_net1);
VS_collector : ENTITY VOLTAGE_SOURCE(sinusodial)
GENERIC MAP (
amplitude => 2.0,
offset => 10.2,
k => 100.0)
PORT MAP ( LT => unnamed_net4,
RT => unnamed_net1);
RES_collecter : ENTITY RESISTOR
GENERIC MAP (
r => 60.0)
PORT MAP ( RT => unnamed_net4,
LT => unnamed_net5);
RES_base : ENTITY RESISTOR
GENERIC MAP (
r => 10000.0)
PORT MAP ( RT => unnamed_net2,
LT => unnamed_net3);
GND : ENTITY GROUND_NODE
PORT MAP ( T1 => unnamed_net1);
END ARCHITECTURE transistor_test;
| gpl-2.0 | 35c7a3bddbeb8a91d8ea4347541dc719 | 0.655287 | 3.111399 | false | false | false | false |
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