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`protect end_protected
| gpl-3.0 | 24fc196e05fd62882b24e6912fd749ee | 0.954452 | 1.813999 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_cast_GNKXX25S2S.vhd | 12 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNKXX25S2S is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(7 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNKXX25S2S is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 8,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; | mit | b8f6f46697a678a8de8e2edab9448c4a | 0.648803 | 3.045139 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_prim.vhd | 9 | 34,989 | `protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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| gpl-3.0 | bea7ba70dc0ed6b0c3349446bfa5c51b | 0.946097 | 1.835633 | false | false | false | false |
ymei/TMSPlane | Firmware/test_bench/channel_avg_tb.vhd | 1 | 2,988 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/29/2014 07:39:31 PM
-- Design Name:
-- Module Name: channel_avg_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY channel_avg_tb IS
END channel_avg_tb;
ARCHITECTURE Behavioral OF channel_avg_tb IS
COMPONENT channel_avg IS
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
CONFIG : IN std_logic_vector(7 DOWNTO 0);
TRIG : IN std_logic;
INDATA_Q : IN std_logic_vector(256-1 DOWNTO 0);
OUTVALID : OUT std_logic;
OUTDATA_Q : OUT std_logic_vector(256-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL RESET : std_logic := '0';
SIGNAL CLK : std_logic := '0';
--
SIGNAL CONFIG : std_logic_vector(7 DOWNTO 0) := x"94";
SIGNAL TRIG : std_logic := '0';
SIGNAL INDATA_Q : std_logic_vector(256-1 DOWNTO 0);
SIGNAL OUTVALID : std_logic;
SIGNAL OUTDATA_Q : std_logic_vector(256-1 DOWNTO 0);
--
SIGNAL ch_val : signed(13 DOWNTO 0) := (OTHERS => '0');
-- Clock period definitions
CONSTANT CLK_period : time := 10 ns;
CONSTANT CLKOUT_period : time := 5 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : channel_avg
PORT MAP (
RESET => RESET,
CLK => CLK,
CONFIG => CONFIG,
TRIG => TRIG,
INDATA_Q => INDATA_Q,
OUTVALID => OUTVALID,
OUTDATA_Q => OUTDATA_Q
);
-- Clock process definitions
CLK_process : PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_period/2;
CLK <= '1';
WAIT FOR CLK_period/2;
END PROCESS;
PROCESS (CLK, RESET) IS
VARIABLE i : integer;
BEGIN
IF RESET = '1' THEN
ch_val <= to_signed(-128, ch_val'length);
ELSIF rising_edge(CLK) THEN
ch_val <= ch_val + 1;
END IF;
FOR i IN 0 TO 15 LOOP
INDATA_Q(i*16+15 DOWNTO i*16+2) <= std_logic_vector(ch_val);
INDATA_Q(i*16+1 DOWNTO i*16) <= "00";
END LOOP;
END PROCESS;
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- hold reset state
RESET <= '0';
WAIT FOR 15 ns;
RESET <= '1';
WAIT FOR CLK_period*3;
RESET <= '0';
WAIT FOR CLK_period*5.3;
TRIG <= '1';
WAIT FOR CLK_period*5.7;
TRIG <= '0';
--
--
WAIT;
END PROCESS;
END Behavioral;
| bsd-3-clause | 5f0dbe34884e71b12216726df48f576e | 0.547189 | 3.544484 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_bin_cntr.vhd | 9 | 21,696 | `protect begin_protected
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| gpl-3.0 | ebce8fdd333ac08866b8cebb5fa740f7 | 0.938007 | 1.835222 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/global_logic.vhd | 4 | 8,982 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/16 00:32:43 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: global_logic_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.5 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- GLOBAL_LOGIC
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: The GLOBAL_LOGIC module handles channel bonding, channel
-- verification, channel error manangement and idle generation.
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity GLOBAL_LOGIC is
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
LANE_UP : in std_logic;
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic
);
end GLOBAL_LOGIC;
architecture MAPPED of GLOBAL_LOGIC is
-- External Register Declarations --
signal EN_CHAN_SYNC_Buffer : std_logic;
signal GEN_A_Buffer : std_logic;
signal GEN_K_Buffer : std_logic_vector(0 to 1);
signal GEN_R_Buffer : std_logic_vector(0 to 1);
signal GEN_V_Buffer : std_logic_vector(0 to 1);
signal RESET_LANES_Buffer : std_logic;
signal CHANNEL_UP_Buffer : std_logic;
signal START_RX_Buffer : std_logic;
signal CHANNEL_SOFT_ERROR_Buffer : std_logic;
signal CHANNEL_HARD_ERROR_Buffer : std_logic;
-- Wire Declarations --
signal gen_ver_i : std_logic;
signal reset_channel_i : std_logic;
signal did_ver_i : std_logic;
-- Component Declarations --
component CHANNEL_INIT_SM
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
-- Idle and Verification Sequence Generator Interface
DID_VER : in std_logic;
GEN_VER : out std_logic;
-- Channel Init State Machine Interface
RESET_CHANNEL : in std_logic
);
end component;
component IDLE_AND_VER_GEN
port (
-- Channel Init SM Interface
GEN_VER : in std_logic;
DID_VER : out std_logic;
-- Aurora Lane Interface
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
-- System Interface
RESET : in std_logic;
USER_CLK : in std_logic
);
end component;
component CHANNEL_ERROR_DETECT
port (
-- Aurora Lane Interface
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
LANE_UP : in std_logic;
-- System Interface
USER_CLK : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic;
-- Channel Init SM Interface
RESET_CHANNEL : out std_logic
);
end component;
begin
EN_CHAN_SYNC <= EN_CHAN_SYNC_Buffer;
GEN_A <= GEN_A_Buffer;
GEN_K <= GEN_K_Buffer;
GEN_R <= GEN_R_Buffer;
GEN_V <= GEN_V_Buffer;
RESET_LANES <= RESET_LANES_Buffer;
CHANNEL_UP <= CHANNEL_UP_Buffer;
START_RX <= START_RX_Buffer;
CHANNEL_SOFT_ERROR <= CHANNEL_SOFT_ERROR_Buffer;
CHANNEL_HARD_ERROR <= CHANNEL_HARD_ERROR_Buffer;
-- Main Body of Code --
-- State Machine for channel bonding and verification.
channel_init_sm_i : CHANNEL_INIT_SM
generic map (
EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
)
port map (
-- MGT Interface
CH_BOND_DONE => CH_BOND_DONE,
EN_CHAN_SYNC => EN_CHAN_SYNC_Buffer,
-- Aurora Lane Interface
CHANNEL_BOND_LOAD => CHANNEL_BOND_LOAD,
GOT_A => GOT_A,
GOT_V => GOT_V,
RESET_LANES => RESET_LANES_Buffer,
-- System Interface
USER_CLK => USER_CLK,
RESET => RESET,
START_RX => START_RX_Buffer,
CHANNEL_UP => CHANNEL_UP_Buffer,
-- Idle and Verification Sequence Generator Interface
DID_VER => did_ver_i,
GEN_VER => gen_ver_i,
-- Channel Error Management Module Interface
RESET_CHANNEL => reset_channel_i
);
-- Idle and verification sequence generator module.
idle_and_ver_gen_i : IDLE_AND_VER_GEN
port map (
-- Channel Init SM Interface
GEN_VER => gen_ver_i,
DID_VER => did_ver_i,
-- Aurora Lane Interface
GEN_A => GEN_A_Buffer,
GEN_K => GEN_K_Buffer,
GEN_R => GEN_R_Buffer,
GEN_V => GEN_V_Buffer,
-- System Interface
RESET => RESET,
USER_CLK => USER_CLK
);
-- Channel Error Management module.
channel_error_detect_i : CHANNEL_ERROR_DETECT
port map (
-- Aurora Lane Interface
SOFT_ERROR => SOFT_ERROR,
HARD_ERROR => HARD_ERROR,
LANE_UP => LANE_UP,
-- System Interface
USER_CLK => USER_CLK,
POWER_DOWN => POWER_DOWN,
CHANNEL_SOFT_ERROR => CHANNEL_SOFT_ERROR_Buffer,
CHANNEL_HARD_ERROR => CHANNEL_HARD_ERROR_Buffer,
-- Channel Init State Machine Interface
RESET_CHANNEL => reset_channel_i
);
end MAPPED;
| bsd-2-clause | 4fd07ff19265b7a8c498c3ecf172437e | 0.492318 | 4.362312 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/compare.vhd | 9 | 11,685 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 309471485251f5ea5744c356805f4d7f | 0.930595 | 1.895377 | false | false | false | false |
apoloval/avionica | vhdl/ic4021_tb.vhdl | 1 | 1,725 | library ieee;
use ieee.std_logic_1164.all;
entity ic4021_tb is
end ic4021_tb;
architecture behavior of ic4021_tb is
component ic4021
port (d : in std_logic_vector(7 downto 0);
pl : in std_logic;
ds : in std_logic;
cp : in std_logic;
q5 : out std_logic;
q6 : out std_logic;
q7 : out std_logic);
end component;
signal clock: std_logic := '0';
signal serial: std_logic := '0';
signal load: std_logic := '0';
signal d: std_logic_vector(0 to 7) := "00000000";
signal q5, q6, q7: std_logic;
for ic: ic4021 use entity work.ic4021;
begin
ic: ic4021 port map (d => d,
pl => load,
ds => serial,
cp => clock,
q5 => q5,
q6 => q6,
q7 => q7);
process
constant byte: std_logic_vector(7 downto 0) := "01001101";
begin
wait for 10 ns;
report "should load parallel data when PL is high";
d <= byte;
load <= '1'; wait for 10 ns; load <= '0'; wait for 10 ns;
assert q5 = '0';
assert q6 = '1';
assert q7 = '0';
report "should load parallel data ignoring CP";
d <= byte;
load <= '1';
clock <= '1'; wait for 10 ns; clock <= '0'; wait for 10 ns;
assert q5 = '0';
assert q6 = '1';
assert q7 = '0';
report "should shift data";
d <= byte;
load <= '1'; wait for 10 ns; load <= '0';
serial <= '1';
for i in byte'range loop
assert q7 = byte(i);
clock <= '1'; wait for 10 ns; clock <= '0'; wait for 10 ns;
end loop;
assert q7 = serial;
report "end of test";
wait;
end process;
end behavior;
| mpl-2.0 | b737941747f7a237a5123ca295ac8c3b | 0.510145 | 3.388998 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/bytefifoFPGA/simulation/bytefifoFPGA_pkg.vhd | 3 | 11,664 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifoFPGA_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE bytefifoFPGA_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT bytefifoFPGA_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT bytefifoFPGA_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT bytefifoFPGA_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT bytefifoFPGA_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT bytefifoFPGA_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT bytefifoFPGA_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
UNDERFLOW : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END bytefifoFPGA_pkg;
PACKAGE BODY bytefifoFPGA_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END bytefifoFPGA_pkg;
| bsd-2-clause | eeee0176e910c8d13bcb2b78ab08ab47 | 0.504715 | 4.004119 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | 1980940e9a8b36c22f76b5b390744cfb | 0.947014 | 1.83669 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_ecc_encoder.vhd | 9 | 20,723 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13600)
`protect data_block
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`protect end_protected
| gpl-3.0 | 50540d35f28b7b85ab9e75e498a9c076 | 0.941273 | 1.851425 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/input_blk.vhd | 9 | 28,136 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19088)
`protect data_block
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`protect end_protected
| gpl-3.0 | 900d2af518590a38b44e0a213b8751e3 | 0.944164 | 1.846437 | false | false | false | false |
ymei/TMSPlane | Firmware/src/i2c/i2c_master.vhd | 1 | 11,099 | --------------------------------------------------------------------------------
--! @file i2c_master
--! @brief As master, read/write up to 2/3 bytes on th i2c bus.
--! @author Dong Wang, 20161009
--! Yuan Mei, 20170817
--! Read/write is initiated by a pulse on START
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY i2c_master IS
GENERIC (
INPUT_CLK_FREQENCY : integer := 100_000_000;
-- BUS CLK freqency should be divided by multiples of 4 from input frequency
BUS_CLK_FREQUENCY : integer := 100_000
);
PORT (
CLK : IN std_logic; -- system clock 50Mhz
RESET : IN std_logic; -- active high reset
START : IN std_logic; -- rising edge triggers r/w; synchronous to CLK
MODE : IN std_logic_vector(1 DOWNTO 0); -- "00" : 1 bytes read or write, "01" : 2 bytes r/w, "10" : 3 bytes write only;
SL_RW : IN std_logic; -- '0' is write, '1' is read
SL_ADDR : IN std_logic_vector(6 DOWNTO 0); -- slave addr
REG_ADDR : IN std_logic_vector(7 DOWNTO 0); -- slave internal reg addr for read and write
WR_DATA0 : IN std_logic_vector(7 DOWNTO 0); -- first data byte to write
WR_DATA1 : IN std_logic_vector(7 DOWNTO 0); -- second data byte to write
RD_DATA0 : OUT std_logic_vector(7 DOWNTO 0); -- first data byte read
RD_DATA1 : OUT std_logic_vector(7 DOWNTO 0); -- second data byte read
BUSY : OUT std_logic; -- indicates transaction in progress
ACK_ERROR : OUT std_logic; -- i2c has unexpected ack
SDA_in : IN std_logic; -- serial data input from i2c bus
SDA_out : OUT std_logic; -- serial data output to i2c bus
SDA_t : OUT std_logic; -- serial data direction to/from i2c bus, '1' is read-in
SCL : OUT std_logic -- serial clock output to i2c bus
);
END i2c_master;
ARCHITECTURE arch OF i2c_master IS
COMPONENT i2c_master_core IS
GENERIC (
INPUT_CLK_FREQENCY : integer;
BUS_CLK_FREQUENCY : integer
);
PORT (
CLK : IN std_logic;
RESET : IN std_logic;
ENA : IN std_logic;
ADDR : IN std_logic_vector(6 DOWNTO 0);
RW : IN std_logic;
DATA_WR : IN std_logic_vector(7 DOWNTO 0);
BUSY : OUT std_logic;
DATA_RD : OUT std_logic_vector(7 DOWNTO 0);
ACK_ERROR : OUT std_logic;
SDA_in : IN std_logic;
SDA_out : OUT std_logic;
SDA_t : OUT std_logic;
SCL : OUT std_logic
);
END COMPONENT i2c_master_core;
SIGNAL sI2C_enable : std_logic;
SIGNAL sI2C_data_wr : std_logic_vector(7 DOWNTO 0);
SIGNAL sI2C_data_rd : std_logic_vector(7 DOWNTO 0);
SIGNAL sI2C_busy : std_logic;
SIGNAL sBusyCnt : std_logic_vector(2 DOWNTO 0);
SIGNAL sBusy_d1 : std_logic;
SIGNAL sBusy_d2 : std_logic;
SIGNAL rd_data0_buf : std_logic_vector(7 DOWNTO 0);
SIGNAL rd_data1_buf : std_logic_vector(7 DOWNTO 0);
TYPE machine_type IS (StWaitStart,
StWr1,
StWr2,
StWr3,
StRd1,
StRd2
); -- needed states
SIGNAL state : machine_type; -- state machine
BEGIN
i2c_master_core_inst : i2c_master_core
GENERIC MAP (
INPUT_CLK_FREQENCY => INPUT_CLK_FREQENCY,
BUS_CLK_FREQUENCY => BUS_CLK_FREQUENCY
)
PORT MAP (
CLK => CLK,
RESET => RESET,
ENA => sI2C_enable,
ADDR => SL_ADDR,
RW => SL_RW,
DATA_WR => sI2C_data_wr,
BUSY => sI2C_busy,
DATA_RD => sI2C_data_rd,
ACK_ERROR => ACK_ERROR,
SDA_in => SDA_in,
SDA_out => SDA_out,
SDA_t => SDA_t,
SCL => SCL
);
--busy counter
busy_d : PROCESS (CLK) IS
BEGIN
IF rising_edge(CLK) THEN
sBusy_d1 <= sI2C_busy;
sBusy_d2 <= sBusy_d1;
END IF;
END PROCESS busy_d;
busy_counter : PROCESS (CLK, RESET) IS
BEGIN
IF RESET = '1' THEN -- asynchronous reset (active high)
sBusyCnt <= "000";
ELSIF rising_edge(CLK) THEN
IF state = StWaitStart THEN
sBusyCnt <= "000";
ELSIF sBusy_d2 = '0' and sBusy_d1 = '1' THEN
sBusyCnt <= std_logic_vector(unsigned(sBusyCnt) + 1);
ELSE
sBusyCnt <= sBusyCnt;
END IF;
END IF;
END PROCESS busy_counter;
state_machine : PROCESS (CLK, RESET) IS
BEGIN
IF RESET = '1' THEN -- asynchronous reset (active high)
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
BUSY <= '0';
rd_data0_buf <= (OTHERS => '0');
rd_data1_buf <= (OTHERS => '0');
state <= StWaitStart;
ELSIF rising_edge(CLK) THEN -- rising clock edge
CASE state IS
-- //// Wait for signal to start I2C transaction
WHEN StWaitStart =>
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
BUSY <= '0';
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= rd_data1_buf;
IF START = '1' THEN
BUSY <= '1';
IF SL_RW = '0' THEN -- write
IF MODE = "00" THEN -- 1 byte write (no payload)
state <= StWr1;
ELSIF MODE = "01" THEN -- 2 bytes write (1 byte payload)
state <= StWr2;
ELSIF MODE = "10" THEN -- 3 bytes write (2 byte payload)
state <= StWr3;
ELSE
state <= StWaitStart;
END IF;
ELSE
IF MODE = "00" THEN -- 1 byte read
state <= StRd1;
ELSIF MODE = "01" THEN -- 2 bytes read
state <= StRd2;
ELSE
state <= StWaitStart;
END IF;
END IF;
ELSE
state <= StWaitStart;
END IF;
-- 1 byte write
WHEN StWr1 =>
BUSY <= '1';
CASE sBusyCnt IS
WHEN "000" =>
sI2C_enable <= '1';
sI2C_data_wr <= REG_ADDR;
state <= StWr1;
WHEN "001" =>
sI2C_enable <= '0';
sI2C_data_wr <= REG_ADDR;
IF sI2C_busy = '0' THEN
state <= StWaitStart;
ELSE
state <= StWr1;
END IF;
WHEN OTHERS =>
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
state <= StWaitStart;
END CASE;
-- 2 bytes write
WHEN StWr2 =>
BUSY <= '1';
CASE sBusyCnt IS
WHEN "000" =>
sI2C_enable <= '1';
sI2C_data_wr <= REG_ADDR;
state <= StWr2;
WHEN "001" =>
sI2C_enable <= '1';
sI2C_data_wr <= WR_DATA0;
state <= StWr2;
WHEN "010" =>
sI2C_enable <= '0';
sI2C_data_wr <= WR_DATA0;
IF sI2C_busy = '0' THEN
state <= StWaitStart;
ELSE
state <= StWr2;
END IF;
WHEN OTHERS =>
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
state <= StWaitStart;
END CASE;
-- 3 bytes write
WHEN StWr3 =>
BUSY <= '1';
CASE sBusyCnt IS
WHEN "000" =>
sI2C_enable <= '1';
sI2C_data_wr <= REG_ADDR;
state <= StWr3;
WHEN "001" =>
sI2C_enable <= '1';
sI2C_data_wr <= WR_DATA0;
state <= StWr3;
WHEN "010" =>
sI2C_enable <= '1';
sI2C_data_wr <= WR_DATA1;
state <= StWr3;
WHEN "011" =>
sI2C_enable <= '0';
sI2C_data_wr <= WR_DATA1;
IF sI2C_busy = '0' THEN
state <= StWaitStart;
ELSE
state <= StWr3;
END IF;
WHEN OTHERS =>
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
state <= StWaitStart;
END CASE;
-- 1 byte read
WHEN StRd1 =>
BUSY <= '1';
rd_data1_buf <= rd_data1_buf;
sI2C_data_wr <= (OTHERS => '0');
CASE sBusyCnt IS
WHEN "000" =>
sI2C_enable <= '1';
rd_data0_buf <= rd_data0_buf;
state <= StRd1;
WHEN "001" =>
sI2C_enable <= '0';
IF sI2C_busy = '0' THEN
state <= StWaitStart;
rd_data0_buf <= sI2C_data_rd;
ELSE
state <= StRd1;
rd_data0_buf <= rd_data0_buf;
END IF;
WHEN OTHERS =>
sI2C_enable <= '0';
rd_data0_buf <= rd_data0_buf;
state <= StWaitStart;
END CASE;
-- 2 bytes read
WHEN StRd2 =>
BUSY <= '1';
sI2C_data_wr <= (OTHERS => '0');
CASE sBusyCnt IS
WHEN "000" =>
sI2C_enable <= '1';
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= rd_data1_buf;
state <= StRd2;
WHEN "001" =>
sI2C_enable <= '1';
IF sI2C_busy = '0' THEN
state <= StRd2;
rd_data0_buf <= sI2C_data_rd;
rd_data1_buf <= rd_data1_buf;
ELSE
state <= StRd2;
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= rd_data1_buf;
END IF;
WHEN "010" =>
sI2C_enable <= '0';
IF sI2C_busy = '0' THEN
state <= StWaitStart;
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= sI2C_data_rd;
ELSE
state <= StRd2;
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= rd_data1_buf;
END IF;
WHEN OTHERS =>
sI2C_enable <= '0';
rd_data0_buf <= rd_data0_buf;
rd_data1_buf <= rd_data1_buf;
state <= StWaitStart;
END CASE;
-- //// shouldn't happen
WHEN OTHERS =>
sI2C_enable <= '0';
sI2C_data_wr <= (OTHERS => '0');
BUSY <= '0';
rd_data0_buf <= (OTHERS => '0');
rd_data1_buf <= (OTHERS => '0');
state <= StWaitStart;
END CASE;
END IF;
END PROCESS state_machine;
RD_DATA0 <= rd_data0_buf;
RD_DATA1 <= rd_data1_buf;
END arch;
| bsd-3-clause | 0435d2d4b683c4f0297c919915057a1a | 0.443373 | 3.657002 | false | false | false | false |
ymei/TMSPlane | Firmware/src/ten_gig_eth/TE07412C1/fifo/xgmac_fifo_pack.vhd | 3 | 5,442 | ------------------------------------------------------------------------
-- title : package for the 10 gig ethernet mac fifo reference design
-- project : 10 gig ethernet mac fifo reference design
------------------------------------------------------------------------
-- file : xgmac_fifo_pack.vhd
-- author : xilinx inc.
------------------------------------------------------------------------
-- description : this module is the package used by the 10-gigabit
-- ethernet mac fifo interface.
--
------------------------------------------------------------------------
-- (c) Copyright 2001-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package xgmac_fifo_pack is
---------------------------------------------------------------------
-- purpose: define function to convert fifo word size into an address
-- width
-- type : function
---------------------------------------------------------------------
function log2 (
value : integer)
return integer;
---------------------------------------------------------------------
-- purpose : converts gray code to binary code
-- type : function
---------------------------------------------------------------------
function gray_to_bin (
gray : std_logic_vector)
return std_logic_vector;
---------------------------------------------------------------------
-- purpose : converts binary to gray code (by calling gray_to_bin)
---------------------------------------------------------------------
function bin_to_gray (
bin : std_logic_vector)
return std_logic_vector;
end xgmac_fifo_pack;
package body xgmac_fifo_pack is
---------------------------------------------------------------------
-- purpose: define function to convert fifo word size into an address
-- width
-- type : function
---------------------------------------------------------------------
function log2 (value : integer) return integer is
variable ret_val : integer;
begin
ret_val := 0;
if value <= 2**ret_val then
ret_val := 0;
else
while 2**ret_val < value loop
ret_val := ret_val + 1;
end loop;
end if;
return ret_val;
end log2;
function gray_to_bin (
gray : std_logic_vector)
return std_logic_vector is
variable binary : std_logic_vector(gray'range);
begin
for i in gray'high downto gray'low loop
if i = gray'high then
binary(i) := gray(i);
else
binary(i) := binary(i+1) xor gray(i);
end if;
end loop; -- i
return binary;
end gray_to_bin;
function bin_to_gray (
bin : std_logic_vector)
return std_logic_vector is
variable gray : std_logic_vector(bin'range);
begin
for i in bin'range loop
if i = bin'left then
gray(i) := bin(i);
else
gray(i) := bin(i+1) xor bin(i);
end if;
end loop; -- i
return gray;
end bin_to_gray;
end xgmac_fifo_pack;
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EV0UmQDpQmeC2Q/pWNOmwF3n7pSqqi2+Nsx97IDet2DhXEE=
`protect end_protected
| gpl-3.0 | 1c7adf35572c64f730e5cf1bace88aef | 0.94936 | 1.817573 | false | false | false | false |
inmcm/Simon_Speck_Ciphers | VHDL/SIMON_CIPHER_TB.vhd | 1 | 14,458 | -- SIMON_CIPHER_TB.vhd
-- Copyright 2016 Michael Calvin McCoy
-- [email protected]
-- see LICENSE.md
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:00:46 10/04/2015
-- Design Name:
-- Module Name: D:/Work/Code/Simon_Speck_Ciphers/VHDL/SIMON_CIPHER_TB.vhd
-- Project Name: Simon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SIMON_CIPHER
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.SIMON_CONSTANTS.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SIMON_CIPHER_TB IS
END SIMON_CIPHER_TB;
ARCHITECTURE behavior OF SIMON_CIPHER_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SIMON_CIPHER
GENERIC(KEY_SIZE : integer range 0 to 256;
BLOCK_SIZE : integer range 0 to 128;
ROUND_LIMIT: integer range 0 to 72);
PORT(
SYS_CLK : IN std_logic;
RST : IN std_logic;
BUSY : OUT std_logic;
CONTROL : IN std_logic_vector(1 downto 0);
KEY : IN std_logic_vector(KEY_SIZE - 1 downto 0);
BLOCK_INPUT : IN std_logic_vector(BLOCK_SIZE - 1 downto 0);
BLOCK_OUTPUT : OUT std_logic_vector(BLOCK_SIZE - 1 downto 0)
);
END COMPONENT;
--Global Inputs
signal SYS_CLK : std_logic := '0';
signal RST : std_logic := '0';
signal CONTROL : std_logic_vector(1 downto 0) := (others => '0');
--UUT 1
signal KEY_1 : std_logic_vector(63 downto 0) := (others => '0');
signal BLOCK_INPUT_1 : std_logic_vector(31 downto 0) := (others => '0');
signal BUSY_1 : std_logic;
signal BLOCK_OUTPUT_1 : std_logic_vector(31 downto 0);
--UUT 2
signal KEY_2 : std_logic_vector(71 downto 0) := (others => '0');
signal BLOCK_INPUT_2 : std_logic_vector(47 downto 0) := (others => '0');
signal BUSY_2 : std_logic;
signal BLOCK_OUTPUT_2 : std_logic_vector(47 downto 0);
--UUT 3
signal KEY_3 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_3 : std_logic_vector(47 downto 0) := (others => '0');
signal BUSY_3 : std_logic;
signal BLOCK_OUTPUT_3 : std_logic_vector(47 downto 0);
--UUT 4
signal KEY_4 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_4 : std_logic_vector(63 downto 0) := (others => '0');
signal BUSY_4 : std_logic;
signal BLOCK_OUTPUT_4 : std_logic_vector(63 downto 0);
--UUT 5
signal KEY_5 : std_logic_vector(127 downto 0) := (others => '0');
signal BLOCK_INPUT_5 : std_logic_vector(63 downto 0) := (others => '0');
signal BUSY_5 : std_logic;
signal BLOCK_OUTPUT_5 : std_logic_vector(63 downto 0);
--UUT 6
signal KEY_6 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_6 : std_logic_vector(95 downto 0) := (others => '0');
signal BUSY_6 : std_logic;
signal BLOCK_OUTPUT_6 : std_logic_vector(95 downto 0);
--UUT 7
signal KEY_7 : std_logic_vector(143 downto 0) := (others => '0');
signal BLOCK_INPUT_7 : std_logic_vector(95 downto 0) := (others => '0');
signal BUSY_7 : std_logic;
signal BLOCK_OUTPUT_7 : std_logic_vector(95 downto 0);
--UUT 8
signal KEY_8 : std_logic_vector(127 downto 0) := (others => '0');
signal BLOCK_INPUT_8 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_8 : std_logic;
signal BLOCK_OUTPUT_8 : std_logic_vector(127 downto 0);
--UUT 9
signal KEY_9 : std_logic_vector(191 downto 0) := (others => '0');
signal BLOCK_INPUT_9 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_9 : std_logic;
signal BLOCK_OUTPUT_9 : std_logic_vector(127 downto 0);
--UUT 10
signal KEY_10 : std_logic_vector(255 downto 0) := (others => '0');
signal BLOCK_INPUT_10 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_10 : std_logic;
signal BLOCK_OUTPUT_10 : std_logic_vector(127 downto 0);
-- Clock period definitions
constant SYS_CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut_1: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 64,
BLOCK_SIZE => 32,
ROUND_LIMIT => Round_Count_Lookup(64, 32))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_1,
CONTROL => CONTROL,
KEY => KEY_1,
BLOCK_INPUT => BLOCK_INPUT_1,
BLOCK_OUTPUT => BLOCK_OUTPUT_1
);
uut_2: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 72,
BLOCK_SIZE => 48,
ROUND_LIMIT => Round_Count_Lookup(72, 48))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_2,
CONTROL => CONTROL,
KEY => KEY_2,
BLOCK_INPUT => BLOCK_INPUT_2,
BLOCK_OUTPUT => BLOCK_OUTPUT_2
);
uut_3: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 48,
ROUND_LIMIT => Round_Count_Lookup(96, 48))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_3,
CONTROL => CONTROL,
KEY => KEY_3,
BLOCK_INPUT => BLOCK_INPUT_3,
BLOCK_OUTPUT => BLOCK_OUTPUT_3
);
uut_4: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 64,
ROUND_LIMIT => Round_Count_Lookup(96, 64))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_4,
CONTROL => CONTROL,
KEY => KEY_4,
BLOCK_INPUT => BLOCK_INPUT_4,
BLOCK_OUTPUT => BLOCK_OUTPUT_4
);
uut_5: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 128,
BLOCK_SIZE => 64,
ROUND_LIMIT => Round_Count_Lookup(128, 64))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_5,
CONTROL => CONTROL,
KEY => KEY_5,
BLOCK_INPUT => BLOCK_INPUT_5,
BLOCK_OUTPUT => BLOCK_OUTPUT_5
);
uut_6: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 96,
ROUND_LIMIT => Round_Count_Lookup(96, 96))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_6,
CONTROL => CONTROL,
KEY => KEY_6,
BLOCK_INPUT => BLOCK_INPUT_6,
BLOCK_OUTPUT => BLOCK_OUTPUT_6
);
uut_7: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 144,
BLOCK_SIZE => 96,
ROUND_LIMIT => Round_Count_Lookup(144, 96))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_7,
CONTROL => CONTROL,
KEY => KEY_7,
BLOCK_INPUT => BLOCK_INPUT_7,
BLOCK_OUTPUT => BLOCK_OUTPUT_7
);
uut_8: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 128,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(128, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_8,
CONTROL => CONTROL,
KEY => KEY_8,
BLOCK_INPUT => BLOCK_INPUT_8,
BLOCK_OUTPUT => BLOCK_OUTPUT_8
);
uut_9: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 192,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(192, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_9,
CONTROL => CONTROL,
KEY => KEY_9,
BLOCK_INPUT => BLOCK_INPUT_9,
BLOCK_OUTPUT => BLOCK_OUTPUT_9
);
uut_10: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 256,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(256, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_10,
CONTROL => CONTROL,
KEY => KEY_10,
BLOCK_INPUT => BLOCK_INPUT_10,
BLOCK_OUTPUT => BLOCK_OUTPUT_10
);
-- Clock process definitions
SYS_CLK_process :process
begin
for i in 0 to 500 loop
SYS_CLK <= '0';
wait for SYS_CLK_period/2;
SYS_CLK <= '1';
wait for SYS_CLK_period/2;
end loop ;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for SYS_CLK_period*10;
KEY_1 <= X"1918111009080100";
KEY_2 <= X"1211100a0908020100";
KEY_3 <= X"1a19181211100a0908020100";
KEY_4 <= X"131211100b0a090803020100";
KEY_5 <= X"1b1a1918131211100b0a090803020100";
KEY_6 <= X"0d0c0b0a0908050403020100";
KEY_7 <= X"1514131211100d0c0b0a0908050403020100";
KEY_8 <= X"0f0e0d0c0b0a09080706050403020100";
KEY_9 <= X"17161514131211100f0e0d0c0b0a09080706050403020100";
KEY_10 <= X"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100";
CONTROL <= "01";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
BLOCK_INPUT_1 <= X"65656877";
BLOCK_INPUT_2 <= X"6120676e696c";
BLOCK_INPUT_3 <= X"72696320646e";
BLOCK_INPUT_4 <= X"6f7220676e696c63";
BLOCK_INPUT_5 <= X"656b696c20646e75";
BLOCK_INPUT_6 <= X"2072616c6c69702065687420";
BLOCK_INPUT_7 <= X"74616874207473756420666f";
BLOCK_INPUT_8 <= X"63736564207372656c6c657661727420";
BLOCK_INPUT_9 <= X"206572656874206e6568772065626972";
BLOCK_INPUT_10 <= X"74206e69206d6f6f6d69732061207369";
CONTROL <= "11";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
assert BLOCK_OUTPUT_1 /= X"c69be9bb" report "UUT1 Encryption Success" severity note;
assert BLOCK_OUTPUT_1 = X"c69be9bb" report "UUT1 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_2 /= X"dae5ac292cac" report "UUT2 Encryption Success" severity note;
assert BLOCK_OUTPUT_2 = X"dae5ac292cac" report "UUT2 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_3 /= X"6e06a5acf156" report "UUT3 Encryption Success" severity note;
assert BLOCK_OUTPUT_3 = X"6e06a5acf156" report "UUT3 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_4 /= X"5ca2e27f111a8fc8" report "UUT4 Encryption Success" severity note;
assert BLOCK_OUTPUT_4 = X"5ca2e27f111a8fc8" report "UUT4 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_5 /= X"44c8fc20b9dfa07a" report "UUT5 Encryption Success" severity note;
assert BLOCK_OUTPUT_5 = X"44c8fc20b9dfa07a" report "UUT5 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_6 /= X"602807a462b469063d8ff082" report "UUT6 Encryption Success" severity note;
assert BLOCK_OUTPUT_6 = X"602807a462b469063d8ff082" report "UUT6 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_7 /= X"ecad1c6c451e3f59c5db1ae9" report "UUT7 Encryption Success" severity note;
assert BLOCK_OUTPUT_7 = X"ecad1c6c451e3f59c5db1ae9" report "UUT7 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_8 /= X"49681b1e1e54fe3f65aa832af84e0bbc" report "UUT8 Encryption Success" severity note;
assert BLOCK_OUTPUT_8 = X"49681b1e1e54fe3f65aa832af84e0bbc" report "UUT8 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_9 /= X"c4ac61effcdc0d4f6c9c8d6e2597b85b" report "UUT9 Encryption Success" severity note;
assert BLOCK_OUTPUT_9 = X"c4ac61effcdc0d4f6c9c8d6e2597b85b" report "UUT9 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_10 /= X"8d2b5579afc8a3a03bf72a87efe7b868" report "UUT10 Encryption Success" severity note;
assert BLOCK_OUTPUT_10 = X"8d2b5579afc8a3a03bf72a87efe7b868" report "UUT10 Encryption Failed" severity failure;
BLOCK_INPUT_1 <= X"c69be9bb";
BLOCK_INPUT_2 <= X"dae5ac292cac";
BLOCK_INPUT_3 <= X"6e06a5acf156";
BLOCK_INPUT_4 <= X"5ca2e27f111a8fc8";
BLOCK_INPUT_5 <= X"44c8fc20b9dfa07a";
BLOCK_INPUT_6 <= X"602807a462b469063d8ff082";
BLOCK_INPUT_7 <= X"ecad1c6c451e3f59c5db1ae9";
BLOCK_INPUT_8 <= X"49681b1e1e54fe3f65aa832af84e0bbc";
BLOCK_INPUT_9 <= X"c4ac61effcdc0d4f6c9c8d6e2597b85b";
BLOCK_INPUT_10 <= X"8d2b5579afc8a3a03bf72a87efe7b868";
CONTROL <= "10";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
assert BLOCK_OUTPUT_1 /= X"65656877" report "UUT1 Decryption Success" severity note;
assert BLOCK_OUTPUT_1 = X"65656877" report "UUT1 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_2 /= X"6120676e696c" report "UUT2 Decryption Success" severity note;
assert BLOCK_OUTPUT_2 = X"6120676e696c" report "UUT2 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_3 /= X"72696320646e" report "UUT3 Decryption Success" severity note;
assert BLOCK_OUTPUT_3 = X"72696320646e" report "UUT3 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_4 /= X"6f7220676e696c63" report "UUT4 Decryption Success" severity note;
assert BLOCK_OUTPUT_4 = X"6f7220676e696c63" report "UUT4 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_5 /= X"656b696c20646e75" report "UUT5 Decryption Success" severity note;
assert BLOCK_OUTPUT_5 = X"656b696c20646e75" report "UUT5 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_6 /= X"2072616c6c69702065687420" report "UUT6 Decryption Success" severity note;
assert BLOCK_OUTPUT_6 = X"2072616c6c69702065687420" report "UUT6 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_7 /= X"74616874207473756420666f" report "UUT7 Decryption Success" severity note;
assert BLOCK_OUTPUT_7 = X"74616874207473756420666f" report "UUT7 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_8 /= X"63736564207372656c6c657661727420" report "UUT8 Decryption Success" severity note;
assert BLOCK_OUTPUT_8 = X"63736564207372656c6c657661727420" report "UUT8 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_9 /= X"206572656874206e6568772065626972" report "UUT9 Decryption Success" severity note;
assert BLOCK_OUTPUT_9 = X"206572656874206e6568772065626972" report "UUT9 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_10 /= X"74206e69206d6f6f6d69732061207369" report "UUT10 Decryption Success" severity note;
assert BLOCK_OUTPUT_10 = X"74206e69206d6f6f6d69732061207369" report "UUT10 Decryption Failed" severity failure;
wait;
end process;
END behavior;
| mit | b27eb7d7b6e8f11346fedd918c57e989 | 0.645663 | 3.180378 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/rawUVCfifo/simulation/rawUVCfifo_pkg.vhd | 3 | 11,590 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE rawUVCfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT rawUVCfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rawUVCfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rawUVCfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT rawUVCfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rawUVCfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rawUVCfifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(24-1 DOWNTO 0);
DOUT : OUT std_logic_vector(24-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END rawUVCfifo_pkg;
PACKAGE BODY rawUVCfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END rawUVCfifo_pkg;
| bsd-2-clause | 6b0c9a9116f2fd27bb27c2d0872385a9 | 0.504228 | 3.991047 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_barrelshifter_GNV5DVAGHT.vhd | 8 | 1,654 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18);
port(
a : in std_logic_vector((WIDTH)-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
direction : in std_logic;
distance : in std_logic_vector((DISTANCE_WIDTH)-1 downto 0);
ena : in std_logic;
r : out std_logic_vector((WIDTH)-1 downto 0);
user_aclr : in std_logic);
end entity;
--- The DSPBuilder BarrelShifter
architecture rtl of alt_dspbuilder_barrelshifter_GNV5DVAGHT is
signal clear : std_logic;
signal a_ext : std_logic_vector(18 downto 0);
signal d_ext : std_logic_vector(5 - 1 downto 0);
signal r_ext : std_logic_vector(18 downto 0);
Begin
clear <= aclr or user_aclr;
a_ext(18 - 1 downto 0) <= a;
a_ext(18) <= '0';
d_ext(4 - 1 downto 0) <= distance;
d_ext(5 - 1 downto 4) <= (others => '0');
BarrelShifteri : alt_dspbuilder_BarrelShiftAltr Generic map (
widthin => WIDTH + 1 ,
pipeline => PIPELINE,
use_dedicated_circuitry => 0 ,
widthd => 5 ,
ndirection => NDIRECTION )
port map (
clock => clock,
aclr => clear,
sclr => '0',
ena => ena,
direction => '0',
xin => a_ext ,
distance => d_ext ,
yout => r_ext );
r <= r_ext(18 - 1 downto 0);
end architecture; | mit | a940855a4774f5d53ad53d54306e03e1 | 0.630593 | 2.779832 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/phase_align.vhd | 4 | 3,410 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/29 11:38:22 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: phase_align_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.2 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- PHASE_ALIGN
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: Phase alignment circuit for the comma alignment signal. Ensures
-- that the enable comma align signal is syncronous with the MGT
-- recovered clock.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity PHASE_ALIGN is
port (
-- Aurora Lane Interface
ENA_COMMA_ALIGN : in std_logic;
-- MGT Interface
RX_REC_CLK : in std_logic;
ENA_CALIGN_REC : out std_logic
);
end PHASE_ALIGN;
architecture RTL of PHASE_ALIGN is
-- Attribute Declaration
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of RTL: architecture is "true";
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal ENA_CALIGN_REC_Buffer : std_logic;
-- Internal Register Declarations --
signal phase_align_flops_r : std_logic_vector(0 to 1);
begin
ENA_CALIGN_REC <= ENA_CALIGN_REC_Buffer;
-- Main Body of Code --
-- To phase align the signal, we sample it using a flop clocked with the recovered
-- clock. We then sample the output of the first flop and pass it to the output.
-- This ensures that the signal is not metastable, and prevents transitions from
-- occuring except at the clock edge. The comma alignment circuit cannot tolerate
-- transitions except at the recovered clock edge.
process (RX_REC_CLK)
begin
if (RX_REC_CLK 'event and RX_REC_CLK = '1') then
phase_align_flops_r(0) <= ENA_COMMA_ALIGN after DLY;
phase_align_flops_r(1) <= phase_align_flops_r(0) after DLY;
end if;
end process;
ENA_CALIGN_REC_Buffer <= phase_align_flops_r(1);
end RTL;
| bsd-2-clause | 601e4f8f1f63126c90fe25a8e0de60a8 | 0.612317 | 4.088729 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/synth/golden_ticket_fifo.vhd | 3 | 37,388 | -- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:10.0
-- IP Revision: 128000
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v10_0;
USE fifo_generator_v10_0.fifo_generator_v10_0;
ENTITY golden_ticket_fifo IS
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END golden_ticket_fifo;
ARCHITECTURE golden_ticket_fifo_arch OF golden_ticket_fifo IS
COMPONENT fifo_generator_v10_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v10_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "fifo_generator_v10_0,Vivado 2013.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF golden_ticket_fifo_arch : ARCHITECTURE IS "golden_ticket_fifo,fifo_generator_v10_0,{x_ipProduct=Vivado 2013.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=10.0,x_ipCoreRevision=128000,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_HAS_AXI_WR_CHANNEL=0,C_HAS_AXI_RD_CHANNEL=0,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=0,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=64,C_AXIS_TID_WIDTH=8,C_AXIS_TDEST_WIDTH=4,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=8,C_AXIS_TKEEP_WIDTH=8,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
BEGIN
U0 : fifo_generator_v10_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 0,
C_HAS_AXI_WR_CHANNEL => 0,
C_HAS_AXI_RD_CHANNEL => 0,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 4,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 0,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 64,
C_AXIS_TID_WIDTH => 8,
C_AXIS_TDEST_WIDTH => 4,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 8,
C_AXIS_TKEEP_WIDTH => 8,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END golden_ticket_fifo_arch;
| gpl-3.0 | 534583035621d9ae40aeaef2df5c3810 | 0.612763 | 2.976989 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_StratixIV_OrphanedGland/top/ip/pll.vhd | 4 | 14,818 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 157 04/27/2011 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 11,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 25000,
intended_device_family => "Stratix IV",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
using_fbmimicbidir_port => "OFF",
width_clock => 10
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "220.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "40.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "220.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "25000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
-- Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 | f74dd7c25ee127b5d5b922ae20ea2e1e | 0.699015 | 3.365433 | false | false | false | false |
Siliciumer/DOS-Mario-FPGA | DOS_Mario.srcs/sources_1/ip/dist_mem_gen_2/synth/dist_mem_gen_2.vhd | 1 | 6,877 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0_10;
USE dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10;
ENTITY dist_mem_gen_2 IS
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END dist_mem_gen_2;
ARCHITECTURE dist_mem_gen_2_arch OF dist_mem_gen_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dist_mem_gen_2_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0_10 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0_10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dist_mem_gen_2_arch: ARCHITECTURE IS "dist_mem_gen_v8_0_10,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dist_mem_gen_2_arch : ARCHITECTURE IS "dist_mem_gen_2,dist_mem_gen_v8_0_10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dist_mem_gen_2_arch: ARCHITECTURE IS "dist_mem_gen_2,dist_mem_gen_v8_0_10,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_ADDR_WIDTH=12,C_DEFAULT_DATA=0,C_DEPTH=2160,C_HAS_CLK=0,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INI" &
"T_FILE=dist_mem_gen_2.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=6,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0_10
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 12,
C_DEFAULT_DATA => "0",
C_DEPTH => 2160,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "dist_mem_gen_2.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 6,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END dist_mem_gen_2_arch;
| mit | 1dcb5937208ea2e9e653aaf3366f0457 | 0.642868 | 3.115995 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/cmdfifo/simulation/cmdfifo_synth.vhd | 3 | 11,373 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY cmdfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF cmdfifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: cmdfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 16,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: cmdfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 16,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: cmdfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 16,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 8,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
cmdfifo_inst : cmdfifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-2-clause | a4acad4bab237f29ba9aedd421763447 | 0.455465 | 4.01589 | false | false | false | false |
inmcm/Simon_Speck_Ciphers | VHDL/AXI_IP/Speck_Block_Cipher_1.0/hdl/Speck_Block_Cipher_v1_0.vhd | 1 | 13,186 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.SPECK_CONSTANTS.all;
entity Speck_Block_Cipher_v1_0 is
generic (
-- Users to add parameters here
KEY_SIZE : integer range 0 to 256 := 256;
BLOCK_SIZE : integer range 0 to 128 := 128;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end Speck_Block_Cipher_v1_0;
architecture arch_imp of Speck_Block_Cipher_v1_0 is
-- component declaration
component Speck_Block_Cipher_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Cipher Block Input
SLV_REG00_OUT : out std_logic_vector(31 downto 0);
SLV_REG01_OUT : out std_logic_vector(31 downto 0);
SLV_REG02_OUT : out std_logic_vector(31 downto 0);
SLV_REG03_OUT : out std_logic_vector(31 downto 0);
-- Cipher Key Input
SLV_REG04_OUT : out std_logic_vector(31 downto 0);
SLV_REG05_OUT : out std_logic_vector(31 downto 0);
SLV_REG06_OUT : out std_logic_vector(31 downto 0);
SLV_REG07_OUT : out std_logic_vector(31 downto 0);
SLV_REG08_OUT : out std_logic_vector(31 downto 0);
SLV_REG09_OUT : out std_logic_vector(31 downto 0);
SLV_REG10_OUT : out std_logic_vector(31 downto 0);
SLV_REG11_OUT : out std_logic_vector(31 downto 0);
-- Cipher Control/Rest Register
SLV_REG12_OUT : out std_logic_vector(31 downto 0);
-- Cipher Block Output
SLV_REG13_IN : in std_logic_vector(31 downto 0);
SLV_REG14_IN : in std_logic_vector(31 downto 0);
SLV_REG15_IN : in std_logic_vector(31 downto 0);
SLV_REG16_IN : in std_logic_vector(31 downto 0);
-- Cipher Status Output
SLV_REG17_IN : in std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component Speck_Block_Cipher_v1_0_S00_AXI;
COMPONENT SPECK_CIPHER
GENERIC(KEY_SIZE : integer range 0 to 256;
BLOCK_SIZE : integer range 0 to 128;
ROUND_LIMIT: integer range 0 to 34);
PORT(
SYS_CLK : IN std_logic;
RST : IN std_logic;
BUSY : OUT std_logic;
CONTROL : IN std_logic_vector(1 downto 0);
KEY : IN std_logic_vector(KEY_SIZE - 1 downto 0);
BLOCK_INPUT : IN std_logic_vector(BLOCK_SIZE - 1 downto 0);
BLOCK_OUTPUT : OUT std_logic_vector(BLOCK_SIZE - 1 downto 0)
);
END COMPONENT;
-- Signals
signal input_key_buffer : std_logic_vector(KEY_SIZE -1 downto 0);
signal input_block_buffer : std_logic_vector(BLOCK_SIZE -1 downto 0);
signal output_block_buffer : std_logic_vector(BLOCK_SIZE -1 downto 0);
signal input_block_register_0 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_block_register_1 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_block_register_2 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_block_register_3 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal output_block_register_0 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal output_block_register_1 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal output_block_register_2 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal output_block_register_3 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_0 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_1 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_2 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_3 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_4 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_5 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_6 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_7 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal block_control_rst : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal block_status : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal busy_buffer : std_logic;
signal control_buffer : std_logic_vector(1 downto 0);
signal reset_buffer : std_logic;
begin
-- Instantiation of Axi Bus Interface S00_AXI
Speck_Block_Cipher_v1_0_S00_AXI_inst : Speck_Block_Cipher_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
-- Cipher Block Input
SLV_REG00_OUT => input_block_register_0,
SLV_REG01_OUT => input_block_register_1,
SLV_REG02_OUT => input_block_register_2,
SLV_REG03_OUT => input_block_register_3,
-- Cipher Key Input
SLV_REG04_OUT => input_key_register_0,
SLV_REG05_OUT => input_key_register_1,
SLV_REG06_OUT => input_key_register_2,
SLV_REG07_OUT => input_key_register_3,
SLV_REG08_OUT => input_key_register_4,
SLV_REG09_OUT => input_key_register_5,
SLV_REG10_OUT => input_key_register_6,
SLV_REG11_OUT => input_key_register_7,
-- Cipher Control/Rest Register
SLV_REG12_OUT => block_control_rst,
-- Cipher Block Output
SLV_REG13_IN => output_block_register_0,
SLV_REG14_IN => output_block_register_1,
SLV_REG15_IN => output_block_register_2,
SLV_REG16_IN => output_block_register_3,
-- Cipher Status Output
SLV_REG17_IN => block_status,
-- AXI Bus
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
Block_Cipher_Instance: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => KEY_SIZE,
BLOCK_SIZE => BLOCK_SIZE,
ROUND_LIMIT => Round_Count_Lookup(KEY_SIZE, BLOCK_SIZE))
PORT MAP (
SYS_CLK => s00_axi_aclk,
RST => reset_buffer,
BUSY => busy_buffer,
CONTROL => control_buffer,
KEY => input_key_buffer,
BLOCK_INPUT => input_block_buffer,
BLOCK_OUTPUT => output_block_buffer
);
-- User logic ends
block_status <= X"0000000" & "000" & busy_buffer;
control_buffer <= block_control_rst(1 downto 0);
reset_buffer <= block_control_rst(C_S00_AXI_DATA_WIDTH - 1);
BLOCK_32 : if (BLOCK_SIZE = 32) generate
begin
input_block_buffer <= input_block_register_0;
output_block_register_0 <= output_block_buffer;
output_block_register_1 <= (OTHERS => '0');
output_block_register_2 <= (OTHERS => '0');
output_block_register_3 <= (OTHERS => '0');
end generate;
BLOCK_48 : if (BLOCK_SIZE = 48) generate
begin
input_block_buffer <= input_block_register_1(15 downto 0) & input_block_register_0;
output_block_register_0 <= output_block_buffer(31 downto 0);
output_block_register_1 <= output_block_buffer(47 downto 32);
output_block_register_2 <= (OTHERS => '0');
output_block_register_3 <= (OTHERS => '0');
end generate;
BLOCK_64 : if (BLOCK_SIZE = 64) generate
begin
input_block_buffer <= input_block_register_1 & input_block_register_0;
output_block_register_0 <= output_block_buffer(31 downto 0);
output_block_register_1 <= output_block_buffer(63 downto 32);
output_block_register_2 <= (OTHERS => '0');
output_block_register_3 <= (OTHERS => '0');
end generate;
BLOCK_96 : if (BLOCK_SIZE = 96) generate
begin
input_block_buffer <= input_block_register_2 & input_block_register_1 & input_block_register_0;
output_block_register_0 <= output_block_buffer(31 downto 0);
output_block_register_1 <= output_block_buffer(63 downto 32);
output_block_register_2 <= output_block_buffer(95 downto 64);
output_block_register_3 <= (OTHERS => '0');
end generate;
BLOCK_128 : if (BLOCK_SIZE = 128) generate
begin
input_block_buffer <= input_block_register_3 & input_block_register_2 & input_block_register_1 & input_block_register_0;
output_block_register_0 <= output_block_buffer(31 downto 0);
output_block_register_1 <= output_block_buffer(63 downto 32);
output_block_register_2 <= output_block_buffer(95 downto 64);
output_block_register_3 <= output_block_buffer(127 downto 96);
end generate;
KEY_64 : if (KEY_SIZE = 64) generate
begin
input_key_buffer <= input_key_register_1 & input_key_register_0;
end generate;
KEY_72 : if (KEY_SIZE = 72) generate
begin
input_key_buffer <= input_key_register_2(7 downto 0) & input_key_register_1 & input_key_register_0;
end generate;
KEY_96 : if (KEY_SIZE = 96) generate
begin
input_key_buffer <= input_key_register_2 & input_key_register_1 & input_key_register_0;
end generate;
KEY_128 : if (KEY_SIZE = 128) generate
begin
input_key_buffer <= input_key_register_3 & input_key_register_2 & input_key_register_1 & input_key_register_0;
end generate;
KEY_144 : if (KEY_SIZE = 144) generate
begin
input_key_buffer <= input_key_register_4(15 downto 0) & input_key_register_3 & input_key_register_2 & input_key_register_1 & input_key_register_0;
end generate;
KEY_192 : if (KEY_SIZE = 192) generate
begin
input_key_buffer <= input_key_register_5 & input_key_register_4 & input_key_register_3 & input_key_register_2 & input_key_register_1 & input_key_register_0;
end generate;
KEY_256 : if (KEY_SIZE = 256) generate
begin
input_key_buffer <= input_key_register_7 & input_key_register_6 & input_key_register_5 & input_key_register_4 & input_key_register_3 & input_key_register_2 & input_key_register_1 & input_key_register_0;
end generate;
end arch_imp;
| mit | acfd9999244dcc3cfe9eb2748f005b1d | 0.626119 | 3.036849 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/ddr2ram/example_design/rtl/memc3_infrastructure.vhd | 4 | 12,268 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 2;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
--U_BUFG_CLK1 : BUFG
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in
-- );
U_BUFG_CLK1 : BUFGCE
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in,
CE => locked
);
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
| bsd-2-clause | 39f62b145fb4b06a38cd8b94138310fe | 0.531219 | 3.967658 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/wr_pf_ss.vhd | 9 | 30,210 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | d5ea54974bfbe18296e66cbf566e5384 | 0.94472 | 1.832019 | false | false | false | false |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_08_a/hdl/vhdl/radio_controller.vhd | 2 | 39,468 | -- Copyright (c) 2006 Rice University
-- All Rights Reserved
-- This code is covered by the Rice-WARP license
-- See http://warp.rice.edu/license/ for details
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library opb_ipif_v3_01_c;
use opb_ipif_v3_01_c.all;
library radio_controller_v1_08_a;
use radio_controller_v1_08_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"0000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
spi_clk : out std_logic;
data_out : out std_logic;
radio1_cs : out std_logic;
radio2_cs : out std_logic;
radio3_cs : out std_logic;
radio4_cs : out std_logic;
dac1_cs : out std_logic;
dac2_cs : out std_logic;
dac3_cs : out std_logic;
dac4_cs : out std_logic;
radio1_SHDN : out std_logic;
radio1_TxEn : out std_logic;
radio1_RxEn : out std_logic;
radio1_RxHP : out std_logic;
radio1_LD : in std_logic;
radio1_24PA : out std_logic;
radio1_5PA : out std_logic;
radio1_ANTSW : out std_logic_vector(0 to 1);
radio1_LED : out std_logic_vector(0 to 2);
radio1_ADC_RX_DCS : out std_logic;
radio1_ADC_RX_DFS : out std_logic;
radio1_ADC_RX_OTRA : in std_logic;
radio1_ADC_RX_OTRB : in std_logic;
radio1_ADC_RX_PWDNA : out std_logic;
radio1_ADC_RX_PWDNB : out std_logic;
radio1_DIPSW : in std_logic_vector(0 to 3);
radio1_RSSI_ADC_CLAMP : out std_logic;
radio1_RSSI_ADC_HIZ : out std_logic;
radio1_RSSI_ADC_OTR : in std_logic;
radio1_RSSI_ADC_SLEEP : out std_logic;
radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio1_TX_DAC_PLL_LOCK : in std_logic;
radio1_TX_DAC_RESET : out std_logic;
radio1_SHDN_external : in std_logic;
radio1_TxEn_external : in std_logic;
radio1_RxEn_external : in std_logic;
radio1_RxHP_external : in std_logic;
radio1_TxGain : out std_logic_vector(0 to 5);
radio1_TxStart : out std_logic;
radio2_SHDN : out std_logic;
radio2_TxEn : out std_logic;
radio2_RxEn : out std_logic;
radio2_RxHP : out std_logic;
radio2_LD : in std_logic;
radio2_24PA : out std_logic;
radio2_5PA : out std_logic;
radio2_ANTSW : out std_logic_vector(0 to 1);
radio2_LED : out std_logic_vector(0 to 2);
radio2_ADC_RX_DCS : out std_logic;
radio2_ADC_RX_DFS : out std_logic;
radio2_ADC_RX_OTRA : in std_logic;
radio2_ADC_RX_OTRB : in std_logic;
radio2_ADC_RX_PWDNA : out std_logic;
radio2_ADC_RX_PWDNB : out std_logic;
radio2_DIPSW : in std_logic_vector(0 to 3);
radio2_RSSI_ADC_CLAMP : out std_logic;
radio2_RSSI_ADC_HIZ : out std_logic;
radio2_RSSI_ADC_OTR : in std_logic;
radio2_RSSI_ADC_SLEEP : out std_logic;
radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio2_TX_DAC_PLL_LOCK : in std_logic;
radio2_TX_DAC_RESET : out std_logic;
radio2_SHDN_external : in std_logic;
radio2_TxEn_external : in std_logic;
radio2_RxEn_external : in std_logic;
radio2_RxHP_external : in std_logic;
radio2_TxGain : out std_logic_vector(0 to 5);
radio2_TxStart : out std_logic;
radio3_SHDN : out std_logic;
radio3_TxEn : out std_logic;
radio3_RxEn : out std_logic;
radio3_RxHP : out std_logic;
radio3_LD : in std_logic;
radio3_24PA : out std_logic;
radio3_5PA : out std_logic;
radio3_ANTSW : out std_logic_vector(0 to 1);
radio3_LED : out std_logic_vector(0 to 2);
radio3_ADC_RX_DCS : out std_logic;
radio3_ADC_RX_DFS : out std_logic;
radio3_ADC_RX_OTRA : in std_logic;
radio3_ADC_RX_OTRB : in std_logic;
radio3_ADC_RX_PWDNA : out std_logic;
radio3_ADC_RX_PWDNB : out std_logic;
radio3_DIPSW : in std_logic_vector(0 to 3);
radio3_RSSI_ADC_CLAMP : out std_logic;
radio3_RSSI_ADC_HIZ : out std_logic;
radio3_RSSI_ADC_OTR : in std_logic;
radio3_RSSI_ADC_SLEEP : out std_logic;
radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio3_TX_DAC_PLL_LOCK : in std_logic;
radio3_TX_DAC_RESET : out std_logic;
radio3_SHDN_external : in std_logic;
radio3_TxEn_external : in std_logic;
radio3_RxEn_external : in std_logic;
radio3_RxHP_external : in std_logic;
radio3_TxGain : out std_logic_vector(0 to 5);
radio3_TxStart : out std_logic;
radio4_SHDN : out std_logic;
radio4_TxEn : out std_logic;
radio4_RxEn : out std_logic;
radio4_RxHP : out std_logic;
radio4_LD : in std_logic;
radio4_24PA : out std_logic;
radio4_5PA : out std_logic;
radio4_ANTSW : out std_logic_vector(0 to 1);
radio4_LED : out std_logic_vector(0 to 2);
radio4_ADC_RX_DCS : out std_logic;
radio4_ADC_RX_DFS : out std_logic;
radio4_ADC_RX_OTRA : in std_logic;
radio4_ADC_RX_OTRB : in std_logic;
radio4_ADC_RX_PWDNA : out std_logic;
radio4_ADC_RX_PWDNB : out std_logic;
radio4_DIPSW : in std_logic_vector(0 to 3);
radio4_RSSI_ADC_CLAMP : out std_logic;
radio4_RSSI_ADC_HIZ : out std_logic;
radio4_RSSI_ADC_OTR : in std_logic;
radio4_RSSI_ADC_SLEEP : out std_logic;
radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio4_TX_DAC_PLL_LOCK : in std_logic;
radio4_TX_DAC_RESET : out std_logic;
radio4_SHDN_external : in std_logic;
radio4_TxEn_external : in std_logic;
radio4_RxEn_external : in std_logic;
radio4_RxHP_external : in std_logic;
radio4_TxGain : out std_logic_vector(0 to 5);
radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Constant: array of address range identifiers
------------------------------------------
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00 -- user logic S/W register address space
);
------------------------------------------
-- Constant: array of address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
);
------------------------------------------
-- Constant: array of data widths for each target address range
------------------------------------------
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic data width
);
------------------------------------------
-- Constant: array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_CE : integer := 17;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
);
------------------------------------------
-- Constant: array of unique properties for each address range
------------------------------------------
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic slave space dependent properties (none defined)
);
------------------------------------------
-- Constant: pipeline mode
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
-- Note:
-- only mode 4, 5, 7 are supported for this release
------------------------------------------
constant PIPELINE_MODEL : integer := 5;
------------------------------------------
-- Constant: user core ID code
------------------------------------------
constant DEV_BLK_ID : integer := 0;
------------------------------------------
-- Constant: enable MIR/Reset register
------------------------------------------
constant DEV_MIR_ENABLE : integer := 0;
------------------------------------------
-- Constant: array of IP interrupt mode
-- 1 = Active-high interrupt condition
-- 2 = Active-low interrupt condition
-- 3 = Active-high pulse interrupt event
-- 4 = Active-low pulse interrupt event
-- 5 = Positive-edge interrupt event
-- 6 = Negative-edge interrupt event
------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
------------------------------------------
-- Constant: enable device burst
------------------------------------------
constant DEV_BURST_ENABLE : integer := 0;
------------------------------------------
-- Constant: include address counter for burst transfers
------------------------------------------
constant INCLUDE_ADDR_CNTR : integer := 0;
------------------------------------------
-- Constant: include write buffer that decouples OPB and IPIC write transactions
------------------------------------------
constant INCLUDE_WR_BUF : integer := 0;
------------------------------------------
-- Constant: index for CS/CE
------------------------------------------
constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal ENABLE_POSTED_WRITE : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- enable posted write behavior
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 17
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
spi_clk : out std_logic;
data_out : out std_logic;
Radio1_cs : out std_logic;
Radio2_cs : out std_logic;
Radio3_cs : out std_logic;
Radio4_cs : out std_logic;
Dac1_cs : out std_logic;
Dac2_cs : out std_logic;
Dac3_cs : out std_logic;
Dac4_cs : out std_logic;
Radio1_SHDN : out std_logic;
Radio1_TxEn : out std_logic;
Radio1_RxEn : out std_logic;
Radio1_RxHP : out std_logic;
Radio1_LD : in std_logic;
Radio1_24PA : out std_logic;
Radio1_5PA : out std_logic;
Radio1_ANTSW : out std_logic_vector(0 to 1);
Radio1_LED : out std_logic_vector(0 to 2);
Radio1_ADC_RX_DCS : out std_logic;
Radio1_ADC_RX_DFS : out std_logic;
Radio1_ADC_RX_OTRA : in std_logic;
Radio1_ADC_RX_OTRB : in std_logic;
Radio1_ADC_RX_PWDNA : out std_logic;
Radio1_ADC_RX_PWDNB : out std_logic;
Radio1_DIPSW : in std_logic_vector(0 to 3);
Radio1_RSSI_ADC_CLAMP : out std_logic;
Radio1_RSSI_ADC_HIZ : out std_logic;
Radio1_RSSI_ADC_OTR : in std_logic;
Radio1_RSSI_ADC_SLEEP : out std_logic;
Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio1_TX_DAC_PLL_LOCK : in std_logic;
Radio1_TX_DAC_RESET : out std_logic;
Radio1_SHDN_external : in std_logic;
Radio1_TxEn_external : in std_logic;
Radio1_RxEn_external : in std_logic;
Radio1_RxHP_external : in std_logic;
Radio1_TxGain : out std_logic_vector(0 to 5);
Radio1_TxStart : out std_logic;
Radio2_SHDN : out std_logic;
Radio2_TxEn : out std_logic;
Radio2_RxEn : out std_logic;
Radio2_RxHP : out std_logic;
Radio2_LD : in std_logic;
Radio2_24PA : out std_logic;
Radio2_5PA : out std_logic;
Radio2_ANTSW : out std_logic_vector(0 to 1);
Radio2_LED : out std_logic_vector(0 to 2);
Radio2_ADC_RX_DCS : out std_logic;
Radio2_ADC_RX_DFS : out std_logic;
Radio2_ADC_RX_OTRA : in std_logic;
Radio2_ADC_RX_OTRB : in std_logic;
Radio2_ADC_RX_PWDNA : out std_logic;
Radio2_ADC_RX_PWDNB : out std_logic;
Radio2_DIPSW : in std_logic_vector(0 to 3);
Radio2_RSSI_ADC_CLAMP : out std_logic;
Radio2_RSSI_ADC_HIZ : out std_logic;
Radio2_RSSI_ADC_OTR : in std_logic;
Radio2_RSSI_ADC_SLEEP : out std_logic;
Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio2_TX_DAC_PLL_LOCK : in std_logic;
Radio2_TX_DAC_RESET : out std_logic;
Radio2_SHDN_external : in std_logic;
Radio2_TxEn_external : in std_logic;
Radio2_RxEn_external : in std_logic;
Radio2_RxHP_external : in std_logic;
Radio2_TxGain : out std_logic_vector(0 to 5);
Radio2_TxStart : out std_logic;
Radio3_SHDN : out std_logic;
Radio3_TxEn : out std_logic;
Radio3_RxEn : out std_logic;
Radio3_RxHP : out std_logic;
Radio3_LD : in std_logic;
Radio3_24PA : out std_logic;
Radio3_5PA : out std_logic;
Radio3_ANTSW : out std_logic_vector(0 to 1);
Radio3_LED : out std_logic_vector(0 to 2);
Radio3_ADC_RX_DCS : out std_logic;
Radio3_ADC_RX_DFS : out std_logic;
Radio3_ADC_RX_OTRA : in std_logic;
Radio3_ADC_RX_OTRB : in std_logic;
Radio3_ADC_RX_PWDNA : out std_logic;
Radio3_ADC_RX_PWDNB : out std_logic;
Radio3_DIPSW : in std_logic_vector(0 to 3);
Radio3_RSSI_ADC_CLAMP : out std_logic;
Radio3_RSSI_ADC_HIZ : out std_logic;
Radio3_RSSI_ADC_OTR : in std_logic;
Radio3_RSSI_ADC_SLEEP : out std_logic;
Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio3_TX_DAC_PLL_LOCK : in std_logic;
Radio3_TX_DAC_RESET : out std_logic;
Radio3_SHDN_external : in std_logic;
Radio3_TxEn_external : in std_logic;
Radio3_RxEn_external : in std_logic;
Radio3_RxHP_external : in std_logic;
Radio3_TxGain : out std_logic_vector(0 to 5);
Radio3_TxStart : out std_logic;
Radio4_SHDN : out std_logic;
Radio4_TxEn : out std_logic;
Radio4_RxEn : out std_logic;
Radio4_RxHP : out std_logic;
Radio4_LD : in std_logic;
Radio4_24PA : out std_logic;
Radio4_5PA : out std_logic;
Radio4_ANTSW : out std_logic_vector(0 to 1);
Radio4_LED : out std_logic_vector(0 to 2);
Radio4_ADC_RX_DCS : out std_logic;
Radio4_ADC_RX_DFS : out std_logic;
Radio4_ADC_RX_OTRA : in std_logic;
Radio4_ADC_RX_OTRB : in std_logic;
Radio4_ADC_RX_PWDNA : out std_logic;
Radio4_ADC_RX_PWDNB : out std_logic;
Radio4_DIPSW : in std_logic_vector(0 to 3);
Radio4_RSSI_ADC_CLAMP : out std_logic;
Radio4_RSSI_ADC_HIZ : out std_logic;
Radio4_RSSI_ADC_OTR : in std_logic;
Radio4_RSSI_ADC_SLEEP : out std_logic;
Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio4_TX_DAC_PLL_LOCK : in std_logic;
Radio4_TX_DAC_RESET : out std_logic;
Radio4_SHDN_external : in std_logic;
Radio4_TxEn_external : in std_logic;
Radio4_RxEn_external : in std_logic;
Radio4_RxHP_external : in std_logic;
Radio4_TxGain : out std_logic_vector(0 to 5);
Radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sl_DBus,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_retry => Sl_retry,
Sln_toutSup => Sl_toutSup,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_AddrAck => '0',
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => ENABLE_POSTED_WRITE,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => iBus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => iBus2IP_Reset
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
spi_clk => spi_clk,
data_out => data_out,
Radio1_cs => radio1_cs,
Radio2_cs => radio2_cs,
Radio3_cs => radio3_cs,
Radio4_cs => radio4_cs,
Dac1_cs => dac1_cs,
Dac2_cs => dac2_cs,
Dac3_cs => dac3_cs,
Dac4_cs => dac4_cs,
Radio1_SHDN => radio1_SHDN,
Radio1_TxEn => radio1_TxEn,
Radio1_RxEn => radio1_RxEn,
Radio1_RxHP => radio1_RxHP,
Radio1_LD => radio1_LD,
Radio1_24PA => radio1_24PA,
Radio1_5PA => radio1_5PA,
Radio1_ANTSW => radio1_ANTSW,
Radio1_LED => radio1_LED,
Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS,
Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS,
Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA,
Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB,
Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA,
Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB,
Radio1_DIPSW => radio1_DIPSW,
Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP,
Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ,
Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR,
Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP,
Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D,
Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK,
Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET,
Radio1_SHDN_external => radio1_SHDN_external,
Radio1_TxEn_external => radio1_TxEn_external,
Radio1_RxEn_external => radio1_RxEn_external,
Radio1_RxHP_external => radio1_RxHP_external,
Radio1_TxGain => radio1_TxGain,
Radio1_TxStart => radio1_TxStart,
Radio2_SHDN => radio2_SHDN,
Radio2_TxEn => radio2_TxEn,
Radio2_RxEn => radio2_RxEn,
Radio2_RxHP => radio2_RxHP,
Radio2_LD => radio2_LD,
Radio2_24PA => radio2_24PA,
Radio2_5PA => radio2_5PA,
Radio2_ANTSW => radio2_ANTSW,
Radio2_LED => radio2_LED,
Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS,
Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS,
Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA,
Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB,
Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA,
Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB,
Radio2_DIPSW => radio2_DIPSW,
Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP,
Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ,
Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR,
Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP,
Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D,
Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK,
Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET,
Radio2_SHDN_external => radio2_SHDN_external,
Radio2_TxEn_external => radio2_TxEn_external,
Radio2_RxEn_external => radio2_RxEn_external,
Radio2_RxHP_external => radio2_RxHP_external,
Radio2_TxGain => radio2_TxGain,
Radio2_TxStart => radio2_TxStart,
Radio3_SHDN => radio3_SHDN,
Radio3_TxEn => radio3_TxEn,
Radio3_RxEn => radio3_RxEn,
Radio3_RxHP => radio3_RxHP,
Radio3_LD => radio3_LD,
Radio3_24PA => radio3_24PA,
Radio3_5PA => radio3_5PA,
Radio3_ANTSW => radio3_ANTSW,
Radio3_LED => radio3_LED,
Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS,
Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS,
Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA,
Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB,
Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA,
Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB,
Radio3_DIPSW => radio3_DIPSW,
Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP,
Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ,
Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR,
Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP,
Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D,
Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK,
Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET,
Radio3_SHDN_external => radio3_SHDN_external,
Radio3_TxEn_external => radio3_TxEn_external,
Radio3_RxEn_external => radio3_RxEn_external,
Radio3_RxHP_external => radio3_RxHP_external,
Radio3_TxGain => radio3_TxGain,
Radio3_TxStart => radio3_TxStart,
Radio4_SHDN => radio4_SHDN,
Radio4_TxEn => radio4_TxEn,
Radio4_RxEn => radio4_RxEn,
Radio4_RxHP => radio4_RxHP,
Radio4_LD => radio4_LD,
Radio4_24PA => radio4_24PA,
Radio4_5PA => radio4_5PA,
Radio4_ANTSW => radio4_ANTSW,
Radio4_LED => radio4_LED,
Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS,
Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS,
Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA,
Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB,
Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA,
Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB,
Radio4_DIPSW => radio4_DIPSW,
Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP,
Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ,
Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR,
Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP,
Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D,
Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK,
Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET,
Radio4_SHDN_external => radio4_SHDN_external,
Radio4_TxEn_external => radio4_TxEn_external,
Radio4_RxEn_external => radio4_RxEn_external,
Radio4_RxHP_external => radio4_RxHP_external,
Radio4_TxGain => radio4_TxGain,
Radio4_TxStart => radio4_TxStart,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-2-clause | ffb0bf3f55f55c95580b9c2c2ec5efb8 | 0.443321 | 3.857687 | false | false | false | false |
ymei/TMSPlane | Firmware/src/gig_eth/KC705/com5402localpkg.vhd | 1 | 2,729 | -------------------------------------------------------------
-- MSS copyright 2011-2013
-- Filename: com5402pkg.VHD
-- Author: Alain Zarembowitch / MSS
-- Version: 1
-- Date last modified: 10/5/13
-- Inheritance: n/a
--
-- description: This package defines supplemental types, subtypes,
-- constants, and functions.
--
-- Usage: enter the number of UDP tx and rx components, the number of TCP servers and the number of TCP clients.
---------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package com5402pkg is
--// UDP -----------------------------------------------------
constant NUDPTX: integer range 0 to 1:= 0;
constant NUDPRX: integer range 0 to 1:= 0;
-- number of UDP ports enabled for tx and rx
constant IPv6_ENABLED: std_logic := '0';
-- future use.
--// TCP STREAMS -----------------------------------------------------
constant NTCPSTREAMS: integer range 0 to 255 := 2; -- number of concurrent TCP streams handled by this component
-- limitation: <= 255 streams (some integer to 8-bit slv conversions in the memory pointers)
-- In practice, the number of concurrent TCP streams per instantiated server is quite small as timing
-- gets worse. If a large number of concurrent TCP streams is needed, it may be better to create
-- multiple instantiations of the TCP_SERVER, each with a limited number of concurrent streams.
type SLV32xNTCPSTREAMStype is array (integer range 0 to (NTCPSTREAMS-1)) of std_logic_vector(31 downto 0);
type SLV24xNTCPSTREAMStype is array (integer range 0 to (NTCPSTREAMS-1)) of std_logic_vector(23 downto 0);
type SLV20xNTCPSTREAMStype is array (integer range 0 to (NTCPSTREAMS-1)) of std_logic_vector(19 downto 0);
type SLV16xNTCPSTREAMStype is array (integer range 0 to (NTCPSTREAMS-1)) of std_logic_vector(15 downto 0);
type SLV17xNTCPSTREAMStype is array (integer range 0 to (NTCPSTREAMS-1)) of std_logic_vector(16 downto 0);
type SLV9xNTCPSTREAMStype is array (integer range 0 to (NTCPSTREAMS-1)) of std_logic_vector(8 downto 0);
type SLV8xNTCPSTREAMStype is array (integer range 0 to (NTCPSTREAMS-1)) of std_logic_vector(7 downto 0);
type SLV4xNTCPSTREAMStype is array (integer range 0 to (NTCPSTREAMS-1)) of std_logic_vector(3 downto 0);
type SLV2xNTCPSTREAMStype is array (integer range 0 to (NTCPSTREAMS-1)) of std_logic_vector(1 downto 0);
type SLxNTCPSTREAMStype is array (integer range 0 to (NTCPSTREAMS-1)) of std_logic;
end com5402pkg;
package body com5402pkg is
-- Future use
end com5402pkg;
| bsd-3-clause | 056af155e97eee6928ea2051d411a121 | 0.633932 | 4.380417 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_prim_width.vhd | 9 | 70,108 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | cf37758f0a702b2b20717f0e2318b7c9 | 0.951646 | 1.826966 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/bin_cntr.vhd | 9 | 8,423 | `protect begin_protected
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| gpl-3.0 | d6fc9712edaef424923d491c4faaa5de | 0.920931 | 1.92746 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_extdepth.vhd | 9 | 51,718 | `protect begin_protected
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| gpl-3.0 | d918c82ac301e4b35c84c857b5b278f7 | 0.950037 | 1.827039 | false | false | false | false |
ymei/TMSPlane | Firmware/src/ten_gig_eth/TE07412C1/pcs_pma/ten_gig_eth_pcs_pma_wrapper.vhd | 3 | 10,440 | -------------------------------------------------------------------------------
-- Title : Example Design level wrapper
-- Project : 10GBASE-R
-------------------------------------------------------------------------------
-- File : ten_gig_eth_pcs_pma_0_example_design.vhd
-------------------------------------------------------------------------------
-- Description: This file is a wrapper for the 10GBASE-R core; it contains the
-- core support level and a few registers, including a DDR output register
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
entity ten_gig_eth_pcs_pma_wrapper is
port (
refclk_p : in std_logic;
refclk_n : in std_logic;
-- ymei dclk : in std_logic;
coreclk_out : out std_logic;
reset : in std_logic;
qpll_locked : out std_logic; -- ymei
sim_speedup_control: in std_logic := '0';
xgmii_txd : in std_logic_vector(63 downto 0);
xgmii_txc : in std_logic_vector(7 downto 0);
xgmii_rxd : out std_logic_vector(63 downto 0) := x"0000000000000000";
xgmii_rxc : out std_logic_vector(7 downto 0) := x"00";
xgmii_rx_clk : out std_logic;
txp : out std_logic;
txn : out std_logic;
rxp : in std_logic;
rxn : in std_logic;
mdc : in std_logic;
mdio_in : in std_logic;
mdio_out : out std_logic := '0';
mdio_tri : out std_logic := '0';
prtad : in std_logic_vector(4 downto 0);
core_status : out std_logic_vector(7 downto 0);
resetdone : out std_logic;
signal_detect : in std_logic;
tx_fault : in std_logic;
tx_disable : out std_logic);
end ten_gig_eth_pcs_pma_wrapper;
library ieee;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
architecture wrapper of ten_gig_eth_pcs_pma_wrapper is
----------------------------------------------------------------------------
-- Component Declaration for the 10GBASE-R block level.
----------------------------------------------------------------------------
component ten_gig_eth_pcs_pma_0_support is
port (
refclk_p : in std_logic;
refclk_n : in std_logic;
dclk_out : out std_logic; -- ymei
coreclk_out : out std_logic;
reset : in std_logic;
sim_speedup_control : in std_logic := '0';
qplloutclk_out : out std_logic;
qplloutrefclk_out : out std_logic;
qplllock_out : out std_logic;
rxrecclk_out : out std_logic;
txusrclk_out : out std_logic;
txusrclk2_out : out std_logic;
gttxreset_out : out std_logic;
gtrxreset_out : out std_logic;
txuserrdy_out : out std_logic;
areset_datapathclk_out : out std_logic;
reset_counter_done_out : out std_logic;
xgmii_txd : in std_logic_vector(63 downto 0);
xgmii_txc : in std_logic_vector(7 downto 0);
xgmii_rxd : out std_logic_vector(63 downto 0);
xgmii_rxc : out std_logic_vector(7 downto 0);
txp : out std_logic;
txn : out std_logic;
rxp : in std_logic;
rxn : in std_logic;
resetdone_out : out std_logic;
signal_detect : in std_logic;
tx_fault : in std_logic;
tx_disable : out std_logic;
mdc : in std_logic;
mdio_in : in std_logic;
mdio_out : out std_logic := '0';
mdio_tri : out std_logic := '0';
prtad : in std_logic_vector(4 downto 0);
pma_pmd_type : in std_logic_vector(2 downto 0);
core_status : out std_logic_vector(7 downto 0));
end component;
----------------------------------------------------------------------------
-- Signal declarations.
----------------------------------------------------------------------------
signal coreclk : std_logic;
signal resetdone_int : std_logic;
signal qplloutclk_out : std_logic;
signal qplloutrefclk_out : std_logic;
signal qplllock_out : std_logic;
signal dclk_buf : std_logic;
signal txusrclk_out : std_logic;
signal txusrclk2_out : std_logic;
signal gttxreset_out : std_logic;
signal gtrxreset_out : std_logic;
signal txuserrdy_out : std_logic;
signal areset_datapathclk_out : std_logic;
signal reset_counter_done_out : std_logic;
signal xgmii_txd_reg : std_logic_vector(63 downto 0) := x"0000000000000000";
signal xgmii_txc_reg : std_logic_vector(7 downto 0) := x"00";
signal xgmii_rxd_int : std_logic_vector(63 downto 0);
signal xgmii_rxc_int : std_logic_vector(7 downto 0);
signal mdio_out_int : std_logic;
signal mdio_tri_int : std_logic;
signal mdc_reg : std_logic := '0';
signal mdio_in_reg : std_logic := '0';
begin
resetdone <= resetdone_int;
-- Add a pipeline to the xmgii_tx inputs, to aid timing closure
tx_reg_proc : process(coreclk)
begin
if(coreclk'event and coreclk = '1') then
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;
end if;
end process;
-- Add a pipeline to the xmgii_rx outputs, to aid timing closure
rx_reg_proc : process(coreclk)
begin
if(coreclk'event and coreclk = '1') then
xgmii_rxd <= xgmii_rxd_int;
xgmii_rxc <= xgmii_rxc_int;
end if;
end process;
-- Add a pipeline to the mdio in/outputs, to aid timing closure
-- This is safe since the mdio clk is running so slowly.
mdio_outtri_reg_proc : process(coreclk)
begin
if(coreclk'event and coreclk = '1') then
mdio_tri <= mdio_tri_int;
mdio_out <= mdio_out_int;
mdc_reg <= mdc;
mdio_in_reg <= mdio_in;
end if;
end process;
-- ymei
-- dclk_bufg_i : BUFG
-- port map
-- (
-- I => dclk,
-- O => dclk_buf
-- );
-- Instance the 10GBASE-KR Core Support layer
ten_gig_eth_pcs_pma_core_support_layer_i : ten_gig_eth_pcs_pma_0_support
port map (
refclk_p => refclk_p,
refclk_n => refclk_n,
dclk_out => dclk_buf, -- ymei
coreclk_out => coreclk,
reset => reset,
sim_speedup_control => sim_speedup_control,
qplloutclk_out => qplloutclk_out,
qplloutrefclk_out => qplloutrefclk_out,
qplllock_out => qplllock_out,
rxrecclk_out => open,
txusrclk_out => txusrclk_out,
txusrclk2_out => txusrclk2_out,
gttxreset_out => gttxreset_out,
gtrxreset_out => gtrxreset_out,
txuserrdy_out => txuserrdy_out,
areset_datapathclk_out => areset_datapathclk_out,
reset_counter_done_out => reset_counter_done_out,
xgmii_txd => xgmii_txd_reg,
xgmii_txc => xgmii_txc_reg,
xgmii_rxd => xgmii_rxd_int,
xgmii_rxc => xgmii_rxc_int,
txp => txp,
txn => txn,
rxp => rxp,
rxn => rxn,
resetdone_out => resetdone_int,
signal_detect => signal_detect,
tx_fault => tx_fault,
tx_disable => tx_disable,
mdc => mdc_reg,
mdio_in => mdio_in_reg,
mdio_out => mdio_out_int,
mdio_tri => mdio_tri_int,
prtad => prtad,
pma_pmd_type => "101",
core_status => core_status);
qpll_locked <= qplllock_out; -- ymei
coreclk_out <= coreclk;
rx_clk_ddr : ODDR
generic map (
SRTYPE => "ASYNC",
DDR_CLK_EDGE => "SAME_EDGE")
port map (
Q => xgmii_rx_clk,
D1 => '0',
D2 => '1',
C => coreclk,
CE => '1',
R => '0',
S => '0');
end wrapper;
| bsd-3-clause | aa88eeb7b3077dddce48fbfc73be4329 | 0.551054 | 3.926288 | false | false | false | false |
ymei/TMSPlane | Firmware/src/clk_fwd.vhd | 1 | 1,558 | --------------------------------------------------------------------------------
--! @file clk_fwd.vhd
--! @brief Clock forwarding
--! @author Yuan Mei
--!
--! Allow both single_ended and differential outputs.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY clk_fwd IS
GENERIC (
INV : boolean := false;
SLEW : string := "SLOW"
);
PORT (
R : IN std_logic;
I : IN std_logic;
O : OUT std_logic;
O_P : OUT std_logic;
O_N : OUT std_logic
);
END clk_fwd;
ARCHITECTURE Behavioral OF clk_fwd IS
SIGNAL d1 : std_logic := '1';
SIGNAL d2 : std_logic := '0';
SIGNAL os : std_logic;
BEGIN
d1 <= '1' WHEN INV = false ELSE '0';
d2 <= '0' WHEN INV = false ELSE '1';
ODDR_inst : ODDR
GENERIC MAP (
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
PORT MAP (
Q => os,
C => I,
CE => '1',
D1 => d1,
D2 => d2,
R => R,
S => '0'
);
clk_fwd_obufds_inst : OBUFDS
GENERIC MAP(
IOSTANDARD => "DEFAULT",
SLEW => SLEW
)
PORT MAP (
O => O_P,
OB => O_N,
I => os
);
O <= os;
END Behavioral;
| bsd-3-clause | 6e259ffe26f2f6754b76f403635eb946 | 0.499358 | 3.648712 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo16_patch/wgtr.vhd | 9 | 22,085 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 67e62dad3f28856b454f925f76acb6df | 0.9434 | 1.858381 | false | false | false | false |
inmcm/Simon_Speck_Ciphers | VHDL/AXI_IP/Speck_Block_Cipher_Multirate_1.0/hdl/Speck_Block_Cipher_Multirate_v1_0.vhd | 1 | 16,041 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.SPECK_CONSTANTS.all;
entity Speck_Block_Cipher_Multirate_v1_0 is
generic (
-- Users to add parameters here
KEY_SIZE : integer range 0 to 256 := 256;
BLOCK_SIZE : integer range 0 to 128 := 128;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
cipher_clock : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end Speck_Block_Cipher_Multirate_v1_0;
architecture arch_imp of Speck_Block_Cipher_Multirate_v1_0 is
-- component declaration
component Speck_Block_Cipher_Multirate_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Cipher Block Input
SLV_REG00_OUT : out std_logic_vector(31 downto 0);
SLV_REG01_OUT : out std_logic_vector(31 downto 0);
SLV_REG02_OUT : out std_logic_vector(31 downto 0);
SLV_REG03_OUT : out std_logic_vector(31 downto 0);
-- Cipher Key Input
SLV_REG04_OUT : out std_logic_vector(31 downto 0);
SLV_REG05_OUT : out std_logic_vector(31 downto 0);
SLV_REG06_OUT : out std_logic_vector(31 downto 0);
SLV_REG07_OUT : out std_logic_vector(31 downto 0);
SLV_REG08_OUT : out std_logic_vector(31 downto 0);
SLV_REG09_OUT : out std_logic_vector(31 downto 0);
SLV_REG10_OUT : out std_logic_vector(31 downto 0);
SLV_REG11_OUT : out std_logic_vector(31 downto 0);
-- Cipher Control/Rest Register
SLV_REG12_OUT : out std_logic_vector(31 downto 0);
-- Cipher Block Output
SLV_REG13_IN : in std_logic_vector(31 downto 0);
SLV_REG14_IN : in std_logic_vector(31 downto 0);
SLV_REG15_IN : in std_logic_vector(31 downto 0);
SLV_REG16_IN : in std_logic_vector(31 downto 0);
-- Cipher Status Output
SLV_REG17_IN : in std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component Speck_Block_Cipher_Multirate_v1_0_S00_AXI;
COMPONENT SPECK_CIPHER
GENERIC(KEY_SIZE : integer range 0 to 256;
BLOCK_SIZE : integer range 0 to 128;
ROUND_LIMIT: integer range 0 to 34);
PORT(
SYS_CLK : IN std_logic;
RST : IN std_logic;
BUSY : OUT std_logic;
CONTROL : IN std_logic_vector(1 downto 0);
KEY : IN std_logic_vector(KEY_SIZE - 1 downto 0);
BLOCK_INPUT : IN std_logic_vector(BLOCK_SIZE - 1 downto 0);
BLOCK_OUTPUT : OUT std_logic_vector(BLOCK_SIZE - 1 downto 0)
);
END COMPONENT;
COMPONENT MUX_SYNCHRONIZER
Generic(BUS_SIZE : integer range 0 to 256 := 128);
Port ( CLK_A, CLK_B, RST : in std_logic;
DATA_BUS_A_IN : in std_logic_vector (BUS_SIZE - 1 downto 0);
DATA_BUS_B_OUT : out std_logic_vector (BUS_SIZE - 1 downto 0));
END COMPONENT;
-- Signals
signal input_key_buffer : std_logic_vector(KEY_SIZE -1 downto 0);
signal axi_key_buffer : std_logic_vector(KEY_SIZE -1 downto 0);
signal input_block_buffer : std_logic_vector(BLOCK_SIZE -1 downto 0);
signal axi_input_block_buffer : std_logic_vector(BLOCK_SIZE -1 downto 0);
signal output_block_buffer : std_logic_vector(BLOCK_SIZE -1 downto 0);
signal axi_output_block_buffer : std_logic_vector(BLOCK_SIZE -1 downto 0);
signal input_block_register_0 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_block_register_1 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_block_register_2 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_block_register_3 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal output_block_register_0 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal output_block_register_1 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal output_block_register_2 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal output_block_register_3 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_0 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_1 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_2 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_3 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_4 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_5 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_6 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal input_key_register_7 : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal block_control_rst : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal block_status : std_logic_vector(C_S00_AXI_DATA_WIDTH - 1 downto 0);
signal busy_buffer : std_logic;
signal busy_sync : std_logic_vector(1 downto 0);
signal axi_busy_buffer : std_logic;
signal control_buffer : std_logic_vector(1 downto 0);
signal axi_control_buffer : std_logic_vector(1 downto 0);
signal reset_buffer : std_logic;
signal reset_sync : std_logic_vector(1 downto 0);
signal axi_reset_buffer : std_logic;
begin
-- Instantiation of Axi Bus Interface S00_AXI
Speck_Block_Cipher_Multirate_v1_0_S00_AXI_inst : Speck_Block_Cipher_Multirate_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
-- Cipher Block Input
SLV_REG00_OUT => input_block_register_0,
SLV_REG01_OUT => input_block_register_1,
SLV_REG02_OUT => input_block_register_2,
SLV_REG03_OUT => input_block_register_3,
-- Cipher Key Input
SLV_REG04_OUT => input_key_register_0,
SLV_REG05_OUT => input_key_register_1,
SLV_REG06_OUT => input_key_register_2,
SLV_REG07_OUT => input_key_register_3,
SLV_REG08_OUT => input_key_register_4,
SLV_REG09_OUT => input_key_register_5,
SLV_REG10_OUT => input_key_register_6,
SLV_REG11_OUT => input_key_register_7,
-- Cipher Control/Rest Register
SLV_REG12_OUT => block_control_rst,
-- Cipher Block Output
SLV_REG13_IN => output_block_register_0,
SLV_REG14_IN => output_block_register_1,
SLV_REG15_IN => output_block_register_2,
SLV_REG16_IN => output_block_register_3,
-- Cipher Status Output
SLV_REG17_IN => block_status,
-- AXI BUS
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
Block_Cipher_Instance: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => KEY_SIZE,
BLOCK_SIZE => BLOCK_SIZE,
ROUND_LIMIT => Round_Count_Lookup(KEY_SIZE, BLOCK_SIZE))
PORT MAP (
SYS_CLK => cipher_clock,
RST => reset_buffer,
BUSY => busy_buffer,
CONTROL => control_buffer,
KEY => input_key_buffer,
BLOCK_INPUT => input_block_buffer,
BLOCK_OUTPUT => output_block_buffer
);
-- Synchronizer Instaniations
INPUT_DATA_SYNC: MUX_SYNCHRONIZER
GENERIC MAP (BUS_SIZE => BLOCK_SIZE)
PORT MAP (
CLK_A => s00_axi_aclk,
CLK_B => cipher_clock,
RST => axi_reset_buffer,
DATA_BUS_A_IN => axi_input_block_buffer,
DATA_BUS_B_OUT => input_block_buffer
);
OUTPUT_DATA_SYNC: MUX_SYNCHRONIZER
GENERIC MAP (BUS_SIZE => BLOCK_SIZE)
PORT MAP (
CLK_A => cipher_clock,
CLK_B => s00_axi_aclk,
RST => axi_reset_buffer,
DATA_BUS_A_IN => output_block_buffer,
DATA_BUS_B_OUT => axi_output_block_buffer
);
INPUT_KEY_SYNC: MUX_SYNCHRONIZER
GENERIC MAP (BUS_SIZE => KEY_SIZE)
PORT MAP (
CLK_A => s00_axi_aclk,
CLK_B => cipher_clock,
RST => axi_reset_buffer,
DATA_BUS_A_IN => axi_key_buffer,
DATA_BUS_B_OUT => input_key_buffer
);
INPUT_CONTROL_SYNC: MUX_SYNCHRONIZER
GENERIC MAP (BUS_SIZE => 2)
PORT MAP (
CLK_A => s00_axi_aclk,
CLK_B => cipher_clock,
RST => axi_reset_buffer,
DATA_BUS_A_IN => axi_control_buffer,
DATA_BUS_B_OUT => control_buffer
);
Reset_Signal_Synchronizer : process(cipher_clock)
begin
if (cipher_clock'event and cipher_clock = '1') then
reset_buffer <= reset_sync(1);
reset_sync <= reset_sync(0) & axi_reset_buffer;
end if;
end process;
Busy_Signal_Synchronizer : process(s00_axi_aclk)
begin
if (s00_axi_aclk'event and s00_axi_aclk = '1') then
axi_busy_buffer <= reset_sync(1);
busy_sync <= busy_sync(0) & busy_buffer;
end if;
end process;
block_status <= X"0000000" & "000" & busy_buffer;
axi_control_buffer <= block_control_rst(1 downto 0);
axi_reset_buffer <= block_control_rst(C_S00_AXI_DATA_WIDTH - 1);
BLOCK_32 : if (BLOCK_SIZE = 32) generate
begin
axi_input_block_buffer <= input_block_register_0;
output_block_register_0 <= axi_output_block_buffer;
output_block_register_1 <= (OTHERS => '0');
output_block_register_2 <= (OTHERS => '0');
output_block_register_3 <= (OTHERS => '0');
end generate;
BLOCK_48 : if (BLOCK_SIZE = 48) generate
begin
axi_input_block_buffer <= input_block_register_1(15 downto 0) & input_block_register_0;
output_block_register_0 <= axi_output_block_buffer(31 downto 0);
output_block_register_1 <= axi_output_block_buffer(47 downto 32);
output_block_register_2 <= (OTHERS => '0');
output_block_register_3 <= (OTHERS => '0');
end generate;
BLOCK_64 : if (BLOCK_SIZE = 64) generate
begin
axi_input_block_buffer <= input_block_register_1 & input_block_register_0;
output_block_register_0 <= axi_output_block_buffer(31 downto 0);
output_block_register_1 <= axi_output_block_buffer(63 downto 32);
output_block_register_2 <= (OTHERS => '0');
output_block_register_3 <= (OTHERS => '0');
end generate;
BLOCK_96 : if (BLOCK_SIZE = 96) generate
begin
axi_input_block_buffer <= input_block_register_2 & input_block_register_1 & input_block_register_0;
output_block_register_0 <= axi_output_block_buffer(31 downto 0);
output_block_register_1 <= axi_output_block_buffer(63 downto 32);
output_block_register_2 <= axi_output_block_buffer(95 downto 64);
output_block_register_3 <= (OTHERS => '0');
end generate;
BLOCK_128 : if (BLOCK_SIZE = 128) generate
begin
axi_input_block_buffer <= input_block_register_3 & input_block_register_2 & input_block_register_1 & input_block_register_0;
output_block_register_0 <= axi_output_block_buffer(31 downto 0);
output_block_register_1 <= axi_output_block_buffer(63 downto 32);
output_block_register_2 <= axi_output_block_buffer(95 downto 64);
output_block_register_3 <= axi_output_block_buffer(127 downto 96);
end generate;
KEY_64 : if (KEY_SIZE = 64) generate
begin
axi_key_buffer <= input_key_register_1 & input_key_register_0;
end generate;
KEY_72 : if (KEY_SIZE = 72) generate
begin
axi_key_buffer <= input_key_register_2(7 downto 0) & input_key_register_1 & input_key_register_0;
end generate;
KEY_96 : if (KEY_SIZE = 96) generate
begin
axi_key_buffer <= input_key_register_2 & input_key_register_1 & input_key_register_0;
end generate;
KEY_128 : if (KEY_SIZE = 128) generate
begin
axi_key_buffer <= input_key_register_3 & input_key_register_2 & input_key_register_1 & input_key_register_0;
end generate;
KEY_144 : if (KEY_SIZE = 144) generate
begin
axi_key_buffer <= input_key_register_4(15 downto 0) & input_key_register_3 & input_key_register_2 & input_key_register_1 & input_key_register_0;
end generate;
KEY_192 : if (KEY_SIZE = 192) generate
begin
axi_key_buffer <= input_key_register_5 & input_key_register_4 & input_key_register_3 & input_key_register_2 & input_key_register_1 & input_key_register_0;
end generate;
KEY_256 : if (KEY_SIZE = 256) generate
begin
axi_key_buffer <= input_key_register_7 & input_key_register_6 & input_key_register_5 & input_key_register_4 & input_key_register_3 & input_key_register_2 & input_key_register_1 & input_key_register_0;
end generate;
-- User logic ends
end arch_imp;
| mit | 6ac478867d5cceac4c9d457af8b3b809 | 0.613989 | 3.11234 | false | false | false | false |
Siliciumer/DOS-Mario-FPGA | DOS_Mario.srcs/sources_1/ip/dist_mem_gen_2/dist_mem_gen_v8_0_10/hdl/dist_mem_gen_v8_0.vhd | 3 | 17,726 | `protect begin_protected
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10992)
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`protect end_protected
| mit | d514794d3022a62cab591b9b65efb16e | 0.93518 | 1.871608 | false | false | false | false |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/hdl/Gray_Processing_GN.vhd | 2 | 8,011 | -- Gray_Processing_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:14:00
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Processing_GN is
port (
Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_valid.wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_data.wire
Avalon_ST_Source_startofpacket : out std_logic; -- Avalon_ST_Source_startofpacket.wire
Avalon_ST_Sink_valid : in std_logic := '0'; -- Avalon_ST_Sink_valid.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset_n
Avalon_ST_Sink_endofpacket : in std_logic := '0'; -- Avalon_ST_Sink_endofpacket.wire
Avalon_ST_Sink_ready : out std_logic; -- Avalon_ST_Sink_ready.wire
Avalon_ST_Source_endofpacket : out std_logic; -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0'); -- Avalon_ST_Sink_data.wire
Avalon_ST_Source_ready : in std_logic := '0'; -- Avalon_ST_Source_ready.wire
Avalon_ST_Sink_startofpacket : in std_logic := '0' -- Avalon_ST_Sink_startofpacket.wire
);
end entity Gray_Processing_GN;
architecture rtl of Gray_Processing_GN is
component alt_dspbuilder_clock_GNF343OQUJ is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNF343OQUJ;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component Gray_Processing_GN_Gray_Processing_Gray_Processing_Module is
port (
eop : in std_logic := 'X'; -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data_out : out std_logic_vector(23 downto 0); -- wire
sop : in std_logic := 'X' -- wire
);
end component Gray_Processing_GN_Gray_Processing_Gray_Processing_Module;
signal avalon_st_sink_valid_0_output_wire : std_logic; -- Avalon_ST_Sink_valid_0:output -> Avalon_ST_Source_valid_0:input
signal avalon_st_sink_startofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_startofpacket_0:output -> [Avalon_ST_Source_startofpacket_0:input, Gray_Processing_Gray_Processing_Module_0:sop]
signal avalon_st_sink_endofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_endofpacket_0:output -> [Avalon_ST_Source_endofpacket_0:input, Gray_Processing_Gray_Processing_Module_0:eop]
signal avalon_st_source_ready_0_output_wire : std_logic; -- Avalon_ST_Source_ready_0:output -> Avalon_ST_Sink_ready_0:input
signal avalon_st_sink_data_0_output_wire : std_logic_vector(23 downto 0); -- Avalon_ST_Sink_data_0:output -> Gray_Processing_Gray_Processing_Module_0:data_in
signal gray_processing_gray_processing_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Gray_Processing_Gray_Processing_Module_0:data_out -> Avalon_ST_Source_data_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Gray_Processing_Gray_Processing_Module_0:aclr
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Gray_Processing_Gray_Processing_Module_0:Clock
begin
clock_0 : component alt_dspbuilder_clock_GNF343OQUJ
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr_n => aclr -- .reset_n
);
avalon_st_sink_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => Avalon_ST_Sink_data, -- input.wire
output => avalon_st_sink_data_0_output_wire -- output.wire
);
avalon_st_sink_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_endofpacket, -- input.wire
output => avalon_st_sink_endofpacket_0_output_wire -- output.wire
);
gray_processing_gray_processing_module_0 : component Gray_Processing_GN_Gray_Processing_Gray_Processing_Module
port map (
eop => avalon_st_sink_endofpacket_0_output_wire, -- eop.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
data_in => avalon_st_sink_data_0_output_wire, -- data_in.wire
data_out => gray_processing_gray_processing_module_0_data_out_wire, -- data_out.wire
sop => avalon_st_sink_startofpacket_0_output_wire -- sop.wire
);
avalon_st_source_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_valid_0_output_wire, -- input.wire
output => Avalon_ST_Source_valid -- output.wire
);
avalon_st_sink_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_valid, -- input.wire
output => avalon_st_sink_valid_0_output_wire -- output.wire
);
avalon_st_source_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_endofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_endofpacket -- output.wire
);
avalon_st_source_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_startofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_startofpacket -- output.wire
);
avalon_st_source_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Source_ready, -- input.wire
output => avalon_st_source_ready_0_output_wire -- output.wire
);
avalon_st_sink_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_source_ready_0_output_wire, -- input.wire
output => Avalon_ST_Sink_ready -- output.wire
);
avalon_st_sink_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_startofpacket, -- input.wire
output => avalon_st_sink_startofpacket_0_output_wire -- output.wire
);
avalon_st_source_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => gray_processing_gray_processing_module_0_data_out_wire, -- input.wire
output => Avalon_ST_Source_data -- output.wire
);
end architecture rtl; -- of Gray_Processing_GN
| mit | 36a0c3bb59863ba427982eea0ce092c0 | 0.569717 | 3.430835 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/bytefifo/simulation/bytefifo_pctrl.vhd | 3 | 20,422 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.bytefifo_pkg.ALL;
ENTITY bytefifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF bytefifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:bytefifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:bytefifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| bsd-2-clause | 6bb69e20c967890555cf52ee8c94feb1 | 0.508765 | 3.197933 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/rawUVCfifo/simulation/rawUVCfifo_dgen.vhd | 3 | 4,535 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rawUVCfifo_pkg.ALL;
ENTITY rawUVCfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF rawUVCfifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:rawUVCfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| bsd-2-clause | c43094d14e7b3fc2e68f6859047b405d | 0.601544 | 4.27427 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/rgbfifo/simulation/rgbfifo_pctrl.vhd | 3 | 16,876 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
ENTITY rgbfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF rgbfifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & af_chk_i & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (EMPTY = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:rgbfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:rgbfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| bsd-2-clause | a3f5d6b60a1297c6b5ecc828b212f2e0 | 0.520028 | 3.344431 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/eeprom_v1_07_a/hdl/vhdl/eeprom.vhd | 6 | 26,908 | ------------------------------------------------------------------------------
-- eeprom.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: eeprom.vhd
-- Version: 1.04.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Jun 24 12:44:50 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_00_a;
use plbv46_slave_single_v1_00_a.plbv46_slave_single;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MEM0_BASEADDR -- User memory space 0 base address
-- C_MEM0_HIGHADDR -- User memory space 0 high address
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity eeprom is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM0_HIGHADDR : std_logic_vector := X"00000000"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
DQ0_T : out std_logic;
DQ0_O : out std_logic;
DQ0_I : in std_logic;
DQ1_T : out std_logic;
DQ1_O : out std_logic;
DQ1_I : in std_logic;
DQ2_T : out std_logic;
DQ2_O : out std_logic;
DQ2_I : in std_logic;
DQ3_T : out std_logic;
DQ3_O : out std_logic;
DQ3_I : in std_logic;
DQ4_T : out std_logic;
DQ4_O : out std_logic;
DQ4_I : in std_logic;
DQ5_T : out std_logic;
DQ5_O : out std_logic;
DQ5_I : in std_logic;
DQ6_T : out std_logic;
DQ6_O : out std_logic;
DQ6_I : in std_logic;
DQ7_T : out std_logic;
DQ7_O : out std_logic;
DQ7_I : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity eeprom;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of eeprom is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_MEM0_BASEADDR, -- user logic memory space 0 base address
ZERO_ADDR_PAD & C_MEM0_HIGHADDR -- user logic memory space 0 high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_MEM : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1 -- number of ce for user logic memory space 0 (always 1 chip enable)
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the slave address bus (32 only)
------------------------------------------
constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_MEM0_CS_INDEX : integer := 0;
constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_NUM_MEM : integer := 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
DQ0_T : out std_logic;
DQ0_O : out std_logic;
DQ0_I : in std_logic;
DQ1_T : out std_logic;
DQ1_O : out std_logic;
DQ1_I : in std_logic;
DQ2_T : out std_logic;
DQ2_O : out std_logic;
DQ2_I : in std_logic;
DQ3_T : out std_logic;
DQ3_O : out std_logic;
DQ3_I : in std_logic;
DQ4_T : out std_logic;
DQ4_O : out std_logic;
DQ4_I : in std_logic;
DQ5_T : out std_logic;
DQ5_O : out std_logic;
DQ5_I : in std_logic;
DQ6_T : out std_logic;
DQ6_O : out std_logic;
DQ6_I : in std_logic;
DQ7_T : out std_logic;
DQ7_O : out std_logic;
DQ7_I : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_SLV_AWIDTH-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_MEM-1);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_AWIDTH => USER_SLV_AWIDTH,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_MEM => USER_NUM_MEM
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
DQ0_T => DQ0_T,
DQ0_O => DQ0_O,
DQ0_I => DQ0_I,
DQ1_T => DQ1_T,
DQ1_O => DQ1_O,
DQ1_I => DQ1_I,
DQ2_T => DQ2_T,
DQ2_O => DQ2_O,
DQ2_I => DQ2_I,
DQ3_T => DQ3_T,
DQ3_O => DQ3_O,
DQ3_I => DQ3_I,
DQ4_T => DQ4_T,
DQ4_O => DQ4_O,
DQ4_I => DQ4_I,
DQ5_T => DQ5_T,
DQ5_O => DQ5_O,
DQ5_I => DQ5_I,
DQ6_T => DQ6_T,
DQ6_O => DQ6_O,
DQ6_I => DQ6_I,
DQ7_T => DQ7_T,
DQ7_O => DQ7_O,
DQ7_I => DQ7_I,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
end IMP;
| bsd-2-clause | 43bd8d761b1bc4f676bc76b521cc48c8 | 0.407462 | 4.573857 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/jpeg_encoder/design/QUANTIZER.vhd | 5 | 7,248 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : DCT QUANTIZER --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : QUANTIZER.VHD --
-- Created : Sun Aug 27 2006 --
-- --
--------------------------------------------------------------------------------
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity quantizer is
generic
(
SIZE_C : INTEGER := 12;
RAMQADDR_W : INTEGER := 7;
RAMQDATA_W : INTEGER := 8
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
divalid : in STD_LOGIC;
qdata : in std_logic_vector(7 downto 0);
qwaddr : in std_logic_vector(6 downto 0);
qwren : in std_logic;
cmp_idx : in unsigned(2 downto 0);
do : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
dovalid : out STD_LOGIC
);
end quantizer;
architecture rtl of quantizer is
constant INTERN_PIPE_C : INTEGER := 3;
signal romaddr_s : UNSIGNED(RAMQADDR_W-2 downto 0):=(others => '0');
signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0):=(others => '0');
signal romdatao_s : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0):=(others => '0');
signal divisor_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0):=(others => '0');
signal remainder_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0):=(others => '0');
signal do_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0):=(others => '0');
signal round_s : STD_LOGIC:='0';
signal di_d1 : std_logic_vector(SIZE_C-1 downto 0):=(others => '0');
signal pipeline_reg : STD_LOGIC_VECTOR(4 downto 0):=(others => '0');
signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0):=(others => '0');
signal do_rdiv : STD_LOGIC_VECTOR(SIZE_C-1 downto 0):=(others => '0');
signal table_select : std_logic:='0';
begin
----------------------------
-- RAMQ
----------------------------
U_RAMQ : entity work.RAMZ
generic map
(
RAMADDR_W => RAMQADDR_W,
RAMDATA_W => RAMQDATA_W
)
port map
(
d => qdata,
waddr => qwaddr,
raddr => slv_romaddr_s,
we => qwren,
clk => CLK,
q => romdatao_s
);
divisor_s(RAMQDATA_W-1 downto 0) <= romdatao_s;
divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0');
r_divider : entity work.r_divider
port map
(
rst => rst,
clk => clk,
a => di_d1,
d => romdatao_s,
q => do_s
) ;
do <= do_s;
slv_romaddr_s <= table_select & STD_LOGIC_VECTOR(romaddr_s);
------------------------------
-- Quantization sub table select
------------------------------
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
table_select <= '0';
else
-- luminance table select
if cmp_idx < 2 then
table_select <= '0';
-- chrominance table select
else
table_select <= '1';
end if;
end if;
end if;
end process;
----------------------------
-- address incrementer
----------------------------
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
romaddr_s <= (others => '0');
pipeline_reg <= (OTHERS => '0');
di_d1 <= (OTHERS => '0');
sign_bit_pipe <= (others => '0');
else
if divalid = '1' then
romaddr_s <= romaddr_s + TO_UNSIGNED(1,romaddr_s'length);
end if;
pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid;
di_d1 <= di;
sign_bit_pipe <= sign_bit_pipe(sign_bit_pipe'length-2 downto 0) & di(SIZE_C-1);
end if;
end if;
end process;
dovalid <= pipeline_reg(pipeline_reg'high);
end rtl;
-------------------------------------------------------------------------------- | bsd-2-clause | 616f375eb67e72a06533a1985159cd79 | 0.422599 | 4.604828 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/Gray_Processing_GN.vhd | 2 | 8,011 | -- Gray_Processing_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.11:11:33
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Processing_GN is
port (
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_data.wire
Avalon_ST_Source_startofpacket : out std_logic; -- Avalon_ST_Source_startofpacket.wire
Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_valid.wire
Avalon_ST_Sink_valid : in std_logic := '0'; -- Avalon_ST_Sink_valid.wire
Avalon_ST_Sink_startofpacket : in std_logic := '0'; -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Sink_ready : out std_logic; -- Avalon_ST_Sink_ready.wire
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0'); -- Avalon_ST_Sink_data.wire
Avalon_ST_Sink_endofpacket : in std_logic := '0'; -- Avalon_ST_Sink_endofpacket.wire
Avalon_ST_Source_ready : in std_logic := '0'; -- Avalon_ST_Source_ready.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset_n
Avalon_ST_Source_endofpacket : out std_logic -- Avalon_ST_Source_endofpacket.wire
);
end entity Gray_Processing_GN;
architecture rtl of Gray_Processing_GN is
component alt_dspbuilder_clock_GNF343OQUJ is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNF343OQUJ;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component Gray_Processing_GN_Gray_Processing_Gray_Processing_Module is
port (
data_out : out std_logic_vector(23 downto 0); -- wire
sop : in std_logic := 'X'; -- wire
eop : in std_logic := 'X'; -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data_in : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component Gray_Processing_GN_Gray_Processing_Gray_Processing_Module;
signal avalon_st_sink_valid_0_output_wire : std_logic; -- Avalon_ST_Sink_valid_0:output -> Avalon_ST_Source_valid_0:input
signal avalon_st_sink_startofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_startofpacket_0:output -> [Avalon_ST_Source_startofpacket_0:input, Gray_Processing_Gray_Processing_Module_0:sop]
signal avalon_st_sink_endofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_endofpacket_0:output -> [Avalon_ST_Source_endofpacket_0:input, Gray_Processing_Gray_Processing_Module_0:eop]
signal avalon_st_source_ready_0_output_wire : std_logic; -- Avalon_ST_Source_ready_0:output -> Avalon_ST_Sink_ready_0:input
signal avalon_st_sink_data_0_output_wire : std_logic_vector(23 downto 0); -- Avalon_ST_Sink_data_0:output -> Gray_Processing_Gray_Processing_Module_0:data_in
signal gray_processing_gray_processing_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Gray_Processing_Gray_Processing_Module_0:data_out -> Avalon_ST_Source_data_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Gray_Processing_Gray_Processing_Module_0:aclr
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Gray_Processing_Gray_Processing_Module_0:Clock
begin
clock_0 : component alt_dspbuilder_clock_GNF343OQUJ
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr_n => aclr -- .reset_n
);
avalon_st_sink_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => Avalon_ST_Sink_data, -- input.wire
output => avalon_st_sink_data_0_output_wire -- output.wire
);
avalon_st_sink_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_endofpacket, -- input.wire
output => avalon_st_sink_endofpacket_0_output_wire -- output.wire
);
gray_processing_gray_processing_module_0 : component Gray_Processing_GN_Gray_Processing_Gray_Processing_Module
port map (
data_out => gray_processing_gray_processing_module_0_data_out_wire, -- data_out.wire
sop => avalon_st_sink_startofpacket_0_output_wire, -- sop.wire
eop => avalon_st_sink_endofpacket_0_output_wire, -- eop.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
data_in => avalon_st_sink_data_0_output_wire -- data_in.wire
);
avalon_st_source_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_valid_0_output_wire, -- input.wire
output => Avalon_ST_Source_valid -- output.wire
);
avalon_st_sink_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_valid, -- input.wire
output => avalon_st_sink_valid_0_output_wire -- output.wire
);
avalon_st_source_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_endofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_endofpacket -- output.wire
);
avalon_st_source_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_startofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_startofpacket -- output.wire
);
avalon_st_source_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Source_ready, -- input.wire
output => avalon_st_source_ready_0_output_wire -- output.wire
);
avalon_st_sink_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_source_ready_0_output_wire, -- input.wire
output => Avalon_ST_Sink_ready -- output.wire
);
avalon_st_sink_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_startofpacket, -- input.wire
output => avalon_st_sink_startofpacket_0_output_wire -- output.wire
);
avalon_st_source_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => gray_processing_gray_processing_module_0_data_out_wire, -- input.wire
output => Avalon_ST_Source_data -- output.wire
);
end architecture rtl; -- of Gray_Processing_GN
| mit | 4eccd2d85ec962bbe49d5515bad7e4af | 0.569717 | 3.430835 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/tx_ll.vhd | 4 | 8,910 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:56 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: tx_ll_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- TX_LL
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- Description: The TX_LL module converts user data from the LocalLink interface
-- to Aurora Data, then sends it to the Aurora Channel for transmission.
-- It also handles NFC and UFC messages.
--
-- This module supports 1 2-byte lane designs
--
-- This module supports Immediate Mode Native Flow Control
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TX_LL is
port (
-- LocalLink PDU Interface
TX_D : in std_logic_vector(0 to 15);
TX_REM : in std_logic;
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
TX_DST_RDY_N : out std_logic;
-- NFC Interface
NFC_REQ_N : in std_logic;
NFC_NB : in std_logic_vector(0 to 3);
NFC_ACK_N : out std_logic;
-- Clock Compensation Interface
WARN_CC : in std_logic;
DO_CC : in std_logic;
-- Global Logic Interface
CHANNEL_UP : in std_logic;
-- Aurora Lane Interface
GEN_SCP : out std_logic;
GEN_ECP : out std_logic;
GEN_SNF : out std_logic;
FC_NB : out std_logic_vector(0 to 3);
TX_PE_DATA_V : out std_logic;
GEN_PAD : out std_logic;
TX_PE_DATA : out std_logic_vector(0 to 15);
GEN_CC : out std_logic;
-- RX_LL Interface
TX_WAIT : in std_logic;
DECREMENT_NFC : out std_logic;
-- System Interface
USER_CLK : in std_logic
);
end TX_LL;
architecture MAPPED of TX_LL is
-- External Register Declarations --
signal TX_DST_RDY_N_Buffer : std_logic;
signal NFC_ACK_N_Buffer : std_logic;
signal GEN_SCP_Buffer : std_logic;
signal GEN_ECP_Buffer : std_logic;
signal GEN_SNF_Buffer : std_logic;
signal FC_NB_Buffer : std_logic_vector(0 to 3);
signal TX_PE_DATA_V_Buffer : std_logic;
signal GEN_PAD_Buffer : std_logic;
signal TX_PE_DATA_Buffer : std_logic_vector(0 to 15);
signal GEN_CC_Buffer : std_logic;
signal DECREMENT_NFC_Buffer : std_logic;
-- Wire Declarations --
signal halt_c_i : std_logic;
signal tx_dst_rdy_n_i : std_logic;
-- Component Declarations --
component TX_LL_DATAPATH
port (
-- LocalLink PDU Interface
TX_D : in std_logic_vector(0 to 15);
TX_REM : in std_logic;
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
-- Aurora Lane Interface
TX_PE_DATA_V : out std_logic;
GEN_PAD : out std_logic;
TX_PE_DATA : out std_logic_vector(0 to 15);
-- TX_LL Control Module Interface
HALT_C : in std_logic;
TX_DST_RDY_N : in std_logic;
-- System Interface
CHANNEL_UP : in std_logic;
USER_CLK : in std_logic
);
end component;
component TX_LL_CONTROL
port (
-- LocalLink PDU Interface
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
TX_REM : in std_logic;
TX_DST_RDY_N : out std_logic;
-- NFC Interface
NFC_REQ_N : in std_logic;
NFC_NB : in std_logic_vector(0 to 3);
NFC_ACK_N : out std_logic;
-- Clock Compensation Interface
WARN_CC : in std_logic;
DO_CC : in std_logic;
-- Global Logic Interface
CHANNEL_UP : in std_logic;
-- TX_LL Control Module Interface
HALT_C : out std_logic;
-- Aurora Lane Interface
GEN_SCP : out std_logic;
GEN_ECP : out std_logic;
GEN_SNF : out std_logic;
FC_NB : out std_logic_vector(0 to 3);
GEN_CC : out std_logic;
-- RX_LL Interface
TX_WAIT : in std_logic;
DECREMENT_NFC : out std_logic;
-- System Interface
USER_CLK : in std_logic
);
end component;
begin
TX_DST_RDY_N <= TX_DST_RDY_N_Buffer;
NFC_ACK_N <= NFC_ACK_N_Buffer;
GEN_SCP <= GEN_SCP_Buffer;
GEN_ECP <= GEN_ECP_Buffer;
GEN_SNF <= GEN_SNF_Buffer;
FC_NB <= FC_NB_Buffer;
TX_PE_DATA_V <= TX_PE_DATA_V_Buffer;
GEN_PAD <= GEN_PAD_Buffer;
TX_PE_DATA <= TX_PE_DATA_Buffer;
GEN_CC <= GEN_CC_Buffer;
DECREMENT_NFC <= DECREMENT_NFC_Buffer;
-- Main Body of Code --
-- TX_DST_RDY_N is generated by TX_LL_CONTROL and used by TX_LL_DATAPATH and
-- external modules to regulate incoming pdu data signals.
TX_DST_RDY_N_Buffer <= tx_dst_rdy_n_i;
-- TX_LL_Datapath module
tx_ll_datapath_i : TX_LL_DATAPATH
port map (
-- LocalLink PDU Interface
TX_D => TX_D,
TX_REM => TX_REM,
TX_SRC_RDY_N => TX_SRC_RDY_N,
TX_SOF_N => TX_SOF_N,
TX_EOF_N => TX_EOF_N,
-- Aurora Lane Interface
TX_PE_DATA_V => TX_PE_DATA_V_Buffer,
GEN_PAD => GEN_PAD_Buffer,
TX_PE_DATA => TX_PE_DATA_Buffer,
-- TX_LL Control Module Interface
HALT_C => halt_c_i,
TX_DST_RDY_N => tx_dst_rdy_n_i,
-- System Interface
CHANNEL_UP => CHANNEL_UP,
USER_CLK => USER_CLK
);
-- TX_LL_Control module
tx_ll_control_i : TX_LL_CONTROL
port map (
-- LocalLink PDU Interface
TX_SRC_RDY_N => TX_SRC_RDY_N,
TX_SOF_N => TX_SOF_N,
TX_EOF_N => TX_EOF_N,
TX_REM => TX_REM,
TX_DST_RDY_N => tx_dst_rdy_n_i,
-- NFC Interface
NFC_REQ_N => NFC_REQ_N,
NFC_NB => NFC_NB,
NFC_ACK_N => NFC_ACK_N_Buffer,
-- Clock Compensation Interface
WARN_CC => WARN_CC,
DO_CC => DO_CC,
-- Global Logic Interface
CHANNEL_UP => CHANNEL_UP,
-- TX_LL Control Module Interface
HALT_C => halt_c_i,
-- Aurora Lane Interface
GEN_SCP => GEN_SCP_Buffer,
GEN_ECP => GEN_ECP_Buffer,
GEN_SNF => GEN_SNF_Buffer,
FC_NB => FC_NB_Buffer,
GEN_CC => GEN_CC_Buffer,
-- RX_LL Interface
TX_WAIT => TX_WAIT,
DECREMENT_NFC => DECREMENT_NFC_Buffer,
-- System Interface
USER_CLK => USER_CLK
);
end MAPPED;
| bsd-2-clause | 4e75571adc39c93ac4db6070b606cadf | 0.482716 | 3.860485 | false | false | false | false |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_01_a/hdl/vhdl/radio_controller.vhd | 2 | 25,787 | ------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY **
-- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR **
-- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND **
-- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES **
-- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: radio_controller.vhd
-- Version: 1.01.a
-- Description: Top level design, instantiates IPIF and user logic.
-- Date: Thu Jul 07 16:33:45 2005 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library opb_ipif_v3_01_a;
use opb_ipif_v3_01_a.all;
library radio_controller_v1_01_a;
use radio_controller_v1_01_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"0000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
radio1_shdn : out std_logic;
radio1_txen : out std_logic;
radio1_rxen : out std_logic;
radio1_rxhp : out std_logic;
radio1_ld : in std_logic;
radio1_24pa : out std_logic;
radio1_5pa : out std_logic;
radio1_antsw : out std_logic_vector(0 to 1);
radio1_led : out std_logic_vector(0 to 2);
radio2_shdn : out std_logic;
radio2_txen : out std_logic;
radio2_rxen : out std_logic;
radio2_rxhp : out std_logic;
radio2_ld : in std_logic;
radio2_24pa : out std_logic;
radio2_5pa : out std_logic;
radio2_antsw : out std_logic_vector(0 to 1);
radio2_led : out std_logic_vector(0 to 2);
radio3_shdn : out std_logic;
radio3_txen : out std_logic;
radio3_rxen : out std_logic;
radio3_rxhp : out std_logic;
radio3_ld : in std_logic;
radio3_24pa : out std_logic;
radio3_5pa : out std_logic;
radio3_antsw : out std_logic_vector(0 to 1);
radio3_led : out std_logic_vector(0 to 2);
radio4_shdn : out std_logic;
radio4_txen : out std_logic;
radio4_rxen : out std_logic;
radio4_rxhp : out std_logic;
radio4_ld : in std_logic;
radio4_24pa : out std_logic;
radio4_5pa : out std_logic;
radio4_antsw : out std_logic_vector(0 to 1);
radio4_led : out std_logic_vector(0 to 2);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Constant: array of address range identifiers
------------------------------------------
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00 -- user logic S/W register address space
);
------------------------------------------
-- Constant: array of address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
);
------------------------------------------
-- Constant: array of data widths for each target address range
------------------------------------------
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic data width
);
------------------------------------------
-- Constant: array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_CE : integer := 4;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
);
------------------------------------------
-- Constant: array of unique properties for each address range
------------------------------------------
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic slave space dependent properties (none defined)
);
------------------------------------------
-- Constant: pipeline mode
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
-- Note:
-- only mode 4, 5, 7 are supported for this release
------------------------------------------
constant PIPELINE_MODEL : integer := 5;
------------------------------------------
-- Constant: user core ID code
------------------------------------------
constant DEV_BLK_ID : integer := 0;
------------------------------------------
-- Constant: enable MIR/Reset register
------------------------------------------
constant DEV_MIR_ENABLE : integer := 0;
------------------------------------------
-- Constant: array of IP interrupt mode
-- 1 = Active-high interrupt condition
-- 2 = Active-low interrupt condition
-- 3 = Active-high pulse interrupt event
-- 4 = Active-low pulse interrupt event
-- 5 = Positive-edge interrupt event
-- 6 = Negative-edge interrupt event
------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
------------------------------------------
-- Constant: enable device burst
------------------------------------------
constant DEV_BURST_ENABLE : integer := 0;
------------------------------------------
-- Constant: include address counter for burst transfers
------------------------------------------
constant INCLUDE_ADDR_CNTR : integer := 0;
------------------------------------------
-- Constant: include write buffer that decouples OPB and IPIC write transactions
------------------------------------------
constant INCLUDE_WR_BUF : integer := 0;
------------------------------------------
-- Constant: index for CS/CE
------------------------------------------
constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Radio1_SHDN : out std_logic;
Radio1_TxEn : out std_logic;
Radio1_RxEn : out std_logic;
Radio1_RxHP : out std_logic;
Radio1_LD : in std_logic;
Radio1_24PA : out std_logic;
Radio1_5PA : out std_logic;
Radio1_ANTSW : out std_logic_vector(0 to 1);
Radio1_LED : out std_logic_vector(0 to 2);
Radio2_SHDN : out std_logic;
Radio2_TxEn : out std_logic;
Radio2_RxEn : out std_logic;
Radio2_RxHP : out std_logic;
Radio2_LD : in std_logic;
Radio2_24PA : out std_logic;
Radio2_5PA : out std_logic;
Radio2_ANTSW : out std_logic_vector(0 to 1);
Radio2_LED : out std_logic_vector(0 to 2);
Radio3_SHDN : out std_logic;
Radio3_TxEn : out std_logic;
Radio3_RxEn : out std_logic;
Radio3_RxHP : out std_logic;
Radio3_LD : in std_logic;
Radio3_24PA : out std_logic;
Radio3_5PA : out std_logic;
Radio3_ANTSW : out std_logic_vector(0 to 1);
Radio3_LED : out std_logic_vector(0 to 2);
Radio4_SHDN : out std_logic;
Radio4_TxEn : out std_logic;
Radio4_RxEn : out std_logic;
Radio4_RxHP : out std_logic;
Radio4_LD : in std_logic;
Radio4_24PA : out std_logic;
Radio4_5PA : out std_logic;
Radio4_ANTSW : out std_logic_vector(0 to 1);
Radio4_LED : out std_logic_vector(0 to 2);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_a.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sl_DBus,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_retry => Sl_retry,
Sln_toutSup => Sl_toutSup,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_AddrAck => '0',
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => iBus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => iBus2IP_Reset
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Radio1_SHDN => radio1_shdn,
Radio1_TxEn => radio1_txen,
Radio1_RxEn => radio1_rxen,
Radio1_RxHP => radio1_rxhp,
Radio1_LD => radio1_ld,
Radio1_24PA => radio1_24pa,
Radio1_5PA => radio1_5pa,
Radio1_ANTSW => radio1_antsw,
Radio1_LED => radio1_led,
Radio2_SHDN => radio2_shdn,
Radio2_TxEn => radio2_txen,
Radio2_RxEn => radio2_rxen,
Radio2_RxHP => radio2_rxhp,
Radio2_LD => radio2_ld,
Radio2_24PA => radio2_24pa,
Radio2_5PA => radio2_5pa,
Radio2_ANTSW => radio2_antsw,
Radio2_LED => radio2_led,
Radio3_SHDN => radio3_shdn,
Radio3_TxEn => radio3_txen,
Radio3_RxEn => radio3_rxen,
Radio3_RxHP => radio3_rxhp,
Radio3_LD => radio3_ld,
Radio3_24PA => radio3_24pa,
Radio3_5PA => radio3_5pa,
Radio3_ANTSW => radio3_antsw,
Radio3_LED => radio3_led,
Radio4_SHDN => radio4_shdn,
Radio4_TxEn => radio4_txen,
Radio4_RxEn => radio4_rxen,
Radio4_RxHP => radio4_rxhp,
Radio4_LD => radio4_ld,
Radio4_24PA => radio4_24pa,
Radio4_5PA => radio4_5pa,
Radio4_ANTSW => radio4_antsw,
Radio4_LED => radio4_led,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-2-clause | 9867f7c39f624e2547152ffa6dd9cb19 | 0.464575 | 4.031739 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_v8_0_synth.vhd | 9 | 160,200 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 985402397706e2e99c3381e530d21ac4 | 0.954488 | 1.813777 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/difclk_v1_00_a/hdl/vhdl/difclk.vhd | 4 | 1,527 | ---------------------------------------------------------------------------------------------------
--
-- Title : difclk
-- Design : flow4
-- Author : jiang hai
-- Company : Nokia
--
---------------------------------------------------------------------------------------------------
--
-- File : difclk.vhd
-- Generated : Mon Jul 31 10:34:43 2006
--
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Library XilinxCoreLib;
use XilinxCoreLib.all;
library unisim ;
use unisim.vcomponents.all ;
entity difclk is
port(
top_ref_clk_p : in STD_LOGIC;
top_ref_clk_n : in STD_LOGIC;
user_clk_i : out STD_LOGIC;
top_ref_clk_i : out STD_LOGIC
);
end difclk;
--}} End of automatically maintained section
architecture difclk of difclk is
signal top_ref_clk_i_1: std_logic;
begin
-- Differential Clock Buffers for top clock input
diff_clk_buff_top : IBUFGDS_LVDS_25
port map(
I =>top_ref_clk_p , --IN
IB =>top_ref_clk_n , --IN
O =>top_ref_clk_i_1 --OUT
);
--
-- Bufg used to drive user clk on global clock net
user_clock_bufg:BUFG
port map(
I =>top_ref_clk_i_1 , --IN
O =>user_clk_i --OUT
);
top_ref_clk_i <= top_ref_clk_i_1;
end difclk;
| bsd-2-clause | d5f6a5fb265ca750f7f57722fc9b6f88 | 0.451866 | 3.510345 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/rgbfifo/simulation/rgbfifo_synth.vhd | 3 | 10,207 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rgbfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF rgbfifo_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: rgbfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: rgbfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: rgbfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
rgbfifo_inst : rgbfifo_exdes
PORT MAP (
CLK => clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-2-clause | 0ed23948c0161d1a51cfdffa789ed552 | 0.456353 | 4.228252 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/clkGen/example_design/clkGen_exdes.vhd | 3 | 6,572 | -- file: clkGen_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clkGen_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(3 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(3 downto 1)
);
end clkGen_exdes;
architecture xilinx of clkGen_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 3;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal clk_n : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component clkGen is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clkGen
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int(1),
CLK_OUT2 => clk_int(2),
CLK_OUT3 => clk_int(3));
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clk_n(clk_out_pins) <= not clk(clk_out_pins);
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(clk_out_pins),
C0 => clk(clk_out_pins),
C1 => clk_n(clk_out_pins),
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
clk(3) <= clk_int(3);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| bsd-2-clause | afab2f667fb1bf391cd073e0dd151ee2 | 0.621576 | 3.809855 | false | false | false | false |
inmcm/Simon_Speck_Ciphers | VHDL/AXI_IP/Speck_Block_Cipher_Multirate_1.0/hdl/Speck_Block_Cipher_Multirate_v1_0_S00_AXI.vhd | 1 | 26,284 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Speck_Block_Cipher_Multirate_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
-- Cipher Block Input
SLV_REG00_OUT : out std_logic_vector(31 downto 0);
SLV_REG01_OUT : out std_logic_vector(31 downto 0);
SLV_REG02_OUT : out std_logic_vector(31 downto 0);
SLV_REG03_OUT : out std_logic_vector(31 downto 0);
-- Cipher Key Input
SLV_REG04_OUT : out std_logic_vector(31 downto 0);
SLV_REG05_OUT : out std_logic_vector(31 downto 0);
SLV_REG06_OUT : out std_logic_vector(31 downto 0);
SLV_REG07_OUT : out std_logic_vector(31 downto 0);
SLV_REG08_OUT : out std_logic_vector(31 downto 0);
SLV_REG09_OUT : out std_logic_vector(31 downto 0);
SLV_REG10_OUT : out std_logic_vector(31 downto 0);
SLV_REG11_OUT : out std_logic_vector(31 downto 0);
-- Cipher Control/Rest Register
SLV_REG12_OUT : out std_logic_vector(31 downto 0);
-- Cipher Block Output
SLV_REG13_IN : in std_logic_vector(31 downto 0);
SLV_REG14_IN : in std_logic_vector(31 downto 0);
SLV_REG15_IN : in std_logic_vector(31 downto 0);
SLV_REG16_IN : in std_logic_vector(31 downto 0);
-- Cipher Status Output
SLV_REG17_IN : in std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end Speck_Block_Cipher_Multirate_v1_0_S00_AXI;
architecture arch_imp of Speck_Block_Cipher_Multirate_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 14
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= slv_reg0;
when b"00001" =>
reg_data_out <= slv_reg1;
when b"00010" =>
reg_data_out <= slv_reg2;
when b"00011" =>
reg_data_out <= slv_reg3;
when b"00100" =>
reg_data_out <= slv_reg4;
when b"00101" =>
reg_data_out <= slv_reg5;
when b"00110" =>
reg_data_out <= slv_reg6;
when b"00111" =>
reg_data_out <= slv_reg7;
when b"01000" =>
reg_data_out <= slv_reg8;
when b"01001" =>
reg_data_out <= slv_reg9;
when b"01010" =>
reg_data_out <= slv_reg10;
when b"01011" =>
reg_data_out <= slv_reg11;
when b"01100" =>
reg_data_out <= slv_reg12;
when b"01101" =>
reg_data_out <= SLV_REG13_IN;
when b"01110" =>
reg_data_out <= SLV_REG14_IN;
when b"01111" =>
reg_data_out <= SLV_REG15_IN;
when b"10000" =>
reg_data_out <= SLV_REG16_IN;
when b"10001" =>
reg_data_out <= SLV_REG17_IN;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
SLV_REG00_OUT <= slv_reg0;
SLV_REG01_OUT <= slv_reg1;
SLV_REG02_OUT <= slv_reg2;
SLV_REG03_OUT <= slv_reg3;
SLV_REG04_OUT <= slv_reg4;
SLV_REG05_OUT <= slv_reg5;
SLV_REG06_OUT <= slv_reg6;
SLV_REG07_OUT <= slv_reg7;
SLV_REG08_OUT <= slv_reg8;
SLV_REG09_OUT <= slv_reg9;
SLV_REG10_OUT <= slv_reg10;
SLV_REG11_OUT <= slv_reg11;
SLV_REG12_OUT <= slv_reg12;
-- User logic ends
end arch_imp; | mit | f740c0be2ae3e60ac6a521736d62952a | 0.568673 | 3.467089 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/cdcfifo/simulation/cdcfifo_synth.vhd | 3 | 11,266 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.cdcfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY cdcfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF cdcfifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: cdcfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: cdcfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: cdcfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
cdcfifo_inst : cdcfifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-2-clause | 6cf3e14523923b461f4570cd31573677 | 0.45695 | 3.99929 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/bytefifoFPGA.vhd | 3 | 10,675 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bytefifoFPGA.vhd when simulating
-- the core, bytefifoFPGA. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bytefifoFPGA IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END bytefifoFPGA;
ARCHITECTURE bytefifoFPGA_a OF bytefifoFPGA IS
-- synthesis translate_off
COMPONENT wrapped_bytefifoFPGA
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bytefifoFPGA USE ENTITY XilinxCoreLib.fifo_generator_v9_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 15,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 1,
c_has_almost_full => 1,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 1,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 1,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "8kx4",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 32256,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 32255,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 15,
c_rd_depth => 32768,
c_rd_freq => 1,
c_rd_pntr_width => 15,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 15,
c_wr_depth => 32768,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 15,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bytefifoFPGA
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
underflow => underflow,
prog_full => prog_full
);
-- synthesis translate_on
END bytefifoFPGA_a;
| bsd-2-clause | 4ea49705c587eec48a6d5f75447630a2 | 0.542295 | 3.37496 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_logic_pkt_fifo.vhd | 9 | 43,848 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | c9d371ca7539c7b1cd231c56392d5b3e | 0.948299 | 1.825707 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_barrelshifter.vhd | 4 | 2,271 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_barrelshifter is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
user_aclr : in std_logic;
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0);
r : out std_logic_vector(WIDTH-1 downto 0);
clock : in std_logic;
direction : in std_logic;
a : in std_logic_vector(WIDTH-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_barrelshifter;
architecture rtl of alt_dspbuilder_barrelshifter is
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18
);
port (
a : in std_logic_vector(18-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
distance : in std_logic_vector(4-1 downto 0);
ena : in std_logic;
r : out std_logic_vector(18-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
begin
alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: if ((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)) generate
inst_alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map(DISTANCE_WIDTH => 4, NDIRECTION => 1, SIGNED => 0, USE_DEDICATED_CIRCUITRY => "false", PIPELINE => 0, WIDTH => 18)
port map(a => a, aclr => aclr, clock => clock, distance => distance, ena => ena, r => r, user_aclr => user_aclr);
end generate;
assert not (((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)))
report "Please run generate again" severity error;
end architecture rtl;
| mit | 767f4f7744cd7727d6d0795903a863c9 | 0.695288 | 3.149792 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/misc/pattern.vhd | 3 | 6,631 | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- Format Pixel Clock | Horizontal (in Pixels) | Vertical (in Lines)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- | Active Video | Front Porch | Sync Pulse | Back Porch | Total | Active Video | Front Porch | Sync Pulse | Back Porch | Total
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- 1024x768,60Hz 65.000 | 1024 | 24 | 136 | 160 | 1344 | 768 | 3 | 6 | 29 | 806
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- Total Horizontal = 1344
-- Total Vertical = 806
-- O Total frame time
-- P Sync length
-- Q Back porch
-- R Active video time
-- S Front porch
-- ______________________ ________
-- ________| VIDEO |________| VIDEO (next frame)
-- |-Q-|----------R-----------|-S-|
-- __ ______________________________ ___________
-- |_| |_|
-- |P|
-- |---------------O----------------|
-- reff: http://martin.hinner.info/vga/timing.html
-- reff: http://www.epanorama.net/faq/vga2rgb/calc.html
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pattern is
generic (
SIMULATION : string := "FALSE");
port
(
rgb : out std_logic_vector(23 downto 0);
resx : out std_logic_vector(15 downto 0);
resy : out std_logic_vector(15 downto 0);
de : out std_logic;
pclk : out std_logic;
vsync : out std_logic;
hsync : out std_logic;
clk : in std_logic;
rst_n : in std_logic
);
end entity pattern;
architecture rtl of pattern is
component patternClk
port
(
CLK_IN1 : in std_logic;
CLK_OUT1 : out std_logic
);
end component;
signal counterX : std_logic_vector(15 downto 0);
signal counterY : std_logic_vector(15 downto 0);
signal resX_i : std_logic_vector(15 downto 0);
signal resY_i : std_logic_vector(15 downto 0);
signal spY : integer;
signal bpY : integer;
signal fpY : integer;
signal spX : integer;
signal bpX : integer;
signal fpX : integer;
signal data : std_logic_vector(23 downto 0);
signal pclk_i : std_logic;
signal vsync_i : std_logic;
signal hsync_i : std_logic;
signal vActive : std_logic;
signal hActive : std_logic;
signal frameCounter : std_logic_vector(5 downto 0) := (others => '0');
signal secondTimeout : std_logic;
signal color : std_logic := '0';
signal barWidth : integer;
-- Color of bars defined here. May be customized
type colorsArray is array (0 to 7) of std_logic_vector(23 downto 0);
constant colors_1 : colorsArray := (X"ffffff", X"000000", X"0000ff", X"00ff00", X"ff0000", X"00ffff", X"ff00ff", X"ffff00");
constant colors_2 : colorsArray := (X"000000", X"ffffff", X"ffff00", X"ff00ff", X"00ffff", X"ff0000", X"00ff00", X"0000ff");
signal colors : colorsArray := colors_1;
begin
RESF: if (SIMULATION = "FALSE" ) generate
resX_i <= X"0400";
resY_i <= X"0300";
spY <= 6;
bpY <= 29;
fpY <= 3;
spX <= 136;
bpX <= 160;
fpX <= 24;
barWidth <= 128;
end generate;
REST: if (SIMULATION = "TRUE" ) generate
resX_i <= X"0200";
resY_i <= X"0008";
spY <= 1;
bpY <= 2;
fpY <= 3;
spX <= 16;
bpX <= 10;
fpX <= 2;
barWidth <= 64;
end generate;
-- rgb <= (data(7 downto 0) & data(23 downto 16) & data(15 downto 8));
rgb <= data;
resX <= resX_i;
resY <= resY_i;
pclk <= pclk_i;
vsync <= vsync_i;
hsync <= hsync_i;
de <= vActive and hActive;
process(rst_n,pclk_i)
begin
if rst_n = '0' then
data <= (others => '0');
counterX <= (others => '0');
counterY <= (others => '0');
vsync_i <= '0';
vActive <= '0';
hsync_i <= '0';
hActive <= '0';
elsif rising_edge(pclk_i) then
counterX <= counterX + 1;
if counterY = 0 then
vsync_i <= '0';
vActive <= '0';
elsif counterY = spY then
vsync_i <= '1';
elsif counterY = (spY+bpY) then
vActive <= '1';
elsif counterY = (spY+bpY+CONV_INTEGER(resY_i)) then
vActive <= '0';
elsif counterY = (spY+bpY+CONV_INTEGER(resY_i)+fpY) then
counterY <= (others => '0');
data <= (others => '0');
end if;
if counterX = 0 then
hsync_i <= '0';
hActive <= '0';
elsif counterX = spX then
hsync_i <= '1';
elsif counterX = (spX+bpX) then
hActive <= '1';
elsif counterX = (spX+bpX+CONV_INTEGER(resX_i)) then
hActive <= '0';
elsif counterX = (spX+bpX+CONV_INTEGER(resX_i)+fpX) then
counterX <= (others => '0');
counterY <= counterY +1;
counterX <= (others => '0');
end if;
-- Generate 8 coloured, equally-space, vertical bars
if vActive = '1' and hActive = '1' then
if counterX < (spX+bpX+barWidth) then
data <= colors(0);
elsif counterX < (spX+bpX+barWidth*2) then
data <= colors(1);
elsif counterX < (spX+bpX+barWidth*3) then
data <= colors(2);
elsif counterX < (spX+bpX+barWidth*4) then
data <= colors(3);
elsif counterX < (spX+bpX+barWidth*5) then
data <= colors(4);
elsif counterX < (spX+bpX+barWidth*6) then
data <= colors(5);
elsif counterX < (spX+bpX+barWidth*7) then
data <= colors(6);
else
data <= colors(7);
end if;
end if;
end if;
end process;
-- Frame Counter process to count 1 Second
-- Since we have 1024*768@60Hz, 1 second occurs after 60 VSYNC Pulses
frameCount: process(rst_n,vsync_i)
begin
if rst_n = '0' then
frameCounter <= (others => '0');
elsif rising_edge(vsync_i) then
frameCounter <= frameCounter + 1;
if frameCounter = "111011" then
secondTimeout <= '1';
frameCounter <= "000000";
else
secondTimeout <= '0';
end if;
end if;
end process;
-- Alternate color of bars every second. Next color is complement of previous color.
process(rst_n, secondTimeout)
begin
if rst_n = '0' then
color <= '0';
colors <= colors_1;
elsif rising_edge(secondTimeout) then
color <= color xor '1';
if color = '0' then
colors <= colors_1;
else
colors <= colors_2;
end if;
end if;
end process;
patternClk_com : patternClk
port map
(
CLK_IN1 => clk,
CLK_OUT1 => pclk_i);
end architecture;
| bsd-2-clause | 9e085d2b9f004fcc393d283164055b48 | 0.521641 | 3.191049 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_bus_concat.vhd | 4 | 1,505 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_bus_concat is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
b : in std_logic_vector(widthB-1 downto 0);
clock : in std_logic;
a : in std_logic_vector(widthA-1 downto 0);
aclr : in std_logic;
output : out std_logic_vector(widthA+widthB-1 downto 0)
);
end entity alt_dspbuilder_bus_concat;
architecture rtl of alt_dspbuilder_bus_concat is
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
a : in std_logic_vector(8-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector(8-1 downto 0);
clock : in std_logic;
output : out std_logic_vector(16-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
begin
alt_dspbuilder_bus_concat_GNIIOZRPJD_0: if ((WIDTHB = 8) and (WIDTHA = 8)) generate
inst_alt_dspbuilder_bus_concat_GNIIOZRPJD_0: alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map(WIDTHB => 8, WIDTHA => 8)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
assert not (((WIDTHB = 8) and (WIDTHA = 8)))
report "Please run generate again" severity error;
end architecture rtl;
| mit | b0a55eea8e8d8a060b10635983e9a205 | 0.703654 | 3.195329 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | AudioVideo_Init.vhd | 1 | 11,568 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo AudioVideo_Init.vhd
-- Versione 1.02 - 18.03.2013
-- **********************************************************
-- **********************************************************
-- Questo modulo si occupa del caricamento dati sui
-- registri di controllo Audio/Video della scheda dopo ogni
-- reset del sistema.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity AudioVideo_Init is generic (
MIN_ROM_ADDRESS: std_logic_vector(5 downto 0) := "000000"; --6'h00;
MAX_ROM_ADDRESS: std_logic_vector(5 downto 0) := "001010"; --6'h0A;
AUD_LINE_IN_LC: std_logic_vector(8 downto 0) := "000011000"; --9'd24;
AUD_LINE_IN_RC: std_logic_vector(8 downto 0) := "000011000"; --9'd24;
AUD_LINE_OUT_LC: std_logic_vector(8 downto 0) := "001110111"; --9'd119;
AUD_LINE_OUT_RC: std_logic_vector(8 downto 0) := "001110111"; --9'd119;
AUD_ADC_PATH: std_logic_vector(8 downto 0) := "000010001"; --9'd17;
AUD_DAC_PATH: std_logic_vector(8 downto 0) := "000000110"; --9'd6;
AUD_POWER: std_logic_vector(8 downto 0) := "000000000"; --9'h000;
AUD_DATA_FORMAT: std_logic_vector(8 downto 0) := "001001101"; --9'd77;
AUD_SAMPLE_CTRL: std_logic_vector(8 downto 0) := "000000000"; --9'd0;
AUD_SET_ACTIVE: std_logic_vector(8 downto 0) := "000000001" --9'h001;
);
port (
clk: in std_logic;
reset: in std_logic;
clear_error: in std_logic;
ack: in std_logic;
transfer_complete: in std_logic;
data_out: out std_logic_vector(7 downto 0);
transfer_data: buffer std_logic;
send_start_bit: out std_logic;
send_stop_bit: out std_logic;
auto_init_complete: out std_logic;
auto_init_error: out std_logic;
useMicInput: in std_logic
);
end AudioVideo_Init;
architecture behaviour of AudioVideo_Init is
-- Definizione stati della FSM per l'inizializzazione
constant AUTO_STATE_0_CHECK_STATUS: std_logic_vector(2 downto 0) := "000";
constant AUTO_STATE_1_SEND_START_BIT: std_logic_vector(2 downto 0) := "001";
constant AUTO_STATE_2_TRANSFER_BYTE_1: std_logic_vector(2 downto 0) := "010";
constant AUTO_STATE_3_TRANSFER_BYTE_2: std_logic_vector(2 downto 0) := "011";
constant AUTO_STATE_4_WAIT: std_logic_vector(2 downto 0) := "100";
constant AUTO_STATE_5_SEND_STOP_BIT: std_logic_vector(2 downto 0) := "101";
constant AUTO_STATE_6_INCREASE_COUNTER: std_logic_vector(2 downto 0) := "110";
constant AUTO_STATE_7_DONE: std_logic_vector(2 downto 0) := "111";
signal change_state: std_logic;
signal finished_auto_init: std_logic;
signal rom_address_counter: std_logic_vector(5 downto 0);
signal rom_data: std_logic_vector(25 downto 0);
signal ns_i2c_auto_init: std_logic_vector(2 downto 0);
signal s_i2c_auto_init: std_logic_vector(2 downto 0);
-- Segnale di buffer
signal rom_data_buff: std_logic_vector(27 downto 0);
begin
rom_data <= rom_data_buff(25 downto 0);
auto_init_complete <= '1' when (s_i2c_auto_init = AUTO_STATE_7_DONE) else '0';
change_state <= transfer_complete and transfer_data;
finished_auto_init <= '1' when (rom_address_counter = MAX_ROM_ADDRESS) else '0';
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
s_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
else
s_i2c_auto_init <= ns_i2c_auto_init;
end if;
end if;
end process;
process (all)
begin
ns_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
---------------------------------------------------------------------------------------------
------------------------------------------------------------------ FSM Inizializzazione Audio
---------------------------------------------------------------------------------------------
if (s_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS) then
if (finished_auto_init = '1') then
ns_i2c_auto_init <= AUTO_STATE_7_DONE;
elsif (rom_data(25) = '1') then
ns_i2c_auto_init <= AUTO_STATE_1_SEND_START_BIT;
else
ns_i2c_auto_init <= AUTO_STATE_3_TRANSFER_BYTE_2;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT) then
if (change_state = '1') then
ns_i2c_auto_init <= AUTO_STATE_2_TRANSFER_BYTE_1;
else
ns_i2c_auto_init <= AUTO_STATE_1_SEND_START_BIT;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_1) then
if (change_state = '1') then
ns_i2c_auto_init <= AUTO_STATE_3_TRANSFER_BYTE_2;
else
ns_i2c_auto_init <= AUTO_STATE_2_TRANSFER_BYTE_1;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2) then
if ((change_state = '1') and (rom_data(24) = '1')) then
ns_i2c_auto_init <= AUTO_STATE_4_WAIT;
elsif (change_state = '1') then
ns_i2c_auto_init <= AUTO_STATE_6_INCREASE_COUNTER;
else
ns_i2c_auto_init <= AUTO_STATE_3_TRANSFER_BYTE_2;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_4_WAIT) then
if (transfer_complete = '0') then
ns_i2c_auto_init <= AUTO_STATE_5_SEND_STOP_BIT;
else
ns_i2c_auto_init <= AUTO_STATE_4_WAIT;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT) then
if (transfer_complete = '1') then
ns_i2c_auto_init <= AUTO_STATE_6_INCREASE_COUNTER;
else
ns_i2c_auto_init <= AUTO_STATE_5_SEND_STOP_BIT;
end if;
elsif (s_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER) then
ns_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
elsif (s_i2c_auto_init = AUTO_STATE_7_DONE) then
ns_i2c_auto_init <= AUTO_STATE_7_DONE;
else
ns_i2c_auto_init <= AUTO_STATE_0_CHECK_STATUS;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
data_out <= "00000000";
elsif (s_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT) then
data_out <= rom_data(23 downto 16);
elsif (s_i2c_auto_init = AUTO_STATE_0_CHECK_STATUS) then
data_out <= rom_data(15 downto 8);
elsif (s_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_1) then
data_out <= rom_data(15 downto 8);
elsif (s_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2) then
data_out <= rom_data( 7 downto 0);
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
transfer_data <= '0';
elsif (transfer_complete = '1') then
transfer_data <= '0';
elsif (s_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT) then
transfer_data <= '1';
elsif (s_i2c_auto_init = AUTO_STATE_2_TRANSFER_BYTE_1) then
transfer_data <= '1';
elsif (s_i2c_auto_init = AUTO_STATE_3_TRANSFER_BYTE_2) then
transfer_data <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
send_start_bit <= '0';
elsif (transfer_complete = '1') then
send_start_bit <= '0';
elsif (s_i2c_auto_init = AUTO_STATE_1_SEND_START_BIT) then
send_start_bit <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
send_stop_bit <= '0';
elsif (transfer_complete = '1') then
send_stop_bit <= '0';
elsif (s_i2c_auto_init = AUTO_STATE_5_SEND_STOP_BIT) then
send_stop_bit <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
auto_init_error <= '0';
elsif (clear_error = '1') then
auto_init_error <= '0';
elsif ((s_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER) and ack='1') then
auto_init_error <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
rom_address_counter <= MIN_ROM_ADDRESS;
elsif (s_i2c_auto_init = AUTO_STATE_6_INCREASE_COUNTER) then
rom_address_counter <= rom_address_counter + "000001";
end if;
end if;
end process;
process (clk, reset, clear_error, ack, transfer_complete)
begin
case (rom_address_counter) is
-- Scrittura configurazione Audio: 7 bit di indirizzo + 9 bit di dati
-- Nota: i primi 2 bit sono usati per comodita' per portare a 28 i bit e usare valori esadecimali!
when "000000" => rom_data_buff <= "00" & "1100110100" & "0000000" & AUD_LINE_IN_LC;
when "000001" => rom_data_buff <= "00" & "1100110100" & "0000001" & AUD_LINE_IN_RC;
when "000010" => rom_data_buff <= "00" & "1100110100" & "0000010" & AUD_LINE_OUT_LC;
when "000011" => rom_data_buff <= "00" & "1100110100" & "0000011" & AUD_LINE_OUT_RC;
when "000100" => rom_data_buff <= ("00" & "1100110100" & "0000100" & AUD_ADC_PATH)
+ ("00" & "00000000000000000000000" & useMicInput & "00"); -- Microfono o Linein
when "000101" => rom_data_buff <= "00" & "1100110100" & "0000101" & AUD_DAC_PATH;
when "000110" => rom_data_buff <= "00" & "1100110100" & "0000110" & AUD_POWER;
when "000111" => rom_data_buff <= "00" & "1100110100" & "0000111" & AUD_DATA_FORMAT;
when "001000" => rom_data_buff <= "00" & "1100110100" & "0001000" & AUD_SAMPLE_CTRL;
when "001001" => rom_data_buff <= "00" & "1100110100" & "0001001" & AUD_SET_ACTIVE;
-- Scrittura configurazione Video
when "001010" => rom_data_buff <= X"3401500";
when "001011" => rom_data_buff <= X"3401741";
when "001100" => rom_data_buff <= X"3403a16";
when "001101" => rom_data_buff <= X"3405004";
when "001110" => rom_data_buff <= X"340c305";
when "001111" => rom_data_buff <= X"340c480";
when "010000" => rom_data_buff <= X"3400e80";
when "010001" => rom_data_buff <= X"3405020";
when "010010" => rom_data_buff <= X"3405218";
when "010011" => rom_data_buff <= X"34058ed";
when "010100" => rom_data_buff <= X"34077c5";
when "010101" => rom_data_buff <= X"3407c93";
when "010110" => rom_data_buff <= X"3407d00";
when "010111" => rom_data_buff <= X"340d048";
when "011000" => rom_data_buff <= X"340d5a0";
when "011001" => rom_data_buff <= X"340d7ea";
when "011010" => rom_data_buff <= X"340e43e";
when "011011" => rom_data_buff <= X"340ea0f";
when "011100" => rom_data_buff <= X"3403112";
when "011101" => rom_data_buff <= X"3403281";
when "011110" => rom_data_buff <= X"3403384";
when "011111" => rom_data_buff <= X"34037A0";
when "100000" => rom_data_buff <= X"340e580";
when "100001" => rom_data_buff <= X"340e603";
when "100010" => rom_data_buff <= X"340e785";
when "100011" => rom_data_buff <= X"3405000";
when "100100" => rom_data_buff <= X"3405100";
when "100101" => rom_data_buff <= X"3400070";
when "100110" => rom_data_buff <= X"3401010";
when "100111" => rom_data_buff <= X"3400482";
when "101000" => rom_data_buff <= X"3400860";
when "101001" => rom_data_buff <= X"3400a18";
when "101010" => rom_data_buff <= X"3401100";
when "101011" => rom_data_buff <= X"3402b00";
when "101100" => rom_data_buff <= X"3402c8c";
when "101101" => rom_data_buff <= X"3402df2";
when "101110" => rom_data_buff <= X"3402eee";
when "101111" => rom_data_buff <= X"3402ff4";
when "110000" => rom_data_buff <= X"34030d2";
when "110001" => rom_data_buff <= X"3400e05";
when others => rom_data_buff <= X"1000000";
end case;
end process;
end behaviour; | mit | 62ca2628759c2fd3c966fa35bb301489 | 0.589817 | 2.581567 | false | false | false | false |
Fju/LeafySan | src/vhdl/testbench/adc_model.vhdl | 1 | 4,121 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : ADC Model
-- Last update : 27.04.2015
-----------------------------------------------------------------
-- Libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity adc_model is
generic(
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
FULL_DEBUG : natural := 0;
FILE_NAME_PRELOAD : string := "adc_preload.txt"
);
port(
-- Global Signals
end_simulation : in std_ulogic;
-- SPI Signals
spi_clk : in std_ulogic;
spi_miso : out std_logic;
spi_cs_n : in std_ulogic;
-- Switch Signals
swt_select : in std_ulogic_vector(2 downto 0);
swt_enable_n : in std_ulogic
);
end entity adc_model;
architecture sim of adc_model is
file file_preload : text open read_mode is FILE_NAME_PRELOAD;
type adc_reg_t is array (0 to 7) of std_ulogic_vector(15 downto 0);
signal tx : std_ulogic_vector(15 downto 0);
signal swt_sel_lut : std_ulogic_vector(2 downto 0);
begin
process
variable adc_reg : adc_reg_t;
variable active_line, out_line : line;
variable cnt : natural := 0;
variable neol : boolean := false;
variable adc_val : real := 0.000;
begin
adc_reg := (others => (others => 'U'));
tx <= (others => 'U');
-- force wait for 1 ps to display full-debug messages after library warnings
if FULL_DEBUG = 1 then
wait for 1 ps;
end if;
-- preload data from adc file here...
while not endfile(file_preload) loop
readline(file_preload, active_line);
loop
read(active_line, adc_val, neol);
exit when not neol;
exit when cnt = 8;
adc_reg(cnt) := std_ulogic_vector(to_unsigned(integer(adc_val*real(4096)/real(3.3)), tx'length));
-- display read values from file
if FULL_DEBUG = 1 then
write(out_line, "[ADC] Preloading channel " & integer'image(cnt) & " with ");
write(out_line, adc_val, right, 3, 3);
write(out_line, 'V');
writeline(output, out_line);
end if;
cnt := cnt + 1;
end loop;
exit when cnt = 8;
end loop;
file_close(file_preload);
-- display unassigned channels
if FULL_DEBUG = 1 then
if cnt < 8 then
for i in cnt to 7 loop
write(out_line, "[ADC] Channel " & integer'image(i) & " is unassigned!");
writeline(output, out_line);
end loop;
end if;
end if;
-- do real work (send adc-values by request)
loop
exit when end_simulation = '1';
if spi_cs_n = '0' then
if swt_enable_n = '0' then
-- data has to be sent out shifted one bit to the left (as in actual chip)
tx <= adc_reg(to_integer(unsigned(swt_sel_lut)))(14 downto 0) & '0';
else
tx <= (others => 'U');
end if;
for i in 0 to 15 loop
wait until spi_clk = '1';
wait until spi_clk = '0';
tx <= tx(14 downto 0) & '0';
end loop;
wait until spi_cs_n = '1';
else
wait for SYSTEM_CYCLE_TIME;
end if;
end loop;
wait;
end process;
spi_miso <= '0' when tx(15) = '0' AND spi_cs_n = '0' else 'Z';
-- lut to map swt_select to correct register content (inverse to interface)
process(swt_select)
variable sel : natural;
begin
sel := to_integer(unsigned(swt_select));
case sel is
when 0 => swt_sel_lut <= std_ulogic_vector(to_unsigned(5, swt_sel_lut'length));
when 1 => swt_sel_lut <= std_ulogic_vector(to_unsigned(3, swt_sel_lut'length));
when 2 => swt_sel_lut <= std_ulogic_vector(to_unsigned(1, swt_sel_lut'length));
when 3 => swt_sel_lut <= std_ulogic_vector(to_unsigned(7, swt_sel_lut'length));
when 4 => swt_sel_lut <= std_ulogic_vector(to_unsigned(6, swt_sel_lut'length));
when 5 => swt_sel_lut <= std_ulogic_vector(to_unsigned(2, swt_sel_lut'length));
when 6 => swt_sel_lut <= std_ulogic_vector(to_unsigned(4, swt_sel_lut'length));
when 7 => swt_sel_lut <= std_ulogic_vector(to_unsigned(0, swt_sel_lut'length));
when others => swt_sel_lut <= std_ulogic_vector(to_unsigned(5, swt_sel_lut'length));
end case;
end process;
end architecture sim; | apache-2.0 | b63a46bbeb60ef990d70f68954cacf69 | 0.603494 | 2.914427 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/or/myOr2.vhdl | 1 | 721 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myOr2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end myOr2;
architecture behavioral of myOr2 is
-- component declaration
component myNot
port(a: in std_logic; s: out std_logic);
end component;
component myNand2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
-- signal declaration
signal not1_out: std_logic;
signal not2_out: std_logic;
begin
-- component instantiation and port mappping
myNot_1: myNot port map(a => a, s => not1_out);
myNot_2: myNot port map(a => b, s => not2_out);
myNand2_1: myNand2 port map(a => not1_out, b => not2_out, s => s);
end behavioral;
| mit | e0b156db35163399336b89d503295ac6 | 0.654646 | 2.991701 | false | false | false | false |
J-Rios/VHDL_Modules | 2.Secuencial/RAM_dedicated.vhd | 1 | 1,343 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity BLOCKRAM is
generic
(
B : NATURAL := 8; -- Address Bus width
W : NATURAL := 2 -- Data Bus width
);
port
(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
wr_en : in STD_LOGIC;
w_addr : in STD_LOGIC_VECTOR(W-1 downto 0);
r_addr : in STD_LOGIC_VECTOR(W-1 downto 0);
w_data : in STD_LOGIC_VECTOR(B-1 downto 0);
r_data : out STD_LOGIC_VECTOR(B-1 downto 0)
);
end BLOCKRAM;
-------------------------------------------------------------------------
architecture Behavioral of BLOCKRAM is
type REG_FILE_TYPE is array (2**W-1 downto 0) of STD_LOGIC_VECTOR (B-1 downto 0);
signal array_reg : REG_FILE_TYPE;
begin
-- Read-First Mode
process(clk)
begin
if (rising_edge(clk)) then
if (wr_en = '1') then
array_reg(to_integer(unsigned(w_addr))) <= w_data;
end if;
end if;
end process;
r_data <= array_reg(to_integer(unsigned(r_addr)));
-- Write-First Mode
--process(clk)
--begin
--if (rising_edge(clk)) then
--if (wr_en = '1') then
--array_reg(to_integer(unsigned(w_addr))) <= w_data;
--r_data <= w_data;
--else
--r_data <= array_reg(to_integer(unsigned(r_addr)));
--end if;
--end if;
--end process;
end Behavioral;
| gpl-3.0 | be2eb64f180ccf58bd99760c55ae48d5 | 0.553984 | 2.833333 | false | false | false | false |
gergoerdi/tinymicro-mos6502-kansas-lava | vhdl/TinyMicro6502.vhdl | 1 | 2,464 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.lava.all;
use work.all;
entity TinyMicro6502 is
port(CLK_32MHZ : in std_logic;
RESET : in std_logic;
VGA_VSYNC : out std_logic;
VGA_HSYNC : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0));
end entity TinyMicro6502;
architecture str of TinyMicro6502 is
signal CLK_40MHZ : std_logic;
signal CLK_1MHZ : std_logic;
signal MAIN_VRAM_WE : std_logic;
signal MAIN_VRAM_W_ADDR : std_logic_vector(9 downto 0);
signal MAIN_VRAM_W_DATA : std_logic_vector(3 downto 0);
signal VIDEO_VRAM_ADDR : std_logic_vector(9 downto 0);
signal VIDEO_VRAM_DATA : std_logic_vector(3 downto 0);
signal CLKDIV : std_logic_vector(5 downto 0) := (others => '0');
signal CLK_8KHZ : std_logic := '1';
begin
inst_clockman : entity work.clockman
port map (CLK_IN1 => CLK_32MHZ,
RESET => RESET,
CLK_OUT1 => CLK_40MHZ,
CLK_OUT2 => CLK_1MHZ);
proc_CLK_8KHZ: process(CLK_1MHZ,RESET) is
begin
if RESET = '1' then
CLKDIV <= (others => '0');
CLK_8KHZ <= '1';
elsif rising_edge(CLK_1MHZ) then
CLKDIV <= std_logic_vector(unsigned(CLKDIV) + 1);
if CLKDIV = "000000" then
CLK_8KHZ <= not CLK_8KHZ;
end if;
end if;
end process proc_CLK_8KHZ;
inst_MainBoard : entity work.MainBoard
port map (CLK_CPU => CLK_8KHZ,
RESET => RESET,
VIDEO_WE => MAIN_VRAM_WE,
VIDEO_W_ADDR => MAIN_VRAM_W_ADDR,
VIDEO_W_DATA => MAIN_VRAM_W_DATA);
inst_vram : entity work.bram_tdp
port map (a_clk => CLK_8KHZ,
a_wr => MAIN_VRAM_WE,
a_addr => MAIN_VRAM_W_ADDR,
a_din => MAIN_VRAM_W_DATA,
a_dout => open,
b_clk => CLK_40MHZ,
b_wr => '0',
b_addr => VIDEO_VRAM_ADDR,
b_din => (others => '0'),
b_dout => VIDEO_VRAM_DATA);
inst_video : entity work.Video
port map (CLK_40MHZ => CLK_40MHZ,
RESET => RESET,
VIDEO_R_DATA => VIDEO_VRAM_DATA,
VIDEO_R_ADDR => VIDEO_VRAM_ADDR,
VGA_VSYNC => VGA_VSYNC,
VGA_HSYNC => VGA_HSYNC,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B);
end architecture str;
| gpl-2.0 | 6ee761755e8507a1fe594bfa4ed7e5f2 | 0.553977 | 3.237845 | false | false | false | false |
J-Rios/VHDL_Modules | 3.Peripherals/UART/UART_Tx.vhd | 1 | 2,603 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity UART_TX is
Generic
(
DBIT : integer := 8; -- # Data BITS
SB_TICK : integer := 16 -- # Stop BITS Tick (1 -> 16, 1.5 -> 24, 2 -> 32)
);
Port
(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
TX_START : in STD_LOGIC;
S_TICK : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR (7 downto 0);
TX_DONE_TICK : out STD_LOGIC;
TX : out STD_LOGIC
);
end UART_TX;
-------------------------------------------------------------------------
architecture Behavioral of UART_TX is
type state_type is (idle, start, data, stop);
signal state_reg, state_next: state_type;
signal s_reg, s_next: unsigned(3 downto 0);
signal n_reg, n_next: unsigned(2 downto 0);
signal b_reg, b_next: std_logic_vector(7 downto 0);
signal TX_reg, TX_next: std_logic;
begin
-- FSMD state & data registers
process(CLK,RESET)
begin
if RESET='1' then
state_reg <= idle;
s_reg <= (others=>'0');
n_reg <= (others=>'0');
b_reg <= (others=>'0');
TX_reg <= '1';
elsif (CLK'event and CLK='1') then
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
TX_reg <= TX_next;
end if;
end process;
-- Next-state logic & data path functional units/routing
process(state_reg,s_reg,n_reg,b_reg,S_TICK, TX_reg,TX_START,DIN)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
TX_next <= TX_reg;
TX_DONE_TICK <= '0';
case state_reg is
when idle =>
TX_next <= '1';
if TX_START='1' then
state_next <= start;
s_next <= (others=>'0');
b_next <= DIN;
end if;
when start =>
TX_next <= '0';
if (S_TICK = '1') then
if s_reg=15 then
state_next <= data;
s_next <= (others=>'0');
n_next <= (others=>'0');
else
s_next <= s_reg + 1;
end if;
end if;
when data =>
TX_next <= b_reg(0);
if (S_TICK = '1') then
if s_reg=15 then
s_next <= (others=>'0');
b_next <= '0' & b_reg(7 downto 1);
if n_reg=(DBIT-1) then
state_next <= stop;
else
n_next <= n_reg + 1;
end if;
else
s_next <= s_reg + 1;
end if;
end if;
when stop =>
TX_next <= '1';
if (S_TICK = '1') then
if s_reg=(SB_TICK-1) then
state_next <= idle;
TX_DONE_TICK <= '1';
else
s_next <= s_reg + 1;
end if;
end if;
end case;
end process;
TX <= TX_reg;
end Behavioral;
| gpl-3.0 | 1525da67625e6401845594592cb4c146 | 0.502113 | 2.737119 | false | false | false | false |
Fju/LeafySan | src/vhdl/modules/adc_sensors.vhdl | 1 | 5,466 | ----------------------------------------------------------------------
-- Project : LeafySan
-- Module : ADC Sensor Module
-- Authors : Florian Winkler
-- Lust update : 01.09.2017
-- Description : Reads voltage of analogue sensors through ADC's and converts them into unit dependent digital values
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity adc_sensors is
port(
clock : in std_ulogic;
reset : in std_ulogic;
temperature : out unsigned(11 downto 0);
carbondioxide : out unsigned(13 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0)
);
end adc_sensors;
architecture rtl of adc_sensors is
constant READ_CLOCK_COUNT : natural := 1953125; -- 39,0625ms (5s / 128)
constant READ_ITEM_COUNT : natural := 128;
constant ADC_RESOLUTION : natural := 12; -- 12 bit
type adc_state_t is (S_ADC_INIT, S_ADC_WAIT, S_ADC_READ_TEMP, S_ADC_READ_CO2);
signal adc_state, adc_state_nxt : adc_state_t;
signal adc_clock, adc_clock_nxt : unsigned(to_log2(READ_CLOCK_COUNT) - 1 downto 0);
signal temp_value, temp_value_nxt : std_ulogic_vector(29 downto 0);
signal temp_sum, temp_sum_nxt : unsigned(ADC_RESOLUTION + to_log2(READ_ITEM_COUNT + 1) - 1 downto 0);
signal temp_cnt, temp_cnt_nxt : unsigned(to_log2(READ_ITEM_COUNT + 1) - 1 downto 0);
signal co2_value, co2_value_nxt : std_ulogic_vector(26 downto 0);
signal co2_sum, co2_sum_nxt : unsigned(ADC_RESOLUTION + to_log2(READ_ITEM_COUNT + 1) - 1 downto 0);
signal co2_cnt, co2_cnt_nxt : unsigned(to_log2(READ_ITEM_COUNT + 1) - 1 downto 0);
signal temp, temp_nxt : unsigned(11 downto 0);
signal co2, co2_nxt : unsigned(13 downto 0);
begin
-- sequential process
process(clock, reset)
begin
if reset = '1' then
adc_state <= S_ADC_INIT;
adc_clock <= (others => '0');
temp_value <= (others => '0');
temp_sum <= (others => '0');
temp_cnt <= (others => '0');
co2_value <= (others => '0');
co2_sum <= (others => '0');
co2_cnt <= (others => '0');
temp <= (others => '0');
co2 <= (others => '0');
elsif rising_edge(clock) then
adc_state <= adc_state_nxt;
adc_clock <= adc_clock_nxt;
temp_value <= temp_value_nxt;
temp_cnt <= temp_cnt_nxt;
temp_sum <= temp_sum_nxt;
co2_value <= co2_value_nxt;
co2_cnt <= co2_cnt_nxt;
co2_sum <= co2_sum_nxt;
temp <= temp_nxt;
co2 <= co2_nxt;
end if;
end process;
process(co2, temp, adc_state, adc_clock, temp_value, temp_cnt, temp_sum, co2_value, co2_sum, co2_cnt, adc_dac_din)
begin
-- hold previous values by default
adc_state_nxt <= adc_state;
adc_clock_nxt <= adc_clock;
temp_value_nxt <= temp_value;
temp_cnt_nxt <= temp_cnt;
temp_sum_nxt <= temp_sum;
co2_value_nxt <= co2_value;
co2_cnt_nxt <= co2_cnt;
co2_sum_nxt <= co2_sum;
temp_nxt <= temp;
co2_nxt <= co2;
-- default assignments for the DAC/ADC module
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
temperature <= temp;
carbondioxide <= co2;
case adc_state is
when S_ADC_INIT =>
-- activate ADC channels
adc_dac_cs <= '1';
adc_dac_wr <= '1';
adc_dac_addr <= CV_ADDR_ADC_DAC_CTRL;
adc_dac_dout(9 downto 0) <= "0011111111";
-- next state
adc_state_nxt <= S_ADC_WAIT;
when S_ADC_WAIT =>
adc_clock_nxt <= adc_clock + to_unsigned(1, adc_clock'length);
if adc_clock = to_unsigned(READ_CLOCK_COUNT - 1, adc_clock'length) then
-- switch state after 50 million clocks (1s @ speed = 1)
adc_clock_nxt <= (others => '0');
adc_state_nxt <= S_ADC_READ_TEMP;
temp_nxt <= resize(shift_right(unsigned(temp_value) * 74043 + 131072, 18), temp'length);
co2_nxt <= resize(shift_right((unsigned(co2_value) - 496) * 82539, 15), co2'length);
end if;
when S_ADC_READ_TEMP =>
adc_dac_cs <= '1';
adc_dac_wr <= '0';
adc_dac_addr(3 downto 0) <= CV_ADDR_ADC0;
temp_cnt_nxt <= temp_cnt + to_unsigned(1, temp_cnt'length);
temp_sum_nxt <= temp_sum + resize(unsigned(adc_dac_din(11 downto 0)), temp_sum'length);
if temp_cnt = to_unsigned(READ_ITEM_COUNT - 1, temp_cnt'length) then
temp_value_nxt <= std_ulogic_vector(resize(shift_right(temp_sum, to_log2(READ_ITEM_COUNT)), temp_value'length));
temp_cnt_nxt <= (others => '0');
temp_sum_nxt <= (others => '0');
end if;
adc_state_nxt <= S_ADC_READ_CO2;
when S_ADC_READ_CO2 =>
adc_dac_cs <= '1';
adc_dac_wr <= '0';
adc_dac_addr(3 downto 0) <= CV_ADDR_ADC1;
co2_cnt_nxt <= co2_cnt + to_unsigned(1, co2_cnt'length);
co2_sum_nxt <= co2_sum + resize(unsigned(adc_dac_din(11 downto 0)), co2_sum'length);
if co2_cnt = to_unsigned(READ_ITEM_COUNT - 1, co2_cnt'length) then
co2_value_nxt <= std_ulogic_vector(resize(shift_right(co2_sum, to_log2(READ_ITEM_COUNT)), co2_value'length));
co2_cnt_nxt <= (others => '0');
co2_sum_nxt <= (others => '0');
end if;
adc_state_nxt <= S_ADC_WAIT;
end case;
end process;
end rtl;
| apache-2.0 | b0d787c4a1997f188caf8ff9e1c5dc3b | 0.596597 | 2.605338 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Controllori_Video/VGA_Adapter.vhd | 1 | 10,302 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo VGA_Adapter.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Modulo trovato in rete, convertito da Verilog a VHDL
-- e successivamente adattato al progetto.
-- Ho utilizzato la risoluzione 320x240 monocromatica.
-- Occupazione totale di memoria: 76800 bit.
-- **********************************************************
--VGA Adapter
------------------
--
--This is an implementation of a VGA Adapter. The adapter uses VGA mode signalling to initiate
--a 640x480 resolution mode on a computer monitor, with a refresh rate of approximately 60Hz.
--It is designed for easy use in an early digital logic design course to facilitate student
--projects on the Altera DE1 Educational board.
--
--This implementation of the VGA adapter can display images of varying colour depth at a resolution of
--320x240 or 160x120 superpixels. The concept of superpixels is introduced to reduce the amount of on-chip
--memory used by the adapter. The following table shows the number of bits of on-chip memory used by
--the adapter in various resolutions and colour depths.
--
---------------------------------------------------------------------------------------------------------------------------------
--Resolution | Mono | 8 colours | 64 colours | 512 colours | 4096 colours | 32768 colours | 262144 colours | 2097152 colours |
---------------------------------------------------------------------------------------------------------------------------------
--160x120 | 19200 | 57600 | 115200 | 172800 | 230400 | 288000 | 345600 | 403200 |
--320x240 | 78600 | 230400 | ############## Does not fit ############################################################## |
---------------------------------------------------------------------------------------------------------------------------------
--
--By default the adapter works at the resolution of 320x240 with 8 colours. To set the adapter in any of
--the other modes, the adapter must be instantiated with specific parameters. These parameters are:
--- RESOLUTION - a string that should be either "320x240" or "160x120".
--- MONOCHROME - a string that should be "TRUE" if you only want black and white colours, and "FALSE"
-- otherwise.
--- BITS_PER_COLOUR_CHANNEL - an integer specifying how many bits are available to describe each colour
-- (R,G,B). A default value of 1 indicates that 1 bit will be used for red
-- channel, 1 for green channel and 1 for blue channel. This allows 8 colours
-- to be used.
--
--In addition to the above parameters, a BACKGROUND_IMAGE parameter can be specified. The parameter
--refers to a memory initilization file (MIF) which contains the initial contents of video memory.
--By specifying the initial contents of the memory we can force the adapter to initially display an
--image of our choice. Please note that the image described by the BACKGROUND_IMAGE file will only
--be valid right after your program the DE2 board. If your circuit draws a single pixel on the screen,
--the video memory will be altered and screen contents will be changed. In order to restore the background
--image your circuti will have to redraw the background image pixel by pixel, or you will have to
--reprogram the DE2 board, thus allowing the video memory to be rewritten.
--
--To use the module connect the vga_adapter to your circuit. Your circuit should produce a value for
--inputs X, Y and plot. When plot is high, at the next positive edge of the input clock the vga_adapter
--will change the contents of the video memory for the pixel at location (X,Y). At the next redraw
--cycle the VGA controller will update the contants of the screen by reading the video memory and copying
--it over to the screen. Since the monitor screen has no memory, the VGA controller has to copy the
--contents of the video memory to the screen once every 60th of a second to keep the image stable. Thus,
--the video memory should not be used for other purposes as it may interfere with the operation of the
--VGA Adapter.
--
--As a final note, ensure that the following conditions are met when using this module:
--1. You are implementing the the VGA Adapter on the Altera DE2 board. Using another board may change
-- the amount of memory you can use, the clock generation mechanism, as well as pin assignments required
-- to properly drive the VGA digital-to-analog converter.
--2. Outputs VGA_* should exist in your top level design. They should be assigned pin locations on the
-- Altera DE2 board as specified by the DE2_pin_assignments.csv file.
--3. The input clock must have a frequency of 50 MHz with a 50% duty cycle. On the Altera DE2 board
-- PIN_N2 is the source for the 50MHz clock.
--
--During compilation with Quartus II you may receive the following warnings:
--- Warning: Variable or input pin "clocken1" is defined but never used
--- Warning: Pin "VGA_SYNC" stuck at VCC
--- Warning: Found xx output pins without output pin load capacitance assignment
--These warnings can be ignored. The first warning is generated, because the software generated
--memory module contains an input called "clocken1" and it does not drive logic. The second warning
--indicates that the VGA_SYNC signal is always high. This is intentional. The final warning is
--generated for the purposes of power analysis. It will persist unless the output pins are assigned
--output capacitance. Leaving the capacitance values at 0 pf did not affect the operation of the module.
--
--If you see any other warnings relating to the vga_adapter, be sure to examine them carefully. They may
--cause your circuit to malfunction.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library Altera_mf;
use altera_mf.altera_mf_components.all;
entity VGA_Adapter is port(
resetn: in std_logic;
clock: in std_logic;
clock_25: in std_logic;
colour: in std_logic;
x: in std_logic_vector(8 downto 0); -- Coordinata x
y: in std_logic_vector(7 downto 0); -- Coordinata y
plot: in std_logic; -- Quando e'=1, il pixel (x,y) cambierà' colore (bisogna plottare)
-- Segnali per il DAC per pilotare il monitor.
VGA_R: out std_logic_vector(9 downto 0);
VGA_G: out std_logic_vector(9 downto 0);
VGA_B: out std_logic_vector(9 downto 0);
VGA_HS: out std_logic;
VGA_VS: out std_logic;
VGA_BLANK: out std_logic;
VGA_SYNC: out std_logic
);
end VGA_Adapter;
architecture behaviour of VGA_Adapter is
component VGA_CalcoloIndirizzo is port (
x : in std_logic_vector(8 downto 0);
y : in std_logic_vector(7 downto 0);
mem_address : out std_logic_vector(16 downto 0)
);
end component;
component VGA_Controller is port(
vga_clock: in std_logic;
resetn: in std_logic;
pixel_colour: in std_logic_vector(0 downto 0);
memory_address: out std_logic_vector(16 downto 0);
VGA_R: out std_logic_vector(9 downto 0) register;
VGA_G: out std_logic_vector(9 downto 0) register;
VGA_B: out std_logic_vector(9 downto 0) register;
VGA_HS: out std_logic register;
VGA_VS: out std_logic register;
VGA_BLANK: out std_logic register;
VGA_SYNC: out std_logic -- VGA sync e' sempre a 1.
);
end component;
signal valid_320x240: std_logic; -- Serve a specificare che le coordinate siano in un range valido.
signal writeEn: std_logic; -- Serve ad abilitare la scrittura della memoria video d un certo pixcel (x,y)
signal to_ctrl_colour: std_logic; -- Pixel letto dal controller VGA
signal user_to_video_memory_addr: std_logic_vector(16 downto 0); -- Indirizzo di memoria per scrivere le coordnate (x,y)
signal controller_to_video_memory_addr: std_logic_vector(16 downto 0); -- Indirizzo di memoria per leggere le coordnate (x,y)
signal vcc: std_logic := '1'; -- Serve al VGA Adapter
signal gnd: std_logic := '0'; -- Serve al VGA Adapter
begin
-- Controllo validita' coordinate
valid_320x240 <= '1' when (
(x >= "000000000")
and (x < "101000000") -- x < 320
and (y >= "00000000")
and (y < "11110000")); -- y < 240
-- Controllo abilitazione scrittura
writeEn <= '1' when (plot='1') and (valid_320x240='1') else '0';
-- Converte le coordinate in un indirizzo di memoria
CoordinatesTranslator : VGA_CalcoloIndirizzo port map(
x => x,
y => y,
mem_address => user_to_video_memory_addr
);
-- Allocazione memoria video
VideoMemory : altsyncram
generic map (
WIDTH_A => 1,
WIDTH_B => 1,
INTENDED_DEVICE_FAMILY => "Cyclone II",
OPERATION_MODE => "DUAL_PORT",
WIDTHAD_A => 17,
NUMWORDS_A => 76800,
WIDTHAD_B => 17,
NUMWORDS_B => 76800,
OUTDATA_REG_B => "CLOCK1",
ADDRESS_REG_B => "CLOCK1",
CLOCK_ENABLE_INPUT_A => "BYPASS",
CLOCK_ENABLE_INPUT_B => "BYPASS",
CLOCK_ENABLE_OUTPUT_B => "BYPASS",
POWER_UP_UNINITIALIZED => "FALSE"
)
port map (
wren_a => writeEn,
wren_b => gnd,
clock0 => clock, -- write clock
clock1 => clock_25, -- read clock
clocken0 => vcc, -- write enable clock
clocken1 => vcc, -- read enable clock
address_a => user_to_video_memory_addr,
address_b => controller_to_video_memory_addr,
data_a(0) => colour, -- data in
q_b(0) => to_ctrl_colour -- data out
);
-- Istanza del controller VGA
VGAcontroller : VGA_Controller port map (
vga_clock => clock_25,
resetn => resetn,
pixel_colour(0) => to_ctrl_colour,
memory_address => controller_to_video_memory_addr,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_BLANK => VGA_BLANK,
VGA_SYNC => VGA_SYNC
);
end behaviour; | mit | 2d5645d66309347d70baac8a9ffe4fba | 0.631431 | 3.585799 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sim_1/fpbaseconv_tb.vhd | 1 | 1,331 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fpbaseconv_tb is
end fpbaseconv_tb;
architecture Behavioral of fpbaseconv_tb is
constant clk_period : time := 10 ns;
signal clk : std_logic := '0';
signal rst : std_logic;
constant precision : integer := 17;
constant exp_precision : integer := 8;
constant nscalestages : integer := 7;
signal scaling : signed(nscalestages-1 downto 0);
signal ratio : unsigned(precision-1 downto 0);
signal strobe : std_logic := '0';
begin
clk <= not clk after clk_period/2;
stim : process
begin
rst <= '1';
wait for clk_period * 10;
rst <= '0';
wait for clk_period;
scaling <= to_signed(-19, scaling'length);
-- ratio <= '1' & x"797D";
ratio <= '1' & x"7981";
wait for clk_period;
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait;
end process;
dut : entity work.fpbaseconv
generic map (
precision => precision,
exp_precision => exp_precision,
nscalestages => nscalestages )
port map (
mantissa => open,
exponent => open,
busy => open,
scaling => scaling,
ratio => ratio,
strobe => strobe,
clk => clk,
rst => rst );
end Behavioral;
| mit | c595bbe88dc3b99f54c319e759e7b42c | 0.572502 | 3.549333 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Utils/BinaryToBcd.vhd | 1 | 2,634 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo BinaryToBcd.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Questo modulo converte un numero binario in BCD per
-- visualizzare numer decimali sul display a 7 segmenti.
-- Utilizza l'algoritmo "Shift and Add-3"
-- 1. Shift a sinistra del numero binario.
-- 2. Dopo 8 shift, il numero BCD e' nel formato centinaia, decine, unita'
-- 3. Se il valore binario dei BCD e' > 4, aggiunge 3 al valore.
-- 4. Vai a 1.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
entity BinaryToBcd is port (
A: in std_logic_vector(7 downto 0);
ONES: out std_logic_vector(3 downto 0);
TENS: out std_logic_vector(3 downto 0);
HUNDREDS: out std_logic_vector(1 downto 0));
end BinaryToBcd;
architecture behaviour OF BinaryToBcd IS
component Add3 is port (
signal s_i: in std_logic_vector(3 downto 0);
signal s_o: out std_logic_vector(3 downto 0)
);
end component;
signal c1 : std_logic_vector(3 downto 0);
signal c2 : std_logic_vector(3 downto 0);
signal c3 : std_logic_vector(3 downto 0);
signal c4 : std_logic_vector(3 downto 0);
signal c5 : std_logic_vector(3 downto 0);
signal c6 : std_logic_vector(3 downto 0);
signal c7 : std_logic_vector(3 downto 0);
signal d1 : std_logic_vector(3 downto 0);
signal d2 : std_logic_vector(3 downto 0);
signal d3 : std_logic_vector(3 downto 0);
signal d4 : std_logic_vector(3 downto 0);
signal d5 : std_logic_vector(3 downto 0);
signal d6 : std_logic_vector(3 downto 0);
signal d7 : std_logic_vector(3 downto 0);
BEGIN
d1 <= '0' & A(7 DOWNTO 5);
d2 <= c1(2 DOWNTO 0) & A(4);
d3 <= c2(2 DOWNTO 0) & A(3);
d4 <= c3(2 DOWNTO 0) & A(2);
d5 <= c4(2 DOWNTO 0) & A(1);
d6 <= '0' & c1(3) & c2(3) & c3(3);
d7 <= c6(2 DOWNTO 0) & c4(3);
ONES <= c5(2 DOWNTO 0) & A(0);
TENS <= c7(2 DOWNTO 0) & c5(3);
HUNDREDS <= c6(3) & c7(3);
m1 : add3 port map ( d1, c1);
m2 : add3 port map ( d2, c2);
m3 : add3 port map ( d3, c3);
m4 : add3 port map ( d4, c4);
m5 : add3 port map ( d5, c5);
m6 : add3 port map ( d6, c6);
m7 : add3 port map ( d7, c7);
END behaviour; | mit | 1699bae99ebed3ae692e3a0350038108 | 0.520501 | 3.020642 | false | false | false | false |
Fju/LeafySan | src/vhdl/testbench/sram_model.vhdl | 1 | 4,825 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : SRAM-Model (a very very very simple model) for Simulation
-- Last update : 02.12.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.iac_pkg.all;
entity sram_model is
generic(
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
FULL_DEBUG : natural := 0;
-- file for preload of sram
FILE_NAME_PRELOAD : string := "preload.txt";
-- file for dump at end of simulation
FILE_NAME_DUMP : string := "dump.txt";
-- number of addressable words in sram (size of sram)
GV_SRAM_SIZE : natural := 2**20
);
port(
-- global signals
end_simulation : in std_ulogic;
-- sram connections
sram_ce_n : in std_ulogic;
sram_oe_n : in std_ulogic;
sram_we_n : in std_ulogic;
sram_ub_n : in std_ulogic;
sram_lb_n : in std_ulogic;
sram_addr : in std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0)
);
end sram_model;
architecture sim of sram_model is
constant DUMP_WORDS_PER_LINE : natural := 8;
-- files
file file_preload : text open read_mode is FILE_NAME_PRELOAD;
file file_dump : text open write_mode is FILE_NAME_DUMP;
-- internal representation of sram (data-array)
type sram_data_t is array (0 to GV_SRAM_SIZE-1) of std_ulogic_vector(sram_dq'length-1 downto 0);
signal sram_data : sram_data_t;
begin
-- set outgoing signals
sram_dq <= std_logic_vector(sram_data(to_integer(unsigned(sram_addr)))) when (sram_ce_n = '0' and sram_we_n = '1') else
(others => 'Z');
process
variable active_line : line;
variable neol : boolean := false;
variable data_value : integer := 0;
variable cnt : natural := 0;
begin
-- preload data from file
-- prefill array with undefined
sram_data <= (others => (others => 'U'));
-- read preload file
while not endfile(file_preload) loop
-- read line
readline(file_preload, active_line);
-- loop until end of line
loop
-- read integer from line
read(active_line, data_value, neol);
-- exit when line has ended
exit when not neol;
-- chancel when sram is already full
exit when cnt = GV_SRAM_SIZE-1;
-- write data to array
sram_data(cnt) <= std_ulogic_vector(to_signed(data_value, sram_dq'length));
-- increment counter
cnt := cnt + 1;
end loop;
end loop;
file_close(file_preload);
loop
-- stop when simulation has ended
exit when end_simulation = '1';
-- chip enable detected
if sram_ce_n = '0' then
-- write (read outside the process)
if sram_we_n = '0' then
-- write data to array
sram_data(to_integer(unsigned(sram_addr))) <= std_ulogic_vector(sram_dq);
if FULL_DEBUG = 1 then
write(active_line, string'("[SRAM] Write "));
write(active_line, to_integer(unsigned(sram_dq)));
write(active_line, string'(" ("));
write(active_line, to_bitvector(sram_dq));
write(active_line, string'(") to Addr "));
write(active_line, to_integer(unsigned(sram_addr)));
write(active_line, string'("."));
writeline(output, active_line);
end if;
-- read
else
if FULL_DEBUG = 1 then
write(active_line, string'("[SRAM] Read "));
write(active_line, to_integer(unsigned(sram_data(to_integer(unsigned(sram_addr))))));
write(active_line, string'(" ("));
write(active_line, to_bitvector(sram_data(to_integer(unsigned(sram_addr)))));
write(active_line, string'(") from Addr "));
write(active_line, to_integer(unsigned(sram_addr)));
write(active_line, string'("."));
writeline(output, active_line);
end if;
end if;
end if;
-- wait for one cycle
wait for SYSTEM_CYCLE_TIME;
end loop;
-- dump data to file after simulation was ended
-- loop over sram-size, with 4 words per line
for i in 0 to (GV_SRAM_SIZE/DUMP_WORDS_PER_LINE)-1 loop
--write(active_line, hex(std_ulogic_vector(to_unsigned(i*DUMP_WORDS_PER_LINE,to_log16(GV_SRAM_SIZE)*4))) & ": ");
for j in 0 to DUMP_WORDS_PER_LINE-1 loop
--write(active_line, hex(sram_data(i*DUMP_WORDS_PER_LINE+j)));
if j /= DUMP_WORDS_PER_LINE-1 then
if (((j+1) mod 4) = 0) then
write(active_line, string'(" "));
else
write(active_line, string'(" "));
end if;
end if;
end loop;
writeline(file_dump, active_line);
end loop;
file_close(file_dump);
-- wait forever
wait;
end process;
end sim;
| apache-2.0 | 401cf1aa085425cb38d743ce6a62747a | 0.58943 | 3.182718 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sources_1/main.vhd | 1 | 5,197 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity main is
Port (
dispc : out std_logic_vector(7 downto 0);
dispa : out std_logic_vector(3 downto 0);
btn : in std_logic_vector(4 downto 1);
led : out std_logic_vector(7 downto 0);
OLED_VDD : out std_logic;
OLED_BAT : out std_logic;
OLED_RST : out std_logic;
OLED_CS : out std_logic;
OLED_SCK : out std_logic;
OLED_MOSI : out std_logic;
OLED_CD : out std_logic;
clk : in std_logic;
rst : in std_logic );
end main;
architecture Behavioral of main is
signal input, clk2 : std_logic;
signal divoverflow : std_logic;
signal final : unsigned(16 downto 0);
signal order, orderlatch : signed(7 downto 0);
constant bcdprecision : integer := 20;
signal bcd, bcdlatch : std_logic_vector(bcdprecision-1 downto 0);
signal dispen : std_logic_vector(3 downto 0);
signal data : std_logic_vector(15 downto 0);
signal tiledata : std_logic_vector(15 downto 0);
signal tileaddr : std_logic_vector(9 downto 0);
signal tilewen : std_logic;
signal digit : unsigned(3 downto 0);
begin
fc : entity work.mwfc
generic map (
precision => final'length,
bcdprecision => bcd'length )
port map (
rawfrq => final,
bcdfrq => bcd,
ord => order,
overflow => divoverflow,
clk => clk,
clk2 => clk2,
rst => rst );
led <= std_logic_vector(order);
dispen <= "1111" when divoverflow = '0' else "0000";
data <= bcd(bcd'high downto bcd'high - 15);
disp : entity work.driveseg
port map (
data => data,
seg_c => dispc,
seg_a => dispa,
en => dispen,
clk => clk,
rst => rst );
gpu : entity work.otile
port map (
clk => clk,
rst => rst,
data => tiledata,
addr => tileaddr,
wen => tilewen,
OLED_VDD => OLED_VDD,
OLED_BAT => OLED_BAT,
OLED_RST => OLED_RST,
OLED_CS => OLED_CS,
OLED_SCK => OLED_SCK,
OLED_MOSI => OLED_MOSI,
OLED_CD => OLED_CD );
-- Increment digit on every clock tic
process(clk)
variable div : unsigned(22 downto 0);
begin
if rising_edge(clk) then
digit <= digit + "1";
if div = "0" then
bcdlatch <= bcd;
orderlatch <= order;
end if;
div := div + "1";
end if;
end process;
-- Set the data depending on the digit
process(digit, orderlatch, bcdlatch)
variable place : signed(order'range);
variable sdigit : signed(digit'length downto digit'low);
constant bcddigits : integer := bcdprecision / 4;
variable diff : integer;
begin
sdigit := signed("0" & std_logic_vector(digit));
-- The counter 'digit' includes the thousands separators, so compute
-- the actual order of the digit currently being displayed
case digit(3 downto 2) is
-- digit = 0 corresponds to 100 MHz, so the 8th place
when "00" => place := to_signed(8, place'length) - sdigit;
when "01" => place := to_signed(9, place'length) - sdigit;
when "10" => place := to_signed(10, place'length) - sdigit;
when "11" => place := to_signed(11, place'length) - sdigit;
when others => place := (others => '0');
end case;
if digit = x"3" then
if orderlatch > to_signed(6 - bcddigits, order'length) then
tiledata <= x"002c";
else
tiledata <= x"0020";
end if;
elsif digit = x"7" then
if orderlatch > to_signed(3 - bcddigits, order'length) then
tiledata <= x"002c";
else
tiledata <= x"0020";
end if;
elsif digit = x"b" then
tiledata <= x"002e";
elsif digit = x"f" then
tiledata <= x"0020";
elsif place < orderlatch then
tiledata <= x"0030";
elsif place > (orderlatch + to_signed(bcddigits-1, order'length)) then
tiledata <= x"0020";
else
diff := to_integer(place - orderlatch);
assert diff >= 0 report "diff should always be > 0" severity error;
assert diff < bcddigits report "diff should not exceed the number of bcd digits" severity error;
tiledata <= x"000" & bcdlatch(4*diff + 3 downto 4*diff);
end if;
end process;
tilewen <= '1';
tileaddr <= "00" & x"6" & std_logic_vector(digit);
inclk : BUFG port map ( O => clk2, I => input );
-- Input test signal: divides clk by 2 * (2 + btn)
clkdiv : process(clk,rst)
variable count : unsigned(10 downto 0);
variable half : unsigned(count'range);
begin
if rising_edge(clk) then
half := to_unsigned(2, half'length) + unsigned(btn & "000");
if count = half - "1" then
input <= '1';
elsif count = shift_left(half,1) - "1" then
input <= '0';
end if;
if rst = '1' then
count := (others => '0');
elsif count = shift_left(half,1) - "1" then
count := (others => '0');
else
count := count + "1";
end if;
end if;
end process;
end Behavioral;
| mit | fd5ab7c88affd5ac4a9547848dce6411 | 0.569752 | 3.381262 | false | false | false | false |
gergoerdi/tinymicro-mos6502-kansas-lava | vhdl/DualRAM.vhdl | 2 | 1,453 | -- http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
-- A parameterized, inferable, true dual-port, dual-clock block RAM in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bram_tdp is
generic (
DATA : integer := 4;
ADDR : integer := 10
);
port (
-- Port A
a_clk : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR-1 downto 0);
a_din : in std_logic_vector(DATA-1 downto 0);
a_dout : out std_logic_vector(DATA-1 downto 0);
-- Port B
b_clk : in std_logic;
b_wr : in std_logic;
b_addr : in std_logic_vector(ADDR-1 downto 0);
b_din : in std_logic_vector(DATA-1 downto 0);
b_dout : out std_logic_vector(DATA-1 downto 0)
);
end bram_tdp;
architecture rtl of bram_tdp is
-- Shared memory
type mem_type is array ( (2**ADDR)-1 downto 0 ) of std_logic_vector(DATA-1 downto 0);
shared variable mem : mem_type;
begin
-- Port A
process(a_clk)
begin
if(a_clk'event and a_clk='1') then
if(a_wr='1') then
mem(conv_integer(a_addr)) := a_din;
end if;
a_dout <= mem(conv_integer(a_addr));
end if;
end process;
-- Port B
process(b_clk)
begin
if(b_clk'event and b_clk='1') then
if(b_wr='1') then
mem(conv_integer(b_addr)) := b_din;
end if;
b_dout <= mem(conv_integer(b_addr));
end if;
end process;
end rtl;
| gpl-2.0 | 03dde7e560c33bfd0c9e6ec9094aa452 | 0.591879 | 2.832359 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue4/Audio/audio_out.vhd | 1 | 2,237 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:20:37 07/08/2016
-- Design Name:
-- Module Name: audio_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity audio_out is port (
clk : in STD_LOGIC;
ready : in STD_LOGIC;
reset : in STD_LOGIC;
scancode : in STD_LOGIC_VECTOR(7 downto 0);
audio : out STD_LOGIC);
end audio_out;
architecture Behavioral of audio_out is
component audio_scancode_to_divisor is port (
scancode : in STD_LOGIC_VECTOR(7 downto 0);
clock_divisor : out INTEGER);
end component;
signal clock_divisor : INTEGER := 378788; -- for 264 Hz (c')
signal clock_counter_max : INTEGER range 0 to 500000000 := 0;
signal clock_counter : INTEGER range 0 to 500000000 := 0;
signal audio_state : STD_LOGIC := '0';
begin
audio_scancode_to_divisor0 : audio_scancode_to_divisor port map (scancode, clock_divisor);
clock_divider : process(clock_counter_max, clk)
begin
if clk'event and clk = '1' then
if clock_counter >= clock_counter_max then
clock_counter <= 0;
if audio_state = '0' then
audio_state <= '1';
else
audio_state <= '0';
end if;
else
clock_counter <= clock_counter + 1;
end if;
end if;
end process clock_divider;
divisor_to_max_counter : process(clock_divisor)
begin
-- 100 MHz divided by clock_divisor
-- result divided again by 2 to achive alternating high and low with correct frequency
--clock_counter_max <= 100000000 / (clock_divisor * 2);
clock_counter_max <= 500000;
end process divisor_to_max_counter;
audio <= audio_state;
end Behavioral;
| mit | 8c6d24f7395d7cfad14de4a46564d679 | 0.637908 | 3.457496 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/and/myAnd2_tb.vhdl | 1 | 1,111 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myAnd2_tb is
end myAnd2_tb;
architecture behavioral of myAnd2_tb is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
-- signals used for testing
signal s1: std_logic;
signal s2: std_logic;
signal o1: std_logic;
begin
-- component instantiation
myAnd2_1: myAnd2 port map(a => s1, b => s2, s => o1);
process
begin
s1 <= '0';
s2 <= '0';
wait for 1 ns;
assert o1 = '0' report "and('0', '0') was not '0'" severity error;
s1 <= '0';
s2 <= '1';
wait for 1 ns;
assert o1 = '0' report "and('0', '1') was not '0'" severity error;
s1 <= '1';
s2 <= '0';
wait for 1 ns;
assert o1 = '0' report "and('1', '0') was not '0'" severity error;
s1 <= '1';
s2 <= '1';
wait for 1 ns;
assert o1 = '1' report "and('1', '1') was not '1'" severity error;
assert false report "test complete" severity note;
wait;
end process;
end behavioral;
| mit | 5907c5b0e5eb39b35545fd325780ac63 | 0.529253 | 3.165242 | false | false | false | false |
timofonic/1541UltimateII | target/simulation/packages/vhdl_source/tl_file_io_pkg.vhd | 4 | 9,339 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: File IO routines
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
package tl_file_io_pkg is
type t_slv8_array is array(natural range <>) of std_logic_vector(7 downto 0);
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character);
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector);
procedure read_hex_file_to_array (file myfile : text; array_size : integer; result : inout t_slv8_array);
-- handling binary files
type t_binary_file is file of integer;
type t_binary_file_rec is record
offset : integer range 0 to 4;
long_vec : std_logic_vector(31 downto 0);
end record;
procedure init_record(rec : inout t_binary_file_rec);
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec);
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec);
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec);
end;
package body tl_file_io_pkg is
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character) is
variable good : boolean := false;
variable stop : boolean := false;
begin
while not(good) loop
READ(my_line, hex, good);
if not(good) then
if ENDFILE(my_file) then
stop := true;
hex := '1';
return;
end if;
READLINE(my_file, my_line);
end if;
end loop;
file_end := stop;
end get_char_from_file;
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector) is
variable hex : character;
variable data : std_logic_vector(7 downto 0);
variable stop : boolean := false;
begin
data := X"00";
l_1 : loop
get_char_from_file(my_file, my_line, stop, hex);
if stop or is_hex_char(hex) then
exit l_1;
end if;
end loop l_1;
data(3 downto 0) := hex_to_nibble(hex);
-- see if we can read another good hex char
get_char_from_file(my_file, my_line, stop, hex);
if not(stop) and is_hex_char(hex) then
data(7 downto 4) := data(3 downto 0);
data(3 downto 0) := hex_to_nibble(hex);
end if;
file_end := stop;
dat := data;
end get_byte_from_file;
procedure read_hex_file_to_array (
file myfile : text;
array_size : integer;
result : inout t_slv8_array)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : std_logic_vector(7 downto 0);
variable sum : unsigned(7 downto 0);
variable rectype : std_logic_vector(7 downto 0);
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
variable out_array: t_slv8_array(0 to array_size-1) := (others => (others => '0'));
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
exit outer;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
out_array(to_integer(addr)) := data;
addr := addr + 1;
end loop;
when X"01" => -- end of file record
exit outer;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
exit outer;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
result := out_array;
end read_hex_file_to_array;
procedure init_record(rec : inout t_binary_file_rec) is
begin
rec.offset := 0;
rec.long_vec := (others => '0');
end procedure;
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset = 0 then
read(my_file, i);
rec.long_vec := std_logic_vector(to_unsigned(i, 32));
end if;
byte := rec.long_vec(7 downto 0);
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
if rec.offset = 3 then
rec.offset := 0;
else
rec.offset := rec.offset + 1;
end if;
end procedure;
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
rec.long_vec(31 downto 24) := byte;
if rec.offset = 3 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
rec.offset := 0;
else
rec.offset := rec.offset + 1;
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
end if;
end procedure;
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset /= 0 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
end if;
end procedure;
end;
| gpl-3.0 | da4696130e416fdb4264be40b4934bed | 0.452297 | 3.979122 | false | false | false | false |
Fju/LeafySan | src/vhdl/interfaces/uart.vhdl | 1 | 11,146 | -----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : UART Interface
-- Author : Jan Dürre
-- Last update : 10.04.2015
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.iac_pkg.all;
entity uart is
generic (
SIMULATION : boolean := false
);
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_UART-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
-- IRQ handling
iobus_irq_rx : out std_ulogic;
iobus_irq_tx : out std_ulogic;
iobus_ack_rx : in std_ulogic;
iobus_ack_tx : in std_ulogic;
-- pins to outside
rts : in std_ulogic;
cts : out std_ulogic;
rxd : in std_ulogic;
txd : out std_ulogic
);
end uart;
architecture rtl of uart is
constant CV_BIT_DURATION_REAL : natural := natural(ceil(real(CV_SYS_CLOCK_RATE) / real(CV_UART_BAUDRATE)));
constant CV_BIT_DURATION_SIM : natural := 16;
signal CV_BIT_DURATION : natural;
component fifo is
generic (
DEPTH : natural;
WORDWIDTH : natural
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
write_en : in std_ulogic;
data_in : in std_ulogic_vector(WORDWIDTH-1 downto 0);
read_en : in std_ulogic;
data_out : out std_ulogic_vector(WORDWIDTH-1 downto 0);
empty : out std_ulogic;
full : out std_ulogic;
fill_cnt : out unsigned(to_log2(DEPTH+1)-1 downto 0)
);
end component fifo;
signal rxbuf_write_en : std_ulogic;
signal rxbuf_data_in : std_ulogic_vector(CV_UART_DATABITS-1 downto 0);
signal rxbuf_read_en : std_ulogic;
signal rxbuf_data_out : std_ulogic_vector(CV_UART_DATABITS-1 downto 0);
signal rxbuf_empty : std_ulogic;
signal rxbuf_full : std_ulogic;
signal txbuf_write_en : std_ulogic;
signal txbuf_data_in : std_ulogic_vector(CV_UART_DATABITS-1 downto 0);
signal txbuf_read_en : std_ulogic;
signal txbuf_data_out : std_ulogic_vector(CV_UART_DATABITS-1 downto 0);
signal txbuf_empty : std_ulogic;
signal txbuf_full : std_ulogic;
-- rx
type state_rx_t is ( S_IDLE,
S_HALFSTARTBIT,
S_DATABITS,
S_PARITY,
S_STOPBITS
);
signal state_rx : state_rx_t;
signal state_rx_nxt : state_rx_t;
signal rxd_reg : std_ulogic_vector(2 downto 0);
signal rxd_reg_nxt : std_ulogic_vector(2 downto 0);
signal rx_cnt : unsigned(to_log2(CV_BIT_DURATION_REAL)-1 downto 0);
signal rx_cnt_nxt : unsigned(to_log2(CV_BIT_DURATION_REAL)-1 downto 0);
signal rx_cnt_reset : std_ulogic;
signal rx_bitcnt : unsigned(to_log2(CV_UART_DATABITS)-1 downto 0);
signal rx_bitcnt_nxt : unsigned(to_log2(CV_UART_DATABITS)-1 downto 0);
signal rx_data : std_ulogic_vector(CV_UART_DATABITS-1 downto 0);
signal rx_data_nxt : std_ulogic_vector(CV_UART_DATABITS-1 downto 0);
signal error_reg : std_ulogic_vector(1 downto 0); -- 1: overflow, 0: parity
signal error_reg_nxt : std_ulogic_vector(1 downto 0);
-- tx
type state_tx_t is ( S_IDLE,
S_STARTBIT,
S_DATABITS,
S_PARITY,
S_STOPBITS
);
signal state_tx : state_tx_t;
signal state_tx_nxt : state_tx_t;
signal tx_cnt : unsigned(to_log2(CV_BIT_DURATION_REAL)-1 downto 0);
signal tx_cnt_nxt : unsigned(to_log2(CV_BIT_DURATION_REAL)-1 downto 0);
signal tx_cnt_reset : std_ulogic;
signal tx_bitcnt : unsigned(to_log2(CV_UART_DATABITS)-1 downto 0);
signal tx_bitcnt_nxt : unsigned(to_log2(CV_UART_DATABITS)-1 downto 0);
signal tx_data : std_ulogic_vector(CV_UART_DATABITS-1 downto 0);
signal tx_data_nxt : std_ulogic_vector(CV_UART_DATABITS-1 downto 0);
signal tx_parity : std_ulogic;
signal tx_parity_nxt : std_ulogic;
begin
CV_BIT_DURATION <= CV_BIT_DURATION_SIM when SIMULATION = true else CV_BIT_DURATION_REAL;
cts <= '0';
rxbuf_inst : fifo
generic map (
DEPTH => CS_UART_BUFFER,
WORDWIDTH => CV_UART_DATABITS
)
port map (
clock => clock,
reset_n => reset_n,
write_en => rxbuf_write_en,
data_in => rxbuf_data_in,
read_en => rxbuf_read_en,
data_out => rxbuf_data_out,
empty => rxbuf_empty,
full => rxbuf_full,
fill_cnt => open
);
txbuf_inst : fifo
generic map (
DEPTH => CS_UART_BUFFER,
WORDWIDTH => CV_UART_DATABITS
)
port map (
clock => clock,
reset_n => reset_n,
write_en => txbuf_write_en,
data_in => txbuf_data_in,
read_en => txbuf_read_en,
data_out => txbuf_data_out,
empty => txbuf_empty,
full => txbuf_full,
fill_cnt => open
);
ff : process (reset_n, clock)
begin
if (reset_n = '0') then
state_rx <= S_IDLE;
rxd_reg <= (others => '0');
rx_cnt <= (others => '0');
rx_bitcnt <= (others => '0');
rx_data <= (others => '0');
error_reg <= (others => '0');
state_tx <= S_IDLE;
tx_cnt <= (others => '0');
tx_bitcnt <= (others => '0');
tx_data <= (others => '0');
tx_parity <= '0';
elsif rising_edge(clock) then
state_rx <= state_rx_nxt;
rxd_reg <= rxd_reg_nxt;
rx_cnt <= rx_cnt_nxt;
rx_bitcnt <= rx_bitcnt_nxt;
rx_data <= rx_data_nxt;
error_reg <= error_reg_nxt;
state_tx <= state_tx_nxt;
tx_cnt <= tx_cnt_nxt;
tx_bitcnt <= tx_bitcnt_nxt;
tx_data <= tx_data_nxt;
tx_parity <= tx_parity_nxt;
end if;
end process;
iobus_if : process(iobus_cs, iobus_wr, iobus_addr, iobus_din, rxbuf_empty, rxbuf_full, rxbuf_data_out, txbuf_empty, txbuf_full, error_reg)
begin
txbuf_write_en <= '0';
txbuf_data_in <= (others => '0');
rxbuf_read_en <= '0';
iobus_irq_rx <= not rxbuf_empty;
iobus_irq_tx <= not txbuf_full;
iobus_dout <= (others => '0');
-- chipselect
if iobus_cs = '1' then
-- write
if iobus_wr = '1' then
-- tx data
if iobus_addr = CV_ADDR_UART_DATA_TX then
-- avoid overflow
if txbuf_full = '0' then
txbuf_write_en <= '1';
txbuf_data_in <= iobus_din;
end if;
end if;
-- read
else
-- rx data
if iobus_addr = CV_ADDR_UART_DATA_RX then
-- avoid underflow
if rxbuf_empty = '0' then
rxbuf_read_en <= '1';
iobus_dout <= rxbuf_data_out;
end if;
end if;
end if;
end if;
end process;
rx_cnt_nxt <= (others => '0') when rx_cnt_reset = '1' else rx_cnt + 1;
tx_cnt_nxt <= (others => '0') when tx_cnt_reset = '1' else tx_cnt + 1;
-- rx fsm
rx : process(state_rx, rxbuf_full, rxd_reg, rx_bitcnt, rx_cnt, rx_data, error_reg, rxd, CV_BIT_DURATION)
begin
state_rx_nxt <= state_rx;
rxd_reg_nxt <= rxd_reg;
rx_bitcnt_nxt <= rx_bitcnt;
rx_data_nxt <= rx_data;
error_reg_nxt <= error_reg;
rx_cnt_reset <= '0';
rxbuf_write_en <= '0';
rxbuf_data_in <= (others => '0');
rxd_reg_nxt <= rxd & rxd_reg(rxd_reg'length-1 downto 1);
case state_rx is
when S_IDLE =>
-- falling edge on rxd
if rxd_reg = "001" then
rx_cnt_reset <= '1';
error_reg_nxt <= (others => '0');
state_rx_nxt <= S_HALFSTARTBIT;
end if;
when S_HALFSTARTBIT =>
-- sync to mid of startbit
if rx_cnt = shift_right(to_unsigned(CV_BIT_DURATION - 1, rx_cnt'length),1) then
rx_cnt_reset <= '1';
rx_bitcnt_nxt <= (others => '0');
state_rx_nxt <= S_DATABITS;
end if;
when S_DATABITS =>
if rx_cnt = CV_BIT_DURATION - 1 then
rx_cnt_reset <= '1';
rx_data_nxt <= rxd_reg(0) & rx_data(rx_data'length-1 downto 1);
-- last databit
if rx_bitcnt = CV_UART_DATABITS-1 then
rx_bitcnt_nxt <= (others => '0');
-- receive parity
if CS_UART_PARITY /= "NONE" then
state_rx_nxt <= S_PARITY;
-- receive stopbits
else
state_rx_nxt <= S_STOPBITS;
end if;
-- next databit
else
rx_bitcnt_nxt <= rx_bitcnt + 1;
end if;
end if;
when S_PARITY =>
if rx_cnt = CV_BIT_DURATION - 1 then
rx_cnt_reset <= '1';
state_rx_nxt <= S_STOPBITS;
-- check parity
if calc_parity(rx_data, CS_UART_PARITY) /= rxd_reg(0) then
-- parity error
error_reg_nxt(0) <= '1';
end if;
end if;
when S_STOPBITS =>
if rx_cnt = CV_BIT_DURATION - 1 then
rx_cnt_reset <= '1';
-- last stopbit
if rx_bitcnt = CV_UART_STOPBITS-1 then
rx_bitcnt_nxt <= (others => '0');
state_rx_nxt <= S_IDLE;
-- write received data to rx-fifo
if rxbuf_full = '0' then
rxbuf_write_en <= '1';
rxbuf_data_in <= rx_data;
else
-- overflow error
error_reg_nxt(1) <= '1';
end if;
-- next stopbit
else
rx_bitcnt_nxt <= rx_bitcnt + 1;
end if;
end if;
end case;
end process;
-- tx fsm
tx : process(state_tx, tx_cnt, tx_bitcnt, tx_data, tx_parity, txbuf_data_out, txbuf_empty, CV_BIT_DURATION)
begin
state_tx_nxt <= state_tx;
tx_cnt_reset <= '0';
tx_bitcnt_nxt <= tx_bitcnt;
tx_data_nxt <= tx_data;
tx_parity_nxt <= tx_parity;
txbuf_read_en <= '0';
txd <= '1';
case state_tx is
when S_IDLE =>
txd <= '1';
-- wait for data in tx-fifo
if txbuf_empty = '0' then
txbuf_read_en <= '1';
tx_cnt_reset <= '1';
tx_bitcnt_nxt <= (others => '0');
tx_data_nxt <= txbuf_data_out;
tx_parity_nxt <= calc_parity(txbuf_data_out, CS_UART_PARITY);
state_tx_nxt <= S_STARTBIT;
end if;
when S_STARTBIT =>
txd <= '0';
-- startbit finished
if tx_cnt = CV_BIT_DURATION - 1 then
tx_cnt_reset <= '1';
state_tx_nxt <= S_DATABITS;
end if;
when S_DATABITS =>
txd <= tx_data(0);
-- single databit finished
if tx_cnt = CV_BIT_DURATION - 1 then
tx_cnt_reset <= '1';
tx_data_nxt <= '0' & tx_data(tx_data'length-1 downto 1);
-- last databit
if tx_bitcnt = CV_UART_DATABITS-1 then
tx_bitcnt_nxt <= (others => '0');
-- transfer parity
if CS_UART_PARITY /= "NONE" then
state_tx_nxt <= S_PARITY;
-- transfer stopbits
else
state_tx_nxt <= S_STOPBITS;
end if;
-- next databit
else
tx_bitcnt_nxt <= tx_bitcnt + 1;
end if;
end if;
when S_PARITY =>
txd <= tx_parity;
-- transfer parity
if tx_cnt = CV_BIT_DURATION - 1 then
tx_cnt_reset <= '1';
state_tx_nxt <= S_STOPBITS;
end if;
when S_STOPBITS =>
txd <= '1';
-- single stopbit finished
if tx_cnt = CV_BIT_DURATION - 1 then
tx_cnt_reset <= '1';
-- last stopbit
if tx_bitcnt = CV_UART_STOPBITS-1 then
state_tx_nxt <= S_IDLE;
-- next stopbit
else
tx_bitcnt_nxt <= tx_bitcnt + 1;
end if;
end if;
end case;
end process;
end rtl;
| apache-2.0 | f531174f9ff540863681faade9a90d8e | 0.570749 | 2.621736 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/mux/myMux2.vhdl | 1 | 885 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myMux2 is
port(a: in std_logic; b: in std_logic; sel: in std_logic; s: out std_logic);
end myMux2;
architecture behavioral of myMux2 is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myOr2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myNot
port(a: in std_logic; s: out std_logic);
end component;
signal selNot: std_logic;
signal aAndNotSelOut: std_logic;
signal bAndSelOut: std_logic;
begin
myNot_1: myNot port map(a => sel, s => selNot);
myAnd2_1: myAnd2 port map(a => a, b => selNot, s => aAndNotSelOut);
myAnd2_2: myAnd2 port map(a => b, b => sel, s => bAndSelOut);
myOr2_1: myOr2 port map(a => aAndNotSelOut, b => bAndSelOut, s => s);
end behavioral;
| mit | a4f5bcf3cc2069b38489ed7297006d96 | 0.637288 | 2.911184 | false | false | false | false |
Fju/LeafySan | src/vhdl/invent_a_chip_leafysan.vhdl | 1 | 27,514 | ----------------------------------------------------------------------
-- Project : LeafySan
-- Module : Main module
-- Authors : Florian Winkler
-- Lust update : 03.09.2017
-- Description : Connects all modules with external stuff (switches, gpio pins, LED's)
-- Furthermore it displays all read sensor values on a LCD and a 7-Segment Display
-- Also sends data via UART to a microcomputer
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
component adc_sensors is
port (
clock : in std_ulogic;
reset : in std_ulogic;
temperature : out unsigned(11 downto 0);
carbondioxide : out unsigned(13 downto 0);
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0)
);
end component adc_sensors;
component light_sensor is
generic (
CYCLE_TICKS : natural := 50000000
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
value : out unsigned(15 downto 0);
enabled : in std_ulogic
);
end component light_sensor;
component moisture_sensor is
generic (
CYCLE_TICKS : natural := 50000000
);
port (
clock : in std_ulogic;
reset : in std_ulogic;
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
moisture : out unsigned(15 downto 0);
temperature : out unsigned(15 downto 0);
address : out unsigned(6 downto 0);
enabled : in std_ulogic
);
end component moisture_sensor;
component peripherals is
port(
clock : in std_ulogic;
reset : in std_ulogic;
temperature : in unsigned(11 downto 0);
brightness : in unsigned(15 downto 0);
moisture : in unsigned(15 downto 0);
lighting_on : out std_ulogic;
heating_on : out std_ulogic;
watering_on : out std_ulogic;
ventilation_on : out std_ulogic;
heating_thresh : in unsigned(11 downto 0);
lighting_thresh : in unsigned(15 downto 0);
watering_thresh : in unsigned(15 downto 0)
);
end component peripherals;
constant SENSOR_CYCLE_TICKS : natural := 50000000; -- 1s
constant LCD_CLOCK_TICKS : natural := 10000000; -- 200ms
constant SEG_CLOCK_TICKS : natural := 12500000; -- 250ms
constant UART_WR_BYTE_COUNT : natural := 13;
constant UART_RD_BYTE_COUNT : natural := 9;
constant UART_DATA_WIDTH : natural := 6;
constant WARNING_CLOCK_TICKS : natural := 37500000; -- 750ms
-- state definitions
type lcd_state_t is (S_LCD_WAIT, S_LCD_DISPLAY);
type seg_state_t is (S_SEG_WAIT, S_SEG_DISPLAY_DEC, S_SEG_DISPLAY_HEX);
type uart_state_t is (S_UART_RD_WAIT_START, S_UART_RD_READ_LOOP, S_UART_WR_START, S_UART_WR_WRITE_LOOP, S_UART_WR_END);
type sensor_state_t is (S_SENS_LIGHT, S_SENS_MOIST);
-- state registers
signal lcd_state, lcd_state_nxt : lcd_state_t;
signal seg_state, seg_state_nxt : seg_state_t;
signal uart_state, uart_state_nxt : uart_state_t;
signal sensor_state, sensor_state_nxt : sensor_state_t;
-- seven-segment registers
signal seg_clock, seg_clock_nxt : unsigned(to_log2(SEG_CLOCK_TICKS) - 1 downto 0);
-- LCD registers
signal lcd_clock, lcd_clock_nxt : unsigned(to_log2(LCD_CLOCK_TICKS) - 1 downto 0);
signal lcd_cmds, lcd_cmds_nxt : lcd_commands_t(0 to 32);
-- amount of bytes sent to determine whether all data has been sent already
signal lcd_sent_chars, lcd_sent_chars_nxt : unsigned(to_log2(lcd_cmds'length) - 1 downto 0);
-- UART registers
signal uart_sent_bytes, uart_sent_bytes_nxt : unsigned(to_log2(UART_WR_BYTE_COUNT) - 1 downto 0);
signal uart_received_bytes, uart_received_bytes_nxt : unsigned(to_log2(UART_RD_BYTE_COUNT) - 1 downto 0);
type uart_protocol_entry_t is record
cmd : std_ulogic_vector(1 downto 0);
data : std_ulogic_vector(5 downto 0);
end record;
type uart_protocol_array is array (natural range <>) of uart_protocol_entry_t;
signal uart_wr_array, uart_wr_array_nxt : uart_protocol_array(0 to UART_WR_BYTE_COUNT - 1);
signal uart_rd_array, uart_rd_array_nxt : uart_protocol_array(0 to UART_RD_BYTE_COUNT - 1);
-- signals for `adc_sensors` component
signal adc_temperature : unsigned(11 downto 0);
signal adc_carbondioxide : unsigned(13 downto 0);
-- signals for `light_sensor` component
signal light_clk_ctrl, light_dat_ctrl : std_ulogic;
signal light_clk_in, light_dat_in : std_ulogic;
signal light_clk_out, light_dat_out : std_ulogic;
signal light_enabled : std_ulogic;
signal light_value : unsigned(15 downto 0);
-- signals for `moisture_sensor` component
signal moist_clk_ctrl, moist_dat_ctrl : std_ulogic;
signal moist_clk_in, moist_dat_in : std_ulogic;
signal moist_clk_out, moist_dat_out : std_ulogic;
signal moist_enabled : std_ulogic;
signal moist_moisture : unsigned(15 downto 0);
signal moist_temperature : unsigned(15 downto 0);
signal moist_address : unsigned(6 downto 0);
-- signals for `peripherals` component
signal peripherals_heating_on : std_ulogic;
signal peripherals_watering_on : std_ulogic;
signal peripherals_lighting_on : std_ulogic;
signal peripherals_ventilation_on : std_ulogic;
signal heating_thresh, heating_thresh_nxt : unsigned(11 downto 0);
signal lighting_thresh, lighting_thresh_nxt : unsigned(15 downto 0);
signal watering_thresh, watering_thresh_nxt : unsigned(15 downto 0);
-- registers to create blinking led effect
signal warning_clock, warning_clock_nxt : unsigned(to_log2(WARNING_CLOCK_TICKS) - 1 downto 0);
signal warning_led, warning_led_nxt : std_ulogic;
begin
-- map all component signals to internal signals
adc_sensors_inst : adc_sensors
port map (
clock => clock,
reset => reset,
temperature => adc_temperature,
carbondioxide => adc_carbondioxide,
adc_dac_cs => adc_dac_cs,
adc_dac_wr => adc_dac_wr,
adc_dac_addr => adc_dac_addr,
adc_dac_din => adc_dac_din,
adc_dac_dout => adc_dac_dout
);
light_sensor_inst : light_sensor
generic map (
CYCLE_TICKS => SENSOR_CYCLE_TICKS
)
port map (
clock => clock,
reset => reset,
i2c_clk_ctrl => light_clk_ctrl,
i2c_clk_in => light_clk_in,
i2c_clk_out => light_clk_out,
i2c_dat_ctrl => light_dat_ctrl,
i2c_dat_in => light_dat_in,
i2c_dat_out => light_dat_out,
value => light_value,
enabled => light_enabled
);
moisture_sensor_inst : moisture_sensor
generic map (
CYCLE_TICKS => SENSOR_CYCLE_TICKS
)
port map (
clock => clock,
reset => reset,
i2c_clk_ctrl => moist_clk_ctrl,
i2c_clk_in => moist_clk_in,
i2c_clk_out => moist_clk_out,
i2c_dat_ctrl => moist_dat_ctrl,
i2c_dat_in => moist_dat_in,
i2c_dat_out => moist_dat_out,
moisture => moist_moisture,
temperature => moist_temperature,
address => moist_address,
enabled => moist_enabled
);
peripherals_inst : peripherals
port map (
clock => clock,
reset => reset,
temperature => adc_temperature,
brightness => light_value,
moisture => moist_moisture,
lighting_on => peripherals_lighting_on,
heating_on => peripherals_heating_on,
watering_on => peripherals_watering_on,
ventilation_on => peripherals_ventilation_on,
heating_thresh => heating_thresh,
lighting_thresh => lighting_thresh,
watering_thresh => watering_thresh
);
-- sequential process
process(clock, reset)
begin
if reset = '1' then
lcd_state <= S_LCD_WAIT;
lcd_clock <= (others => '0');
lcd_cmds <= (others => (others => '0'));
lcd_sent_chars <= (others => '0');
seg_state <= S_SEG_WAIT;
seg_clock <= (others => '0');
uart_state <= S_UART_RD_WAIT_START;
uart_wr_array <= (others => (others => (others => '0')));
uart_rd_array <= (others => (others => (others => '0')));
uart_sent_bytes <= (others => '0');
uart_received_bytes <= (others => '0');
warning_clock <= (others => '0');
warning_led <= '0';
-- set thresholds to default value
heating_thresh <= to_unsigned(220, heating_thresh'length); -- 22,0 °C
lighting_thresh <= to_unsigned(400, lighting_thresh'length); -- 400 lx
watering_thresh <= to_unsigned(500, watering_thresh'length); -- 50,0 %
elsif rising_edge(clock) then
lcd_state <= lcd_state_nxt;
lcd_clock <= lcd_clock_nxt;
lcd_cmds <= lcd_cmds_nxt;
lcd_sent_chars <= lcd_sent_chars_nxt;
seg_state <= seg_state_nxt;
seg_clock <= seg_clock_nxt;
uart_state <= uart_state_nxt;
uart_wr_array <= uart_wr_array_nxt;
uart_rd_array <= uart_rd_array_nxt;
uart_sent_bytes <= uart_sent_bytes_nxt;
uart_received_bytes <= uart_received_bytes_nxt;
warning_clock <= warning_clock_nxt;
warning_led <= warning_led_nxt;
heating_thresh <= heating_thresh_nxt;
lighting_thresh <= lighting_thresh_nxt;
watering_thresh <= watering_thresh_nxt;
end if;
end process;
-- GPIO process
process(peripherals_ventilation_on, peripherals_heating_on, peripherals_lighting_on, peripherals_watering_on,
moist_clk_ctrl, moist_clk_in, moist_clk_out, moist_dat_ctrl, moist_dat_in, moist_dat_out,
light_clk_ctrl, light_clk_in, light_clk_out, light_dat_ctrl, light_dat_in, light_dat_out,
warning_clock, warning_led, gp_in, switch)
begin
-- safety / development / debug switches
led_green(0) <= switch(0);
led_green(1) <= not(gp_in(8));
-- automatic / manual peripherals control switch
led_green(2) <= switch(1);
led_red <= (others => '0'); -- default assignment
-- i2c connections
light_enabled <= '1'; -- for debugging purpose
gp_ctrl(1 downto 0) <= light_clk_ctrl & light_dat_ctrl;
gp_out(1 downto 0) <= light_clk_out & light_dat_out;
light_clk_in <= gp_in(1);
light_dat_in <= gp_in(0);
moist_enabled <= '1'; -- for debugging purpose
gp_ctrl(3 downto 2) <= moist_clk_ctrl & moist_dat_ctrl;
gp_out(3 downto 2) <= moist_clk_out & moist_dat_out;
moist_clk_in <= gp_in(3);
moist_dat_in <= gp_in(2);
-- setup pin mode: 1 input (safety switch), 4 outputs (relais control)
gp_ctrl(8 downto 4) <= "01111";
-- disable all relais by default
gp_out(7 downto 4) <= not("0000");
warning_led_nxt <= warning_led;
warning_clock_nxt <= warning_clock;
if gp_in(8) = '1' or switch(0) = '1' then
warning_led_nxt <= '0';
warning_clock_nxt <= (others => '0');
if switch(1) = '0' then
-- automatic GPIO outputs
-- Map: GPIO_4 -> IN1 (lighting), GPIO_5 -> IN2 (watering), GPIO_6 -> IN3 (ventilation), GPIO_7 -> IN4 (heating)
-- relais needs '1' for off and '0' for on, that's why `not(...)` is used
gp_out(7 downto 4) <= not(peripherals_heating_on & peripherals_ventilation_on & peripherals_watering_on & peripherals_lighting_on);
led_red(3 downto 0) <= peripherals_heating_on & peripherals_ventilation_on & peripherals_watering_on & peripherals_lighting_on;
else
-- manual GPIO outputs
gp_out(7 downto 4) <= not(switch(5 downto 2));
led_red(3 downto 0) <= switch(5 downto 2);
end if;
else
-- generate blinking led row when safety switch is off
led_red <= (others => warning_led); -- all on or all off
if warning_clock = to_unsigned(WARNING_CLOCK_TICKS - 1, warning_clock'length) then
warning_clock_nxt <= (others => '0');
if warning_led = '1' then
warning_led_nxt <= '0';
else
warning_led_nxt <= '1';
end if;
else
warning_clock_nxt <= warning_clock + to_unsigned(1, warning_clock'length);
end if;
end if;
--
gp_ctrl(15 downto 9) <= (others => '0');
gp_out(15 downto 8) <= (others => '0');
led_green(8 downto 3) <= (others => '0');
end process;
-- LCD process
process(key, adc_dac_din, lcd_state, lcd_clock, lcd_irq_rdy, lcd_cmds, lcd_sent_chars, moist_moisture, moist_temperature, light_value, adc_carbondioxide,
lighting_thresh, watering_thresh, heating_thresh)
-- variables for converting numbers into lcd_cmds
variable mst_bcd_value : unsigned(15 downto 0) := (others => '0');
variable tmp_bcd_value : unsigned(15 downto 0) := (others => '0');
variable lux_bcd_value : unsigned(19 downto 0) := (others => '0');
variable co2_bcd_value : unsigned(15 downto 0) := (others => '0');
variable mst_bcd_thresh : unsigned(11 downto 0) := (others => '0');
variable tmp_bcd_thresh : unsigned(11 downto 0) := (others => '0');
variable lux_bcd_thresh : unsigned(19 downto 0) := (others => '0');
variable lcd_cmds_mst : std_ulogic_vector(55 downto 0) := (others => '0');
variable lcd_cmds_tmp : std_ulogic_vector(55 downto 0) := (others => '0');
variable lcd_cmds_lux : std_ulogic_vector(63 downto 0) := (others => '0');
variable lcd_cmds_co2 : std_ulogic_vector(55 downto 0) := (others => '0');
variable lcd_thresh_mst : std_ulogic_vector(31 downto 0) := (others => '0');
variable lcd_thresh_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
variable lcd_thresh_lux : std_ulogic_vector(39 downto 0) := (others => '0');
begin
-- hold values of all registers by default
lcd_state_nxt <= lcd_state;
lcd_clock_nxt <= lcd_clock;
lcd_cmds_nxt <= lcd_cmds;
lcd_sent_chars_nxt <= lcd_sent_chars;
-- default assignments for the LCD module
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
case lcd_state is
when S_LCD_WAIT =>
-- increment counter value
lcd_clock_nxt <= lcd_clock + to_unsigned(1, lcd_clock'length);
if lcd_clock >= to_unsigned(LCD_CLOCK_TICKS, lcd_clock'length) then
-- switch state after 10000000 "clocks" (200 ms)
lcd_clock_nxt <= (others => '0');
lcd_sent_chars_nxt <= (others => '0');
-- convert binary values into x decimal numbers
mst_bcd_value := unsigned(to_bcd(std_ulogic_vector(moist_moisture), 4));
tmp_bcd_value := unsigned(to_bcd(std_ulogic_vector(moist_temperature), 4));
lux_bcd_value := unsigned(to_bcd(std_ulogic_vector(light_value), 5));
co2_bcd_value := unsigned(to_bcd(std_ulogic_vector(adc_carbondioxide), 4));
mst_bcd_thresh := unsigned(to_bcd(std_ulogic_vector(watering_thresh), 3));
tmp_bcd_thresh := unsigned(to_bcd(std_ulogic_vector(heating_thresh), 3));
lux_bcd_thresh := unsigned(to_bcd(std_ulogic_vector(lighting_thresh), 5));
-- ascii storages
lcd_cmds_mst := asciitext("M: ") & ascii(mst_bcd_value(15 downto 12)) & ascii(mst_bcd_value(11 downto 8)) & ascii(mst_bcd_value(7 downto 4)) & ascii(mst_bcd_value(3 downto 0));
lcd_cmds_tmp := asciitext("T: ") & ascii(tmp_bcd_value(15 downto 12)) & ascii(tmp_bcd_value(11 downto 8)) & ascii(tmp_bcd_value(7 downto 4)) & ascii(tmp_bcd_value(3 downto 0));
lcd_cmds_lux := asciitext("L: ") & ascii(lux_bcd_value(19 downto 16)) & ascii(lux_bcd_value(15 downto 12)) & ascii(lux_bcd_value(11 downto 8)) & ascii(lux_bcd_value(7 downto 4)) & ascii(lux_bcd_value(3 downto 0));
lcd_cmds_co2 := asciitext("C: ") & ascii(co2_bcd_value(15 downto 12)) & ascii(co2_bcd_value(11 downto 8)) & ascii(co2_bcd_value(7 downto 4)) & ascii(co2_bcd_value(3 downto 0));
lcd_thresh_mst := ascii(mst_bcd_thresh(11 downto 8)) & ascii(mst_bcd_thresh(7 downto 4)) & asciitext(".") & ascii(mst_bcd_thresh(3 downto 0));
lcd_thresh_tmp := ascii(tmp_bcd_thresh(11 downto 8)) & ascii(tmp_bcd_thresh(7 downto 4)) & asciitext(".") & ascii(tmp_bcd_thresh(3 downto 0));
lcd_thresh_lux := ascii(lux_bcd_value(19 downto 16)) & ascii(lux_bcd_thresh(15 downto 12)) & ascii(lux_bcd_thresh(11 downto 8)) & ascii(lux_bcd_thresh(7 downto 4)) & ascii(lux_bcd_thresh(3 downto 0));
-- set next lcd commands that will be displayed
if key(1) = '0' then
lcd_cmds_nxt <= lcd_cmd(lcd_cursor_pos(0, 0) & lcd_cmds_mst & asciitext(" ") & lcd_cmds_co2 & lcd_cmds_lux & asciitext(" ") & lcd_cmds_tmp);
else
lcd_cmds_nxt <= lcd_cmd(lcd_cursor_pos(0, 0) & asciitext("Thresh (L,M,T)") & asciitext(" ") & lcd_thresh_lux & asciitext(" ") & lcd_thresh_mst & asciitext(" ") & lcd_thresh_tmp & asciitext(" "));
end if;
-- change state in order to display it/send it to the LCD
lcd_state_nxt <= S_LCD_DISPLAY;
end if;
when S_LCD_DISPLAY =>
if lcd_irq_rdy = '1' then
-- enable Chip Select, Write Mode and acknowledge ready
lcd_cs <= '1';
lcd_wr <= '1';
lcd_ack_rdy <= '1';
lcd_addr <= CV_ADDR_LCD_DATA;
-- send one byte of date
lcd_dout(7 downto 0) <= lcd_cmds(to_integer(lcd_sent_chars));
-- check whether all characters have already been sent
if lcd_sent_chars = to_unsigned(lcd_cmds'length - 1, lcd_sent_chars'length) then
-- all characters have been sent, so switch state back to S_WAIT
lcd_state_nxt <= S_LCD_WAIT;
else
-- increment `lcd_sent_chars` in order to send the next character
lcd_sent_chars_nxt <= lcd_sent_chars + to_unsigned(1, lcd_sent_chars'length);
end if;
end if;
end case;
end process;
-- UART process
process(uart_state, uart_wr_array, uart_rd_array, uart_sent_bytes, uart_received_bytes, uart_irq_tx, uart_irq_rx, uart_din,
peripherals_ventilation_on, peripherals_heating_on, peripherals_lighting_on, peripherals_watering_on, moist_moisture, moist_temperature, light_value, adc_carbondioxide,
heating_thresh, lighting_thresh, watering_thresh)
constant VALUE_COUNT : natural := 5; -- amount of data segments (four segments for each sensor + one segment including all states (on/off) of peripherals)
constant SEGMENT_COUNT : natural := 3; -- 3 bytes per "segment"
variable i, j : natural := 0; -- loop variables
variable segment_cmd : std_ulogic_vector(1 downto 0);
variable segment_data : std_ulogic_vector(SEGMENT_COUNT * UART_DATA_WIDTH - 1 downto 0);
variable item : uart_protocol_entry_t;
variable segment_value : std_ulogic_vector(15 downto 0);
begin
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
-- hold values
uart_state_nxt <= uart_state;
uart_sent_bytes_nxt <= uart_sent_bytes;
uart_received_bytes_nxt <= uart_received_bytes;
uart_rd_array_nxt <= uart_rd_array;
uart_wr_array_nxt <= uart_wr_array;
lighting_thresh_nxt <= lighting_thresh;
watering_thresh_nxt <= watering_thresh;
heating_thresh_nxt <= heating_thresh;
case uart_state is
when S_UART_RD_WAIT_START =>
if uart_irq_rx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_RX;
uart_wr <= '0';
-- save data
if uart_din(7 downto 0) = "01000000" then
uart_received_bytes_nxt <= to_unsigned(0, uart_received_bytes'length);
uart_rd_array_nxt <= (others => (others => (others => '0')));
uart_state_nxt <= S_UART_RD_READ_LOOP;
end if;
end if;
when S_UART_RD_READ_LOOP =>
if uart_irq_rx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_RX;
uart_wr <= '0';
-- increment counter
uart_received_bytes_nxt <= uart_received_bytes + to_unsigned(1, uart_received_bytes'length);
if uart_din(7 downto 0) = "00111111" then
-- received end command
if uart_received_bytes = to_unsigned(UART_RD_BYTE_COUNT, uart_received_bytes'length) then
for i in 0 to 2 loop
if uart_rd_array(i*3).cmd = "10" or uart_rd_array(i*3).cmd = "11" then
segment_value := uart_rd_array(i*3).data & uart_rd_array(i*3+1).data & uart_rd_array(i*3+2).data(5 downto 2);
if uart_rd_array(i*3+2).data(1 downto 0) = "00" then
lighting_thresh_nxt <= unsigned(segment_value);
elsif uart_rd_array(i*3+2).data(1 downto 0) = "01" then
watering_thresh_nxt <= unsigned(segment_value);
elsif uart_rd_array(i*3+2).data(1 downto 0) = "10" then
heating_thresh_nxt <= resize(unsigned(segment_value), heating_thresh'length);
end if;
end if;
end loop;
end if;
uart_state_nxt <= S_UART_WR_START;
else
uart_rd_array_nxt(to_integer(uart_received_bytes)) <= (
uart_din(7 downto 6), -- cmd
uart_din(5 downto 0) -- data
);
end if;
end if;
when S_UART_WR_START =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
-- write `start` cmd
uart_dout(7 downto 0) <= "01000000";
-- assign sensor values to protocol
for i in 0 to VALUE_COUNT - 1 loop
if i = 0 then
segment_cmd := "10";
segment_data := std_ulogic_vector(resize(light_value, segment_data'length - 2)) & "00";
elsif i = 1 then
segment_cmd := "11";
segment_data := std_ulogic_vector(moist_moisture) & "01";
elsif i = 2 then
segment_cmd := "10";
segment_data := std_ulogic_vector(moist_temperature) & "10";
elsif i = 3 then
segment_cmd := "11";
segment_data := std_ulogic_vector(resize(adc_carbondioxide, segment_data'length - 2)) & "11";
else
segment_cmd := "10";
segment_data := std_ulogic_vector(shift_left(resize(unsigned'(peripherals_lighting_on & peripherals_watering_on & peripherals_heating_on & peripherals_ventilation_on & "00"), segment_data'length), 12));
end if;
for j in 0 to SEGMENT_COUNT - 1 loop
if i < 4 or j = 0 then
uart_wr_array_nxt(j + i * SEGMENT_COUNT) <= (
segment_cmd, -- cmd
std_ulogic_vector(resize(shift_right(unsigned(segment_data), (2 - j) * UART_DATA_WIDTH), UART_DATA_WIDTH)) -- data
);
end if;
end loop;
end loop;
uart_state_nxt <= S_UART_WR_WRITE_LOOP;
end if;
when S_UART_WR_WRITE_LOOP =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
item := uart_wr_array(to_integer(uart_sent_bytes));
uart_dout(7 downto 0) <= item.cmd & item.data;
if uart_sent_bytes = to_unsigned(UART_WR_BYTE_COUNT - 1, uart_sent_bytes'length) then
-- last byte sent
uart_sent_bytes_nxt <= (others => '0'); -- reset counter
uart_state_nxt <= S_UART_WR_END;
else
-- increment counter
uart_sent_bytes_nxt <= uart_sent_bytes + to_unsigned(1, uart_sent_bytes'length);
end if;
end if;
when S_UART_WR_END =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
-- write `end` cmd
uart_dout(7 downto 0) <= "00111111";
uart_state_nxt <= S_UART_RD_WAIT_START;
end if;
end case;
end process;
-- Seven Segment process
process(seg_state, seg_clock, adc_temperature, moist_address)
begin
seg_state_nxt <= seg_state;
seg_clock_nxt <= seg_clock;
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= CV_ADDR_SEVENSEG_DEC;
sevenseg_dout <= (others => '0');
case seg_state is
when S_SEG_WAIT =>
if seg_clock = to_unsigned(SEG_CLOCK_TICKS - 1, seg_clock'length) then
seg_clock_nxt <= (others => '0');
seg_state_nxt <= S_SEG_DISPLAY_DEC;
else
seg_clock_nxt <= seg_clock + to_unsigned(1, seg_clock'length);
end if;
when S_SEG_DISPLAY_DEC =>
sevenseg_cs <= '1';
sevenseg_wr <= '1';
sevenseg_dout <= std_ulogic_vector(resize(adc_temperature, sevenseg_dout'length));
seg_state_nxt <= S_SEG_DISPLAY_HEX;
when S_SEG_DISPLAY_HEX =>
sevenseg_cs <= '1';
sevenseg_wr <= '1';
sevenseg_addr <= CV_ADDR_SEVENSEG_HEX4 or CV_ADDR_SEVENSEG_HEX5;
sevenseg_dout <= std_ulogic_vector("000000000" & moist_address);
seg_state_nxt <= S_SEG_WAIT;
end case;
end process;
-- unused signals
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
end rtl;
| apache-2.0 | dcb3d61ad4430c1c1360f9dd4326d98e | 0.629593 | 2.719751 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_audio_adc_to_gain.vhdl | 1 | 12,897 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Jan Dürre
-- Year : 2013
-- Description : This example uses adc-channel 0 as gain-control
-- for audio pass-through. Two independent FSMs are
-- required, since the lcd is too slow for 44,1kHz
-- sampling rate.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register for audio control
type state_audio_t is (S_INIT, S_WAIT_SAMPLE, S_ADC_READ, S_WRITE_SAMPLE_LEFT, S_WRITE_SAMPLE_RIGHT, S_WRITE_CONFIG);
signal state_audio, state_audio_nxt : state_audio_t;
-- state register for lcd control
type state_lcd_t is (S_WAIT_LCD, S_PRINT_CHARACTERS, S_WAIT_FOR_NEW_GAIN);
signal state_lcd, state_lcd_nxt : state_lcd_t;
-- register to save audio-sample
signal sample, sample_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
-- register to save adc-value
signal adc_value, adc_value_nxt : std_ulogic_vector(11 downto 0);
-- signals to communicate between fsms
signal lcd_refresh, lcd_refresh_nxt : std_ulogic;
signal lcd_refresh_ack : std_ulogic;
-- array of every single character to print out to the lcd
signal lcd_cmds, lcd_cmds_nxt : lcd_commands_t(0 to 12);
-- counter
signal char_count, char_count_nxt : unsigned(to_log2(lcd_cmds'length)-1 downto 0);
begin
-- sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
state_audio <= S_INIT;
sample <= (others => '0');
adc_value <= (others => '0');
lcd_refresh <= '0';
state_lcd <= S_WAIT_LCD;
lcd_cmds <= lcd_cmd(lcd_cursor_pos(0, 0) & asciitext("Volume: XXX%"));
char_count <= (others => '0');
elsif rising_edge(clock) then
state_audio <= state_audio_nxt;
sample <= sample_nxt;
adc_value <= adc_value_nxt;
lcd_refresh <= lcd_refresh_nxt;
state_lcd <= state_lcd_nxt;
lcd_cmds <= lcd_cmds_nxt;
char_count <= char_count_nxt;
end if;
end process;
-- audio data-path (combinational process contains logic only)
process(state_audio, state_lcd, key, adc_dac_din, audio_din, audio_irq_left, audio_irq_right, lcd_refresh, lcd_refresh_ack, sample, adc_value, switch)
begin
-- default assignment
-- leds
led_green <= (others => '0');
-- adc/dac interface
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
-- audio interface
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
-- communication between fsms
lcd_refresh_nxt <= lcd_refresh;
-- hold previous values of all registers
state_audio_nxt <= state_audio;
sample_nxt <= sample;
adc_value_nxt <= adc_value;
-- reset lcd_refresh if lcd-fsm acks request
if lcd_refresh_ack = '1' then
lcd_refresh_nxt <= '0';
end if;
-- audio data-path
case state_audio is
-- initial state
when S_INIT =>
led_green(0) <= '1';
-- wait for key 0 to start work
if key(0) = '1' then
-- activate ADC channel 0
adc_dac_cs <= '1';
adc_dac_wr <= '1';
adc_dac_addr <= CV_ADDR_ADC_DAC_CTRL;
adc_dac_dout(9 downto 0) <= "0000000001";
-- next state
state_audio_nxt <= S_WAIT_SAMPLE;
end if;
-- wait for audio-interrupt signals to indicate new audio-sample
when S_WAIT_SAMPLE =>
led_green(1) <= '1';
-- new audio sample on left or right channel detected
if (audio_irq_left = '1') or (audio_irq_right = '1') then
-- start reading adc-value
state_audio_nxt <= S_ADC_READ;
end if;
-- read adc value
when S_ADC_READ =>
led_green(2) <= '1';
-- chip select for adc/dac-interface
adc_dac_cs <= '1';
-- read mode
adc_dac_wr <= '0';
-- address of adc-channel 0
adc_dac_addr <= CV_ADDR_ADC0;
-- if adc-value has changed:
if adc_dac_din(11 downto 0) /= adc_value then
-- save adc-value of selected channel to register
adc_value_nxt <= adc_dac_din(11 downto 0);
-- initiate rewrite of lcd display
lcd_refresh_nxt <= '1';
end if;
-- choose correct audio channel
if audio_irq_left = '1' then
-- chip select for audio-interface
audio_cs <= '1';
-- read mode
audio_wr <= '0';
-- acknowledge interrupt
audio_ack_left <= '1';
-- set address for left channel
audio_addr <= CV_ADDR_AUDIO_LEFT_IN;
-- save sample to register
sample_nxt <= audio_din;
-- next state
state_audio_nxt <= S_WRITE_SAMPLE_LEFT;
end if;
if audio_irq_right = '1' then
-- chip select for audio-interface
audio_cs <= '1';
-- read mode
audio_wr <= '0';
-- acknowledge interrupt
audio_ack_right <= '1';
-- set address for right channel
audio_addr <= CV_ADDR_AUDIO_RIGHT_IN;
-- save sample to register
sample_nxt <= audio_din;
-- next state
state_audio_nxt <= S_WRITE_SAMPLE_RIGHT;
end if;
-- write new sample to left channel
when S_WRITE_SAMPLE_LEFT =>
led_green(5) <= '1';
-- chip select for audio-interface
audio_cs <= '1';
-- write mode
audio_wr <= '1';
-- set address for left channel
audio_addr <= CV_ADDR_AUDIO_LEFT_OUT;
-- write sample * gain-factor to audio-interface
audio_dout <= std_ulogic_vector(resize(shift_right(signed(sample) * signed('0' & adc_value(11 downto 4)), 7), audio_dout'length));
-- write config to acodec
state_audio_nxt <= S_WRITE_CONFIG;
-- write new sample to right channel
when S_WRITE_SAMPLE_RIGHT =>
led_green(6) <= '1';
-- chip select for audio-interface
audio_cs <= '1';
-- write mode
audio_wr <= '1';
-- set address for right channel
audio_addr <= CV_ADDR_AUDIO_RIGHT_OUT;
-- write sample * gain-factor to audio-interface
audio_dout <= std_ulogic_vector(resize(shift_right(signed(sample) * signed('0' & adc_value(11 downto 4)), 7), audio_dout'length));
-- write config to acodec
state_audio_nxt <= S_WRITE_CONFIG;
when S_WRITE_CONFIG =>
led_green(7) <= '1';
-- chip select for audio-interface
audio_cs <= '1';
-- write mode
audio_wr <= '1';
-- set address for config register
audio_addr <= CV_ADDR_AUDIO_CONFIG;
-- set mic boost & in-select
audio_dout <= "00000000000000" & switch(1) & switch(0);
-- back to wait-state
state_audio_nxt <= S_WAIT_SAMPLE;
end case;
end process;
-- lcd control (combinational process contains logic only)
process(state_lcd, lcd_cmds, char_count, lcd_din, lcd_irq_rdy, lcd_refresh, adc_value)
variable bcd_value : unsigned(11 downto 0) := (others => '0');
variable adc_recalc : std_ulogic_vector(11 downto 0) := (others => '0');
begin
-- default assignment
-- leds
led_red <= (others => '0');
-- lcd interface
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
-- communication between FSMs
lcd_refresh_ack <= '0';
--registers
state_lcd_nxt <= state_lcd;
lcd_cmds_nxt <= lcd_cmds;
char_count_nxt <= char_count;
-- second state machine to generate output on lcd-screen
case state_lcd is
-- wait for lcd-interface to be 'not busy' / finished writing old commands to lcd
when S_WAIT_LCD =>
led_red(0) <= '1';
-- chip select for lcd-interface
lcd_cs <= '1';
-- read mode
lcd_wr <= '0';
-- set address for status
lcd_addr <= CV_ADDR_LCD_STATUS;
-- start printing characters
if lcd_din(0) = '0' then
state_lcd_nxt <= S_PRINT_CHARACTERS;
end if;
-- send characters to lcd-interface
when S_PRINT_CHARACTERS =>
led_red(1) <= '1';
-- lcd ready for data
if lcd_irq_rdy = '1' then
-- chip select for lcd-interface
lcd_cs <= '1';
-- write mode
lcd_wr <= '1';
-- set address for data register of lcd
lcd_addr <= CV_ADDR_LCD_DATA;
-- select character from lcd-commands-array
lcd_dout(7 downto 0) <= lcd_cmds(to_integer(char_count));
-- decide if every character has been sent
if char_count = lcd_cmds'length-1 then
state_lcd_nxt <= S_WAIT_FOR_NEW_GAIN;
-- continue sending characters to lcd-interface
else
char_count_nxt <= char_count + 1;
end if;
end if;
when S_WAIT_FOR_NEW_GAIN =>
led_red(2) <= '1';
-- write new value, only when adc value has changed
if lcd_refresh = '1' then
-- ack refresh request
lcd_refresh_ack <= '1';
-- calculate gain-value
adc_recalc := std_ulogic_vector(resize(shift_right( unsigned(adc_value(11 downto 4)) * 200,8), adc_recalc'length));
bcd_value := unsigned(to_bcd(adc_recalc, 3));
-- generate lcd-commands
lcd_cmds_nxt <= lcd_cmd(lcd_cursor_pos(0, 0) & asciitext("Volume: ") & ascii(bcd_value(11 downto 8)) & ascii(bcd_value(7 downto 4)) & ascii(bcd_value(3 downto 0)) & asciitext("%"));
-- reset char counter
char_count_nxt <= (others => '0');
-- start writing to lcd
state_lcd_nxt <= S_WAIT_LCD;
end if;
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 | 679d764a8a0aff6fe9c1881f505fbb29 | 0.600217 | 2.842627 | false | false | false | false |
J-Rios/VHDL_Modules | 3.Peripherals/Debounced_Input/TOP.vhd | 1 | 909 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity TOP is
port
(
CLK : in STD_LOGIC;
SW : in STD_LOGIC_VECTOR (15 downto 0);
BTN : in STD_LOGIC_VECTOR (4 downto 0);
);
end TOP;
-------------------------------------------------------------------------
architecture BEHAVIORAL of TOP is
signal db : STD_LOGIC;
signal tick_sw : STD_LOGIC;
begin
-- Debounce module
miDEB : entity WORK.DEBOUNCE port map
(
c => CLK,
r => BTN(0),
sw => SW(0), -- Switch input (it can be buttons or switches)
db => db
);
-- Edge detection module
myED : entity WORK.edge_detect port map
(
c => MCLK,
level => db,
tick => tick_sw -- Switch output debounced
);
end BEHAVIORAL;
| gpl-3.0 | 67dce8486840520a421cc0a29e8d4069 | 0.455446 | 4.18894 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/and/myAnd16_tb.vhdl | 1 | 1,370 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myAnd16_tb is
end myAnd16_tb;
architecture behavioral of myAnd16_tb is
component myAnd16
port(a: in std_logic_vector(15 downto 0); b: in std_logic_vector(15 downto 0); s: out std_logic_vector(15 downto 0));
end component;
-- signals used for testing
signal s1: std_logic_vector(15 downto 0);
signal s2: std_logic_vector(15 downto 0);
signal o1: std_logic_vector(15 downto 0);
begin
-- component instantiation
myAnd16_1: myAnd16 port map(a => s1, b => s2, s => o1);
process
begin
s1 <= "0000000000000000";
s2 <= "0000000000000000";
wait for 1 ns;
assert o1 = "0000000000000000" report "and('0000000000000000', '0000000000000000') was not '0000000000000000'" severity error;
s1 <= "1111111100000000";
s2 <= "1111111100000000";
wait for 1 ns;
assert o1 = "1111111100000000" report "and('1111111100000000', '1111111100000000') was not '1111111100000000'" severity error;
s1 <= "1111111111111111";
s2 <= "1111111111111111";
wait for 1 ns;
assert o1 = "1111111111111111" report "and('1111111111111111', '1111111111111111') was not '1111111111111111'" severity error;
assert false report "test complete" severity note;
wait;
end process;
end behavioral;
| mit | cf1b54b67420474746cd582a5ac73443 | 0.655474 | 4.005848 | false | false | false | false |
Fju/LeafySan | src/vhdl/testbench/dac_model.vhdl | 1 | 2,537 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : DAC Model
-- Last update : 02.12.2013
-----------------------------------------------------------------
-- Libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity dac_model is
generic(
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
FILE_NAME_DUMP : string := "dac_dump.txt"
);
port(
-- Global Signals
end_simulation : in std_ulogic;
-- SPI Signals
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_cs_n : in std_ulogic;
-- DAC Signals
dac_ldac_n : in std_ulogic
);
end entity dac_model;
architecture sim of dac_model is
type dac_reg_t is array (0 to 1) of real;
signal rx : std_ulogic_vector(15 downto 0);
file file_dump : text open write_mode is FILE_NAME_DUMP;
begin
process
variable vref : real := 2.048;
variable dac_out : dac_reg_t;
variable dac_pre : dac_reg_t;
variable v_out : string(1 to 4);
variable outLine : line;
begin
dac_out := (others => (real(0)));
dac_pre := (others => (real(0)));
rx <= (others => '0');
loop
exit when end_simulation = '1';
if spi_cs_n = '0' then
for i in 0 to 15 loop
wait until spi_clk = '1';
rx <= rx(14 downto 0) & spi_mosi;
wait until spi_clk = '0';
end loop;
wait until spi_cs_n = '1';
if rx(13) = '1' then
dac_pre(to_integer(unsigned(rx(15 downto 15)))) := vref * real(to_integer(unsigned(rx(11 downto 4)))) / real(256);
else
dac_pre(to_integer(unsigned(rx(15 downto 15)))) := real(2) * vref * real(to_integer(unsigned(rx(11 downto 4)))) / real(256);
end if;
if dac_pre(to_integer(unsigned(rx(15 downto 15)))) > real(3.3) then
dac_pre(to_integer(unsigned(rx(15 downto 15)))) := real(3.3);
end if;
else
wait for SYSTEM_CYCLE_TIME;
end if;
if dac_ldac_n = '0' then
for i in 0 to 1 loop
if dac_pre(i) /= dac_out(i) then
dac_out(i) := dac_pre(i);
v_out := integer'image(integer(dac_out(i)*real(1000)));
write(outLine, "DAC" & integer'image(i) & " = " & v_out(1) & "." & v_out(2 to 4) & "V");
writeline(file_dump, outLine);
write(outLine, "[DAC] Setting output voltage of DAC" & integer'image(i) & " to " & v_out(1) & "." & v_out(2 to 4) & "V");
writeline(output, outLine);
end if;
end loop;
end if;
end loop;
file_close(file_dump);
wait;
end process;
end architecture sim; | apache-2.0 | da986e57623681a44509e30e1861234d | 0.560899 | 2.856982 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_lcd_test_switch_commands.vhdl | 1 | 6,072 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Christian Leibold
-- Year : 2013
-- Description : With this example it is possible to generate
-- control-commands for the LCD-Display by using
-- switch 0 to 7. The command is send by pressing
-- key 0.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register
type state_t is (S_WAIT_KEY_PRESS, S_SEND_DATA, S_WAIT_KEY_RELEASE);
signal state, state_nxt : state_t;
begin
-- sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
state <= S_WAIT_KEY_PRESS;
elsif rising_edge(clock) then
state <= state_nxt;
end if;
end process;
-- combinational process contains logic only
process(state, lcd_irq_rdy, key, switch)
begin
-- set default values for the internal bus -> zero on all signals means, nothing will happen
lcd_cs <= '0';
lcd_wr <= '0';
lcd_dout <= (others => '0');
lcd_addr <= (others => '0');
lcd_ack_rdy <= '0';
-- hold previous values of all registers
state_nxt <= state;
case state is
-- Wait until KEY0 is triggered
when S_WAIT_KEY_PRESS =>
if key(0) = '1' then
-- next state
state_nxt <= S_SEND_DATA;
end if;
-- Read value from ADC and save it into the led_out-register
when S_SEND_DATA =>
if lcd_irq_rdy = '1' then
-- Enable the Chip-Select signal for the LCD-Module
lcd_cs <= '1';
-- Enable the Write-Select signal
lcd_wr <= '1';
-- Set address of the LCD interface to print a character
lcd_addr <= CV_ADDR_LCD_DATA;
-- Take the new data from the first eight switches (SW0 to SW7)
lcd_dout(7 downto 0) <= switch(7 downto 0);
-- next state
state_nxt <= S_WAIT_KEY_RELEASE;
end if;
-- Wait until KEY0 is released
when S_WAIT_KEY_RELEASE =>
if key(0) = '0' then
-- next state
state_nxt <= S_WAIT_KEY_PRESS;
end if;
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
led_green <= (others => '0');
led_red <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 | d36966c0acb3e612feaa0b56efe8b5f5 | 0.583827 | 2.660824 | false | false | false | false |
Fju/LeafySan | src/vhdl/interfaces/adc_dac.vhdl | 1 | 11,546 | -----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : ADC/DAC Communication for the extension board
-- Author : Christian Leibold / Jan Dürre
-- Last update : 24.03.2014
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity adc_dac is
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- adc/dac signals
-- spi signals
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
spi_miso : in std_ulogic;
spi_cs_dac_n : out std_ulogic;
spi_cs_adc_n : out std_ulogic;
-- switch signals
swt_select : out std_ulogic_vector(2 downto 0);
swt_enable_n : out std_ulogic;
-- dac Signals
dac_ldac_n : out std_ulogic
);
end adc_dac;
architecture rtl of adc_dac is
constant MUX_SWITCH_TIME : natural := 20;
constant ADC_COOLDOWN_TIME : natural := 4;
constant DAC_COOLDOWN_TIME : natural := 4;
component spi_master
port(
clock : in std_ulogic;
reset_n : in std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
spi_cs_n : out std_ulogic_vector(1 downto 0);
spi_miso : in std_logic;
spi_slaveid : in std_ulogic;
spi_trenable : in std_ulogic;
spi_txdata : in std_ulogic_vector(15 downto 0);
spi_rxdata : out std_ulogic_vector(15 downto 0);
spi_trcomplete : out std_ulogic
);
end component spi_master;
signal control_idx, control_idx_nxt : unsigned(to_log2(10)-1 downto 0);
signal control_reg, control_reg_nxt : std_ulogic_vector(9 downto 0); -- 8 adc + 2 dac
signal dac_control_last, dac_control_last_nxt : std_ulogic_vector(1 downto 0);
type adc_reg_t is array (0 to 7) of std_ulogic_vector(11 downto 0);
signal adc_reg, adc_reg_nxt : adc_reg_t;
type dac_reg_t is array (0 to 1) of std_ulogic_vector(7 downto 0);
signal dac_reg, dac_reg_nxt : dac_reg_t;
signal adc_select , adc_select_nxt : std_ulogic_vector(3 downto 0);
signal dac_select , dac_select_nxt : std_ulogic;
signal mux_switch_cnt, mux_switch_cnt_nxt : unsigned(to_log2(MUX_SWITCH_TIME)-1 downto 0);
signal adc_cooldown_cnt, adc_cooldown_cnt_nxt : unsigned(to_log2(ADC_COOLDOWN_TIME)-1 downto 0);
signal dac_cooldown_cnt, dac_cooldown_cnt_nxt : unsigned(to_log2(DAC_COOLDOWN_TIME)-1 downto 0);
type state_t is (S_INIT, S_CONTROL, S_ADC_MUX_SWITCH, S_ADC_READ, S_ADC_WAIT, S_ADC_COOLDOWN, S_DAC_SET, S_DAC_WAIT, S_DAC_COOLDOWN, S_DAC_SHUTDOWN);
signal state, state_nxt : state_t;
signal txdata, rxdata : std_ulogic_vector(15 downto 0);
signal trcomplete : std_ulogic;
signal slaveid : std_ulogic;
signal trenable : std_ulogic;
signal mux_select : std_ulogic_vector(2 downto 0);
signal spi_cs_n : std_ulogic_vector(1 downto 0);
begin
spi_inst : spi_master
port map(
clock => clock,
reset_n => reset_n,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
spi_cs_n => spi_cs_n,
spi_miso => spi_miso,
spi_slaveid => slaveid,
spi_trenable => trenable,
spi_txdata => txdata,
spi_rxdata => rxdata,
spi_trcomplete => trcomplete
);
spi_cs_adc_n <= spi_cs_n(0);
spi_cs_dac_n <= spi_cs_n(1);
process(clock, reset_n)
begin
if reset_n = '0' then
control_idx <= (others => '0');
control_reg <= (others => '0');
dac_control_last <= (others => '1');
adc_reg <= (others => (others => '0'));
dac_reg <= (others => (others => '0'));
adc_select <= (others => '0');
dac_select <= '0';
mux_switch_cnt <= (others => '0');
adc_cooldown_cnt <= (others => '0');
dac_cooldown_cnt <= (others => '0');
state <= S_INIT;
elsif rising_edge(clock) then
control_idx <= control_idx_nxt;
control_reg <= control_reg_nxt;
dac_control_last <= dac_control_last_nxt;
adc_reg <= adc_reg_nxt;
dac_reg <= dac_reg_nxt;
adc_select <= adc_select_nxt;
dac_select <= dac_select_nxt;
mux_switch_cnt <= mux_switch_cnt_nxt;
adc_cooldown_cnt <= adc_cooldown_cnt_nxt;
dac_cooldown_cnt <= dac_cooldown_cnt_nxt;
state <= state_nxt;
end if;
end process;
process(state, trcomplete, rxdata, control_idx, control_reg, adc_reg, dac_reg, adc_select, dac_select, mux_switch_cnt, adc_cooldown_cnt, dac_cooldown_cnt, dac_control_last)
begin
txdata <= (others => '0');
trenable <= '0';
slaveid <= '0';
state_nxt <= state;
control_idx_nxt <= control_idx;
dac_control_last_nxt <= dac_control_last;
adc_reg_nxt <= adc_reg;
adc_select_nxt <= adc_select;
dac_select_nxt <= dac_select;
mux_switch_cnt_nxt <= mux_switch_cnt;
adc_cooldown_cnt_nxt <= adc_cooldown_cnt;
dac_cooldown_cnt_nxt <= dac_cooldown_cnt;
case state is
when S_INIT =>
state_nxt <= S_CONTROL;
control_idx_nxt <= (others => '0');
adc_select_nxt <= (others => '0');
when S_CONTROL =>
-- control index counter
if control_idx < to_unsigned(10-1, control_idx'length) then
control_idx_nxt <= control_idx + 1;
else
control_idx_nxt <= (others => '0');
end if;
-- choose next state
-- adc
if control_idx < to_unsigned(8, control_idx'length) then
if control_reg(to_integer(control_idx)) = '1' then
adc_select_nxt <= std_ulogic_vector(control_idx(adc_select'range));
mux_switch_cnt_nxt <= (others => '0');
state_nxt <= S_ADC_MUX_SWITCH;
end if;
-- dac
else
if control_idx = to_unsigned(8, control_idx'length) then
if control_reg(8) = '0' and dac_control_last(0) = '1' then
dac_control_last_nxt(0) <= '0';
state_nxt <= S_DAC_SHUTDOWN;
elsif control_reg(8) = '1' then
dac_control_last_nxt(0) <= '1';
state_nxt <= S_DAC_SET;
end if;
dac_select_nxt <= '0';
else
if control_reg(9) = '0' and dac_control_last(1) = '1' then
dac_control_last_nxt(1) <= '0';
state_nxt <= S_DAC_SHUTDOWN;
elsif control_reg(9) = '1' then
dac_control_last_nxt(1) <= '1';
state_nxt <= S_DAC_SET;
end if;
dac_select_nxt <= '1';
end if;
end if;
when S_ADC_MUX_SWITCH =>
-- wait for mux to switch
if mux_switch_cnt < to_unsigned(MUX_SWITCH_TIME,mux_switch_cnt'length) then
mux_switch_cnt_nxt <= mux_switch_cnt + 1;
-- start read of adc
else
state_nxt <= S_ADC_READ;
end if;
when S_ADC_READ =>
-- request spi-data from adc
trenable <= '1';
slaveid <= '0';
state_nxt <= S_ADC_WAIT;
when S_ADC_WAIT =>
-- transfer finished
if trcomplete = '1' then
-- save data
adc_reg_nxt(to_integer(unsigned(adc_select))) <= rxData(12 downto 1);
-- set cooldown counter
adc_cooldown_cnt_nxt <= (others => '0');
state_nxt <= S_ADC_COOLDOWN;
end if;
when S_ADC_COOLDOWN =>
-- wait for adc cooldown
if adc_cooldown_cnt < to_unsigned(ADC_COOLDOWN_TIME, adc_cooldown_cnt'length) then
adc_cooldown_cnt_nxt <= adc_cooldown_cnt + 1;
-- back to control state
else
state_nxt <= S_CONTROL;
end if;
when S_DAC_SET =>
trenable <= '1';
slaveid <= '1'; -- DAC
txdata(15) <= dac_select;
txdata(13) <= '0';
txdata(12) <= '1';
if dac_select = '0' then
txdata(11 downto 4) <= dac_reg(0);
else
txdata(11 downto 4) <= dac_reg(1);
end if;
state_nxt <= S_DAC_WAIT;
when S_DAC_WAIT =>
if trcomplete = '1' then
dac_cooldown_cnt_nxt <= (others => '0');
state_nxt <= S_DAC_COOLDOWN;
end if;
when S_DAC_COOLDOWN =>
-- wait for dac cooldown
if dac_cooldown_cnt < to_unsigned(DAC_COOLDOWN_TIME, dac_cooldown_cnt'length) then
dac_cooldown_cnt_nxt <= dac_cooldown_cnt + 1;
-- back to control state
else
state_nxt <= S_CONTROL;
end if;
when S_DAC_SHUTDOWN =>
trenable <= '1';
slaveid <= '1'; -- DAC
txdata(15) <= dac_select;
txdata(13) <= '0';
txdata(12) <= '0'; -- shutdown_n
state_nxt <= S_DAC_WAIT;
end case;
end process;
swt_Select <= mux_select;
swt_Enable_n <= '1' when unsigned(control_reg(7 downto 0)) = 0 else -- no adc is activated
'0';
dac_ldac_n <= '0';
process(iobus_cs, iobus_wr, iobus_addr, iobus_din, adc_reg, dac_reg, control_reg)
begin
control_reg_nxt <= control_reg;
dac_reg_nxt <= dac_reg;
iobus_dout <= (others => '0');
if iobus_cs = '1' then
if iobus_wr = '1' then
if iobus_addr = CV_ADDR_DAC0 then
dac_reg_nxt(0) <= iobus_din(7 downto 0);
elsif iobus_addr = CV_ADDR_DAC1 then
dac_reg_nxt(1) <= iobus_din(7 downto 0);
elsif iobus_addr = CV_ADDR_ADC_DAC_CTRL then
control_reg_nxt <= iobus_din(control_reg'range);
end if;
else
if iobus_addr = CV_ADDR_DAC0 then
iobus_dout(7 downto 0) <= dac_reg(0);
elsif iobus_addr = CV_ADDR_DAC1 then
iobus_dout(7 downto 0) <= dac_reg(1);
elsif iobus_addr = CV_ADDR_ADC0 then
iobus_dout(11 downto 0) <= adc_reg(0);
elsif iobus_addr = CV_ADDR_ADC1 then
iobus_dout(11 downto 0) <= adc_reg(1);
elsif iobus_addr = CV_ADDR_ADC2 then
iobus_dout(11 downto 0) <= adc_reg(2);
elsif iobus_addr = CV_ADDR_ADC3 then
iobus_dout(11 downto 0) <= adc_reg(3);
elsif iobus_addr = CV_ADDR_ADC4 then
iobus_dout(11 downto 0) <= adc_reg(4);
elsif iobus_addr = CV_ADDR_ADC5 then
iobus_dout(11 downto 0) <= adc_reg(5);
elsif iobus_addr = CV_ADDR_ADC6 then
iobus_dout(11 downto 0) <= adc_reg(6);
elsif iobus_addr = CV_ADDR_ADC7 then
iobus_dout(11 downto 0) <= adc_reg(7);
elsif iobus_addr = CV_ADDR_ADC_DAC_CTRL then
iobus_dout(9 downto 0) <= control_reg;
end if;
end if;
end if;
end process;
process(adc_select)
variable sel : natural;
begin
sel := to_integer(unsigned(adc_select));
case sel is
when 0 => mux_select <= std_ulogic_vector(to_unsigned(7, mux_select'length));
when 1 => mux_select <= std_ulogic_vector(to_unsigned(2, mux_select'length));
when 2 => mux_select <= std_ulogic_vector(to_unsigned(5, mux_select'length));
when 3 => mux_select <= std_ulogic_vector(to_unsigned(1, mux_select'length));
when 4 => mux_select <= std_ulogic_vector(to_unsigned(6, mux_select'length));
when 5 => mux_select <= std_ulogic_vector(to_unsigned(0, mux_select'length));
when 6 => mux_select <= std_ulogic_vector(to_unsigned(4, mux_select'length));
when 7 => mux_select <= std_ulogic_vector(to_unsigned(3, mux_select'length));
when others => mux_select <= std_ulogic_vector(to_unsigned(7, mux_select'length));
end case;
end process;
end rtl; | apache-2.0 | e102dbd7d40ab7b058ee8c252809170d | 0.575091 | 2.751668 | false | false | false | false |
Fju/LeafySan | src/vhdl/utils/spi_master.vhdl | 1 | 4,456 | -----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : SPI Master
-- Author : Jan Dürre
-- Last update : 19.08.2014
-- Description : SPI Master Interface
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
port(
-- global signals
clock : in std_ulogic; -- 50MHz Clock
reset_n : in std_ulogic; -- Default High
-- spi signals
spi_clk : out std_ulogic; -- Signale die über den Expansion Header nach außen geführt werden
spi_mosi : out std_ulogic;
spi_cs_n : out std_ulogic_vector(1 downto 0);
spi_miso : in std_logic; -- Signale die über den Expansion Header rein kommen
-- interface signals
spi_slaveid : in std_ulogic;
spi_trenable : in std_ulogic; -- Triggern der Übertragung
spi_txdata : in std_ulogic_vector(15 downto 0); -- An den uC zu sendender Befehl, wird mit dem enable Signal übernommen
spi_rxdata : out std_ulogic_vector(15 downto 0); -- Vom uC erhaltenes Ergebnis, wird mit dem zurücknehmen des enable Signal übergeben
spi_trcomplete : out std_ulogic
);
end spi_master;
architecture rtl of spi_master is
component clock_generator
generic (
GV_CLOCK_DIV : natural
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
enable : in std_ulogic;
clock_out : out std_ulogic
);
end component clock_generator;
signal rx, rx_nxt : std_ulogic_vector(15 downto 0);
signal tx, tx_nxt : std_ulogic_vector(15 downto 0);
signal bit_cnt, bit_cnt_nxt : unsigned(3 downto 0);
signal spi_clk_now, spi_clk_last : std_ulogic;
signal spi_slave_id , spi_slave_id_nxt : std_ulogic;
signal activate_slave, activate_slave_nxt : std_ulogic;
type state_t is (S_IDLE, S_CLK_FALL, S_CLK_RISE, S_END_TRANSFER);
signal state, state_nxt : state_t;
begin
spiclkgen : clock_generator
generic map (
GV_CLOCK_DIV => 50 -- resulting in 1MHz
)
port map (
clock => clock,
reset_n => reset_n,
enable => activate_slave,
clock_out => spi_clk_now
);
process(clock, reset_n)
begin
if reset_n = '0' then
rx <= (others => '0');
tx <= (others => '0');
bit_cnt <= (others => '0');
spi_clk_last <= '0';
spi_slave_id <= '0';
activate_slave <= '0';
state <= S_IDLE;
elsif rising_edge(clock) then
rx <= rx_nxt;
tx <= tx_nxt;
bit_cnt <= bit_cnt_nxt;
spi_clk_last <= spi_clk_now;
spi_slave_id <= spi_slave_id_nxt;
activate_slave <= activate_slave_nxt;
state <= state_nxt;
end if;
end process;
process(state, rx, tx, bit_cnt, activate_slave, spi_clk_now, spi_clk_last, spi_miso, spi_trenable, spi_slave_id, spi_txdata, spi_slaveid)
begin
state_nxt <= state;
rx_nxt <= rx;
tx_nxt <= tx;
bit_cnt_nxt <= bit_cnt;
spi_slave_id_nxt <= spi_slave_id;
activate_slave_nxt <= activate_slave;
spi_trcomplete <= '0';
case state is
when S_IDLE =>
if spi_trenable = '1' then
rx_nxt <= (others => '0');
tx_nxt <= spi_txdata;
spi_slave_id_nxt <= spi_slaveid;
activate_slave_nxt <= '1';
bit_cnt_nxt <= (others => '0');
state_nxt <= S_CLK_RISE;
end if;
when S_CLK_RISE =>
if spi_clk_now = '1' and spi_clk_last = '0' then
rx_nxt <= rx(14 downto 0) & spi_miso;
bit_cnt_nxt <= bit_cnt + to_unsigned(1, bit_cnt'length);
state_nxt <= S_CLK_FALL;
end if;
when S_CLK_FALL =>
if spi_clk_now = '0' and spi_clk_last = '1' then
tx_nxt <= tx(14 downto 0) & '0';
state_nxt <= S_CLK_RISE;
if bit_cnt = to_unsigned(0, bit_cnt'length) then
state_nxt <= S_END_TRANSFER;
end if;
end if;
when S_END_TRANSFER =>
spi_trcomplete <= '1';
activate_slave_nxt <= '0';
state_nxt <= S_IDLE;
end case;
end process;
spi_clk <= spi_clk_now;
spi_mosi <= tx(15) when activate_slave = '1' else '0';
spi_cs_n(0) <= '0' when spi_slave_id = '0' and activate_slave = '1' else '1';
spi_cs_n(1) <= '0' when spi_slave_id = '1' and activate_slave = '1' else '1';
spi_rxdata <= rx when state = S_END_TRANSFER else (others => '0');
end architecture rtl; | apache-2.0 | 40c8d7cdfdff3999afa2daf6a924d754 | 0.563076 | 2.818124 | false | false | false | false |
Fju/LeafySan | src/vhdl/testbench/io_model.vhdl | 1 | 2,497 | ---------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : simple filebased model for GP-In, Switches & Pushbuttons
-- Last update : 27.04.2015
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity io_model is
generic(
-- file containing static bit-settings for io's
FILE_NAME_SET : string := "io.txt"
);
port(
-- io's
gpio : inout std_logic_vector(15 downto 0);
switch : out std_ulogic_vector(17 downto 0);
key : out std_ulogic_vector(2 downto 0)
);
end io_model;
architecture sim of io_model is
-- file containing static bit-settings for io's
-- order of bits: gp_in(0) ... gp_in(15), switch(0) ... switch(17), key_n(0) ... key_n(2)
file file_set : text open read_mode is FILE_NAME_SET;
begin
process
variable active_line : line;
variable neol : boolean := false;
variable char_value : character := '0';
variable cnt : natural := 0;
begin
-- preset io's
switch <= (others => 'U');
key <= (others => 'U');
-- read bit-settings file
while not endfile(file_set) loop
-- read line
readline(file_set, active_line);
-- loop until end of line
loop
-- read integer from line
read(active_line, char_value, neol);
-- exit when line has ended
exit when not neol;
-- chancel when enough data is read
exit when cnt = 16 + 18 + 3;
-- write data to output
if cnt < 16 then
-- gpio
if char_value = '1' then
gpio(cnt) <= '1';
elsif char_value = '0' then
gpio(cnt) <= '0';
elsif char_value = 'Z' then
gpio(cnt) <= 'Z';
else
gpio(cnt) <= 'U';
end if;
elsif cnt < 16 + 18 then
-- switch
if char_value = '1' then
switch(cnt-16) <= '1';
elsif char_value = '0' then
switch(cnt-16) <= '0';
else
switch(cnt-16) <= 'U';
end if;
else
-- key
if char_value = '1' then
key(cnt-16-18) <= '1';
elsif char_value = '0' then
key(cnt-16-18) <= '0';
else
key(cnt-16-18) <= 'U';
end if;
end if;
-- increment counter
cnt := cnt + 1;
end loop;
end loop;
file_close(file_set);
wait;
end process;
end sim;
| apache-2.0 | 467c351cdea538e08681dd5399f446e7 | 0.506207 | 3.152778 | false | false | false | false |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ts_7300_usercore.vhd | 1 | 13,033 | -------------------------------------------------------------------------------
--
-- Title : R4B user core
-- Design : r4b
-- Author : Bulent Selek
-- Company : Best Bilgisayar ve Elektronik Sanayi Ticaret
--
-------------------------------------------------------------------------------
--
-- File : ts7300_usercore.vhd
-- Generated : Fri Jan 8 13:22:36 2007
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Modified by Nigel Gunton
-- Company : Bristol Institute of Technology
-- version 1.0
-- full access to the DIO pins split into 3 registers plus output enable registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ts7300_usercore is
-- 75Mhz clock is fed to this module */
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_adr_i : in std_logic_vector ( 21 downto 0 );
wb_dat_i : in std_logic_vector ( 31 downto 0 );
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_dat_o : out std_logic_vector ( 31 downto 0 );
headerpin_i : in std_logic_vector( 40 downto 1 );
headerpin_o : out std_logic_vector( 40 downto 1 );
headerpin_oe_o : out std_logic_vector( 40 downto 1 );
irq_o : out std_logic;
-- SDRAM
sdram_ras_o : out std_logic; -- SDRAM row address strobe
sdram_cas_o : out std_logic; -- SDRAM column address strobe
sdram_we_n_o : out std_logic; -- SDRAM write enable
sdram_ba_o : out std_logic_vector( 1 downto 0 ); -- SDRAM bank address
sdram_saddr_o : out std_logic_vector( 11 downto 0 ); -- SDRAM row/column address
sdram_sdata_i : in std_logic_vector ( 15 downto 0 ); -- data from SDRAM
sdram_sdata_o : out std_logic_vector ( 15 downto 0 ); -- data to SDRAM
sdram_sdata_oe : out std_logic -- true if data is output to SDRAM on sDOut
);
end ts7300_usercore;
architecture ts7300_usercore of ts7300_usercore is
--- PWM Stuff ---
component pwm
port (
clk : in std_logic;
duty_cycle : in std_logic_vector(15 downto 0);
pwm_enable : in std_logic;
resetn : in std_logic;
pwm_out : out std_logic);
end component;
constant deadbeaf : std_logic_vector( 31 downto 0 ) := x"deadcafe";
signal vga_reg : std_logic_vector( 14 downto 0 ); -- only 14 downto 0 valid
signal dio2_reg : std_logic_vector( 15 downto 0 ); -- only 15 downto 0 valid
signal dummyreg : std_logic_vector( 31 downto 0 ); -- temporary reg
signal misc_reg : std_logic_vector( 3 downto 0 ); -- only 3 downto 0 valid
signal vga_enable : std_logic_vector( 14 downto 0 ); -- 1 = output enabled
signal dio2_enable : std_logic_vector( 15 downto 0 ); -- ditto
signal misc_enable : std_logic_vector( 3 downto 0 ); -- ditto
signal vga_read : std_logic_vector(14 downto 0); -- read from I/O pins
signal dio2_read : std_logic_vector(15 downto 0); -- ditto
signal misc_read : std_logic_vector(3 downto 0); -- ditto
signal DUTY_CYCLEA : std_logic_vector(15 downto 0) := X"006F";
signal DUTY_CYCLEB : std_logic_vector(15 downto 0) := X"006F";
signal DUTY_CYCLEC : std_logic_vector(15 downto 0) := X"006F";
signal DUTY_CYCLED : std_logic_vector(15 downto 0) := X"006F";
signal PWM_not_reset, PWM_enable_A, PWM_enable_B, PWM_enable_C, PWM_enable_D : std_logic := '1';
--- Read and write cycles of FPGA by and to the Processor
begin
process ( wb_clk_i )
variable addr : std_logic_vector ( 23 downto 0 );
begin
if ( wb_clk_i'event ) and ( wb_clk_i = '1' ) then
addr := "00" & wb_adr_i;
if (wb_cyc_i = '1' and wb_stb_i = '1' ) and ( wb_we_i = '1') then
-- WRITE CYCLE
case addr is
when x"280000" => vga_reg <= wb_dat_i(14 downto 0);
when x"280001" => vga_enable <= wb_dat_i(14 downto 0);
when x"280002" => dio2_reg <= wb_dat_i(15 downto 0);
when x"280003" => dio2_enable <= wb_dat_i(15 downto 0);
when x"280004" => misc_reg <= wb_dat_i(3 downto 0);
when x"280005" => misc_enable <= wb_dat_i(3 downto 0);
when x"280006" => DUTY_CYCLEA <= wb_dat_i(15 downto 0);
when x"280007" => DUTY_CYCLEB <= wb_dat_i(15 downto 0);
when x"280008" => DUTY_CYCLEC <= wb_dat_i(15 downto 0);
when x"280009" => DUTY_CYCLED <= wb_dat_i(15 downto 0);
when x"28000A" => PWM_enable_A <= wb_dat_i(0);
when x"28000B" => PWM_enable_B <= wb_dat_i(0);
when x"28000C" => PWM_enable_C <= wb_dat_i(0);
when x"28000D" => PWM_enable_D <= wb_dat_i(0);
when x"28000E" => PWM_not_reset <= wb_dat_i(0);
when others => null;
end case;
end if;
-- READ CYCLE
case addr is
when x"280000" => dummyreg <= "00000000000000000" & vga_read;
when x"280001" => dummyreg <= "00000000000000000" & vga_enable;
when x"280002" => dummyreg <= "0000000000000000" & dio2_read;
when x"280003" => dummyreg <= "0000000000000000" & dio2_enable;
when x"280004" => dummyreg <= "0000000000000000000000000000" & misc_read;
when x"280005" => dummyreg <= "0000000000000000000000000000" & misc_enable;
when x"280006" => dummyreg <= "0000000000000000" & DUTY_CYCLEA;
when x"280007" => dummyreg <= "0000000000000000" & DUTY_CYCLEB;
when x"280008" => dummyreg <= "0000000000000000" & DUTY_CYCLEC;
when x"280009" => dummyreg <= "0000000000000000" & DUTY_CYCLED;
when x"28000A" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_A;
when x"28000B" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_B;
when x"28000C" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_C;
when x"28000D" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_D;
when x"28000E" => dummyreg <= "0000000000000000000000000000000" & PWM_not_reset ;
when others => dummyreg <= x"deadbeef";
end case;
end if;
end process;
wb_ack_o <= wb_cyc_i and wb_stb_i; -- 0-wait state WISHBONE
wb_dat_o <= dummyreg;
irq_o <= '0';
-------------------------------------------------------------------------------
-- FPGA DIO output enable assignments: 40 downto 1
-- What follows is a pigs ear of assignments as the output enables are in pin
-- number order and the enable registers are in data name order
-------------------------------------------------------------------------------
headerpin_oe_o(1) <= vga_enable(0); -- blu0
headerpin_oe_o(3) <= vga_enable(1); -- blu1
headerpin_oe_o(5) <= vga_enable(2); -- blu2
headerpin_oe_o(7) <= vga_enable(3); -- blu3
headerpin_oe_o(9) <= vga_enable(4); -- blu4
headerpin_oe_o(11) <= vga_enable(5); -- grn0
headerpin_oe_o(13) <= vga_enable(6); -- grn1
headerpin_oe_o(15) <= vga_enable(7); -- grn2
headerpin_oe_o(17) <= vga_enable(8); -- grn3
headerpin_oe_o(4) <= vga_enable(10); -- red0
headerpin_oe_o(6) <= vga_enable(11); -- red1
headerpin_oe_o(8) <= vga_enable(12); -- red2
headerpin_oe_o(10) <= vga_enable(13); -- red3
headerpin_oe_o(12) <= vga_enable(14); -- red4
--headerpin_oe_o(19) <= '1';
headerpin_oe_o(21) <= '1';
headerpin_oe_o(23) <= '1';
headerpin_oe_o(25) <= '1';
headerpin_oe_o(29) <= '1';
-- headerpin_oe_o(29) <= dio2_enable(4); -- DIO2
headerpin_oe_o(31) <= dio2_enable(5); -- DIO2
headerpin_oe_o(33) <= dio2_enable(6); -- DIO2
headerpin_oe_o(35) <= dio2_enable(7); -- DIO2
headerpin_oe_o(37) <= dio2_enable(8); -- DIO2
-- THE FOLLOWING PIN IS DEDICATED CLK INPUT ONLY
-- headerpin_oe_o(39) <= dio2_enable(9); -- DIO2
headerpin_oe_o(24) <= dio2_enable(10); -- DIO2
headerpin_oe_o(26) <= dio2_enable(11); -- DIO2
headerpin_oe_o(28) <= dio2_enable(12); -- DIO2
headerpin_oe_o(30) <= dio2_enable(13); -- DIO2
headerpin_oe_o(32) <= dio2_enable(14); -- DIO2
headerpin_oe_o(34) <= dio2_enable(15); -- DIO2
headerpin_oe_o(14) <= misc_enable(0); -- HSYNC
headerpin_oe_o(16) <= misc_enable(1); -- VSYNC
headerpin_oe_o(36) <= misc_enable(2); -- RX_LD
headerpin_oe_o(38) <= misc_enable(3); -- TX_LD
-- the following MUST NOT be altered as they have dedicated use
headerpin_oe_o(2) <= '0'; -- GND
headerpin_oe_o(18) <= '0'; -- OEV
headerpin_oe_o(20) <= '0'; -- +5v fused
headerpin_oe_o(22) <= '0'; -- GND
headerpin_oe_o(39) <= '0'; -- external clk input only
headerpin_oe_o(40) <= '0'; -- +3.3v
-------------------------------------------------------------------------------
-- output assignments
-------------------------------------------------------------------------------
headerpin_o(1) <= vga_reg(0); --blu0
headerpin_o(3) <= vga_reg(1); --blu1
headerpin_o(5) <= vga_reg(2); --blu2
headerpin_o(6) <= vga_reg(3); --blu3
headerpin_o(7) <= vga_reg(4); --blu4
headerpin_o(11) <= vga_reg(5); --grn0
headerpin_o(13) <= vga_reg(6); --grn1
headerpin_o(15) <= vga_reg(7); --grn2
headerpin_o(17) <= vga_reg(8); --grn3
-- headerpin_o(29) <= dio2_reg(4); -- DIO2
headerpin_o(31) <= dio2_reg(5); -- DIO2
headerpin_o(33) <= dio2_reg(6); -- DIO2
headerpin_o(35) <= dio2_reg(7); -- DIO2
headerpin_o(37) <= dio2_reg(8); -- DIO2
-- THE FOLLOWING PIN IS INPUT ONLY
-- headerpin_o(39) <= dio2_reg(9); -- DIO2
headerpin_o(24) <= dio2_reg(10); -- DIO2
headerpin_o(26) <= dio2_reg(11); -- DIO2
headerpin_o(28) <= dio2_reg(12); -- DIO2
headerpin_o(30) <= dio2_reg(13); -- DIO2
headerpin_o(32) <= dio2_reg(14); -- DIO2
headerpin_o(34) <= dio2_reg(15); -- DIO2
headerpin_o(14) <= misc_reg(0); -- HSYNC
headerpin_o(16) <= misc_reg(1); -- VSYNC
headerpin_o(36) <= misc_reg(2); -- RX_LD
headerpin_o(38) <= misc_reg(3); -- TX_LD
-- just to keep synthesis warnings down ;)
headerpin_o(2) <= '0'; -- GND
headerpin_o(18) <= '0'; -- OEV
headerpin_o(20) <= '0'; -- +5v fused
headerpin_o(22) <= '0'; -- GND
headerpin_o(40) <= '0'; -- +3.3v
-----------------------------------------------------------------------------
-- read values on the IO pins; the special pins are handled in ts7300_top.v
-----------------------------------------------------------------------------
vga_read(0) <= headerpin_i(1); -- blu0
vga_read(1) <= headerpin_i(3); -- blu1
vga_read(2) <= headerpin_i(5); -- blu2
vga_read(3) <= headerpin_i(7); -- blu3
vga_read(4) <= headerpin_i(9); -- blu4
vga_read(5) <= headerpin_i(11); -- grn0
vga_read(6) <= headerpin_i(13); -- grn1
vga_read(7) <= headerpin_i(15); -- grn2
vga_read(8) <= headerpin_i(17); -- grn3
dio2_read(0) <= headerpin_i(21); -- DIO2
dio2_read(1) <= headerpin_i(23); -- DIO2
dio2_read(2) <= headerpin_i(25); -- DIO2
dio2_read(3) <= headerpin_i(27); -- DIO2
dio2_read(4) <= headerpin_i(29); -- DIO2
dio2_read(5) <= headerpin_i(31); -- DIO2
dio2_read(6) <= headerpin_i(33); -- DIO2
dio2_read(7) <= headerpin_i(35); -- DIO2
dio2_read(8) <= headerpin_i(37); -- DIO2
-- dio2_read(9) deliberately left out; see above
dio2_read(10) <= headerpin_i(24); -- DIO2
dio2_read(11) <= headerpin_i(26); -- DIO2
dio2_read(12) <= headerpin_i(28); -- DIO2
dio2_read(13) <= headerpin_i(30); -- DIO2
dio2_read(14) <= headerpin_i(32); -- DIO2
dio2_read(15) <= headerpin_i(34); -- DIO2
misc_read(0) <= headerpin_i(14); -- HSYNC
misc_read(1) <= headerpin_i(16); -- VSYNC
misc_read(2) <= headerpin_i(36); -- RX_LD but not a lot of point
misc_read(3) <= headerpin_i(38); -- TX_LD
PWM_1:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLEA,
pwm_enable => PWM_enable_A,--Enable_output_A,
resetn => PWM_not_reset,
pwm_out => headerpin_o(21));
PWM_2:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLEB,
pwm_enable => PWM_enable_B,--Enable_output_B,
resetn => PWM_not_reset,
pwm_out => headerpin_o(23));
PWM_3:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLEC,
pwm_enable => PWM_enable_C,--Enable_output_C,
resetn => PWM_not_reset,
pwm_out => headerpin_o(25));
PWM_4:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLED,
pwm_enable => PWM_enable_D,--Enable_output_D,
resetn => PWM_not_reset,
pwm_out => headerpin_o(29));
end ts7300_usercore;
| gpl-2.0 | 821a87fe3e47e2d441fc74bd599cccb8 | 0.533032 | 2.965415 | false | false | false | false |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/pwm.vhd | 1 | 2,840 | -------------------------------------------------------------------------------
-- Title : PWM for robot servos
-- Project :
-------------------------------------------------------------------------------
-- File : my_pwm.vhd
-- Author : <[email protected]>
-- Company : FoCEMS, UWE
-- Last update: 2011-03-28
-- Platform : Altera Quartus with std_arith library and DE0 board
-------------------------------------------------------------------------------
-- Description: A very simple example of a pwm hardware implementation. It has
-- three processes, one to divide the 50Mhz clock down to ~1khz, an eight bit
-- counter for the full cycle (at 1khz) and a loadable duty cycle register (8
-- bit). Button 0 is the reset, press to start. switches 7 to 0 are the load
-- value for the duty cycle register. Switch 9 is the pwm output enable. The
-- PWM output is connected to LED0 which will range from always on (100% duty)
-- to always off (0% duty). Enjoy.
--
-------------------------------------------------------------------------------
-- Revisions : 0
-- Date Version Author Description
-- 2007/02/07 1.0 ngunton Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_Arith.all;
entity pwm is
port (
clk : in std_logic;
duty_cycle : in std_logic_vector(15 downto 0);
pwm_enable : in std_logic;
resetn : in std_logic;
pwm_out : out std_logic);
end pwm;
architecture behavioural of pwm is
signal clock_div : unsigned(15 downto 0);
signal counter : unsigned(7 downto 0);
signal pwm_out_sig, slow_clk : std_logic;
signal duty_cycle_reg : unsigned(7 downto 0);
begin -- behavioural
-- purpose: control the pwm_out
-- type : sequential
-- inputs : slow_clk, resetn, pwm_enable
-- outputs: pwm_out_sig
pulse: process (slow_clk, resetn, pwm_enable)
begin -- process pulse
if resetn = '0' then -- asynchronous reset (active low)
pwm_out_sig <= '0';
duty_cycle_reg <= conv_unsigned(X"6F",8);
slow_clk <= '0'; -- Resets the clock
else
if clk'event and clk = '1' then
duty_cycle_reg <= unsigned(duty_cycle (7 downto 0));
if clock_div = conv_unsigned(X"0B00",16) then --clock speed
clock_div <= conv_unsigned(X"0000",16);
slow_clk <= not slow_clk; -- toggle
else
clock_div <= clock_div + 1;
end if;
end if;
if slow_clk'event and slow_clk = '1' then -- rising clock edge
counter <= counter +1;
if pwm_enable = '1' and (counter < conv_unsigned(duty_cycle_reg,8)) then
pwm_out_sig <= '1';
else
pwm_out_sig <= '0';
end if;
end if;
end if;
end process pulse;
pwm_out <= pwm_out_sig;
end behavioural; | gpl-2.0 | d4b5bef5ce999f44aa97eeb7590d0f1d | 0.544014 | 3.722149 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue2/Prelldemo/VDFF.vhd | 1 | 1,214 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:34:39 06/13/2016
-- Design Name:
-- Module Name: VDFF - Automat
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- vorderflankengetaktetes D-FF, D-Wechsel bei c+ wird NICHT registriert (ALT)
-- Automatenebene
-- Simulation: ok
-- Schaltung: nicht ok (ISE kann keine async. Schaltungen entwerfen)
entity VDFF is
Port ( R : in std_logic;
c : in std_logic;
Q : out std_logic;
nQ: out std_logic;
dummy : out std_logic);
end VDFF;
architecture Automat of VDFF is
signal Z: std_logic := '0';
begin
dummy <= c;
-- Zustandsberfhrungsfunktion (siehe Automat aus Lsung 7)
Delta: process (c,Z)
begin
if R = '1' then
Z <= '0';
elsif c'event and c = '1' then
Z <= not Z;
end if;
end process Delta;
-- Y auf Ausgabe-Port legen
Q <= Z;
nQ <= not Z;
end Automat;
| mit | cc5da0e62401b85a4a71401df5f1ec90 | 0.534596 | 3.186352 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sources_1/counter.vhd | 1 | 8,026 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter is
Generic ( Tlen : integer;
Ilen : integer;
measureinterval : integer );
Port ( timer : in STD_LOGIC;
input : in STD_LOGIC;
tcount : out UNSIGNED (Tlen-1 downto 0);
icount : out UNSIGNED (Ilen-1 downto 0);
-- overflow : out STD_LOGIC;
enable : in STD_LOGIC;
strobe : out STD_LOGIC;
rst : in STD_LOGIC);
end counter;
architecture Behavioral of counter is
type states is (ST_WAIT, ST_COUNTING, ST_FINISHING, ST_OVERFLOW);
-- *** input-based signals ***
signal input_en, input_en_next : std_logic;
signal M : unsigned (icount'range);
signal icount_int, icount_next : unsigned (icount'range); -- Main counter
signal iover, iover_next : std_logic; -- Overflow of the 'input' counter
signal istate, istate_next : states;
-- *** timer-based signals ***
signal timer_en, timer_en_next : std_logic;
signal N : unsigned (tcount'range);
signal tcount_int, tcount_next : unsigned (tcount'range); -- Main counter
signal sync_ien : std_logic_vector(1 downto 0); -- Synchronizer for 'input_en'
signal tover, tover_next: std_logic; -- Overflow of the 'timer' counter
signal tstate, tstate_next : states;
signal done, done_next : std_logic;
signal strobe_next : std_logic;
-- For synchronizing the 'done' signal into the 'input' clock domain
-- Introduces a significant delay when the frequency of 'input' is
-- low, possibly enough to cause the 'timer' counter to overflow.
-- It prevents metastability problems, however, and increasing the
-- measurement time will help accuracy.
signal sync_done : std_logic_vector(1 downto 0);
-- Likewise for the 'timer_en' signal
signal sync_ten : std_logic_vector(1 downto 0);
begin
icount <= icount_int;
tcount <= tcount_int;
-- overflow <= tover or iover;
-- 'input_en' needs to be available in the 'timer' domain so that
-- the 'timer' counter knows when to start and stop counting
process(rst,timer)
begin
if rst = '1' then
sync_ien <= (others => '0');
elsif rising_edge(timer) then
sync_ien <= sync_ien(0) & input_en;
end if;
end process;
-- Main FSM-type programming of the counter
comb : process(enable, input_en, sync_ien, icount_int, timer_en, sync_ten, tcount_int, done, sync_done, M, N, tover, iover, istate, tstate)
variable input_en_new, timer_en_new, done_new : std_logic;
variable tover_new, iover_new : std_logic;
variable istate_new, tstate_new : states;
begin
input_en_new := input_en;
timer_en_new := timer_en;
done_new := done;
tcount_next <= tcount_int;
icount_next <= icount_int;
tover_new := tover;
iover_new := iover;
strobe_next <= '0';
istate_new := istate;
tstate_new := tstate;
case istate is
when ST_WAIT =>
-- DANGER: crosses clock domain
-- 'timer_en' and 'done' is in the 'timer' domain
if sync_ten(1) = '0' and sync_done(1) = '0' then
istate_new := ST_COUNTING;
-- 'input' couter is started on rising edge of 'input'
input_en_new := '1';
end if;
when ST_COUNTING =>
-- On overflow, turn off counter and wait for timer to stop
if M + "1" = "0" then
istate_new := ST_OVERFLOW;
end if;
-- DANGER: crosses clock domain
-- input done is in the 'timer' domain
if sync_done(1) = '1' then
istate_new := ST_WAIT;
input_en_new := '0'; -- Disable the counter
icount_next <= M + "1"; -- Latch out the counter result
iover_new := '0'; -- Clear any overflow
end if;
when ST_OVERFLOW =>
iover_new := '1';
input_en_new := '0'; -- Disable the counter
istate_new := ST_WAIT;
when others =>
end case;
case tstate is
when ST_WAIT =>
done_new := '0';
if sync_ien(1) = '1' then
tstate_new := ST_COUNTING;
-- 'timer' couter is started on rising edge of 'timer'
timer_en_new := '1';
end if;
when ST_COUNTING =>
if N + "1" = "0" then
tstate_new := ST_OVERFLOW;
end if;
-- Indicate when the minimum measurement interval has been reached
if N = to_unsigned(measureinterval, N'length) then
tstate_new := ST_FINISHING;
done_new := '1';
end if;
when ST_FINISHING =>
if N + "1" = "0" then
tstate_new := ST_OVERFLOW;
end if;
-- If the timer's off, signal done and valid output
if timer_en = '0' then
-- done_new := '0';
strobe_next <= '1';
tstate_new := ST_WAIT;
-- Otherwise, turn off the timer when the input counter is off
elsif sync_ien(1) = '0' then
timer_en_new := '0'; -- Disable the counter
tcount_next <= N + "1"; -- Latch out the counter result
tover_new := '0'; -- Clear any overflow
end if;
when ST_OVERFLOW =>
timer_en_new := '0'; -- Disable the counter
tover_new := '1';
done_new := '1';
if sync_ien(1) = '0' then
strobe_next <= '1';
tstate_new := ST_WAIT;
end if;
when others =>
end case;
input_en_next <= input_en_new;
timer_en_next <= timer_en_new;
done_next <= done_new;
tover_next <= tover_new;
iover_next <= iover_new;
istate_next <= istate_new;
tstate_next <= tstate_new;
end process;
-- Processes synchronous to the 'timer' clock
tmem : process(rst, timer)
begin
if rst = '1' then
timer_en <= '0';
done <= '0';
N <= (others => '0');
tcount_int <= (others => '1'); -- Nonzero, avoids 1/0 fault
tover <= '0';
strobe <= '0';
tstate <= ST_WAIT;
elsif rising_edge(timer) then
if timer_en = '1' then
N <= N + "1";
else
N <= (others => '0');
end if;
timer_en <= timer_en_next;
done <= done_next;
tcount_int <= tcount_next;
tover <= tover_next;
strobe <= strobe_next;
tstate <= tstate_next;
end if;
end process;
-- Processes synchronous to the 'input' clock
imem : process(rst, input)
begin
if rst = '1' then
input_en <= '0';
M <= (others => '0');
icount_int <= (others => '0');
iover <= '0';
istate <= ST_WAIT;
sync_done <= (others => '0');
sync_ten <= (others => '0');
elsif rising_edge(input) then
if input_en = '1' then
M <= M + "1";
else
M <= (others => '0');
end if;
input_en <= input_en_next;
icount_int <= icount_next;
iover <= iover_next;
istate <= istate_next;
sync_done <= sync_done(0) & done;
sync_ten <= sync_ten(0) & timer_en;
end if;
end process;
end Behavioral;
| mit | 9976c465d444f0e93668b2c338e0c140 | 0.488786 | 4.013 | false | false | false | false |
maly/fpmi | FPGA/8080/l80pkg.vhd | 1 | 2,977 | --------------------------------------------------------------------------------
-- l80pkg.vhdl -- Support package for Light8080 SoC.
--
-- Contains functions used to initialize internal BRAM with object code.
--
-- This package will be used from the object code package where the program
-- initialized RAM constant is defined. If you use script obj2hdl it will
-- take care of this for you.
-- The package is used in entity l80soc too, and nowhere else.
--
-- This file and all the light8080 project files are freeware (See COPYING.TXT)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package l80pkg is
-- Basic array type for the declaration of initialization constants.
-- This type is meant to be used to declare a constant with the object code
-- that is to be preprogrammed in an initialized RAM.
type obj_code_t is array(integer range <>) of std_logic_vector(7 downto 0);
-- Basic array type for the definition of initialized RAMs.
type ram_t is array(integer range <>) of std_logic_vector(7 downto 0);
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
-- The object code is placed at the beginning of the BRAM and the rest is
-- filled with zeros.
-- CAN BE USED IN SYNTHESIZABLE CODE to compute a BRAM initialization constant
-- from a constant argument.
--
-- oC: Object code table (as generated by utility script obj2hdl for instance).
-- size: Size of the target memory.
-- Returns ram_t value size-bytes long, suitable for synth-time initialization
-- of a BRAM.
function objcode_to_bram(oC : obj_code_t; size : integer) return ram_t;
-- Compute log2(A), rounding up.
-- Use this to get the minimum width of the address bus necessary to
-- address A locations.
function log2(A : natural) return natural;
end package;
package body l80pkg is
-- Builds BRAM initialization constant from a constant CONSTRAINED byte array
-- containing the application object code.
function objcode_to_bram(oC : obj_code_t; size : integer) return ram_t is
variable br : ram_t(integer range 0 to size-1);
variable i : integer;
variable obj_size : integer;
begin
-- If the object code table is longer than the array size, truncate code
if oC'length > size then
obj_size := size;
else
obj_size := oC'length;
end if;
-- Copy object code to start of BRAM...
for i in 0 to obj_size-1 loop
br(i) := oC(i);
end loop;
-- ... and fill the rest with zeros
br(obj_size to size-1) := (others => x"00");
return br;
end function objcode_to_bram;
function log2(A : natural) return natural is
begin
for I in 1 to 30 loop -- Works for up to 32 bit integers
if(2**I >= A) then
return(I);
end if;
end loop;
return(30);
end function log2;
end package body;
| mit | 538b92f7feacaad45aa2ae8865cfb765 | 0.66913 | 3.948276 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | RegistratorePortatile.vhd | 1 | 22,108 | -- **********************************************************
-- Corso di Reti Logiche - "Mp3 Recorder" Project
-- Andrea Carrer - 729101
-- Module RegistratorePortatile.vhd
-- Version 1.02 - 18.03.2013
-- **********************************************************
-- **********************************************************
-- Main Module, written in VHDL.
-- Definisce la logica e le connessioni tra i diversi moduli:
-- - PlayRecord: gestione comandi registratore
-- - Display: gestione segnali grafica
-- - Audio_Controller: interfaccia con il chip WM8731
-- - VGA_Adapter: interfaccia con l'uscita VGA
-- - SDRAM: interfaccia con la SDRAM
-- E gestisce i componenti I/O della scheda Altera DE1
-- **********************************************************
-- --------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------- Main Module definition
-- --------------------------------------------------------------------------------------------
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity RegistratorePortatile is port(
DRAM_DQ: inout std_logic_vector(15 downto 0); -- SDRAM Data bus 16 Bits
DRAM_ADDR: out std_logic_vector(11 downto 0); -- SDRAM Address bus 12 Bits
DRAM_LDQM: buffer std_logic; -- SDRAM Low-byte Data Mask
DRAM_UDQM: buffer std_logic; -- SDRAM High-byte Data Mask
DRAM_WE_N: out std_logic; -- SDRAM Write Enable
DRAM_CAS_N: out std_logic; -- SDRAM Column Address Strobe
DRAM_RAS_N: out std_logic; -- SDRAM Row Address Strobe
DRAM_CS_N: out std_logic; -- SDRAM Chip Select
DRAM_BA_0: buffer std_logic; -- SDRAM Bank Address 0
DRAM_BA_1: buffer std_logic; -- SDRAM Bank Address 1
DRAM_CLK: out std_logic; -- SDRAM Clock
DRAM_CKE: out std_logic; -- SDRAM Clock Enable
CLOCK_50: in std_logic; -- On Board 50 MHz
KEY: in std_logic_vector(3 downto 0); -- Pushbutton[3:0]
SW: in std_logic_vector(9 downto 0); -- Toggle Switch[9:0]
HEX0: out std_logic_vector(6 downto 0); -- Seven Segment Digit 0
HEX1: out std_logic_vector(6 downto 0); -- Seven Segment Digit 1
HEX2: out std_logic_vector(6 downto 0); -- Seven Segment Digit 2
HEX3: out std_logic_vector(6 downto 0); -- Seven Segment Digit 3
LEDG: out std_logic_vector(7 downto 0); -- LED Green[7:0]
LEDR: out std_logic_vector(9 downto 0); -- LED Red[9:0]
AUD_ADCLRCK:inout std_logic; -- Audio CODEC ADC LR Clock
AUD_ADCDAT: in std_logic; -- Audio CODEC ADC Data
AUD_DACLRCK:inout std_logic; -- Audio CODEC DAC LR Clock
AUD_DACDAT: out std_logic; -- Audio CODEC DAC Data
AUD_BCLK: inout std_logic; -- Audio CODEC Bit-Stream Clock
AUD_XCK: out std_logic; -- Audio CODEC Chip Clock
I2C_SDAT: inout std_logic; -- I2C Data
I2C_SCLK: out std_logic; -- I2C Clock
VGA_CLK: inout std_logic; -- VGA Clock
VGA_HS: out std_logic; -- VGA H_SYNC
VGA_VS: out std_logic; -- VGA V_SYNC
VGA_BLANK: out std_logic; -- VGA BLANK
VGA_SYNC: out std_logic; -- VGA SYNC
VGA_R: out std_logic_vector(9 downto 0); -- VGA Red[9:0]
VGA_G: out std_logic_vector(9 downto 0); -- VGA Green[9:0]
VGA_B: out std_logic_vector(9 downto 0) -- VGA Blue[9:0]
);
end RegistratorePortatile;
-- --------------------------------------------------------------------------------------------
-- ------------------------------------------------------------------------ Definizione segnali
-- --------------------------------------------------------------------------------------------
architecture behaviour of RegistratorePortatile is
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------- Componenti usati
-------------------------------------------------------------------------------------------
component SDRAM_pll is port(
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic
);
end component;
component sdram is port(
az_addr: in std_logic_vector(21 downto 0);
az_be_n: in std_logic_vector(1 downto 0);
az_cs: in std_logic;
az_data: in std_logic_vector(15 downto 0);
az_rd_n: in std_logic;
az_wr_n: in std_logic;
clk: in std_logic;
reset_n: in std_logic;
za_data: out std_logic_vector(15 downto 0);
za_valid: out std_logic;
za_waitrequest: out std_logic;
zs_addr: out std_logic_vector(11 downto 0);
zs_ba: out std_logic_vector(1 downto 0);
zs_cas_n: out std_logic;
zs_cke: out std_logic;
zs_cs_n: out std_logic;
zs_dq: inout std_logic_vector(15 downto 0);
zs_dqm: out std_logic_vector(1 downto 0);
zs_ras_n: out std_logic;
zs_we_n: out std_logic
);
end component;
component Audio_Controller is port(
clk: in std_logic;
reset: in std_logic;
clear_audio_in_memory: in std_logic;
read_audio_in: in std_logic;
clear_audio_out_memory: in std_logic;
left_channel_audio_out: in std_logic_vector(32 downto 1); -- TODO parametrizzare con AUDIO_DATA_WIDTH
right_channel_audio_out: in std_logic_vector(32 downto 1); -- TODO parametrizzare con AUDIO_DATA_WIDTH
write_audio_out: in std_logic;
AUD_ADCDAT: in std_logic;
AUD_BCLK: inout std_logic;
AUD_ADCLRCK: inout std_logic;
AUD_DACLRCK: inout std_logic;
I2C_SDAT: inout std_logic;
audio_in_available: out std_logic;
left_channel_audio_in: buffer std_logic_vector(32 downto 1); -- TODO parametrizzare con AUDIO_DATA_WIDTH
right_channel_audio_in: out std_logic_vector(32 downto 1); -- TODO parametrizzare con AUDIO_DATA_WIDTH
audio_out_allowed: out std_logic;
AUD_XCK: out std_logic;
AUD_DACDAT: out std_logic;
I2C_SCLK: out std_logic;
useMicInput: in std_logic
);
end component;
component PlayRecord is port (
CLOCK_50 : in std_logic;
CLOCK_1S : in std_logic;
reset : in std_logic;
ram_addr : out std_logic_vector(21 downto 0);
ram_data_in : out std_logic_vector(15 downto 0);
ram_read : out std_logic;
ram_write : out std_logic;
ram_data_out : in std_logic_vector(15 downto 0);
ram_valid : in std_logic;
ram_waitrq : in std_logic;
audio_out : out std_logic_vector(15 downto 0);
audio_in : in std_logic_vector(15 downto 0);
audio_out_allowed : in std_logic;
audio_in_available : in std_logic;
write_audio_out : out std_logic;
read_audio_in : out std_logic;
play : in std_logic;
rec : in std_logic;
pause : in std_logic;
speed : in std_logic_vector(1 downto 0);
ram_addr_max : in std_logic_vector(21 downto 0);
playLimitReached : inout std_logic;
secondsCounter : inout std_logic_vector(7 downto 0)
);
end component;
component VGA_Adapter is port(
resetn: in std_logic;
clock: in std_logic;
clock_25: in std_logic;
colour: in std_logic;
x: in std_logic_vector(8 downto 0); -- x coordinate
y: in std_logic_vector(7 downto 0); -- y coordinate
plot: in std_logic; -- Quando e'=1, il pixel (x,y) cambiera' colore (bisogna plottare)
-- Segnali per il DAC per pilotare the monitor.
VGA_R: out std_logic_vector(9 downto 0);
VGA_G: out std_logic_vector(9 downto 0);
VGA_B: out std_logic_vector(9 downto 0);
VGA_HS: out std_logic;
VGA_VS: out std_logic;
VGA_BLANK: out std_logic;
VGA_SYNC: out std_logic
);
end component;
component Display is port (
clock : in std_logic;
reset : in std_logic;
freeze : in std_logic;
data : in std_logic_vector(15 downto 0);
x : inout std_logic_vector(8 downto 0);
y : inout std_logic_vector(7 downto 0);
color : inout std_logic;
plot : inout std_logic
);
end component;
component BinaryToBcd is port (
A : in std_logic_vector(7 downto 0);
ONES : out std_logic_vector(3 downto 0);
TENS : out std_logic_vector(3 downto 0);
HUNDREDS : out std_logic_vector(1 downto 0)
);
end component;
component hex2seg is port (
hex: in std_logic_vector(3 downto 0);
seg: out std_logic_vector(6 downto 0)
);
end component;
-- Segnali usati per leggere e scrivere dalla RAM
signal ram_addr: std_logic_vector(21 downto 0); -- Indirizzamento a 22 bit
signal ram_data_in, ram_data_out: std_logic_vector(15 downto 0); -- Bus dati a 16 bit I/O
signal ram_valid, ram_waitrq, ram_read, ram_write: std_logic; -- Segnali di abilitazione per lettura/scrittura
signal ram_addr_max: std_logic_vector(21 downto 0); -- Memorizza l'ultimo banco di RAM memorizzato
signal playLimitReached: std_logic; -- A 1 se durante il play si raggiunge la fine della registrazione
-- Segnali per gestione lettura/scrittura audio
signal audio_out, audio_in: std_logic_vector(15 downto 0); -- Bus a 16 bit
signal audio_out_allowed, audio_in_available: std_logic; -- Segnali di controllo abilitazione lettura/scrittura audio
signal write_audio_out, read_audio_in: std_logic;
-- Segnali per interfaccia con VGA
signal vga_color: std_logic; -- Colore (monocromatico, pixel acceso/spento)
signal vga_x: std_logic_vector(8 downto 0); -- x massimo = 319 (9 bit)
signal vga_y: std_logic_vector(7 downto 0); -- y massimo = 239 (8 bit)
signal vga_plot: std_logic; -- Abilitazione a scrittura pixel
-- Visualizzo l'uscita se sono in Play, altrimenti visualizzo l'ingresso del microfono
signal display_data: std_logic_vector(15 downto 0);
signal display_data_scaled: std_logic_vector(15 downto 0); -- Dati in scala usati per VGA e led rossi (volume)
signal useMicInput: std_logic; -- Quando e' a 1 usa il microfono, altrimenti il LineIn
signal blink_cnt: std_logic_vector(25 downto 0); -- Usato per blink pausa
-- Contatore di secondi
signal secondsCounter: std_logic_vector(7 downto 0); -- Contatore di secondi durante Play & Rec
signal secondsCounter0, secondsCounter1: std_logic_vector(3 downto 0); -- BCD
signal secondsCounter2: std_logic_vector(1 downto 0); -- BCD
signal seconds_max: std_logic_vector(7 downto 0); -- Memorizza i secondi memorizzati con l'ultima registrazione
signal seconds_max0, seconds_max1: std_logic_vector(3 downto 0); -- BCD
signal seconds_max2: std_logic_vector(1 downto 0); -- BCD
signal cnt_clock: integer;
signal CLOCK_1S: std_logic;
-----------------------------------------------------------------------------------------------
------------------------------------------------------------ Definizione input dalla Altera DE1
-----------------------------------------------------------------------------------------------
-- Tasti e switch per comandi
signal reset: std_logic := not KEY(0); -- Reset del sistema
signal AudioInChanged: std_logic := not KEY(1); -- Gestione del soft reset del chip audio
signal DisplayRamAddr: std_logic := not KEY(2); -- Se premuto visualizza l'indirizzo RAM anziche' i secondi
signal play_Cmd: std_logic := SW(0); -- Riproduce l'audio
signal pause_Cmd: std_logic := SW(1); -- Mette in pausa
signal record_Cmd: std_logic := SW(2); -- Registra
signal speed: std_logic_vector(1 downto 0) := SW(4 downto 3); -- Settaggi di velocita riproduzione
signal scale: std_logic_vector(1 downto 0) := SW(6 downto 5); -- Scala di visualizzazione dell'onda
signal showMaxAddr: std_logic := SW(7); -- Visualizzazione del limite dell'ultima registrazione
-----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------- Segnali di buffer
-----------------------------------------------------------------------------------------------
-- Segnali per display a 7 segmenti
signal h0_sig: std_logic_vector(3 downto 0);
signal h1_sig: std_logic_vector(3 downto 0);
signal h2_sig: std_logic_vector(3 downto 0);
signal h3_sig: std_logic_vector(3 downto 0);
signal ramMaxAddr_sig: std_logic_vector(1 downto 0); -- Serve per assegnare h0 e h1
signal zs_ba_sig: std_logic_vector(1 downto 0);
signal zs_dqm_sig: std_logic_vector(1 downto 0);
signal left_channel_audio_in_sig: std_logic_vector(32 downto 1);
begin
display_data <= audio_out when play_Cmd='1' else audio_in;
-----------------------------------------------------------------------------------------------
--------------------------------------------------- Definizione output diretti sulla Altera DE1
-----------------------------------------------------------------------------------------------
-- Spie per livello audio (volume) sui led rossi
LEDR(0) <= '0' when display_data_scaled(15)='1' else display_data_scaled(0);
LEDR(1) <= '0' when display_data_scaled(15)='1' else display_data_scaled(2);
LEDR(2) <= '0' when display_data_scaled(15)='1' else display_data_scaled(4);
LEDR(3) <= '0' when display_data_scaled(15)='1' else display_data_scaled(6);
LEDR(4) <= '0' when display_data_scaled(15)='1' else display_data_scaled(8);
LEDR(5) <= '0' when display_data_scaled(15)='1' else display_data_scaled(10);
LEDR(6) <= '0' when display_data_scaled(15)='1' else display_data_scaled(12);
LEDR(7) <= '0' when display_data_scaled(15)='1' else display_data_scaled(14);
-- Spia per la pausa
LEDG(7) <= blink_cnt(25) when pause_Cmd='1' and (play_Cmd='1' or record_Cmd='1') else '0';
LEDG(6) <= play_Cmd and playLimitReached;
-- Spia per reset
LEDG(0) <= reset;
-- Spia per input audio
LEDG(1) <= useMicInput;
-- Clock 1S (debug)
LEDG(2) <=
CLOCK_1S
and (play_Cmd or record_Cmd)
and (not pause_Cmd)
and (not playLimitReached);
-- Led non usati
LEDR(9 downto 8) <= "00";
LEDG(5 downto 3) <= "000";
-----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------- Segnali di buffer
-----------------------------------------------------------------------------------------------
-- Visualizzo l'uscita se sono in Play, altrimenti visualizzo l'ingresso del microfono
display_data <= audio_out when play_Cmd='1' else audio_in;
ramMaxAddr_sig <= DisplayRamAddr & showMaxAddr;
with ramMaxAddr_sig select
h0_sig <=
ram_addr_max(17 downto 14) when "11", -- Mostra Max Ram Address
ram_addr(17 downto 14) when "10", -- Mostra Ram Address
seconds_max0 when "01", -- Mostra Max Secondi
secondsCounter0 when "00", -- Mostra secondi
"0000" when others;
with ramMaxAddr_sig select
h1_sig <=
ram_addr_max(21 downto 18) when "11", -- Mostra Max Ram Address
ram_addr(21 downto 18) when "10", -- Mostra Ram Address
seconds_max1 when "01", -- Mostra Max Secondi
secondsCounter1 when "00", -- Mostra secondi
"0000" when others;
h2_sig <= "00" & scale;
h3_sig <= "00" & speed;
zs_ba_sig <= DRAM_BA_1 & DRAM_BA_0;
zs_dqm_sig <= DRAM_UDQM & DRAM_LDQM;
left_channel_audio_in_sig <= audio_in & "XXXXXXXXXXXXXXXX";
-----------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------- Processi
-----------------------------------------------------------------------------------------------
-- Intercetto il cambio di input per generare un "soft reset" del codec
-- Visto che il settaggio della periferica deve essere fatto allo startup del CODEC
process (AudioInChanged)
begin
if rising_edge(AudioInChanged) then
useMicInput <= not useMicInput;
end if;
end process;
-- Calcolo dei dati in base alla scala scelta: piu' e' alto il valore di scala piu'
-- Viene ridotta l'altezza della forma d'onda visualizzata
process (all)
begin
case(scale) is
when "00" => display_data_scaled <= display_data;
when "01" => display_data_scaled <= display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(14 downto 4);
when "10" => display_data_scaled <= display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(14 downto 8);
when "11" => display_data_scaled <= display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(14 downto 12);
end case;
end process;
-- Blinking della pausa
process (CLOCK_50)
begin
if rising_edge(CLOCK_50) then
blink_cnt <= blink_cnt + 1;
end if;
end process;
-- Memorizzazione dell'ultimo indirizzo registrato
process (record_Cmd)
begin
if falling_edge(record_Cmd) then
ram_addr_max <= ram_addr;
seconds_max <= secondsCounter;
end if;
end process;
-- Generazione clock a 2 Hz per contare i secondi
process (CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if (cnt_clock = 25000000) then
CLOCK_1S <= not CLOCK_1S;
cnt_clock <= 0;
else
cnt_clock <= cnt_clock + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------
----------------------------------------------------------------------- Collegamento Componenti
-----------------------------------------------------------------------------------------------
-- Modulo PLL generato con la megafunction ALTPLL
SDRAM_PLL_Entity: SDRAM_PLL port map(
inclk0 => CLOCK_50,
c0 => DRAM_CLK,
c1 => VGA_CLK,
c2 => AUD_XCK
);
-- Modulo generato dal SOPC builder
SDRAM_Entity: sdram port map(
az_addr => ram_addr,
az_be_n => "00",
az_cs => '1',
az_data => ram_data_in,
az_rd_n => not ram_read,
az_wr_n => not ram_write,
clk => CLOCK_50,
reset_n => not reset,
za_data => ram_data_out,
za_valid => ram_valid,
za_waitrequest => ram_waitrq,
zs_addr => DRAM_ADDR,
zs_ba => zs_ba_sig,
zs_cas_n => DRAM_CAS_N,
zs_cke => DRAM_CKE,
zs_cs_n => DRAM_CS_N,
zs_dq => DRAM_DQ,
zs_dqm => zs_dqm_sig,
zs_ras_n => DRAM_RAS_N,
zs_we_n => DRAM_WE_N
);
-- Lettura e scrittura sul chip audio
Audio_Controller_Entity: Audio_Controller port map (
clk => CLOCK_50,
reset => reset or AudioInChanged,
clear_audio_in_memory => '0',
read_audio_in => read_audio_in,
clear_audio_out_memory => '0',
left_channel_audio_out => audio_out & "0000000000000000",
right_channel_audio_out => audio_out & "0000000000000000",
write_audio_out => write_audio_out,
AUD_ADCDAT => AUD_ADCDAT,
AUD_BCLK => AUD_BCLK,
AUD_ADCLRCK => AUD_ADCLRCK,
AUD_DACLRCK => AUD_DACLRCK,
I2C_SDAT => I2C_SDAT,
audio_in_available => audio_in_available,
left_channel_audio_in => left_channel_audio_in_sig,
right_channel_audio_in => OPEN,
audio_out_allowed => audio_out_allowed,
AUD_XCK => OPEN,
AUD_DACDAT => AUD_DACDAT,
I2C_SCLK => I2C_SCLK,
useMicInput => useMicInput
);
-- Gestisce registrazione su RAM e riproduzione da RM dell'audio
PlayRecord_Entity: PlayRecord port map(
CLOCK_50,
CLOCK_1S,
reset,
ram_addr,
ram_data_in,
ram_read,
ram_write,
ram_data_out,
ram_valid,
ram_waitrq,
audio_out,
audio_in,
audio_out_allowed,
audio_in_available,
write_audio_out,
read_audio_in,
play_Cmd,
record_Cmd,
pause_Cmd,
speed,
ram_addr_max,
playLimitReached,
secondsCounter
);
-- Inizializzazione adattatore monitor VGA
VGA_Adapter_Entity: VGA_Adapter port map(
NOT reset,
CLOCK_50,
VGA_CLK,
vga_color,
vga_x,
vga_y,
vga_plot,
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
VGA_BLANK,
VGA_SYNC
);
-- Modulo che gestisce il display su monitor VGA
Display_Entity: Display port map(
CLOCK_50,
reset,
pause_Cmd,
display_data_scaled,
vga_x,
vga_y,
vga_color,
vga_plot
);
-- Convertitori da Binario a BCD
SecondsCounter_Entity: BinaryToBcd port map(secondsCounter, secondsCounter0, secondsCounter1, secondsCounter2);
SecondsMax_Entity: BinaryToBcd port map(seconds_max, seconds_max0, seconds_max1, seconds_max2);
-- I display a 7 segmenti 0 e 1 sono usati per visualizzare l'indirizzo della RAM o dei secondi (in rec o play)
h0_Entity: hex2seg port map(h0_sig, HEX0);
h1_Entity: hex2seg port map(h1_sig, HEX1);
-- Il display a 7 segmenti 2 e' usato per visualizzare il fattore di scala dell'onda sul monitor VGA
h4_Entity: hex2seg port map(h2_sig,HEX2);
-- Il display a 7 segmenti 3 viene usato per visualizzare la velocita di riproduzione
h3_Entity: hex2seg port map(h3_sig,HEX3);
end behaviour;
| mit | 65178552b796915fe3dcee8bde5f4a79 | 0.551248 | 3.156482 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue3/Keyboard/output_main.vhd | 1 | 3,639 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:45:03 07/06/2016
-- Design Name:
-- Module Name: output_main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity output_main is
Port ( scancode : in STD_LOGIC_VECTOR(7 downto 0);
ready : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
led_out : out STD_LOGIC_VECTOR(7 downto 0);
segment_out : out STD_LOGIC_VECTOR(14 downto 0));
end output_main;
architecture Behavioral of output_main is
component key2segments is port (
scancode : in STD_LOGIC_VECTOR(7 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal isE0, isF0, stw_q: STD_LOGIC;
signal segments : STD_LOGIC_VECTOR(6 downto 0);
signal mul_ctr : Integer range 0 to 100000;
signal cur_led : Integer range 0 to 7;
signal led0 : STD_LOGIC_VECTOR (6 downto 0);
signal led1 : STD_LOGIC_VECTOR (6 downto 0);
signal led2 : STD_LOGIC_VECTOR (6 downto 0);
signal led3 : STD_LOGIC_VECTOR (6 downto 0);
signal led4 : STD_LOGIC_VECTOR (6 downto 0);
signal led5 : STD_LOGIC_VECTOR (6 downto 0);
signal led6 : STD_LOGIC_VECTOR (6 downto 0);
signal led7 : STD_LOGIC_VECTOR (6 downto 0);
begin
ef0_detector : process(scancode)
begin
if(scancode = "11100000") then
isE0 <= '1';
else
isE0 <= '0';
end if;
if(scancode = "11110000") then
isF0 <= '1';
else
isF0 <= '0';
end if;
end process ef0_detector;
key2seg1: key2segments port map (scancode, segments);
led_out_pipe: process(isE0, isF0, ready, scancode, clk, segments)
begin
if clk'event and clk = '1' and (not (isE0 = '1' or isF0 = '1')) and ready = '1' then
led_out <= scancode;
end if;
end process led_out_pipe;
stw : process (isE0, isF0, ready, clk)
begin
if clk'event and clk = '1' and ready = '1' then
if stw_q = '0' then
if isE0 = '0' AND isF0 = '0' then
led7 <= led6;
led6 <= led5;
led5 <= led4;
led4 <= led3;
led3 <= led2;
led2 <= led1;
led1 <= led0;
led0 <= segments;
elsif isE0 = '0' AND isF0 = '1' then
stw_q <= '1';
end if;
else
stw_q <= '0';
end if;
end if;
end process stw;
ctr : process(clk)
begin
if(clk'event and clk = '1') then
if mul_ctr >= 99999 then
mul_ctr <= 0;
cur_led <= cur_led + 1;
else
mul_ctr <= mul_ctr + 1;
end if;
end if;
end process ctr;
multiplex : process (cur_led)
begin
if cur_led = 0 then
segment_out <= "11111110" & led0;
elsif cur_led = 1 then
segment_out <= "11111101" & led1;
elsif cur_led = 2 then
segment_out <= "11111011" & led2;
elsif cur_led = 3 then
segment_out <= "11110111" & led3;
elsif cur_led = 4 then
segment_out <= "11101111" & led4;
elsif cur_led = 5 then
segment_out <= "11011111" & led5;
elsif cur_led = 6 then
segment_out <= "10111111" & led6;
else
segment_out <= "01111111" & led7;
end if;
end process multiplex;
end Behavioral;
| mit | 4c3f6b083c0cffba46ecc5a18317dac6 | 0.598241 | 3.022425 | false | false | false | false |
Fju/LeafySan | src/vhdl/utils/i2c_master.vhdl | 1 | 27,816 | -----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : I2C Master
-- Author : Jan Dürre
-- Last update : 13.01.2016
-- Description : This I2C-Master supports 4 modes:
-- mode = 00: Only Read Bytes
-- mode = 01: Only Write Bytes
-- mode = 10: Read Bytes, Repeated Start, Write Bytes
-- mode = 11: Write Bytes, Repeated Start, Read Bytes
-- Clock Stretching is supported.
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity i2c_master is
generic (
GV_SYS_CLOCK_RATE : natural := 50000000;
GV_I2C_CLOCK_RATE : natural := 400000; -- standard mode: (100000) 100 kHz; fast mode: 400000 Hz (400 kHz)
GW_SLAVE_ADDR : natural := 7;
GV_MAX_BYTES : natural := 16;
GB_USE_INOUT : boolean := true;
GB_TIMEOUT : boolean := false
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
-- i2c master
i2c_clk : inout std_logic;
-- separated in / out
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
-- inout
i2c_dat : inout std_logic;
-- separated in / out
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
-- interface
busy : out std_ulogic;
cs : in std_ulogic;
mode : in std_ulogic_vector(1 downto 0);
slave_addr : in std_ulogic_vector(GW_SLAVE_ADDR-1 downto 0);
bytes_tx : in unsigned(to_log2(GV_MAX_BYTES+1)-1 downto 0);
bytes_rx : in unsigned(to_log2(GV_MAX_BYTES+1)-1 downto 0);
tx_data : in std_ulogic_vector(7 downto 0);
tx_data_valid : in std_ulogic;
rx_data : out std_ulogic_vector(7 downto 0);
rx_data_valid : out std_ulogic;
rx_data_en : in std_ulogic;
error : out std_ulogic
);
end i2c_master;
architecture rtl of i2c_master is
constant BIT_PERIOD : natural := GV_SYS_CLOCK_RATE / GV_I2C_CLOCK_RATE;
constant BIT_HALFPERIOD : natural := GV_SYS_CLOCK_RATE / (2 * GV_I2C_CLOCK_RATE);
constant BIT_QUARTERPERIOD : natural := GV_SYS_CLOCK_RATE / (4 * GV_I2C_CLOCK_RATE);
constant BIT_PAUSE : natural := BIT_PERIOD * 3;
constant BIT_TIMEOUT : natural := (GV_SYS_CLOCK_RATE / 1000) * 35; -- 35ms
-- fifos
component fifo is
generic (
DEPTH : natural;
WORDWIDTH : natural
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
write_en : in std_ulogic;
data_in : in std_ulogic_vector(WORDWIDTH-1 downto 0);
read_en : in std_ulogic;
data_out : out std_ulogic_vector(WORDWIDTH-1 downto 0);
empty : out std_ulogic;
full : out std_ulogic;
fill_cnt : out unsigned(to_log2(DEPTH+1)-1 downto 0)
);
end component fifo;
signal rx_fifo_write_en : std_ulogic;
signal rx_fifo_data_in : std_ulogic_vector(7 downto 0);
signal rx_fifo_read_en : std_ulogic;
signal rx_fifo_data_out : std_ulogic_vector(7 downto 0);
signal rx_fifo_empty : std_ulogic;
signal tx_fifo_write_en : std_ulogic;
signal tx_fifo_data_in : std_ulogic_vector(7 downto 0);
signal tx_fifo_read_en : std_ulogic;
signal tx_fifo_data_out : std_ulogic_vector(7 downto 0);
signal tx_fifo_empty : std_ulogic;
-- register to save requests
signal mode_reg, mode_reg_nxt : std_ulogic_vector(1 downto 0);
signal slave_addr_reg, slave_addr_reg_nxt : std_ulogic_vector(GW_SLAVE_ADDR-1 downto 0);
signal bytes_tx_reg, bytes_tx_reg_nxt : unsigned(to_log2(GV_MAX_BYTES+1)-1 downto 0);
signal bytes_rx_reg, bytes_rx_reg_nxt : unsigned(to_log2(GV_MAX_BYTES+1)-1 downto 0);
-- control fsm
type state_t is ( S_IDLE,
S_START,
S_START_PAUSE,
S_TX_SLAVE_ADDR_LF, S_TX_SLAVE_ADDR_H, S_TX_SLAVE_ADDR_LB,
S_TX_BYTE_LF, S_TX_BYTE_H, S_TX_BYTE_LB,
S_REPEAT_START_L, S_REPEAT_START_H,
S_RX_BYTE_L, S_RX_BYTE_H,
S_PAUSE,
S_RX_ACK_L, S_RX_ACK_H,
S_TX_ACK_LF, S_TX_ACK_H, S_TX_ACK_LB,
S_STOP_L, S_STOP_H,
S_CLEANUP
);
signal state, state_nxt : state_t;
signal follow_state, follow_state_nxt : state_t;
-- data shift register
signal i2c_tx_shift_reg, i2c_tx_shift_reg_nxt : std_logic_vector(max(8, GW_SLAVE_ADDR + 1)-1 downto 0);
signal i2c_rx_shift_reg, i2c_rx_shift_reg_nxt : std_logic_vector(7 downto 0);
-- counter
signal tx_byte_cnt, tx_byte_cnt_nxt : unsigned(to_log2(GV_MAX_BYTES+1)-1 downto 0);
signal rx_byte_cnt, rx_byte_cnt_nxt : unsigned(to_log2(GV_MAX_BYTES+1)-1 downto 0);
signal bit_cnt, bit_cnt_nxt : unsigned(to_log2(max(8, GW_SLAVE_ADDR + 1))-1 downto 0);
signal time_cnt, time_cnt_nxt : unsigned(to_log2(10 * BIT_PERIOD)-1 downto 0);
signal time_cnt_reset : std_ulogic;
signal time_cnt_period : std_ulogic;
signal time_cnt_period_tick : std_ulogic;
signal time_cnt_halfperiod : std_ulogic;
signal time_cnt_halfperiod_tick : std_ulogic;
signal time_cnt_quarterperiod : std_ulogic;
signal time_cnt_quarterperiod_tick : std_ulogic;
signal time_cnt_pause_timeout : std_ulogic;
signal timeout_cnt, timeout_cnt_nxt : unsigned(31 downto 0);
signal timeout_reset : std_ulogic;
signal timeout : std_ulogic;
-- error flag
signal error_int, error_int_nxt : std_ulogic;
-- i2c wires
signal i2c_clk_wire : std_logic;
signal i2c_clk_in_wire : std_ulogic;
signal i2c_dat_wire : std_logic;
signal i2c_dat_in_wire : std_ulogic;
begin
-- check if slave-address-width is 7 or 10 (as in nxp reference definition)
assert ((GW_SLAVE_ADDR = 7) or (GW_SLAVE_ADDR = 10)) report "Warning: Most I2C-Interfaces only support 7 or 10 Bit Slave-Addresses!" severity warning;
-- fifos
rx_buf_inst : fifo
generic map (
DEPTH => GV_MAX_BYTES,
WORDWIDTH => 8
)
port map (
clock => clock,
reset_n => reset_n,
write_en => rx_fifo_write_en,
data_in => rx_fifo_data_in,
read_en => rx_fifo_read_en,
data_out => rx_fifo_data_out,
empty => rx_fifo_empty,
full => open,
fill_cnt => open
);
tx_buf_inst : fifo
generic map (
DEPTH => GV_MAX_BYTES,
WORDWIDTH => 8
)
port map (
clock => clock,
reset_n => reset_n,
write_en => tx_fifo_write_en,
data_in => tx_fifo_data_in,
read_en => tx_fifo_read_en,
data_out => tx_fifo_data_out,
empty => tx_fifo_empty,
full => open,
fill_cnt => open
);
-- ff
process(clock, reset_n)
begin
if reset_n = '0' then
state <= S_IDLE;
follow_state <= S_IDLE;
i2c_tx_shift_reg <= (others => '0');
i2c_rx_shift_reg <= (others => '0');
mode_reg <= (others => '0');
slave_addr_reg <= (others => '0');
bytes_tx_reg <= (others => '0');
bytes_rx_reg <= (others => '0');
tx_byte_cnt <= (others => '0');
rx_byte_cnt <= (others => '0');
bit_cnt <= (others => '0');
time_cnt <= (others => '0');
timeout_cnt <= (others => '0');
error_int <= '0';
elsif rising_edge(clock) then
state <= state_nxt;
follow_state <= follow_state_nxt;
i2c_tx_shift_reg <= i2c_tx_shift_reg_nxt;
i2c_rx_shift_reg <= i2c_rx_shift_reg_nxt;
mode_reg <= mode_reg_nxt;
slave_addr_reg <= slave_addr_reg_nxt;
bytes_tx_reg <= bytes_tx_reg_nxt;
bytes_rx_reg <= bytes_rx_reg_nxt;
tx_byte_cnt <= tx_byte_cnt_nxt;
rx_byte_cnt <= rx_byte_cnt_nxt;
bit_cnt <= bit_cnt_nxt;
time_cnt <= time_cnt_nxt;
timeout_cnt <= timeout_cnt_nxt;
error_int <= error_int_nxt;
end if;
end process;
-- connect entity to fifos
tx_fifo_data_in <= tx_data;
tx_fifo_write_en <= tx_data_valid;
rx_data <= rx_fifo_data_out;
rx_data_valid <= not rx_fifo_empty;
rx_fifo_read_en <= rx_data_en;
-- time counter
process(time_cnt, time_cnt_reset)
begin
time_cnt_period <= '0';
time_cnt_period_tick <= '0';
time_cnt_halfperiod <= '0';
time_cnt_halfperiod_tick <= '0';
time_cnt_quarterperiod <= '0';
time_cnt_quarterperiod_tick <= '0';
time_cnt_pause_timeout <= '0';
if time_cnt_reset = '1' then
time_cnt_nxt <= (others => '0');
else
time_cnt_nxt <= time_cnt + 1;
end if;
if time_cnt >= BIT_PERIOD then
time_cnt_period <= '1';
end if;
if time_cnt = BIT_PERIOD then
time_cnt_period_tick <= '1';
end if;
if time_cnt >= BIT_HALFPERIOD then
time_cnt_halfperiod <= '1';
end if;
if time_cnt = BIT_HALFPERIOD then
time_cnt_halfperiod_tick <= '1';
end if;
if time_cnt >= BIT_QUARTERPERIOD then
time_cnt_quarterperiod <= '1';
end if;
if time_cnt = BIT_QUARTERPERIOD then
time_cnt_quarterperiod_tick <= '1';
end if;
if time_cnt >= BIT_PAUSE then
time_cnt_pause_timeout <= '1';
end if;
end process;
-- timeout counter
process(timeout_cnt, timeout_reset)
begin
timeout <= '0';
if timeout_reset = '1' then
timeout_cnt_nxt <= (others => '0');
else
timeout_cnt_nxt <= timeout_cnt + 1;
end if;
if GB_TIMEOUT = true then
if timeout_cnt = BIT_TIMEOUT then
timeout <= '1';
end if;
end if;
end process;
-- i2c lines can only be driven with '0', a logical one is implemented via pull-up -> 'Z'
inout_gen : if GB_USE_INOUT = true generate
i2c_clk <= '0' when i2c_clk_wire = '0' else
'Z';
i2c_clk_ctrl <= '0';
i2c_clk_out <= 'Z';
i2c_clk_in_wire <= i2c_clk;
i2c_dat <= '0' when i2c_dat_wire = '0' else
'Z';
i2c_dat_ctrl <= '0';
i2c_dat_out <= 'Z';
i2c_dat_in_wire <= i2c_dat;
end generate inout_gen;
sep_inout_gen : if GB_USE_INOUT = false generate
i2c_clk <= 'Z';
i2c_clk_in_wire <= i2c_clk_in;
i2c_dat <= 'Z';
i2c_dat_in_wire <= i2c_dat_in;
process(i2c_clk_wire)
begin
if i2c_clk_wire = '0' then
i2c_clk_ctrl <= '1';
i2c_clk_out <= '0';
else
i2c_clk_ctrl <= '0';
i2c_clk_out <= 'Z';
end if;
end process;
process(i2c_dat_wire)
begin
if i2c_dat_wire = '0' then
i2c_dat_ctrl <= '1';
i2c_dat_out <= '0';
else
i2c_dat_ctrl <= '0';
i2c_dat_out <= 'Z';
end if;
end process;
end generate sep_inout_gen;
-- logic
process(state, follow_state, i2c_tx_shift_reg, i2c_rx_shift_reg, mode_reg, slave_addr_reg, bytes_tx_reg, bytes_rx_reg, tx_byte_cnt, rx_byte_cnt, bit_cnt, time_cnt_period, time_cnt_period_tick, time_cnt_halfperiod, time_cnt_halfperiod_tick, time_cnt_quarterperiod, time_cnt_quarterperiod_tick, time_cnt_pause_timeout, timeout, error_int, cs, mode, slave_addr, bytes_tx, bytes_rx, tx_fifo_empty, tx_fifo_data_out, i2c_clk_in_wire, i2c_dat_in_wire)
begin
-- regs
state_nxt <= state;
follow_state_nxt <= follow_state;
i2c_tx_shift_reg_nxt <= i2c_tx_shift_reg;
i2c_rx_shift_reg_nxt <= i2c_rx_shift_reg;
mode_reg_nxt <= mode_reg;
slave_addr_reg_nxt <= slave_addr_reg;
bytes_tx_reg_nxt <= bytes_tx_reg;
bytes_rx_reg_nxt <= bytes_rx_reg;
tx_byte_cnt_nxt <= tx_byte_cnt;
rx_byte_cnt_nxt <= rx_byte_cnt;
bit_cnt_nxt <= bit_cnt;
-- busy signal
busy <= '1';
-- count control
time_cnt_reset <= '0';
timeout_reset <= '0';
-- i2c
i2c_dat_wire <= '1';
i2c_clk_wire <= '1';
-- error
error_int_nxt <= error_int;
error <= error_int;
-- fifo
rx_fifo_write_en <= '0';
rx_fifo_data_in <= (others => '0');
tx_fifo_read_en <= '0';
-- fsm
case state is
----------
-- Idle --
----------
when S_IDLE =>
busy <= '0';
-- work request
if cs = '1' then
--if i2c_clk_in_wire = '1' and i2c_dat_in_wire = '1' then
if i2c_clk_in_wire = '1' then
-- save relevant information to registers
mode_reg_nxt <= mode;
slave_addr_reg_nxt <= slave_addr;
bytes_tx_reg_nxt <= bytes_tx;
bytes_rx_reg_nxt <= bytes_rx;
-- reset error-flag
error_int_nxt <= '0';
-- begin with start-condition
state_nxt <= S_START;
time_cnt_reset <= '1';
timeout_reset <= '1';
else
-- something is going on!
-- set error-flag
error_int_nxt <= '1';
end if;
end if;
-----------
-- Start --
-----------
when S_START =>
-- generate start condition
i2c_clk_wire <= '1';
i2c_dat_wire <= '0';
if time_cnt_halfperiod = '1' then
state_nxt <= S_START_PAUSE;--S_TX_SLAVE_ADDR_LF;
time_cnt_reset <= '1';
timeout_reset <= '1';
bit_cnt_nxt <= (others => '0');
tx_byte_cnt_nxt <= (others => '0');
rx_byte_cnt_nxt <= (others => '0');
-- next follows RX
if mode_reg = "00" or mode_reg = "10" then
i2c_tx_shift_reg_nxt <= std_logic_vector(slave_addr_reg) & '1';
follow_state_nxt <= S_RX_BYTE_L;
-- next follows TX
elsif mode_reg = "01" or mode_reg = "11" then
i2c_tx_shift_reg_nxt <= std_logic_vector(slave_addr_reg) & '0';
follow_state_nxt <= S_TX_BYTE_LF;
end if;
end if;
when S_START_PAUSE =>
-- pull down clk
i2c_clk_wire <= '0';
-- pull down dat
i2c_dat_wire <= '0';
if time_cnt_pause_timeout = '1' then
state_nxt <= S_TX_SLAVE_ADDR_LF;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
----------------
-- Slave Addr --
----------------
when S_TX_SLAVE_ADDR_LF =>
-- pull clk low
i2c_clk_wire <= '0';
-- set data
i2c_dat_wire <= i2c_tx_shift_reg(i2c_tx_shift_reg'length-1);
-- wait for quarter-period
if time_cnt_quarterperiod = '1' then
state_nxt <= S_TX_SLAVE_ADDR_H;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
when S_TX_SLAVE_ADDR_H =>
-- let clk float
i2c_clk_wire <= '1';
-- hold data
i2c_dat_wire <= i2c_tx_shift_reg(i2c_tx_shift_reg'length-1);
-- wait for clk to pull up, reset counter while low
if i2c_clk_in_wire = '0' then
time_cnt_reset <= '1';
end if;
-- wait for a half-period
if time_cnt_halfperiod = '1' then
state_nxt <= S_TX_SLAVE_ADDR_LB;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
-- reset
if timeout = '1' then
state_nxt <= S_STOP_L;
timeout_reset <= '1';
error_int_nxt <= '1';
end if;
when S_TX_SLAVE_ADDR_LB =>
-- pull clk low again
i2c_clk_wire <= '0';
-- set data
i2c_dat_wire <= i2c_tx_shift_reg(i2c_tx_shift_reg'length-1);
if time_cnt_quarterperiod = '1' then
-- shift tx data
i2c_tx_shift_reg_nxt <= i2c_tx_shift_reg(i2c_tx_shift_reg'length-2 downto 0) & '0';
-- size of slave address reached
if bit_cnt = GW_SLAVE_ADDR then
-- reset counter
bit_cnt_nxt <= (others => '0');
state_nxt <= S_RX_ACK_L;
time_cnt_reset <= '1';
timeout_reset <= '1';
-- fetch byte from fifo when TX is following
if follow_state = S_TX_BYTE_LF then
if tx_fifo_empty = '0' then
tx_fifo_read_en <= '1';
end if;
i2c_tx_shift_reg_nxt(i2c_tx_shift_reg'length-1 downto i2c_tx_shift_reg'length-8) <= std_logic_vector(tx_fifo_data_out);
end if;
else
-- addr-bits missing
bit_cnt_nxt <= bit_cnt + 1;
state_nxt <= S_TX_SLAVE_ADDR_LF;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
end if;
-------------
-- TX Byte --
-------------
when S_TX_BYTE_LF =>
-- pull clk low
i2c_clk_wire <= '0';
-- set data
i2c_dat_wire <= i2c_tx_shift_reg(i2c_tx_shift_reg'length-1);
-- wait for a quarter-period
if time_cnt_halfperiod = '1' then
state_nxt <= S_TX_BYTE_H;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
when S_TX_BYTE_H =>
-- let clk float
i2c_clk_wire <= '1';
-- hold data
i2c_dat_wire <= i2c_tx_shift_reg(i2c_tx_shift_reg'length-1);
-- wait for clk to pull up, reset counter while low
if i2c_clk_in_wire = '0' then
time_cnt_reset <= '1';
end if;
-- wait for a half-period
if time_cnt_halfperiod = '1' then
state_nxt <= S_TX_BYTE_LB;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
-- reset
if timeout = '1' then
state_nxt <= S_STOP_L;
timeout_reset <= '1';
error_int_nxt <= '1';
end if;
when S_TX_BYTE_LB =>
-- pull clk low again
i2c_clk_wire <= '0';
-- set data
i2c_dat_wire <= i2c_tx_shift_reg(i2c_tx_shift_reg'length-1);
if time_cnt_quarterperiod = '1' then
-- shift tx data
i2c_tx_shift_reg_nxt <= i2c_tx_shift_reg(i2c_tx_shift_reg'length-2 downto 0) & '0';
-- byte complete
if bit_cnt = 7 then
-- next byte
tx_byte_cnt_nxt <= tx_byte_cnt + 1;
-- reset counter
bit_cnt_nxt <= (others => '0');
-- await ack
state_nxt <= S_RX_ACK_L;
time_cnt_reset <= '1';
timeout_reset <= '1';
-- all bytes transferred
if tx_byte_cnt = bytes_tx_reg - 1 then
if mode_reg = "01" or mode_reg = "10" then
-- end transfer after ack
follow_state_nxt <= S_STOP_L;
elsif mode_reg = "11" then
-- turn to rx
follow_state_nxt <= S_REPEAT_START_L;
end if;
-- not all bytes transferred
else
-- fetch new byte from fifo
if tx_fifo_empty = '0' then
tx_fifo_read_en <= '1';
end if;
i2c_tx_shift_reg_nxt(i2c_tx_shift_reg'length-1 downto i2c_tx_shift_reg'length-8) <= std_logic_vector(tx_fifo_data_out);
-- continue after ack
follow_state_nxt <= S_TX_BYTE_LF;
end if;
else
-- continue byte
bit_cnt_nxt <= bit_cnt + 1;
state_nxt <= S_TX_BYTE_LF;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
end if;
--------------------
-- Repeated Start --
--------------------
when S_REPEAT_START_L =>
-- pull clk low
i2c_clk_wire <= '0';
-- let dat float
i2c_dat_wire <= '1';
-- wait for data to pull up, reset counter while low
if i2c_dat_in_wire = '0' then
time_cnt_reset <= '1';
end if;
-- wait for a half-period
if time_cnt_halfperiod = '1' then
state_nxt <= S_REPEAT_START_H;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
-- reset
if timeout = '1' then
state_nxt <= S_STOP_L;
timeout_reset <= '1';
error_int_nxt <= '1';
end if;
when S_REPEAT_START_H =>
-- let clk float
i2c_clk_wire <= '1';
-- let dat float
i2c_dat_wire <= '1';
-- wait for clk to pull up, reset counter while low
if i2c_clk_in_wire = '0' then
time_cnt_reset <= '1';
end if;
-- wait for a half-period
if time_cnt_halfperiod = '1' then
-- pull dat down for repeated start condition
i2c_dat_wire <= '0';
end if;
-- wait for one period
if time_cnt_period = '1' then
state_nxt <= S_START_PAUSE;
time_cnt_reset <= '1';
timeout_reset <= '1';
-- next follows TX
if mode_reg = "10" then
i2c_tx_shift_reg_nxt <= std_logic_vector(slave_addr_reg) & '0';
follow_state_nxt <= S_TX_BYTE_LF;
-- next follows RX
elsif mode_reg = "11" then
i2c_tx_shift_reg_nxt <= std_logic_vector(slave_addr_reg) & '1';
follow_state_nxt <= S_RX_BYTE_L;
end if;
end if;
-- reset
if timeout = '1' then
state_nxt <= S_STOP_L;
timeout_reset <= '1';
error_int_nxt <= '1';
end if;
-------------
-- RX Byte --
-------------
when S_RX_BYTE_L =>
-- pull clk down
i2c_clk_wire <= '0';
-- let dat float
i2c_dat_wire <= '1';
-- wait for a half-period
if time_cnt_halfperiod = '1' then
state_nxt <= S_RX_BYTE_H;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
when S_RX_BYTE_H =>
-- let clk float
i2c_clk_wire <= '1';
-- let dat float
i2c_dat_wire <= '1';
-- wait for clk to pull up, reset counter while low
if i2c_clk_in_wire = '0' then
time_cnt_reset <= '1';
end if;
-- wait for a quarter-period
if time_cnt_quarterperiod_tick = '1' then
-- shift in data bit
i2c_rx_shift_reg_nxt <= i2c_rx_shift_reg(i2c_rx_shift_reg'length-2 downto 0) & i2c_dat_in_wire;
end if;
-- wait for a half-period
if time_cnt_halfperiod = '1' then
-- byte complete
if bit_cnt = 7 then
-- next byte
rx_byte_cnt_nxt <= rx_byte_cnt + 1;
-- reset counter
bit_cnt_nxt <= (others => '0');
-- send ack
state_nxt <= S_TX_ACK_LF;
time_cnt_reset <= '1';
timeout_reset <= '1';
-- all bytes transferred (register data)
if rx_byte_cnt = bytes_rx_reg - 1 then
if mode_reg = "00" or mode_reg = "11" then
-- stop start after ack-transfer
follow_state_nxt <= S_STOP_L;
elsif mode_reg = "10" then
-- or turn to TX
follow_state_nxt <= S_REPEAT_START_L;
end if;
-- not all bytes transferred
else
-- continue receiving register data after ack-transfer
follow_state_nxt <= S_RX_BYTE_L;
end if;
else
-- continue byte
bit_cnt_nxt <= bit_cnt + 1;
state_nxt <= S_RX_BYTE_L;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
end if;
-- reset
if timeout = '1' then
state_nxt <= S_STOP_L;
timeout_reset <= '1';
error_int_nxt <= '1';
end if;
------------
-- RX Ack --
------------
when S_RX_ACK_L =>
-- pull clk down
i2c_clk_wire <= '0';
-- let dat float
i2c_dat_wire <= '1';
-- wait for a half-period
if time_cnt_halfperiod = '1' then
state_nxt <= S_RX_ACK_H;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
when S_RX_ACK_H =>
-- let clk float
i2c_clk_wire <= '1';
-- let dat float
i2c_dat_wire <= '1';
-- wait for clk to pull up, reset counter while low
if i2c_clk_in_wire = '0' then
time_cnt_reset <= '1';
end if;
-- wait for a quarter-period
if time_cnt_quarterperiod_tick = '1' then
-- check for nack
if i2c_dat_in_wire = '1' then
error_int_nxt <= '1';
end if;
end if;
-- wait for a half-period
if time_cnt_halfperiod = '1' then
if error_int = '0' then
-- continue
state_nxt <= S_PAUSE;
time_cnt_reset <= '1';
timeout_reset <= '1';
-- negative ack
else
-- abort
state_nxt <= S_STOP_L;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
end if;
-- reset
if timeout = '1' then
state_nxt <= S_STOP_L;
timeout_reset <= '1';
error_int_nxt <= '1';
end if;
------------
-- TX Ack --
------------
when S_TX_ACK_LF =>
-- pull clk down
i2c_clk_wire <= '0';
-- let dat flow
i2c_dat_wire <= '1';
-- wait for quarter-period
if time_cnt_quarterperiod = '1' then
-- only ack when not last rx-byte!
if rx_byte_cnt /= bytes_rx_reg then
-- pull down dat (ack)
i2c_dat_wire <= '0';
end if;
end if;
-- wait for half-period
if time_cnt_halfperiod = '1' then
state_nxt <= S_TX_ACK_H;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
when S_TX_ACK_H =>
-- let clk float
i2c_clk_wire <= '1';
-- only ack when not last rx-byte!
if rx_byte_cnt /= bytes_rx_reg then
-- pull down dat (ack)
i2c_dat_wire <= '0';
else
-- let dat float (nack)
i2c_dat_wire <= '1';
end if;
-- wait for clk to pull up, reset counter while low
if i2c_clk_in_wire = '0' then
time_cnt_reset <= '1';
end if;
-- wait for a half-period
if time_cnt_halfperiod = '1' then
state_nxt <= S_TX_ACK_LB;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
-- reset
if timeout = '1' then
state_nxt <= S_STOP_L;
timeout_reset <= '1';
error_int_nxt <= '1';
end if;
when S_TX_ACK_LB =>
-- pull clk down
i2c_clk_wire <= '0';
-- only ack when not last rx-byte!
if rx_byte_cnt /= bytes_rx_reg then
-- pull down dat (ack)
i2c_dat_wire <= '0';
else
-- let dat float (nack)
i2c_dat_wire <= '1';
end if;
-- wait for quarter-period
if time_cnt_quarterperiod = '1' then
-- save byte to fifo
rx_fifo_write_en <= '1';
rx_fifo_data_in <= std_ulogic_vector(i2c_rx_shift_reg);
-- continue
state_nxt <= S_PAUSE;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
-----------
-- Pause --
-----------
when S_PAUSE =>
-- let clk float
i2c_clk_wire <= '0';
-- let dat float
i2c_dat_wire <= '1';
if time_cnt_pause_timeout = '1' then
state_nxt <= follow_state;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
----------
-- Stop --
----------
when S_STOP_L =>
-- pull clk down
i2c_clk_wire <= '0';
-- pull clk down
i2c_dat_wire <= '0';
-- wait for a half-period
if time_cnt_halfperiod = '1' then
state_nxt <= S_STOP_H;
time_cnt_reset <= '1';
timeout_reset <= '1';
end if;
when S_STOP_H =>
-- let clk float
i2c_clk_wire <= '1';
-- pull clk down
i2c_dat_wire <= '0';
-- wait for clk to pull up, reset counter while low
if i2c_clk_in_wire = '0' then
time_cnt_reset <= '1';
end if;
-- wait for a half-period
if time_cnt_halfperiod = '1' then
-- let dat float for stop condition
i2c_dat_wire <= '1';
end if;
-- clean exit
if time_cnt_period = '1' then
state_nxt <= S_CLEANUP;
end if;
-- error
if timeout = '1' then
state_nxt <= S_CLEANUP;
error_int_nxt <= '1';
end if;
--------------
-- Clean-Up --
--------------
when S_CLEANUP =>
-- not all bytes transferred, empty tx-fifo
if tx_byte_cnt /= bytes_tx_reg then
if tx_fifo_empty = '0' then
tx_fifo_read_en <= '1';
end if;
-- next byte
tx_byte_cnt_nxt <= tx_byte_cnt + 1;
else
state_nxt <= S_IDLE;
end if;
end case;
end process;
end rtl;
| apache-2.0 | cdc507adc8114adfe580842ac3bad5c8 | 0.51891 | 2.716406 | false | false | false | false |
maly/fpmi | FPGA/disp8.vhd | 1 | 2,225 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DISP8 is
port (anode: out std_logic_vector(8 downto 0);
cathode: out std_logic_vector(7 downto 0);
data1: in std_logic_vector(7 downto 0); --PA
data2: in std_logic_vector(7 downto 0); --PA
addr: in std_logic_vector(15 downto 0); --PA
clk:in std_logic
);
end entity;
architecture a of DISP8 is
signal clkx: unsigned(2 downto 0):="000";
signal bcd:std_logic_vector(3 downto 0);
begin
process (clk) is
variable div:integer:=0;
begin
if rising_edge(clk) then
div:=div+1;
if (div=10000) then
clkx<=clkx+1;
div:=0;
end if;
case bcd is
when "0000"=> cathode <="00111111"; -- '0'
when "0001"=> cathode <="00000110"; -- '1'
when "0010"=> cathode <="01011011"; -- '2'
when "0011"=> cathode <="01001111"; -- '3'
when "0100"=> cathode <="01100110"; -- '4'
when "0101"=> cathode <="01101101"; -- '5'
when "0110"=> cathode <="01111101"; -- '6'
when "0111"=> cathode <="00000111"; -- '7'
when "1000"=> cathode <="01111111"; -- '8'
when "1001"=> cathode <="01101111"; -- '9'
when "1010"=> cathode <="01110111"; -- 'a'
when "1011"=> cathode <="01111100"; -- 'b'
when "1100"=> cathode <="00111001"; -- 'c'
when "1101"=> cathode <="01011110"; -- 'd'
when "1110"=> cathode <="01111001"; -- 'e'
when "1111"=> cathode <="01110001"; -- 'f'
--nothing is displayed when a number more than 9 is given as input.
when others=> cathode <="00000000";
end case;
end if;
end process;
anode<= "111111110" when clkx="000" else
"111111101" when clkx="001" else
"111111011" when clkx="010" else
"111110111" when clkx="011" else
"111101111" when clkx="100" else
"111011111" when clkx="101" else
"110111111" when clkx="110" else
"101111111" when clkx="111" else
"111111111";
bcd<= data1(3 downto 0) when clkx="001" else
data1(7 downto 4) when clkx="000" else
data2(3 downto 0) when clkx="011" else
data2(7 downto 4) when clkx="010" else
addr(3 downto 0) when clkx="111" else
addr(7 downto 4) when clkx="110" else
addr(11 downto 8) when clkx="101" else
addr(15 downto 12) when clkx="100" else
x"0";
end architecture; | mit | 36f31d40a7034322e99c2f3df1ca40be | 0.615281 | 3.160511 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Altpll_Generated_Files/SDRAM_pll.vhd | 1 | 18,000 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: SDRAM_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY SDRAM_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC
);
END SDRAM_pll;
ARCHITECTURE SYN OF sdram_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "-167",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
clk2_divide_by => 4,
clk2_duty_cycle => 50,
clk2_multiply_by => 1,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=SDRAM_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.500000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "SDRAM_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-167"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| mit | b3593b07dd66213cb14adf5a699533dd | 0.685333 | 3.251445 | false | false | false | false |
maly/fpmi | FPGA/8255/pia8255.vhd | 1 | 4,252 | library IEEE;
use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pia8255 is
port
(
-- uC interface
clk : in std_logic;
clken : in std_logic;
reset : in std_logic;
a : in std_logic_vector(1 downto 0);
d_i : in std_logic_vector(7 downto 0);
d_o : out std_logic_vector(7 downto 0);
cs : in std_logic;
rd : in std_logic;
wr : in std_logic;
-- I/O interface
pa_i : in std_logic_vector(7 downto 0);
pb_i : in std_logic_vector(7 downto 0);
pc_i : in std_logic_vector(7 downto 0);
pa_o : out std_logic_vector(7 downto 0);
pb_o : out std_logic_vector(7 downto 0);
pc_o : out std_logic_vector(7 downto 0)
);
end pia8255;
architecture SYN of pia8255 is
type byte_vector is array (natural range <>) of std_logic_vector(7 downto 0);
signal ctrl : std_logic_vector(7 downto 0);
signal pa_oen : std_logic;
signal pb_oen : std_logic;
signal pcl_oen : std_logic;
signal pch_oen : std_logic;
signal pa_d : std_logic_vector(7 downto 0);
signal pb_d : std_logic_vector(7 downto 0);
signal pc_d : std_logic_vector(7 downto 0);
begin
pa_o <= pa_d when (reset = '0' and pa_oen = '1') else X"FF";
pb_o <= pb_d when (reset = '0' and pb_oen = '1') else X"FF";
pc_o(7 downto 4) <= pc_d(7 downto 4) when (reset = '0' and pch_oen = '1') else X"F";
pc_o(3 downto 0) <= pc_d(3 downto 0) when (reset = '0' and pcl_oen = '1') else X"F";
-- Synchronous logic
process(clk, reset)
variable ctrl_r : std_logic_vector(7 downto 0);
variable csel : integer;
begin
pa_oen <= not ctrl_r(4);
pb_oen <= not ctrl_r(1);
pcl_oen <= not ctrl_r(0);
pch_oen <= not ctrl_r(3);
ctrl <= ctrl_r;
-- Reset values
if reset = '1' then
ctrl_r := X"9B";
pa_d <= X"00";
pb_d <= X"00";
pc_d <= X"00";
-- Handle register writes
elsif rising_edge(clk) and clken = '1' and cs = '1' and wr = '1' then
if a = "00" then
pa_d <= d_i;
end if;
if a = "01" then
pb_d <= d_i;
end if;
if a = "10" then
pc_d <= d_i;
end if;
if a = "11" then
-- D7=1, write control
if d_i(7) = '1' then
ctrl_r := d_i;
pa_d <= X"00";
pb_d <= X"00";
pc_d <= X"00";
-- D7=0, write C bit
else
csel := conv_integer(d_i(3 downto 1));
pc_d(csel) <= d_i(0);
end if;
end if;
end if;
end process;
-- Data out mux
process(a, cs, rd)
variable data_out : std_logic_vector(7 downto 0);
begin
if cs = '1' and rd = '1' then
case a is
when "00" => data_out := pa_i;
when "01" => data_out := pb_i;
when "10" => data_out := pc_i;
when "11" => data_out := ctrl;
when others => data_out := (others => 'X');
end case;
else
data_out := (others => 'X');
end if;
d_o <= data_out;
end process;
end SYN;
library IEEE;
use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pia8255_n is
port
(
-- uC interface
clk : in std_logic;
clken : in std_logic;
reset : in std_logic;
a : in std_logic_vector(1 downto 0);
d_i : in std_logic_vector(7 downto 0);
d_o : out std_logic_vector(7 downto 0);
cs_n : in std_logic;
rd_n : in std_logic;
wr_n : in std_logic;
-- I/O interface
pa_i : in std_logic_vector(7 downto 0);
pb_i : in std_logic_vector(7 downto 0);
pc_i : in std_logic_vector(7 downto 0);
pa_o : out std_logic_vector(7 downto 0);
pb_o : out std_logic_vector(7 downto 0);
pc_o : out std_logic_vector(7 downto 0)
);
end pia8255_n;
architecture SYN of pia8255_n is
signal cs : std_logic;
signal rd : std_logic;
signal wr : std_logic;
begin
cs <= not cs_n;
rd <= not rd_n;
wr <= not wr_n;
pia_inst : entity work.pia8255
port map
(
-- uC interface
clk => clk,
clken => clken,
reset => reset,
a => a,
d_i => d_i,
d_o => d_o,
cs => cs,
rd => rd,
wr => wr,
-- I/O interface
pa_i => pa_i,
pb_i => pb_i,
pc_i => pc_i,
pa_o => pa_o,
pb_o => pb_o,
pc_o => pc_o
);
end SYN;
| mit | 9b1787765eae9c3e4a5c0d7a3d26c456 | 0.540452 | 2.504122 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sim_1/hex2bcd_tb.vhd | 1 | 1,458 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity hex2bcd_tb is
end hex2bcd_tb;
architecture Behavioral of hex2bcd_tb is
constant clk_period : time := 10 ns;
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal strobe : std_logic := '0';
signal hex : unsigned(12 downto 0);
begin
clk <= not clk after clk_period/2;
stim : process
begin
wait for clk_period * 10;
rst <= '0';
wait for clk_period;
hex <= to_unsigned(400, hex'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 15;
hex <= to_unsigned(8191, hex'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 15;
hex <= to_unsigned(4096, hex'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 15;
hex <= to_unsigned(1, hex'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 15;
wait;
end process;
dut : entity work.hex2bcd
generic map (
precision => hex'length,
width => 16,
bits => 4 )
port map (
hex => hex,
bcd => open,
strobe => strobe,
rst => rst,
clk => clk );
end Behavioral;
| mit | bc2fc9b65d9dd5803986193e4d84d4a8 | 0.501372 | 3.777202 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/or/myOr16_tb.vhdl | 1 | 1,361 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myOr16_tb is
end myOr16_tb;
architecture behavioral of myOr16_tb is
component myOr16
port(a: in std_logic_vector(15 downto 0); b: in std_logic_vector(15 downto 0); s: out std_logic_vector(15 downto 0));
end component;
-- signals used for testing
signal s1: std_logic_vector(15 downto 0);
signal s2: std_logic_vector(15 downto 0);
signal o1: std_logic_vector(15 downto 0);
begin
-- component instantiation
myOr16_1: myOr16 port map(a => s1, b => s2, s => o1);
process
begin
s1 <= "0000000000000000";
s2 <= "0000000000000000";
wait for 1 ns;
assert o1 = "0000000000000000" report "or('0000000000000000', '0000000000000000') was not '0000000000000000'" severity error;
s1 <= "1111111100000000";
s2 <= "0000000011111111";
wait for 1 ns;
assert o1 = "1111111111111111" report "or('1111111100000000', '0000000011111111') was not '1111111111111111'" severity error;
s1 <= "0000111100001111";
s2 <= "0000111111110000";
wait for 1 ns;
assert o1 = "0000111111111111" report "or('0000111100001111', '0000111111110000') was not '0000111111111111'" severity error;
assert false report "test complete" severity note;
wait;
end process;
end behavioral;
| mit | a5f54294526d5f573e861f28cb9d5314 | 0.653196 | 3.933526 | false | false | false | false |
J-Rios/VHDL_Modules | 3.Peripherals/Debounced_Input/DEBOUNCE_bb.vhd | 1 | 17,292 |
--------------------------------------------------------
-- INSTANCE TEMPLATE
--------------------------------------------------------
-- deb_inst : entity work.DEBOUNCE
-- port map (
-- c => ,
-- r => ,
-- sw => , --input
-- db => --debounced output
-- );
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DEBOUNCE is
port(
c : in std_logic;
r : in std_logic;
sw : in std_logic;
db : out std_logic
);
end DEBOUNCE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- NO MODIFICAR ---------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
architecture BlackBox of DEBOUNCE is
signal Mcount_q_reg_cy_10_rt_2 : STD_LOGIC;
signal Mcount_q_reg_cy_11_rt_4 : STD_LOGIC;
signal Mcount_q_reg_cy_12_rt_6 : STD_LOGIC;
signal Mcount_q_reg_cy_13_rt_8 : STD_LOGIC;
signal Mcount_q_reg_cy_14_rt_10 : STD_LOGIC;
signal Mcount_q_reg_cy_15_rt_12 : STD_LOGIC;
signal Mcount_q_reg_cy_16_rt_14 : STD_LOGIC;
signal Mcount_q_reg_cy_17_rt_16 : STD_LOGIC;
signal Mcount_q_reg_cy_1_rt_18 : STD_LOGIC;
signal Mcount_q_reg_cy_2_rt_20 : STD_LOGIC;
signal Mcount_q_reg_cy_3_rt_22 : STD_LOGIC;
signal Mcount_q_reg_cy_4_rt_24 : STD_LOGIC;
signal Mcount_q_reg_cy_5_rt_26 : STD_LOGIC;
signal Mcount_q_reg_cy_6_rt_28 : STD_LOGIC;
signal Mcount_q_reg_cy_7_rt_30 : STD_LOGIC;
signal Mcount_q_reg_cy_8_rt_32 : STD_LOGIC;
signal Mcount_q_reg_cy_9_rt_34 : STD_LOGIC;
signal Mcount_q_reg_xor_18_rt_36 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N3 : STD_LOGIC;
signal N5 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal NlwRenamedSig_OI_db : STD_LOGIC;
signal m_tick : STD_LOGIC;
signal state_reg_FSM_FFd1_In_93 : STD_LOGIC;
signal state_reg_FSM_FFd2_94 : STD_LOGIC;
signal state_reg_FSM_FFd2_In_95 : STD_LOGIC;
signal state_reg_FSM_FFd3_96 : STD_LOGIC;
signal state_reg_FSM_FFd3_In_97 : STD_LOGIC;
signal Mcount_q_reg_cy : STD_LOGIC_VECTOR ( 17 downto 0 );
signal Mcount_q_reg_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal Result : STD_LOGIC_VECTOR ( 18 downto 1 );
signal m_tick_cmp_eq0000_wg_cy : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m_tick_cmp_eq0000_wg_lut : STD_LOGIC_VECTOR ( 4 downto 0 );
signal q_reg : STD_LOGIC_VECTOR ( 18 downto 0 );
begin
db <= NlwRenamedSig_OI_db;
XST_GND : GND
port map (
G => N2
);
XST_VCC : VCC
port map (
P => N3
);
q_reg_0 : FD
port map (
C => c,
D => Mcount_q_reg_lut(0),
Q => q_reg(0)
);
q_reg_1 : FD
port map (
C => c,
D => Result(1),
Q => q_reg(1)
);
q_reg_2 : FD
port map (
C => c,
D => Result(2),
Q => q_reg(2)
);
q_reg_3 : FD
port map (
C => c,
D => Result(3),
Q => q_reg(3)
);
q_reg_4 : FD
port map (
C => c,
D => Result(4),
Q => q_reg(4)
);
q_reg_5 : FD
port map (
C => c,
D => Result(5),
Q => q_reg(5)
);
q_reg_6 : FD
port map (
C => c,
D => Result(6),
Q => q_reg(6)
);
q_reg_7 : FD
port map (
C => c,
D => Result(7),
Q => q_reg(7)
);
q_reg_8 : FD
port map (
C => c,
D => Result(8),
Q => q_reg(8)
);
q_reg_9 : FD
port map (
C => c,
D => Result(9),
Q => q_reg(9)
);
q_reg_10 : FD
port map (
C => c,
D => Result(10),
Q => q_reg(10)
);
q_reg_11 : FD
port map (
C => c,
D => Result(11),
Q => q_reg(11)
);
q_reg_12 : FD
port map (
C => c,
D => Result(12),
Q => q_reg(12)
);
q_reg_13 : FD
port map (
C => c,
D => Result(13),
Q => q_reg(13)
);
q_reg_14 : FD
port map (
C => c,
D => Result(14),
Q => q_reg(14)
);
q_reg_15 : FD
port map (
C => c,
D => Result(15),
Q => q_reg(15)
);
q_reg_16 : FD
port map (
C => c,
D => Result(16),
Q => q_reg(16)
);
q_reg_17 : FD
port map (
C => c,
D => Result(17),
Q => q_reg(17)
);
q_reg_18 : FD
port map (
C => c,
D => Result(18),
Q => q_reg(18)
);
Mcount_q_reg_cy_0_Q : MUXCY
port map (
CI => N2,
DI => N3,
S => Mcount_q_reg_lut(0),
O => Mcount_q_reg_cy(0)
);
Mcount_q_reg_cy_1_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(0),
DI => N2,
S => Mcount_q_reg_cy_1_rt_18,
O => Mcount_q_reg_cy(1)
);
Mcount_q_reg_xor_1_Q : XORCY
port map (
CI => Mcount_q_reg_cy(0),
LI => Mcount_q_reg_cy_1_rt_18,
O => Result(1)
);
Mcount_q_reg_cy_2_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(1),
DI => N2,
S => Mcount_q_reg_cy_2_rt_20,
O => Mcount_q_reg_cy(2)
);
Mcount_q_reg_xor_2_Q : XORCY
port map (
CI => Mcount_q_reg_cy(1),
LI => Mcount_q_reg_cy_2_rt_20,
O => Result(2)
);
Mcount_q_reg_cy_3_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(2),
DI => N2,
S => Mcount_q_reg_cy_3_rt_22,
O => Mcount_q_reg_cy(3)
);
Mcount_q_reg_xor_3_Q : XORCY
port map (
CI => Mcount_q_reg_cy(2),
LI => Mcount_q_reg_cy_3_rt_22,
O => Result(3)
);
Mcount_q_reg_cy_4_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(3),
DI => N2,
S => Mcount_q_reg_cy_4_rt_24,
O => Mcount_q_reg_cy(4)
);
Mcount_q_reg_xor_4_Q : XORCY
port map (
CI => Mcount_q_reg_cy(3),
LI => Mcount_q_reg_cy_4_rt_24,
O => Result(4)
);
Mcount_q_reg_cy_5_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(4),
DI => N2,
S => Mcount_q_reg_cy_5_rt_26,
O => Mcount_q_reg_cy(5)
);
Mcount_q_reg_xor_5_Q : XORCY
port map (
CI => Mcount_q_reg_cy(4),
LI => Mcount_q_reg_cy_5_rt_26,
O => Result(5)
);
Mcount_q_reg_cy_6_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(5),
DI => N2,
S => Mcount_q_reg_cy_6_rt_28,
O => Mcount_q_reg_cy(6)
);
Mcount_q_reg_xor_6_Q : XORCY
port map (
CI => Mcount_q_reg_cy(5),
LI => Mcount_q_reg_cy_6_rt_28,
O => Result(6)
);
Mcount_q_reg_cy_7_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(6),
DI => N2,
S => Mcount_q_reg_cy_7_rt_30,
O => Mcount_q_reg_cy(7)
);
Mcount_q_reg_xor_7_Q : XORCY
port map (
CI => Mcount_q_reg_cy(6),
LI => Mcount_q_reg_cy_7_rt_30,
O => Result(7)
);
Mcount_q_reg_cy_8_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(7),
DI => N2,
S => Mcount_q_reg_cy_8_rt_32,
O => Mcount_q_reg_cy(8)
);
Mcount_q_reg_xor_8_Q : XORCY
port map (
CI => Mcount_q_reg_cy(7),
LI => Mcount_q_reg_cy_8_rt_32,
O => Result(8)
);
Mcount_q_reg_cy_9_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(8),
DI => N2,
S => Mcount_q_reg_cy_9_rt_34,
O => Mcount_q_reg_cy(9)
);
Mcount_q_reg_xor_9_Q : XORCY
port map (
CI => Mcount_q_reg_cy(8),
LI => Mcount_q_reg_cy_9_rt_34,
O => Result(9)
);
Mcount_q_reg_cy_10_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(9),
DI => N2,
S => Mcount_q_reg_cy_10_rt_2,
O => Mcount_q_reg_cy(10)
);
Mcount_q_reg_xor_10_Q : XORCY
port map (
CI => Mcount_q_reg_cy(9),
LI => Mcount_q_reg_cy_10_rt_2,
O => Result(10)
);
Mcount_q_reg_cy_11_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(10),
DI => N2,
S => Mcount_q_reg_cy_11_rt_4,
O => Mcount_q_reg_cy(11)
);
Mcount_q_reg_xor_11_Q : XORCY
port map (
CI => Mcount_q_reg_cy(10),
LI => Mcount_q_reg_cy_11_rt_4,
O => Result(11)
);
Mcount_q_reg_cy_12_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(11),
DI => N2,
S => Mcount_q_reg_cy_12_rt_6,
O => Mcount_q_reg_cy(12)
);
Mcount_q_reg_xor_12_Q : XORCY
port map (
CI => Mcount_q_reg_cy(11),
LI => Mcount_q_reg_cy_12_rt_6,
O => Result(12)
);
Mcount_q_reg_cy_13_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(12),
DI => N2,
S => Mcount_q_reg_cy_13_rt_8,
O => Mcount_q_reg_cy(13)
);
Mcount_q_reg_xor_13_Q : XORCY
port map (
CI => Mcount_q_reg_cy(12),
LI => Mcount_q_reg_cy_13_rt_8,
O => Result(13)
);
Mcount_q_reg_cy_14_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(13),
DI => N2,
S => Mcount_q_reg_cy_14_rt_10,
O => Mcount_q_reg_cy(14)
);
Mcount_q_reg_xor_14_Q : XORCY
port map (
CI => Mcount_q_reg_cy(13),
LI => Mcount_q_reg_cy_14_rt_10,
O => Result(14)
);
Mcount_q_reg_cy_15_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(14),
DI => N2,
S => Mcount_q_reg_cy_15_rt_12,
O => Mcount_q_reg_cy(15)
);
Mcount_q_reg_xor_15_Q : XORCY
port map (
CI => Mcount_q_reg_cy(14),
LI => Mcount_q_reg_cy_15_rt_12,
O => Result(15)
);
Mcount_q_reg_cy_16_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(15),
DI => N2,
S => Mcount_q_reg_cy_16_rt_14,
O => Mcount_q_reg_cy(16)
);
Mcount_q_reg_xor_16_Q : XORCY
port map (
CI => Mcount_q_reg_cy(15),
LI => Mcount_q_reg_cy_16_rt_14,
O => Result(16)
);
Mcount_q_reg_cy_17_Q : MUXCY
port map (
CI => Mcount_q_reg_cy(16),
DI => N2,
S => Mcount_q_reg_cy_17_rt_16,
O => Mcount_q_reg_cy(17)
);
Mcount_q_reg_xor_17_Q : XORCY
port map (
CI => Mcount_q_reg_cy(16),
LI => Mcount_q_reg_cy_17_rt_16,
O => Result(17)
);
Mcount_q_reg_xor_18_Q : XORCY
port map (
CI => Mcount_q_reg_cy(17),
LI => Mcount_q_reg_xor_18_rt_36,
O => Result(18)
);
state_reg_FSM_FFd3 : FDR
generic map(
INIT => '0'
)
port map (
C => c,
D => state_reg_FSM_FFd3_In_97,
R => r,
Q => state_reg_FSM_FFd3_96
);
state_reg_FSM_FFd1 : FDR
generic map(
INIT => '0'
)
port map (
C => c,
D => state_reg_FSM_FFd1_In_93,
R => r,
Q => NlwRenamedSig_OI_db
);
state_reg_FSM_FFd2 : FDR
generic map(
INIT => '0'
)
port map (
C => c,
D => state_reg_FSM_FFd2_In_95,
R => r,
Q => state_reg_FSM_FFd2_94
);
m_tick_cmp_eq0000_wg_lut_0_Q : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => q_reg(7),
I1 => q_reg(4),
I2 => q_reg(5),
O => m_tick_cmp_eq0000_wg_lut(0)
);
m_tick_cmp_eq0000_wg_cy_0_Q : MUXCY
port map (
CI => N3,
DI => N2,
S => m_tick_cmp_eq0000_wg_lut(0),
O => m_tick_cmp_eq0000_wg_cy(0)
);
m_tick_cmp_eq0000_wg_lut_1_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => q_reg(6),
I1 => q_reg(8),
I2 => q_reg(3),
I3 => q_reg(9),
O => m_tick_cmp_eq0000_wg_lut(1)
);
m_tick_cmp_eq0000_wg_cy_1_Q : MUXCY
port map (
CI => m_tick_cmp_eq0000_wg_cy(0),
DI => N2,
S => m_tick_cmp_eq0000_wg_lut(1),
O => m_tick_cmp_eq0000_wg_cy(1)
);
m_tick_cmp_eq0000_wg_lut_2_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => q_reg(12),
I1 => q_reg(10),
I2 => q_reg(1),
I3 => q_reg(11),
O => m_tick_cmp_eq0000_wg_lut(2)
);
m_tick_cmp_eq0000_wg_cy_2_Q : MUXCY
port map (
CI => m_tick_cmp_eq0000_wg_cy(1),
DI => N2,
S => m_tick_cmp_eq0000_wg_lut(2),
O => m_tick_cmp_eq0000_wg_cy(2)
);
m_tick_cmp_eq0000_wg_lut_3_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => q_reg(13),
I1 => q_reg(14),
I2 => q_reg(0),
I3 => q_reg(15),
O => m_tick_cmp_eq0000_wg_lut(3)
);
m_tick_cmp_eq0000_wg_cy_3_Q : MUXCY
port map (
CI => m_tick_cmp_eq0000_wg_cy(2),
DI => N2,
S => m_tick_cmp_eq0000_wg_lut(3),
O => m_tick_cmp_eq0000_wg_cy(3)
);
m_tick_cmp_eq0000_wg_lut_4_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => q_reg(16),
I1 => q_reg(17),
I2 => q_reg(2),
I3 => q_reg(18),
O => m_tick_cmp_eq0000_wg_lut(4)
);
m_tick_cmp_eq0000_wg_cy_4_Q : MUXCY
port map (
CI => m_tick_cmp_eq0000_wg_cy(3),
DI => N2,
S => m_tick_cmp_eq0000_wg_lut(4),
O => m_tick
);
state_reg_FSM_FFd1_In : LUT4
generic map(
INIT => X"D8CC"
)
port map (
I0 => state_reg_FSM_FFd3_96,
I1 => NlwRenamedSig_OI_db,
I2 => N12,
I3 => m_tick,
O => state_reg_FSM_FFd1_In_93
);
state_reg_FSM_FFd2_In : LUT4
generic map(
INIT => X"B8F0"
)
port map (
I0 => sw,
I1 => state_reg_FSM_FFd3_96,
I2 => N5,
I3 => m_tick,
O => state_reg_FSM_FFd2_In_95
);
state_reg_FSM_FFd3_In_SW0 : LUT3
generic map(
INIT => X"E7"
)
port map (
I0 => state_reg_FSM_FFd2_94,
I1 => NlwRenamedSig_OI_db,
I2 => sw,
O => N9
);
state_reg_FSM_FFd3_In : LUT4
generic map(
INIT => X"331B"
)
port map (
I0 => state_reg_FSM_FFd3_96,
I1 => N9,
I2 => N10,
I3 => m_tick,
O => state_reg_FSM_FFd3_In_97
);
Mcount_q_reg_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(1),
O => Mcount_q_reg_cy_1_rt_18
);
Mcount_q_reg_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(2),
O => Mcount_q_reg_cy_2_rt_20
);
Mcount_q_reg_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(3),
O => Mcount_q_reg_cy_3_rt_22
);
Mcount_q_reg_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(4),
O => Mcount_q_reg_cy_4_rt_24
);
Mcount_q_reg_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(5),
O => Mcount_q_reg_cy_5_rt_26
);
Mcount_q_reg_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(6),
O => Mcount_q_reg_cy_6_rt_28
);
Mcount_q_reg_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(7),
O => Mcount_q_reg_cy_7_rt_30
);
Mcount_q_reg_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(8),
O => Mcount_q_reg_cy_8_rt_32
);
Mcount_q_reg_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(9),
O => Mcount_q_reg_cy_9_rt_34
);
Mcount_q_reg_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(10),
O => Mcount_q_reg_cy_10_rt_2
);
Mcount_q_reg_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(11),
O => Mcount_q_reg_cy_11_rt_4
);
Mcount_q_reg_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(12),
O => Mcount_q_reg_cy_12_rt_6
);
Mcount_q_reg_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(13),
O => Mcount_q_reg_cy_13_rt_8
);
Mcount_q_reg_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(14),
O => Mcount_q_reg_cy_14_rt_10
);
Mcount_q_reg_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(15),
O => Mcount_q_reg_cy_15_rt_12
);
Mcount_q_reg_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(16),
O => Mcount_q_reg_cy_16_rt_14
);
Mcount_q_reg_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(17),
O => Mcount_q_reg_cy_17_rt_16
);
Mcount_q_reg_xor_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => q_reg(18),
O => Mcount_q_reg_xor_18_rt_36
);
Mcount_q_reg_lut_0_INV_0 : INV
port map (
I => q_reg(0),
O => Mcount_q_reg_lut(0)
);
state_reg_FSM_FFd1_In_SW0 : LUT3_D
generic map(
INIT => X"E8"
)
port map (
I0 => state_reg_FSM_FFd2_94,
I1 => NlwRenamedSig_OI_db,
I2 => sw,
LO => N12,
O => N5
);
state_reg_FSM_FFd3_In_SW1 : LUT2_L
generic map(
INIT => X"9"
)
port map (
I0 => NlwRenamedSig_OI_db,
I1 => sw,
LO => N10
);
end BlackBox;
| gpl-3.0 | 202b170c5e9d80289cba6d9edc8f1d0b | 0.452406 | 2.664817 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue3/Keyboard/key2segments.vhd | 1 | 1,939 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:08:31 07/07/2016
-- Design Name:
-- Module Name: key2segments - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity key2segments is
Port ( scancode : in STD_LOGIC_VECTOR(7 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end key2segments;
architecture Behavioral of key2segments is
begin
process (scancode)
begin
case scancode is
when "00010110" => segments <= "1001111"; --1
when "00011110" => segments <= "0010010"; --2
when "00100110" => segments <= "0000110"; --3
when "00100101" => segments <= "1001100"; --4
when "00101110" => segments <= "0100100"; --5
when "00110110" => segments <= "0100000"; --6
when "00111101" => segments <= "0001111"; --7
when "00111110" => segments <= "0000000"; --8
when "01000110" => segments <= "0000100"; --9
when "01000101" => segments <= "0000001"; --0
when "00011100" => segments <= "0001000"; --A
when "00110010" => segments <= "1100000"; --b
when "00100001" => segments <= "0110001"; --c
when "00100011" => segments <= "1000010"; --d
when "00100100" => segments <= "0110000"; --E
when "00101011" => segments <= "0111000"; --F
when others => segments <= "1000001"; --u;
end case;
end process;
end Behavioral;
| mit | 2c015996f60c87dd778129238562134e | 0.585869 | 3.816929 | false | false | false | false |
Fju/LeafySan | src/vhdl/testbench/lcd_model.vhdl | 1 | 6,600 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : LCD-Display Model
-- Last update : 04.12.2013
-----------------------------------------------------------------
-- Libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity lcd_model is
generic(
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
FULL_DEBUG : natural := 0
);
port(
-- Global Signals
end_simulation : in std_ulogic;
-- LCD Signals
disp_en : in std_ulogic;
disp_rs : in std_ulogic;
disp_rw : in std_ulogic;
disp_dat : in std_ulogic_vector(7 downto 0)
);
end entity lcd_model;
architecture sim of lcd_model is
type lcd_t is array (0 to 1) of string(1 to 16);
begin
process
variable lcd : lcd_t;
variable col, row : integer;
variable outLine : line;
variable disp_on : std_ulogic;
variable cursor_on : std_ulogic;
variable blink_on : std_ulogic;
begin
lcd := (others => (others => ' '));
col := 0;
row := 0;
disp_on := '0';
cursor_on := '0';
blink_on := '0';
loop
exit when end_simulation = '1';
if disp_en = '1' then
-- Function setting
if disp_rs = '0' then
-- Set DDRAM Address (Set Cursor)
if disp_dat(7) = '1' then
col := to_integer(unsigned(disp_dat(3 downto 0)));
row := to_integer(unsigned(disp_dat(6 downto 6)));
if FULL_DEBUG = 1 then
write(outLine, "[LCD] Setting cursor to position " & integer'image(col) & " and line " & integer'image(row));
writeline(output, outLine);
end if;
-- Set CDRAM Address (can't happen)
elsif disp_dat(6) = '1' then
-- not implemented yet
-- Function set
elsif disp_dat(5) = '1' then
if FULL_DEBUG = 1 then
write(outLine, string'("[LCD] Function setting: "));
writeline(output, outLine);
if disp_dat(4) = '1' then
write(outLine, string'(" Data width -> 8 bit"));
else
write(outLine, string'(" Data width -> 4 bit"));
end if;
writeline(output, outLine);
if disp_dat(3) = '1' then
write(outLine, string'(" Number lines -> 2"));
else
write(outLine, string'(" Number lines -> 1"));
end if;
writeline(output, outLine);
if disp_dat(2) = '1' then
write(outLine, string'(" Dots format -> 5x11"));
else
write(outLine, string'(" Dots format -> 5x8"));
end if;
writeline(output, outLine);
end if;
-- Cursor or Display Shift
elsif disp_dat(4) = '1' then
if FULL_DEBUG = 1 then
write(outLine, string'("[LCD] Setting "));
if disp_dat(3) = '1' then
write(outLine, string'("shift all the display "));
else
write(outLine, string'("shift cursor "));
end if;
if disp_dat(2) = '1' then
write(outLine, string'("to right"));
else
write(outLine, string'("to left"));
end if;
writeline(output, outLine);
end if;
-- Display On/Off Control
elsif disp_dat(3) = '1' then
-- Display on/off
if disp_dat(2) /= disp_on then
disp_on := disp_dat(2);
if FULL_DEBUG = 1 then
if disp_dat(2) = '1' then
write(outLine, string'("[LCD] Setting display on"));
else
write(outLine, string'("[LCD] Setting display off"));
end if;
writeline(output, outLine);
end if;
end if;
-- Cursor on/off
if disp_dat(1) /= cursor_on then
cursor_on := disp_dat(1);
if FULL_DEBUG = 1 then
if disp_dat(1) = '1' then
write(outLine, string'("[LCD] Setting cursor on"));
else
write(outLine, string'("[LCD] Setting cursor off"));
end if;
writeline(output, outLine);
end if;
end if;
-- Blink on/off
if disp_dat(0) /= blink_on then
blink_on := disp_dat(0);
if FULL_DEBUG = 1 then
if disp_dat(0) = '1' then
write(outLine, string'("[LCD] Setting blink on"));
else
write(outLine, string'("[LCD] Setting blink off"));
end if;
writeline(output, outLine);
end if;
end if;
-- Entry mode set
elsif disp_dat(2) = '1' then
if FULL_DEBUG = 1 then
write(outLine, string'("[LCD] Setting "));
if disp_dat(1) = '1' then
write(outLine, string'("DDRAM increment mode, "));
else
write(outLine, string'("DDRAM decrement mode, "));
end if;
if disp_dat(0) = '1' then
write(outLine, string'("shift entire display on"));
else
write(outLine, string'("shift entire display off"));
end if;
writeline(output, outLine);
end if;
-- Return Home
elsif disp_dat(1) = '1' then
col := 0;
row := 0;
if FULL_DEBUG = 1 then
write(outLine, string'("[LCD] Setting cursor to position " & integer'image(col) & " and line " & integer'image(row)));
writeline(output, outLine);
end if;
-- Clear Display
else
lcd := (others => (others => ' '));
col := 0;
row := 0;
write(outLine, string'("[LCD] Clear Display"));
writeline(output, outLine);
write(outLine, string'("[LCD] Actual display:"));
writeline(output, outLine);
write(outLine, string'(" Line 0: |" & lcd(0) & "|"));
writeline(output, outLine);
write(outLine, string'(" Line 1: |" & lcd(1) & "|"));
writeline(output, outLine);
if FULL_DEBUG = 1 then
write(outLine, string'("[LCD] Setting cursor to position " & integer'image(col) & " and line " & integer'image(row)));
writeline(output, outLine);
end if;
end if;
-- Print charachter
else
lcd(row)(col+1) := character'val(to_integer(unsigned(disp_dat)));
write(outLine, string'("[LCD] Printing character '" & lcd(row)(col+1) & "' on LCD"));
writeline(output, outLine);
write(outLine, string'("[LCD] Actual display:"));
writeline(output, outLine);
write(outLine, string'(" Line 0: |" & lcd(0) & "|"));
writeline(output, outLine);
write(outLine, string'(" Line 1: |" & lcd(1) & "|"));
writeline(output, outLine);
end if;
wait until disp_en = '0';
else
wait for SYSTEM_CYCLE_TIME;
end if;
end loop;
wait;
end process;
end architecture sim; | apache-2.0 | 32d1c554d9f79aea70554731f7806940 | 0.530606 | 3.407331 | false | false | false | false |
maly/fpmi | FPGA/ram2.vhd | 1 | 9,287 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram2.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram2 IS
PORT
(
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram2;
ARCHITECTURE SYN OF ram2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
ram_block_type => "M4K",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => 10,
widthad_b => 10,
width_a => 8,
width_b => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => clock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram2.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit | 973e4c68abdbc3892892378f1fe3e2a8 | 0.680521 | 3.426937 | false | false | false | false |
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