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fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/rd_pe_as.vhd | 9 | 25,068 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 088049b8e70995a35cb30da3c99d1873 | 0.942995 | 1.82273 | false | false | false | false |
inmcm/Simon_Speck_Ciphers | VHDL/Speck.vhd | 3 | 11,909 | -- Speck.vhd
-- Copyright 2016 Michael Calvin McCoy
-- [email protected]
-- see LICENSE.md
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.SPECK_CONSTANTS.all;
entity SPECK_CIPHER is
Generic(KEY_SIZE : integer range 0 to 256 := 256;
BLOCK_SIZE : integer range 0 to 128 := 128;
ROUND_LIMIT: integer range 0 to 34 := 34);
Port (SYS_CLK,RST : in std_logic;
BUSY : out std_logic;
CONTROL : in std_logic_vector(1 downto 0);
KEY : in std_logic_vector (KEY_SIZE - 1 downto 0);
BLOCK_INPUT : in std_logic_vector (BLOCK_SIZE - 1 downto 0);
BLOCK_OUTPUT : out std_logic_vector (BLOCK_SIZE - 1 downto 0));
end SPECK_CIPHER;
architecture Behavioral of SPECK_CIPHER is
-------------------------------------------------------------
-- Cipher Constants
constant WORD_SIZE : integer range 0 to 64 := BLOCK_SIZE / 2;
constant KEY_WORDS_M : integer range 0 to 4 := KEY_SIZE / WORD_SIZE;
constant ALPHA_SHIFT : integer range 0 to 15 := Alpha_Lookup(KEY_SIZE, BLOCK_SIZE);
constant BETA_SHIFT : integer range 0 to 3 := Beta_Lookup(KEY_SIZE, BLOCK_SIZE);
-------------------------------------------------------------
-- Key Schedule Storage Array
type ARRAY_ROUNDxWORDSIZE is array(0 to (ROUND_LIMIT - 1)) of std_logic_vector(WORD_SIZE - 1 downto 0);
signal key_schedule: ARRAY_ROUNDxWORDSIZE;
signal round_key : std_logic_vector(WORD_SIZE - 1 downto 0);
type ARRAY_PARTKEYxWORD is array (0 to KEY_WORDS_M-1) of std_logic_vector(WORD_SIZE - 1 downto 0);
signal key_l : ARRAY_PARTKEYxWORD;
signal key_feedback : ARRAY_PARTKEYxWORD;
signal key_gen_round_output : STD_LOGIC_VECTOR(BLOCK_SIZE - 1 downto 0);
------------------------------------------------------
-- Fiestel Structure Signals
signal b_buf : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal a_buf : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal encryption_round_output : STD_LOGIC_VECTOR(BLOCK_SIZE - 1 downto 0);
signal decryption_round_output : STD_LOGIC_VECTOR(BLOCK_SIZE - 1 downto 0);
--------------------------------------------------------
--------------------------------------------------------
-- State Machine Signals
type state is (Reset,Idle,Key_Schedule_Generation_Run,Key_Schedule_Generation_Finish,
Cipher_Start,Cipher_Run,Cipher_Finish_1,Cipher_Finish_2,Cipher_Latch);
signal pr_state,nx_state : state;
--------------------------------------------------------
--------------------------------------------------------
-- Round Counting Signals
signal round_count : integer range 0 to (ROUND_LIMIT - 1);
signal inv_round_count : integer range 0 to (ROUND_LIMIT - 1);
signal round_count_mux : integer range 0 to (ROUND_LIMIT - 1);
signal cipher_direction : std_logic;
--------------------------------------------------------
function Encrypt_Round(b, a, key_i : std_logic_vector(WORD_SIZE -1 downto 0)) return std_logic_vector is
variable b_unsigned : unsigned(WORD_SIZE - 1 downto 0);
variable a_unsigned : unsigned(WORD_SIZE - 1 downto 0);
variable r_shift_alpha : unsigned(WORD_SIZE - 1 downto 0);
variable l_shift_beta : unsigned(WORD_SIZE - 1 downto 0);
variable adder: unsigned(WORD_SIZE - 1 downto 0);
variable key_xor : unsigned(WORD_SIZE - 1 downto 0);
variable cross_xor : unsigned(WORD_SIZE - 1 downto 0);
variable encrypt_output : std_logic_vector(BLOCK_SIZE - 1 downto 0);
begin
b_unsigned := unsigned(b);
a_unsigned := unsigned(a);
r_shift_alpha := b_unsigned(ALPHA_SHIFT - 1 downto 0) & b_unsigned(WORD_SIZE -1 downto ALPHA_SHIFT);
l_shift_beta := a_unsigned(WORD_SIZE - (BETA_SHIFT + 1) downto 0) & a_unsigned((WORD_SIZE -1) downto (WORD_SIZE - BETA_SHIFT));
adder := r_shift_alpha + a_unsigned;
key_xor := adder xor unsigned(key_i);
cross_xor := l_shift_beta xor key_xor;
encrypt_output := std_logic_vector(key_xor) & std_logic_vector(cross_xor);
return encrypt_output;
end Encrypt_Round;
function Decrypt_Round(b, a, key_i : std_logic_vector(WORD_SIZE -1 downto 0)) return std_logic_vector is
variable b_unsigned : unsigned(WORD_SIZE - 1 downto 0);
variable a_unsigned : unsigned(WORD_SIZE - 1 downto 0);
variable l_shift_alpha : unsigned(WORD_SIZE - 1 downto 0);
variable r_shift_beta : unsigned(WORD_SIZE - 1 downto 0);
variable subtractor: unsigned(WORD_SIZE - 1 downto 0);
variable key_xor : unsigned(WORD_SIZE - 1 downto 0);
variable cross_xor : unsigned(WORD_SIZE - 1 downto 0);
variable decrypt_output : std_logic_vector(BLOCK_SIZE - 1 downto 0);
begin
b_unsigned := unsigned(b);
a_unsigned := unsigned(a);
cross_xor := b_unsigned xor a_unsigned;
r_shift_beta := cross_xor(BETA_SHIFT - 1 downto 0) & cross_xor(WORD_SIZE -1 downto BETA_SHIFT);
key_xor := b_unsigned xor unsigned(key_i);
subtractor := key_xor - r_shift_beta;
l_shift_alpha := subtractor(WORD_SIZE - (ALPHA_SHIFT + 1) downto 0) & subtractor((WORD_SIZE -1) downto (WORD_SIZE - ALPHA_SHIFT));
decrypt_output := std_logic_vector(l_shift_alpha) & std_logic_vector(r_shift_beta);
return decrypt_output;
end Decrypt_Round;
begin
----------------------------------------------------------------------
-- State Machine Processes
----------------------------------------------------------------------
State_Machine_Head : process (SYS_CLK) ----State Machine Master Control
begin
if (SYS_CLK'event and SYS_CLK='1') then
if (RST = '1') then
pr_state <= RESET;
else
pr_state <= nx_state;
end if;
end if;
end process; -- State_Machine_Head
State_Machine_Body : process (CONTROL, round_count, pr_state) ---State Machine State Definitions
begin
case pr_state is
when Reset => --Master Reset State
nx_state <= Idle;
when Idle =>
if (CONTROL = "01") then
nx_state <= Key_Schedule_Generation_Run;
elsif (CONTROL = "11" or CONTROL = "10") then
nx_state <= Cipher_Start;
else
nx_state <= Idle;
end if;
when Key_Schedule_Generation_Run =>
if (round_count = ROUND_LIMIT - 2) then
nx_state <= Key_Schedule_Generation_Finish;
else
nx_state <= Key_Schedule_Generation_Run;
end if;
when Key_Schedule_Generation_Finish =>
nx_state <= Idle;
when Cipher_Start =>
nx_state <= Cipher_Run;
when Cipher_Run =>
if (round_count = ROUND_LIMIT - 2) then
nx_state <= Cipher_Finish_1;
else
nx_state <= Cipher_Run;
end if;
when Cipher_Finish_1 =>
nx_state <= Cipher_Finish_2;
when Cipher_Finish_2 =>
nx_state <= Cipher_Latch;
when Cipher_Latch =>
nx_state <= Idle;
end case;
end process;
----------------------------------------------------------------------
-- END State Machine Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Register Processes
----------------------------------------------------------------------
Cipher_Direction_Flag : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Reset) then
cipher_direction <= '0';
elsif (pr_state = Idle) then
cipher_direction <= CONTROL(0);
end if ;
end if;
end process;
Busy_Flag_Generator : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Reset or (pr_state = Idle and CONTROL /= "00")) then
BUSY <= '1';
elsif ((pr_state = Idle and CONTROL = "00") or pr_state = Cipher_Latch or pr_state = Key_Schedule_Generation_Finish) then
BUSY <= '0';
end if;
end if;
end process ; -- Busy_Flag_Generator
Key_Schedule_Generator : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Idle) then
Init_Gen_Regs : for i in 0 to (KEY_WORDS_M -1) loop
key_l(i) <= key(((i + 1) * WORD_SIZE) - 1 downto (i * WORD_SIZE));
end loop ; -- Update_Gen_Regs
elsif (pr_state = Key_Schedule_Generation_Run or pr_state = Key_Schedule_Generation_Finish) then
for i in 0 to (KEY_WORDS_M - 1) loop
key_l(i) <= key_feedback(i);
end loop;
end if;
end if;
end process ; -- Key_Schedule_Generator
Main_Cipher_Process : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
-- Load for Encryption/Decryption
if (pr_state = Idle) then
if (CONTROL(1) = '1') then
a_buf <= BLOCK_INPUT(WORD_SIZE - 1 downto 0);
b_buf <= BLOCK_INPUT(BLOCK_SIZE - 1 downto WORD_SIZE);
end if;
-- Run Cipher Engine
elsif (pr_state = Cipher_Run or pr_state = Cipher_Finish_1 or pr_state = Cipher_Finish_2) then
if (cipher_direction = '1') then -- Encryption
a_buf <= encryption_round_output(WORD_SIZE - 1 downto 0);
b_buf <= encryption_round_output(BLOCK_SIZE - 1 downto WORD_SIZE);
else -- Decryption
a_buf <= decryption_round_output(WORD_SIZE - 1 downto 0);
b_buf <= decryption_round_output(BLOCK_SIZE - 1 downto WORD_SIZE);
end if;
end if;
end if;
end process ;
Output_Buffer : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Cipher_Latch) then
BLOCK_OUTPUT <= b_buf & a_buf;
end if;
end if;
end process ; -- Output_Buffer
----------------------------------------------------------------------
-- END Register Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- RAM Processes
----------------------------------------------------------------------
Key_Schedule_Array: process (SYS_CLK)
begin
if (SYS_CLK'event and SYS_CLK = '1') then
round_key <= key_schedule(round_count_mux);
if (pr_state = Key_Schedule_Generation_Run or pr_state = Key_Schedule_Generation_Finish) then
key_schedule(round_count) <= key_l(0);
end if;
end if;
end process;
----------------------------------------------------------------------
-- End RAM Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Counter Processes
----------------------------------------------------------------------
Round_Counter : process(SYS_CLK)
begin
if (SYS_CLK'event and SYS_CLK = '1') then
if (pr_state = Reset) then
round_count <= 0;
inv_round_count <= 0;
elsif (pr_state = Idle) then
round_count <= 0;
inv_round_count <= ROUND_LIMIT - 1;
elsif (pr_state = Cipher_Start or pr_state = Cipher_Run or pr_state = Key_Schedule_Generation_Run) then
round_count <= round_count + 1;
inv_round_count <= inv_round_count - 1;
end if ;
end if ;
end process;
----------------------------------------------------------------------
-- END Counter Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Async Signals
----------------------------------------------------------------------
round_count_mux <= round_count when cipher_direction = '1' else inv_round_count;
key_gen_round_output <= Encrypt_Round(key_l(1), key_l(0), std_logic_vector(to_unsigned(round_count, WORD_SIZE)));
encryption_round_output <= Encrypt_Round(b_buf, a_buf, round_key);
decryption_round_output <= Decrypt_Round(b_buf, a_buf, round_key);
key_feedback(0) <= key_gen_round_output(WORD_SIZE - 1 downto 0);
key_feedback(KEY_WORDS_M - 1) <= key_gen_round_output(BLOCK_SIZE - 1 downto WORD_SIZE);
Keys_3 : if (KEY_WORDS_M = 3) generate
begin
key_feedback(1) <= key_l(2);
end generate;
Keys_4 : if (KEY_WORDS_M = 4) generate
begin
key_feedback(1) <= key_l(2);
key_feedback(2) <= key_l(3);
end generate;
end Behavioral;
| mit | 2b5f11ceb199fd3cd59bbb4971a8f3aa | 0.555546 | 3.516091 | false | false | false | false |
ymei/TMSPlane | Firmware/src/ten_gig_eth/TE07412C1/fifo/ten_gig_eth_mac_0_xgmac_fifo.vhd | 3 | 10,927 | -------------------------------------------------------------------------------
-- Title : XG MAC Tx/Rx FIFO Wrapper
-- Project : 10 Gig Ethernet MAC Core
-------------------------------------------------------------------------------
-- File : ten_gig_eth_mac_0_xgmac_fifo.vhd
-- Author : Xilinx Inc.
-------------------------------------------------------------------------------
-- Description:
-- This module is the top level entity for the 10 Gig Ethernet MAC FIFO
-- This top level connects together the lower hierarchial
-- entities which create this design. This is illustrated below.
-------------------------------------------------------------------------------
--
-- .---------------------------------------------.
-- | |
-- | .----------------------------. |
-- | | TRANSMIT_FIFO | |
-- ---------|------>| |--------|-------> MAC Tx
-- | | | | Interface
-- | '----------------------------' |
-- | |
-- | |
-- | |
-- External | |
-- AXI-S | |
-- Interface | |
-- | |
-- | .----------------------------. |
-- | | RECEIVE_FIFO | |
-- <--------|-------| |<-------|-------- MAC Rx Interface
-- | | | |
-- | '----------------------------' |
-- | |
-- | |
-- | |
-- | |
-- | |
-- '---------------------------------------------'
--
-------------------------------------------------------------------------------
-- Functionality:
--
-- 1. TRANSMIT_FIFO accepts 64-bit data from the client and writes
-- this into the Transmitter FIFO. The logic will then extract this from
-- the FIFO and write this data to the MAC Transmitter in 64-bit words.
--
-- 2. RECEIVE_FIFO accepts 64-bit data from the MAC Receiver and
-- writes this into the Receiver FIFO. The client inferface can then
-- read 64-bit words from this FIFO.
--
-------------------------------------------------------------------------------
-- (c) Copyright 2001-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.xgmac_fifo_pack.all;
entity ten_gig_eth_mac_0_xgmac_fifo is
generic (
TX_FIFO_SIZE : integer := 512; -- valid fifo sizes: 512, 1024, 2048, 4096, 8192, 16384 words.
RX_FIFO_SIZE : integer := 512); -- valid fifo sizes: 512, 1024, 2048, 4096, 8192, 16384 words.
port (
----------------------------------------------------------------
-- client interface --
----------------------------------------------------------------
-- tx_wr_clk domain
tx_axis_fifo_aresetn : in std_logic; -- the transmit client clock.
tx_axis_fifo_aclk : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(63 downto 0);
tx_axis_fifo_tkeep : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_fifo_full : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
--rx_rd_clk domain
rx_axis_fifo_aresetn : in std_logic;
rx_axis_fifo_aclk : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(63 downto 0);
rx_axis_fifo_tkeep : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
---------------------------------------------------------------------------
-- mac transmitter interface --
---------------------------------------------------------------------------
tx_axis_mac_aresetn : in std_logic;
tx_axis_mac_aclk : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(63 downto 0);
tx_axis_mac_tkeep : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
---------------------------------------------------------------------------
-- mac receiver interface --
---------------------------------------------------------------------------
rx_axis_mac_aresetn : in std_logic;
rx_axis_mac_aclk : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(63 downto 0);
rx_axis_mac_tkeep : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_full : out std_logic
);
end ten_gig_eth_mac_0_xgmac_fifo;
architecture rtl of ten_gig_eth_mac_0_xgmac_fifo is
component ten_gig_eth_mac_0_axi_fifo is
generic (
FIFO_SIZE : integer := 512;
WR_FLOW_CTRL : boolean := false);
port (
-- FIFO write domain
wr_axis_aresetn : in std_logic;
wr_axis_aclk : in std_logic;
wr_axis_tdata : in std_logic_vector(63 downto 0);
wr_axis_tkeep : in std_logic_vector(7 downto 0);
wr_axis_tvalid : in std_logic;
wr_axis_tlast : in std_logic;
wr_axis_tready : out std_logic;
wr_axis_tuser : in std_logic;
-- FIFO read domain
rd_axis_aresetn : in std_logic;
rd_axis_aclk : in std_logic;
rd_axis_tdata : out std_logic_vector(63 downto 0);
rd_axis_tkeep : out std_logic_vector(7 downto 0);
rd_axis_tvalid : out std_logic;
rd_axis_tlast : out std_logic;
rd_axis_tready : in std_logic;
-- FIFO Status Signals
fifo_status : out std_logic_vector(3 downto 0);
fifo_full : out std_logic );
end component;
begin
--Instance the transmit fifo.
i_tx_fifo : ten_gig_eth_mac_0_axi_fifo
generic map(
FIFO_SIZE => TX_FIFO_SIZE,
WR_FLOW_CTRL => true)
port map (
wr_axis_aresetn => tx_axis_fifo_aresetn,
wr_axis_aclk => tx_axis_fifo_aclk,
wr_axis_tdata => tx_axis_fifo_tdata,
wr_axis_tkeep => tx_axis_fifo_tkeep,
wr_axis_tvalid => tx_axis_fifo_tvalid,
wr_axis_tlast => tx_axis_fifo_tlast,
wr_axis_tready => tx_axis_fifo_tready,
wr_axis_tuser => tx_axis_fifo_tlast,
rd_axis_aresetn => tx_axis_mac_aresetn,
rd_axis_aclk => tx_axis_mac_aclk,
rd_axis_tdata => tx_axis_mac_tdata,
rd_axis_tkeep => tx_axis_mac_tkeep,
rd_axis_tvalid => tx_axis_mac_tvalid,
rd_axis_tlast => tx_axis_mac_tlast,
rd_axis_tready => tx_axis_mac_tready,
fifo_status => tx_fifo_status,
fifo_full => tx_fifo_full);
--Instance the receive fifo
rx_fifo_inst : ten_gig_eth_mac_0_axi_fifo
generic map (
FIFO_SIZE => RX_FIFO_SIZE,
WR_FLOW_CTRL => false)
port map (
wr_axis_aresetn => rx_axis_mac_aresetn,
wr_axis_aclk => rx_axis_mac_aclk,
wr_axis_tdata => rx_axis_mac_tdata,
wr_axis_tkeep => rx_axis_mac_tkeep,
wr_axis_tvalid => rx_axis_mac_tvalid,
wr_axis_tlast => rx_axis_mac_tlast,
wr_axis_tready => open,
wr_axis_tuser => rx_axis_mac_tuser,
rd_axis_aresetn => rx_axis_fifo_aresetn,
rd_axis_aclk => rx_axis_fifo_aclk,
rd_axis_tdata => rx_axis_fifo_tdata,
rd_axis_tkeep => rx_axis_fifo_tkeep,
rd_axis_tvalid => rx_axis_fifo_tvalid,
rd_axis_tlast => rx_axis_fifo_tlast,
rd_axis_tready => rx_axis_fifo_tready,
fifo_status => rx_fifo_status,
fifo_full => rx_fifo_full);
end rtl;
| bsd-3-clause | 39780fc90c2feefad427877771b3916a | 0.486867 | 4.142153 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/sym_gen.vhd | 4 | 13,857 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: sym_gen_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- SYM_GEN
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- Description: The SYM_GEN module is a symbol generator for 2-byte Aurora Lanes.
-- Its inputs request the transmission of specific symbols, and its
-- outputs drive the MGT interface to fulfil those requests.
--
-- All generation request inputs must be asserted exclusively
-- except for the GEN_K, GEN_R and GEN_A signals from the Global
-- Logic, and the GEN_PAD and TX_PE_DATA_V signals from TX_LL.
--
-- GEN_K, GEN_R and GEN_A can be asserted anytime, but they are
-- ignored when other signals are being asserted. This allows the
-- idle generator in the Global Logic to run continuosly without
-- feedback, but requires the TX_LL and Lane Init SM modules to
-- be quiescent during Channel Bonding and Verification.
--
-- The GEN_PAD signal is only valid while the TX_PE_DATA_V signal
-- is asserted. This allows padding to be specified for the LSB of
-- the data transmission. GEN_PAD must not be asserted when
-- TX_PE_DATA_V is not asserted - this will generate errors.
--
-- This module supports Immediate Mode Native Flow Control.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SYM_GEN is
port (
-- TX_LL Interface -- See description for info about GEN_PAD and TX_PE_DATA_V.
GEN_SCP : in std_logic; -- Generate SCP.
GEN_ECP : in std_logic; -- Generate ECP.
GEN_SNF : in std_logic; -- Generate SNF using code given by FC_NB.
GEN_PAD : in std_logic; -- Replace LSB with Pad character.
FC_NB : in std_logic_vector(0 to 3); -- Size code for Flow Control messages.
TX_PE_DATA : in std_logic_vector(0 to 15); -- Data. Transmitted when TX_PE_DATA_V is asserted.
TX_PE_DATA_V : in std_logic; -- Transmit data.
GEN_CC : in std_logic; -- Generate Clock Correction symbols.
-- Global Logic Interface -- See description for info about GEN_K,GEN_R and GEN_A.
GEN_A : in std_logic; -- Generate A character for selected bytes.
GEN_K : in std_logic_vector(0 to 1); -- Generate K character for selected bytes.
GEN_R : in std_logic_vector(0 to 1); -- Generate R character for selected bytes.
GEN_V : in std_logic_vector(0 to 1); -- Generate Ver data character on selected bytes.
-- Lane Init SM Interface
GEN_K_FSM : in std_logic; -- Generate K character on byte 0.
GEN_SP_DATA : in std_logic_vector(0 to 1); -- Generate SP data character on selected bytes.
GEN_SPA_DATA : in std_logic_vector(0 to 1); -- Generate SPA data character on selected bytes.
-- MGT Interface
TX_CHAR_IS_K : out std_logic_vector(1 downto 0); -- Transmit TX_DATA as a control character.
TX_DATA : out std_logic_vector(15 downto 0); -- Data to MGT for transmission to channel partner.
-- System Interface
USER_CLK : in std_logic -- Clock for all non-MGT Aurora Logic.
);
end SYM_GEN;
architecture RTL of SYM_GEN is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal TX_CHAR_IS_K_Buffer : std_logic_vector(1 downto 0);
signal TX_DATA_Buffer : std_logic_vector(15 downto 0);
-- Internal Register Declarations --
-- Slack registers. Allow slack for routing delay and automatic retiming.
signal gen_scp_r : std_logic;
signal gen_ecp_r : std_logic;
signal gen_snf_r : std_logic;
signal gen_pad_r : std_logic;
signal fc_nb_r : std_logic_vector(0 to 3);
signal tx_pe_data_r : std_logic_vector(0 to 15);
signal tx_pe_data_v_r : std_logic;
signal gen_cc_r : std_logic;
signal gen_a_r : std_logic;
signal gen_k_r : std_logic_vector(0 to 1);
signal gen_r_r : std_logic_vector(0 to 1);
signal gen_v_r : std_logic_vector(0 to 1);
signal gen_k_fsm_r : std_logic;
signal gen_sp_data_r : std_logic_vector(0 to 1);
signal gen_spa_data_r : std_logic_vector(0 to 1);
-- Wire Declarations --
signal idle_c : std_logic_vector(0 to 1);
begin
TX_CHAR_IS_K <= TX_CHAR_IS_K_Buffer;
TX_DATA <= TX_DATA_Buffer;
-- Main Body of Code --
-- Register all inputs with the slack registers.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
gen_scp_r <= GEN_SCP after DLY;
gen_ecp_r <= GEN_ECP after DLY;
gen_snf_r <= GEN_SNF after DLY;
gen_pad_r <= GEN_PAD after DLY;
fc_nb_r <= FC_NB after DLY;
tx_pe_data_r <= TX_PE_DATA after DLY;
tx_pe_data_v_r <= TX_PE_DATA_V after DLY;
gen_cc_r <= GEN_CC after DLY;
gen_a_r <= GEN_A after DLY;
gen_k_r <= GEN_K after DLY;
gen_r_r <= GEN_R after DLY;
gen_v_r <= GEN_V after DLY;
gen_k_fsm_r <= GEN_K_FSM after DLY;
gen_sp_data_r <= GEN_SP_DATA after DLY;
gen_spa_data_r <= GEN_SPA_DATA after DLY;
end if;
end process;
-- When none of the msb non_idle inputs are asserted, allow idle characters.
idle_c(0) <= not (gen_scp_r or
gen_ecp_r or
gen_snf_r or
tx_pe_data_v_r or
gen_cc_r or
gen_k_fsm_r or
gen_sp_data_r(0) or
gen_spa_data_r(0) or
gen_v_r(0));
-- Generate data for MSB. Note that all inputs must be asserted exclusively, except
-- for the GEN_A, GEN_K and GEN_R inputs which are ignored when other characters
-- are asserted.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (gen_scp_r = '1') then
TX_DATA_Buffer(15 downto 8) <= X"5C" after DLY; -- K28.2(SCP)
end if;
if (gen_ecp_r = '1') then
TX_DATA_Buffer(15 downto 8) <= X"FD" after DLY; -- K29.7(ECP)
end if;
if (gen_snf_r = '1') then
TX_DATA_Buffer(15 downto 8) <= X"DC" after DLY; -- K28.6(SNF)
end if;
if (tx_pe_data_v_r = '1') then
TX_DATA_Buffer(15 downto 8) <= tx_pe_data_r(0 to 7) after DLY; -- DATA
end if;
if (gen_cc_r = '1') then
TX_DATA_Buffer(15 downto 8) <= X"F7" after DLY; -- K23.7(CC)
end if;
if ((idle_c(0) and gen_a_r) = '1') then
TX_DATA_Buffer(15 downto 8) <= X"7C" after DLY; -- K28.3(A)
end if;
if ((idle_c(0) and gen_k_r(0)) = '1') then
TX_DATA_Buffer(15 downto 8) <= X"BC" after DLY; -- K28.5(K)
end if;
if ((idle_c(0) and gen_r_r(0)) = '1') then
TX_DATA_Buffer(15 downto 8) <= X"1C" after DLY; -- K28.0(R)
end if;
if (gen_k_fsm_r = '1') then
TX_DATA_Buffer(15 downto 8) <= X"BC" after DLY; -- K28.5(K)
end if;
if (gen_sp_data_r(0) = '1') then
TX_DATA_Buffer(15 downto 8) <= X"4A" after DLY; -- D10.2(SP data)
end if;
if (gen_spa_data_r(0) = '1') then
TX_DATA_Buffer(15 downto 8) <= X"2C" after DLY; -- D12.1(SPA data)
end if;
if (gen_v_r(0) = '1') then
TX_DATA_Buffer(15 downto 8) <= X"E8" after DLY; -- D8.7(Ver data)
end if;
end if;
end process;
-- Generate control signal for MSB.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
TX_CHAR_IS_K_Buffer(1) <= not (tx_pe_data_v_r or
gen_sp_data_r(0) or
gen_spa_data_r(0) or
gen_v_r(0)) after DLY;
end if;
end process;
-- When none of the msb non_idle inputs are asserted, allow idle characters. Note that
-- because gen_pad is only valid with the data valid signal, we only look at the data
-- valid signal.
idle_c(1) <= not (gen_scp_r or
gen_ecp_r or
gen_snf_r or
tx_pe_data_v_r or
gen_cc_r or
gen_sp_data_r(1) or
gen_spa_data_r(1) or
gen_v_r(1));
-- Generate data for LSB. Note that all inputs must be asserted exclusively except for
-- the GEN_PAD signal and the GEN_K and GEN_R. GEN_PAD can be asserted
-- at the same time as TX_DATA_VALID. This will override TX_DATA and replace the
-- lsb user data with a PAD character. The GEN_K and GEN_R inputs are ignored
-- if any other input is asserted.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (gen_scp_r = '1') then
TX_DATA_Buffer(7 downto 0) <= X"FB" after DLY; -- K27.7(SCP)
end if;
if (gen_ecp_r = '1') then
TX_DATA_Buffer(7 downto 0) <= X"FE" after DLY; -- K30.7(ECP)
end if;
if (gen_snf_r = '1') then
TX_DATA_Buffer(7 downto 0) <= fc_nb_r & "0000" after DLY; -- SNF Data
end if;
if ((tx_pe_data_v_r and gen_pad_r) = '1') then
TX_DATA_Buffer(7 downto 0) <= X"9C" after DLY; -- K28.4(PAD)
end if;
if ((tx_pe_data_v_r and not gen_pad_r) = '1') then
TX_DATA_Buffer(7 downto 0) <= tx_pe_data_r(8 to 15) after DLY; -- DATA
end if;
if (gen_cc_r = '1') then
TX_DATA_Buffer(7 downto 0) <= X"F7" after DLY; -- K23.7(CC)
end if;
if ((idle_c(1) and gen_k_r(1)) = '1') then
TX_DATA_Buffer(7 downto 0) <= X"BC" after DLY; -- K28.5(K)
end if;
if ((idle_c(1) and gen_r_r(1)) = '1') then
TX_DATA_Buffer(7 downto 0) <= X"1C" after DLY; -- K28.0(R)
end if;
if (gen_sp_data_r(1) = '1') then
TX_DATA_Buffer(7 downto 0) <= X"4A" after DLY; -- D10.2(SP data)
end if;
if (gen_spa_data_r(1) = '1') then
TX_DATA_Buffer(7 downto 0) <= X"2C" after DLY; -- D12.1(SPA data)
end if;
if (gen_v_r(1) = '1') then
TX_DATA_Buffer(7 downto 0) <= X"E8" after DLY; -- D8.7(Ver data)
end if;
end if;
end process;
-- Generate control signal for LSB.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
TX_CHAR_IS_K_Buffer(0) <= not ((tx_pe_data_v_r and not gen_pad_r) or
gen_snf_r or
gen_sp_data_r(1) or
gen_spa_data_r(1) or
gen_v_r(1)) after DLY;
end if;
end process;
end RTL;
| bsd-2-clause | 9328bab09c940d6fbb79a5f29cb71e7d | 0.486108 | 3.709047 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/cmdfifo/simulation/cmdfifo_dverif.vhd | 3 | 5,496 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF cmdfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| bsd-2-clause | d166fd6a45404cbe6eb7a3d2c3fbaffd | 0.575328 | 4.129226 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/axi_reg_slice.vhd | 9 | 17,112 | `protect begin_protected
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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uQuNZxad074P2Hys1lo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10928)
`protect data_block
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`protect end_protected
| gpl-3.0 | 0c20a000946e94154bc9a52fb1eb78da | 0.938055 | 1.854959 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/user_io_board_controller_plbw_v1_01_a/hdl/vhdl/dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8.vhd | 4 | 5,975 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8.vhd when simulating
-- the core, dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8 IS
port (
addra: IN std_logic_VECTOR(7 downto 0);
addrb: IN std_logic_VECTOR(7 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(31 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(31 downto 0);
ena: IN std_logic;
enb: IN std_logic;
wea: IN std_logic;
web: IN std_logic);
END dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8;
ARCHITECTURE dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8_a OF dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8 IS
-- synthesis translate_off
component wrapped_dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8
port (
addra: IN std_logic_VECTOR(7 downto 0);
addrb: IN std_logic_VECTOR(7 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(31 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(31 downto 0);
ena: IN std_logic;
enb: IN std_logic;
wea: IN std_logic;
web: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8 use entity XilinxCoreLib.blkmemdp_v6_3(behavioral)
generic map(
c_reg_inputsb => 0,
c_reg_inputsa => 0,
c_has_ndb => 0,
c_has_nda => 0,
c_ytop_addr => "1024",
c_has_rfdb => 0,
c_has_rfda => 0,
c_ywea_is_high => 1,
c_yena_is_high => 1,
c_yclka_is_rising => 1,
c_yhierarchy => "hierarchy1",
c_ysinita_is_high => 1,
c_ybottom_addr => "0",
c_width_b => 32,
c_width_a => 32,
c_sinita_value => "0",
c_sinitb_value => "0",
c_limit_data_pitch => 18,
c_write_modeb => 0,
c_write_modea => 0,
c_has_rdyb => 0,
c_yuse_single_primitive => 0,
c_has_rdya => 0,
c_addra_width => 8,
c_addrb_width => 8,
c_has_limit_data_pitch => 0,
c_default_data => "0",
c_pipe_stages_b => 0,
c_yweb_is_high => 1,
c_yenb_is_high => 1,
c_pipe_stages_a => 0,
c_yclkb_is_rising => 1,
c_yydisable_warnings => 1,
c_enable_rlocs => 0,
c_ysinitb_is_high => 1,
c_has_web => 1,
c_has_default_data => 0,
c_has_sinitb => 0,
c_has_wea => 1,
c_has_sinita => 0,
c_has_dinb => 1,
c_has_dina => 1,
c_ymake_bmm => 0,
c_sim_collision_check => "NONE",
c_has_enb => 1,
c_has_ena => 1,
c_mem_init_file => "dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8.mif",
c_depth_b => 256,
c_depth_a => 256,
c_has_doutb => 1,
c_has_douta => 1,
c_yprimitive_type => "16kx1");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8
port map (
addra => addra,
addrb => addrb,
clka => clka,
clkb => clkb,
dina => dina,
dinb => dinb,
douta => douta,
doutb => doutb,
ena => ena,
enb => enb,
wea => wea,
web => web);
-- synthesis translate_on
END dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8_a;
| bsd-2-clause | 4156b041d577942c1271437c507682a7 | 0.583598 | 3.263244 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/image_selector_fifo/simulation/image_selector_fifo_tb.vhd | 3 | 6,442 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.image_selector_fifo_pkg.ALL;
ENTITY image_selector_fifo_tb IS
END ENTITY;
ARCHITECTURE image_selector_fifo_arch OF image_selector_fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from image_selector_fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of image_selector_fifo_synth
image_selector_fifo_synth_inst:image_selector_fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 28
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| bsd-2-clause | 3818127e69a53fc3cf0ca9cec936655b | 0.615647 | 4.142765 | false | false | false | false |
ymei/TMSPlane | Firmware/test_bench/i2c/i2c_master_tb.vhd | 1 | 5,116 | -------------------------------------------------------------------------------
-- Title : I2C Master Testbench
-- Project : MIMOSA readout
-------------------------------------------------------------------------------
-- File : i2c_master_tb.vhd
-- Author : Dong Wang
-- Company : CCNU, LBNL
-- Created : 2016-11-30
-- Last update:
-- Platform : Linux, Xilinx Vivado 2015.4.2
-- Target : KC705
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: I2C master testbench
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-30 1.0 Dong Wang Created
-- 2017-08-17 Yuan Mei Add extra test cases
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY i2c_master_tb IS
END i2c_master_tb;
ARCHITECTURE behavior OF i2c_master_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT i2c_master
GENERIC (
INPUT_CLK_FREQENCY : integer := 50_000_000;
-- BUS CLK freqency should be divided by multiples of 4 from input frequency
BUS_CLK_FREQUENCY : integer := 50_000
);
PORT (
CLK : IN std_logic; -- system clock 50Mhz
RESET : IN std_logic; -- active high reset
START : IN std_logic; -- the rising edge trigger a start, generate by config_reg
MODE : IN std_logic_vector(1 DOWNTO 0); -- "00" : 1 bytes read or write, "01" : 2 bytes r/w, "10" : 3 bytes write only;
SL_RW : IN std_logic; -- '0' is write, '1' is read
SL_ADDR : IN std_logic_vector(6 DOWNTO 0); -- slave addr
REG_ADDR : IN std_logic_vector(7 DOWNTO 0); -- chip internal addr for read and write
WR_DATA0 : IN std_logic_vector(7 DOWNTO 0); -- first data byte to write
WR_DATA1 : IN std_logic_vector(7 DOWNTO 0); -- second data byte to write
RD_DATA0 : OUT std_logic_vector(7 DOWNTO 0); -- first byte readout
RD_DATA1 : OUT std_logic_vector(7 DOWNTO 0); -- second byte readout
ACK_ERROR : OUT std_logic; -- i2c has unexpected ack
BUSY : OUT std_logic; -- indicates transaction in progress
SDA_in : IN std_logic; -- serial data input of i2c bus
SDA_out : OUT std_logic; -- serial data output of i2c bus
SDA_T : OUT std_logic; -- serial data direction of i2c bus
SCL : OUT std_logic -- serial clock output of i2c bus
);
END COMPONENT;
--Inputs
SIGNAL CLK : std_logic := '0';
SIGNAL RESET : std_logic := '0';
SIGNAL START : std_logic := '0';
SIGNAL MODE : std_logic_vector(1 DOWNTO 0) := "00";
SIGNAL SL_RW : std_logic := '0';
SIGNAL SL_ADDR : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL REG_ADDR : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL WR_DATA0 : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL WR_DATA1 : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL SDA_in : std_logic := '0';
--Outputs
SIGNAL ACK_ERROR : std_logic;
SIGNAL BUSY : std_logic;
SIGNAL SDA_out : std_logic;
SIGNAL SDA_T : std_logic;
SIGNAL SCL : std_logic;
SIGNAL RD_DATA0 : std_logic_vector(7 DOWNTO 0);
SIGNAL RD_DATA1 : std_logic_vector(7 DOWNTO 0);
-- Clock period definitions
CONSTANT CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : i2c_master
GENERIC MAP (
INPUT_CLK_FREQENCY => 50_000_000,
BUS_CLK_FREQUENCY => 100_000
)
PORT MAP (
CLK => CLK,
RESET => RESET,
START => START,
MODE => MODE,
SL_RW => SL_RW,
SL_ADDR => SL_ADDR,
REG_ADDR => REG_ADDR,
WR_DATA0 => WR_DATA0,
WR_DATA1 => WR_DATA1,
RD_DATA0 => RD_DATA0,
RD_DATA1 => RD_DATA1,
BUSY => BUSY,
ACK_ERROR => ACK_ERROR,
SDA_in => SDA_in,
SDA_out => SDA_out,
SDA_T => SDA_T,
SCL => SCL
);
-- Clock process definitions
CLK_process : PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_period/2;
CLK <= '1';
WAIT FOR CLK_period/2;
END PROCESS;
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- initial values:
SL_ADDR <= "0100010";
REG_ADDR <= "10000010";
WR_DATA0 <= x"ab";
WR_DATA1 <= x"31";
START <= '0';
MODE <= "10";
SL_RW <= '0';
SDA_in <= '1';
-- hold reset state for 100 ns.
WAIT FOR 1000 ns;
RESET <= '1';
WAIT FOR 100 ns;
RESET <= '0';
-- stimulate START
WAIT FOR CLK_period * 10;
START <= '1';
WAIT FOR CLK_period * 2;
START <= '0';
WAIT;
END PROCESS;
END;
| bsd-3-clause | f3b29a3ca18b8c3656f95f7f187b03e9 | 0.498045 | 3.643875 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/bytefifoFPGA/simulation/bytefifoFPGA_synth.vhd | 3 | 11,634 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifoFPGA_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.bytefifoFPGA_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bytefifoFPGA_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF bytefifoFPGA_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL overflow : STD_LOGIC;
SIGNAL underflow : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: bytefifoFPGA_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: bytefifoFPGA_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: bytefifoFPGA_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 15,
C_RD_PNTR_WIDTH => 15,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
bytefifoFPGA_inst : bytefifoFPGA_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
OVERFLOW => overflow,
UNDERFLOW => underflow,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-2-clause | 9d1dd1f95d53258fbbe1aa1d8ad9697d | 0.456421 | 4.053659 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/usb/raw_uvc.vhd | 3 | 8,175 | -- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity raw_uvc is
port (
-- raw signals
raw_en : in std_logic;
raw_bytes : in std_logic_vector(23 downto 0);
raw_fifo_full : out std_logic;
error : out std_logic;
raw_clk : in std_logic;
raw_enable : in std_logic;
-- USB signals
slwr : out std_logic;
pktend : out std_logic;
fdata : out std_logic_vector(7 downto 0);
flag_full : in std_logic;
ifclk : in std_logic;
faddr : in std_logic_vector(1 downto 0);
uvcin : in std_logic_vector(1 downto 0);
header : in std_logic;
to_send : in std_logic_vector(23 downto 0);
-- others
uvc_in_free : out std_logic;
uvc_rst : in std_logic
);
end entity raw_uvc;
architecture rtl of raw_uvc is
COMPONENT rawUVCfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
signal fid : std_logic;
signal eof : std_logic;
signal total_send: std_logic_vector(23 downto 0);
signal dout: std_logic_vector(23 downto 0);
signal wrightcount: std_logic_vector(11 downto 0);
signal watchdog: std_logic_vector(5 downto 0);
signal count: std_logic_vector(1 downto 0);
signal raw_en_i : std_logic;
signal full,empty,almost_empty,valid,rd_en : std_logic;
type states is (wait_for_uvc,uvc_wait,uvc_in_pktend,uvc_send_data,s_reset,free_uvc,s_skip);
signal ps : states;
begin
syncProc: process(uvc_rst,ifclk)
begin
if uvc_rst = '1' then
slwr <= '1';
pktend <= '1';
rd_en <= '0';
fid <= '0';
uvc_in_free <= '1';
wrightcount <= (others => '0');
watchdog <= (others => '0');
ps <= s_reset;
eof <= '0';
elsif falling_edge(ifclk) then
slwr <= '1';
pktend <= '1';
rd_en <= '0';
case ps is
when s_reset =>
slwr <= '1';
pktend <= '1';
rd_en <= '0';
fid <= '0';
uvc_in_free <= '1';
ps <= wait_for_uvc;
fdata <= (others => '0');
watchdog <= (others => '0');
wrightcount <= (others => '0');
total_send <= (others => '0');
count <= (others => '0');
when wait_for_uvc =>
if faddr = uvcin and raw_enable = '1' then
ps <= uvc_wait;
uvc_in_free <= '0';
end if;
when uvc_send_data =>
if empty = '0' and flag_full = '1' then
wrightcount <= wrightcount +1;
if header = '1' then
if wrightcount = X"400" then
ps <= uvc_wait;
wrightcount <= (others => '0');
elsif wrightcount = X"000" then
slwr <= '0';
fdata <= X"0C"; -- header length
elsif wrightcount = X"001" then
slwr <= '0';
fdata <= ( "100000" & eof & fid ); -- EOH ERR STI RES SCR PTS EOF FID
eof <= '0';
elsif wrightcount = X"002" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"003" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"004" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"005" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"006" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"007" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"008" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"009" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"00A" then
slwr <= '0';
fdata <= X"00";
elsif wrightcount = X"00B" then
slwr <= '0';
fdata <= X"00";
else -- header sent
total_send <= total_send + 1;
if total_send = to_send then
fid <= not fid;
ps <= uvc_in_pktend;
wrightcount <= (others => '0');
total_send <= (others => '0');
else
slwr <= '0';
count <= count+1;
if count = "00" then
fdata <= dout(7 downto 0);
elsif count = "01" then
fdata <= dout(15 downto 8);
rd_en <= '1';
elsif count = "10" then
fdata <= dout(7 downto 0);
else
fdata <= dout(23 downto 16);
rd_en <= '1';
end if;
end if; -- to_send
if (total_send = to_send - 1012) then
eof <= '1';
end if;
end if;
else -- if header not send
if wrightcount = X"400" then
ps <= uvc_wait;
wrightcount <= (others => '0');
else
total_send <= total_send + 1;
if total_send = to_send then
fid <= not fid;
ps <= uvc_in_pktend;
wrightcount <= (others => '0');
total_send <= (others => '0');
else
slwr <= '0';
count <= count+1;
if count = "00" then
fdata <= dout(7 downto 0);
elsif count = "01" then
fdata <= dout(15 downto 8);
rd_en <= '1';
elsif count = "10" then
fdata <= dout(7 downto 0);
else
fdata <= dout(23 downto 16);
rd_en <= '1';
end if;
end if; -- to_send
end if; -- end if header
end if; -- end if empty
-- else
-- ps <= uvc_wait;
end if;
when uvc_wait =>
watchdog <= watchdog + 1;
if empty = '0' and flag_full = '1' then
ps <= uvc_send_data;
watchdog <= (others => '0');
elsif watchdog(watchdog'range) = (watchdog'range => '1') then
ps <= free_uvc;
watchdog <= (others => '0');
end if;
when uvc_in_pktend =>
pktend <= '0';
ps <= free_uvc;
when free_uvc =>
uvc_in_free <= '1';
ps <= s_skip;
when s_skip =>
ps <= wait_for_uvc;
when others =>
ps <= s_reset;
end case;
end if;
end process;
raw_en_i <= (raw_en and raw_enable);
rawUVCfifo_Comp : rawUVCfifo
PORT MAP (
rst => uvc_rst,
wr_clk => raw_clk,
rd_clk => ifclk,
din => raw_bytes,
wr_en => raw_en_i,
rd_en => rd_en,
dout => dout,
full => full,
-- almost_full => raw_fifo_full,
prog_full => raw_fifo_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
end rtl; | bsd-2-clause | 74471218ead745df68c9e257f5311d19 | 0.543731 | 3.102467 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/warp_timer_plbw_v1_00_a/hdl/vhdl/warp_timer.vhd | 4 | 209,538 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e IS
port (
A: IN std_logic_VECTOR(32 downto 0);
B: IN std_logic_VECTOR(32 downto 0);
S: OUT std_logic_VECTOR(32 downto 0));
END adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e;
ARCHITECTURE adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e_a OF adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e
port (
A: IN std_logic_VECTOR(32 downto 0);
B: IN std_logic_VECTOR(32 downto 0);
S: OUT std_logic_VECTOR(32 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 0,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 32,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 0,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 1,
c_has_aclr => 0,
c_out_width => 33,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 33,
c_a_width => 33,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_b57302a6bcbb6876.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_b57302a6bcbb6876. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_b57302a6bcbb6876 IS
port (
Q: OUT std_logic_VECTOR(31 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_b57302a6bcbb6876;
ARCHITECTURE binary_counter_virtex2p_7_0_b57302a6bcbb6876_a OF binary_counter_virtex2p_7_0_b57302a6bcbb6876 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876
port (
Q: OUT std_logic_VECTOR(31 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 32,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_b57302a6bcbb6876_a;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
package clock_pkg is
-- synopsys translate_off
signal int_clk : std_logic;
-- synopsys translate_on
end clock_pkg;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_b389f41afb is
port (
plbrst : in std_logic_vector((1 - 1) downto 0);
plbabus : in std_logic_vector((32 - 1) downto 0);
plbpavalid : in std_logic_vector((1 - 1) downto 0);
plbrnw : in std_logic_vector((1 - 1) downto 0);
plbwrdbus : in std_logic_vector((32 - 1) downto 0);
rddata : in std_logic_vector((32 - 1) downto 0);
addrpref : in std_logic_vector((20 - 1) downto 0);
wrdbusreg : out std_logic_vector((32 - 1) downto 0);
addrack : out std_logic_vector((1 - 1) downto 0);
rdcomp : out std_logic_vector((1 - 1) downto 0);
wrdack : out std_logic_vector((1 - 1) downto 0);
bankaddr : out std_logic_vector((2 - 1) downto 0);
rnwreg : out std_logic_vector((1 - 1) downto 0);
rddack : out std_logic_vector((1 - 1) downto 0);
rddbus : out std_logic_vector((32 - 1) downto 0);
linearaddr : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_b389f41afb;
architecture behavior of mcode_block_b389f41afb is
signal plbrst_2_20: unsigned((1 - 1) downto 0);
signal plbabus_2_28: unsigned((32 - 1) downto 0);
signal plbpavalid_2_37: unsigned((1 - 1) downto 0);
signal plbrnw_2_49: unsigned((1 - 1) downto 0);
signal plbwrdbus_2_57: unsigned((32 - 1) downto 0);
signal rddata_2_68: unsigned((32 - 1) downto 0);
signal addrpref_2_76: unsigned((20 - 1) downto 0);
signal plbrstreg_13_24_next: boolean;
signal plbrstreg_13_24: boolean := false;
signal plbabusreg_14_25_next: unsigned((32 - 1) downto 0);
signal plbabusreg_14_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal plbpavalidreg_15_28_next: boolean;
signal plbpavalidreg_15_28: boolean := false;
signal plbrnwreg_16_24_next: unsigned((1 - 1) downto 0);
signal plbrnwreg_16_24: unsigned((1 - 1) downto 0) := "0";
signal plbwrdbusreg_17_27_next: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_17_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal avalidreg_29_23_next: boolean;
signal avalidreg_29_23: boolean := false;
signal ps1reg_40_20_next: boolean;
signal ps1reg_40_20: boolean := false;
signal psreg_48_19_next: boolean;
signal psreg_48_19: boolean := false;
type array_type_rdcompdelay_59_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25: array_type_rdcompdelay_59_25 := (
"0",
"0",
"0");
signal rdcompdelay_59_25_front_din: unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25_back: unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25_push_front_pop_back_en: std_logic;
signal rdcompreg_63_23_next: unsigned((1 - 1) downto 0);
signal rdcompreg_63_23: unsigned((1 - 1) downto 0) := "0";
signal rddackreg_67_23_next: unsigned((1 - 1) downto 0);
signal rddackreg_67_23: unsigned((1 - 1) downto 0) := "0";
signal wrdackreg_71_23_next: unsigned((1 - 1) downto 0);
signal wrdackreg_71_23: unsigned((1 - 1) downto 0) := "0";
signal rddbusreg_85_23_next: unsigned((32 - 1) downto 0);
signal rddbusreg_85_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_21_1_slice: unsigned((2 - 1) downto 0);
signal linearaddr_22_1_slice: unsigned((8 - 1) downto 0);
signal addrpref_in_33_1_slice: unsigned((20 - 1) downto 0);
signal rel_34_4: boolean;
signal ps1_join_34_1: boolean;
signal ps_43_1_bit: boolean;
signal bitnot_50_49: boolean;
signal bitnot_50_73: boolean;
signal bit_50_49: boolean;
signal addrack_50_1_convert: unsigned((1 - 1) downto 0);
signal bit_56_43: unsigned((1 - 1) downto 0);
signal bitnot_73_35: unsigned((1 - 1) downto 0);
signal wrdackreg_73_1_bit: unsigned((1 - 1) downto 0);
signal rdsel_77_1_bit: unsigned((1 - 1) downto 0);
signal rel_79_4: boolean;
signal rddbus1_join_79_1: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_98_1_slice: unsigned((32 - 1) downto 0);
signal plbrstreg_13_24_next_x_000000: boolean;
signal plbpavalidreg_15_28_next_x_000000: boolean;
begin
plbrst_2_20 <= std_logic_vector_to_unsigned(plbrst);
plbabus_2_28 <= std_logic_vector_to_unsigned(plbabus);
plbpavalid_2_37 <= std_logic_vector_to_unsigned(plbpavalid);
plbrnw_2_49 <= std_logic_vector_to_unsigned(plbrnw);
plbwrdbus_2_57 <= std_logic_vector_to_unsigned(plbwrdbus);
rddata_2_68 <= std_logic_vector_to_unsigned(rddata);
addrpref_2_76 <= std_logic_vector_to_unsigned(addrpref);
proc_plbrstreg_13_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrstreg_13_24 <= plbrstreg_13_24_next;
end if;
end if;
end process proc_plbrstreg_13_24;
proc_plbabusreg_14_25: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbabusreg_14_25 <= plbabusreg_14_25_next;
end if;
end if;
end process proc_plbabusreg_14_25;
proc_plbpavalidreg_15_28: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbpavalidreg_15_28 <= plbpavalidreg_15_28_next;
end if;
end if;
end process proc_plbpavalidreg_15_28;
proc_plbrnwreg_16_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrnwreg_16_24 <= plbrnwreg_16_24_next;
end if;
end if;
end process proc_plbrnwreg_16_24;
proc_plbwrdbusreg_17_27: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbwrdbusreg_17_27 <= plbwrdbusreg_17_27_next;
end if;
end if;
end process proc_plbwrdbusreg_17_27;
proc_avalidreg_29_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
avalidreg_29_23 <= avalidreg_29_23_next;
end if;
end if;
end process proc_avalidreg_29_23;
proc_ps1reg_40_20: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ps1reg_40_20 <= ps1reg_40_20_next;
end if;
end if;
end process proc_ps1reg_40_20;
proc_psreg_48_19: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
psreg_48_19 <= psreg_48_19_next;
end if;
end if;
end process proc_psreg_48_19;
rdcompdelay_59_25_back <= rdcompdelay_59_25(2);
proc_rdcompdelay_59_25: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (rdcompdelay_59_25_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
rdcompdelay_59_25(i) <= rdcompdelay_59_25(i-1);
end loop;
rdcompdelay_59_25(0) <= rdcompdelay_59_25_front_din;
end if;
end if;
end process proc_rdcompdelay_59_25;
proc_rdcompreg_63_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rdcompreg_63_23 <= rdcompreg_63_23_next;
end if;
end if;
end process proc_rdcompreg_63_23;
proc_rddackreg_67_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddackreg_67_23 <= rddackreg_67_23_next;
end if;
end if;
end process proc_rddackreg_67_23;
proc_wrdackreg_71_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
wrdackreg_71_23 <= wrdackreg_71_23_next;
end if;
end if;
end process proc_wrdackreg_71_23;
proc_rddbusreg_85_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddbusreg_85_23 <= rddbusreg_85_23_next;
end if;
end if;
end process proc_rddbusreg_85_23;
bankaddr_21_1_slice <= u2u_slice(plbabusreg_14_25, 11, 10);
linearaddr_22_1_slice <= u2u_slice(plbabusreg_14_25, 9, 2);
addrpref_in_33_1_slice <= u2u_slice(plbabusreg_14_25, 31, 12);
rel_34_4 <= addrpref_in_33_1_slice = addrpref_2_76;
proc_if_34_1: process (rel_34_4)
is
begin
if rel_34_4 then
ps1_join_34_1 <= true;
else
ps1_join_34_1 <= false;
end if;
end process proc_if_34_1;
ps_43_1_bit <= ((boolean_to_vector(ps1_join_34_1) and boolean_to_vector(plbpavalidreg_15_28)) = "1");
bitnot_50_49 <= ((not boolean_to_vector(plbrstreg_13_24)) = "1");
bitnot_50_73 <= ((not boolean_to_vector(psreg_48_19)) = "1");
bit_50_49 <= ((boolean_to_vector(bitnot_50_49) and boolean_to_vector(ps_43_1_bit) and boolean_to_vector(bitnot_50_73)) = "1");
addrack_50_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_50_49)), 0, 1, 0);
bit_56_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_16_24));
bitnot_73_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_16_24));
wrdackreg_73_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(bitnot_73_35));
rdsel_77_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_59_25_back) or unsigned_to_std_logic_vector(rdcompreg_63_23));
rel_79_4 <= rdsel_77_1_bit = std_logic_vector_to_unsigned("1");
proc_if_79_1: process (rddata_2_68, rel_79_4)
is
begin
if rel_79_4 then
rddbus1_join_79_1 <= rddata_2_68;
else
rddbus1_join_79_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
end if;
end process proc_if_79_1;
plbwrdbusreg_98_1_slice <= u2u_slice(plbwrdbus_2_57, 31, 0);
plbrstreg_13_24_next_x_000000 <= (plbrst_2_20 /= "0");
plbrstreg_13_24_next <= plbrstreg_13_24_next_x_000000;
plbabusreg_14_25_next <= plbabus_2_28;
plbpavalidreg_15_28_next_x_000000 <= (plbpavalid_2_37 /= "0");
plbpavalidreg_15_28_next <= plbpavalidreg_15_28_next_x_000000;
plbrnwreg_16_24_next <= plbrnw_2_49;
plbwrdbusreg_17_27_next <= plbwrdbusreg_98_1_slice;
avalidreg_29_23_next <= plbpavalidreg_15_28;
ps1reg_40_20_next <= ps1_join_34_1;
psreg_48_19_next <= ps_43_1_bit;
rdcompdelay_59_25_front_din <= bit_56_43;
rdcompdelay_59_25_push_front_pop_back_en <= '1';
rdcompreg_63_23_next <= rdcompdelay_59_25_back;
rddackreg_67_23_next <= rdcompreg_63_23;
wrdackreg_71_23_next <= wrdackreg_73_1_bit;
rddbusreg_85_23_next <= rddbus1_join_79_1;
wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_17_27);
addrack <= unsigned_to_std_logic_vector(addrack_50_1_convert);
rdcomp <= unsigned_to_std_logic_vector(rdcompreg_63_23);
wrdack <= unsigned_to_std_logic_vector(wrdackreg_71_23);
bankaddr <= unsigned_to_std_logic_vector(bankaddr_21_1_slice);
rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_16_24);
rddack <= unsigned_to_std_logic_vector(rddackreg_67_23);
rddbus <= unsigned_to_std_logic_vector(rddbusreg_85_23);
linearaddr <= unsigned_to_std_logic_vector(linearaddr_22_1_slice);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_b59e0d51fc is
port (
wrdbus : in std_logic_vector((32 - 1) downto 0);
bankaddr : in std_logic_vector((2 - 1) downto 0);
linearaddr : in std_logic_vector((8 - 1) downto 0);
rnwreg : in std_logic_vector((1 - 1) downto 0);
addrack : in std_logic_vector((1 - 1) downto 0);
sm_timer0_timeleft : in std_logic_vector((32 - 1) downto 0);
sm_timer1_timeleft : in std_logic_vector((32 - 1) downto 0);
sm_timer2_timeleft : in std_logic_vector((32 - 1) downto 0);
sm_timer3_timeleft : in std_logic_vector((32 - 1) downto 0);
sm_timer_control_r : in std_logic_vector((32 - 1) downto 0);
sm_timer_status : in std_logic_vector((32 - 1) downto 0);
sm_timer0_countto : in std_logic_vector((32 - 1) downto 0);
sm_timer1_countto : in std_logic_vector((32 - 1) downto 0);
sm_timer2_countto : in std_logic_vector((32 - 1) downto 0);
sm_timer3_countto : in std_logic_vector((32 - 1) downto 0);
sm_timer_control_w : in std_logic_vector((32 - 1) downto 0);
read_bank_out : out std_logic_vector((32 - 1) downto 0);
sm_timer0_countto_din : out std_logic_vector((32 - 1) downto 0);
sm_timer0_countto_en : out std_logic_vector((1 - 1) downto 0);
sm_timer1_countto_din : out std_logic_vector((32 - 1) downto 0);
sm_timer1_countto_en : out std_logic_vector((1 - 1) downto 0);
sm_timer2_countto_din : out std_logic_vector((32 - 1) downto 0);
sm_timer2_countto_en : out std_logic_vector((1 - 1) downto 0);
sm_timer3_countto_din : out std_logic_vector((32 - 1) downto 0);
sm_timer3_countto_en : out std_logic_vector((1 - 1) downto 0);
sm_timer_control_w_din : out std_logic_vector((32 - 1) downto 0);
sm_timer_control_w_en : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_b59e0d51fc;
architecture behavior of mcode_block_b59e0d51fc is
signal wrdbus_1_273: unsigned((32 - 1) downto 0);
signal bankaddr_1_281: unsigned((2 - 1) downto 0);
signal linearaddr_1_291: unsigned((8 - 1) downto 0);
signal rnwreg_1_303: unsigned((1 - 1) downto 0);
signal addrack_1_311: unsigned((1 - 1) downto 0);
signal sm_timer0_timeleft_1_320: unsigned((32 - 1) downto 0);
signal sm_timer1_timeleft_1_340: unsigned((32 - 1) downto 0);
signal sm_timer2_timeleft_1_360: unsigned((32 - 1) downto 0);
signal sm_timer3_timeleft_1_380: unsigned((32 - 1) downto 0);
signal sm_timer_control_r_1_400: unsigned((32 - 1) downto 0);
signal sm_timer_status_1_420: unsigned((32 - 1) downto 0);
signal sm_timer0_countto_1_437: unsigned((32 - 1) downto 0);
signal sm_timer1_countto_1_456: unsigned((32 - 1) downto 0);
signal sm_timer2_countto_1_475: unsigned((32 - 1) downto 0);
signal sm_timer3_countto_1_494: unsigned((32 - 1) downto 0);
signal sm_timer_control_w_1_513: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_47_30_next: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_47_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal read_bank_out_reg_158_31_next: unsigned((32 - 1) downto 0);
signal read_bank_out_reg_158_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_reg_161_26_next: unsigned((2 - 1) downto 0);
signal bankaddr_reg_161_26: unsigned((2 - 1) downto 0) := "00";
signal rel_50_4: boolean;
signal rel_52_8: boolean;
signal rel_54_8: boolean;
signal rel_56_8: boolean;
signal rel_58_8: boolean;
signal rel_60_8: boolean;
signal rel_62_8: boolean;
signal rel_64_8: boolean;
signal rel_66_8: boolean;
signal rel_68_8: boolean;
signal rel_70_8: boolean;
signal reg_bank_out_reg_join_50_1: unsigned((32 - 1) downto 0);
signal opcode_81_1_concat: unsigned((12 - 1) downto 0);
signal rel_102_4: boolean;
signal sm_timer0_countto_en_join_102_1: boolean;
signal rel_108_4: boolean;
signal sm_timer1_countto_en_join_108_1: boolean;
signal rel_114_4: boolean;
signal sm_timer2_countto_en_join_114_1: boolean;
signal rel_120_4: boolean;
signal sm_timer3_countto_en_join_120_1: boolean;
signal rel_126_4: boolean;
signal sm_timer_control_w_en_join_126_1: boolean;
signal slice_141_42: unsigned((32 - 1) downto 0);
signal slice_144_42: unsigned((32 - 1) downto 0);
signal slice_147_42: unsigned((32 - 1) downto 0);
signal slice_150_42: unsigned((32 - 1) downto 0);
signal slice_153_43: unsigned((32 - 1) downto 0);
signal rel_163_4: boolean;
signal rel_166_8: boolean;
signal rel_169_8: boolean;
signal rel_172_8: boolean;
signal read_bank_out_reg_join_163_1: unsigned((32 - 1) downto 0);
begin
wrdbus_1_273 <= std_logic_vector_to_unsigned(wrdbus);
bankaddr_1_281 <= std_logic_vector_to_unsigned(bankaddr);
linearaddr_1_291 <= std_logic_vector_to_unsigned(linearaddr);
rnwreg_1_303 <= std_logic_vector_to_unsigned(rnwreg);
addrack_1_311 <= std_logic_vector_to_unsigned(addrack);
sm_timer0_timeleft_1_320 <= std_logic_vector_to_unsigned(sm_timer0_timeleft);
sm_timer1_timeleft_1_340 <= std_logic_vector_to_unsigned(sm_timer1_timeleft);
sm_timer2_timeleft_1_360 <= std_logic_vector_to_unsigned(sm_timer2_timeleft);
sm_timer3_timeleft_1_380 <= std_logic_vector_to_unsigned(sm_timer3_timeleft);
sm_timer_control_r_1_400 <= std_logic_vector_to_unsigned(sm_timer_control_r);
sm_timer_status_1_420 <= std_logic_vector_to_unsigned(sm_timer_status);
sm_timer0_countto_1_437 <= std_logic_vector_to_unsigned(sm_timer0_countto);
sm_timer1_countto_1_456 <= std_logic_vector_to_unsigned(sm_timer1_countto);
sm_timer2_countto_1_475 <= std_logic_vector_to_unsigned(sm_timer2_countto);
sm_timer3_countto_1_494 <= std_logic_vector_to_unsigned(sm_timer3_countto);
sm_timer_control_w_1_513 <= std_logic_vector_to_unsigned(sm_timer_control_w);
proc_reg_bank_out_reg_47_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
reg_bank_out_reg_47_30 <= reg_bank_out_reg_47_30_next;
end if;
end if;
end process proc_reg_bank_out_reg_47_30;
proc_read_bank_out_reg_158_31: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
read_bank_out_reg_158_31 <= read_bank_out_reg_158_31_next;
end if;
end if;
end process proc_read_bank_out_reg_158_31;
proc_bankaddr_reg_161_26: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
bankaddr_reg_161_26 <= bankaddr_reg_161_26_next;
end if;
end if;
end process proc_bankaddr_reg_161_26;
rel_50_4 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000101");
rel_52_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000110");
rel_54_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000111");
rel_56_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001000");
rel_58_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001001");
rel_60_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001010");
rel_62_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000000");
rel_64_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000001");
rel_66_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000010");
rel_68_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000011");
rel_70_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000100");
proc_if_50_1: process (reg_bank_out_reg_47_30, rel_50_4, rel_52_8, rel_54_8, rel_56_8, rel_58_8, rel_60_8, rel_62_8, rel_64_8, rel_66_8, rel_68_8, rel_70_8, sm_timer0_countto_1_437, sm_timer0_timeleft_1_320, sm_timer1_countto_1_456, sm_timer1_timeleft_1_340, sm_timer2_countto_1_475, sm_timer2_timeleft_1_360, sm_timer3_countto_1_494, sm_timer3_timeleft_1_380, sm_timer_control_r_1_400, sm_timer_control_w_1_513, sm_timer_status_1_420)
is
begin
if rel_50_4 then
reg_bank_out_reg_join_50_1 <= sm_timer0_timeleft_1_320;
elsif rel_52_8 then
reg_bank_out_reg_join_50_1 <= sm_timer1_timeleft_1_340;
elsif rel_54_8 then
reg_bank_out_reg_join_50_1 <= sm_timer2_timeleft_1_360;
elsif rel_56_8 then
reg_bank_out_reg_join_50_1 <= sm_timer3_timeleft_1_380;
elsif rel_58_8 then
reg_bank_out_reg_join_50_1 <= sm_timer_control_r_1_400;
elsif rel_60_8 then
reg_bank_out_reg_join_50_1 <= sm_timer_status_1_420;
elsif rel_62_8 then
reg_bank_out_reg_join_50_1 <= sm_timer0_countto_1_437;
elsif rel_64_8 then
reg_bank_out_reg_join_50_1 <= sm_timer1_countto_1_456;
elsif rel_66_8 then
reg_bank_out_reg_join_50_1 <= sm_timer2_countto_1_475;
elsif rel_68_8 then
reg_bank_out_reg_join_50_1 <= sm_timer3_countto_1_494;
elsif rel_70_8 then
reg_bank_out_reg_join_50_1 <= sm_timer_control_w_1_513;
else
reg_bank_out_reg_join_50_1 <= reg_bank_out_reg_47_30;
end if;
end process proc_if_50_1;
opcode_81_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_311) & unsigned_to_std_logic_vector(rnwreg_1_303) & unsigned_to_std_logic_vector(bankaddr_1_281) & unsigned_to_std_logic_vector(linearaddr_1_291));
rel_102_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000000");
proc_if_102_1: process (rel_102_4)
is
begin
if rel_102_4 then
sm_timer0_countto_en_join_102_1 <= true;
else
sm_timer0_countto_en_join_102_1 <= false;
end if;
end process proc_if_102_1;
rel_108_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000001");
proc_if_108_1: process (rel_108_4)
is
begin
if rel_108_4 then
sm_timer1_countto_en_join_108_1 <= true;
else
sm_timer1_countto_en_join_108_1 <= false;
end if;
end process proc_if_108_1;
rel_114_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000010");
proc_if_114_1: process (rel_114_4)
is
begin
if rel_114_4 then
sm_timer2_countto_en_join_114_1 <= true;
else
sm_timer2_countto_en_join_114_1 <= false;
end if;
end process proc_if_114_1;
rel_120_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000011");
proc_if_120_1: process (rel_120_4)
is
begin
if rel_120_4 then
sm_timer3_countto_en_join_120_1 <= true;
else
sm_timer3_countto_en_join_120_1 <= false;
end if;
end process proc_if_120_1;
rel_126_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000100");
proc_if_126_1: process (rel_126_4)
is
begin
if rel_126_4 then
sm_timer_control_w_en_join_126_1 <= true;
else
sm_timer_control_w_en_join_126_1 <= false;
end if;
end process proc_if_126_1;
slice_141_42 <= u2u_slice(wrdbus_1_273, 31, 0);
slice_144_42 <= u2u_slice(wrdbus_1_273, 31, 0);
slice_147_42 <= u2u_slice(wrdbus_1_273, 31, 0);
slice_150_42 <= u2u_slice(wrdbus_1_273, 31, 0);
slice_153_43 <= u2u_slice(wrdbus_1_273, 31, 0);
rel_163_4 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("00");
rel_166_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("01");
rel_169_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("10");
rel_172_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("11");
proc_if_163_1: process (read_bank_out_reg_158_31, reg_bank_out_reg_47_30, rel_163_4, rel_166_8, rel_169_8, rel_172_8)
is
begin
if rel_163_4 then
read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_166_8 then
read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_169_8 then
read_bank_out_reg_join_163_1 <= reg_bank_out_reg_47_30;
elsif rel_172_8 then
read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
else
read_bank_out_reg_join_163_1 <= read_bank_out_reg_158_31;
end if;
end process proc_if_163_1;
reg_bank_out_reg_47_30_next <= reg_bank_out_reg_join_50_1;
read_bank_out_reg_158_31_next <= read_bank_out_reg_join_163_1;
bankaddr_reg_161_26_next <= bankaddr_1_281;
read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_158_31);
sm_timer0_countto_din <= unsigned_to_std_logic_vector(slice_141_42);
sm_timer0_countto_en <= boolean_to_vector(sm_timer0_countto_en_join_102_1);
sm_timer1_countto_din <= unsigned_to_std_logic_vector(slice_144_42);
sm_timer1_countto_en <= boolean_to_vector(sm_timer1_countto_en_join_108_1);
sm_timer2_countto_din <= unsigned_to_std_logic_vector(slice_147_42);
sm_timer2_countto_en <= boolean_to_vector(sm_timer2_countto_en_join_114_1);
sm_timer3_countto_din <= unsigned_to_std_logic_vector(slice_150_42);
sm_timer3_countto_en <= boolean_to_vector(sm_timer3_countto_en_join_120_1);
sm_timer_control_w_din <= unsigned_to_std_logic_vector(slice_153_43);
sm_timer_control_w_en <= boolean_to_vector(sm_timer_control_w_en_join_126_1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e5b38cca3b is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e5b38cca3b;
architecture behavior of inverter_e5b38cca3b is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_push_front_pop_back_en <= '0';
op <= boolean_to_vector(internal_ip_12_1_bitnot);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlregister is
generic (d_width : integer := 5;
init_value : bit_vector := b"00");
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end xlregister;
architecture behavior of xlregister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
-- synopsys translate_off
signal real_d, real_q : real;
-- synopsys translate_on
signal internal_clr : std_logic;
signal internal_ce : std_logic;
begin
internal_clr <= rst(0) and ce;
internal_ce <= en(0) and ce;
synth_reg_inst : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => q);
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xldelay is
generic(width : integer := -1;
latency : integer := -1;
reg_retiming : integer := 0);
port(d : in std_logic_vector (width-1 downto 0);
ce : in std_logic;
clk : in std_logic;
en : in std_logic;
q : out std_logic_vector (width-1 downto 0));
end xldelay;
architecture behavior of xldelay is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component synth_reg_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
signal internal_ce : std_logic;
begin
internal_ce <= ce and en;
srl_delay: if (reg_retiming = 0) or (latency < 1) generate
synth_reg_srl_inst : synth_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate srl_delay;
reg_delay: if (reg_retiming = 1) and (latency >= 1) generate
synth_reg_reg_inst : synth_reg_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate reg_delay;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_80f90b97d0 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_80f90b97d0;
architecture behavior of logical_80f90b97d0 is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 and d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xladdsub is
generic (
core_name0: string := "";
a_width: integer := 16;
a_bin_pt: integer := 4;
a_arith: integer := xlUnsigned;
c_in_width: integer := 16;
c_in_bin_pt: integer := 4;
c_in_arith: integer := xlUnsigned;
c_out_width: integer := 16;
c_out_bin_pt: integer := 4;
c_out_arith: integer := xlUnsigned;
b_width: integer := 8;
b_bin_pt: integer := 2;
b_arith: integer := xlUnsigned;
s_width: integer := 17;
s_bin_pt: integer := 4;
s_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
full_s_width: integer := 17;
full_s_arith: integer := xlUnsigned;
mode: integer := xlAddMode;
extra_registers: integer := 0;
latency: integer := 0;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
c_latency: integer := 0;
c_output_width: integer := 17;
c_has_q : integer := 1;
c_has_s : integer := 0;
c_has_c_out : integer := 0;
c_has_q_c_out : integer := 0;
c_has_b_out : integer := 0;
c_has_q_b_out : integer := 0;
c_has_q_ovfl : integer := 0;
c_has_ovfl : integer := 0
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
c_in : in std_logic_vector (0 downto 0) := "0";
ce: in std_logic;
clr: in std_logic := '0';
clk: in std_logic;
rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
en: in std_logic_vector(en_width - 1 downto 0) := "1";
c_out : out std_logic_vector (0 downto 0);
s: out std_logic_vector(s_width - 1 downto 0)
);
end xladdsub ;
architecture behavior of xladdsub is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function format_input(inp: std_logic_vector; old_width, delta, new_arith,
new_width: integer)
return std_logic_vector
is
variable vec: std_logic_vector(old_width-1 downto 0);
variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0);
variable result: std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
constant full_a_width: integer := full_s_width;
constant full_b_width: integer := full_s_width;
signal full_a: std_logic_vector(full_a_width - 1 downto 0);
signal full_b: std_logic_vector(full_b_width - 1 downto 0);
signal core_s: std_logic_vector(full_s_width - 1 downto 0);
signal conv_s: std_logic_vector(s_width - 1 downto 0);
signal temp_cout : std_logic;
signal internal_clr: std_logic;
signal internal_ce: std_logic;
signal extra_reg_ce: std_logic;
signal override: std_logic;
signal logic1: std_logic_vector(0 downto 0);
component adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e
port (
a: in std_logic_vector( 33 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(33 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e:
component is "black_box";
begin
internal_clr <= (clr or (rst(0))) and ce;
internal_ce <= ce and en(0);
logic1(0) <= '1';
addsub_process: process(a, b, core_s)
begin
full_a <= format_input(a, a_width, b_bin_pt - a_bin_pt, a_arith,
full_a_width);
full_b <= format_input(b, b_width, a_bin_pt - b_bin_pt, b_arith,
full_b_width);
conv_s <= convert_type(core_s, full_s_width, full_s_bin_pt, full_s_arith,
s_width, s_bin_pt, s_arith, quantization, overflow);
end process addsub_process;
comp0: if ((core_name0 = "adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e")) generate
core_instance0: adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
latency_test: if (extra_registers > 0) generate
override_test: if (c_latency > 1) generate
override_pipe: synth_reg
generic map (
width => 1,
latency => c_latency)
port map (
i => logic1,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o(0) => override);
extra_reg_ce <= ce and en(0) and override;
end generate override_test;
no_override: if (c_latency = 0) or (c_latency = 1) generate
extra_reg_ce <= ce and en(0);
end generate no_override;
extra_reg: synth_reg
generic map (
width => s_width,
latency => extra_registers
)
port map (
i => conv_s,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => s
);
cout_test : if((c_has_c_out = 1) or
(c_has_b_out = 1) or
(c_has_q_c_out = 1) or
(c_has_q_b_out = 1)) generate
c_out_extra_reg: synth_reg
generic map (
width => 1,
latency => extra_registers
)
port map (
i(0) => temp_cout,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => c_out
);
end generate cout_test;
end generate;
latency_s: if ((latency = 0) or (extra_registers = 0)) generate
s <= conv_s;
end generate latency_s;
latency0: if ( ((latency = 0) or (extra_registers = 0)) and
((c_has_b_out = 1) or
(c_has_q_c_out = 1) or
(c_has_c_out = 1) or
(c_has_q_b_out = 1))) generate
c_out(0) <= temp_cout;
end generate latency0;
tie_dangling_cout: if ((c_has_c_out = 0) and
(c_has_b_out = 0) and
(c_has_q_c_out = 0) and
(c_has_q_b_out = 0)) generate
c_out <= "0";
end generate tie_dangling_cout;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_6293007044 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_6293007044;
architecture behavior of constant_6293007044 is
begin
op <= "1";
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity convert_func_call is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call;
architecture behavior of convert_func_call is
begin
result <= convert_type(din, din_width, din_bin_pt, din_arith,
dout_width, dout_bin_pt, dout_arith,
quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlconvert is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
bool_conversion : integer :=0;
latency : integer := 0;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector (dout_width-1 downto 0));
end xlconvert;
architecture behavior of xlconvert is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component convert_func_call
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end component;
-- synopsys translate_off
signal real_din, real_dout : real;
-- synopsys translate_on
signal result : std_logic_vector(dout_width-1 downto 0);
begin
-- synopsys translate_off
-- synopsys translate_on
bool_conversion_generate : if (bool_conversion = 1)
generate
result <= din;
end generate;
std_conversion_generate : if (bool_conversion = 0)
generate
convert : convert_func_call
generic map (
din_width => din_width,
din_bin_pt => din_bin_pt,
din_arith => din_arith,
dout_width => dout_width,
dout_bin_pt => dout_bin_pt,
dout_arith => dout_arith,
quantization => quantization,
overflow => overflow)
port map (
din => din,
result => result);
end generate;
latency_test : if (latency > 0)
generate
reg : synth_reg
generic map ( width => dout_width,
latency => latency)
port map (i => result,
ce => ce,
clr => clr,
clk => clk,
o => dout);
end generate;
latency0 : if (latency = 0)
generate
dout <= result;
end generate latency0;
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlcounter_free is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
load: in std_logic_vector(0 downto 0) := (others => '0');
din: in std_logic_vector(op_width - 1 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_free ;
architecture behavior of xlcounter_free is
component binary_counter_virtex2p_7_0_b57302a6bcbb6876
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_b57302a6bcbb6876:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_b57302a6bcbb6876:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_b57302a6bcbb6876:
component is "black_box";
-- synopsys translate_off
constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
signal core_sinit: std_logic;
signal core_ce: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
begin
core_ce <= ce and en(0);
core_sinit <= (clr or rst(0)) and ce;
op <= op_net;
comp0: if ((core_name0 = "binary_counter_virtex2p_7_0_b57302a6bcbb6876")) generate
core_instance0: binary_counter_virtex2p_7_0_b57302a6bcbb6876
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_6cb8f0ce02 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_6cb8f0ce02;
architecture behavior of logical_6cb8f0ce02 is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal d2_1_30: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
d2_1_30 <= d2(0);
fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_aacf6e1b0e is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_aacf6e1b0e;
architecture behavior of logical_aacf6e1b0e is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 or d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_112ed141f4 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_112ed141f4;
architecture behavior of mux_112ed141f4 is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0);
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0;
d1_1_27 <= d1;
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_3ffd1d0a40 is
port (
a : in std_logic_vector((32 - 1) downto 0);
b : in std_logic_vector((32 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_3ffd1d0a40;
architecture behavior of relational_3ffd1d0a40 is
signal a_1_31: unsigned((32 - 1) downto 0);
signal b_1_34: unsigned((32 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
result_12_3_rel <= a_1_31 = b_1_34;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_34fc311f5b is
port (
a : in std_logic_vector((32 - 1) downto 0);
b : in std_logic_vector((32 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_34fc311f5b;
architecture behavior of relational_34fc311f5b is
signal a_1_31: unsigned((32 - 1) downto 0);
signal b_1_34: unsigned((32 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_18_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_18_3_rel <= a_1_31 > b_1_34;
op_mem_32_22_front_din <= result_18_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_37567836aa is
port (
op : out std_logic_vector((32 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_37567836aa;
architecture behavior of constant_37567836aa is
begin
op <= "00000000000000000000000000000000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_a1e126f11c is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
in2 : in std_logic_vector((8 - 1) downto 0);
in3 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((32 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_a1e126f11c;
architecture behavior of concat_a1e126f11c is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal in2_1_31: unsigned((8 - 1) downto 0);
signal in3_1_35: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((32 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
in3_1_35 <= std_logic_vector_to_unsigned(in3);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_09e13b86e0 is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
in2 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_09e13b86e0;
architecture behavior of concat_09e13b86e0 is
signal in0_1_23: boolean;
signal in1_1_27: boolean;
signal in2_1_31: boolean;
signal y_2_1_concat: unsigned((3 - 1) downto 0);
begin
in0_1_23 <= ((in0) = "1");
in1_1_27 <= ((in1) = "1");
in2_1_31 <= ((in2) = "1");
y_2_1_concat <= std_logic_vector_to_unsigned(boolean_to_vector(in0_1_23) & boolean_to_vector(in1_1_27) & boolean_to_vector(in2_1_31));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_a6d07705dd is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
d3 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_a6d07705dd;
architecture behavior of logical_a6d07705dd is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal d2_1_30: std_logic;
signal d3_1_33: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
d2_1_30 <= d2(0);
d3_1_33 <= d3(0);
fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30 or d3_1_33;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer/EDK Processor"
entity edk_processor_entity_cddda35d8e is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(31 downto 0);
from_register1: in std_logic_vector(31 downto 0);
from_register2: in std_logic_vector(31 downto 0);
from_register3: in std_logic_vector(31 downto 0);
from_register4: in std_logic_vector(31 downto 0);
from_register5: in std_logic_vector(31 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
to_register: in std_logic_vector(31 downto 0);
to_register1: in std_logic_vector(31 downto 0);
to_register2: in std_logic_vector(31 downto 0);
to_register3: in std_logic_vector(31 downto 0);
to_register4: in std_logic_vector(31 downto 0);
constant5_x0: out std_logic;
plb_decode_x0: out std_logic;
plb_decode_x1: out std_logic;
plb_decode_x2: out std_logic;
plb_decode_x3: out std_logic;
plb_decode_x4: out std_logic_vector(31 downto 0);
plb_memmap_x0: out std_logic_vector(31 downto 0);
plb_memmap_x1: out std_logic;
plb_memmap_x2: out std_logic_vector(31 downto 0);
plb_memmap_x3: out std_logic;
plb_memmap_x4: out std_logic_vector(31 downto 0);
plb_memmap_x5: out std_logic;
plb_memmap_x6: out std_logic_vector(31 downto 0);
plb_memmap_x7: out std_logic;
plb_memmap_x8: out std_logic_vector(31 downto 0);
plb_memmap_x9: out std_logic
);
end edk_processor_entity_cddda35d8e;
architecture structural of edk_processor_entity_cddda35d8e is
signal bankaddr: std_logic_vector(1 downto 0);
signal ce_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal linearaddr: std_logic_vector(7 downto 0);
signal plb_abus_net_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_net_x0: std_logic;
signal plb_rnw_net_x0: std_logic;
signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0);
signal rddata: std_logic_vector(31 downto 0);
signal rnwreg: std_logic;
signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_rddbus_x0: std_logic_vector(31 downto 0);
signal sl_wait_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_net_x0: std_logic;
signal timer0_countto_din_x0: std_logic_vector(31 downto 0);
signal timer0_countto_dout_x0: std_logic_vector(31 downto 0);
signal timer0_countto_en_x0: std_logic;
signal timer0_timeleft_dout_x0: std_logic_vector(31 downto 0);
signal timer1_countto_din_x0: std_logic_vector(31 downto 0);
signal timer1_countto_dout_x0: std_logic_vector(31 downto 0);
signal timer1_countto_en_x0: std_logic;
signal timer1_timeleft_dout_x0: std_logic_vector(31 downto 0);
signal timer2_countto_din_x0: std_logic_vector(31 downto 0);
signal timer2_countto_dout_x0: std_logic_vector(31 downto 0);
signal timer2_countto_en_x0: std_logic;
signal timer2_timeleft_dout_x0: std_logic_vector(31 downto 0);
signal timer3_countto_din_x0: std_logic_vector(31 downto 0);
signal timer3_countto_dout_x0: std_logic_vector(31 downto 0);
signal timer3_countto_en_x0: std_logic;
signal timer3_timeleft_dout_x0: std_logic_vector(31 downto 0);
signal timer_control_r_dout_x0: std_logic_vector(31 downto 0);
signal timer_control_w_din_x0: std_logic_vector(31 downto 0);
signal timer_control_w_dout_x0: std_logic_vector(31 downto 0);
signal timer_control_w_en_x0: std_logic;
signal timer_status_dout_x0: std_logic_vector(31 downto 0);
signal wrdbusreg: std_logic_vector(31 downto 0);
begin
ce_1_sg_x0 <= ce_1;
clk_1_sg_x0 <= clk_1;
timer0_timeleft_dout_x0 <= from_register;
timer1_timeleft_dout_x0 <= from_register1;
timer2_timeleft_dout_x0 <= from_register2;
timer3_timeleft_dout_x0 <= from_register3;
timer_control_r_dout_x0 <= from_register4;
timer_status_dout_x0 <= from_register5;
plb_abus_net_x0 <= plb_abus;
plb_pavalid_net_x0 <= plb_pavalid;
plb_rnw_net_x0 <= plb_rnw;
plb_wrdbus_net_x0 <= plb_wrdbus;
sg_plb_addrpref_net_x0 <= sg_plb_addrpref;
splb_rst_net_x0 <= splb_rst;
timer0_countto_dout_x0 <= to_register;
timer1_countto_dout_x0 <= to_register1;
timer2_countto_dout_x0 <= to_register2;
timer3_countto_dout_x0 <= to_register3;
timer_control_w_dout_x0 <= to_register4;
constant5_x0 <= sl_wait_x0;
plb_decode_x0 <= sl_addrack_x0;
plb_decode_x1 <= sl_rdcomp_x0;
plb_decode_x2 <= sl_wrdack_x0;
plb_decode_x3 <= sl_rddack_x0;
plb_decode_x4 <= sl_rddbus_x0;
plb_memmap_x0 <= timer0_countto_din_x0;
plb_memmap_x1 <= timer0_countto_en_x0;
plb_memmap_x2 <= timer1_countto_din_x0;
plb_memmap_x3 <= timer1_countto_en_x0;
plb_memmap_x4 <= timer2_countto_din_x0;
plb_memmap_x5 <= timer2_countto_en_x0;
plb_memmap_x6 <= timer3_countto_din_x0;
plb_memmap_x7 <= timer3_countto_en_x0;
plb_memmap_x8 <= timer_control_w_din_x0;
plb_memmap_x9 <= timer_control_w_en_x0;
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => sl_wait_x0
);
plb_decode: entity work.mcode_block_b389f41afb
port map (
addrpref => sg_plb_addrpref_net_x0,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
plbabus => plb_abus_net_x0,
plbpavalid(0) => plb_pavalid_net_x0,
plbrnw(0) => plb_rnw_net_x0,
plbrst(0) => splb_rst_net_x0,
plbwrdbus => plb_wrdbus_net_x0,
rddata => rddata,
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
linearaddr => linearaddr,
rdcomp(0) => sl_rdcomp_x0,
rddack(0) => sl_rddack_x0,
rddbus => sl_rddbus_x0,
rnwreg(0) => rnwreg,
wrdack(0) => sl_wrdack_x0,
wrdbusreg => wrdbusreg
);
plb_memmap: entity work.mcode_block_b59e0d51fc
port map (
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
linearaddr => linearaddr,
rnwreg(0) => rnwreg,
sm_timer0_countto => timer0_countto_dout_x0,
sm_timer0_timeleft => timer0_timeleft_dout_x0,
sm_timer1_countto => timer1_countto_dout_x0,
sm_timer1_timeleft => timer1_timeleft_dout_x0,
sm_timer2_countto => timer2_countto_dout_x0,
sm_timer2_timeleft => timer2_timeleft_dout_x0,
sm_timer3_countto => timer3_countto_dout_x0,
sm_timer3_timeleft => timer3_timeleft_dout_x0,
sm_timer_control_r => timer_control_r_dout_x0,
sm_timer_control_w => timer_control_w_dout_x0,
sm_timer_status => timer_status_dout_x0,
wrdbus => wrdbusreg,
read_bank_out => rddata,
sm_timer0_countto_din => timer0_countto_din_x0,
sm_timer0_countto_en(0) => timer0_countto_en_x0,
sm_timer1_countto_din => timer1_countto_din_x0,
sm_timer1_countto_en(0) => timer1_countto_en_x0,
sm_timer2_countto_din => timer2_countto_din_x0,
sm_timer2_countto_en(0) => timer2_countto_en_x0,
sm_timer3_countto_din => timer3_countto_din_x0,
sm_timer3_countto_en(0) => timer3_countto_en_x0,
sm_timer_control_w_din => timer_control_w_din_x0,
sm_timer_control_w_en(0) => timer_control_w_en_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer/timer/S-R_Latch1"
entity s_r_latch1_entity_5f9ce35768 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
r: in std_logic;
s: in std_logic;
q: out std_logic
);
end s_r_latch1_entity_5f9ce35768;
architecture structural of s_r_latch1_entity_5f9ce35768 is
signal ce_1_sg_x1: std_logic;
signal clk_1_sg_x1: std_logic;
signal inverter_op_net: std_logic;
signal logical2_y_net_x0: std_logic;
signal logical3_y_net_x0: std_logic;
signal register_q_net_x0: std_logic;
begin
ce_1_sg_x1 <= ce_1;
clk_1_sg_x1 <= clk_1;
logical2_y_net_x0 <= r;
logical3_y_net_x0 <= s;
q <= register_q_net_x0;
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
ip(0) => register_q_net_x0,
op(0) => inverter_op_net
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
d(0) => logical3_y_net_x0,
en(0) => inverter_op_net,
rst(0) => logical2_y_net_x0,
q(0) => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer/timer/posedge"
entity posedge_entity_8c50a6be04 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
in_x0: in std_logic;
out_x0: out std_logic
);
end posedge_entity_8c50a6be04;
architecture structural of posedge_entity_8c50a6be04 is
signal ce_1_sg_x3: std_logic;
signal clk_1_sg_x3: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal slice_y_net_x0: std_logic;
begin
ce_1_sg_x3 <= ce_1;
clk_1_sg_x3 <= clk_1;
slice_y_net_x0 <= in_x0;
out_x0 <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
d(0) => slice_y_net_x0,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x3,
clk => clk_1_sg_x3,
clr => '0',
ip(0) => delay_q_net,
op(0) => inverter_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => slice_y_net_x0,
d1(0) => inverter_op_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer/timer"
entity timer_entity_fee90fe8e7 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
countto: in std_logic_vector(31 downto 0);
idlefordifs_inp: in std_logic;
interruptreset: in std_logic;
mode: in std_logic;
pause: in std_logic;
resume: in std_logic;
start: in std_logic;
stop: in std_logic;
active: out std_logic;
interrupt: out std_logic;
paused: out std_logic;
timeleft: out std_logic_vector(31 downto 0)
);
end timer_entity_fee90fe8e7;
architecture structural of timer_entity_fee90fe8e7 is
signal addsub_s_net_x0: std_logic_vector(31 downto 0);
signal ce_1_sg_x5: std_logic;
signal clk_1_sg_x5: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic_vector(31 downto 0);
signal convert1_dout_net: std_logic;
signal counter_op_net: std_logic_vector(31 downto 0);
signal from_register1_data_out_net_x0: std_logic_vector(31 downto 0);
signal idlefordifs_net_x0: std_logic;
signal inverter_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net_x0: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical4_y_net_x0: std_logic;
signal logical_y_net: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal mux_y_net: std_logic;
signal register_q_net_x2: std_logic;
signal register_q_net_x3: std_logic;
signal relational1_op_net: std_logic;
signal relational_op_net_x0: std_logic;
signal slice1_y_net_x0: std_logic;
signal slice2_y_net_x1: std_logic;
signal slice3_y_net_x0: std_logic;
signal slice4_y_net_x0: std_logic;
signal slice5_y_net_x1: std_logic;
signal slice_y_net_x1: std_logic;
begin
ce_1_sg_x5 <= ce_1;
clk_1_sg_x5 <= clk_1;
from_register1_data_out_net_x0 <= countto;
idlefordifs_net_x0 <= idlefordifs_inp;
slice5_y_net_x1 <= interruptreset;
slice4_y_net_x0 <= mode;
slice3_y_net_x0 <= pause;
slice2_y_net_x1 <= resume;
slice_y_net_x1 <= start;
slice1_y_net_x0 <= stop;
active <= register_q_net_x2;
interrupt <= register_q_net_x3;
paused <= logical4_y_net_x0;
timeleft <= addsub_s_net_x0;
addsub: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 32,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 32,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 33,
core_name0 => "adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 33,
latency => 0,
mode => 2,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 32
)
port map (
a => from_register1_data_out_net_x0,
b => counter_op_net,
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
clr => '0',
en => "1",
s => addsub_s_net_x0
);
constant1: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => mux_y_net,
dout(0) => convert1_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_b57302a6bcbb6876",
op_arith => xlUnsigned,
op_width => 32
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
clr => '0',
en(0) => logical_y_net,
rst(0) => logical1_y_net,
op => counter_op_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
clr => '0',
ip(0) => register_q_net_x2,
op(0) => inverter_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => convert1_dout_net,
d1(0) => register_q_net_x2,
y(0) => logical_y_net
);
logical1: entity work.logical_6cb8f0ce02
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational_op_net_x0,
d1(0) => slice1_y_net_x0,
d2(0) => logical_y_net_x0,
y(0) => logical1_y_net
);
logical2: entity work.logical_6cb8f0ce02
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => slice1_y_net_x0,
d1(0) => slice3_y_net_x0,
d2(0) => relational_op_net_x0,
y(0) => logical2_y_net_x0
);
logical3: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => logical_y_net_x0,
d1(0) => logical_y_net_x1,
y(0) => logical3_y_net_x0
);
logical4: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational1_op_net,
d1(0) => inverter_op_net,
y(0) => logical4_y_net_x0
);
mux: entity work.mux_112ed141f4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => constant1_op_net,
d1(0) => idlefordifs_net_x0,
sel(0) => slice4_y_net_x0,
y(0) => mux_y_net
);
posedge1_8332b77348: entity work.posedge_entity_8c50a6be04
port map (
ce_1 => ce_1_sg_x5,
clk_1 => clk_1_sg_x5,
in_x0 => slice2_y_net_x1,
out_x0 => logical_y_net_x1
);
posedge_8c50a6be04: entity work.posedge_entity_8c50a6be04
port map (
ce_1 => ce_1_sg_x5,
clk_1 => clk_1_sg_x5,
in_x0 => slice_y_net_x1,
out_x0 => logical_y_net_x0
);
relational: entity work.relational_3ffd1d0a40
port map (
a => from_register1_data_out_net_x0,
b => counter_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational_op_net_x0
);
relational1: entity work.relational_34fc311f5b
port map (
a => counter_op_net,
b => constant_op_net,
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
clr => '0',
op(0) => relational1_op_net
);
s_r_latch1_5f9ce35768: entity work.s_r_latch1_entity_5f9ce35768
port map (
ce_1 => ce_1_sg_x5,
clk_1 => clk_1_sg_x5,
r => logical2_y_net_x0,
s => logical3_y_net_x0,
q => register_q_net_x2
);
s_r_latch2_722d862217: entity work.s_r_latch1_entity_5f9ce35768
port map (
ce_1 => ce_1_sg_x5,
clk_1 => clk_1_sg_x5,
r => slice5_y_net_x1,
s => relational_op_net_x0,
q => register_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer/timer_control"
entity timer_control_entity_09b11c57d8 is
port (
constant6_x0: out std_logic
);
end timer_control_entity_09b11c57d8;
architecture structural of timer_control_entity_09b11c57d8 is
signal constant6_op_net_x0: std_logic;
begin
constant6_x0 <= constant6_op_net_x0;
constant6: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant6_op_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "warp_timer"
entity warp_timer is
port (
ce_1: in std_logic;
clk_1: in std_logic;
data_out: in std_logic_vector(31 downto 0);
data_out_x0: in std_logic_vector(31 downto 0);
data_out_x1: in std_logic_vector(31 downto 0);
data_out_x2: in std_logic_vector(31 downto 0);
data_out_x3: in std_logic_vector(31 downto 0);
data_out_x4: in std_logic_vector(31 downto 0);
data_out_x5: in std_logic_vector(31 downto 0);
data_out_x6: in std_logic_vector(31 downto 0);
data_out_x7: in std_logic_vector(31 downto 0);
data_out_x8: in std_logic_vector(31 downto 0);
data_out_x9: in std_logic_vector(31 downto 0);
dout_x4: in std_logic_vector(31 downto 0);
dout_x5: in std_logic_vector(31 downto 0);
dout_x6: in std_logic_vector(31 downto 0);
dout_x7: in std_logic_vector(31 downto 0);
dout_x8: in std_logic_vector(31 downto 0);
idlefordifs: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
data_in: out std_logic_vector(31 downto 0);
data_in_x0: out std_logic_vector(31 downto 0);
data_in_x1: out std_logic_vector(31 downto 0);
data_in_x2: out std_logic_vector(31 downto 0);
data_in_x3: out std_logic_vector(31 downto 0);
data_in_x4: out std_logic_vector(31 downto 0);
data_in_x5: out std_logic_vector(31 downto 0);
data_in_x6: out std_logic_vector(31 downto 0);
data_in_x7: out std_logic_vector(31 downto 0);
data_in_x8: out std_logic_vector(31 downto 0);
data_in_x9: out std_logic_vector(31 downto 0);
en: out std_logic;
en_x0: out std_logic;
en_x1: out std_logic;
en_x2: out std_logic;
en_x3: out std_logic;
en_x4: out std_logic;
en_x5: out std_logic;
en_x6: out std_logic;
en_x7: out std_logic;
en_x8: out std_logic;
en_x9: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
timer0_active: out std_logic;
timer1_active: out std_logic;
timer2_active: out std_logic;
timer3_active: out std_logic;
timerexpire: out std_logic
);
end warp_timer;
architecture structural of warp_timer is
signal ce_1_sg_x21: std_logic;
signal clk_1_sg_x21: std_logic;
signal concat1_y_net: std_logic_vector(2 downto 0);
signal concat2_y_net: std_logic_vector(2 downto 0);
signal concat3_y_net: std_logic_vector(2 downto 0);
signal concat4_y_net: std_logic_vector(2 downto 0);
signal convert1_dout_net: std_logic_vector(7 downto 0);
signal convert2_dout_net: std_logic_vector(7 downto 0);
signal convert3_dout_net: std_logic_vector(7 downto 0);
signal convert_dout_net: std_logic_vector(7 downto 0);
signal data_in_net: std_logic_vector(31 downto 0);
signal data_in_x0_net: std_logic_vector(31 downto 0);
signal data_in_x1_net: std_logic_vector(31 downto 0);
signal data_in_x2_net: std_logic_vector(31 downto 0);
signal data_in_x3_net: std_logic_vector(31 downto 0);
signal data_in_x4_net: std_logic_vector(31 downto 0);
signal data_in_x5_net: std_logic_vector(31 downto 0);
signal data_in_x6_net: std_logic_vector(31 downto 0);
signal data_in_x7_net: std_logic_vector(31 downto 0);
signal data_in_x8_net: std_logic_vector(31 downto 0);
signal data_out_net: std_logic_vector(31 downto 0);
signal data_out_x0_net: std_logic_vector(31 downto 0);
signal data_out_x1_net: std_logic_vector(31 downto 0);
signal data_out_x2_net: std_logic_vector(31 downto 0);
signal data_out_x3_net: std_logic_vector(31 downto 0);
signal data_out_x4_net: std_logic_vector(31 downto 0);
signal data_out_x5_net: std_logic_vector(31 downto 0);
signal data_out_x6_net: std_logic_vector(31 downto 0);
signal data_out_x7_net: std_logic_vector(31 downto 0);
signal data_out_x8_net: std_logic_vector(31 downto 0);
signal dout_x4_net: std_logic_vector(31 downto 0);
signal dout_x5_net: std_logic_vector(31 downto 0);
signal dout_x6_net: std_logic_vector(31 downto 0);
signal dout_x7_net: std_logic_vector(31 downto 0);
signal dout_x8_net: std_logic_vector(31 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal en_x1_net: std_logic;
signal en_x2_net: std_logic;
signal en_x3_net: std_logic;
signal en_x4_net: std_logic;
signal en_x5_net: std_logic;
signal en_x6_net: std_logic;
signal en_x7_net: std_logic;
signal en_x8_net: std_logic;
signal en_x9_net: std_logic;
signal from_register2_data_out_net_x0: std_logic_vector(31 downto 0);
signal idlefordifs_net: std_logic;
signal logical4_y_net_x0: std_logic;
signal logical4_y_net_x1: std_logic;
signal logical4_y_net_x2: std_logic;
signal logical4_y_net_x3: std_logic;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal register_q_net_x3: std_logic;
signal register_q_net_x5: std_logic;
signal register_q_net_x7: std_logic;
signal register_q_net_x9: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal slice10_y_net_x0: std_logic;
signal slice11_y_net_x1: std_logic;
signal slice12_y_net_x1: std_logic;
signal slice13_y_net_x0: std_logic;
signal slice14_y_net_x1: std_logic;
signal slice15_y_net_x0: std_logic;
signal slice16_y_net_x0: std_logic;
signal slice17_y_net_x1: std_logic;
signal slice18_y_net_x1: std_logic;
signal slice19_y_net_x0: std_logic;
signal slice1_y_net_x0: std_logic;
signal slice20_y_net_x1: std_logic;
signal slice21_y_net_x0: std_logic;
signal slice22_y_net_x0: std_logic;
signal slice23_y_net_x1: std_logic;
signal slice2_y_net_x1: std_logic;
signal slice3_y_net_x0: std_logic;
signal slice4_y_net_x0: std_logic;
signal slice5_y_net_x1: std_logic;
signal slice6_y_net_x1: std_logic;
signal slice7_y_net_x0: std_logic;
signal slice8_y_net_x1: std_logic;
signal slice9_y_net_x0: std_logic;
signal slice_y_net_x1: std_logic;
signal splb_rst_net: std_logic;
signal timer0_active_net: std_logic;
signal timer1_active_net: std_logic;
signal timer2_active_net: std_logic;
signal timer3_active_net: std_logic;
signal timerexpire_net: std_logic;
begin
ce_1_sg_x21 <= ce_1;
clk_1_sg_x21 <= clk_1;
data_out_net <= data_out;
data_out_x0_net <= data_out_x0;
data_out_x1_net <= data_out_x1;
data_out_x2_net <= data_out_x2;
data_out_x3_net <= data_out_x3;
data_out_x4_net <= data_out_x4;
data_out_x5_net <= data_out_x5;
data_out_x6_net <= data_out_x6;
data_out_x7_net <= data_out_x7;
data_out_x8_net <= data_out_x8;
from_register2_data_out_net_x0 <= data_out_x9;
dout_x4_net <= dout_x4;
dout_x5_net <= dout_x5;
dout_x6_net <= dout_x6;
dout_x7_net <= dout_x7;
dout_x8_net <= dout_x8;
idlefordifs_net <= idlefordifs;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
data_in <= data_in_net;
data_in_x0 <= data_in_x0_net;
data_in_x1 <= data_in_x1_net;
data_in_x2 <= data_in_x2_net;
data_in_x3 <= data_in_x3_net;
data_in_x4 <= data_in_x4_net;
data_in_x5 <= data_in_x5_net;
data_in_x6 <= data_in_x6_net;
data_in_x7 <= data_in_x7_net;
data_in_x8 <= data_in_x8_net;
data_in_x9 <= from_register2_data_out_net_x0;
en <= en_net;
en_x0 <= en_x0_net;
en_x1 <= en_x1_net;
en_x2 <= en_x2_net;
en_x3 <= en_x3_net;
en_x4 <= en_x4_net;
en_x5 <= en_x5_net;
en_x6 <= en_x6_net;
en_x7 <= en_x7_net;
en_x8 <= en_x8_net;
en_x9 <= en_x9_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x1;
timer0_active <= timer0_active_net;
timer1_active <= timer1_active_net;
timer2_active <= timer2_active_net;
timer3_active <= timer3_active_net;
timerexpire <= timerexpire_net;
concat: entity work.concat_a1e126f11c
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => convert3_dout_net,
in1 => convert2_dout_net,
in2 => convert1_dout_net,
in3 => convert_dout_net,
y => data_in_x3_net
);
concat1: entity work.concat_09e13b86e0
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => logical4_y_net_x0,
in1(0) => timer0_active_net,
in2(0) => register_q_net_x3,
y => concat1_y_net
);
concat2: entity work.concat_09e13b86e0
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => logical4_y_net_x1,
in1(0) => timer1_active_net,
in2(0) => register_q_net_x5,
y => concat2_y_net
);
concat3: entity work.concat_09e13b86e0
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => logical4_y_net_x2,
in1(0) => timer2_active_net,
in2(0) => register_q_net_x7,
y => concat3_y_net
);
concat4: entity work.concat_09e13b86e0
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => logical4_y_net_x3,
in1(0) => timer3_active_net,
in2(0) => register_q_net_x9,
y => concat4_y_net
);
constant1: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => en_net
);
constant2: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => en_x0_net
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => en_x1_net
);
constant4: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => en_x2_net
);
constant5: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => en_x3_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 3,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 8,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din => concat1_y_net,
dout => convert_dout_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 3,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 8,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din => concat2_y_net,
dout => convert1_dout_net
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 3,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 8,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din => concat3_y_net,
dout => convert2_dout_net
);
convert3: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 3,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 8,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din => concat4_y_net,
dout => convert3_dout_net
);
edk_processor_cddda35d8e: entity work.edk_processor_entity_cddda35d8e
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_x3_net,
from_register1 => data_out_x4_net,
from_register2 => data_out_x5_net,
from_register3 => data_out_x6_net,
from_register4 => data_out_x7_net,
from_register5 => data_out_x8_net,
plb_abus => plb_abus_net,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
to_register => dout_x4_net,
to_register1 => dout_x5_net,
to_register2 => dout_x6_net,
to_register3 => dout_x7_net,
to_register4 => dout_x8_net,
constant5_x0 => sl_wait_net,
plb_decode_x0 => sl_addrack_net,
plb_decode_x1 => sl_rdcomp_net,
plb_decode_x2 => sl_wrdack_x1,
plb_decode_x3 => sl_rddack_net,
plb_decode_x4 => sl_rddbus_net,
plb_memmap_x0 => data_in_x4_net,
plb_memmap_x1 => en_x4_net,
plb_memmap_x2 => data_in_x5_net,
plb_memmap_x3 => en_x5_net,
plb_memmap_x4 => data_in_x6_net,
plb_memmap_x5 => en_x6_net,
plb_memmap_x6 => data_in_x7_net,
plb_memmap_x7 => en_x7_net,
plb_memmap_x8 => data_in_x8_net,
plb_memmap_x9 => en_x8_net
);
logical: entity work.logical_a6d07705dd
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register_q_net_x3,
d1(0) => register_q_net_x5,
d2(0) => register_q_net_x7,
d3(0) => register_q_net_x9,
y(0) => timerexpire_net
);
slice: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice_y_net_x1
);
slice1: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 1,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice1_y_net_x0
);
slice10: entity work.xlslice
generic map (
new_lsb => 12,
new_msb => 12,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice10_y_net_x0
);
slice11: entity work.xlslice
generic map (
new_lsb => 13,
new_msb => 13,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice11_y_net_x1
);
slice12: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 16,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice12_y_net_x1
);
slice13: entity work.xlslice
generic map (
new_lsb => 17,
new_msb => 17,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice13_y_net_x0
);
slice14: entity work.xlslice
generic map (
new_lsb => 18,
new_msb => 18,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice14_y_net_x1
);
slice15: entity work.xlslice
generic map (
new_lsb => 19,
new_msb => 19,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice15_y_net_x0
);
slice16: entity work.xlslice
generic map (
new_lsb => 20,
new_msb => 20,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice16_y_net_x0
);
slice17: entity work.xlslice
generic map (
new_lsb => 21,
new_msb => 21,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice17_y_net_x1
);
slice18: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 24,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice18_y_net_x1
);
slice19: entity work.xlslice
generic map (
new_lsb => 25,
new_msb => 25,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice19_y_net_x0
);
slice2: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 2,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice2_y_net_x1
);
slice20: entity work.xlslice
generic map (
new_lsb => 26,
new_msb => 26,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice20_y_net_x1
);
slice21: entity work.xlslice
generic map (
new_lsb => 27,
new_msb => 27,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice21_y_net_x0
);
slice22: entity work.xlslice
generic map (
new_lsb => 28,
new_msb => 28,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice22_y_net_x0
);
slice23: entity work.xlslice
generic map (
new_lsb => 29,
new_msb => 29,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice23_y_net_x1
);
slice3: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice3_y_net_x0
);
slice4: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 4,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice4_y_net_x0
);
slice5: entity work.xlslice
generic map (
new_lsb => 5,
new_msb => 5,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice5_y_net_x1
);
slice6: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice6_y_net_x1
);
slice7: entity work.xlslice
generic map (
new_lsb => 9,
new_msb => 9,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice7_y_net_x0
);
slice8: entity work.xlslice
generic map (
new_lsb => 10,
new_msb => 10,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice8_y_net_x1
);
slice9: entity work.xlslice
generic map (
new_lsb => 11,
new_msb => 11,
x_width => 32,
y_width => 1
)
port map (
x => from_register2_data_out_net_x0,
y(0) => slice9_y_net_x0
);
timer1_a9ea58dee7: entity work.timer_entity_fee90fe8e7
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
countto => data_out_x0_net,
idlefordifs_inp => idlefordifs_net,
interruptreset => slice11_y_net_x1,
mode => slice10_y_net_x0,
pause => slice9_y_net_x0,
resume => slice8_y_net_x1,
start => slice6_y_net_x1,
stop => slice7_y_net_x0,
active => timer1_active_net,
interrupt => register_q_net_x5,
paused => logical4_y_net_x1,
timeleft => data_in_x0_net
);
timer2_15928ecc3b: entity work.timer_entity_fee90fe8e7
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
countto => data_out_x1_net,
idlefordifs_inp => idlefordifs_net,
interruptreset => slice17_y_net_x1,
mode => slice16_y_net_x0,
pause => slice15_y_net_x0,
resume => slice14_y_net_x1,
start => slice12_y_net_x1,
stop => slice13_y_net_x0,
active => timer2_active_net,
interrupt => register_q_net_x7,
paused => logical4_y_net_x2,
timeleft => data_in_x1_net
);
timer3_4ea9afe7c4: entity work.timer_entity_fee90fe8e7
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
countto => data_out_x2_net,
idlefordifs_inp => idlefordifs_net,
interruptreset => slice23_y_net_x1,
mode => slice22_y_net_x0,
pause => slice21_y_net_x0,
resume => slice20_y_net_x1,
start => slice18_y_net_x1,
stop => slice19_y_net_x0,
active => timer3_active_net,
interrupt => register_q_net_x9,
paused => logical4_y_net_x3,
timeleft => data_in_x2_net
);
timer_control_09b11c57d8: entity work.timer_control_entity_09b11c57d8
port map (
constant6_x0 => en_x9_net
);
timer_fee90fe8e7: entity work.timer_entity_fee90fe8e7
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
countto => data_out_net,
idlefordifs_inp => idlefordifs_net,
interruptreset => slice5_y_net_x1,
mode => slice4_y_net_x0,
pause => slice3_y_net_x0,
resume => slice2_y_net_x1,
start => slice_y_net_x1,
stop => slice1_y_net_x0,
active => timer0_active_net,
interrupt => register_q_net_x3,
paused => logical4_y_net_x0,
timeleft => data_in_net
);
end structural;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;
entity xlclkprobe is
port (clk : in std_logic;
clr : in std_logic;
ce : in std_logic;
fakeOutForXst : out std_logic);
end xlclkprobe;
architecture behavior of xlclkprobe is
begin
fakeOutForXst <= '0';
-- synopsys translate_off
work.clock_pkg.int_clk <= clk;
-- synopsys translate_on
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xland2 is
port (
a : in std_logic;
b : in std_logic;
dout : out std_logic
);
end xland2;
architecture behavior of xland2 is
begin
dout <= a and b;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity warp_timer_cw is
port (
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
idlefordifs: in std_logic;
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(19 downto 0);
splb_rst: in std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
timer0_active: out std_logic;
timer1_active: out std_logic;
timer2_active: out std_logic;
timer3_active: out std_logic;
timerexpire: out std_logic
);
end warp_timer_cw;
architecture structural of warp_timer_cw is
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type: string;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal ce_1_sg_x21: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x21: signal is "REDUCE";
signal clkNet: std_logic;
signal clk_1_sg_x21: std_logic;
signal data_in_net: std_logic_vector(31 downto 0);
signal data_in_x0_net: std_logic_vector(31 downto 0);
signal data_in_x1_net: std_logic_vector(31 downto 0);
signal data_in_x2_net: std_logic_vector(31 downto 0);
signal data_in_x3_net: std_logic_vector(31 downto 0);
signal data_in_x4_net: std_logic_vector(31 downto 0);
signal data_in_x5_net: std_logic_vector(31 downto 0);
signal data_in_x6_net: std_logic_vector(31 downto 0);
signal data_in_x7_net: std_logic_vector(31 downto 0);
signal data_in_x8_net: std_logic_vector(31 downto 0);
signal data_out_net: std_logic_vector(31 downto 0);
signal data_out_x0_net: std_logic_vector(31 downto 0);
signal data_out_x1_net: std_logic_vector(31 downto 0);
signal data_out_x2_net: std_logic_vector(31 downto 0);
signal data_out_x3_net: std_logic_vector(31 downto 0);
signal data_out_x4_net: std_logic_vector(31 downto 0);
signal data_out_x5_net: std_logic_vector(31 downto 0);
signal data_out_x6_net: std_logic_vector(31 downto 0);
signal data_out_x7_net: std_logic_vector(31 downto 0);
signal data_out_x8_net: std_logic_vector(31 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal en_x1_net: std_logic;
signal en_x2_net: std_logic;
signal en_x3_net: std_logic;
signal en_x4_net: std_logic;
signal en_x5_net: std_logic;
signal en_x6_net: std_logic;
signal en_x7_net: std_logic;
signal en_x8_net: std_logic;
signal en_x9_net: std_logic;
signal from_register2_data_out_net_x0: std_logic_vector(31 downto 0);
signal from_register2_data_out_net_x1: std_logic_vector(31 downto 0);
signal idlefordifs_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal sg_plb_addrpref_net: std_logic_vector(19 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal timer0_active_net: std_logic;
signal timer0_countTo_reg_ce: std_logic;
signal timer0_timeLeft_reg_ce: std_logic;
signal timer1_active_net: std_logic;
signal timer1_countTo_reg_ce: std_logic;
signal timer1_timeLeft_reg_ce: std_logic;
signal timer2_active_net: std_logic;
signal timer2_countTo_reg_ce: std_logic;
signal timer2_timeLeft_reg_ce: std_logic;
signal timer3_active_net: std_logic;
signal timer3_countTo_reg_ce: std_logic;
signal timer3_timeLeft_reg_ce: std_logic;
signal timer_control_r_reg_ce: std_logic;
signal timer_control_w_reg_ce: std_logic;
signal timer_status_reg_ce: std_logic;
signal timerexpire_net: std_logic;
begin
clkNet <= clk;
idlefordifs_net <= idlefordifs;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x2;
sl_wrdack <= sl_wrdack_x1;
timer0_active <= timer0_active_net;
timer1_active <= timer1_active_net;
timer2_active <= timer2_active_net;
timer3_active <= timer3_active_net;
timerexpire <= timerexpire_net;
clk_probe: entity work.xlclkprobe
port map (
ce => '1',
clk => clkNet,
clr => '0'
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
timer0_countTo: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer0_countTo_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x4_net,
o => data_out_net
);
timer0_countTo_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x4_net,
dout => timer0_countTo_reg_ce
);
timer0_timeLeft: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer0_timeLeft_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_net,
o => data_out_x3_net
);
timer0_timeLeft_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_net,
dout => timer0_timeLeft_reg_ce
);
timer1_countTo: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer1_countTo_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x5_net,
o => data_out_x0_net
);
timer1_countTo_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x5_net,
dout => timer1_countTo_reg_ce
);
timer1_timeLeft: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer1_timeLeft_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x0_net,
o => data_out_x4_net
);
timer1_timeLeft_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x0_net,
dout => timer1_timeLeft_reg_ce
);
timer2_countTo: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer2_countTo_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x6_net,
o => data_out_x1_net
);
timer2_countTo_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x6_net,
dout => timer2_countTo_reg_ce
);
timer2_timeLeft: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer2_timeLeft_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x1_net,
o => data_out_x5_net
);
timer2_timeLeft_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x1_net,
dout => timer2_timeLeft_reg_ce
);
timer3_countTo: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer3_countTo_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x7_net,
o => data_out_x2_net
);
timer3_countTo_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x7_net,
dout => timer3_countTo_reg_ce
);
timer3_timeLeft: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer3_timeLeft_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x2_net,
o => data_out_x6_net
);
timer3_timeLeft_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x2_net,
dout => timer3_timeLeft_reg_ce
);
timer_control_r: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer_control_r_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => from_register2_data_out_net_x1,
o => data_out_x7_net
);
timer_control_r_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x9_net,
dout => timer_control_r_reg_ce
);
timer_control_w: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer_control_w_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x8_net,
o => from_register2_data_out_net_x0
);
timer_control_w_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x8_net,
dout => timer_control_w_reg_ce
);
timer_status: entity work.synth_reg_w_init
generic map (
width => 32,
init_index => 2,
init_value => b"00000000000000000000000000000000",
latency => 1
)
port map (
ce => timer_status_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x3_net,
o => data_out_x8_net
);
timer_status_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x3_net,
dout => timer_status_reg_ce
);
warp_timer_x0: entity work.warp_timer
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
data_out => data_out_net,
data_out_x0 => data_out_x0_net,
data_out_x1 => data_out_x1_net,
data_out_x2 => data_out_x2_net,
data_out_x3 => data_out_x3_net,
data_out_x4 => data_out_x4_net,
data_out_x5 => data_out_x5_net,
data_out_x6 => data_out_x6_net,
data_out_x7 => data_out_x7_net,
data_out_x8 => data_out_x8_net,
data_out_x9 => from_register2_data_out_net_x0,
dout_x4 => data_out_net,
dout_x5 => data_out_x0_net,
dout_x6 => data_out_x1_net,
dout_x7 => data_out_x2_net,
dout_x8 => from_register2_data_out_net_x0,
idlefordifs => idlefordifs_net,
plb_abus => plb_abus_net,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
data_in => data_in_net,
data_in_x0 => data_in_x0_net,
data_in_x1 => data_in_x1_net,
data_in_x2 => data_in_x2_net,
data_in_x3 => data_in_x3_net,
data_in_x4 => data_in_x4_net,
data_in_x5 => data_in_x5_net,
data_in_x6 => data_in_x6_net,
data_in_x7 => data_in_x7_net,
data_in_x8 => data_in_x8_net,
data_in_x9 => from_register2_data_out_net_x1,
en => en_net,
en_x0 => en_x0_net,
en_x1 => en_x1_net,
en_x2 => en_x2_net,
en_x3 => en_x3_net,
en_x4 => en_x4_net,
en_x5 => en_x5_net,
en_x6 => en_x6_net,
en_x7 => en_x7_net,
en_x8 => en_x8_net,
en_x9 => en_x9_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x2,
sl_wrdack => sl_wrdack_x1,
timer0_active => timer0_active_net,
timer1_active => timer1_active_net,
timer2_active => timer2_active_net,
timer3_active => timer3_active_net,
timerexpire => timerexpire_net
);
end structural;
| bsd-2-clause | dcbc35553582859d53e7cff81af7310c | 0.596049 | 3.289037 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_top_v6.vhd | 9 | 52,731 | `protect begin_protected
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37296)
`protect data_block
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`protect end_protected
| gpl-3.0 | 0157c0bab7cbeb01f3a6b4514b75f171 | 0.94855 | 1.820193 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo_generator_top.vhd | 9 | 37,688 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26160)
`protect data_block
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| gpl-3.0 | 54d04060becac63a43368ff2aa09b3bc | 0.947437 | 1.828804 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/ddr2ram/user_design/rtl/memc3_wrapper.vhd | 6 | 46,600 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Rd Port signals
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0) ;
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0) ;
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
--User Port3 Interface Signals
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0) ;
p3_cmd_bl : in std_logic_vector(5 downto 0) ;
p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
--Data Wr Port signals
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0) ;
p3_wr_data : in std_logic_vector(31 downto 0) ;
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0) ;
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "001100";
constant C_PORT_CONFIG : string := "B32_B32_R32_W32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_ddr2_s6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3200, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port2_Port3, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '0',
p0_cmd_clk => '0',
p0_cmd_en => '0',
p0_cmd_instr => (others => '0'),
p0_cmd_bl => (others => '0'),
p0_cmd_byte_addr => (others => '0'),
p0_cmd_empty => open,
p0_cmd_full => open,
p0_rd_clk => '0',
p0_rd_en => '0',
p0_rd_data => open,
p0_rd_full => open,
p0_rd_empty => open,
p0_rd_count => open,
p0_rd_overflow => open,
p0_rd_error => open,
p0_wr_clk => '0',
p0_wr_en => '0',
p0_wr_mask => (others => '0'),
p0_wr_data => (others => '0'),
p0_wr_full => open,
p0_wr_empty => open,
p0_wr_count => open,
p0_wr_underrun => open,
p0_wr_error => open,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => p2_rd_clk,
p2_rd_en => p2_rd_en,
p2_rd_data => p2_rd_data,
p2_rd_full => p2_rd_full,
p2_rd_empty => p2_rd_empty,
p2_rd_count => p2_rd_count,
p2_rd_overflow => p2_rd_overflow,
p2_rd_error => p2_rd_error,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '1',
p3_cmd_clk => p3_cmd_clk,
p3_cmd_en => p3_cmd_en,
p3_cmd_instr => p3_cmd_instr,
p3_cmd_bl => p3_cmd_bl,
p3_cmd_byte_addr => p3_cmd_byte_addr,
p3_cmd_empty => p3_cmd_empty,
p3_cmd_full => p3_cmd_full,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => p3_wr_clk,
p3_wr_en => p3_wr_en,
p3_wr_mask => p3_wr_mask,
p3_wr_data => p3_wr_data,
p3_wr_full => p3_wr_full,
p3_wr_empty => p3_wr_empty,
p3_wr_count => p3_wr_count,
p3_wr_underrun => p3_wr_underrun,
p3_wr_error => p3_wr_error,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
| bsd-2-clause | 5ca3c26e74cac276f7e24db0c157a238 | 0.425751 | 3.503496 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_getinit_pkg.vhd | 9 | 54,741 | `protect begin_protected
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| gpl-3.0 | bdb346adfffeff97e69fc1d7ce0ab177 | 0.949745 | 1.823484 | false | false | false | false |
ymei/TMSPlane | Firmware/src/ten_gig_eth/TE07412C1/pcs_pma/ten_gig_eth_pcs_pma_0_gt_common.vhd | 3 | 10,216 | -------------------------------------------------------------------------------
-- Title : GT Common wrapper
-- Project : 10GBASE-R
-------------------------------------------------------------------------------
-- File : ten_gig_eth_pcs_pma_0_gt_common.vhd
-------------------------------------------------------------------------------
-- Description: This file contains the
-- 10GBASE-R Transceiver GT Common block.
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ten_gig_eth_pcs_pma_0_gt_common is
generic
(
WRAPPER_SIM_GTRESET_SPEEDUP : string := "false" --Does not affect hardware
);
port
(
refclk : in std_logic;
qpllreset : in std_logic;
qplllock : out std_logic;
qplloutclk : out std_logic;
qplloutrefclk : out std_logic
);
end entity ten_gig_eth_pcs_pma_0_gt_common;
architecture wrapper of ten_gig_eth_pcs_pma_0_gt_common is
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
-- List of signals to connect to GT Common block
signal gt0_gtrefclk0_common_in : std_logic;
signal gt0_qpllreset_in : std_logic;
signal gt0_qplllock_out : std_logic;
signal gt0_qplloutclk_i : std_logic;
signal gt0_qplloutrefclk_i : std_logic;
--*************************Logic to set Attribute QPLL_FB_DIV*****************************
impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
begin
if (qpllfbdiv_top = 16) then
return "0000100000";
elsif (qpllfbdiv_top = 20) then
return "0000110000" ;
elsif (qpllfbdiv_top = 32) then
return "0001100000" ;
elsif (qpllfbdiv_top = 40) then
return "0010000000" ;
elsif (qpllfbdiv_top = 64) then
return "0011100000" ;
elsif (qpllfbdiv_top = 66) then
return "0101000000" ;
elsif (qpllfbdiv_top = 80) then
return "0100100000" ;
elsif (qpllfbdiv_top = 100) then
return "0101110000" ;
else
return "0000000000" ;
end if;
end function;
impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
begin
if (qpllfbdiv_top = 16) then
return '1';
elsif (qpllfbdiv_top = 20) then
return '1' ;
elsif (qpllfbdiv_top = 32) then
return '1' ;
elsif (qpllfbdiv_top = 40) then
return '1' ;
elsif (qpllfbdiv_top = 64) then
return '1' ;
elsif (qpllfbdiv_top = 66) then
return '0' ;
elsif (qpllfbdiv_top = 80) then
return '1' ;
elsif (qpllfbdiv_top = 100) then
return '1' ;
else
return '1' ;
end if;
end function;
constant QPLL_FBDIV_TOP : integer := 66;
constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
gt0_gtrefclk0_common_in <= refclk;
gt0_qpllreset_in <= qpllreset;
qplllock <= gt0_qplllock_out;
qplloutclk <= gt0_qplloutclk_i;
qplloutrefclk <= gt0_qplloutrefclk_i;
gtxe2_common_0_i : GTXE2_COMMON
generic map
(
-- Simulation attributes
SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
SIM_QPLLREFCLK_SEL => ("001"),
SIM_VERSION => "4.0",
------------------COMMON BLOCK Attributes---------------
BIAS_CFG => (x"0000040000001000"),
COMMON_CFG => (x"00000000"),
QPLL_CFG => (x"0680181"),
QPLL_CLKOUT_CFG => ("0000"),
QPLL_COARSE_FREQ_OVRD => ("010000"),
QPLL_COARSE_FREQ_OVRD_EN => ('0'),
QPLL_CP => ("0000011111"),
QPLL_CP_MONITOR_EN => ('0'),
QPLL_DMONITOR_SEL => ('0'),
QPLL_FBDIV => (QPLL_FBDIV_IN),
QPLL_FBDIV_MONITOR_EN => ('0'),
QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
QPLL_INIT_CFG => (x"000006"),
QPLL_LOCK_CFG => (x"21E8"),
QPLL_LPF => ("1111"),
QPLL_REFCLK_DIV => (1)
)
port map
(
------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
DRPADDR => tied_to_ground_vec_i(7 downto 0),
DRPCLK => tied_to_ground_i,
DRPDI => tied_to_ground_vec_i(15 downto 0),
DRPDO => open,
DRPEN => tied_to_ground_i,
DRPRDY => open,
DRPWE => tied_to_ground_i,
---------------------- Common Block - Ref Clock Ports ---------------------
GTGREFCLK => tied_to_ground_i,
GTNORTHREFCLK0 => tied_to_ground_i,
GTNORTHREFCLK1 => tied_to_ground_i,
GTREFCLK0 => gt0_gtrefclk0_common_in,
GTREFCLK1 => tied_to_ground_i,
GTSOUTHREFCLK0 => tied_to_ground_i,
GTSOUTHREFCLK1 => tied_to_ground_i,
----------------------- Common Block - Clocking Ports ----------------------
QPLLOUTCLK => gt0_qplloutclk_i,
QPLLOUTREFCLK => gt0_qplloutrefclk_i,
REFCLKOUTMONITOR => open,
------------------------- Common Block - QPLL Ports ------------------------
QPLLDMONITOR => open,
QPLLFBCLKLOST => open,
QPLLLOCK => gt0_qplllock_out,
QPLLLOCKDETCLK => '0',
QPLLLOCKEN => tied_to_vcc_i,
QPLLOUTRESET => tied_to_ground_i,
QPLLPD => tied_to_ground_i,
QPLLREFCLKLOST => open,
QPLLREFCLKSEL => "001",
QPLLRESET => gt0_qpllreset_in,
QPLLRSVD1 => "0000000000000000",
QPLLRSVD2 => "11111",
--------------------------------- QPLL Ports -------------------------------
BGBYPASSB => tied_to_vcc_i,
BGMONITORENB => tied_to_vcc_i,
BGPDB => tied_to_vcc_i,
BGRCALOVRD => "11111",
PMARSVD => "00000000",
RCALENB => tied_to_vcc_i
);
end wrapper;
| bsd-3-clause | 32b2a57978b32d7c4940a35a2061ecaa | 0.480227 | 4.380789 | false | false | false | false |
ymei/TMSPlane | Firmware/src/channel_avg.vhd | 2 | 3,633 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:32:46 06/20/2014
-- Design Name:
-- Module Name: channel_avg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY channel_avg IS
GENERIC (
NCH : positive := 16;
OUTCH_WIDTH : positive := 16;
INTERNAL_WIDTH : positive := 32;
INDATA_WIDTH : positive := 256;
OUTDATA_WIDTH : positive := 256
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
-- high 4-bit is offset, 2**(low 4-bit) is number of points to average
CONFIG : IN std_logic_vector(7 DOWNTO 0);
TRIG : IN std_logic;
INDATA_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0);
OUTVALID : OUT std_logic;
OUTDATA_Q : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0)
);
END channel_avg;
ARCHITECTURE Behavioral OF channel_avg IS
SIGNAL trig_prev : std_logic;
SIGNAL trig_prev1 : std_logic;
SIGNAL trig_prev2 : std_logic;
SIGNAL trig_synced : std_logic;
--
SIGNAL avg_n : positive;
--
TYPE INTERNALVAL IS ARRAY(NCH-1 DOWNTO 0) OF signed(INTERNAL_WIDTH-1 DOWNTO 0);
SIGNAL inch_val : INTERNALVAL;
SIGNAL internal_val : INTERNALVAL;
BEGIN
PROCESS (CLK) IS
VARIABLE i : integer;
BEGIN
IF falling_edge(CLK) THEN -- register half-cycle earlier
FOR i IN 0 TO NCH-1 LOOP
inch_val(i) <= resize(signed(INDATA_Q(16*(i+1)-1 DOWNTO 16*i)), INTERNAL_WIDTH);
END LOOP;
END IF;
END PROCESS;
-- capture the rising edge of trigger
PROCESS (CLK, RESET) IS
BEGIN
IF RESET = '1' THEN
trig_prev <= '0';
trig_prev1 <= '0';
trig_prev2 <= '0';
ELSIF rising_edge(CLK) THEN
trig_prev <= TRIG;
trig_prev1 <= trig_prev;
trig_prev2 <= trig_prev1;
END IF;
END PROCESS;
trig_synced <= '1' WHEN trig_prev2 = '0' AND trig_prev1 = '1' ELSE '0';
avg_n <= to_integer(unsigned(CONFIG(3 DOWNTO 0)));
PROCESS (CLK, RESET) IS
VARIABLE i : integer;
VARIABLE j : unsigned(15 DOWNTO 0);
BEGIN
IF RESET = '1' THEN
FOR i IN 0 TO NCH-1 LOOP
internal_val(i) <= (OTHERS => '0');
END LOOP;
OUTVALID <= '0';
j := (OTHERS => '0');
ELSIF rising_edge(CLK) THEN
IF trig_synced = '1' THEN
j := resize(unsigned(CONFIG(7 DOWNTO 4)), j'length) + 1;
END IF;
FOR i IN 0 TO NCH-1 LOOP
IF j = 1 THEN
internal_val(i) <= inch_val(i);
ELSE
internal_val(i) <= internal_val(i) + inch_val(i);
END IF;
END LOOP;
IF j(avg_n) = '1' THEN
j := to_unsigned(1, j'length);
OUTVALID <= '1';
ELSE
j := j + 1;
OUTVALID <= '0';
END IF;
END IF;
END PROCESS;
outdata_q_inst : FOR i IN 0 TO NCH-1 GENERATE
OUTDATA_Q(OUTCH_WIDTH*(i+1)-1 DOWNTO OUTCH_WIDTH*i) <=
std_logic_vector(internal_val(i)(OUTCH_WIDTH-1+avg_n DOWNTO avg_n));
END GENERATE;
END Behavioral;
| bsd-3-clause | 0f40beb252f278f34c775f5abc28ab9e | 0.561519 | 3.476555 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_v8_0.vhd | 9 | 19,058 | `protect begin_protected
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12368)
`protect data_block
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`protect end_protected
| gpl-3.0 | 290701c0d94cfa135c0ac98160ec4cbf | 0.939396 | 1.852089 | false | false | false | false |
ymei/TMSPlane | Firmware/src/clk_div.vhd | 2 | 1,481 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:32:46 01/25/2015
-- Design Name:
-- Module Name: clk_div - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Clock dividing
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY clk_div IS
GENERIC (
WIDTH : positive := 16;
PBITS : positive := 4 -- log2(WIDTH)
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
DIV : IN std_logic_vector(PBITS-1 DOWNTO 0);
CLK_DIV : OUT std_logic
);
END clk_div;
ARCHITECTURE Behavioral OF clk_div IS
SIGNAL cnt : unsigned(WIDTH-1 DOWNTO 0);
BEGIN
PROCESS (CLK, RESET) IS
BEGIN
IF RESET = '1' THEN
cnt <= (OTHERS => '0');
ELSIF rising_edge(CLK) THEN
cnt <= cnt + 1;
END IF;
END PROCESS;
CLK_DIV <= CLK WHEN to_integer(unsigned(DIV)) = 0 ELSE
cnt(to_integer(unsigned(DIV))-1);
END Behavioral;
| bsd-3-clause | 47a1acc297d763c1ce28a3ef5b23066a | 0.565159 | 3.846753 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/misc/controller.vhd | 2 | 13,411 | -- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--
-- Adds
-- U = usb/uvc
-- J = jpeg encoder
-- S = source selector
-- H = Hdmi
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity controller is
port
(
status : out std_logic_vector(4 downto 0);
usb_cmd : out std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
jpeg_encoder_cmd : out std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
selector_cmd : out std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
HB_on : out std_logic;
uart_rd : out std_logic;
uart_rx_empty : in std_logic;
uart_din : in std_logic_vector(7 downto 0);
uart_clk : in std_logic;
usb_or_uart : in std_logic;
hdmi_cmd : out std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
hdmi_dvi : in std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
rdy_H : in std_logic_vector(1 downto 0);
btnu : in std_logic;
btnd : in std_logic;
btnl : in std_logic;
btnr : in std_logic;
uvc_rst : out std_logic;
cmd_byte : in std_logic_vector(7 downto 0);
cmd_en : in std_logic;
rst : in std_logic;
ifclk : in std_logic;
clk : in std_logic
);
end entity;
ARCHITECTURE rtl OF controller is
COMPONENT cmdfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
signal usb_cmd_i : std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
signal jpeg_encoder_cmd_i : std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
signal selector_cmd_i : std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
signal HB_on_i : std_logic;
signal hdmi_cmd_i : std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
signal hdmi_dvi_q : std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
signal counter : std_logic_vector(7 downto 0);
signal cmd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal add : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rd_en : STD_LOGIC;
signal dout : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal full : STD_LOGIC;
signal almost_full : STD_LOGIC;
signal empty : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal valid : STD_LOGIC;
signal uvc_rst_i : STD_LOGIC;
signal vsync_q : STD_LOGIC;
signal vsync_rising_edge : STD_LOGIC;
signal pressed : STD_LOGIC;
signal toggle : STD_LOGIC;
signal uart_rd_s : STD_LOGIC;
signal empty_s : STD_LOGIC;
signal fifo_din : STD_LOGIC_VECTOR(7 downto 0);
signal fifo_clk : STD_LOGIC;
signal fifo_wr : STD_LOGIC;
begin
-- comb logic
usb_cmd <= usb_cmd_i;
jpeg_encoder_cmd <= jpeg_encoder_cmd_i;
selector_cmd <= selector_cmd_i;
hdmi_cmd <= hdmi_cmd_i;
HB_on <= HB_on_i;
-- CMD Decoder
process(rst,clk)
begin
if rst = '1' then
usb_cmd_i <= "001"; -- uvc on/off(2) raw/jpeg(1) UVCpayloadheader(0)
jpeg_encoder_cmd_i <= "00"; -- encodingQuality(1 downto 0)
selector_cmd_i(3 downto 0) <= "0111"; -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted)
selector_cmd_i(12 downto 4) <= "111000000"; --(4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
HB_on_i <= '1';
hdmi_cmd_i <= "11"; -- if 1 then dvi else hdmi
uvc_rst_i <= '1';
pressed <= '0';
hdmi_dvi_q <= "00";
status <= (others => '0');
toggle <= '0';
counter <= (others => '0');
elsif rising_edge(clk) then
if uvc_rst_i = '1' then
uvc_rst <= '1';
counter <= (others => '0');
toggle <= '1';
else
counter <= counter+1;
end if;
if counter = (counter'range => '1') and toggle = '1' then
uvc_rst <= '0';
toggle <= '0';
end if;
uvc_rst_i <= '0';
status <= (others => '0');
rd_en <= '0';
hdmi_dvi_q <= hdmi_dvi;
if (hdmi_dvi_q(0) xor hdmi_dvi(0)) = '1' then
hdmi_cmd_i(0) <= hdmi_dvi(0);
end if;
if (hdmi_dvi_q(1) xor hdmi_dvi(1)) = '1' then
hdmi_cmd_i(1) <= hdmi_dvi(1);
end if;
if btnd = '1' and pressed = '0' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "11";
pressed <= '1';
else
pressed <= '0';
end if;
if btnl = '1' and pressed = '0' and rdy_H(1) = '1' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "01";
pressed <= '1';
else
pressed <= '0';
end if;
if btnu = '1' and pressed = '0' and rdy_H(0) = '1' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "00";
pressed <= '1';
else
pressed <= '0';
end if;
if empty = '0' and rd_en = '0' then
rd_en <= '1';
case add is
when X"55" | X"75" => -- U UVC/USB / UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
case cmd is
when X"4a" | X"6a" => -- J j
usb_cmd_i(1) <= '1';
uvc_rst_i <= '1';
when X"52" | X"72" => -- Rr
usb_cmd_i(1) <= '0';
uvc_rst_i <= '1';
when X"4e" | X"6e" => -- N n (on)
usb_cmd_i(2) <= '1';
uvc_rst_i <= '1';
when X"46" | X"66" => -- Ff (off)
usb_cmd_i(2) <= '0';
uvc_rst_i <= '1';
when X"56" | X"76" => -- V v (video) header on
usb_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when X"49" | X"69" => -- I i (image) header off
usb_cmd_i(0) <= '0';
uvc_rst_i <= '1';
when X"53" | X"73" => -- Status
status(0) <= '1';
when X"48" | X"68" => -- H
uvc_rst_i <= '1';
if (selector_cmd_i(1 downto 0) = "00") then -- hdmi 0
hdmi_cmd_i(0) <= '0'; -- HDMI
elsif (selector_cmd_i(1 downto 0) = "01") then -- hdmi 1
hdmi_cmd_i(1) <= '0'; -- HDMI
end if;
when X"44" | X"64" => -- D
uvc_rst_i <= '1';
if (selector_cmd_i(1 downto 0) = "00") then -- hdmi 0
hdmi_cmd_i(0) <= '1'; -- DVI
elsif (selector_cmd_i(1 downto 0) = "01") then -- hdmi 1
hdmi_cmd_i(1) <= '1'; -- DVI
end if;
when others =>
end case;
when X"4a" | X"6a" => -- J Jpeg
case cmd is
when X"53" | X"73" => -- Status
status(1) <= '1';
when X"30" => -- quality 100 %
jpeg_encoder_cmd_i(1 downto 0) <= "00";
when X"31" => -- quality 85%
jpeg_encoder_cmd_i(1 downto 0) <= "01";
when X"32" => -- quality 75%
jpeg_encoder_cmd_i(1 downto 0) <= "10";
when X"33" => -- quality 50%
jpeg_encoder_cmd_i(1 downto 0) <= "11";
when others =>
end case;
when X"48" | X"68" => -- H Hdmi
case cmd is
when X"53" | X"73" => -- Status
status(3) <= '1';
when X"30" => -- Force HDMI 0 to 720p
hdmi_cmd_i(0) <= '0';
uvc_rst_i <= '1';
when X"31" => -- Force HDMI 0 to 1024
hdmi_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when X"32" => -- Force HDMI 1 to 720p
hdmi_cmd_i(1) <= '0';
uvc_rst_i <= '1';
when X"33" => -- Force HDMI 1 to 1024
hdmi_cmd_i(1) <= '1';
uvc_rst_i <= '1';
when others =>
end case;
when X"53" | X"73" => -- S Source Selector
case cmd is -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
when X"53" | X"73" => -- Status
status(2) <= '1';
when X"55" | X"75" => -- U button force source to HDMI0
if rdy_H(0) = '1' then
selector_cmd_i(1 downto 0) <= "00";
uvc_rst_i <= '1';
end if;
when X"4c" | X"6c" => -- L button force source to HDMI1
if rdy_H(1) = '1' then
selector_cmd_i(1 downto 0) <= "01";
uvc_rst_i <= '1';
end if;
when X"52" | X"72" => -- V button force source to VGA
-- selector_cmd_i(1 downto 0) <= "10";
when X"44" | X"64" => -- D button force source to test pattern
selector_cmd_i(1 downto 0) <= "11";
uvc_rst_i <= '1';
when X"47" | X"67" => -- Froce Gray
selector_cmd_i(2) <= '0';
when X"43" | X"63" => -- Froce Color
selector_cmd_i(2) <= '1';
when X"49" | X"69" => -- Invert Color
selector_cmd_i(3) <= not selector_cmd_i(3);
when X"48" | X"68" => -- Heart Beat On/Off
HB_on_i <= not HB_on_i;
when others =>
end case;
-- RGB (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
when X"52" | X"72" => -- Red
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(12) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(12) <= '0';
when X"30" =>
selector_cmd_i(9 downto 8) <= "00";
when X"31" =>
selector_cmd_i(9 downto 8) <= "01";
when X"32" =>
selector_cmd_i(9 downto 8) <= "10";
when X"33" =>
selector_cmd_i(9 downto 8) <= "11";
when others =>
end case;
when X"47" | X"67" => -- Green (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(11) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(11) <= '0';
when X"30" =>
selector_cmd_i(7 downto 6) <= "00";
when X"31" =>
selector_cmd_i(7 downto 6) <= "01";
when X"32" =>
selector_cmd_i(7 downto 6) <= "10";
when X"33" =>
selector_cmd_i(7 downto 6) <= "11";
when others =>
end case;
when X"42" | X"62" => -- Blue
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(10) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(10) <= '0';
when X"30" =>
selector_cmd_i(5 downto 4) <= "00";
when X"31" =>
selector_cmd_i(5 downto 4) <= "01";
when X"32" =>
selector_cmd_i(5 downto 4) <= "10";
when X"33" =>
selector_cmd_i(5 downto 4) <= "11";
when others =>
end case;
when X"44" | X"64" => --Debug
case cmd is
when X"53" | X"73" => --Status
status(4) <= '1';
when others =>
end case;
when others =>
end case; -- case add
end if; -- cmd_en
end if; -- clk
end process;
uart_rd <= uart_rd_s;
uart_ctrl : process(uart_clk, uart_rx_empty, empty_s)
begin
if rst = '1' then
uart_rd_s <= '0';
elsif rising_edge(uart_clk) then
empty_s <= uart_rx_empty;
end if;
if empty_s = '1' and uart_rx_empty = '0' then
uart_rd_s <= '1';
end if;
if empty_s = uart_rx_empty then
uart_rd_s <= '0';
end if;
end process;
fifo_mux: process(usb_or_uart, uart_rd_s, cmd_en, uart_din, cmd_byte, uart_clk, ifclk)
begin
if usb_or_uart = '0' then
fifo_din <= cmd_byte;
fifo_wr <= cmd_en;
fifo_clk <= ifclk;
else
fifo_din <= uart_din;
fifo_wr <= uart_rd_s;
fifo_clk <= uart_clk;
end if;
end process;
cmd <= dout(7 downto 0);
add <= dout(15 downto 8);
cmdfifo_comp : cmdfifo
PORT MAP (
rst => rst,
wr_clk => fifo_clk,
rd_clk => clk,
din => fifo_din,
wr_en => fifo_wr,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
END ARCHITECTURE;
| bsd-2-clause | b678bdbcd6af63a5346b62af19f656fa | 0.544851 | 2.715877 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_Xilinx_Port/sha256_pipeline.vhd | 4 | 3,834 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:22:06 05/28/2011
-- Design Name:
-- Module Name: sha256_pipeline - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_pipeline is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
input : in STD_LOGIC_VECTOR (511 downto 0);
hash : out STD_LOGIC_VECTOR (255 downto 0));
end sha256_pipeline;
architecture Behavioral of sha256_pipeline is
COMPONENT sha256_transform
PORT(
clk : IN std_logic;
w_in : IN std_logic_vector(511 downto 0);
s_in : IN std_logic_vector(255 downto 0);
w_out : OUT std_logic_vector(511 downto 0);
s_out : OUT std_logic_vector(255 downto 0);
k : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
type k_array is array(integer range 0 to 63) of std_logic_vector(31 downto 0);
constant K : k_array := (
x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2"
);
type w_array is array(integer range 0 to 64) of std_logic_vector(511 downto 0);
signal w : w_array;
type s_array is array(integer range 0 to 64) of std_logic_vector(255 downto 0);
signal s : s_array;
begin
w(0) <= input;
s(0) <= state;
hash(255 downto 224) <= state(255 downto 224) + s(2 ** DEPTH)(255 downto 224);
hash(223 downto 192) <= state(223 downto 192) + s(2 ** DEPTH)(223 downto 192);
hash(191 downto 160) <= state(191 downto 160) + s(2 ** DEPTH)(191 downto 160);
hash(159 downto 128) <= state(159 downto 128) + s(2 ** DEPTH)(159 downto 128);
hash(127 downto 96) <= state(127 downto 96) + s(2 ** DEPTH)(127 downto 96);
hash(95 downto 64) <= state(95 downto 64) + s(2 ** DEPTH)(95 downto 64);
hash(63 downto 32) <= state(63 downto 32) + s(2 ** DEPTH)(63 downto 32);
hash(31 downto 0) <= state(31 downto 0) + s(2 ** DEPTH)(31 downto 0);
rounds: for i in 0 to 2 ** DEPTH - 1 generate
signal round_k : std_logic_vector(31 downto 0);
signal round_w : std_logic_vector(511 downto 0);
signal round_s : std_logic_vector(255 downto 0);
begin
round_k <= K(i * 2 ** (6 - DEPTH) + conv_integer(step));
round_w <= w(i) when step = "000000" else w(i + 1);
round_s <= s(i) when step = "000000" else s(i + 1);
transform: sha256_transform
port map (
clk => clk,
w_in => round_w,
w_out => w(i + 1),
s_in => round_s,
s_out => s(i + 1),
k => round_k
);
end generate;
end Behavioral;
| gpl-3.0 | 381de317eb6ded63b0ab68188ce6c088 | 0.616328 | 2.64779 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_fwft.vhd | 9 | 38,295 | `protect begin_protected
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| gpl-3.0 | 38c362e5668cb0253ce2a9506541e1b2 | 0.948427 | 1.841726 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/channel_init_sm.vhd | 4 | 15,099 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/21 23:26:37 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: channel_init_sm_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.6 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- CHANNEL_INIT_SM
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: the CHANNEL_INIT_SM module is a state machine for managing channel
-- bonding and verification.
--
-- The channel init state machine is reset until the lane up signals
-- of all the lanes that constitute the channel are asserted. It then
-- requests channel bonding until the lanes have been bonded and
-- checks to make sure the bonding was successful. Channel bonding is
-- skipped if there is only one lane in the channel. If bonding is
-- unsuccessful, the lanes are reset.
--
-- After the bonding phase is complete, the state machine sends
-- verification sequences through the channel until it is clear that
-- the channel is ready to be used. If verification is successful,
-- the CHANNEL_UP signal is asserted. If it is unsuccessful, the
-- lanes are reset.
--
-- After CHANNEL_UP goes high, the state machine is quiescent, and will
-- reset only if one of the lanes goes down, a hard error is detected, or
-- a general reset is requested.
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use WORK.AURORA.all;
-- synthesis translate_off
library UNISIM;
use UNISIM.all;
-- synthesis translate_on
entity CHANNEL_INIT_SM is
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
-- Idle and Verification Sequence Generator Interface
DID_VER : in std_logic;
GEN_VER : out std_logic;
-- Channel Init State Machine Interface
RESET_CHANNEL : in std_logic
);
end CHANNEL_INIT_SM;
architecture RTL of CHANNEL_INIT_SM is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal EN_CHAN_SYNC_Buffer : std_logic;
signal RESET_LANES_Buffer : std_logic;
signal CHANNEL_UP_Buffer : std_logic;
signal START_RX_Buffer : std_logic;
signal GEN_VER_Buffer : std_logic;
-- Internal Register Declarations --
signal free_count_done_r : std_logic;
signal extend_watchdogs_n_r : std_logic;
signal verify_watchdog_r : std_logic_vector(0 to 15);
signal all_lanes_v_r : std_logic;
signal got_first_v_r : std_logic;
signal v_count_r : std_logic_vector(0 to 31);
signal bad_v_r : std_logic;
signal rxver_count_r : std_logic_vector(0 to 2);
signal txver_count_r : std_logic_vector(0 to 7);
-- State registers
signal wait_for_lane_up_r : std_logic;
signal verify_r : std_logic;
signal ready_r : std_logic;
-- Wire Declarations --
signal free_count_1_r : std_logic;
signal free_count_2_r : std_logic;
signal extend_watchdogs_1_r : std_logic;
signal extend_watchdogs_2_r : std_logic;
signal extend_watchdogs_n_c : std_logic;
signal insert_ver_c : std_logic;
signal verify_watchdog_done_r : std_logic;
signal rxver_3d_done_r : std_logic;
signal txver_8d_done_r : std_logic;
signal reset_lanes_c : std_logic;
-- Next state signals
signal next_verify_c : std_logic;
signal next_ready_c : std_logic;
-- VHDL utility signals
signal tied_to_vcc : std_logic;
signal tied_to_gnd : std_logic;
-- Component Declarations
component SRL16
generic (INIT : bit_vector := X"0000");
port (
Q : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
CLK : in std_ulogic;
D : in std_ulogic
);
end component;
component SRL16E
generic (INIT : bit_vector := X"0000");
port (
Q : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
D : in std_ulogic
);
end component;
component FD
generic (INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic
);
end component;
begin
EN_CHAN_SYNC <= EN_CHAN_SYNC_Buffer;
RESET_LANES <= RESET_LANES_Buffer;
CHANNEL_UP <= CHANNEL_UP_Buffer;
START_RX <= START_RX_Buffer;
GEN_VER <= GEN_VER_Buffer;
tied_to_vcc <= '1';
tied_to_gnd <= '0';
-- Main Body of Code --
-- Main state machine for bonding and verification --
-- State registers
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if ((RESET or RESET_CHANNEL) = '1') then
wait_for_lane_up_r <= '1' after DLY;
verify_r <= '0' after DLY;
ready_r <= '0' after DLY;
else
wait_for_lane_up_r <= '0' after DLY;
verify_r <= next_verify_c after DLY;
ready_r <= next_ready_c after DLY;
end if;
end if;
end process;
-- Next state logic
next_verify_c <= wait_for_lane_up_r or
(verify_r and (not rxver_3d_done_r or not txver_8d_done_r));
next_ready_c <= ((verify_r and txver_8d_done_r) and rxver_3d_done_r) or
ready_r;
-- Output Logic
-- Channel up is high as long as the Global Logic is in the ready state.
CHANNEL_UP_Buffer <= ready_r;
-- Turn the receive engine on as soon as all the lanes are up.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (RESET = '1') then
START_RX_Buffer <= '0' after DLY;
else
START_RX_Buffer <= not wait_for_lane_up_r after DLY;
end if;
end if;
end process;
-- Generate the Verification sequence when in the verify state.
GEN_VER_Buffer <= verify_r;
-- Channel Reset --
-- Some problems during channel bonding and verification require the lanes to
-- be reset. When this happens, we assert the Reset Lanes signal, which gets
-- sent to all Aurora Lanes. When the Aurora Lanes reset, their LANE_UP signals
-- go down. This causes the Channel Error Detector to assert the Reset Channel
-- signal.
reset_lanes_c <= (verify_r and verify_watchdog_done_r) or
(verify_r and bad_v_r and not rxver_3d_done_r) or
(RESET_CHANNEL and not wait_for_lane_up_r) or
RESET;
reset_lanes_flop_i : FD
generic map (INIT => '1')
port map (
D => reset_lanes_c,
C => USER_CLK,
Q => RESET_LANES_Buffer
);
-- Watchdog timers --
-- We create a free counter out of SRLs to count large values without excessive cost.
free_count_1_i : SRL16
generic map (INIT => X"8000")
port map (
Q => free_count_1_r,
A0 => tied_to_vcc,
A1 => tied_to_vcc,
A2 => tied_to_vcc,
A3 => tied_to_vcc,
CLK => USER_CLK,
D => free_count_1_r
);
free_count_2_i : SRL16E
generic map (INIT => X"8000")
port map (
Q => free_count_2_r,
A0 => tied_to_vcc,
A1 => tied_to_vcc,
A2 => tied_to_vcc,
A3 => tied_to_vcc,
CLK => USER_CLK,
CE => free_count_1_r,
D => free_count_2_r
);
-- The watchdog extention SRLs are used to multiply the free count by 32
extend_watchdogs_1_i :SRL16E
port map
(
Q => extend_watchdogs_1_r,
A0 => tied_to_vcc,
A1 => tied_to_vcc,
A2 => tied_to_vcc,
A3 => tied_to_vcc,
CLK => USER_CLK,
CE => free_count_1_r,
D => extend_watchdogs_n_c
);
extend_watchdogs_2_i :SRL16E
port map
(
Q => extend_watchdogs_2_r,
A0 => tied_to_vcc,
A1 => tied_to_vcc,
A2 => tied_to_vcc,
A3 => tied_to_vcc,
CLK => USER_CLK,
CE => free_count_1_r,
D => extend_watchdogs_1_r
);
extend_watchdogs_n_c <= not extend_watchdogs_2_r;
process (USER_CLK)
begin
if( USER_CLK'event and USER_CLK='1') then
extend_watchdogs_n_r <= extend_watchdogs_n_c;
end if;
end process;
-- Finally we have logic hat registers a pulse when both the inner and the
-- outer SRLs have a bit in their last position. This should map to carry logic
-- and a register.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if(EXTEND_WATCHDOGS) then
free_count_done_r <= extend_watchdogs_2_r and extend_watchdogs_n_r after DLY;
else
free_count_done_r <= free_count_2_r and free_count_1_r after DLY;
end if;
end if;
end process;
-- We use the free running count as a CE for the verify watchdog. The
-- count runs continuously so the watchdog will vary between a count of 4096
-- and 3840 cycles - acceptable for this application.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if ((free_count_done_r or not verify_r) = '1') then
verify_watchdog_r <= verify_r & verify_watchdog_r(0 to 14) after DLY;
end if;
end if;
end process;
verify_watchdog_done_r <= verify_watchdog_r(15);
-- Channel Bonding --
-- We don't use channel bonding for the single lane case, so we tie the
-- EN_CHAN_SYNC signal low.
EN_CHAN_SYNC_Buffer <= '0';
-- Verification --
-- Vs need to appear on all lanes simultaneously.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
all_lanes_v_r <= GOT_V after DLY;
end if;
end process;
-- Vs need to be decoded by the aurora lane and then checked by the
-- Global logic. They must appear periodically.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (verify_r = '0') then
got_first_v_r <= '0' after DLY;
else
if (all_lanes_v_r = '1') then
got_first_v_r <= '1' after DLY;
end if;
end if;
end if;
end process;
insert_ver_c <= (all_lanes_v_r and not got_first_v_r) or (v_count_r(31) and verify_r);
-- Shift register for measuring the time between V counts.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
v_count_r <= insert_ver_c & v_count_r(0 to 30) after DLY;
end if;
end process;
-- Assert bad_v_r if a V does not arrive when expected.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
bad_v_r <= (v_count_r(31) xor all_lanes_v_r) and got_first_v_r after DLY;
end if;
end process;
-- Count the number of Ver sequences received. You're done after you receive four.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (((v_count_r(31) and all_lanes_v_r) or not verify_r) = '1') then
rxver_count_r <= verify_r & rxver_count_r(0 to 1) after DLY;
end if;
end if;
end process;
rxver_3d_done_r <= rxver_count_r(2);
-- Count the number of Ver sequences transmitted. You're done after you send eight.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if ((DID_VER or not verify_r) = '1') then
txver_count_r <= verify_r & txver_count_r(0 to 6) after DLY;
end if;
end if;
end process;
txver_8d_done_r <= txver_count_r(7);
end RTL;
| bsd-2-clause | f28e9a3eb111fc4d2493833f0726cd3c | 0.523743 | 3.790861 | false | false | false | false |
ymei/TMSPlane | Firmware/src/control_interface.vhd | 2 | 15,627 | --------------------------------------------------------------------------------
--! @file control_interface.vhd
--! @brief Control Interface
--! \verbatim
--! Author : JS <[email protected]>
--! Company : University of Texas at Austin
--! Created : 2013-06-12
--! Last update: 2016-12-25
--! Description: Read words from command FIFO and interpret
--! This defines some example interfaces at different addresses:
--! Address 32 - 63: 16bit Configuration registers
--! These registers can be written and read.
--! Could be used to define operations parameters
--! Address 11: 16bit Pulse REGISTER
--! This register generates a pulse at the bits
--! set to 1 that is 3 clocks wide
--! Could be used to start some action, e.g. jtag
--! Address 0 - 10: 16bit Status registers
--! These are read-only.
--! Can be used to read the status of some external
--! device, .e.g an ADC, or input pins.
--! Address 16 - 20: 32bit memory interface
--! The idea is to write an address into 17 (LSB)
--! and 18 (MSB)
--! Then write the LSB16 into 19, and finally
--! the MSB16 into 20. On write to 20, the 32bit
--! data in 19 and 20 is written to the memory, AND
--! the address is auto-incremented, so that the NEXT
--! write seuqence doesn't need to re-write the address.
--! A Read on 20 reads the current address and returns
--! a 32bit data word into the FIFO, then increases
--! the memory. This read is repeated n times, where
--! "n" is the 16bit value at address 16.
--! Address 25: This address initiates a read from the DATA_FIFO
--! The value written `n' indicates the number of
--! words to copy from the DATA_FIFO to the FIFO.
--! Write `n' will result in n+1 words to be transferred.
--! Will wait indefinitely for all words to be transferred
--! should FIFOs stay in empty/full state.
--!
--! Revisions :
--! Date Version Author Description
--! 2013-06-12 1.0 jschamba Created
--! 2013-10-21 1.1 thorsten changed memory address space to 32 bit
--! added an interface to read a data fifo
--! 2016-12-25 ymei Adapt to FWFT FIFO
--! \endverbatim
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Entity Declaration
ENTITY control_interface IS
PORT (
RESET : IN std_logic;
CLK : IN std_logic; -- system clock
-- From FPGA to PC
FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); -- interface fifo data output port
FIFO_EMPTY : OUT std_logic; -- interface fifo "emtpy" signal
FIFO_RDREQ : IN std_logic; -- interface fifo read request
FIFO_RDCLK : IN std_logic; -- interface fifo read clock
-- From PC to FPGA, FWFT
CMD_FIFO_Q : IN std_logic_vector(35 DOWNTO 0); -- interface command fifo data out port
CMD_FIFO_EMPTY : IN std_logic; -- interface command fifo "emtpy" signal
CMD_FIFO_RDREQ : OUT std_logic; -- interface command fifo read request
-- Digital I/O
CONFIG_REG : OUT std_logic_vector(511 DOWNTO 0); -- thirtytwo 16bit registers
PULSE_REG : OUT std_logic_vector(15 DOWNTO 0); -- 16bit pulse register
STATUS_REG : IN std_logic_vector(175 DOWNTO 0); -- eleven 16bit registers
-- Memory interface
MEM_WE : OUT std_logic; -- memory write enable
MEM_ADDR : OUT std_logic_vector(31 DOWNTO 0);
MEM_DIN : OUT std_logic_vector(31 DOWNTO 0); -- memory data input
MEM_DOUT : IN std_logic_vector(31 DOWNTO 0); -- memory data output
-- Data FIFO interface, FWFT
DATA_FIFO_Q : IN std_logic_vector(31 DOWNTO 0);
DATA_FIFO_EMPTY : IN std_logic;
DATA_FIFO_RDREQ : OUT std_logic;
DATA_FIFO_RDCLK : OUT std_logic
);
END control_interface;
-- Architecture body
ARCHITECTURE a OF control_interface IS
COMPONENT fifo36x512
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(35 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(35 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
-- signals for FIFO
SIGNAL bMemNotReg : integer;
CONSTANT SEL_REG : integer := 0;
CONSTANT SEL_MEM : integer := 1;
CONSTANT SEL_FIFO : integer := 2;
SIGNAL sFifoD : std_logic_vector(35 DOWNTO 0);
SIGNAL sFifoFull : std_logic;
SIGNAL sFifoWren : std_logic;
SIGNAL sFifoWrreq : std_logic;
SIGNAL sFifoRst : std_logic;
SIGNAL sFifoClk : std_logic;
-- signals for single-port RAM
SIGNAL sWea : std_logic;
SIGNAL sAddrA : unsigned(31 DOWNTO 0);
SIGNAL sDinA : std_logic_vector(31 DOWNTO 0);
SIGNAL sDoutA : std_logic_vector(31 DOWNTO 0);
SIGNAL sDinReg : std_logic_vector(15 DOWNTO 0);
SIGNAL sMemioCnt : std_logic_vector(15 DOWNTO 0);
SIGNAL sMemLatch : std_logic_vector(31 DOWNTO 0);
-- Configuration registers: 8 x 16bit
SIGNAL sConfigReg : std_logic_vector(511 DOWNTO 0);
SIGNAL sPulseReg : std_logic_vector(15 DOWNTO 0);
SIGNAL sRegOut : std_logic_vector(15 DOWNTO 0);
-- signals for FIFO read
-- to read data from a FIFO
SIGNAL sDataFifoCount : std_logic_vector(15 DOWNTO 0);
-- State machine variable
TYPE cmdState_t IS (
INIT,
WAIT_CMD,
GET_CMD,
INTERPRET_CMD,
MEM_ADV,
MEM_RD_CNT,
PULSE_DELAY,
FIFO_ADV
);
SIGNAL cmdState : cmdState_t;
BEGIN
CONFIG_REG <= sConfigReg;
PULSE_REG <= sPulseReg;
MEM_WE <= sWea;
MEM_ADDR <= std_logic_vector(sAddrA);
MEM_DIN <= sDinA;
sDoutA <= MEM_DOUT;
-- memory input
sDinA(15 DOWNTO 0) <= sDinReg;
-- When FWFT FIFO is used, high 16 bits have to be registered by a cycled.
PROCESS (CLK) IS
BEGIN
IF rising_edge(CLK) THEN
sDinA(31 DOWNTO 16) <= CMD_FIFO_Q(15 DOWNTO 0);
END IF;
END PROCESS;
-- data fifo
DATA_FIFO_RDCLK <= CLK;
-- data/event FIFO
sFifoRst <= RESET;
sFifoClk <= CLK;
data_fifo : fifo36x512
PORT MAP (
rst => sFifoRst,
wr_clk => sFifoClk,
rd_clk => FIFO_RDCLK,
din => sFifoD,
wr_en => sFifoWren,
rd_en => FIFO_RDREQ,
dout => FIFO_Q,
full => sFifoFull,
empty => FIFO_EMPTY
);
sFifoD(35 DOWNTO 32) <= (OTHERS => '0'); -- these bits not used
sFifoD(31 DOWNTO 0) <= MEM_DOUT WHEN bMemNotReg = SEL_MEM ELSE
DATA_FIFO_Q WHEN bMemNotReg = SEL_FIFO ELSE
x"0000" & sRegOut;
sFifoWren <= (NOT DATA_FIFO_EMPTY) WHEN bMemNotReg = SEL_FIFO
ELSE sFifoWrreq;
DATA_FIFO_RDREQ <= (NOT sFifoFull) WHEN bMemNotReg = SEL_FIFO
ELSE '0';
cmdIF_inst : PROCESS (CLK, RESET) IS
VARIABLE counterV : integer RANGE 0 TO 65535 := 0;
VARIABLE address_i : integer RANGE 0 TO 4095 := 0;
VARIABLE counterFIFO : integer RANGE 0 TO 65535 := 0;
BEGIN
IF RESET = '1' THEN
counterV := 0;
cmdState <= INIT;
CMD_FIFO_RDREQ <= '0';
sConfigReg <= (OTHERS => '0');
sPulseReg <= (OTHERS => '0');
sDinReg <= (OTHERS => '0');
sMemioCnt <= (OTHERS => '0');
sWea <= '0';
sAddrA <= (OTHERS => '0');
bMemNotReg <= SEL_REG;
ELSIF rising_edge(CLK) THEN
-- defaults:
CMD_FIFO_RDREQ <= '0';
sFifoWrreq <= '0';
sWea <= '0';
sRegOut <= (OTHERS => '0');
CASE cmdState IS
-- //// initialize registers to some sensible values
WHEN INIT =>
-- currently all 0
sConfigReg <= (OTHERS => '0');
sPulseReg <= (OTHERS => '0');
sAddrA <= (OTHERS => '0');
-- at least 1 memory read
sMemioCnt <= x"0001";
cmdState <= WAIT_CMD;
-- //// Wait for CMD_FIFO words
WHEN WAIT_CMD =>
bMemNotReg <= SEL_REG; -- output registers
sPulseReg <= (OTHERS => '0'); -- reset pulse REGISTER
-- wait for FIFO not empty
IF CMD_FIFO_EMPTY = '0' THEN
CMD_FIFO_RDREQ <= '1';
cmdState <= INTERPRET_CMD; -- GET_CMD;
END IF;
-- //// one wait state to get next CMD_FIFO word
-- When FWFT FIFO is used, this state should be skipped.
-- WHEN GET_CMD =>
-- cmdState <= INTERPRET_CMD;
-- //// Now interpret the current CMD_FIFO output
WHEN INTERPRET_CMD =>
---------------------------------------------------------------------
-- CMD_FIFO_Q format:
-- Q(31) : READ/NOT_WRITE
-- Q(30:28) : not used
-- Q(27:16) : ADDRESS
-- Q(15:0) : DATA
---------------------------------------------------------------------
--address_i := conv_integer(unsigned(CMD_FIFO_Q(27 DOWNTO 16)));
address_i := to_integer(unsigned(CMD_FIFO_Q(27 DOWNTO 16)));
IF CMD_FIFO_Q(31) = '1' THEN
-- //// a READ transaction ////////
CASE address_i IS
WHEN 32 TO 63 => -- CONFIG_REG
sRegOut <= sConfigReg((address_i-32)*16+15 DOWNTO
(address_i-32)*16);
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 0 TO 10 => -- STATUS_REG
sRegOut <= STATUS_REG(address_i*16+15 DOWNTO address_i*16);
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 16 => -- memory count REGISTER
sRegOut <= sMemioCnt;
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 17 => -- memory address LSB REGISTER
sRegOut <= std_logic_vector(sAddrA (15 DOWNTO 0));
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 18 => -- memory address MSB REGISTER
sRegOut <= std_logic_vector(sAddrA (31 DOWNTO 16));
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
WHEN 20 => -- read sMemioCnt 32bit memory words
-- reads 32bit memory words starting at the current
-- address sAddrA
counterV := to_integer(unsigned(sMemioCnt));
bMemNotReg <= SEL_MEM; -- switch FIFO input to memory output
IF sFifoFull = '0' THEN
sFifoWrreq <= '1'; -- latch current memory output
sAddrA <= sAddrA + 1; -- and advance the address
cmdState <= MEM_RD_CNT;
END IF;
WHEN OTHERS => -- bad address, return FFFF
sRegOut <= (OTHERS => '1');
sFifoWrreq <= '1';
cmdState <= WAIT_CMD;
END CASE;
ELSE
-- //// a WRITE transaction ////////
CASE address_i IS
WHEN 32 TO 63 => -- CONFIG_REG
sConfigReg((address_i-32)*16+15 DOWNTO
(address_i-32)*16) <= CMD_FIFO_Q(15 DOWNTO 0);
cmdState <= WAIT_CMD;
WHEN 11 => -- PULSE_REG
sPulseReg <= CMD_FIFO_Q(15 DOWNTO 0);
counterV := 2; -- 60ns
cmdState <= PULSE_DELAY;
WHEN 16 => -- memory count REGISTER
sMemioCnt <= CMD_FIFO_Q(15 DOWNTO 0);
cmdState <= WAIT_CMD;
WHEN 17 => -- memory address LSB REGISTER
sAddrA (15 DOWNTO 0) <= unsigned(CMD_FIFO_Q(15 DOWNTO 0));
cmdState <= WAIT_CMD;
WHEN 18 => -- memory address MSB REGISTER
--sAddrA <= CMD_FIFO_Q(15 DOWNTO 0);
sAddrA (31 DOWNTO 16) <= unsigned(CMD_FIFO_Q(15 DOWNTO 0));
cmdState <= WAIT_CMD;
WHEN 19 => -- memory LS16B
sDinReg <= CMD_FIFO_Q(15 DOWNTO 0);
cmdState <= WAIT_CMD;
WHEN 20 => -- memory MS16B
-- raise WriteEnable for one clock, which clocks IN
-- register 18 as LS16B and the data content of
-- the CMD_FIFO word as MS16B
sWea <= '1';
cmdState <= MEM_ADV;
WHEN 25 => -- Data Fifo read count
counterFIFO := to_integer(unsigned(CMD_FIFO_Q(15 DOWNTO 0)));
bMemNotReg <= SEL_FIFO;
cmdState <= FIFO_ADV;
WHEN OTHERS => -- bad address, do nothing
cmdState <= WAIT_CMD;
END CASE;
END IF;
-- //// advance memory address
WHEN MEM_ADV =>
sAddrA <= sAddrA + 1;
cmdState <= WAIT_CMD;
-- //// read sMemioCnt memory addresses
WHEN MEM_RD_CNT =>
counterV := counterV - 1;
-- wait for FIFO not FULL
IF (counterV = 0) THEN
-- Done
cmdState <= WAIT_CMD;
ELSIF sFifoFull = '0' THEN
-- latch current memory output
sFifoWrreq <= '1';
-- and advance address
sAddrA <= sAddrA + 1;
cmdState <= MEM_RD_CNT;
ELSE
-- FIFO Full:
-- go back to previous count and wait for FIFO not full
counterV := counterV + 1;
cmdState <= MEM_RD_CNT;
END IF;
-- //// delay two clocks to keep pulse high (total 3 clocks)
WHEN PULSE_DELAY =>
counterV := counterV - 1;
IF (counterV = 0) THEN
cmdState <= WAIT_CMD;
END IF;
-- //// Data FIFO read
WHEN FIFO_ADV =>
-- read data fifo, write reads to output fifo
-- exit when enough words were transferred
bMemNotReg <= SEL_FIFO;
cmdState <= FIFO_ADV;
IF (DATA_FIFO_EMPTY = '0') AND (sFifoFull = '0') THEN
IF counterFIFO = 0 THEN
-- we are done.
bMemNotReg <= SEL_REG;
cmdState <= WAIT_CMD;
ELSE
-- reduce the counter.
counterFIFO := counterFIFO - 1;
END IF;
END IF;
-- //// shouldn't happen
WHEN OTHERS =>
cmdState <= WAIT_CMD;
END CASE;
END IF;
END PROCESS cmdIF_inst;
END a;
| bsd-3-clause | f4e4fe6360f0fcc2b59322c66a458c86 | 0.490817 | 4.147293 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_StratixIV_OrphanedGland/sha256/rtl/sha256_pc.vhd | 4 | 9,814 | --
-- Copyright (c) 2011 OrphanedGland ([email protected])
-- Send donations to : 1PioyqqFWXbKryxysGqoq5XAu9MTRANCEP
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- SHA256 core using H+K+W precalculation technique
-- Inspired by fpgaminer's sha256_transform.v
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end entity sha256_pc;
architecture sha256_pc_rtl of sha256_pc is
alias slv is std_logic_vector;
subtype msg is unsigned(511 downto 0);
subtype word is unsigned(31 downto 0);
function e0(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(1 downto 0) & x(31 downto 2)) xor (x(12 downto 0) & x(31 downto 13)) xor (x(21 downto 0) & x(31 downto 22));
end e0;
function e1(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(5 downto 0) & x(31 downto 6)) xor (x(10 downto 0) & x(31 downto 11)) xor (x(24 downto 0) & x(31 downto 25));
end e1;
function s0(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 29) := x(6 downto 4) xor x(17 downto 15);
y(28 downto 0) := (x(3 downto 0) & x(31 downto 7)) xor (x(14 downto 0) & x(31 downto 18)) xor x(31 downto 3);
return y;
end s0;
function s1(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 22) := x(16 downto 7) xor x(18 downto 9);
y(21 downto 0) := (x(6 downto 0) & x(31 downto 17)) xor (x(8 downto 0) & x(31 downto 19)) xor x(31 downto 10);
return y;
end s1;
function ch(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (not(x) and z);
end ch;
function maj(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (x and z) xor (y and z);
end maj;
type msg_array is array(0 to 63) of msg;
type word_array is array(0 to 63) of word;
type hash_array is array(0 to 7) of word;
constant k : word_array := ( X"428a2f98", X"71374491", X"b5c0fbcf", X"e9b5dba5", X"3956c25b", X"59f111f1", X"923f82a4", X"ab1c5ed5",
X"d807aa98", X"12835b01", X"243185be", X"550c7dc3", X"72be5d74", X"80deb1fe", X"9bdc06a7", X"c19bf174",
X"e49b69c1", X"efbe4786", X"0fc19dc6", X"240ca1cc", X"2de92c6f", X"4a7484aa", X"5cb0a9dc", X"76f988da",
X"983e5152", X"a831c66d", X"b00327c8", X"bf597fc7", X"c6e00bf3", X"d5a79147", X"06ca6351", X"14292967",
X"27b70a85", X"2e1b2138", X"4d2c6dfc", X"53380d13", X"650a7354", X"766a0abb", X"81c2c92e", X"92722c85",
X"a2bfe8a1", X"a81a664b", X"c24b8b70", X"c76c51a3", X"d192e819", X"d6990624", X"f40e3585", X"106aa070",
X"19a4c116", X"1e376c08", X"2748774c", X"34b0bcb5", X"391c0cb3", X"4ed8aa4a", X"5b9cca4f", X"682e6ff3",
X"748f82ee", X"78a5636f", X"84c87814", X"8cc70208", X"90befffa", X"a4506ceb", X"bef9a3f7", X"c67178f2" );
constant h_default : hash_array := ( X"6a09e667", X"bb67ae85", X"3c6ef372", X"a54ff53a", X"510e527f", X"9b05688c", X"1f83d9ab", X"5be0cd19" );
signal w : msg_array;
signal new_w : word_array;
signal t1 : word_array;
signal t2 : word_array;
signal a : word_array;
signal b : word_array;
signal c : word_array;
signal d : word_array;
signal e : word_array;
signal f : word_array;
signal g : word_array;
signal h : word_array;
signal hkw_precalc : word_array;
signal hash : hash_array;
signal h_init : hash_array;
signal q_w : msg_array;
signal q_a : word_array;
signal q_b : word_array;
signal q_c : word_array;
signal q_d : word_array;
signal q_e : word_array;
signal q_f : word_array;
signal q_g : word_array;
signal q_h : word_array;
signal q_hkw_precalc : word_array;
signal q_hash : hash_array;
signal q_msg : msg;
begin
output_mapping: for i in 0 to 7 generate
--digest((i+1)*32-1 downto i*32) <= slv(q_hash(7-i));
digest((i+1)*32-1 downto i*32) <= slv(q_hash(i));
end generate output_mapping;
default_h_gen: if default_h = true generate
h_init <= h_default;
end generate default_h_gen;
h_gen: if default_h = false generate
h_array_gen: for i in 0 to 7 generate
h_init(i) <= unsigned(h_in((i+1)*32-1 downto i*32));
end generate h_array_gen;
end generate h_gen;
hkw_precalc(0) <= h_init(7) + k(0) + unsigned(msg_in(31 downto 0));
hash_pipeline: for i in 0 to 63 generate
first_stage: if i = 0 generate
t1_no_precalc_gen: if default_h = true generate
-- no point precalculating when constants are used, so save a clock cycle
t1(i) <= h_init(7) + e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + k(i) + w(i)(31 downto 0);
w(i) <= unsigned(msg_in);
end generate t1_no_precalc_gen;
t1_precalc_gen: if default_h = false generate
t1(i) <= e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6)) + q_hkw_precalc(i);
w(i) <= q_msg;
end generate t1_precalc_gen;
t2(i) <= e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
a(i) <= t1(i) + t2(i);
b(i) <= h_init(0);
c(i) <= h_init(1);
d(i) <= h_init(2);
e(i) <= h_init(3) + t1(i);
f(i) <= h_init(4);
g(i) <= h_init(5);
h(i) <= h_init(6);
hkw_precalc(i+1) <= h_init(6) + k(i+1) + w(i)(63 downto 32);
end generate first_stage;
other_stages: if i /= 0 generate
t1(i) <= e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1)) + q_hkw_precalc(i);
t2(i) <= e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= t1(i) + t2(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= q_d(i-1) + t1(i);
f(i) <= q_e(i-1);
g(i) <= q_f(i-1);
h(i) <= q_g(i-1);
precalc: if i /= 63 generate
hkw_precalc(i+1) <= q_g(i-1) + k(i+1) + w(i)(63 downto 32);
end generate precalc;
end generate other_stages;
end generate hash_pipeline;
hash(0) <= q_a(63) + h_init(0);
hash(1) <= q_b(63) + h_init(1);
hash(2) <= q_c(63) + h_init(2);
hash(3) <= q_d(63) + h_init(3);
hash(4) <= q_e(63) + h_init(4);
hash(5) <= q_f(63) + h_init(5);
hash(6) <= q_g(63) + h_init(6);
hash(7) <= q_h(63) + h_init(7);
registers : process(clk, reset) is
begin
if reset = '1' then
null;
elsif rising_edge(clk) then
q_msg <= unsigned(msg_in);
q_w <= w;
q_a <= a;
q_b <= b;
q_c <= c;
q_d <= d;
q_e <= e;
q_f <= f;
q_g <= g;
q_h <= h;
q_hkw_precalc <= hkw_precalc;
q_hash <= hash;
end if;
end process registers;
end architecture sha256_pc_rtl;
| gpl-3.0 | 1c2c8d5df729c05b924f0bb50bfd3efb | 0.471877 | 3.128467 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_write_fsm.vhd | 9 | 61,290 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | cd15b80340b5defc1a0a0f6ce750aaed | 0.950661 | 1.818155 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_cast_GN7IAAYCSZ.vhd | 8 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN7IAAYCSZ is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(7 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN7IAAYCSZ is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 8 + 1 ,
width_inr=> 16,
width_outl=> 8,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; | mit | cb1cd2620fd559c63a460abf658a0729 | 0.648803 | 3.045139 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_v8_0_defaults.vhd | 9 | 32,415 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| gpl-3.0 | f4578beb3357de8efb81e6133cbe8da3 | 0.945457 | 1.829805 | false | false | false | false |
ymei/TMSPlane | Firmware/test_bench/i2c/i2c_write_regmap_tb.vhd | 1 | 3,834 | --------------------------------------------------------------------------------
--! @file i2c_write_regmap_tb
--! @brief testbench of i2c_write_regmap
--! @author Yuan Mei, 20170819
--!
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY i2c_write_regmap_tb IS
END i2c_write_regmap_tb;
ARCHITECTURE behavior OF i2c_write_regmap_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT i2c_write_regmap
GENERIC (
REGMAP_FNAME : string;
INPUT_CLK_FREQENCY : integer := 100_000_000;
-- BUS CLK freqency should be divided by multiples of 4 from input frequency
BUS_CLK_FREQUENCY : integer := 100_000;
START_DELAY_CYCLE : integer := 100_000_000; -- ext_rst to happen # of clk cycles after START
EXT_RST_WIDTH_CYCLE : integer := 1000; -- pulse width of ext_rst in clk cycles
EXT_RST_DELAY_CYCLE : integer := 100_000 -- 1st reg write to happen clk cycles after ext_rst
);
PORT (
CLK : IN std_logic; -- system clock 50Mhz
RESET : IN std_logic; -- active high reset
START : IN std_logic; -- rising edge triggers r/w; synchronous to CLK
EXT_RSTn : OUT std_logic; -- active low for resetting the slave
BUSY : OUT std_logic; -- indicates transaction in progress
ACK_ERROR : OUT std_logic; -- i2c has unexpected ack
SDA_in : IN std_logic; -- serial data input from i2c bus
SDA_out : OUT std_logic; -- serial data output to i2c bus
SDA_t : OUT std_logic; -- serial data direction to/from i2c bus, '1' is read-in
SCL : OUT std_logic -- serial clock output to i2c bus
);
END COMPONENT;
--Inputs
SIGNAL CLK : std_logic := '0';
SIGNAL RESET : std_logic := '0';
SIGNAL START : std_logic := '0';
SIGNAL SDA_in : std_logic := '0';
--Outputs
SIGNAL EXT_RSTn : std_logic;
SIGNAL BUSY : std_logic;
SIGNAL ACK_ERROR : std_logic;
SIGNAL SDA_out : std_logic;
SIGNAL SDA_t : std_logic;
SIGNAL SCL : std_logic;
SIGNAL RD_DATA0 : std_logic_vector(7 DOWNTO 0);
SIGNAL RD_DATA1 : std_logic_vector(7 DOWNTO 0);
-- Clock period definitions
CONSTANT CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : i2c_write_regmap
GENERIC MAP (
REGMAP_FNAME => "../../../../config/Si5324_125MHz_regmap.txt",
INPUT_CLK_FREQENCY => 100_000_000,
BUS_CLK_FREQUENCY => 25_000_000,
START_DELAY_CYCLE => 12,
EXT_RST_WIDTH_CYCLE => 13,
EXT_RST_DELAY_CYCLE => 14
)
PORT MAP (
CLK => CLK,
RESET => RESET,
START => START,
EXT_RSTn => EXT_RSTn,
BUSY => BUSY,
ACK_ERROR => ACK_ERROR,
SDA_in => SDA_in,
SDA_out => SDA_out,
SDA_t => SDA_t,
SCL => SCL
);
-- Clock process definitions
CLK_process : PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_period/2;
CLK <= '1';
WAIT FOR CLK_period/2;
END PROCESS;
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- initial values:
START <= '0';
SDA_in <= '1';
-- hold reset state for 100 ns.
WAIT FOR 10 ns;
RESET <= '1';
WAIT FOR 100 ns;
RESET <= '0';
-- stimulate START
WAIT FOR CLK_period * 10;
START <= '1';
WAIT FOR CLK_period * 2;
START <= '0';
WAIT UNTIL (falling_edge(BUSY));
START <= '1';
WAIT FOR CLK_period * 2;
START <= '0';
WAIT UNTIL (falling_edge(BUSY));
RESET <= '1';
WAIT FOR CLK_period * 2;
RESET <= '0';
WAIT;
END PROCESS;
END;
| bsd-3-clause | 82926d9b8963258f379f428150bc3877 | 0.534168 | 3.627247 | false | false | false | false |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_09_a/hdl/vhdl/radio_controller.vhd | 2 | 39,468 | -- Copyright (c) 2006 Rice University
-- All Rights Reserved
-- This code is covered by the Rice-WARP license
-- See http://warp.rice.edu/license/ for details
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library opb_ipif_v3_01_c;
use opb_ipif_v3_01_c.all;
library radio_controller_v1_09_a;
use radio_controller_v1_09_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"0000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
spi_clk : out std_logic;
data_out : out std_logic;
radio1_cs : out std_logic;
radio2_cs : out std_logic;
radio3_cs : out std_logic;
radio4_cs : out std_logic;
dac1_cs : out std_logic;
dac2_cs : out std_logic;
dac3_cs : out std_logic;
dac4_cs : out std_logic;
radio1_SHDN : out std_logic;
radio1_TxEn : out std_logic;
radio1_RxEn : out std_logic;
radio1_RxHP : out std_logic;
radio1_LD : in std_logic;
radio1_24PA : out std_logic;
radio1_5PA : out std_logic;
radio1_ANTSW : out std_logic_vector(0 to 1);
radio1_LED : out std_logic_vector(0 to 2);
radio1_ADC_RX_DCS : out std_logic;
radio1_ADC_RX_DFS : out std_logic;
radio1_ADC_RX_OTRA : in std_logic;
radio1_ADC_RX_OTRB : in std_logic;
radio1_ADC_RX_PWDNA : out std_logic;
radio1_ADC_RX_PWDNB : out std_logic;
radio1_DIPSW : in std_logic_vector(0 to 3);
radio1_RSSI_ADC_CLAMP : out std_logic;
radio1_RSSI_ADC_HIZ : out std_logic;
radio1_RSSI_ADC_OTR : in std_logic;
radio1_RSSI_ADC_SLEEP : out std_logic;
radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio1_TX_DAC_PLL_LOCK : in std_logic;
radio1_TX_DAC_RESET : out std_logic;
radio1_SHDN_external : in std_logic;
radio1_TxEn_external : in std_logic;
radio1_RxEn_external : in std_logic;
radio1_RxHP_external : in std_logic;
radio1_TxGain : out std_logic_vector(0 to 5);
radio1_TxStart : out std_logic;
radio2_SHDN : out std_logic;
radio2_TxEn : out std_logic;
radio2_RxEn : out std_logic;
radio2_RxHP : out std_logic;
radio2_LD : in std_logic;
radio2_24PA : out std_logic;
radio2_5PA : out std_logic;
radio2_ANTSW : out std_logic_vector(0 to 1);
radio2_LED : out std_logic_vector(0 to 2);
radio2_ADC_RX_DCS : out std_logic;
radio2_ADC_RX_DFS : out std_logic;
radio2_ADC_RX_OTRA : in std_logic;
radio2_ADC_RX_OTRB : in std_logic;
radio2_ADC_RX_PWDNA : out std_logic;
radio2_ADC_RX_PWDNB : out std_logic;
radio2_DIPSW : in std_logic_vector(0 to 3);
radio2_RSSI_ADC_CLAMP : out std_logic;
radio2_RSSI_ADC_HIZ : out std_logic;
radio2_RSSI_ADC_OTR : in std_logic;
radio2_RSSI_ADC_SLEEP : out std_logic;
radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio2_TX_DAC_PLL_LOCK : in std_logic;
radio2_TX_DAC_RESET : out std_logic;
radio2_SHDN_external : in std_logic;
radio2_TxEn_external : in std_logic;
radio2_RxEn_external : in std_logic;
radio2_RxHP_external : in std_logic;
radio2_TxGain : out std_logic_vector(0 to 5);
radio2_TxStart : out std_logic;
radio3_SHDN : out std_logic;
radio3_TxEn : out std_logic;
radio3_RxEn : out std_logic;
radio3_RxHP : out std_logic;
radio3_LD : in std_logic;
radio3_24PA : out std_logic;
radio3_5PA : out std_logic;
radio3_ANTSW : out std_logic_vector(0 to 1);
radio3_LED : out std_logic_vector(0 to 2);
radio3_ADC_RX_DCS : out std_logic;
radio3_ADC_RX_DFS : out std_logic;
radio3_ADC_RX_OTRA : in std_logic;
radio3_ADC_RX_OTRB : in std_logic;
radio3_ADC_RX_PWDNA : out std_logic;
radio3_ADC_RX_PWDNB : out std_logic;
radio3_DIPSW : in std_logic_vector(0 to 3);
radio3_RSSI_ADC_CLAMP : out std_logic;
radio3_RSSI_ADC_HIZ : out std_logic;
radio3_RSSI_ADC_OTR : in std_logic;
radio3_RSSI_ADC_SLEEP : out std_logic;
radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio3_TX_DAC_PLL_LOCK : in std_logic;
radio3_TX_DAC_RESET : out std_logic;
radio3_SHDN_external : in std_logic;
radio3_TxEn_external : in std_logic;
radio3_RxEn_external : in std_logic;
radio3_RxHP_external : in std_logic;
radio3_TxGain : out std_logic_vector(0 to 5);
radio3_TxStart : out std_logic;
radio4_SHDN : out std_logic;
radio4_TxEn : out std_logic;
radio4_RxEn : out std_logic;
radio4_RxHP : out std_logic;
radio4_LD : in std_logic;
radio4_24PA : out std_logic;
radio4_5PA : out std_logic;
radio4_ANTSW : out std_logic_vector(0 to 1);
radio4_LED : out std_logic_vector(0 to 2);
radio4_ADC_RX_DCS : out std_logic;
radio4_ADC_RX_DFS : out std_logic;
radio4_ADC_RX_OTRA : in std_logic;
radio4_ADC_RX_OTRB : in std_logic;
radio4_ADC_RX_PWDNA : out std_logic;
radio4_ADC_RX_PWDNB : out std_logic;
radio4_DIPSW : in std_logic_vector(0 to 3);
radio4_RSSI_ADC_CLAMP : out std_logic;
radio4_RSSI_ADC_HIZ : out std_logic;
radio4_RSSI_ADC_OTR : in std_logic;
radio4_RSSI_ADC_SLEEP : out std_logic;
radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio4_TX_DAC_PLL_LOCK : in std_logic;
radio4_TX_DAC_RESET : out std_logic;
radio4_SHDN_external : in std_logic;
radio4_TxEn_external : in std_logic;
radio4_RxEn_external : in std_logic;
radio4_RxHP_external : in std_logic;
radio4_TxGain : out std_logic_vector(0 to 5);
radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Constant: array of address range identifiers
------------------------------------------
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00 -- user logic S/W register address space
);
------------------------------------------
-- Constant: array of address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
);
------------------------------------------
-- Constant: array of data widths for each target address range
------------------------------------------
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic data width
);
------------------------------------------
-- Constant: array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_CE : integer := 17;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
);
------------------------------------------
-- Constant: array of unique properties for each address range
------------------------------------------
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic slave space dependent properties (none defined)
);
------------------------------------------
-- Constant: pipeline mode
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
-- Note:
-- only mode 4, 5, 7 are supported for this release
------------------------------------------
constant PIPELINE_MODEL : integer := 5;
------------------------------------------
-- Constant: user core ID code
------------------------------------------
constant DEV_BLK_ID : integer := 0;
------------------------------------------
-- Constant: enable MIR/Reset register
------------------------------------------
constant DEV_MIR_ENABLE : integer := 0;
------------------------------------------
-- Constant: array of IP interrupt mode
-- 1 = Active-high interrupt condition
-- 2 = Active-low interrupt condition
-- 3 = Active-high pulse interrupt event
-- 4 = Active-low pulse interrupt event
-- 5 = Positive-edge interrupt event
-- 6 = Negative-edge interrupt event
------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
------------------------------------------
-- Constant: enable device burst
------------------------------------------
constant DEV_BURST_ENABLE : integer := 0;
------------------------------------------
-- Constant: include address counter for burst transfers
------------------------------------------
constant INCLUDE_ADDR_CNTR : integer := 0;
------------------------------------------
-- Constant: include write buffer that decouples OPB and IPIC write transactions
------------------------------------------
constant INCLUDE_WR_BUF : integer := 0;
------------------------------------------
-- Constant: index for CS/CE
------------------------------------------
constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal ENABLE_POSTED_WRITE : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- enable posted write behavior
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 17
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
spi_clk : out std_logic;
data_out : out std_logic;
Radio1_cs : out std_logic;
Radio2_cs : out std_logic;
Radio3_cs : out std_logic;
Radio4_cs : out std_logic;
Dac1_cs : out std_logic;
Dac2_cs : out std_logic;
Dac3_cs : out std_logic;
Dac4_cs : out std_logic;
Radio1_SHDN : out std_logic;
Radio1_TxEn : out std_logic;
Radio1_RxEn : out std_logic;
Radio1_RxHP : out std_logic;
Radio1_LD : in std_logic;
Radio1_24PA : out std_logic;
Radio1_5PA : out std_logic;
Radio1_ANTSW : out std_logic_vector(0 to 1);
Radio1_LED : out std_logic_vector(0 to 2);
Radio1_ADC_RX_DCS : out std_logic;
Radio1_ADC_RX_DFS : out std_logic;
Radio1_ADC_RX_OTRA : in std_logic;
Radio1_ADC_RX_OTRB : in std_logic;
Radio1_ADC_RX_PWDNA : out std_logic;
Radio1_ADC_RX_PWDNB : out std_logic;
Radio1_DIPSW : in std_logic_vector(0 to 3);
Radio1_RSSI_ADC_CLAMP : out std_logic;
Radio1_RSSI_ADC_HIZ : out std_logic;
Radio1_RSSI_ADC_OTR : in std_logic;
Radio1_RSSI_ADC_SLEEP : out std_logic;
Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio1_TX_DAC_PLL_LOCK : in std_logic;
Radio1_TX_DAC_RESET : out std_logic;
Radio1_SHDN_external : in std_logic;
Radio1_TxEn_external : in std_logic;
Radio1_RxEn_external : in std_logic;
Radio1_RxHP_external : in std_logic;
Radio1_TxGain : out std_logic_vector(0 to 5);
Radio1_TxStart : out std_logic;
Radio2_SHDN : out std_logic;
Radio2_TxEn : out std_logic;
Radio2_RxEn : out std_logic;
Radio2_RxHP : out std_logic;
Radio2_LD : in std_logic;
Radio2_24PA : out std_logic;
Radio2_5PA : out std_logic;
Radio2_ANTSW : out std_logic_vector(0 to 1);
Radio2_LED : out std_logic_vector(0 to 2);
Radio2_ADC_RX_DCS : out std_logic;
Radio2_ADC_RX_DFS : out std_logic;
Radio2_ADC_RX_OTRA : in std_logic;
Radio2_ADC_RX_OTRB : in std_logic;
Radio2_ADC_RX_PWDNA : out std_logic;
Radio2_ADC_RX_PWDNB : out std_logic;
Radio2_DIPSW : in std_logic_vector(0 to 3);
Radio2_RSSI_ADC_CLAMP : out std_logic;
Radio2_RSSI_ADC_HIZ : out std_logic;
Radio2_RSSI_ADC_OTR : in std_logic;
Radio2_RSSI_ADC_SLEEP : out std_logic;
Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio2_TX_DAC_PLL_LOCK : in std_logic;
Radio2_TX_DAC_RESET : out std_logic;
Radio2_SHDN_external : in std_logic;
Radio2_TxEn_external : in std_logic;
Radio2_RxEn_external : in std_logic;
Radio2_RxHP_external : in std_logic;
Radio2_TxGain : out std_logic_vector(0 to 5);
Radio2_TxStart : out std_logic;
Radio3_SHDN : out std_logic;
Radio3_TxEn : out std_logic;
Radio3_RxEn : out std_logic;
Radio3_RxHP : out std_logic;
Radio3_LD : in std_logic;
Radio3_24PA : out std_logic;
Radio3_5PA : out std_logic;
Radio3_ANTSW : out std_logic_vector(0 to 1);
Radio3_LED : out std_logic_vector(0 to 2);
Radio3_ADC_RX_DCS : out std_logic;
Radio3_ADC_RX_DFS : out std_logic;
Radio3_ADC_RX_OTRA : in std_logic;
Radio3_ADC_RX_OTRB : in std_logic;
Radio3_ADC_RX_PWDNA : out std_logic;
Radio3_ADC_RX_PWDNB : out std_logic;
Radio3_DIPSW : in std_logic_vector(0 to 3);
Radio3_RSSI_ADC_CLAMP : out std_logic;
Radio3_RSSI_ADC_HIZ : out std_logic;
Radio3_RSSI_ADC_OTR : in std_logic;
Radio3_RSSI_ADC_SLEEP : out std_logic;
Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio3_TX_DAC_PLL_LOCK : in std_logic;
Radio3_TX_DAC_RESET : out std_logic;
Radio3_SHDN_external : in std_logic;
Radio3_TxEn_external : in std_logic;
Radio3_RxEn_external : in std_logic;
Radio3_RxHP_external : in std_logic;
Radio3_TxGain : out std_logic_vector(0 to 5);
Radio3_TxStart : out std_logic;
Radio4_SHDN : out std_logic;
Radio4_TxEn : out std_logic;
Radio4_RxEn : out std_logic;
Radio4_RxHP : out std_logic;
Radio4_LD : in std_logic;
Radio4_24PA : out std_logic;
Radio4_5PA : out std_logic;
Radio4_ANTSW : out std_logic_vector(0 to 1);
Radio4_LED : out std_logic_vector(0 to 2);
Radio4_ADC_RX_DCS : out std_logic;
Radio4_ADC_RX_DFS : out std_logic;
Radio4_ADC_RX_OTRA : in std_logic;
Radio4_ADC_RX_OTRB : in std_logic;
Radio4_ADC_RX_PWDNA : out std_logic;
Radio4_ADC_RX_PWDNB : out std_logic;
Radio4_DIPSW : in std_logic_vector(0 to 3);
Radio4_RSSI_ADC_CLAMP : out std_logic;
Radio4_RSSI_ADC_HIZ : out std_logic;
Radio4_RSSI_ADC_OTR : in std_logic;
Radio4_RSSI_ADC_SLEEP : out std_logic;
Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio4_TX_DAC_PLL_LOCK : in std_logic;
Radio4_TX_DAC_RESET : out std_logic;
Radio4_SHDN_external : in std_logic;
Radio4_TxEn_external : in std_logic;
Radio4_RxEn_external : in std_logic;
Radio4_RxHP_external : in std_logic;
Radio4_TxGain : out std_logic_vector(0 to 5);
Radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sl_DBus,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_retry => Sl_retry,
Sln_toutSup => Sl_toutSup,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_AddrAck => '0',
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => ENABLE_POSTED_WRITE,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => iBus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => iBus2IP_Reset
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
spi_clk => spi_clk,
data_out => data_out,
Radio1_cs => radio1_cs,
Radio2_cs => radio2_cs,
Radio3_cs => radio3_cs,
Radio4_cs => radio4_cs,
Dac1_cs => dac1_cs,
Dac2_cs => dac2_cs,
Dac3_cs => dac3_cs,
Dac4_cs => dac4_cs,
Radio1_SHDN => radio1_SHDN,
Radio1_TxEn => radio1_TxEn,
Radio1_RxEn => radio1_RxEn,
Radio1_RxHP => radio1_RxHP,
Radio1_LD => radio1_LD,
Radio1_24PA => radio1_24PA,
Radio1_5PA => radio1_5PA,
Radio1_ANTSW => radio1_ANTSW,
Radio1_LED => radio1_LED,
Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS,
Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS,
Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA,
Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB,
Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA,
Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB,
Radio1_DIPSW => radio1_DIPSW,
Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP,
Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ,
Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR,
Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP,
Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D,
Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK,
Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET,
Radio1_SHDN_external => radio1_SHDN_external,
Radio1_TxEn_external => radio1_TxEn_external,
Radio1_RxEn_external => radio1_RxEn_external,
Radio1_RxHP_external => radio1_RxHP_external,
Radio1_TxGain => radio1_TxGain,
Radio1_TxStart => radio1_TxStart,
Radio2_SHDN => radio2_SHDN,
Radio2_TxEn => radio2_TxEn,
Radio2_RxEn => radio2_RxEn,
Radio2_RxHP => radio2_RxHP,
Radio2_LD => radio2_LD,
Radio2_24PA => radio2_24PA,
Radio2_5PA => radio2_5PA,
Radio2_ANTSW => radio2_ANTSW,
Radio2_LED => radio2_LED,
Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS,
Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS,
Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA,
Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB,
Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA,
Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB,
Radio2_DIPSW => radio2_DIPSW,
Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP,
Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ,
Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR,
Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP,
Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D,
Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK,
Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET,
Radio2_SHDN_external => radio2_SHDN_external,
Radio2_TxEn_external => radio2_TxEn_external,
Radio2_RxEn_external => radio2_RxEn_external,
Radio2_RxHP_external => radio2_RxHP_external,
Radio2_TxGain => radio2_TxGain,
Radio2_TxStart => radio2_TxStart,
Radio3_SHDN => radio3_SHDN,
Radio3_TxEn => radio3_TxEn,
Radio3_RxEn => radio3_RxEn,
Radio3_RxHP => radio3_RxHP,
Radio3_LD => radio3_LD,
Radio3_24PA => radio3_24PA,
Radio3_5PA => radio3_5PA,
Radio3_ANTSW => radio3_ANTSW,
Radio3_LED => radio3_LED,
Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS,
Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS,
Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA,
Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB,
Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA,
Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB,
Radio3_DIPSW => radio3_DIPSW,
Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP,
Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ,
Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR,
Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP,
Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D,
Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK,
Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET,
Radio3_SHDN_external => radio3_SHDN_external,
Radio3_TxEn_external => radio3_TxEn_external,
Radio3_RxEn_external => radio3_RxEn_external,
Radio3_RxHP_external => radio3_RxHP_external,
Radio3_TxGain => radio3_TxGain,
Radio3_TxStart => radio3_TxStart,
Radio4_SHDN => radio4_SHDN,
Radio4_TxEn => radio4_TxEn,
Radio4_RxEn => radio4_RxEn,
Radio4_RxHP => radio4_RxHP,
Radio4_LD => radio4_LD,
Radio4_24PA => radio4_24PA,
Radio4_5PA => radio4_5PA,
Radio4_ANTSW => radio4_ANTSW,
Radio4_LED => radio4_LED,
Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS,
Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS,
Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA,
Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB,
Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA,
Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB,
Radio4_DIPSW => radio4_DIPSW,
Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP,
Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ,
Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR,
Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP,
Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D,
Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK,
Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET,
Radio4_SHDN_external => radio4_SHDN_external,
Radio4_TxEn_external => radio4_TxEn_external,
Radio4_RxEn_external => radio4_RxEn_external,
Radio4_RxHP_external => radio4_RxHP_external,
Radio4_TxGain => radio4_TxGain,
Radio4_TxStart => radio4_TxStart,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-2-clause | 26d7c936abd0ad9872b718b5f002ba6b | 0.443321 | 3.857687 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/ddr2ram/user_design/rtl/memc3_infrastructure.vhd | 3 | 12,567 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKOUT4_DIVIDE : integer := 1;
C_CLKFBOUT_MULT : integer := 2;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
clk_img : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
signal clk_img_bufg_in : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
-- u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
sys_clk_ibufg <= sys_clk;
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => C_CLKOUT4_DIVIDE,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => clk_img_bufg_in,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
U_BUFG_img : BUFG
port map
(
O => clk_img,
I => clk_img_bufg_in
);
U_BUFG_CLK1 : BUFG
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in
);
-- U_BUFG_CLK1 : BUFGCE
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in,
-- CE => locked
-- );
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
| bsd-2-clause | 89101779af149e57ced0299ae2256e9f | 0.52988 | 3.93703 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_testbench_capture_GN5SAAB6UA.vhd | 2 | 1,775 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GN5SAAB6UA is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(16 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GN5SAAB6UA is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
| mit | 3bd7b09f2bfe994e0308aec66d2ccb05 | 0.629296 | 3.311567 | false | false | false | false |
ymei/TMSPlane | Firmware/src/top_TMS1mmX19_TE07412C1.vhd | 1 | 66,479 | --------------------------------------------------------------------------------
--! @file top.vhd
--! @brief Toplevel module for TE0741-2C1.
--! @author Yuan Mei
--!
--! Target Devices: Kintex-7 XC7K160T-FFG676-2
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
LIBRARY work;
USE work.utility.ALL;
ENTITY top IS
GENERIC (
ENABLE_DEBUG : boolean := false;
ENABLE_TEN_GIG_ETH : boolean := false
);
PORT (
SYS_RST : IN std_logic;
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
SGMIICLK_Q0_P : IN std_logic; --! 125 MHz, for GTP/GTH/GTX
SGMIICLK_Q0_N : IN std_logic;
--
LED8Bit : OUT std_logic_vector(7 DOWNTO 0);
-- SFP
SFP_TX_P : OUT std_logic;
SFP_TX_N : OUT std_logic;
SFP_RX_P : IN std_logic;
SFP_RX_N : IN std_logic;
SFP_LOS_LS : IN std_logic;
SFP_TX_DISABLE_N : OUT std_logic;
-- MGT
MGT_CLK3_P : IN std_logic; --! 156.25 MHz, for GTX/10GbE
MGT_CLK3_N : IN std_logic;
SMA_MGT_TX_P : OUT std_logic;
SMA_MGT_TX_N : OUT std_logic;
SMA_MGT_RX_P : IN std_logic;
SMA_MGT_RX_N : IN std_logic;
--
I2C_SCL : INOUT std_logic;
I2C_SDA : INOUT std_logic;
-- TE0741 B2B connector
B12_L_P : INOUT std_logic_vector(25 DOWNTO 0);
B12_L_N : INOUT std_logic_vector(25 DOWNTO 0);
B13_L_P : INOUT std_logic_vector(24 DOWNTO 0);
B13_L_N : INOUT std_logic_vector(24 DOWNTO 0);
B14_L_P : INOUT std_logic_vector(24 DOWNTO 0);
B14_L_N : INOUT std_logic_vector(24 DOWNTO 0);
B15_L_P : INOUT std_logic_vector(23 DOWNTO 0);
B15_L_N : INOUT std_logic_vector(23 DOWNTO 0);
B16_L_P : INOUT std_logic_vector(23 DOWNTO 0);
B16_L_N : INOUT std_logic_vector(23 DOWNTO 0)
);
END top;
ARCHITECTURE Behavioral OF top IS
-- Components
COMPONENT global_clock_reset
PORT (
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
FORCE_RST : IN std_logic;
-- output
GLOBAL_RST : OUT std_logic;
SYS_CLK : OUT std_logic;
LOCKED : OUT std_logic;
CLK_OUT1 : OUT std_logic;
CLK_OUT2 : OUT std_logic;
CLK_OUT3 : OUT std_logic;
CLK_OUT4 : OUT std_logic
);
END COMPONENT;
---------------------------------------------< ten_gig_eth
COMPONENT ten_gig_eth
PORT (
REFCLK_P : IN std_logic; -- 156.25MHz for transceiver
REFCLK_N : IN std_logic;
RESET : IN std_logic;
SFP_TX_P : OUT std_logic;
SFP_TX_N : OUT std_logic;
SFP_RX_P : IN std_logic;
SFP_RX_N : IN std_logic;
SFP_LOS : IN std_logic; -- loss of receiver signal
SFP_TX_DISABLE : OUT std_logic;
-- clk156.25 domain, clock generated by the core
CLK156p25 : OUT std_logic;
PCS_PMA_CORE_STATUS : OUT std_logic_vector(7 DOWNTO 0);
TX_STATISTICS_VECTOR : OUT std_logic_vector(25 DOWNTO 0);
TX_STATISTICS_VALID : OUT std_logic;
RX_STATISTICS_VECTOR : OUT std_logic_vector(29 DOWNTO 0);
RX_STATISTICS_VALID : OUT std_logic;
PAUSE_VAL : IN std_logic_vector(15 DOWNTO 0);
PAUSE_REQ : IN std_logic;
TX_IFG_DELAY : IN std_logic_vector(7 DOWNTO 0);
-- emac control interface
S_AXI_ACLK : IN std_logic;
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(10 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WDATA : IN std_logic_vector(31 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(10 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- tx_wr_clk domain
TX_AXIS_FIFO_ARESETN : IN std_logic;
TX_AXIS_FIFO_ACLK : IN std_logic;
TX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
TX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
TX_AXIS_FIFO_TVALID : IN std_logic;
TX_AXIS_FIFO_TLAST : IN std_logic;
TX_AXIS_FIFO_TREADY : OUT std_logic;
-- rx_rd_clk domain
RX_AXIS_FIFO_ARESETN : IN std_logic;
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : OUT std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : OUT std_logic;
RX_AXIS_FIFO_TLAST : OUT std_logic;
RX_AXIS_FIFO_TREADY : IN std_logic
);
END COMPONENT;
COMPONENT ten_gig_eth_packet_gen
PORT (
RESET : IN std_logic;
MEM_CLK : IN std_logic;
MEM_WE : IN std_logic; -- memory write enable
MEM_ADDR : IN std_logic_vector(31 DOWNTO 0);
MEM_D : IN std_logic_vector(31 DOWNTO 0); -- memory data
--
TX_AXIS_ACLK : IN std_logic;
TX_START : IN std_logic;
TX_BYTES : IN std_logic_vector(15 DOWNTO 0); -- number of bytes to send
TX_AXIS_TDATA : OUT std_logic_vector(63 DOWNTO 0);
TX_AXIS_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
TX_AXIS_TVALID : OUT std_logic;
TX_AXIS_TLAST : OUT std_logic;
TX_AXIS_TREADY : IN std_logic
);
END COMPONENT;
COMPONENT ten_gig_eth_rx_parser
PORT (
RESET : IN std_logic;
RX_AXIS_FIFO_ARESETN : OUT std_logic;
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : IN std_logic;
RX_AXIS_FIFO_TLAST : IN std_logic;
RX_AXIS_FIFO_TREADY : OUT std_logic;
-- Constants
SRC_MAC : IN std_logic_vector(47 DOWNTO 0);
SRC_IP : IN std_logic_vector(31 DOWNTO 0);
SRC_PORT : IN std_logic_vector(15 DOWNTO 0);
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q : OUT std_logic_vector(127 DOWNTO 0);
CMD_FIFO_EMPTY : OUT std_logic;
CMD_FIFO_RDREQ : IN std_logic;
CMD_FIFO_RDCLK : IN std_logic
);
END COMPONENT;
---------------------------------------------> ten_gig_eth
---------------------------------------------< gtx / aurora
COMPONENT aurora_64b66b
PORT (
RESET : IN std_logic;
SYS_CLK : IN std_logic;
MGT_REFCLK_P : IN std_logic;
MGT_REFCLK_N : IN std_logic;
-- Data interfaces are synchronous to USER_CLK
USER_CLK : OUT std_logic;
MGT_REFCLK_BUFG_OUT : OUT std_logic;
-- TX AXI4 interface
S_AXI_TX_TDATA : IN std_logic_vector(0 TO 63);
S_AXI_TX_TVALID : IN std_logic;
S_AXI_TX_TREADY : OUT std_logic;
-- RX AXI4 interface
M_AXI_RX_TDATA : OUT std_logic_vector(0 TO 63);
M_AXI_RX_TVALID : OUT std_logic;
-- User flow control (UFC) TX
UFC_TX_REQ : IN std_logic;
S_AXI_UFC_TX_TDATA : IN std_logic_vector(0 TO 63);
UFC_TX_MS : IN std_logic_vector(0 TO 7);
S_AXI_UFC_TX_TVALID : IN std_logic;
S_AXI_UFC_TX_TREADY : OUT std_logic;
-- UFC RX
M_AXI_UFC_RX_TDATA : OUT std_logic_vector(0 TO 63);
M_AXI_UFC_RX_TKEEP : OUT std_logic_vector(0 TO 7);
M_AXI_UFC_RX_TLAST : OUT std_logic;
M_AXI_UFC_RX_TVALID : OUT std_logic;
UFC_IN_PROGRESSn : OUT std_logic;
-- GTX pins
RXP : IN std_logic;
RXN : IN std_logic;
TXP : OUT std_logic;
TXN : OUT std_logic;
-- Status
STATUS : OUT std_logic_vector(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_over_ufc
GENERIC (
FIFO_DATA_WIDTH : positive := 32;
AURORA_DATA_WIDTH : positive := 64
);
PORT (
RESET : IN std_logic;
AURORA_USER_CLK : IN std_logic;
AURORA_TX_REQ : OUT std_logic;
AURORA_TX_MS : OUT std_logic_vector(7 DOWNTO 0);
AURORA_TX_TREADY : IN std_logic;
AURORA_TX_TDATA : OUT std_logic_vector(AURORA_DATA_WIDTH-1 DOWNTO 0);
AURORA_TX_TVALID : OUT std_logic;
AURORA_RX_TDATA : IN std_logic_vector(AURORA_DATA_WIDTH-1 DOWNTO 0);
AURORA_RX_TVALID : IN std_logic;
FIFO_CLK : OUT std_logic;
TX_FIFO_Q : OUT std_logic_vector(FIFO_DATA_WIDTH-1 DOWNTO 0);
TX_FIFO_WREN : OUT std_logic;
TX_FIFO_FULL : IN std_logic;
RX_FIFO_Q : IN std_logic_vector(FIFO_DATA_WIDTH-1 DOWNTO 0);
RX_FIFO_RDEN : OUT std_logic;
RX_FIFO_EMPTY : IN std_logic;
ERR : OUT std_logic
);
END COMPONENT;
COMPONENT fifo36x512
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(35 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(35 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
---------------------------------------------> gtx / aurora
---------------------------------------------< UART/RS232
COMPONENT control_interface
PORT (
RESET : IN std_logic;
CLK : IN std_logic; -- system clock
-- From FPGA to PC
FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); -- interface fifo data output port
FIFO_EMPTY : OUT std_logic; -- interface fifo "emtpy" signal
FIFO_RDREQ : IN std_logic; -- interface fifo read request
FIFO_RDCLK : IN std_logic; -- interface fifo read clock
-- From PC to FPGA, FWFT
CMD_FIFO_Q : IN std_logic_vector(35 DOWNTO 0); -- interface command fifo data out port
CMD_FIFO_EMPTY : IN std_logic; -- interface command fifo "emtpy" signal
CMD_FIFO_RDREQ : OUT std_logic; -- interface command fifo read request
-- Digital I/O
CONFIG_REG : OUT std_logic_vector(511 DOWNTO 0); -- thirtytwo 16bit registers
PULSE_REG : OUT std_logic_vector(15 DOWNTO 0); -- 16bit pulse register
STATUS_REG : IN std_logic_vector(175 DOWNTO 0); -- eleven 16bit registers
-- Memory interface
MEM_WE : OUT std_logic; -- memory write enable
MEM_ADDR : OUT std_logic_vector(31 DOWNTO 0);
MEM_DIN : OUT std_logic_vector(31 DOWNTO 0); -- memory data input
MEM_DOUT : IN std_logic_vector(31 DOWNTO 0); -- memory data output
-- Data FIFO interface, FWFT
DATA_FIFO_Q : IN std_logic_vector(31 DOWNTO 0);
DATA_FIFO_EMPTY : IN std_logic;
DATA_FIFO_RDREQ : OUT std_logic;
DATA_FIFO_RDCLK : OUT std_logic
);
END COMPONENT;
---------------------------------------------> UART/RS232
---------------------------------------------< I2C
COMPONENT i2c_master
GENERIC (
INPUT_CLK_FREQENCY : integer := 100_000_000;
-- BUS CLK freqency should be divided by multiples of 4 from input frequency
BUS_CLK_FREQUENCY : integer := 100_000
);
PORT (
CLK : IN std_logic; -- system clock 50Mhz
RESET : IN std_logic; -- active high reset
START : IN std_logic; -- rising edge triggers r/w; synchronous to CLK
MODE : IN std_logic_vector(1 DOWNTO 0); -- "00" : 1 bytes read or write, "01" : 2 bytes r/w, "10" : 3 bytes write only;
SL_RW : IN std_logic; -- '0' is write, '1' is read
SL_ADDR : IN std_logic_vector(6 DOWNTO 0); -- slave addr
REG_ADDR : IN std_logic_vector(7 DOWNTO 0); -- slave internal reg addr for read and write
WR_DATA0 : IN std_logic_vector(7 DOWNTO 0); -- first data byte to write
WR_DATA1 : IN std_logic_vector(7 DOWNTO 0); -- second data byte to write
RD_DATA0 : OUT std_logic_vector(7 DOWNTO 0); -- first data byte read
RD_DATA1 : OUT std_logic_vector(7 DOWNTO 0); -- second data byte read
BUSY : OUT std_logic; -- indicates transaction in progress
ACK_ERROR : OUT std_logic; -- i2c has unexpected ack
SDA_in : IN std_logic; -- serial data input from i2c bus
SDA_out : OUT std_logic; -- serial data output to i2c bus
SDA_t : OUT std_logic; -- serial data direction to/from i2c bus, '1' is read-in
SCL : OUT std_logic -- serial clock output to i2c bus
);
END COMPONENT;
COMPONENT i2c_write_regmap
GENERIC (
REGMAP_FNAME : string;
INPUT_CLK_FREQENCY : integer := 100_000_000;
-- BUS CLK freqency should be divided by multiples of 4 from input frequency
BUS_CLK_FREQUENCY : integer := 100_000;
START_DELAY_CYCLE : integer := 100_000_000; -- ext_rst to happen # of clk cycles after START
EXT_RST_WIDTH_CYCLE : integer := 1000; -- pulse width of ext_rst in clk cycles
EXT_RST_DELAY_CYCLE : integer := 100_000 -- 1st reg write to happen clk cycles after ext_rst
);
PORT (
CLK : IN std_logic; -- system clock 50Mhz
RESET : IN std_logic; -- active high reset
START : IN std_logic; -- rising edge triggers r/w; synchronous to CLK
EXT_RSTn : OUT std_logic; -- active low for resetting the slave
BUSY : OUT std_logic; -- indicates transaction in progress
ACK_ERROR : OUT std_logic; -- i2c has unexpected ack
SDA_in : IN std_logic; -- serial data input from i2c bus
SDA_out : OUT std_logic; -- serial data output to i2c bus
SDA_t : OUT std_logic; -- serial data direction to/from i2c bus, '1' is read-in
SCL : OUT std_logic -- serial clock output to i2c bus
);
END COMPONENT;
---------------------------------------------> I2C
---------------------------------------------< shiftreg driver for DAC8568
COMPONENT fifo2shiftreg
GENERIC (
DATA_WIDTH : positive := 32; -- parallel data width
CLK_DIV_WIDTH : positive := 16;
DELAY_AFTER_SYNCn : natural := 0; -- number of SCLK cycles' wait after falling edge OF SYNCn
SCLK_IDLE_LEVEL : std_logic := '0'; -- High or Low for SCLK when not switching
DOUT_DRIVE_EDGE : std_logic := '1'; -- 1/0 rising/falling edge of SCLK drives new DOUT bit
DIN_CAPTURE_EDGE : std_logic := '0' -- 1/0 rising/falling edge of SCLK captures new DIN bit
);
PORT (
CLK : IN std_logic; -- clock
RESET : IN std_logic; -- reset
-- input data interface
WR_CLK : IN std_logic; -- FIFO write clock
DINFIFO : IN std_logic_vector(15 DOWNTO 0);
WR_EN : IN std_logic;
WR_PULSE : IN std_logic; -- one pulse writes one word, regardless of pulse duration
FULL : OUT std_logic;
-- captured data
BUSY : OUT std_logic;
DATAOUT : OUT std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
-- serial interface
CLK_DIV : IN std_logic_vector(CLK_DIV_WIDTH-1 DOWNTO 0); -- SCLK freq is CLK / 2**(CLK_DIV)
SCLK : OUT std_logic;
DOUT : OUT std_logic;
SYNCn : OUT std_logic;
DIN : IN std_logic
);
END COMPONENT;
---------------------------------------------> shiftreg driver for DAC8568
---------------------------------------------< TMS serial io
COMPONENT shiftreg_drive
GENERIC (
DATA_WIDTH : positive := 32; -- parallel data width
CLK_DIV_WIDTH : positive := 16;
DELAY_AFTER_SYNCn : natural := 0; -- number of SCLK cycles' wait after falling edge OF SYNCn
SCLK_IDLE_LEVEL : std_logic := '0'; -- High or Low for SCLK when not switching
DOUT_DRIVE_EDGE : std_logic := '1'; -- 1/0 rising/falling edge of SCLK drives new DOUT bit
DIN_CAPTURE_EDGE : std_logic := '0' -- 1/0 rising/falling edge of SCLK captures new DIN bit
);
PORT (
CLK : IN std_logic; -- clock
RESET : IN std_logic; -- reset
-- internal data interface
CLK_DIV : IN std_logic_vector(CLK_DIV_WIDTH-1 DOWNTO 0); -- SCLK freq is CLK / 2**(CLK_DIV)
DATAIN : IN std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
START : IN std_logic;
BUSY : OUT std_logic;
DATAOUT : OUT std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
-- external serial interface
SCLK : OUT std_logic;
DOUT : OUT std_logic;
SYNCn : OUT std_logic;
DIN : IN std_logic
);
END COMPONENT;
---------------------------------------------> TMS serial io
---------------------------------------------< TMS SDM
COMPONENT tms_sdm_recv
GENERIC (
NCH : positive := 19
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic; -- DELAY_* must be synchronous to this clock
REFCLK : IN std_logic; -- REFCLK (200MHz) for IDELAYCTRL
DELAY_CHANNEL : IN std_logic_vector(7 DOWNTO 0); -- input iodelay channel selection
DELAY_VALUE : IN std_logic_vector(4 DOWNTO 0); -- input iodelay value
DELAY_UPDATE : IN std_logic; -- a pulse to update the delay value
CLKFF_DIV : IN std_logic_vector(3 DOWNTO 0);
CLKFF_P : OUT std_logic;
CLKFF_N : OUT std_logic;
CLK_LPBK_P : IN std_logic;
CLK_LPBK_N : IN std_logic;
CLK_LPBK : OUT std_logic;
SDM_OUT1_P : IN std_logic_vector(NCH-1 DOWNTO 0);
SDM_OUT1_N : IN std_logic_vector(NCH-1 DOWNTO 0);
SDM_OUT2_P : IN std_logic_vector(NCH-1 DOWNTO 0);
SDM_OUT2_N : IN std_logic_vector(NCH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(NCH*2-1 DOWNTO 0);
DOUT_VALID : OUT std_logic
);
END COMPONENT;
---------------------------------------------> TMS SDM
---------------------------------------------< ADC, external, LTC2325-16
COMPONENT adc_cnv_sipo
GENERIC (
NCH : positive := 20
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic; -- DELAY_* must be synchronous to this clock
REFCLK : IN std_logic; -- REFCLK (200MHz) for IDELAYCTRL
DELAY_CHANNEL : IN std_logic_vector(7 DOWNTO 0); -- ADC data input iodelay channel selection
DELAY_VALUE : IN std_logic_vector(4 DOWNTO 0); -- ADC data input iodelay value
DELAY_UPDATE : IN std_logic; -- a pulse to update the delay value
CLKFF_DIV : IN std_logic_vector(3 DOWNTO 0);
CLKFF_P : OUT std_logic;
CLKFF_N : OUT std_logic;
CLK_LPBK_P : IN std_logic;
CLK_LPBK_N : IN std_logic;
CLK_LPBK : OUT std_logic;
CNV_N_P : OUT std_logic;
CNV_N_N : OUT std_logic;
CNV_N : OUT std_logic;
INPUTS_P : IN std_logic_vector(NCH-1 DOWNTO 0);
INPUTS_N : IN std_logic_vector(NCH-1 DOWNTO 0);
INPUTS_OUT : OUT std_logic_vector(NCH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(NCH*16-1 DOWNTO 0);
DOUT_VALID : OUT std_logic
);
END COMPONENT;
COMPONENT sdm_adc_data_aggregator
GENERIC (
NCH_ADC : positive := 20;
ADC_CYC : positive := 20;
NCH_SDM : positive := 19;
SDM_CYC : positive := 4
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
ADC_Q : IN std_logic_vector(NCH_ADC*16-1 DOWNTO 0);
ADC_Q_VALID : IN std_logic;
SDM_Q : IN std_logic_vector(NCH_SDM*2-1 DOWNTO 0);
SDM_Q_VALID : IN std_logic;
DOUT : OUT std_logic_vector(511 DOWNTO 0);
DOUT_VALID : OUT std_logic;
USER_CLK : IN std_logic;
S_AXI_TX_TDATA : OUT std_logic_vector(63 DOWNTO 0);
S_AXI_TX_TVALID : OUT std_logic;
S_AXI_TX_TREADY : IN std_logic;
FIFO_FULL : OUT std_logic
);
END COMPONENT;
---------------------------------------------> ADC, external, LTC2325-16
---------------------------------------------< debug : ILA and VIO (`Chipscope')
COMPONENT dbg_ila
PORT (
CLK : IN std_logic;
PROBE0 : IN std_logic_vector(63 DOWNTO 0);
PROBE1 : IN std_logic_vector(79 DOWNTO 0);
PROBE2 : IN std_logic_vector(79 DOWNTO 0);
PROBE3 : IN std_logic_vector(2047 DOWNTO 0)
);
END COMPONENT;
COMPONENT dbg_ila1
PORT (
CLK : IN std_logic;
PROBE0 : IN std_logic_vector(15 DOWNTO 0);
PROBE1 : IN std_logic_vector(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT dbg_vio
PORT (
CLK : IN std_logic;
PROBE_IN0 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN1 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN2 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN3 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN4 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN5 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN6 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN7 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN8 : IN std_logic_vector(35 DOWNTO 0);
PROBE_OUT0 : OUT std_logic_vector(63 DOWNTO 0)
);
END COMPONENT;
---------------------------------------------> debug : ILA and VIO (`Chipscope')
-- Signals
SIGNAL reset : std_logic;
SIGNAL sys_clk : std_logic;
SIGNAL global_clk_locked : std_logic;
SIGNAL clk_50MHz : std_logic;
SIGNAL clk_100MHz : std_logic;
SIGNAL clk_125MHz : std_logic;
SIGNAL clk_200MHz : std_logic;
SIGNAL clk_250MHz : std_logic;
SIGNAL clk_sgmii_i : std_logic;
SIGNAL clk_sgmii : std_logic;
SIGNAL clk156p25 : std_logic;
SIGNAL clk_user : std_logic;
---------------------------------------------< UART/RS232
SIGNAL uart_rx_data : std_logic_vector(7 DOWNTO 0);
SIGNAL uart_rx_rdy : std_logic;
SIGNAL control_clk : std_logic;
SIGNAL control_fifo_q : std_logic_vector(35 DOWNTO 0);
SIGNAL control_fifo_rdreq : std_logic;
SIGNAL control_fifo_empty : std_logic;
SIGNAL control_fifo_rdclk : std_logic;
SIGNAL cmd_fifo_q : std_logic_vector(35 DOWNTO 0);
SIGNAL cmd_fifo_empty : std_logic;
SIGNAL cmd_fifo_rdreq : std_logic;
-- thirtytwo 16bit registers
SIGNAL config_reg : std_logic_vector(511 DOWNTO 0);
-- 16bit pulse register
SIGNAL pulse_reg : std_logic_vector(15 DOWNTO 0);
-- eleven 16bit registers
SIGNAL status_reg : std_logic_vector(175 DOWNTO 0) := (OTHERS => '0');
SIGNAL control_mem_we : std_logic;
SIGNAL control_mem_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL control_mem_din : std_logic_vector(31 DOWNTO 0);
---------------------------------------------> UART/RS232
---------------------------------------------< gtx / aurora
SIGNAL aurora_reset : std_logic;
SIGNAL aurora_status : std_logic_vector(15 DOWNTO 0);
SIGNAL aurora_user_clk : std_logic;
SIGNAL aurora_ufc_tx_req : std_logic;
SIGNAL aurora_ufc_tx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_ufc_tx_ms : std_logic_vector(7 DOWNTO 0);
SIGNAL aurora_ufc_tx_tvalid : std_logic;
SIGNAL aurora_ufc_tx_tready : std_logic;
SIGNAL aurora_ufc_rx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_ufc_rx_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL aurora_ufc_rx_tlast : std_logic;
SIGNAL aurora_ufc_rx_tvalid : std_logic;
SIGNAL aurora_ufc_in_progress_n : std_logic;
SIGNAL aurora_ufc_tx_fifo_q : std_logic_vector(31 DOWNTO 0);
SIGNAL aurora_ufc_tx_fifo_wren : std_logic;
SIGNAL aurora_ufc_tx_fifo_full : std_logic;
SIGNAL aurora_tx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_tx_tvalid : std_logic;
SIGNAL aurora_tx_tready : std_logic;
SIGNAL aurora_rx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_rx_tvalid : std_logic;
---------------------------------------------> gtx / aurora
---------------------------------------------< ten_gig_eth
SIGNAL sfp_tx_disable_i : std_logic;
SIGNAL sPcs_pma_core_status : std_logic_vector(7 DOWNTO 0);
SIGNAL sEmac_status_vector : std_logic_vector(1 DOWNTO 0);
SIGNAL sTx_axis_fifo_aresetn : std_logic;
SIGNAL sTx_axis_fifo_aclk : std_logic;
SIGNAL sTx_axis_fifo_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL sTx_axis_fifo_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL sTx_axis_fifo_tvalid : std_logic;
SIGNAL sTx_axis_fifo_tlast : std_logic;
SIGNAL sTx_axis_fifo_tready : std_logic;
SIGNAL sRx_axis_fifo_aresetn : std_logic;
SIGNAL sRx_axis_fifo_aclk : std_logic;
SIGNAL sRx_axis_fifo_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL sRx_axis_fifo_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL sRx_axis_fifo_tvalid : std_logic;
SIGNAL sRx_axis_fifo_tlast : std_logic;
SIGNAL sRx_axis_fifo_tready : std_logic;
-- control interface
SIGNAL s_axi_aclk : std_logic;
SIGNAL s_axi_aresetn : std_logic;
SIGNAL s_axi_awaddr : std_logic_vector(10 DOWNTO 0);
SIGNAL s_axi_awvalid : std_logic;
SIGNAL s_axi_awready : std_logic;
SIGNAL s_axi_wdata : std_logic_vector(31 DOWNTO 0);
SIGNAL s_axi_wvalid : std_logic;
SIGNAL s_axi_wready : std_logic;
SIGNAL s_axi_bresp : std_logic_vector(1 DOWNTO 0);
SIGNAL s_axi_bvalid : std_logic;
SIGNAL s_axi_bready : std_logic;
SIGNAL s_axi_araddr : std_logic_vector(10 DOWNTO 0);
SIGNAL s_axi_arvalid : std_logic;
SIGNAL s_axi_arready : std_logic;
SIGNAL s_axi_rdata : std_logic_vector(31 DOWNTO 0);
SIGNAL s_axi_rresp : std_logic_vector(1 DOWNTO 0);
SIGNAL s_axi_rvalid : std_logic;
SIGNAL s_axi_rready : std_logic;
-- packets
SIGNAL ten_gig_eth_tx_start : std_logic;
SIGNAL tge_cmd_fifo_q : std_logic_vector(127 DOWNTO 0);
SIGNAL tge_cmd_fifo_empty : std_logic;
SIGNAL tge_cmd_fifo_rdreq : std_logic;
---------------------------------------------> ten_gig_eth
SIGNAL usr_data_output : std_logic_vector (7 DOWNTO 0);
---------------------------------------------< IDATA
SIGNAL TRIG_OUT_0 : std_logic;
SIGNAL idata_cmd_out : std_logic_vector(63 DOWNTO 0);
SIGNAL idata_cmd_out_val : std_logic;
SIGNAL idata_cmd_in : std_logic_vector(63 DOWNTO 0);
SIGNAL idata_cmd_in_val : std_logic;
SIGNAL idata_adc_data_clk : std_logic;
SIGNAL idata_adc_refout_clkdiv : std_logic;
SIGNAL idata_adc_data0 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data1 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data2 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data3 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data4 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data5 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data6 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data7 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data8 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data9 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data10 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data11 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_data_fifo_reset : std_logic;
SIGNAL idata_data_fifo_rdclk : std_logic;
SIGNAL idata_data_fifo_din : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_channel_avg_outdata_q : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_channel_avg_outvalid : std_logic;
SIGNAL idata_data_fifo_wren : std_logic;
SIGNAL idata_data_fifo_rden : std_logic;
SIGNAL idata_data_fifo_dout : std_logic_vector(31 DOWNTO 0);
SIGNAL idata_data_fifo_full : std_logic;
SIGNAL idata_data_fifo_empty : std_logic;
SIGNAL idata_idata_fifo_q : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_idata_fifo_wren : std_logic;
SIGNAL idata_idata_fifo_rden : std_logic;
SIGNAL idata_idata_fifo_full : std_logic;
SIGNAL idata_idata_fifo_empty : std_logic;
SIGNAL idata_trig_allow : std_logic;
SIGNAL idata_trig_in : std_logic;
SIGNAL idata_trig_synced : std_logic;
SIGNAL idata_data_wr_start : std_logic;
SIGNAL idata_data_wr_busy : std_logic;
SIGNAL idata_data_wr_wrapped : std_logic;
---------------------------------------------> IDATA
---------------------------------------------< I2C
SIGNAL i2c_sda_out : std_logic;
SIGNAL i2c_sda_in : std_logic;
SIGNAL i2c_sda_t : std_logic;
SIGNAL i2c_scl_out : std_logic;
SIGNAL i2c1_sda_out : std_logic;
SIGNAL i2c1_sda_in : std_logic;
SIGNAL i2c1_sda_t : std_logic;
SIGNAL i2c1_scl_out : std_logic;
---------------------------------------------> I2C
---------------------------------------------< shiftreg driver for DAC8568
SIGNAL spi_sclk : std_logic;
SIGNAL spi_dout : std_logic;
SIGNAL spi_sync_n : std_logic;
SIGNAL spi_din : std_logic;
---------------------------------------------> shiftreg driver for DAC8568
---------------------------------------------< TMS
SIGNAL tms_pwr_on : std_logic;
SIGNAL tms_sio_a : std_logic_vector(2 DOWNTO 0);
SIGNAL tms_sdi : std_logic;
SIGNAL tms_sdo : std_logic;
SIGNAL tms_sck : std_logic;
SIGNAL dac_din : std_logic;
SIGNAL dac_sclk : std_logic;
SIGNAL dac_sync_n : std_logic;
SIGNAL tms_reset : std_logic;
SIGNAL tms_sdm_clk_src_sel : std_logic;
SIGNAL tms_sdm_clkff_div : std_logic_vector(3 DOWNTO 0);
SIGNAL tms_sdm_clk_lpbk : std_logic;
SIGNAL tms_sdm_out1_p : std_logic_vector(18 DOWNTO 0);
SIGNAL tms_sdm_out1_n : std_logic_vector(18 DOWNTO 0);
SIGNAL tms_sdm_out2_p : std_logic_vector(18 DOWNTO 0);
SIGNAL tms_sdm_out2_n : std_logic_vector(18 DOWNTO 0);
SIGNAL tms_sdm_out : std_logic_vector(37 DOWNTO 0);
SIGNAL tms_sdm_out_valid : std_logic;
SIGNAL tms_sdm_adc_dout : std_logic_vector(511 DOWNTO 0);
SIGNAL tms_sdm_adc_dout_valid : std_logic;
SIGNAL adc_clk_src_sel : std_logic;
SIGNAL adc_clkff_div : std_logic_vector(3 DOWNTO 0);
SIGNAL adc_clk0_lpbk : std_logic;
SIGNAL adc_sdrn_ddr : std_logic;
SIGNAL adc_cnv_n : std_logic;
SIGNAL adc_sdo_p : std_logic_vector(19 DOWNTO 0);
SIGNAL adc_sdo_n : std_logic_vector(19 DOWNTO 0);
SIGNAL adc_sdo : std_logic_vector(19 DOWNTO 0);
SIGNAL adc_dout : std_logic_vector(20*16-1 DOWNTO 0);
SIGNAL adc_dout_valid : std_logic;
SIGNAL sdm_adc_data_aggregator_fifo_full : std_logic;
---------------------------------------------> TMS
---------------------------------------------< debug
SIGNAL dbg_ila_probe0 : std_logic_vector(63 DOWNTO 0);
SIGNAL dbg_ila_probe1 : std_logic_vector(79 DOWNTO 0);
SIGNAL dbg_ila_probe2 : std_logic_vector(79 DOWNTO 0);
SIGNAL dbg_ila_probe3 : std_logic_vector(2047 DOWNTO 0);
SIGNAL dbg_vio_probe_out0 : std_logic_vector(63 DOWNTO 0);
SIGNAL dbg_ila1_probe0 : std_logic_vector(15 DOWNTO 0);
SIGNAL dbg_ila1_probe1 : std_logic_vector(15 DOWNTO 0);
ATTRIBUTE mark_debug : string;
ATTRIBUTE keep : string;
ATTRIBUTE mark_debug OF uart_rx_data : SIGNAL IS "true";
ATTRIBUTE mark_debug OF uart_rx_rdy : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_empty : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_rdreq : SIGNAL IS "true";
ATTRIBUTE mark_debug OF config_reg : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF status_reg : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF pulse_reg : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_we : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_addr : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_din : SIGNAL IS "true";
--
ATTRIBUTE mark_debug OF sPcs_pma_core_status : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sEmac_status_vector : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_aresetn : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_aclk : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tkeep : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tlast : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tready : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_aresetn : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_aclk : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tkeep : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tlast : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tready : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF ten_gig_eth_tx_start : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_empty : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_rdreq : SIGNAL IS "true";
---------------------------------------------> debug
BEGIN
---------------------------------------------< Clock
global_clock_reset_inst : global_clock_reset
PORT MAP (
SYS_CLK_P => SYS_CLK_P,
SYS_CLK_N => SYS_CLK_N,
FORCE_RST => SYS_RST,
-- output
GLOBAL_RST => reset,
SYS_CLK => sys_clk,
LOCKED => global_clk_locked,
CLK_OUT1 => clk_50MHz,
CLK_OUT2 => OPEN,
CLK_OUT3 => clk_200MHz,
CLK_OUT4 => clk_250MHz
);
clk_100MHz <= sys_clk;
-- user_clk_ibufds_inst : IBUFDS
-- GENERIC MAP (
-- DIFF_TERM => true, -- Differential Termination
-- IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-- IOSTANDARD => "LVDS"
-- )
-- PORT MAP (
-- O => clk_user, -- Buffer output
-- I => USER_CLK_P, -- Diff_p buffer input (connect directly to top-level port)
-- IB => USER_CLK_N -- Diff_n buffer input (connect directly to top-level port)
-- );
-- gtx/gth reference clock can be used as general purpose clock this way
-- sgmiiclk_ibufds_inst : IBUFDS_GTE2
-- PORT MAP (
-- O => clk_sgmii_i,
-- ODIV2 => OPEN,
-- CEB => '0',
-- I => SGMIICLK_Q0_P,
-- IB => SGMIICLK_Q0_N
-- );
-- sgmiiclk_bufg_inst : BUFG
-- PORT MAP (
-- I => clk_sgmii_i,
-- O => clk_sgmii
-- );
clk_125MHz <= clk_sgmii;
---------------------------------------------> Clock
---------------------------------------------< debug : ILA and VIO (`Chipscope')
dbg_cores : IF ENABLE_DEBUG GENERATE
dbg_ila_inst : dbg_ila
PORT MAP (
CLK => sys_clk,
PROBE0 => dbg_ila_probe0,
PROBE1 => dbg_ila_probe1,
PROBE2 => dbg_ila_probe2,
PROBE3 => dbg_ila_probe3
);
dbg_vio_inst : dbg_vio
PORT MAP (
CLK => sys_clk,
PROBE_IN0 => config_reg(64*1-1 DOWNTO 64*0),
PROBE_IN1 => config_reg(64*2-1 DOWNTO 64*1),
PROBE_IN2 => config_reg(64*3-1 DOWNTO 64*2),
PROBE_IN3 => config_reg(64*4-1 DOWNTO 64*3),
PROBE_IN4 => config_reg(64*5-1 DOWNTO 64*4),
PROBE_IN5 => config_reg(64*6-1 DOWNTO 64*5),
PROBE_IN6 => config_reg(64*7-1 DOWNTO 64*6),
PROBE_IN7 => x"00000000000000" & sPcs_pma_core_status, -- config_reg(64*8-1 DOWNTO 64*7),
PROBE_IN8 => cmd_fifo_q,
PROBE_OUT0 => dbg_vio_probe_out0
);
--dbg_ila1_inst : dbg_ila1
-- PORT MAP (
-- CLK => sys_clk,
-- PROBE0 => dbg_ila1_probe0,
-- PROBE1 => dbg_ila1_probe1
-- );
END GENERATE dbg_cores;
---------------------------------------------> debug : ILA and VIO (`Chipscope')
---------------------------------------------< UART/RS232
uart_cores : IF false GENERATE
uartio_inst : uartio
GENERIC MAP (
-- tick repetition frequency is (input freq) / (2**COUNTER_WIDTH / DIVISOR)
COUNTER_WIDTH => 16,
DIVISOR => 1208*2
)
PORT MAP (
CLK => clk_50MHz,
RESET => reset,
RX_DATA => uart_rx_data,
RX_RDY => uart_rx_rdy,
TX_DATA => x"00",
TX_EN => '1',
TX_RDY => dbg_ila_probe0(2),
-- serial lines
RX_PIN => '0',
TX_PIN => OPEN
);
--dbg_ila1_probe0(7 DOWNTO 0) <= uart_rx_data;
--dbg_ila1_probe0(8) <= uart_rx_rdy;
--dbg_ila1_probe0(9) <= USB_TX;
-- dbg_ila_probe0(63 DOWNTO 32) <= cmd_fifo_q(31 DOWNTO 0);
dbg_ila_probe0(31) <= cmd_fifo_empty;
dbg_ila_probe0(30) <= cmd_fifo_rdreq;
byte2cmd_inst : byte2cmd
PORT MAP (
CLK => clk_50MHz,
RESET => reset,
-- byte in
RX_DATA => uart_rx_data,
RX_RDY => uart_rx_rdy,
-- cmd out
CMD_FIFO_Q => OPEN,-- cmd_fifo_q,
CMD_FIFO_EMPTY => OPEN,-- cmd_fifo_empty,
CMD_FIFO_RDCLK => control_clk,
CMD_FIFO_RDREQ => '0' -- cmd_fifo_rdreq
);
END GENERATE uart_cores;
control_clk <= clk_100MHz;
control_interface_inst : control_interface
PORT MAP (
RESET => reset,
CLK => control_clk,
-- From FPGA to PC
FIFO_Q => control_fifo_q,
FIFO_EMPTY => control_fifo_empty,
FIFO_RDREQ => control_fifo_rdreq,
FIFO_RDCLK => control_fifo_rdclk,
-- From PC to FPGA, FWFT
CMD_FIFO_Q => cmd_fifo_q,
CMD_FIFO_EMPTY => cmd_fifo_empty,
CMD_FIFO_RDREQ => cmd_fifo_rdreq,
-- Digital I/O
CONFIG_REG => config_reg,
PULSE_REG => pulse_reg,
STATUS_REG => status_reg,
-- Memory interface
MEM_WE => control_mem_we,
MEM_ADDR => control_mem_addr,
MEM_DIN => control_mem_din,
MEM_DOUT => (OTHERS => '0'),
-- Data FIFO interface, FWFT
DATA_FIFO_Q => idata_data_fifo_dout,
DATA_FIFO_EMPTY => idata_data_fifo_empty,
DATA_FIFO_RDREQ => idata_data_fifo_rden,
DATA_FIFO_RDCLK => idata_data_fifo_rdclk
);
dbg_ila_probe0(18 DOWNTO 3) <= pulse_reg;
---------------------------------------------> UART/RS232
---------------------------------------------< ten_gig_eth
B14_L_N(5) <= '1'; -- TE0741 CLK_EN
B14_L_N(21) <= '1'; -- TE0741 EN_MGT
ten_gig_eth_cores : IF ENABLE_TEN_GIG_ETH GENERATE
ten_gig_eth_inst : ten_gig_eth
PORT MAP (
REFCLK_P => MGT_CLK3_P, -- 156.25MHz for transceiver
REFCLK_N => MGT_CLK3_N,
RESET => reset,
SFP_TX_P => SFP_TX_P,
SFP_TX_N => SFP_TX_N,
SFP_RX_P => SFP_RX_P,
SFP_RX_N => SFP_RX_N,
SFP_LOS => SFP_LOS_LS, -- loss of receiver signal
SFP_TX_DISABLE => sfp_tx_disable_i,
-- clk156.25 domain, clock generated by the core
CLK156p25 => clk156p25,
PCS_PMA_CORE_STATUS => sPcs_pma_core_status,
TX_STATISTICS_VECTOR => OPEN,
TX_STATISTICS_VALID => OPEN,
RX_STATISTICS_VECTOR => OPEN,
RX_STATISTICS_VALID => OPEN,
PAUSE_VAL => (OTHERS => '0'),
PAUSE_REQ => '0',
TX_IFG_DELAY => x"ff",
-- emac control interface
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- tx_wr_clk domain
TX_AXIS_FIFO_ARESETN => sTx_axis_fifo_aresetn,
Tx_AXIS_FIFO_ACLK => sTx_axis_fifo_aclk,
TX_AXIS_FIFO_TDATA => sTx_axis_fifo_tdata,
TX_AXIS_FIFO_TKEEP => sTx_axis_fifo_tkeep,
TX_AXIS_FIFO_TVALID => sTx_axis_fifo_tvalid,
TX_AXIS_FIFO_TLAST => sTx_axis_fifo_tlast,
TX_AXIS_FIFO_TREADY => sTx_axis_fifo_tready,
-- rx_rd_clk domain
RX_AXIS_FIFO_ARESETN => sRx_axis_fifo_aresetn,
RX_AXIS_FIFO_ACLK => sRx_axis_fifo_aclk,
RX_AXIS_FIFO_TDATA => sRx_axis_fifo_tdata,
RX_AXIS_FIFO_TKEEP => sRx_axis_fifo_tkeep,
RX_AXIS_FIFO_TVALID => sRx_axis_fifo_tvalid,
RX_AXIS_FIFO_TLAST => sRx_axis_fifo_tlast,
RX_AXIS_FIFO_TREADY => sRx_axis_fifo_tready
);
SFP_TX_DISABLE_N <= NOT sfp_tx_disable_i;
LED8Bit(7) <= sPcs_pma_core_status(0);
LED8Bit(6) <= NOT sfp_tx_disable_i;
LED8Bit(5) <= NOT SFP_LOS_LS;
s_axi_aclk <= clk_50MHz;
sTx_axis_fifo_aclk <= clk_200MHz;
sRx_axis_fifo_aclk <= sTx_axis_fifo_aclk;
s_axi_aresetn <= '1';
sTx_axis_fifo_aresetn <= '1';
-- sRx_axis_fifo_aresetn <= '1';
ten_gig_eth_packet_gen_inst : ten_gig_eth_packet_gen
PORT MAP (
RESET => reset,
MEM_CLK => control_clk,
MEM_WE => control_mem_we,
MEM_ADDR => control_mem_addr,
MEM_D => control_mem_din,
--
TX_AXIS_ACLK => sTx_axis_fifo_aclk,
TX_START => ten_gig_eth_tx_start,
TX_BYTES => config_reg(15 DOWNTO 0),
TX_AXIS_TDATA => OPEN, -- sTx_axis_fifo_tdata,
TX_AXIS_TKEEP => sTx_axis_fifo_tkeep,
TX_AXIS_TVALID => sTx_axis_fifo_tvalid,
TX_AXIS_TLAST => sTx_axis_fifo_tlast,
TX_AXIS_TREADY => sTx_axis_fifo_tready
);
ten_gig_eth_rx_parser_inst : ten_gig_eth_rx_parser
PORT MAP (
RESET => reset,
RX_AXIS_FIFO_ARESETN => sRx_axis_fifo_aresetn,
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK => sRx_axis_fifo_aclk,
RX_AXIS_FIFO_TDATA => sRx_axis_fifo_tdata,
RX_AXIS_FIFO_TKEEP => sRx_axis_fifo_tkeep,
RX_AXIS_FIFO_TVALID => sRx_axis_fifo_tvalid,
RX_AXIS_FIFO_TLAST => sRx_axis_fifo_tlast,
RX_AXIS_FIFO_TREADY => sRx_axis_fifo_tready,
-- Constants
SRC_MAC => x"000a3502a759",
SRC_IP => x"c0a80302",
SRC_PORT => x"ea62",
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q => tge_cmd_fifo_q,
CMD_FIFO_EMPTY => tge_cmd_fifo_empty,
CMD_FIFO_RDREQ => '1',
CMD_FIFO_RDCLK => clk_200MHz
);
ten_gig_eth_tx_start <= pulse_reg(0);
dbg_ila_probe0(0) <= clk156p25;
dbg_ila_probe0(1) <= ten_gig_eth_tx_start;
dbg_ila_probe1(79 DOWNTO 16) <= sTx_axis_fifo_tdata;
dbg_ila_probe1(15 DOWNTO 8) <= sTx_axis_fifo_tkeep;
dbg_ila_probe1(7) <= sTx_axis_fifo_tvalid;
dbg_ila_probe1(6) <= sTx_axis_fifo_tlast;
dbg_ila_probe1(5) <= sTx_axis_fifo_tready;
--dbg_ila_probe2(79 DOWNTO 16) <= sRx_axis_fifo_tdata;
--dbg_ila_probe2(79 DOWNTO 48) <= control_mem_addr;
--dbg_ila_probe2(47 DOWNTO 16) <= control_mem_din;
--dbg_ila_probe2(15 DOWNTO 8) <= sRx_axis_fifo_tkeep;
dbg_ila_probe2(7) <= sRx_axis_fifo_tvalid;
dbg_ila_probe2(6) <= sRx_axis_fifo_tlast;
dbg_ila_probe2(5) <= sRx_axis_fifo_tready;
dbg_ila_probe2(4) <= control_mem_we;
--
--dbg_ila_probe3(127 DOWNTO 0) <= tge_cmd_fifo_q;
--dbg_ila_probe3(128) <= tge_cmd_fifo_empty;
END GENERATE ten_gig_eth_cores;
---------------------------------------------> ten_gig_eth
---------------------------------------------< gtx / aurora
-- SFP_TX_DISABLE_N <= '1';
-- LED8Bit(0) <= NOT B14_L_P(19); -- NOT SFP_LOS_LS; -- SFP is plugged in.
LED8Bit(1) <= aurora_status(0); -- link up
aurora_64b66b_inst : aurora_64b66b
PORT MAP (
RESET => aurora_reset,
SYS_CLK => clk_100MHz,
MGT_REFCLK_P => SGMIICLK_Q0_P,
MGT_REFCLK_N => SGMIICLK_Q0_N,
-- Data interfaces are synchronous to USER_CLK
USER_CLK => aurora_user_clk,
MGT_REFCLK_BUFG_OUT => clk_sgmii,
-- TX AXI4 interface
S_AXI_TX_TDATA => aurora_tx_tdata,
S_AXI_TX_TVALID => aurora_tx_tvalid,
S_AXI_TX_TREADY => aurora_tx_tready,
-- RX AXI4 interface
M_AXI_RX_TDATA => aurora_rx_tdata,
M_AXI_RX_TVALID => aurora_rx_tvalid,
-- User flow control (UFC) TX
UFC_TX_REQ => aurora_ufc_tx_req,
S_AXI_UFC_TX_TDATA => aurora_ufc_tx_tdata,
UFC_TX_MS => aurora_ufc_tx_ms,
S_AXI_UFC_TX_TVALID => aurora_ufc_tx_tvalid,
S_AXI_UFC_TX_TREADY => aurora_ufc_tx_tready,
-- UFC RX
M_AXI_UFC_RX_TDATA => aurora_ufc_rx_tdata,
M_AXI_UFC_RX_TKEEP => aurora_ufc_rx_tkeep,
M_AXI_UFC_RX_TLAST => aurora_ufc_rx_tlast,
M_AXI_UFC_RX_TVALID => aurora_ufc_rx_tvalid,
UFC_IN_PROGRESSn => aurora_ufc_in_progress_n,
-- GTX pins
RXP => SMA_MGT_RX_P,
RXN => SMA_MGT_RX_N,
TXP => SMA_MGT_TX_P,
TXN => SMA_MGT_TX_N,
-- Status
STATUS => aurora_status
);
aurora_reset <= reset OR pulse_reg(15);
fifo_over_ufc_inst : fifo_over_ufc
PORT MAP (
RESET => aurora_reset,
AURORA_USER_CLK => aurora_user_clk,
AURORA_TX_REQ => aurora_ufc_tx_req,
AURORA_TX_MS => aurora_ufc_tx_ms,
AURORA_TX_TREADY => aurora_ufc_tx_tready,
AURORA_TX_TDATA => aurora_ufc_tx_tdata,
AURORA_TX_TVALID => aurora_ufc_tx_tvalid,
AURORA_RX_TDATA => aurora_ufc_rx_tdata,
AURORA_RX_TVALID => aurora_ufc_rx_tvalid,
FIFO_CLK => control_fifo_rdclk,
TX_FIFO_Q => aurora_ufc_tx_fifo_q,
TX_FIFO_WREN => aurora_ufc_tx_fifo_wren,
TX_FIFO_FULL => aurora_ufc_tx_fifo_full,
RX_FIFO_Q => control_fifo_q(31 DOWNTO 0),
RX_FIFO_RDEN => control_fifo_rdreq,
RX_FIFO_EMPTY => control_fifo_empty,
ERR => OPEN -- LED8Bit(1)
);
fifo_over_ufc_tx_fifo : fifo36x512
PORT MAP (
rst => aurora_reset,
wr_clk => control_fifo_rdclk,
rd_clk => control_clk,
din => x"0" & aurora_ufc_tx_fifo_q,
wr_en => aurora_ufc_tx_fifo_wren,
rd_en => cmd_fifo_rdreq,
dout => cmd_fifo_q,
full => aurora_ufc_tx_fifo_full,
empty => cmd_fifo_empty
);
sdm_adc_data_aggregator_inst : sdm_adc_data_aggregator
GENERIC MAP (
NCH_ADC => 20,
ADC_CYC => 20,
NCH_SDM => 19,
SDM_CYC => 4
)
PORT MAP (
RESET => reset,
CLK => control_clk,
ADC_Q => adc_dout,
ADC_Q_VALID => adc_dout_valid,
SDM_Q => tms_sdm_out,
SDM_Q_VALID => tms_sdm_out_valid,
DOUT => tms_sdm_adc_dout,
DOUT_VALID => tms_sdm_adc_dout_valid,
USER_CLK => aurora_user_clk,
S_AXI_TX_TDATA => aurora_tx_tdata,
S_AXI_TX_TVALID => aurora_tx_tvalid,
S_AXI_TX_TREADY => aurora_tx_tready,
FIFO_FULL => sdm_adc_data_aggregator_fifo_full
);
-- -- debug
-- aurora_ufc_tx_req <= pulse_reg(8);
-- ufc_tx_tvalid_edge_sync_inst : edge_sync
-- GENERIC MAP (
-- EDGE => '0'
-- )
-- PORT MAP (
-- RESET => reset,
-- CLK => aurora_user_clk,
-- EI => aurora_ufc_tx_req,
-- SO => aurora_ufc_tx_tvalid
-- );
-- aurora_ufc_tx_tdata <= x"0000_0000_0000" & config_reg(30*16+15 DOWNTO 30*16);
-- aurora_ufc_tx_ms <= config_reg(29*16+7 DOWNTO 29*16); -- don't reverse bit-order here
--
dbg_ila1_inst : dbg_ila1
PORT MAP (
CLK => clk_200MHz, -- aurora_user_clk,
PROBE0 => dbg_ila1_probe0,
PROBE1 => dbg_ila1_probe1
);
-- dbg_ila1_probe0 <=
-- "00000" & aurora_status(2) & aurora_status(1) & aurora_status(0)
-- & aurora_reset & aurora_ufc_in_progress_n & aurora_ufc_rx_tlast & aurora_ufc_rx_tvalid
-- & aurora_ufc_tx_req & aurora_ufc_tx_tready & aurora_ufc_tx_tvalid & aurora_tx_tready;
dbg_ila1_probe0 <= tms_sdm_adc_dout(16*19+15 DOWNTO 16*19);
-- dbg_ila1_probe1 <= aurora_ufc_rx_tdata(7 DOWNTO 0) & aurora_ufc_tx_tdata(7 DOWNTO 0);
dbg_ila1_probe1 <= aurora_tx_tdata(63 DOWNTO 63-12) & sdm_adc_data_aggregator_fifo_full & aurora_tx_tvalid & aurora_tx_tready;
---------------------------------------------> gtx / aurora
---------------------------------------------< I2C
i2c_sda_iobuf_inst : IOBUF
GENERIC MAP(
DRIVE => 12,
SLEW => "SLOW"
)
PORT MAP(
O => i2c_sda_in,
IO => I2C_SDA,
I => i2c_sda_out,
T => i2c_sda_t
);
i2c_scl_iobuf_inst : IOBUF
GENERIC MAP(
DRIVE => 12,
SLEW => "SLOW"
)
PORT MAP(
O => OPEN,
IO => I2C_SCL,
I => i2c_scl_out,
T => '0'
);
-- External clock IC
si5338_clk_div_inst : clk_div
GENERIC MAP (
WIDTH => 32,
PBITS => 8
)
PORT MAP (
RESET => reset,
CLK => clk156p25,
DIV => x"1b",
CLK_DIV => LED8Bit(0)
);
-- Temperature and voltage sensors
i2c1_sda_iobuf_inst : IOBUF
GENERIC MAP(
DRIVE => 12,
SLEW => "SLOW"
)
PORT MAP(
O => i2c1_sda_in,
IO => B14_L_P(19),
I => i2c1_sda_out,
T => i2c1_sda_t
);
i2c1_scl_iobuf_inst : IOBUF
GENERIC MAP(
DRIVE => 12,
SLEW => "SLOW"
)
PORT MAP(
O => OPEN,
IO => B14_L_P(14),
I => i2c1_scl_out,
T => '0'
);
i2c1_master_inst : i2c_master
GENERIC MAP (
INPUT_CLK_FREQENCY => 100_000_000,
BUS_CLK_FREQUENCY => 100_000
)
PORT MAP (
CLK => control_clk,
RESET => reset,
START => pulse_reg(2),
MODE => config_reg(16*2+1 DOWNTO 16*2),
SL_RW => config_reg(16*3+15),
SL_ADDR => config_reg(16*3+14 DOWNTO 16*3+8),
REG_ADDR => config_reg(16*3+7 DOWNTO 16*3),
WR_DATA0 => config_reg(16*4+15 DOWNTO 16*4+8),
WR_DATA1 => config_reg(16*4+7 DOWNTO 16*4),
RD_DATA0 => status_reg(16*0+15 DOWNTO 16*0+8),
RD_DATA1 => status_reg(16*0+7 DOWNTO 16*0),
BUSY => OPEN,
ACK_ERROR => OPEN,
SDA_in => i2c1_sda_in,
SDA_out => i2c1_sda_out,
SDA_t => i2c1_sda_t,
SCL => i2c1_scl_out
);
---------------------------------------------> I2C
---------------------------------------------< shiftreg driver for DAC8568
B14_L_P(21) <= dac_din;
B14_L_P(20) <= dac_sclk;
B14_L_N(23) <= dac_sync_n;
dac_din <= spi_dout;
dac_sclk <= spi_sclk;
dac_sync_n <= spi_sync_n;
dac8568_inst : fifo2shiftreg
GENERIC MAP (
DATA_WIDTH => 32, -- parallel data width
CLK_DIV_WIDTH => 16,
DELAY_AFTER_SYNCn => 0, -- number of SCLK cycles' wait after falling edge OF SYNCn
SCLK_IDLE_LEVEL => '0', -- High or Low for SCLK when not switching
DOUT_DRIVE_EDGE => '1', -- 1/0 rising/falling edge of SCLK drives new DOUT bit
DIN_CAPTURE_EDGE => '0' -- 1/0 rising/falling edge of SCLK captures new DIN bit
)
PORT MAP (
CLK => control_clk, -- clock
RESET => reset, -- reset
-- input data interface
WR_CLK => control_clk, -- FIFO write clock
DINFIFO => config_reg(16*1+15 DOWNTO 16*1),
WR_EN => '0',
WR_PULSE => pulse_reg(1), -- one pulse writes one word, regardless of pulse duration
FULL => OPEN,
-- captured data
BUSY => OPEN,
DATAOUT => OPEN,
-- serial interface
CLK_DIV => x"0006",
SCLK => spi_sclk,
DOUT => spi_dout,
SYNCn => spi_sync_n,
DIN => spi_din
);
---------------------------------------------> shiftreg driver for DAC8568
---------------------------------------------< TMS serial io
B14_L_N(4) <= tms_pwr_on;
B14_L_P(4) <= tms_sio_a(2);
B14_L_N(13) <= tms_sio_a(1);
B14_L_P(13) <= tms_sio_a(0);
B14_L_P(23) <= tms_sdi;
tms_sdo <= B14_L_N(19);
B14_L_P(0) <= tms_sck;
tms_pwr_on <= config_reg(16*0+0);
tms_sio_a <= config_reg(16*13+8+tms_sio_a'length-1 DOWNTO 16*13+8);
tms_sio_drive_inst : shiftreg_drive
GENERIC MAP (
DATA_WIDTH => 130, -- parallel data width
CLK_DIV_WIDTH => 16,
DELAY_AFTER_SYNCn => 0, -- number of SCLK cycles' wait after falling edge OF SYNCn
SCLK_IDLE_LEVEL => '1', -- High or Low for SCLK when not switching
DOUT_DRIVE_EDGE => '0', -- 1/0 rising/falling edge of SCLK drives new DOUT bit
DIN_CAPTURE_EDGE => '1' -- 1/0 rising/falling edge of SCLK captures new DIN bit
)
PORT MAP (
CLK => control_clk, -- clock
RESET => reset, -- reset
-- internal data interface
CLK_DIV => x"00" & "00" & config_reg(16*13+7 DOWNTO 16*13+2), -- SCLK freq is CLK / 2**(CLK_DIV)
DATAIN => config_reg(16*13+1 DOWNTO 16*5),
START => pulse_reg(3),
BUSY => status_reg(16*9+2),
DATAOUT => status_reg(16*9+1 DOWNTO 16*1),
-- external serial interface
SCLK => tms_sck,
DOUT => tms_sdi,
SYNCn => OPEN,
DIN => tms_sdo
);
---------------------------------------------> TMS serial io
---------------------------------------------< TMS
-- TMS reset, also function as serial io load
tms_reset_obufds_inst : OBUFDS
GENERIC MAP(
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
)
PORT MAP (
O => B13_L_P(3),
OB => B13_L_N(3),
I => tms_reset
);
tms_reset_width_pulse_sync_inst : width_pulse_sync
GENERIC MAP (
DATA_WIDTH => 8,
MODE => 0
)
PORT MAP (
RESET => reset,
CLK => control_clk,
PW => x"ff",
START => pulse_reg(0),
BUSY => OPEN,
CLKO => control_clk,
RSTO => OPEN,
PO => tms_reset
);
-- TMS SDM
B12_L_P(0) <= tms_sdm_clk_src_sel;
tms_sdm_clk_src_sel <= config_reg(16*0+1);
tms_sdm_clkff_div <= config_reg(16*0+11 DOWNTO 16*0+8);
tms_sdm_recv_inst : tms_sdm_recv
GENERIC MAP (
NCH => 19
)
PORT MAP (
RESET => reset,
CLK => control_clk, -- DELAY_* must be synchronous to this clock
REFCLK => clk_200MHz, -- REFCLK (200MHz) for IDELAYCTRL
DELAY_CHANNEL => config_reg(16*14+15 DOWNTO 16*14+8), -- input iodelay channel selection
DELAY_VALUE => config_reg(16*14+4 DOWNTO 16*14), -- input iodelay value
DELAY_UPDATE => pulse_reg(4), -- a pulse to update the delay value
CLKFF_DIV => tms_sdm_clkff_div,
CLKFF_P => B12_L_P(16),
CLKFF_N => B12_L_N(16),
CLK_LPBK_P => B12_L_P(12),
CLK_LPBK_N => B12_L_N(12),
CLK_LPBK => tms_sdm_clk_lpbk,
SDM_OUT1_P => tms_sdm_out1_p,
SDM_OUT1_N => tms_sdm_out1_n,
SDM_OUT2_P => tms_sdm_out2_p,
SDM_OUT2_N => tms_sdm_out2_n,
DOUT => tms_sdm_out,
DOUT_VALID => tms_sdm_out_valid
);
tms_sdm_out1_p <= (
0 => B12_L_P(18),
1 => B12_L_P(9),
2 => B12_L_P(20),
3 => B13_L_P(23),
4 => B13_L_P(21),
5 => B13_L_P(12),
6 => B12_L_P(5),
7 => B12_L_P(7),
8 => B12_L_P(21),
9 => B12_L_P(24),
10 => B13_L_P(6),
11 => B13_L_P(9),
12 => B13_L_P(16),
13 => B13_L_P(22),
14 => B13_L_P(10),
15 => B13_L_P(8),
16 => B13_L_P(4),
17 => B12_L_P(11),
18 => B12_L_P(13)
);
tms_sdm_out1_n <= (
0 => B12_L_N(18),
1 => B12_L_N(9),
2 => B12_L_N(20),
3 => B13_L_N(23),
4 => B13_L_N(21),
5 => B13_L_N(12),
6 => B12_L_N(5),
7 => B12_L_N(7),
8 => B12_L_N(21),
9 => B12_L_N(24),
10 => B13_L_N(6),
11 => B13_L_N(9),
12 => B13_L_N(16),
13 => B13_L_N(22),
14 => B13_L_N(10),
15 => B13_L_N(8),
16 => B13_L_N(4),
17 => B12_L_N(11),
18 => B12_L_N(13)
);
tms_sdm_out2_p <= (
0 => B12_L_P(17),
1 => B12_L_P(8),
2 => B12_L_P(22),
3 => B13_L_P(13),
4 => B13_L_P(11),
5 => B13_L_P(15),
6 => B12_L_P(3),
7 => B12_L_P(10),
8 => B12_L_P(23),
9 => B12_L_P(19),
10 => B13_L_P(17),
11 => B13_L_P(18),
12 => B13_L_P(14),
13 => B13_L_P(24),
14 => B13_L_P(7),
15 => B13_L_P(20),
16 => B13_L_P(2),
17 => B12_L_P(2),
18 => B12_L_P(14)
);
tms_sdm_out2_n <= (
0 => B12_L_N(17),
1 => B12_L_N(8),
2 => B12_L_N(22),
3 => B13_L_N(13),
4 => B13_L_N(11),
5 => B13_L_N(15),
6 => B12_L_N(3),
7 => B12_L_N(10),
8 => B12_L_N(23),
9 => B12_L_N(19),
10 => B13_L_N(17),
11 => B13_L_N(18),
12 => B13_L_N(14),
13 => B13_L_N(24),
14 => B13_L_N(7),
15 => B13_L_N(20),
16 => B13_L_N(2),
17 => B12_L_N(2),
18 => B12_L_N(14)
);
-- ADC, external, LTC2325-16
B16_L_N(6) <= adc_clk_src_sel;
B16_L_N(19) <= adc_clk_src_sel;
B12_L_P(25) <= adc_sdrn_ddr;
adc_clk_src_sel <= config_reg(16*0+2);
adc_sdrn_ddr <= config_reg(16*0+3);
adc_clkff_div <= config_reg(16*0+15 DOWNTO 16*0+12);
adc_cnv_sipo_inst : adc_cnv_sipo
GENERIC MAP (
NCH => 20
)
PORT MAP (
RESET => reset,
CLK => control_clk, -- DELAY_* must be synchronous to this clock
REFCLK => clk_200MHz, -- REFCLK (200MHz) for IDELAYCTRL
DELAY_CHANNEL => config_reg(16*14+15 DOWNTO 16*14+8), -- ADC data input iodelay channel selection
DELAY_VALUE => config_reg(16*14+4 DOWNTO 16*14), -- ADC data input iodelay value
DELAY_UPDATE => pulse_reg(5), -- a pulse to update the delay value
CLKFF_DIV => adc_clkff_div,
CLKFF_P => B16_L_P(13),
CLKFF_N => B16_L_N(13),
CLK_LPBK_P => B16_L_P(12),
CLK_LPBK_N => B16_L_N(12),
CLK_LPBK => adc_clk0_lpbk,
CNV_N_P => B16_L_P(17),
CNV_N_N => B16_L_N(17),
CNV_N => adc_cnv_n,
INPUTS_P => adc_sdo_p,
INPUTS_N => adc_sdo_n,
INPUTS_OUT => adc_sdo,
DOUT => adc_dout,
DOUT_VALID => adc_dout_valid
);
adc_sdo_p <= (
0 => B12_L_P(4),
1 => B12_L_P(1),
2 => B12_L_P(6),
3 => B15_L_P(23),
4 => B12_L_P(15),
5 => B15_L_P(21),
6 => B15_L_P(14),
7 => B15_L_P(12),
8 => B15_L_P(13),
9 => B15_L_P(11),
10 => B15_L_P(5),
11 => B15_L_P(20),
12 => B16_L_P(18),
13 => B15_L_P(7),
14 => B16_L_P(14),
15 => B16_L_P(23),
16 => B16_L_P(11),
17 => B16_L_P(21),
18 => B13_L_P(5),
19 => B13_L_P(1)
);
adc_sdo_n <= (
0 => B12_L_N(4),
1 => B12_L_N(1),
2 => B12_L_N(6),
3 => B15_L_N(23),
4 => B12_L_N(15),
5 => B15_L_N(21),
6 => B15_L_N(14),
7 => B15_L_N(12),
8 => B15_L_N(13),
9 => B15_L_N(11),
10 => B15_L_N(5),
11 => B15_L_N(20),
12 => B16_L_N(18),
13 => B15_L_N(7),
14 => B16_L_N(14),
15 => B16_L_N(23),
16 => B16_L_N(11),
17 => B16_L_N(21),
18 => B13_L_N(5),
19 => B13_L_N(1)
);
--
-- dbg_ila1_probe0 <= adc_dout(16*19+15 DOWNTO 16*19);
-- dbg_ila1_probe1 <= tms_sdm_out(3 DOWNTO 0) & tms_sdm_out_valid & tms_sdm_clk_lpbk & '0' & sdm_adc_data_aggregator_fifo_full
-- & i2c1_sda_in & i2c1_scl_out & tms_sck & adc_dout_valid
-- & adc_cnv_n & adc_clk0_lpbk & adc_sdo(19) & adc_sdo(0);
---------------------------------------------> TMS
-- clock output
refout_clk_div_inst : clk_div
PORT MAP (
RESET => reset,
CLK => idata_adc_data_clk,
DIV => config_reg(16*15+3 DOWNTO 16*15),
CLK_DIV => idata_adc_refout_clkdiv
);
clk_fwd_inst : clk_fwd -- idata_adc_refout_clkdiv
PORT MAP (R => reset, I => clk156p25, O => OPEN);
clk_fwd_inst1 : clk_fwd GENERIC MAP (INV => true)
PORT MAP (R => reset, I => clk156p25, O => OPEN);
clk_fwd_inst2 : clk_fwd GENERIC MAP (INV => true)
PORT MAP (R => reset, I => idata_adc_data_clk, O => OPEN);
-- capture the rising edge of trigger
trig_edge_sync_inst : edge_sync
PORT MAP (
RESET => reset,
CLK => control_clk,
EI => idata_trig_in,
SO => idata_trig_synced
);
idata_trig_allow <= config_reg(32*6+30);
idata_data_wr_start <= pulse_reg(3) OR (idata_trig_synced AND idata_trig_allow
AND (NOT idata_data_wr_busy)
AND (NOT idata_data_wr_wrapped));
--led_obufs : FOR i IN 0 TO 7 GENERATE
-- led_obuf : OBUF
-- PORT MAP (
-- I => usr_data_output(i),
-- O => LED8Bit(i)
-- );
--END GENERATE led_obufs;
--LED8Bit(5 DOWNTO 1) <= (OTHERS => '0');
END Behavioral;
| bsd-3-clause | 2f07e32d96f5cfcd41f72d126360c433 | 0.507408 | 3.320961 | false | false | false | false |
Andy46/OV7670-VHDL | OV7670/src/mod_7SEG/mod_bcd.vhd | 1 | 1,668 | ----------------------------------------------------------------------------------
-- Company: *
-- Engineer: Andres Gamboa
--
-- Create Date: 09:50:50 10/11/2013
-- Design Name:
-- Module Name: sevseg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod_bcd is
port ( bcd : in std_logic_vector(3 downto 0);
g : in std_logic;
segment7 : out std_logic_vector(6 downto 0));
end mod_bcd;
architecture Behavioral of mod_bcd is
begin
process(bcd, g)
begin
if g = '0' then
segment7 <= "0111111"; -- '-'
else
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
when "1010"=> segment7 <="0001000"; -- 'A'
when "1011"=> segment7 <="0000011"; -- 'B'
when "1100"=> segment7 <="1000110"; -- 'C'
when "1101"=> segment7 <="0100001"; -- 'D'
when "1110"=> segment7 <="0000110"; -- 'E'
when "1111"=> segment7 <="0001110"; -- 'F'
when others=> segment7 <="0111111"; -- '-'
end case;
end if;
end process;
end Behavioral; | mit | b2d102580d98e7123eee1e246a85a97d | 0.514388 | 3.226306 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/error_detect.vhd | 4 | 9,545 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:52 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: error_detect_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.1 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- ERROR_DETECT
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description : The ERROR_DETECT module monitors the MGT to detect hard
-- errors. It accumulates the Soft errors according to the
-- leaky bucket algorithm described in the Aurora
-- Specification to detect Hard errors. All errors are
-- reported to the Global Logic Interface.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.AURORA.all;
entity ERROR_DETECT is
port (
-- Lane Init SM Interface
ENABLE_ERROR_DETECT : in std_logic;
HARD_ERROR_RESET : out std_logic;
-- Global Logic Interface
SOFT_ERROR : out std_logic;
HARD_ERROR : out std_logic;
-- MGT Interface
RX_DISP_ERR : in std_logic_vector(1 downto 0);
TX_K_ERR : in std_logic_vector(1 downto 0);
RX_NOT_IN_TABLE : in std_logic_vector(1 downto 0);
RX_BUF_STATUS : in std_logic;
TX_BUF_ERR : in std_logic;
RX_REALIGN : in std_logic;
-- System Interface
USER_CLK : in std_logic
);
end ERROR_DETECT;
architecture RTL of ERROR_DETECT is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal HARD_ERROR_RESET_Buffer : std_logic;
signal SOFT_ERROR_Buffer : std_logic;
signal HARD_ERROR_Buffer : std_logic;
-- Internal Register Declarations --
signal count_r : std_logic_vector(0 to 1);
signal bucket_full_r : std_logic;
signal soft_error_r : std_logic_vector(0 to 1);
signal good_count_r : std_logic_vector(0 to 1);
signal soft_error_flop_r : std_logic; -- Traveling flop for timing.
signal hard_error_flop_r : std_logic; -- Traveling flop for timing.
begin
HARD_ERROR_RESET <= HARD_ERROR_RESET_Buffer;
SOFT_ERROR <= SOFT_ERROR_Buffer;
HARD_ERROR <= HARD_ERROR_Buffer;
-- Main Body of Code --
-- Detect Soft Errors
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (ENABLE_ERROR_DETECT = '1') then
soft_error_r(0) <= RX_DISP_ERR(1) or RX_NOT_IN_TABLE(1) after DLY;
soft_error_r(1) <= RX_DISP_ERR(0) or RX_NOT_IN_TABLE(0) after DLY;
else
soft_error_r(0) <= '0' after DLY;
soft_error_r(1) <= '0' after DLY;
end if;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
soft_error_flop_r <= soft_error_r(0) or
soft_error_r(1) after DLY;
SOFT_ERROR_Buffer <= soft_error_flop_r after DLY;
end if;
end process;
-- Detect Hard Errors
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (ENABLE_ERROR_DETECT = '1') then
hard_error_flop_r <= std_bool(TX_K_ERR /= "00") or
RX_BUF_STATUS or
TX_BUF_ERR or
RX_REALIGN or
bucket_full_r after DLY;
HARD_ERROR_Buffer <= hard_error_flop_r after DLY;
else
hard_error_flop_r <= '0' after DLY;
HARD_ERROR_Buffer <= '0' after DLY;
end if;
end if;
end process;
-- Assert hard error reset when there is a hard error. This assignment
-- just renames the two fanout branches of the hard error signal.
HARD_ERROR_RESET_Buffer <= hard_error_flop_r;
-- Leaky Bucket --
-- Good cycle counter: it takes 2 consecutive good cycles to remove a demerit from
-- the leaky bucket
process (USER_CLK)
variable err_vec : std_logic_vector(3 downto 0);
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (ENABLE_ERROR_DETECT = '0') then
good_count_r <= "01" after DLY;
else
err_vec := soft_error_r & good_count_r;
case err_vec is
when "0000" => good_count_r <= "01" after DLY;
when "0001" => good_count_r <= "10" after DLY;
when "0010" => good_count_r <= "01" after DLY;
when "0011" => good_count_r <= "01" after DLY;
when others => good_count_r <= "00" after DLY;
end case;
end if;
end if;
end process;
-- Perform the leaky bucket algorithm using an up/down counter. A drop is
-- added to the bucket whenever a soft error occurs and is allowed to leak
-- out whenever the good cycles counter reaches 2. Once the bucket fills
-- (3 drops) it stays full until it is reset by disabling and then enabling
-- the error detection circuit.
process (USER_CLK)
variable leaky_bucket : std_logic_vector(4 downto 0);
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (ENABLE_ERROR_DETECT = '0') then
count_r <= "00" after DLY;
else
leaky_bucket := soft_error_r & good_count_r(0) & count_r;
case leaky_bucket is
when "00000" => count_r <= count_r after DLY;
when "00001" => count_r <= count_r after DLY;
when "00010" => count_r <= count_r after DLY;
when "00011" => count_r <= count_r after DLY;
when "00100" => count_r <= "00" after DLY;
when "00101" => count_r <= "00" after DLY;
when "00110" => count_r <= "01" after DLY;
when "00111" => count_r <= "11" after DLY;
when "01000" => count_r <= "01" after DLY;
when "01001" => count_r <= "10" after DLY;
when "01010" => count_r <= "11" after DLY;
when "01011" => count_r <= "11" after DLY;
when "01100" => count_r <= "01" after DLY;
when "01101" => count_r <= "10" after DLY;
when "01110" => count_r <= "11" after DLY;
when "01111" => count_r <= "11" after DLY;
when "10000" => count_r <= "01" after DLY;
when "10001" => count_r <= "10" after DLY;
when "10010" => count_r <= "11" after DLY;
when "10011" => count_r <= "11" after DLY;
when "10100" => count_r <= "01" after DLY;
when "10101" => count_r <= "10" after DLY;
when "10110" => count_r <= "11" after DLY;
when "10111" => count_r <= "11" after DLY;
when "11000" => count_r <= "10" after DLY;
when "11001" => count_r <= "11" after DLY;
when "11010" => count_r <= "11" after DLY;
when "11011" => count_r <= "11" after DLY;
when "11100" => count_r <= "10" after DLY;
when "11101" => count_r <= "11" after DLY;
when "11110" => count_r <= "11" after DLY;
when "11111" => count_r <= "11" after DLY;
when others => count_r <= "XX" after DLY;
end case;
end if;
end if;
end process;
-- Detect when the bucket is full and register the signal.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
bucket_full_r <= std_bool(count_r = "11") after DLY;
end if;
end process;
end RTL;
| bsd-2-clause | 4dbcdd6e9a0bf717eeb7b084f8def702 | 0.50791 | 4.02403 | false | false | false | false |
nxt4hll/roccc-2.0 | roccc-compiler/src/llvm-2.3/include/rocccLibrary/TripleSingleWordVoter.vhd | 1 | 1,514 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SingleWordVoter is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
inputReady : in STD_LOGIC;
outputReady : out STD_LOGIC;
done : out STD_LOGIC;
stall : in STD_LOGIC;
error : out STD_LOGIC;
val0_in : in STD_LOGIC_VECTOR(31 downto 0);
val1_in : in STD_LOGIC_VECTOR(31 downto 0);
val2_in : in STD_LOGIC_VECTOR(31 downto 0);
val0_out : out STD_LOGIC_VECTOR(31 downto 0);
val1_out : out STD_LOGIC_VECTOR(31 downto 0);
val2_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end SingleWordVoter;
architecture Behavioral of SingleWordVoter is
begin
process(clk, rst)
begin
if( rst = '1' ) then
elsif( clk'event and clk = '1' ) then
val0_out <= (others=>'0');
val1_out <= (others=>'0');
val2_out <= (others=>'0');
error <= '1';
if( val0_in = val1_in ) then
val0_out <= val0_in;
val1_out <= val0_in;
val2_out <= val0_in;
error <= '0';
elsif( val1_in = val2_in ) then
val0_out <= val1_in;
val1_out <= val1_in;
val2_out <= val1_in;
error <= '0';
elsif( val2_in = val0_in ) then
val0_out <= val2_in;
val1_out <= val2_in;
val2_out <= val2_in;
error <= '0';
end if;
end if;
end process;
end Behavioral;
| epl-1.0 | d927b40a64b3e67f4c3908f92f4082d1 | 0.611625 | 2.872865 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo16_patch/fifo16_patch_top.vhd | 9 | 11,515 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 7bde67d5c68a3284ec212f0ef290b18c | 0.930352 | 1.894849 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/user_io_board_controller_plbw_v1_01_a/hdl/vhdl/user_io_board_controller.vhd | 4 | 452,905 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_453ed16ba8e84295.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_453ed16ba8e84295. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_453ed16ba8e84295 IS
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
END adder_subtracter_virtex2p_7_0_453ed16ba8e84295;
ARCHITECTURE adder_subtracter_virtex2p_7_0_453ed16ba8e84295_a OF adder_subtracter_virtex2p_7_0_453ed16ba8e84295 IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_453ed16ba8e84295 use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 1,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 8,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 1,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 0,
c_has_aclr => 0,
c_out_width => 9,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 9,
c_a_width => 9,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_453ed16ba8e84295_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_7182743c9e7adf5e.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_7182743c9e7adf5e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_7182743c9e7adf5e IS
port (
A: IN std_logic_VECTOR(4 downto 0);
B: IN std_logic_VECTOR(4 downto 0);
S: OUT std_logic_VECTOR(4 downto 0));
END adder_subtracter_virtex2p_7_0_7182743c9e7adf5e;
ARCHITECTURE adder_subtracter_virtex2p_7_0_7182743c9e7adf5e_a OF adder_subtracter_virtex2p_7_0_7182743c9e7adf5e IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port (
A: IN std_logic_VECTOR(4 downto 0);
B: IN std_logic_VECTOR(4 downto 0);
S: OUT std_logic_VECTOR(4 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_7182743c9e7adf5e use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 1,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 4,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 1,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 0,
c_has_aclr => 0,
c_out_width => 5,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 5,
c_a_width => 5,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_7182743c9e7adf5e_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3.vhd when simulating
-- the core, adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3 IS
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
END adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3;
ARCHITECTURE adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3_a OF adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3 IS
-- synthesis translate_off
component wrapped_adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port (
A: IN std_logic_VECTOR(8 downto 0);
B: IN std_logic_VECTOR(8 downto 0);
S: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3 use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral)
generic map(
c_has_bypass_with_cin => 0,
c_a_type => 0,
c_has_sclr => 0,
c_sync_priority => 1,
c_has_aset => 0,
c_has_b_out => 0,
c_has_s => 1,
c_has_q => 0,
c_bypass_enable => 0,
c_b_constant => 0,
c_has_ovfl => 0,
c_high_bit => 8,
c_latency => 0,
c_sinit_val => "0",
c_has_bypass => 0,
c_pipe_stages => 1,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 0,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 1,
c_b_value => "0",
c_add_mode => 1,
c_has_aclr => 0,
c_out_width => 9,
c_ainit_val => "0000",
c_low_bit => 0,
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 9,
c_a_width => 9,
c_sync_enable => 0,
c_has_ce => 1,
c_has_c_in => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port map (
A => A,
B => B,
S => S);
-- synthesis translate_on
END adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_23542cbcca0efa2e.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_23542cbcca0efa2e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_23542cbcca0efa2e IS
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_23542cbcca0efa2e;
ARCHITECTURE binary_counter_virtex2p_7_0_23542cbcca0efa2e_a OF binary_counter_virtex2p_7_0_23542cbcca0efa2e IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_23542cbcca0efa2e
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_23542cbcca0efa2e use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 4,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_23542cbcca0efa2e
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_23542cbcca0efa2e_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_32a1863440903b9d.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_32a1863440903b9d. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_32a1863440903b9d IS
port (
Q: OUT std_logic_VECTOR(14 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_32a1863440903b9d;
ARCHITECTURE binary_counter_virtex2p_7_0_32a1863440903b9d_a OF binary_counter_virtex2p_7_0_32a1863440903b9d IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_32a1863440903b9d
port (
Q: OUT std_logic_VECTOR(14 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_32a1863440903b9d use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 15,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_32a1863440903b9d
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_32a1863440903b9d_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_77cea312f82499f0.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_77cea312f82499f0. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_77cea312f82499f0 IS
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(3 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_77cea312f82499f0;
ARCHITECTURE binary_counter_virtex2p_7_0_77cea312f82499f0_a OF binary_counter_virtex2p_7_0_77cea312f82499f0 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_77cea312f82499f0
port (
Q: OUT std_logic_VECTOR(3 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(3 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_77cea312f82499f0 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 4,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 1,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "1111",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "1111",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 1,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_77cea312f82499f0
port map (
Q => Q,
CLK => CLK,
LOAD => LOAD,
L => L,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_77cea312f82499f0_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_950e4ab582797264.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_950e4ab582797264. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_950e4ab582797264 IS
port (
Q: OUT std_logic_VECTOR(17 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_950e4ab582797264;
ARCHITECTURE binary_counter_virtex2p_7_0_950e4ab582797264_a OF binary_counter_virtex2p_7_0_950e4ab582797264 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_950e4ab582797264
port (
Q: OUT std_logic_VECTOR(17 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_950e4ab582797264 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 18,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "0000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "0000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_950e4ab582797264
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_950e4ab582797264_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_a22528b4c55dc1cd.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_a22528b4c55dc1cd. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_a22528b4c55dc1cd IS
port (
Q: OUT std_logic_VECTOR(13 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_a22528b4c55dc1cd;
ARCHITECTURE binary_counter_virtex2p_7_0_a22528b4c55dc1cd_a OF binary_counter_virtex2p_7_0_a22528b4c55dc1cd IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port (
Q: OUT std_logic_VECTOR(13 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_a22528b4c55dc1cd use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 14,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "11111111111111",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "11111111111111",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_a22528b4c55dc1cd_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_b0a257f5389d649a.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_b0a257f5389d649a. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_b0a257f5389d649a IS
port (
Q: OUT std_logic_VECTOR(6 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_b0a257f5389d649a;
ARCHITECTURE binary_counter_virtex2p_7_0_b0a257f5389d649a_a OF binary_counter_virtex2p_7_0_b0a257f5389d649a IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_b0a257f5389d649a
port (
Q: OUT std_logic_VECTOR(6 downto 0);
CLK: IN std_logic;
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_b0a257f5389d649a use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 7,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 0,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "1111111",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "1111111",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "0001",
c_has_l => 0,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_b0a257f5389d649a
port map (
Q => Q,
CLK => CLK,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_b0a257f5389d649a_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file binary_counter_virtex2p_7_0_b511f9871581ee23.vhd when simulating
-- the core, binary_counter_virtex2p_7_0_b511f9871581ee23. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY binary_counter_virtex2p_7_0_b511f9871581ee23 IS
port (
Q: OUT std_logic_VECTOR(2 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(2 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
END binary_counter_virtex2p_7_0_b511f9871581ee23;
ARCHITECTURE binary_counter_virtex2p_7_0_b511f9871581ee23_a OF binary_counter_virtex2p_7_0_b511f9871581ee23 IS
-- synthesis translate_off
component wrapped_binary_counter_virtex2p_7_0_b511f9871581ee23
port (
Q: OUT std_logic_VECTOR(2 downto 0);
CLK: IN std_logic;
LOAD: IN std_logic;
L: IN std_logic_VECTOR(2 downto 0);
CE: IN std_logic;
SINIT: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_binary_counter_virtex2p_7_0_b511f9871581ee23 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral)
generic map(
c_count_mode => 0,
c_load_enable => 1,
c_has_aset => 0,
c_load_low => 0,
c_count_to => "1111111111111111",
c_sync_priority => 1,
c_has_iv => 0,
c_restrict_count => 0,
c_has_sclr => 0,
c_width => 3,
c_has_q_thresh1 => 0,
c_enable_rlocs => 0,
c_has_q_thresh0 => 0,
c_thresh1_value => "1111111111111111",
c_has_load => 1,
c_thresh_early => 1,
c_has_up => 0,
c_has_thresh1 => 0,
c_has_thresh0 => 0,
c_ainit_val => "000",
c_has_ce => 1,
c_pipe_stages => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_sinit_val => "000",
c_has_sset => 0,
c_has_sinit => 1,
c_count_by => "001",
c_has_l => 1,
c_thresh0_value => "1111111111111111");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_binary_counter_virtex2p_7_0_b511f9871581ee23
port map (
Q => Q,
CLK => CLK,
LOAD => LOAD,
L => L,
CE => CE,
SINIT => SINIT);
-- synthesis translate_on
END binary_counter_virtex2p_7_0_b511f9871581ee23_a;
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file multiplier_virtex2p_10_1_817edd563258bb47.vhd when simulating
-- the core, multiplier_virtex2p_10_1_817edd563258bb47. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY multiplier_virtex2p_10_1_817edd563258bb47 IS
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(17 downto 0);
b: IN std_logic_VECTOR(17 downto 0);
ce: IN std_logic;
sclr: IN std_logic;
p: OUT std_logic_VECTOR(35 downto 0));
END multiplier_virtex2p_10_1_817edd563258bb47;
ARCHITECTURE multiplier_virtex2p_10_1_817edd563258bb47_a OF multiplier_virtex2p_10_1_817edd563258bb47 IS
-- synthesis translate_off
component wrapped_multiplier_virtex2p_10_1_817edd563258bb47
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(17 downto 0);
b: IN std_logic_VECTOR(17 downto 0);
ce: IN std_logic;
sclr: IN std_logic;
p: OUT std_logic_VECTOR(35 downto 0));
end component;
-- Configuration specification
for all : wrapped_multiplier_virtex2p_10_1_817edd563258bb47 use entity XilinxCoreLib.mult_gen_v10_1(behavioral)
generic map(
c_a_width => 18,
c_b_type => 1,
c_ce_overrides_sclr => 1,
c_has_sclr => 1,
c_round_pt => 0,
c_model_type => 0,
c_out_high => 35,
c_verbosity => 0,
c_mult_type => 1,
c_ccm_imp => 0,
c_latency => 1,
c_has_ce => 1,
c_has_zero_detect => 0,
c_round_output => 0,
c_optimize_goal => 1,
c_xdevicefamily => "virtex2p",
c_a_type => 1,
c_out_low => 0,
c_b_width => 18,
c_b_value => "10000001");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_multiplier_virtex2p_10_1_817edd563258bb47
port map (
clk => clk,
a => a,
b => b,
ce => ce,
sclr => sclr,
p => p);
-- synthesis translate_on
END multiplier_virtex2p_10_1_817edd563258bb47_a;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
package clock_pkg is
-- synopsys translate_off
signal int_clk : std_logic;
-- synopsys translate_on
end clock_pkg;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity convert_func_call is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call;
architecture behavior of convert_func_call is
begin
result <= convert_type(din, din_width, din_bin_pt, din_arith,
dout_width, dout_bin_pt, dout_arith,
quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlconvert is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
bool_conversion : integer :=0;
latency : integer := 0;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector (dout_width-1 downto 0));
end xlconvert;
architecture behavior of xlconvert is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component convert_func_call
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end component;
-- synopsys translate_off
signal real_din, real_dout : real;
-- synopsys translate_on
signal result : std_logic_vector(dout_width-1 downto 0);
begin
-- synopsys translate_off
-- synopsys translate_on
bool_conversion_generate : if (bool_conversion = 1)
generate
result <= din;
end generate;
std_conversion_generate : if (bool_conversion = 0)
generate
convert : convert_func_call
generic map (
din_width => din_width,
din_bin_pt => din_bin_pt,
din_arith => din_arith,
dout_width => dout_width,
dout_bin_pt => dout_bin_pt,
dout_arith => dout_arith,
quantization => quantization,
overflow => overflow)
port map (
din => din,
result => result);
end generate;
latency_test : if (latency > 0)
generate
reg : synth_reg
generic map ( width => dout_width,
latency => latency)
port map (i => result,
ce => ce,
clr => clr,
clk => clk,
o => dout);
end generate;
latency0 : if (latency = 0)
generate
dout <= result;
end generate latency0;
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlcounter_free is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
load: in std_logic_vector(0 downto 0) := (others => '0');
din: in std_logic_vector(op_width - 1 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_free ;
architecture behavior of xlcounter_free is
component binary_counter_virtex2p_7_0_950e4ab582797264
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_950e4ab582797264:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_950e4ab582797264:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_950e4ab582797264:
component is "black_box";
component binary_counter_virtex2p_7_0_b0a257f5389d649a
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_b0a257f5389d649a:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_b0a257f5389d649a:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_b0a257f5389d649a:
component is "black_box";
component binary_counter_virtex2p_7_0_b511f9871581ee23
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
load: in std_logic;
l: in std_logic_vector(op_width - 1 downto 0);
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_b511f9871581ee23:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_b511f9871581ee23:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_b511f9871581ee23:
component is "black_box";
component binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_a22528b4c55dc1cd:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_a22528b4c55dc1cd:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_a22528b4c55dc1cd:
component is "black_box";
component binary_counter_virtex2p_7_0_77cea312f82499f0
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
load: in std_logic;
l: in std_logic_vector(op_width - 1 downto 0);
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_77cea312f82499f0:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_77cea312f82499f0:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_77cea312f82499f0:
component is "black_box";
-- synopsys translate_off
constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
signal core_sinit: std_logic;
signal core_ce: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
begin
core_ce <= ce and en(0);
core_sinit <= (clr or rst(0)) and ce;
op <= op_net;
comp0: if ((core_name0 = "binary_counter_virtex2p_7_0_950e4ab582797264")) generate
core_instance0: binary_counter_virtex2p_7_0_950e4ab582797264
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp1: if ((core_name0 = "binary_counter_virtex2p_7_0_b0a257f5389d649a")) generate
core_instance1: binary_counter_virtex2p_7_0_b0a257f5389d649a
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp2: if ((core_name0 = "binary_counter_virtex2p_7_0_b511f9871581ee23")) generate
core_instance2: binary_counter_virtex2p_7_0_b511f9871581ee23
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
load => load(0),
l => din,
q => op_net
);
end generate;
comp3: if ((core_name0 = "binary_counter_virtex2p_7_0_a22528b4c55dc1cd")) generate
core_instance3: binary_counter_virtex2p_7_0_a22528b4c55dc1cd
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp4: if ((core_name0 = "binary_counter_virtex2p_7_0_77cea312f82499f0")) generate
core_instance4: binary_counter_virtex2p_7_0_77cea312f82499f0
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
load => load(0),
l => din,
q => op_net
);
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e2b989a05e is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e2b989a05e;
architecture behavior of inverter_e2b989a05e is
signal ip_1_26: unsigned((1 - 1) downto 0);
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => "0");
signal op_mem_22_20_front_din: unsigned((1 - 1) downto 0);
signal op_mem_22_20_back: unsigned((1 - 1) downto 0);
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: unsigned((1 - 1) downto 0);
begin
ip_1_26 <= std_logic_vector_to_unsigned(ip);
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(ip_1_26));
op_mem_22_20_push_front_pop_back_en <= '0';
op <= unsigned_to_std_logic_vector(internal_ip_12_1_bitnot);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlmult_v9_0 is
generic (
core_name0: string := "";
a_width: integer := 4;
a_bin_pt: integer := 2;
a_arith: integer := xlSigned;
b_width: integer := 4;
b_bin_pt: integer := 1;
b_arith: integer := xlSigned;
p_width: integer := 8;
p_bin_pt: integer := 2;
p_arith: integer := xlSigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
extra_registers: integer := 0;
c_a_width: integer := 7;
c_b_width: integer := 7;
c_type: integer := 0;
c_a_type: integer := 0;
c_b_type: integer := 0;
c_pipelined: integer := 1;
c_baat: integer := 4;
multsign: integer := xlSigned;
c_output_width: integer := 16
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
core_ce: in std_logic := '0';
core_clr: in std_logic := '0';
core_clk: in std_logic := '0';
rst: in std_logic_vector(rst_width - 1 downto 0);
en: in std_logic_vector(en_width - 1 downto 0);
p: out std_logic_vector(p_width - 1 downto 0)
);
end xlmult_v9_0 ;
architecture behavior of xlmult_v9_0 is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
component multiplier_virtex2p_10_1_817edd563258bb47
port (
b: in std_logic_vector(c_b_width - 1 downto 0);
p: out std_logic_vector(c_output_width - 1 downto 0);
clk: in std_logic;
ce: in std_logic;
sclr: in std_logic;
a: in std_logic_vector(c_a_width - 1 downto 0)
);
end component;
attribute syn_black_box of multiplier_virtex2p_10_1_817edd563258bb47:
component is true;
attribute fpga_dont_touch of multiplier_virtex2p_10_1_817edd563258bb47:
component is "true";
attribute box_type of multiplier_virtex2p_10_1_817edd563258bb47:
component is "black_box";
signal tmp_a: std_logic_vector(c_a_width - 1 downto 0);
signal conv_a: std_logic_vector(c_a_width - 1 downto 0);
signal tmp_b: std_logic_vector(c_b_width - 1 downto 0);
signal conv_b: std_logic_vector(c_b_width - 1 downto 0);
signal tmp_p: std_logic_vector(c_output_width - 1 downto 0);
signal conv_p: std_logic_vector(p_width - 1 downto 0);
-- synopsys translate_off
signal real_a, real_b, real_p: real;
-- synopsys translate_on
signal rfd: std_logic;
signal rdy: std_logic;
signal nd: std_logic;
signal internal_ce: std_logic;
signal internal_clr: std_logic;
signal internal_core_ce: std_logic;
begin
-- synopsys translate_off
-- synopsys translate_on
internal_ce <= ce and en(0);
internal_core_ce <= core_ce and en(0);
internal_clr <= (clr or rst(0)) and ce;
nd <= internal_ce;
input_process: process (a,b)
begin
tmp_a <= zero_ext(a, c_a_width);
tmp_b <= zero_ext(b, c_b_width);
end process;
output_process: process (tmp_p)
begin
conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign,
p_width, p_bin_pt, p_arith, quantization, overflow);
end process;
comp0: if ((core_name0 = "multiplier_virtex2p_10_1_817edd563258bb47")) generate
core_instance0: multiplier_virtex2p_10_1_817edd563258bb47
port map (
a => tmp_a,
clk => clk,
ce => internal_ce,
sclr => internal_clr,
p => tmp_p,
b => tmp_b
);
end generate;
latency_gt_0: if (extra_registers > 0) generate
reg: synth_reg
generic map (
width => p_width,
latency => extra_registers
)
port map (
i => conv_p,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => p
);
end generate;
latency_eq_0: if (extra_registers = 0) generate
p <= conv_p;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlregister is
generic (d_width : integer := 5;
init_value : bit_vector := b"00");
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end xlregister;
architecture behavior of xlregister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
-- synopsys translate_off
signal real_d, real_q : real;
-- synopsys translate_on
signal internal_clr : std_logic;
signal internal_ce : std_logic;
begin
internal_clr <= rst(0) and ce;
internal_ce <= en(0) and ce;
synth_reg_inst : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => q);
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_4e76b03051 is
port (
a : in std_logic_vector((18 - 1) downto 0);
b : in std_logic_vector((18 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_4e76b03051;
architecture behavior of relational_4e76b03051 is
signal a_1_31: unsigned((18 - 1) downto 0);
signal b_1_34: unsigned((18 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_12_3_rel <= a_1_31 = b_1_34;
op_mem_32_22_front_din <= result_12_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_1433264a0c is
port (
a : in std_logic_vector((18 - 1) downto 0);
b : in std_logic_vector((18 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_1433264a0c;
architecture behavior of relational_1433264a0c is
signal a_1_31: unsigned((18 - 1) downto 0);
signal b_1_34: unsigned((18 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_22_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_22_3_rel <= a_1_31 >= b_1_34;
op_mem_32_22_front_din <= result_22_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_8231ed31e4 is
port (
plbrst : in std_logic_vector((1 - 1) downto 0);
plbabus : in std_logic_vector((32 - 1) downto 0);
plbpavalid : in std_logic_vector((1 - 1) downto 0);
plbrnw : in std_logic_vector((1 - 1) downto 0);
plbwrdbus : in std_logic_vector((32 - 1) downto 0);
rddata : in std_logic_vector((32 - 1) downto 0);
addrpref : in std_logic_vector((15 - 1) downto 0);
wrdbusreg : out std_logic_vector((32 - 1) downto 0);
addrack : out std_logic_vector((1 - 1) downto 0);
rdcomp : out std_logic_vector((1 - 1) downto 0);
wrdack : out std_logic_vector((1 - 1) downto 0);
bankaddr : out std_logic_vector((2 - 1) downto 0);
rnwreg : out std_logic_vector((1 - 1) downto 0);
rddack : out std_logic_vector((1 - 1) downto 0);
rddbus : out std_logic_vector((32 - 1) downto 0);
linearaddr : out std_logic_vector((13 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_8231ed31e4;
architecture behavior of mcode_block_8231ed31e4 is
signal plbrst_2_20: unsigned((1 - 1) downto 0);
signal plbabus_2_28: unsigned((32 - 1) downto 0);
signal plbpavalid_2_37: unsigned((1 - 1) downto 0);
signal plbrnw_2_49: unsigned((1 - 1) downto 0);
signal plbwrdbus_2_57: unsigned((32 - 1) downto 0);
signal rddata_2_68: unsigned((32 - 1) downto 0);
signal addrpref_2_76: unsigned((15 - 1) downto 0);
signal plbrstreg_13_24_next: boolean;
signal plbrstreg_13_24: boolean := false;
signal plbabusreg_14_25_next: unsigned((32 - 1) downto 0);
signal plbabusreg_14_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal plbpavalidreg_15_28_next: boolean;
signal plbpavalidreg_15_28: boolean := false;
signal plbrnwreg_16_24_next: unsigned((1 - 1) downto 0);
signal plbrnwreg_16_24: unsigned((1 - 1) downto 0) := "0";
signal plbwrdbusreg_17_27_next: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_17_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal avalidreg_29_23_next: boolean;
signal avalidreg_29_23: boolean := false;
signal ps1reg_40_20_next: boolean;
signal ps1reg_40_20: boolean := false;
signal psreg_48_19_next: boolean;
signal psreg_48_19: boolean := false;
type array_type_rdcompdelay_59_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25: array_type_rdcompdelay_59_25 := (
"0",
"0",
"0");
signal rdcompdelay_59_25_front_din: unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25_back: unsigned((1 - 1) downto 0);
signal rdcompdelay_59_25_push_front_pop_back_en: std_logic;
signal rdcompreg_63_23_next: unsigned((1 - 1) downto 0);
signal rdcompreg_63_23: unsigned((1 - 1) downto 0) := "0";
signal rddackreg_67_23_next: unsigned((1 - 1) downto 0);
signal rddackreg_67_23: unsigned((1 - 1) downto 0) := "0";
signal wrdackreg_71_23_next: unsigned((1 - 1) downto 0);
signal wrdackreg_71_23: unsigned((1 - 1) downto 0) := "0";
signal rddbusreg_85_23_next: unsigned((32 - 1) downto 0);
signal rddbusreg_85_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_21_1_slice: unsigned((2 - 1) downto 0);
signal linearaddr_22_1_slice: unsigned((13 - 1) downto 0);
signal addrpref_in_33_1_slice: unsigned((15 - 1) downto 0);
signal rel_34_4: boolean;
signal ps1_join_34_1: boolean;
signal ps_43_1_bit: boolean;
signal bitnot_50_49: boolean;
signal bitnot_50_73: boolean;
signal bit_50_49: boolean;
signal addrack_50_1_convert: unsigned((1 - 1) downto 0);
signal bit_56_43: unsigned((1 - 1) downto 0);
signal bitnot_73_35: unsigned((1 - 1) downto 0);
signal wrdackreg_73_1_bit: unsigned((1 - 1) downto 0);
signal rdsel_77_1_bit: unsigned((1 - 1) downto 0);
signal rel_79_4: boolean;
signal rddbus1_join_79_1: unsigned((32 - 1) downto 0);
signal plbwrdbusreg_98_1_slice: unsigned((32 - 1) downto 0);
signal plbrstreg_13_24_next_x_000000: boolean;
signal plbpavalidreg_15_28_next_x_000000: boolean;
begin
plbrst_2_20 <= std_logic_vector_to_unsigned(plbrst);
plbabus_2_28 <= std_logic_vector_to_unsigned(plbabus);
plbpavalid_2_37 <= std_logic_vector_to_unsigned(plbpavalid);
plbrnw_2_49 <= std_logic_vector_to_unsigned(plbrnw);
plbwrdbus_2_57 <= std_logic_vector_to_unsigned(plbwrdbus);
rddata_2_68 <= std_logic_vector_to_unsigned(rddata);
addrpref_2_76 <= std_logic_vector_to_unsigned(addrpref);
proc_plbrstreg_13_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrstreg_13_24 <= plbrstreg_13_24_next;
end if;
end if;
end process proc_plbrstreg_13_24;
proc_plbabusreg_14_25: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbabusreg_14_25 <= plbabusreg_14_25_next;
end if;
end if;
end process proc_plbabusreg_14_25;
proc_plbpavalidreg_15_28: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbpavalidreg_15_28 <= plbpavalidreg_15_28_next;
end if;
end if;
end process proc_plbpavalidreg_15_28;
proc_plbrnwreg_16_24: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbrnwreg_16_24 <= plbrnwreg_16_24_next;
end if;
end if;
end process proc_plbrnwreg_16_24;
proc_plbwrdbusreg_17_27: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
plbwrdbusreg_17_27 <= plbwrdbusreg_17_27_next;
end if;
end if;
end process proc_plbwrdbusreg_17_27;
proc_avalidreg_29_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
avalidreg_29_23 <= avalidreg_29_23_next;
end if;
end if;
end process proc_avalidreg_29_23;
proc_ps1reg_40_20: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ps1reg_40_20 <= ps1reg_40_20_next;
end if;
end if;
end process proc_ps1reg_40_20;
proc_psreg_48_19: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
psreg_48_19 <= psreg_48_19_next;
end if;
end if;
end process proc_psreg_48_19;
rdcompdelay_59_25_back <= rdcompdelay_59_25(2);
proc_rdcompdelay_59_25: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (rdcompdelay_59_25_push_front_pop_back_en = '1')) then
for i in 2 downto 1 loop
rdcompdelay_59_25(i) <= rdcompdelay_59_25(i-1);
end loop;
rdcompdelay_59_25(0) <= rdcompdelay_59_25_front_din;
end if;
end if;
end process proc_rdcompdelay_59_25;
proc_rdcompreg_63_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rdcompreg_63_23 <= rdcompreg_63_23_next;
end if;
end if;
end process proc_rdcompreg_63_23;
proc_rddackreg_67_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddackreg_67_23 <= rddackreg_67_23_next;
end if;
end if;
end process proc_rddackreg_67_23;
proc_wrdackreg_71_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
wrdackreg_71_23 <= wrdackreg_71_23_next;
end if;
end if;
end process proc_wrdackreg_71_23;
proc_rddbusreg_85_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
rddbusreg_85_23 <= rddbusreg_85_23_next;
end if;
end if;
end process proc_rddbusreg_85_23;
bankaddr_21_1_slice <= u2u_slice(plbabusreg_14_25, 16, 15);
linearaddr_22_1_slice <= u2u_slice(plbabusreg_14_25, 14, 2);
addrpref_in_33_1_slice <= u2u_slice(plbabusreg_14_25, 31, 17);
rel_34_4 <= addrpref_in_33_1_slice = addrpref_2_76;
proc_if_34_1: process (rel_34_4)
is
begin
if rel_34_4 then
ps1_join_34_1 <= true;
else
ps1_join_34_1 <= false;
end if;
end process proc_if_34_1;
ps_43_1_bit <= ((boolean_to_vector(ps1_join_34_1) and boolean_to_vector(plbpavalidreg_15_28)) = "1");
bitnot_50_49 <= ((not boolean_to_vector(plbrstreg_13_24)) = "1");
bitnot_50_73 <= ((not boolean_to_vector(psreg_48_19)) = "1");
bit_50_49 <= ((boolean_to_vector(bitnot_50_49) and boolean_to_vector(ps_43_1_bit) and boolean_to_vector(bitnot_50_73)) = "1");
addrack_50_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_50_49)), 0, 1, 0);
bit_56_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_16_24));
bitnot_73_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_16_24));
wrdackreg_73_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(bitnot_73_35));
rdsel_77_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_59_25_back) or unsigned_to_std_logic_vector(rdcompreg_63_23));
rel_79_4 <= rdsel_77_1_bit = std_logic_vector_to_unsigned("1");
proc_if_79_1: process (rddata_2_68, rel_79_4)
is
begin
if rel_79_4 then
rddbus1_join_79_1 <= rddata_2_68;
else
rddbus1_join_79_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
end if;
end process proc_if_79_1;
plbwrdbusreg_98_1_slice <= u2u_slice(plbwrdbus_2_57, 31, 0);
plbrstreg_13_24_next_x_000000 <= (plbrst_2_20 /= "0");
plbrstreg_13_24_next <= plbrstreg_13_24_next_x_000000;
plbabusreg_14_25_next <= plbabus_2_28;
plbpavalidreg_15_28_next_x_000000 <= (plbpavalid_2_37 /= "0");
plbpavalidreg_15_28_next <= plbpavalidreg_15_28_next_x_000000;
plbrnwreg_16_24_next <= plbrnw_2_49;
plbwrdbusreg_17_27_next <= plbwrdbusreg_98_1_slice;
avalidreg_29_23_next <= plbpavalidreg_15_28;
ps1reg_40_20_next <= ps1_join_34_1;
psreg_48_19_next <= ps_43_1_bit;
rdcompdelay_59_25_front_din <= bit_56_43;
rdcompdelay_59_25_push_front_pop_back_en <= '1';
rdcompreg_63_23_next <= rdcompdelay_59_25_back;
rddackreg_67_23_next <= rdcompreg_63_23;
wrdackreg_71_23_next <= wrdackreg_73_1_bit;
rddbusreg_85_23_next <= rddbus1_join_79_1;
wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_17_27);
addrack <= unsigned_to_std_logic_vector(addrack_50_1_convert);
rdcomp <= unsigned_to_std_logic_vector(rdcompreg_63_23);
wrdack <= unsigned_to_std_logic_vector(wrdackreg_71_23);
bankaddr <= unsigned_to_std_logic_vector(bankaddr_21_1_slice);
rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_16_24);
rddack <= unsigned_to_std_logic_vector(rddackreg_67_23);
rddbus <= unsigned_to_std_logic_vector(rddbusreg_85_23);
linearaddr <= unsigned_to_std_logic_vector(linearaddr_22_1_slice);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mcode_block_66f25059c9 is
port (
wrdbus : in std_logic_vector((32 - 1) downto 0);
bankaddr : in std_logic_vector((2 - 1) downto 0);
linearaddr : in std_logic_vector((13 - 1) downto 0);
rnwreg : in std_logic_vector((1 - 1) downto 0);
addrack : in std_logic_vector((1 - 1) downto 0);
sm_buttons_big : in std_logic_vector((2 - 1) downto 0);
sm_buttons_small : in std_logic_vector((6 - 1) downto 0);
sm_dip_switch : in std_logic_vector((4 - 1) downto 0);
sm_trackball : in std_logic_vector((5 - 1) downto 0);
sm_buzzer_dutycycle : in std_logic_vector((18 - 1) downto 0);
sm_buzzer_enable : in std_logic_vector((1 - 1) downto 0);
sm_buzzer_period : in std_logic_vector((18 - 1) downto 0);
sm_lcd_backgroundcolor : in std_logic_vector((9 - 1) downto 0);
sm_lcd_characteroffset : in std_logic_vector((4 - 1) downto 0);
sm_lcd_charactersselect : in std_logic_vector((3 - 1) downto 0);
sm_lcd_colset : in std_logic_vector((9 - 1) downto 0);
sm_lcd_configlocation : in std_logic_vector((2 - 1) downto 0);
sm_lcd_dividerselect : in std_logic_vector((1 - 1) downto 0);
sm_lcd_firstend : in std_logic_vector((9 - 1) downto 0);
sm_lcd_firststart : in std_logic_vector((9 - 1) downto 0);
sm_lcd_lineoffset : in std_logic_vector((4 - 1) downto 0);
sm_lcd_ramwrite : in std_logic_vector((9 - 1) downto 0);
sm_lcd_reset : in std_logic_vector((1 - 1) downto 0);
sm_lcd_resetlcd : in std_logic_vector((1 - 1) downto 0);
sm_lcd_rowset : in std_logic_vector((9 - 1) downto 0);
sm_lcd_secondend : in std_logic_vector((9 - 1) downto 0);
sm_lcd_secondstart : in std_logic_vector((9 - 1) downto 0);
sm_lcd_send : in std_logic_vector((1 - 1) downto 0);
sm_lcd_totalcmdtransfer : in std_logic_vector((8 - 1) downto 0);
sm_leds : in std_logic_vector((8 - 1) downto 0);
sm_lcd_charactermap : in std_logic_vector((32 - 1) downto 0);
sm_lcd_characters : in std_logic_vector((32 - 1) downto 0);
sm_lcd_commands : in std_logic_vector((32 - 1) downto 0);
read_bank_out : out std_logic_vector((32 - 1) downto 0);
sm_buzzer_dutycycle_din : out std_logic_vector((18 - 1) downto 0);
sm_buzzer_dutycycle_en : out std_logic_vector((1 - 1) downto 0);
sm_buzzer_enable_din : out std_logic_vector((1 - 1) downto 0);
sm_buzzer_enable_en : out std_logic_vector((1 - 1) downto 0);
sm_buzzer_period_din : out std_logic_vector((18 - 1) downto 0);
sm_buzzer_period_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_backgroundcolor_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_backgroundcolor_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_characteroffset_din : out std_logic_vector((4 - 1) downto 0);
sm_lcd_characteroffset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_charactersselect_din : out std_logic_vector((3 - 1) downto 0);
sm_lcd_charactersselect_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_colset_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_colset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_configlocation_din : out std_logic_vector((2 - 1) downto 0);
sm_lcd_configlocation_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_dividerselect_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_dividerselect_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_firstend_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_firstend_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_firststart_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_firststart_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_lineoffset_din : out std_logic_vector((4 - 1) downto 0);
sm_lcd_lineoffset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_ramwrite_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_ramwrite_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_reset_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_reset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_resetlcd_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_resetlcd_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_rowset_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_rowset_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_secondend_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_secondend_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_secondstart_din : out std_logic_vector((9 - 1) downto 0);
sm_lcd_secondstart_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_send_din : out std_logic_vector((1 - 1) downto 0);
sm_lcd_send_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_totalcmdtransfer_din : out std_logic_vector((8 - 1) downto 0);
sm_lcd_totalcmdtransfer_en : out std_logic_vector((1 - 1) downto 0);
sm_leds_din : out std_logic_vector((8 - 1) downto 0);
sm_leds_en : out std_logic_vector((1 - 1) downto 0);
sm_lcd_charactermap_addr : out std_logic_vector((12 - 1) downto 0);
sm_lcd_charactermap_din : out std_logic_vector((32 - 1) downto 0);
sm_lcd_charactermap_we : out std_logic_vector((1 - 1) downto 0);
sm_lcd_characters_addr : out std_logic_vector((9 - 1) downto 0);
sm_lcd_characters_din : out std_logic_vector((32 - 1) downto 0);
sm_lcd_characters_we : out std_logic_vector((1 - 1) downto 0);
sm_lcd_commands_addr : out std_logic_vector((8 - 1) downto 0);
sm_lcd_commands_din : out std_logic_vector((32 - 1) downto 0);
sm_lcd_commands_we : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mcode_block_66f25059c9;
architecture behavior of mcode_block_66f25059c9 is
signal wrdbus_1_1186: unsigned((32 - 1) downto 0);
signal bankaddr_1_1194: unsigned((2 - 1) downto 0);
signal linearaddr_1_1204: unsigned((13 - 1) downto 0);
signal rnwreg_1_1216: unsigned((1 - 1) downto 0);
signal addrack_1_1224: unsigned((1 - 1) downto 0);
signal sm_buttons_big_1_1233: unsigned((2 - 1) downto 0);
signal sm_buttons_small_1_1249: unsigned((6 - 1) downto 0);
signal sm_dip_switch_1_1267: unsigned((4 - 1) downto 0);
signal sm_trackball_1_1282: unsigned((5 - 1) downto 0);
signal sm_buzzer_dutycycle_1_1296: unsigned((18 - 1) downto 0);
signal sm_buzzer_enable_1_1317: unsigned((1 - 1) downto 0);
signal sm_buzzer_period_1_1335: unsigned((18 - 1) downto 0);
signal sm_lcd_backgroundcolor_1_1353: unsigned((9 - 1) downto 0);
signal sm_lcd_characteroffset_1_1377: unsigned((4 - 1) downto 0);
signal sm_lcd_charactersselect_1_1401: unsigned((3 - 1) downto 0);
signal sm_lcd_colset_1_1426: unsigned((9 - 1) downto 0);
signal sm_lcd_configlocation_1_1441: unsigned((2 - 1) downto 0);
signal sm_lcd_dividerselect_1_1464: unsigned((1 - 1) downto 0);
signal sm_lcd_firstend_1_1486: unsigned((9 - 1) downto 0);
signal sm_lcd_firststart_1_1503: unsigned((9 - 1) downto 0);
signal sm_lcd_lineoffset_1_1522: unsigned((4 - 1) downto 0);
signal sm_lcd_ramwrite_1_1541: unsigned((9 - 1) downto 0);
signal sm_lcd_reset_1_1558: unsigned((1 - 1) downto 0);
signal sm_lcd_resetlcd_1_1572: unsigned((1 - 1) downto 0);
signal sm_lcd_rowset_1_1589: unsigned((9 - 1) downto 0);
signal sm_lcd_secondend_1_1604: unsigned((9 - 1) downto 0);
signal sm_lcd_secondstart_1_1622: unsigned((9 - 1) downto 0);
signal sm_lcd_send_1_1642: unsigned((1 - 1) downto 0);
signal sm_lcd_totalcmdtransfer_1_1655: unsigned((8 - 1) downto 0);
signal sm_leds_1_1680: unsigned((8 - 1) downto 0);
signal sm_lcd_charactermap_1_1689: unsigned((32 - 1) downto 0);
signal sm_lcd_characters_1_1710: unsigned((32 - 1) downto 0);
signal sm_lcd_commands_1_1729: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_98_30_next: unsigned((32 - 1) downto 0);
signal reg_bank_out_reg_98_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal ram_bank_out_reg_203_30_next: unsigned((32 - 1) downto 0);
signal ram_bank_out_reg_203_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal sm_lcd_charactermap_we_reg_226_40_next: boolean;
signal sm_lcd_charactermap_we_reg_226_40: boolean := false;
signal sm_lcd_characters_we_reg_245_38_next: boolean;
signal sm_lcd_characters_we_reg_245_38: boolean := false;
signal sm_lcd_commands_we_reg_264_36_next: boolean;
signal sm_lcd_commands_we_reg_264_36: boolean := false;
signal sm_lcd_charactermap_addr_reg_287_1_next: unsigned((12 - 1) downto 0);
signal sm_lcd_charactermap_addr_reg_287_1: unsigned((12 - 1) downto 0) := "000000000000";
signal sm_lcd_charactermap_addr_reg_287_1_en: std_logic;
signal sm_lcd_characters_addr_reg_295_1_next: unsigned((9 - 1) downto 0);
signal sm_lcd_characters_addr_reg_295_1: unsigned((9 - 1) downto 0) := "000000000";
signal sm_lcd_characters_addr_reg_295_1_en: std_logic;
signal sm_lcd_commands_addr_reg_303_1_next: unsigned((8 - 1) downto 0);
signal sm_lcd_commands_addr_reg_303_1: unsigned((8 - 1) downto 0) := "00000000";
signal sm_lcd_commands_addr_reg_303_1_en: std_logic;
signal read_bank_out_reg_516_31_next: unsigned((32 - 1) downto 0);
signal read_bank_out_reg_516_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000";
signal bankaddr_reg_519_26_next: unsigned((2 - 1) downto 0);
signal bankaddr_reg_519_26: unsigned((2 - 1) downto 0) := "00";
signal rel_101_4: boolean;
signal rel_103_8: boolean;
signal rel_105_8: boolean;
signal rel_107_8: boolean;
signal rel_109_8: boolean;
signal rel_111_8: boolean;
signal rel_113_8: boolean;
signal rel_115_8: boolean;
signal rel_117_8: boolean;
signal rel_119_8: boolean;
signal rel_121_8: boolean;
signal rel_123_8: boolean;
signal rel_125_8: boolean;
signal rel_127_8: boolean;
signal rel_129_8: boolean;
signal rel_131_8: boolean;
signal rel_133_8: boolean;
signal rel_135_8: boolean;
signal rel_137_8: boolean;
signal rel_139_8: boolean;
signal rel_141_8: boolean;
signal rel_143_8: boolean;
signal rel_145_8: boolean;
signal rel_147_8: boolean;
signal rel_149_8: boolean;
signal reg_bank_out_reg_join_101_1: unsigned((32 - 1) downto 0);
signal opcode_160_1_concat: unsigned((17 - 1) downto 0);
signal slice_164_51: unsigned((1 - 1) downto 0);
signal sm_lcd_charactermap_sel_value_164_1_concat: unsigned((1 - 1) downto 0);
signal rel_168_4: boolean;
signal sm_lcd_charactermap_sel_join_168_1: boolean;
signal slice_176_49: unsigned((4 - 1) downto 0);
signal sm_lcd_characters_sel_value_176_1_concat: unsigned((4 - 1) downto 0);
signal rel_180_4: boolean;
signal sm_lcd_characters_sel_join_180_1: boolean;
signal slice_188_47: unsigned((5 - 1) downto 0);
signal sm_lcd_commands_sel_value_188_1_concat: unsigned((5 - 1) downto 0);
signal rel_192_4: boolean;
signal sm_lcd_commands_sel_join_192_1: boolean;
signal ram_bank_out_reg_join_205_1: unsigned((32 - 1) downto 0);
signal slice_214_44: unsigned((32 - 1) downto 0);
signal slice_217_42: unsigned((32 - 1) downto 0);
signal slice_220_40: unsigned((32 - 1) downto 0);
signal slice_231_46: unsigned((1 - 1) downto 0);
signal opcode_sm_lcd_charactermap_228_1_concat: unsigned((5 - 1) downto 0);
signal rel_235_4: boolean;
signal sm_lcd_charactermap_we_reg_join_235_1: boolean;
signal slice_250_46: unsigned((4 - 1) downto 0);
signal opcode_sm_lcd_characters_247_1_concat: unsigned((8 - 1) downto 0);
signal rel_254_4: boolean;
signal sm_lcd_characters_we_reg_join_254_1: boolean;
signal slice_269_46: unsigned((5 - 1) downto 0);
signal opcode_sm_lcd_commands_266_1_concat: unsigned((9 - 1) downto 0);
signal rel_273_4: boolean;
signal sm_lcd_commands_we_reg_join_273_1: boolean;
signal sm_lcd_charactermap_addr_reg_290_5_slice: unsigned((13 - 1) downto 0);
signal rel_289_4: boolean;
signal sm_lcd_charactermap_addr_reg_join_289_1: unsigned((13 - 1) downto 0);
signal sm_lcd_charactermap_addr_reg_join_289_1_en: std_logic;
signal sm_lcd_characters_addr_reg_298_5_slice: unsigned((10 - 1) downto 0);
signal rel_297_4: boolean;
signal sm_lcd_characters_addr_reg_join_297_1: unsigned((10 - 1) downto 0);
signal sm_lcd_characters_addr_reg_join_297_1_en: std_logic;
signal sm_lcd_commands_addr_reg_306_5_slice: unsigned((9 - 1) downto 0);
signal rel_305_4: boolean;
signal sm_lcd_commands_addr_reg_join_305_1: unsigned((9 - 1) downto 0);
signal sm_lcd_commands_addr_reg_join_305_1_en: std_logic;
signal rel_316_4: boolean;
signal sm_buzzer_dutycycle_en_join_316_1: boolean;
signal rel_322_4: boolean;
signal sm_buzzer_enable_en_join_322_1: boolean;
signal rel_328_4: boolean;
signal sm_buzzer_period_en_join_328_1: boolean;
signal rel_334_4: boolean;
signal sm_lcd_backgroundcolor_en_join_334_1: boolean;
signal rel_340_4: boolean;
signal sm_lcd_characteroffset_en_join_340_1: boolean;
signal rel_346_4: boolean;
signal sm_lcd_charactersselect_en_join_346_1: boolean;
signal rel_352_4: boolean;
signal sm_lcd_colset_en_join_352_1: boolean;
signal rel_358_4: boolean;
signal sm_lcd_configlocation_en_join_358_1: boolean;
signal rel_364_4: boolean;
signal sm_lcd_dividerselect_en_join_364_1: boolean;
signal rel_370_4: boolean;
signal sm_lcd_firstend_en_join_370_1: boolean;
signal rel_376_4: boolean;
signal sm_lcd_firststart_en_join_376_1: boolean;
signal rel_382_4: boolean;
signal sm_lcd_lineoffset_en_join_382_1: boolean;
signal rel_388_4: boolean;
signal sm_lcd_ramwrite_en_join_388_1: boolean;
signal rel_394_4: boolean;
signal sm_lcd_reset_en_join_394_1: boolean;
signal rel_400_4: boolean;
signal sm_lcd_resetlcd_en_join_400_1: boolean;
signal rel_406_4: boolean;
signal sm_lcd_rowset_en_join_406_1: boolean;
signal rel_412_4: boolean;
signal sm_lcd_secondend_en_join_412_1: boolean;
signal rel_418_4: boolean;
signal sm_lcd_secondstart_en_join_418_1: boolean;
signal rel_424_4: boolean;
signal sm_lcd_send_en_join_424_1: boolean;
signal rel_430_4: boolean;
signal sm_lcd_totalcmdtransfer_en_join_430_1: boolean;
signal rel_436_4: boolean;
signal sm_leds_en_join_436_1: boolean;
signal slice_451_44: unsigned((18 - 1) downto 0);
signal slice_454_41: unsigned((1 - 1) downto 0);
signal slice_457_41: unsigned((18 - 1) downto 0);
signal slice_460_47: unsigned((9 - 1) downto 0);
signal slice_463_47: unsigned((4 - 1) downto 0);
signal slice_466_48: unsigned((3 - 1) downto 0);
signal slice_469_38: unsigned((9 - 1) downto 0);
signal slice_472_46: unsigned((2 - 1) downto 0);
signal slice_475_45: unsigned((1 - 1) downto 0);
signal slice_478_40: unsigned((9 - 1) downto 0);
signal slice_481_42: unsigned((9 - 1) downto 0);
signal slice_484_42: unsigned((4 - 1) downto 0);
signal slice_487_40: unsigned((9 - 1) downto 0);
signal slice_490_37: unsigned((1 - 1) downto 0);
signal slice_493_40: unsigned((1 - 1) downto 0);
signal slice_496_38: unsigned((9 - 1) downto 0);
signal slice_499_41: unsigned((9 - 1) downto 0);
signal slice_502_43: unsigned((9 - 1) downto 0);
signal slice_505_36: unsigned((1 - 1) downto 0);
signal slice_508_48: unsigned((8 - 1) downto 0);
signal slice_511_32: unsigned((8 - 1) downto 0);
signal rel_521_4: boolean;
signal rel_524_8: boolean;
signal rel_527_8: boolean;
signal rel_530_8: boolean;
signal read_bank_out_reg_join_521_1: unsigned((32 - 1) downto 0);
signal cast_sm_lcd_charactermap_addr_reg_287_1_next: unsigned((12 - 1) downto 0);
signal cast_sm_lcd_characters_addr_reg_295_1_next: unsigned((9 - 1) downto 0);
signal cast_sm_lcd_commands_addr_reg_303_1_next: unsigned((8 - 1) downto 0);
begin
wrdbus_1_1186 <= std_logic_vector_to_unsigned(wrdbus);
bankaddr_1_1194 <= std_logic_vector_to_unsigned(bankaddr);
linearaddr_1_1204 <= std_logic_vector_to_unsigned(linearaddr);
rnwreg_1_1216 <= std_logic_vector_to_unsigned(rnwreg);
addrack_1_1224 <= std_logic_vector_to_unsigned(addrack);
sm_buttons_big_1_1233 <= std_logic_vector_to_unsigned(sm_buttons_big);
sm_buttons_small_1_1249 <= std_logic_vector_to_unsigned(sm_buttons_small);
sm_dip_switch_1_1267 <= std_logic_vector_to_unsigned(sm_dip_switch);
sm_trackball_1_1282 <= std_logic_vector_to_unsigned(sm_trackball);
sm_buzzer_dutycycle_1_1296 <= std_logic_vector_to_unsigned(sm_buzzer_dutycycle);
sm_buzzer_enable_1_1317 <= std_logic_vector_to_unsigned(sm_buzzer_enable);
sm_buzzer_period_1_1335 <= std_logic_vector_to_unsigned(sm_buzzer_period);
sm_lcd_backgroundcolor_1_1353 <= std_logic_vector_to_unsigned(sm_lcd_backgroundcolor);
sm_lcd_characteroffset_1_1377 <= std_logic_vector_to_unsigned(sm_lcd_characteroffset);
sm_lcd_charactersselect_1_1401 <= std_logic_vector_to_unsigned(sm_lcd_charactersselect);
sm_lcd_colset_1_1426 <= std_logic_vector_to_unsigned(sm_lcd_colset);
sm_lcd_configlocation_1_1441 <= std_logic_vector_to_unsigned(sm_lcd_configlocation);
sm_lcd_dividerselect_1_1464 <= std_logic_vector_to_unsigned(sm_lcd_dividerselect);
sm_lcd_firstend_1_1486 <= std_logic_vector_to_unsigned(sm_lcd_firstend);
sm_lcd_firststart_1_1503 <= std_logic_vector_to_unsigned(sm_lcd_firststart);
sm_lcd_lineoffset_1_1522 <= std_logic_vector_to_unsigned(sm_lcd_lineoffset);
sm_lcd_ramwrite_1_1541 <= std_logic_vector_to_unsigned(sm_lcd_ramwrite);
sm_lcd_reset_1_1558 <= std_logic_vector_to_unsigned(sm_lcd_reset);
sm_lcd_resetlcd_1_1572 <= std_logic_vector_to_unsigned(sm_lcd_resetlcd);
sm_lcd_rowset_1_1589 <= std_logic_vector_to_unsigned(sm_lcd_rowset);
sm_lcd_secondend_1_1604 <= std_logic_vector_to_unsigned(sm_lcd_secondend);
sm_lcd_secondstart_1_1622 <= std_logic_vector_to_unsigned(sm_lcd_secondstart);
sm_lcd_send_1_1642 <= std_logic_vector_to_unsigned(sm_lcd_send);
sm_lcd_totalcmdtransfer_1_1655 <= std_logic_vector_to_unsigned(sm_lcd_totalcmdtransfer);
sm_leds_1_1680 <= std_logic_vector_to_unsigned(sm_leds);
sm_lcd_charactermap_1_1689 <= std_logic_vector_to_unsigned(sm_lcd_charactermap);
sm_lcd_characters_1_1710 <= std_logic_vector_to_unsigned(sm_lcd_characters);
sm_lcd_commands_1_1729 <= std_logic_vector_to_unsigned(sm_lcd_commands);
proc_reg_bank_out_reg_98_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
reg_bank_out_reg_98_30 <= reg_bank_out_reg_98_30_next;
end if;
end if;
end process proc_reg_bank_out_reg_98_30;
proc_ram_bank_out_reg_203_30: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
ram_bank_out_reg_203_30 <= ram_bank_out_reg_203_30_next;
end if;
end if;
end process proc_ram_bank_out_reg_203_30;
proc_sm_lcd_charactermap_we_reg_226_40: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_lcd_charactermap_we_reg_226_40 <= sm_lcd_charactermap_we_reg_226_40_next;
end if;
end if;
end process proc_sm_lcd_charactermap_we_reg_226_40;
proc_sm_lcd_characters_we_reg_245_38: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_lcd_characters_we_reg_245_38 <= sm_lcd_characters_we_reg_245_38_next;
end if;
end if;
end process proc_sm_lcd_characters_we_reg_245_38;
proc_sm_lcd_commands_we_reg_264_36: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
sm_lcd_commands_we_reg_264_36 <= sm_lcd_commands_we_reg_264_36_next;
end if;
end if;
end process proc_sm_lcd_commands_we_reg_264_36;
proc_sm_lcd_charactermap_addr_reg_287_1: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (sm_lcd_charactermap_addr_reg_287_1_en = '1')) then
sm_lcd_charactermap_addr_reg_287_1 <= sm_lcd_charactermap_addr_reg_287_1_next;
end if;
end if;
end process proc_sm_lcd_charactermap_addr_reg_287_1;
proc_sm_lcd_characters_addr_reg_295_1: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (sm_lcd_characters_addr_reg_295_1_en = '1')) then
sm_lcd_characters_addr_reg_295_1 <= sm_lcd_characters_addr_reg_295_1_next;
end if;
end if;
end process proc_sm_lcd_characters_addr_reg_295_1;
proc_sm_lcd_commands_addr_reg_303_1: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (sm_lcd_commands_addr_reg_303_1_en = '1')) then
sm_lcd_commands_addr_reg_303_1 <= sm_lcd_commands_addr_reg_303_1_next;
end if;
end if;
end process proc_sm_lcd_commands_addr_reg_303_1;
proc_read_bank_out_reg_516_31: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
read_bank_out_reg_516_31 <= read_bank_out_reg_516_31_next;
end if;
end if;
end process proc_read_bank_out_reg_516_31;
proc_bankaddr_reg_519_26: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
bankaddr_reg_519_26 <= bankaddr_reg_519_26_next;
end if;
end if;
end process proc_bankaddr_reg_519_26;
rel_101_4 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010101");
rel_103_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010110");
rel_105_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010111");
rel_107_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000011000");
rel_109_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000000");
rel_111_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000001");
rel_113_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000010");
rel_115_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000011");
rel_117_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000100");
rel_119_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000101");
rel_121_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000110");
rel_123_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000000111");
rel_125_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001000");
rel_127_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001001");
rel_129_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001010");
rel_131_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001011");
rel_133_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001100");
rel_135_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001101");
rel_137_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001110");
rel_139_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000001111");
rel_141_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010000");
rel_143_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010001");
rel_145_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010010");
rel_147_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010011");
rel_149_8 <= linearaddr_1_1204 = std_logic_vector_to_unsigned("0000000010100");
proc_if_101_1: process (reg_bank_out_reg_98_30, rel_101_4, rel_103_8, rel_105_8, rel_107_8, rel_109_8, rel_111_8, rel_113_8, rel_115_8, rel_117_8, rel_119_8, rel_121_8, rel_123_8, rel_125_8, rel_127_8, rel_129_8, rel_131_8, rel_133_8, rel_135_8, rel_137_8, rel_139_8, rel_141_8, rel_143_8, rel_145_8, rel_147_8, rel_149_8, sm_buttons_big_1_1233, sm_buttons_small_1_1249, sm_buzzer_dutycycle_1_1296, sm_buzzer_enable_1_1317, sm_buzzer_period_1_1335, sm_dip_switch_1_1267, sm_lcd_backgroundcolor_1_1353, sm_lcd_characteroffset_1_1377, sm_lcd_charactersselect_1_1401, sm_lcd_colset_1_1426, sm_lcd_configlocation_1_1441, sm_lcd_dividerselect_1_1464, sm_lcd_firstend_1_1486, sm_lcd_firststart_1_1503, sm_lcd_lineoffset_1_1522, sm_lcd_ramwrite_1_1541, sm_lcd_reset_1_1558, sm_lcd_resetlcd_1_1572, sm_lcd_rowset_1_1589, sm_lcd_secondend_1_1604, sm_lcd_secondstart_1_1622, sm_lcd_send_1_1642, sm_lcd_totalcmdtransfer_1_1655, sm_leds_1_1680, sm_trackball_1_1282)
is
begin
if rel_101_4 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buttons_big_1_1233, 0, 32, 0);
elsif rel_103_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buttons_small_1_1249, 0, 32, 0);
elsif rel_105_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_dip_switch_1_1267, 0, 32, 0);
elsif rel_107_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_trackball_1_1282, 0, 32, 0);
elsif rel_109_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buzzer_dutycycle_1_1296, 0, 32, 0);
elsif rel_111_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buzzer_enable_1_1317, 0, 32, 0);
elsif rel_113_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_buzzer_period_1_1335, 0, 32, 0);
elsif rel_115_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_backgroundcolor_1_1353, 0, 32, 0);
elsif rel_117_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_characteroffset_1_1377, 0, 32, 0);
elsif rel_119_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_charactersselect_1_1401, 0, 32, 0);
elsif rel_121_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_colset_1_1426, 0, 32, 0);
elsif rel_123_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_configlocation_1_1441, 0, 32, 0);
elsif rel_125_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_dividerselect_1_1464, 0, 32, 0);
elsif rel_127_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_firstend_1_1486, 0, 32, 0);
elsif rel_129_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_firststart_1_1503, 0, 32, 0);
elsif rel_131_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_lineoffset_1_1522, 0, 32, 0);
elsif rel_133_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_ramwrite_1_1541, 0, 32, 0);
elsif rel_135_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_reset_1_1558, 0, 32, 0);
elsif rel_137_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_resetlcd_1_1572, 0, 32, 0);
elsif rel_139_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_rowset_1_1589, 0, 32, 0);
elsif rel_141_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_secondend_1_1604, 0, 32, 0);
elsif rel_143_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_secondstart_1_1622, 0, 32, 0);
elsif rel_145_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_send_1_1642, 0, 32, 0);
elsif rel_147_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_lcd_totalcmdtransfer_1_1655, 0, 32, 0);
elsif rel_149_8 then
reg_bank_out_reg_join_101_1 <= u2u_cast(sm_leds_1_1680, 0, 32, 0);
else
reg_bank_out_reg_join_101_1 <= reg_bank_out_reg_98_30;
end if;
end process proc_if_101_1;
opcode_160_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(linearaddr_1_1204));
slice_164_51 <= u2u_slice(linearaddr_1_1204, 12, 12);
sm_lcd_charactermap_sel_value_164_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_164_51));
rel_168_4 <= sm_lcd_charactermap_sel_value_164_1_concat = std_logic_vector_to_unsigned("0");
proc_if_168_1: process (rel_168_4)
is
begin
if rel_168_4 then
sm_lcd_charactermap_sel_join_168_1 <= true;
else
sm_lcd_charactermap_sel_join_168_1 <= false;
end if;
end process proc_if_168_1;
slice_176_49 <= u2u_slice(linearaddr_1_1204, 12, 9);
sm_lcd_characters_sel_value_176_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_176_49));
rel_180_4 <= sm_lcd_characters_sel_value_176_1_concat = std_logic_vector_to_unsigned("1000");
proc_if_180_1: process (rel_180_4)
is
begin
if rel_180_4 then
sm_lcd_characters_sel_join_180_1 <= true;
else
sm_lcd_characters_sel_join_180_1 <= false;
end if;
end process proc_if_180_1;
slice_188_47 <= u2u_slice(linearaddr_1_1204, 12, 8);
sm_lcd_commands_sel_value_188_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_188_47));
rel_192_4 <= sm_lcd_commands_sel_value_188_1_concat = std_logic_vector_to_unsigned("10010");
proc_if_192_1: process (rel_192_4)
is
begin
if rel_192_4 then
sm_lcd_commands_sel_join_192_1 <= true;
else
sm_lcd_commands_sel_join_192_1 <= false;
end if;
end process proc_if_192_1;
proc_if_205_1: process (ram_bank_out_reg_203_30, sm_lcd_charactermap_1_1689, sm_lcd_charactermap_sel_join_168_1, sm_lcd_characters_1_1710, sm_lcd_characters_sel_join_180_1, sm_lcd_commands_1_1729, sm_lcd_commands_sel_join_192_1)
is
begin
if sm_lcd_charactermap_sel_join_168_1 then
ram_bank_out_reg_join_205_1 <= sm_lcd_charactermap_1_1689;
elsif sm_lcd_characters_sel_join_180_1 then
ram_bank_out_reg_join_205_1 <= sm_lcd_characters_1_1710;
elsif sm_lcd_commands_sel_join_192_1 then
ram_bank_out_reg_join_205_1 <= sm_lcd_commands_1_1729;
else
ram_bank_out_reg_join_205_1 <= ram_bank_out_reg_203_30;
end if;
end process proc_if_205_1;
slice_214_44 <= u2u_slice(wrdbus_1_1186, 31, 0);
slice_217_42 <= u2u_slice(wrdbus_1_1186, 31, 0);
slice_220_40 <= u2u_slice(wrdbus_1_1186, 31, 0);
slice_231_46 <= u2u_slice(linearaddr_1_1204, 12, 12);
opcode_sm_lcd_charactermap_228_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(slice_231_46));
rel_235_4 <= opcode_sm_lcd_charactermap_228_1_concat = std_logic_vector_to_unsigned("10000");
proc_if_235_1: process (rel_235_4)
is
begin
if rel_235_4 then
sm_lcd_charactermap_we_reg_join_235_1 <= true;
else
sm_lcd_charactermap_we_reg_join_235_1 <= false;
end if;
end process proc_if_235_1;
slice_250_46 <= u2u_slice(linearaddr_1_1204, 12, 9);
opcode_sm_lcd_characters_247_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(slice_250_46));
rel_254_4 <= opcode_sm_lcd_characters_247_1_concat = std_logic_vector_to_unsigned("10001000");
proc_if_254_1: process (rel_254_4)
is
begin
if rel_254_4 then
sm_lcd_characters_we_reg_join_254_1 <= true;
else
sm_lcd_characters_we_reg_join_254_1 <= false;
end if;
end process proc_if_254_1;
slice_269_46 <= u2u_slice(linearaddr_1_1204, 12, 8);
opcode_sm_lcd_commands_266_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_1224) & unsigned_to_std_logic_vector(rnwreg_1_1216) & unsigned_to_std_logic_vector(bankaddr_1_1194) & unsigned_to_std_logic_vector(slice_269_46));
rel_273_4 <= opcode_sm_lcd_commands_266_1_concat = std_logic_vector_to_unsigned("100010010");
proc_if_273_1: process (rel_273_4)
is
begin
if rel_273_4 then
sm_lcd_commands_we_reg_join_273_1 <= true;
else
sm_lcd_commands_we_reg_join_273_1 <= false;
end if;
end process proc_if_273_1;
sm_lcd_charactermap_addr_reg_290_5_slice <= u2u_slice(linearaddr_1_1204, 12, 0);
rel_289_4 <= addrack_1_1224 = std_logic_vector_to_unsigned("1");
proc_if_289_1: process (rel_289_4, sm_lcd_charactermap_addr_reg_290_5_slice)
is
begin
if rel_289_4 then
sm_lcd_charactermap_addr_reg_join_289_1_en <= '1';
else
sm_lcd_charactermap_addr_reg_join_289_1_en <= '0';
end if;
sm_lcd_charactermap_addr_reg_join_289_1 <= sm_lcd_charactermap_addr_reg_290_5_slice;
end process proc_if_289_1;
sm_lcd_characters_addr_reg_298_5_slice <= u2u_slice(linearaddr_1_1204, 9, 0);
rel_297_4 <= addrack_1_1224 = std_logic_vector_to_unsigned("1");
proc_if_297_1: process (rel_297_4, sm_lcd_characters_addr_reg_298_5_slice)
is
begin
if rel_297_4 then
sm_lcd_characters_addr_reg_join_297_1_en <= '1';
else
sm_lcd_characters_addr_reg_join_297_1_en <= '0';
end if;
sm_lcd_characters_addr_reg_join_297_1 <= sm_lcd_characters_addr_reg_298_5_slice;
end process proc_if_297_1;
sm_lcd_commands_addr_reg_306_5_slice <= u2u_slice(linearaddr_1_1204, 8, 0);
rel_305_4 <= addrack_1_1224 = std_logic_vector_to_unsigned("1");
proc_if_305_1: process (rel_305_4, sm_lcd_commands_addr_reg_306_5_slice)
is
begin
if rel_305_4 then
sm_lcd_commands_addr_reg_join_305_1_en <= '1';
else
sm_lcd_commands_addr_reg_join_305_1_en <= '0';
end if;
sm_lcd_commands_addr_reg_join_305_1 <= sm_lcd_commands_addr_reg_306_5_slice;
end process proc_if_305_1;
rel_316_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000000");
proc_if_316_1: process (rel_316_4)
is
begin
if rel_316_4 then
sm_buzzer_dutycycle_en_join_316_1 <= true;
else
sm_buzzer_dutycycle_en_join_316_1 <= false;
end if;
end process proc_if_316_1;
rel_322_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000001");
proc_if_322_1: process (rel_322_4)
is
begin
if rel_322_4 then
sm_buzzer_enable_en_join_322_1 <= true;
else
sm_buzzer_enable_en_join_322_1 <= false;
end if;
end process proc_if_322_1;
rel_328_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000010");
proc_if_328_1: process (rel_328_4)
is
begin
if rel_328_4 then
sm_buzzer_period_en_join_328_1 <= true;
else
sm_buzzer_period_en_join_328_1 <= false;
end if;
end process proc_if_328_1;
rel_334_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000011");
proc_if_334_1: process (rel_334_4)
is
begin
if rel_334_4 then
sm_lcd_backgroundcolor_en_join_334_1 <= true;
else
sm_lcd_backgroundcolor_en_join_334_1 <= false;
end if;
end process proc_if_334_1;
rel_340_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000100");
proc_if_340_1: process (rel_340_4)
is
begin
if rel_340_4 then
sm_lcd_characteroffset_en_join_340_1 <= true;
else
sm_lcd_characteroffset_en_join_340_1 <= false;
end if;
end process proc_if_340_1;
rel_346_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000101");
proc_if_346_1: process (rel_346_4)
is
begin
if rel_346_4 then
sm_lcd_charactersselect_en_join_346_1 <= true;
else
sm_lcd_charactersselect_en_join_346_1 <= false;
end if;
end process proc_if_346_1;
rel_352_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000110");
proc_if_352_1: process (rel_352_4)
is
begin
if rel_352_4 then
sm_lcd_colset_en_join_352_1 <= true;
else
sm_lcd_colset_en_join_352_1 <= false;
end if;
end process proc_if_352_1;
rel_358_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000000111");
proc_if_358_1: process (rel_358_4)
is
begin
if rel_358_4 then
sm_lcd_configlocation_en_join_358_1 <= true;
else
sm_lcd_configlocation_en_join_358_1 <= false;
end if;
end process proc_if_358_1;
rel_364_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001000");
proc_if_364_1: process (rel_364_4)
is
begin
if rel_364_4 then
sm_lcd_dividerselect_en_join_364_1 <= true;
else
sm_lcd_dividerselect_en_join_364_1 <= false;
end if;
end process proc_if_364_1;
rel_370_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001001");
proc_if_370_1: process (rel_370_4)
is
begin
if rel_370_4 then
sm_lcd_firstend_en_join_370_1 <= true;
else
sm_lcd_firstend_en_join_370_1 <= false;
end if;
end process proc_if_370_1;
rel_376_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001010");
proc_if_376_1: process (rel_376_4)
is
begin
if rel_376_4 then
sm_lcd_firststart_en_join_376_1 <= true;
else
sm_lcd_firststart_en_join_376_1 <= false;
end if;
end process proc_if_376_1;
rel_382_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001011");
proc_if_382_1: process (rel_382_4)
is
begin
if rel_382_4 then
sm_lcd_lineoffset_en_join_382_1 <= true;
else
sm_lcd_lineoffset_en_join_382_1 <= false;
end if;
end process proc_if_382_1;
rel_388_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001100");
proc_if_388_1: process (rel_388_4)
is
begin
if rel_388_4 then
sm_lcd_ramwrite_en_join_388_1 <= true;
else
sm_lcd_ramwrite_en_join_388_1 <= false;
end if;
end process proc_if_388_1;
rel_394_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001101");
proc_if_394_1: process (rel_394_4)
is
begin
if rel_394_4 then
sm_lcd_reset_en_join_394_1 <= true;
else
sm_lcd_reset_en_join_394_1 <= false;
end if;
end process proc_if_394_1;
rel_400_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001110");
proc_if_400_1: process (rel_400_4)
is
begin
if rel_400_4 then
sm_lcd_resetlcd_en_join_400_1 <= true;
else
sm_lcd_resetlcd_en_join_400_1 <= false;
end if;
end process proc_if_400_1;
rel_406_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000001111");
proc_if_406_1: process (rel_406_4)
is
begin
if rel_406_4 then
sm_lcd_rowset_en_join_406_1 <= true;
else
sm_lcd_rowset_en_join_406_1 <= false;
end if;
end process proc_if_406_1;
rel_412_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010000");
proc_if_412_1: process (rel_412_4)
is
begin
if rel_412_4 then
sm_lcd_secondend_en_join_412_1 <= true;
else
sm_lcd_secondend_en_join_412_1 <= false;
end if;
end process proc_if_412_1;
rel_418_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010001");
proc_if_418_1: process (rel_418_4)
is
begin
if rel_418_4 then
sm_lcd_secondstart_en_join_418_1 <= true;
else
sm_lcd_secondstart_en_join_418_1 <= false;
end if;
end process proc_if_418_1;
rel_424_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010010");
proc_if_424_1: process (rel_424_4)
is
begin
if rel_424_4 then
sm_lcd_send_en_join_424_1 <= true;
else
sm_lcd_send_en_join_424_1 <= false;
end if;
end process proc_if_424_1;
rel_430_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010011");
proc_if_430_1: process (rel_430_4)
is
begin
if rel_430_4 then
sm_lcd_totalcmdtransfer_en_join_430_1 <= true;
else
sm_lcd_totalcmdtransfer_en_join_430_1 <= false;
end if;
end process proc_if_430_1;
rel_436_4 <= opcode_160_1_concat = std_logic_vector_to_unsigned("10100000000010100");
proc_if_436_1: process (rel_436_4)
is
begin
if rel_436_4 then
sm_leds_en_join_436_1 <= true;
else
sm_leds_en_join_436_1 <= false;
end if;
end process proc_if_436_1;
slice_451_44 <= u2u_slice(wrdbus_1_1186, 17, 0);
slice_454_41 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_457_41 <= u2u_slice(wrdbus_1_1186, 17, 0);
slice_460_47 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_463_47 <= u2u_slice(wrdbus_1_1186, 3, 0);
slice_466_48 <= u2u_slice(wrdbus_1_1186, 2, 0);
slice_469_38 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_472_46 <= u2u_slice(wrdbus_1_1186, 1, 0);
slice_475_45 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_478_40 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_481_42 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_484_42 <= u2u_slice(wrdbus_1_1186, 3, 0);
slice_487_40 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_490_37 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_493_40 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_496_38 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_499_41 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_502_43 <= u2u_slice(wrdbus_1_1186, 8, 0);
slice_505_36 <= u2u_slice(wrdbus_1_1186, 0, 0);
slice_508_48 <= u2u_slice(wrdbus_1_1186, 7, 0);
slice_511_32 <= u2u_slice(wrdbus_1_1186, 7, 0);
rel_521_4 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("00");
rel_524_8 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("01");
rel_527_8 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("10");
rel_530_8 <= bankaddr_reg_519_26 = std_logic_vector_to_unsigned("11");
proc_if_521_1: process (ram_bank_out_reg_203_30, read_bank_out_reg_516_31, reg_bank_out_reg_98_30, rel_521_4, rel_524_8, rel_527_8, rel_530_8)
is
begin
if rel_521_4 then
read_bank_out_reg_join_521_1 <= ram_bank_out_reg_203_30;
elsif rel_524_8 then
read_bank_out_reg_join_521_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
elsif rel_527_8 then
read_bank_out_reg_join_521_1 <= reg_bank_out_reg_98_30;
elsif rel_530_8 then
read_bank_out_reg_join_521_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000");
else
read_bank_out_reg_join_521_1 <= read_bank_out_reg_516_31;
end if;
end process proc_if_521_1;
reg_bank_out_reg_98_30_next <= reg_bank_out_reg_join_101_1;
ram_bank_out_reg_203_30_next <= ram_bank_out_reg_join_205_1;
sm_lcd_charactermap_we_reg_226_40_next <= sm_lcd_charactermap_we_reg_join_235_1;
sm_lcd_characters_we_reg_245_38_next <= sm_lcd_characters_we_reg_join_254_1;
sm_lcd_commands_we_reg_264_36_next <= sm_lcd_commands_we_reg_join_273_1;
cast_sm_lcd_charactermap_addr_reg_287_1_next <= u2u_cast(sm_lcd_charactermap_addr_reg_join_289_1, 0, 12, 0);
sm_lcd_charactermap_addr_reg_287_1_next <= cast_sm_lcd_charactermap_addr_reg_287_1_next;
sm_lcd_charactermap_addr_reg_287_1_en <= sm_lcd_charactermap_addr_reg_join_289_1_en;
cast_sm_lcd_characters_addr_reg_295_1_next <= u2u_cast(sm_lcd_characters_addr_reg_join_297_1, 0, 9, 0);
sm_lcd_characters_addr_reg_295_1_next <= cast_sm_lcd_characters_addr_reg_295_1_next;
sm_lcd_characters_addr_reg_295_1_en <= sm_lcd_characters_addr_reg_join_297_1_en;
cast_sm_lcd_commands_addr_reg_303_1_next <= u2u_cast(sm_lcd_commands_addr_reg_join_305_1, 0, 8, 0);
sm_lcd_commands_addr_reg_303_1_next <= cast_sm_lcd_commands_addr_reg_303_1_next;
sm_lcd_commands_addr_reg_303_1_en <= sm_lcd_commands_addr_reg_join_305_1_en;
read_bank_out_reg_516_31_next <= read_bank_out_reg_join_521_1;
bankaddr_reg_519_26_next <= bankaddr_1_1194;
read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_516_31);
sm_buzzer_dutycycle_din <= unsigned_to_std_logic_vector(slice_451_44);
sm_buzzer_dutycycle_en <= boolean_to_vector(sm_buzzer_dutycycle_en_join_316_1);
sm_buzzer_enable_din <= unsigned_to_std_logic_vector(slice_454_41);
sm_buzzer_enable_en <= boolean_to_vector(sm_buzzer_enable_en_join_322_1);
sm_buzzer_period_din <= unsigned_to_std_logic_vector(slice_457_41);
sm_buzzer_period_en <= boolean_to_vector(sm_buzzer_period_en_join_328_1);
sm_lcd_backgroundcolor_din <= unsigned_to_std_logic_vector(slice_460_47);
sm_lcd_backgroundcolor_en <= boolean_to_vector(sm_lcd_backgroundcolor_en_join_334_1);
sm_lcd_characteroffset_din <= unsigned_to_std_logic_vector(slice_463_47);
sm_lcd_characteroffset_en <= boolean_to_vector(sm_lcd_characteroffset_en_join_340_1);
sm_lcd_charactersselect_din <= unsigned_to_std_logic_vector(slice_466_48);
sm_lcd_charactersselect_en <= boolean_to_vector(sm_lcd_charactersselect_en_join_346_1);
sm_lcd_colset_din <= unsigned_to_std_logic_vector(slice_469_38);
sm_lcd_colset_en <= boolean_to_vector(sm_lcd_colset_en_join_352_1);
sm_lcd_configlocation_din <= unsigned_to_std_logic_vector(slice_472_46);
sm_lcd_configlocation_en <= boolean_to_vector(sm_lcd_configlocation_en_join_358_1);
sm_lcd_dividerselect_din <= unsigned_to_std_logic_vector(slice_475_45);
sm_lcd_dividerselect_en <= boolean_to_vector(sm_lcd_dividerselect_en_join_364_1);
sm_lcd_firstend_din <= unsigned_to_std_logic_vector(slice_478_40);
sm_lcd_firstend_en <= boolean_to_vector(sm_lcd_firstend_en_join_370_1);
sm_lcd_firststart_din <= unsigned_to_std_logic_vector(slice_481_42);
sm_lcd_firststart_en <= boolean_to_vector(sm_lcd_firststart_en_join_376_1);
sm_lcd_lineoffset_din <= unsigned_to_std_logic_vector(slice_484_42);
sm_lcd_lineoffset_en <= boolean_to_vector(sm_lcd_lineoffset_en_join_382_1);
sm_lcd_ramwrite_din <= unsigned_to_std_logic_vector(slice_487_40);
sm_lcd_ramwrite_en <= boolean_to_vector(sm_lcd_ramwrite_en_join_388_1);
sm_lcd_reset_din <= unsigned_to_std_logic_vector(slice_490_37);
sm_lcd_reset_en <= boolean_to_vector(sm_lcd_reset_en_join_394_1);
sm_lcd_resetlcd_din <= unsigned_to_std_logic_vector(slice_493_40);
sm_lcd_resetlcd_en <= boolean_to_vector(sm_lcd_resetlcd_en_join_400_1);
sm_lcd_rowset_din <= unsigned_to_std_logic_vector(slice_496_38);
sm_lcd_rowset_en <= boolean_to_vector(sm_lcd_rowset_en_join_406_1);
sm_lcd_secondend_din <= unsigned_to_std_logic_vector(slice_499_41);
sm_lcd_secondend_en <= boolean_to_vector(sm_lcd_secondend_en_join_412_1);
sm_lcd_secondstart_din <= unsigned_to_std_logic_vector(slice_502_43);
sm_lcd_secondstart_en <= boolean_to_vector(sm_lcd_secondstart_en_join_418_1);
sm_lcd_send_din <= unsigned_to_std_logic_vector(slice_505_36);
sm_lcd_send_en <= boolean_to_vector(sm_lcd_send_en_join_424_1);
sm_lcd_totalcmdtransfer_din <= unsigned_to_std_logic_vector(slice_508_48);
sm_lcd_totalcmdtransfer_en <= boolean_to_vector(sm_lcd_totalcmdtransfer_en_join_430_1);
sm_leds_din <= unsigned_to_std_logic_vector(slice_511_32);
sm_leds_en <= boolean_to_vector(sm_leds_en_join_436_1);
sm_lcd_charactermap_addr <= unsigned_to_std_logic_vector(sm_lcd_charactermap_addr_reg_287_1);
sm_lcd_charactermap_din <= unsigned_to_std_logic_vector(slice_214_44);
sm_lcd_charactermap_we <= boolean_to_vector(sm_lcd_charactermap_we_reg_226_40);
sm_lcd_characters_addr <= unsigned_to_std_logic_vector(sm_lcd_characters_addr_reg_295_1);
sm_lcd_characters_din <= unsigned_to_std_logic_vector(slice_217_42);
sm_lcd_characters_we <= boolean_to_vector(sm_lcd_characters_we_reg_245_38);
sm_lcd_commands_addr <= unsigned_to_std_logic_vector(sm_lcd_commands_addr_reg_303_1);
sm_lcd_commands_din <= unsigned_to_std_logic_vector(slice_220_40);
sm_lcd_commands_we <= boolean_to_vector(sm_lcd_commands_we_reg_264_36);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xldelay is
generic(width : integer := -1;
latency : integer := -1;
reg_retiming : integer := 0);
port(d : in std_logic_vector (width-1 downto 0);
ce : in std_logic;
clk : in std_logic;
en : in std_logic;
q : out std_logic_vector (width-1 downto 0));
end xldelay;
architecture behavior of xldelay is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component synth_reg_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
signal internal_ce : std_logic;
begin
internal_ce <= ce and en;
srl_delay: if (reg_retiming = 0) or (latency < 1) generate
synth_reg_srl_inst : synth_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate srl_delay;
reg_delay: if (reg_retiming = 1) and (latency >= 1) generate
synth_reg_reg_inst : synth_reg_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate reg_delay;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_4ad38e8aed is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
d3 : in std_logic_vector((1 - 1) downto 0);
d4 : in std_logic_vector((1 - 1) downto 0);
d5 : in std_logic_vector((1 - 1) downto 0);
d6 : in std_logic_vector((1 - 1) downto 0);
d7 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_4ad38e8aed;
architecture behavior of logical_4ad38e8aed is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal d2_1_30: std_logic_vector((1 - 1) downto 0);
signal d3_1_33: std_logic_vector((1 - 1) downto 0);
signal d4_1_36: std_logic_vector((1 - 1) downto 0);
signal d5_1_39: std_logic_vector((1 - 1) downto 0);
signal d6_1_42: std_logic_vector((1 - 1) downto 0);
signal d7_1_45: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bit: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30 or d3_1_33 or d4_1_36 or d5_1_39 or d6_1_42 or d7_1_45;
y <= fully_2_1_bit;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_2b3acb49f4 is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
in2 : in std_logic_vector((1 - 1) downto 0);
in3 : in std_logic_vector((1 - 1) downto 0);
in4 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((5 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_2b3acb49f4;
architecture behavior of concat_2b3acb49f4 is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((1 - 1) downto 0);
signal in2_1_31: unsigned((1 - 1) downto 0);
signal in3_1_35: unsigned((1 - 1) downto 0);
signal in4_1_39: unsigned((1 - 1) downto 0);
signal y_2_1_concat: unsigned((5 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
in3_1_35 <= std_logic_vector_to_unsigned(in3);
in4_1_39 <= std_logic_vector_to_unsigned(in4);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35) & unsigned_to_std_logic_vector(in4_1_39));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_6293007044 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_6293007044;
architecture behavior of constant_6293007044 is
begin
op <= "1";
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_37567836aa is
port (
op : out std_logic_vector((32 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_37567836aa;
architecture behavior of constant_37567836aa is
begin
op <= "00000000000000000000000000000000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_2c45f290ed is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((16 - 1) downto 0);
d1 : in std_logic_vector((16 - 1) downto 0);
y : out std_logic_vector((16 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_2c45f290ed;
architecture behavior of mux_2c45f290ed is
signal sel_1_20: std_logic_vector((1 - 1) downto 0);
signal d0_1_24: std_logic_vector((16 - 1) downto 0);
signal d1_1_27: std_logic_vector((16 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((16 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20)
is
begin
case sel_1_20 is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_b1e9d7c303 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_b1e9d7c303;
architecture behavior of logical_b1e9d7c303 is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal bit_2_26: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bitnot: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
bit_2_26 <= d0_1_24 or d1_1_27;
fully_2_1_bitnot <= not bit_2_26;
y <= fully_2_1_bitnot;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity accum_2cb0e56e96 is
port (
b : in std_logic_vector((1 - 1) downto 0);
rst : in std_logic_vector((1 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((7 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end accum_2cb0e56e96;
architecture behavior of accum_2cb0e56e96 is
signal b_17_24: unsigned((1 - 1) downto 0);
signal rst_17_27: boolean;
signal en_17_32: boolean;
signal accum_reg_41_23: unsigned((7 - 1) downto 0) := "0000000";
signal accum_reg_41_23_rst: std_logic;
signal accum_reg_41_23_en: std_logic;
signal cast_51_42: unsigned((7 - 1) downto 0);
signal accum_reg_join_47_1: unsigned((8 - 1) downto 0);
signal accum_reg_join_47_1_en: std_logic;
signal accum_reg_join_47_1_rst: std_logic;
begin
b_17_24 <= std_logic_vector_to_unsigned(b);
rst_17_27 <= ((rst) = "1");
en_17_32 <= ((en) = "1");
proc_accum_reg_41_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (accum_reg_41_23_rst = '1')) then
accum_reg_41_23 <= "0000000";
elsif ((ce = '1') and (accum_reg_41_23_en = '1')) then
accum_reg_41_23 <= accum_reg_41_23 + cast_51_42;
end if;
end if;
end process proc_accum_reg_41_23;
cast_51_42 <= u2u_cast(b_17_24, 0, 7, 0);
proc_if_47_1: process (accum_reg_41_23, cast_51_42, en_17_32, rst_17_27)
is
begin
if rst_17_27 then
accum_reg_join_47_1_rst <= '1';
elsif en_17_32 then
accum_reg_join_47_1_rst <= '0';
else
accum_reg_join_47_1_rst <= '0';
end if;
if en_17_32 then
accum_reg_join_47_1_en <= '1';
else
accum_reg_join_47_1_en <= '0';
end if;
end process proc_if_47_1;
accum_reg_41_23_rst <= accum_reg_join_47_1_rst;
accum_reg_41_23_en <= accum_reg_join_47_1_en;
q <= unsigned_to_std_logic_vector(accum_reg_41_23);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity accum_be45dd0aa2 is
port (
b : in std_logic_vector((1 - 1) downto 0);
rst : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end accum_be45dd0aa2;
architecture behavior of accum_be45dd0aa2 is
signal b_17_24: unsigned((1 - 1) downto 0);
signal rst_17_27: boolean;
signal accum_reg_41_23: unsigned((4 - 1) downto 0) := "0000";
signal accum_reg_41_23_rst: std_logic;
signal cast_51_42: unsigned((4 - 1) downto 0);
signal accum_reg_join_47_1: unsigned((5 - 1) downto 0);
signal accum_reg_join_47_1_rst: std_logic;
begin
b_17_24 <= std_logic_vector_to_unsigned(b);
rst_17_27 <= ((rst) = "1");
proc_accum_reg_41_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (accum_reg_41_23_rst = '1')) then
accum_reg_41_23 <= "0000";
elsif (ce = '1') then
accum_reg_41_23 <= accum_reg_41_23 + cast_51_42;
end if;
end if;
end process proc_accum_reg_41_23;
cast_51_42 <= u2u_cast(b_17_24, 0, 4, 0);
proc_if_47_1: process (accum_reg_41_23, cast_51_42, rst_17_27)
is
begin
if rst_17_27 then
accum_reg_join_47_1_rst <= '1';
else
accum_reg_join_47_1_rst <= '0';
end if;
end process proc_if_47_1;
accum_reg_41_23_rst <= accum_reg_join_47_1_rst;
q <= unsigned_to_std_logic_vector(accum_reg_41_23);
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xladdsub is
generic (
core_name0: string := "";
a_width: integer := 16;
a_bin_pt: integer := 4;
a_arith: integer := xlUnsigned;
c_in_width: integer := 16;
c_in_bin_pt: integer := 4;
c_in_arith: integer := xlUnsigned;
c_out_width: integer := 16;
c_out_bin_pt: integer := 4;
c_out_arith: integer := xlUnsigned;
b_width: integer := 8;
b_bin_pt: integer := 2;
b_arith: integer := xlUnsigned;
s_width: integer := 17;
s_bin_pt: integer := 4;
s_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
full_s_width: integer := 17;
full_s_arith: integer := xlUnsigned;
mode: integer := xlAddMode;
extra_registers: integer := 0;
latency: integer := 0;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
c_latency: integer := 0;
c_output_width: integer := 17;
c_has_q : integer := 1;
c_has_s : integer := 0;
c_has_c_out : integer := 0;
c_has_q_c_out : integer := 0;
c_has_b_out : integer := 0;
c_has_q_b_out : integer := 0;
c_has_q_ovfl : integer := 0;
c_has_ovfl : integer := 0
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
c_in : in std_logic_vector (0 downto 0) := "0";
ce: in std_logic;
clr: in std_logic := '0';
clk: in std_logic;
rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
en: in std_logic_vector(en_width - 1 downto 0) := "1";
c_out : out std_logic_vector (0 downto 0);
s: out std_logic_vector(s_width - 1 downto 0)
);
end xladdsub ;
architecture behavior of xladdsub is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function format_input(inp: std_logic_vector; old_width, delta, new_arith,
new_width: integer)
return std_logic_vector
is
variable vec: std_logic_vector(old_width-1 downto 0);
variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0);
variable result: std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
constant full_a_width: integer := full_s_width;
constant full_b_width: integer := full_s_width;
signal full_a: std_logic_vector(full_a_width - 1 downto 0);
signal full_b: std_logic_vector(full_b_width - 1 downto 0);
signal core_s: std_logic_vector(full_s_width - 1 downto 0);
signal conv_s: std_logic_vector(s_width - 1 downto 0);
signal temp_cout : std_logic;
signal internal_clr: std_logic;
signal internal_ce: std_logic;
signal extra_reg_ce: std_logic;
signal override: std_logic;
signal logic1: std_logic_vector(0 downto 0);
component adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port (
a: in std_logic_vector( 9 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(9 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3:
component is "black_box";
component adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port (
a: in std_logic_vector( 9 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(9 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_453ed16ba8e84295:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_453ed16ba8e84295:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_453ed16ba8e84295:
component is "black_box";
component adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port (
a: in std_logic_vector( 5 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(5 - 1 downto 0)
);
end component;
attribute syn_black_box of adder_subtracter_virtex2p_7_0_7182743c9e7adf5e:
component is true;
attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_7182743c9e7adf5e:
component is "true";
attribute box_type of adder_subtracter_virtex2p_7_0_7182743c9e7adf5e:
component is "black_box";
begin
internal_clr <= (clr or (rst(0))) and ce;
internal_ce <= ce and en(0);
logic1(0) <= '1';
addsub_process: process(a, b, core_s)
begin
full_a <= format_input(a, a_width, b_bin_pt - a_bin_pt, a_arith,
full_a_width);
full_b <= format_input(b, b_width, a_bin_pt - b_bin_pt, b_arith,
full_b_width);
conv_s <= convert_type(core_s, full_s_width, full_s_bin_pt, full_s_arith,
s_width, s_bin_pt, s_arith, quantization, overflow);
end process addsub_process;
comp0: if ((core_name0 = "adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3")) generate
core_instance0: adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
comp1: if ((core_name0 = "adder_subtracter_virtex2p_7_0_453ed16ba8e84295")) generate
core_instance1: adder_subtracter_virtex2p_7_0_453ed16ba8e84295
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
comp2: if ((core_name0 = "adder_subtracter_virtex2p_7_0_7182743c9e7adf5e")) generate
core_instance2: adder_subtracter_virtex2p_7_0_7182743c9e7adf5e
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
latency_test: if (extra_registers > 0) generate
override_test: if (c_latency > 1) generate
override_pipe: synth_reg
generic map (
width => 1,
latency => c_latency)
port map (
i => logic1,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o(0) => override);
extra_reg_ce <= ce and en(0) and override;
end generate override_test;
no_override: if (c_latency = 0) or (c_latency = 1) generate
extra_reg_ce <= ce and en(0);
end generate no_override;
extra_reg: synth_reg
generic map (
width => s_width,
latency => extra_registers
)
port map (
i => conv_s,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => s
);
cout_test : if((c_has_c_out = 1) or
(c_has_b_out = 1) or
(c_has_q_c_out = 1) or
(c_has_q_b_out = 1)) generate
c_out_extra_reg: synth_reg
generic map (
width => 1,
latency => extra_registers
)
port map (
i(0) => temp_cout,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => c_out
);
end generate cout_test;
end generate;
latency_s: if ((latency = 0) or (extra_registers = 0)) generate
s <= conv_s;
end generate latency_s;
latency0: if ( ((latency = 0) or (extra_registers = 0)) and
((c_has_b_out = 1) or
(c_has_q_c_out = 1) or
(c_has_c_out = 1) or
(c_has_q_b_out = 1))) generate
c_out(0) <= temp_cout;
end generate latency0;
tie_dangling_cout: if ((c_has_c_out = 0) and
(c_has_b_out = 0) and
(c_has_q_c_out = 0) and
(c_has_q_b_out = 0)) generate
c_out <= "0";
end generate tie_dangling_cout;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_f62149b02a is
port (
in0 : in std_logic_vector((2 - 1) downto 0);
in1 : in std_logic_vector((7 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_f62149b02a;
architecture behavior of concat_f62149b02a is
signal in0_1_23: unsigned((2 - 1) downto 0);
signal in1_1_27: unsigned((7 - 1) downto 0);
signal y_2_1_concat: unsigned((9 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_1ece14600f is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_1ece14600f;
architecture behavior of concat_1ece14600f is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((9 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_443ed96427 is
port (
op : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_443ed96427;
architecture behavior of constant_443ed96427 is
begin
op <= "101011100";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_145086465d is
port (
op : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_145086465d;
architecture behavior of constant_145086465d is
begin
op <= "1000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_fb9f6d3796 is
port (
op : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_fb9f6d3796;
architecture behavior of constant_fb9f6d3796 is
begin
op <= "100010101";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_09a4afb2ee is
port (
op : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_09a4afb2ee;
architecture behavior of constant_09a4afb2ee is
begin
op <= "101110101";
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlcounter_limit is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned;
cnt_63_48: integer:= 0;
cnt_47_32: integer:= 0;
cnt_31_16: integer:= 0;
cnt_15_0: integer:= 0;
count_limited: integer := 0
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_limit ;
architecture behavior of xlcounter_limit is
signal high_cnt_to: std_logic_vector(31 downto 0);
signal low_cnt_to: std_logic_vector(31 downto 0);
signal cnt_to: std_logic_vector(63 downto 0);
signal core_sinit, op_thresh0, core_ce: std_logic;
signal rst_overrides_en: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
-- synopsys translate_off
signal real_op : real;
-- synopsys translate_on
function equals(op, cnt_to : std_logic_vector; width, arith : integer)
return std_logic
is
variable signed_op, signed_cnt_to : signed (width - 1 downto 0);
variable unsigned_op, unsigned_cnt_to : unsigned (width - 1 downto 0);
variable result : std_logic;
begin
-- synopsys translate_off
if ((is_XorU(op)) or (is_XorU(cnt_to)) ) then
result := '0';
return result;
end if;
-- synopsys translate_on
if (op = cnt_to) then
result := '1';
else
result := '0';
end if;
return result;
end;
component binary_counter_virtex2p_7_0_32a1863440903b9d
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_32a1863440903b9d:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_32a1863440903b9d:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_32a1863440903b9d:
component is "black_box";
component binary_counter_virtex2p_7_0_23542cbcca0efa2e
port (
clk: in std_logic;
ce: in std_logic;
sinit: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of binary_counter_virtex2p_7_0_23542cbcca0efa2e:
component is true;
attribute fpga_dont_touch of binary_counter_virtex2p_7_0_23542cbcca0efa2e:
component is "true";
attribute box_type of binary_counter_virtex2p_7_0_23542cbcca0efa2e:
component is "black_box";
-- synopsys translate_off
constant zeroVec : std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec : std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr : string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr : string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
begin
-- synopsys translate_off
-- synopsys translate_on
cnt_to(63 downto 48) <= integer_to_std_logic_vector(cnt_63_48, 16, op_arith);
cnt_to(47 downto 32) <= integer_to_std_logic_vector(cnt_47_32, 16, op_arith);
cnt_to(31 downto 16) <= integer_to_std_logic_vector(cnt_31_16, 16, op_arith);
cnt_to(15 downto 0) <= integer_to_std_logic_vector(cnt_15_0, 16, op_arith);
op <= op_net;
core_ce <= ce and en(0);
rst_overrides_en <= rst(0) or en(0);
limit : if (count_limited = 1) generate
eq_cnt_to : process (op_net, cnt_to)
begin
op_thresh0 <= equals(op_net, cnt_to(op_width - 1 downto 0),
op_width, op_arith);
end process;
core_sinit <= (op_thresh0 or clr or rst(0)) and ce and rst_overrides_en;
end generate;
no_limit : if (count_limited = 0) generate
core_sinit <= (clr or rst(0)) and ce and rst_overrides_en;
end generate;
comp0: if ((core_name0 = "binary_counter_virtex2p_7_0_32a1863440903b9d")) generate
core_instance0: binary_counter_virtex2p_7_0_32a1863440903b9d
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
comp1: if ((core_name0 = "binary_counter_virtex2p_7_0_23542cbcca0efa2e")) generate
core_instance1: binary_counter_virtex2p_7_0_23542cbcca0efa2e
port map (
clk => clk,
ce => core_ce,
sinit => core_sinit,
q => op_net
);
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e5b38cca3b is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e5b38cca3b;
architecture behavior of inverter_e5b38cca3b is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_push_front_pop_back_en <= '0';
op <= boolean_to_vector(internal_ip_12_1_bitnot);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_aacf6e1b0e is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_aacf6e1b0e;
architecture behavior of logical_aacf6e1b0e is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 or d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_80f90b97d0 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_80f90b97d0;
architecture behavior of logical_80f90b97d0 is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 and d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_d99e59b6d4 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_d99e59b6d4;
architecture behavior of mux_d99e59b6d4 is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic;
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= std_logic_to_vector(unregy_join_6_1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_1f00a411aa is
port (
sel : in std_logic_vector((4 - 1) downto 0);
d0 : in std_logic_vector((9 - 1) downto 0);
d1 : in std_logic_vector((9 - 1) downto 0);
d2 : in std_logic_vector((9 - 1) downto 0);
d3 : in std_logic_vector((9 - 1) downto 0);
d4 : in std_logic_vector((9 - 1) downto 0);
d5 : in std_logic_vector((9 - 1) downto 0);
d6 : in std_logic_vector((9 - 1) downto 0);
d7 : in std_logic_vector((9 - 1) downto 0);
d8 : in std_logic_vector((9 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_1f00a411aa;
architecture behavior of mux_1f00a411aa is
signal sel_1_20: std_logic_vector((4 - 1) downto 0);
signal d0_1_24: std_logic_vector((9 - 1) downto 0);
signal d1_1_27: std_logic_vector((9 - 1) downto 0);
signal d2_1_30: std_logic_vector((9 - 1) downto 0);
signal d3_1_33: std_logic_vector((9 - 1) downto 0);
signal d4_1_36: std_logic_vector((9 - 1) downto 0);
signal d5_1_39: std_logic_vector((9 - 1) downto 0);
signal d6_1_42: std_logic_vector((9 - 1) downto 0);
signal d7_1_45: std_logic_vector((9 - 1) downto 0);
signal d8_1_48: std_logic_vector((9 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((9 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
d8_1_48 <= d8;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, d6_1_42, d7_1_45, d8_1_48, sel_1_20)
is
begin
case sel_1_20 is
when "0000" =>
unregy_join_6_1 <= d0_1_24;
when "0001" =>
unregy_join_6_1 <= d1_1_27;
when "0010" =>
unregy_join_6_1 <= d2_1_30;
when "0011" =>
unregy_join_6_1 <= d3_1_33;
when "0100" =>
unregy_join_6_1 <= d4_1_36;
when "0101" =>
unregy_join_6_1 <= d5_1_39;
when "0110" =>
unregy_join_6_1 <= d6_1_42;
when "0111" =>
unregy_join_6_1 <= d7_1_45;
when others =>
unregy_join_6_1 <= d8_1_48;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_92c392c8b6 is
port (
a : in std_logic_vector((7 - 1) downto 0);
b : in std_logic_vector((9 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_92c392c8b6;
architecture behavior of relational_92c392c8b6 is
signal a_1_31: unsigned((7 - 1) downto 0);
signal b_1_34: signed((9 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal cast_20_12: signed((9 - 1) downto 0);
signal result_20_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_signed(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
cast_20_12 <= u2s_cast(a_1_31, 0, 9, 0);
result_20_3_rel <= cast_20_12 <= b_1_34;
op_mem_32_22_front_din <= result_20_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_fb96203f91 is
port (
a : in std_logic_vector((4 - 1) downto 0);
b : in std_logic_vector((4 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_fb96203f91;
architecture behavior of relational_fb96203f91 is
signal a_1_31: unsigned((4 - 1) downto 0);
signal b_1_34: unsigned((4 - 1) downto 0);
signal result_16_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
result_16_3_rel <= a_1_31 < b_1_34;
op <= boolean_to_vector(result_16_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_998e20a1ca is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((8 - 1) downto 0);
d1 : in std_logic_vector((8 - 1) downto 0);
d2 : in std_logic_vector((8 - 1) downto 0);
d3 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_998e20a1ca;
architecture behavior of mux_998e20a1ca is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((8 - 1) downto 0);
signal d1_1_27: std_logic_vector((8 - 1) downto 0);
signal d2_1_30: std_logic_vector((8 - 1) downto 0);
signal d3_1_33: std_logic_vector((8 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((8 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_32864ba5d6 is
port (
in0 : in std_logic_vector((4 - 1) downto 0);
in1 : in std_logic_vector((3 - 1) downto 0);
y : out std_logic_vector((7 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_32864ba5d6;
architecture behavior of concat_32864ba5d6 is
signal in0_1_23: unsigned((4 - 1) downto 0);
signal in1_1_27: unsigned((3 - 1) downto 0);
signal y_2_1_concat: unsigned((7 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_822933f89b is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_822933f89b;
architecture behavior of constant_822933f89b is
begin
op <= "000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_21d4a28b7e is
port (
op : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_21d4a28b7e;
architecture behavior of constant_21d4a28b7e is
begin
op <= "00000011";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_b940b9054a is
port (
op : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_b940b9054a;
architecture behavior of constant_b940b9054a is
begin
op <= "00001010";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_78218439f3 is
port (
in0 : in std_logic_vector((3 - 1) downto 0);
in1 : in std_logic_vector((4 - 1) downto 0);
in2 : in std_logic_vector((4 - 1) downto 0);
y : out std_logic_vector((11 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_78218439f3;
architecture behavior of concat_78218439f3 is
signal in0_1_23: unsigned((3 - 1) downto 0);
signal in1_1_27: unsigned((4 - 1) downto 0);
signal in2_1_31: unsigned((4 - 1) downto 0);
signal y_2_1_concat: unsigned((11 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
in2_1_31 <= std_logic_vector_to_unsigned(in2);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_25ab81b400 is
port (
in0 : in std_logic_vector((8 - 1) downto 0);
in1 : in std_logic_vector((6 - 1) downto 0);
y : out std_logic_vector((14 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_25ab81b400;
architecture behavior of concat_25ab81b400 is
signal in0_1_23: unsigned((8 - 1) downto 0);
signal in1_1_27: unsigned((6 - 1) downto 0);
signal y_2_1_concat: unsigned((14 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_e6f5ee726b is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_e6f5ee726b;
architecture behavior of concat_e6f5ee726b is
signal in0_1_23: unsigned((1 - 1) downto 0);
signal in1_1_27: unsigned((1 - 1) downto 0);
signal y_2_1_concat: unsigned((2 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_469094441c is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_469094441c;
architecture behavior of constant_469094441c is
begin
op <= "100";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_a1c496ea88 is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_a1c496ea88;
architecture behavior of constant_a1c496ea88 is
begin
op <= "001";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_2ec2057ae3 is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((3 - 1) downto 0);
d1 : in std_logic_vector((3 - 1) downto 0);
d2 : in std_logic_vector((3 - 1) downto 0);
d3 : in std_logic_vector((3 - 1) downto 0);
y : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_2ec2057ae3;
architecture behavior of mux_2ec2057ae3 is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((3 - 1) downto 0);
signal d1_1_27: std_logic_vector((3 - 1) downto 0);
signal d2_1_30: std_logic_vector((3 - 1) downto 0);
signal d3_1_33: std_logic_vector((3 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((3 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_7586447000 is
port (
sel : in std_logic_vector((3 - 1) downto 0);
d0 : in std_logic_vector((9 - 1) downto 0);
d1 : in std_logic_vector((9 - 1) downto 0);
d2 : in std_logic_vector((9 - 1) downto 0);
d3 : in std_logic_vector((9 - 1) downto 0);
d4 : in std_logic_vector((9 - 1) downto 0);
d5 : in std_logic_vector((9 - 1) downto 0);
d6 : in std_logic_vector((9 - 1) downto 0);
d7 : in std_logic_vector((9 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_7586447000;
architecture behavior of mux_7586447000 is
signal sel_1_20: std_logic_vector((3 - 1) downto 0);
signal d0_1_24: std_logic_vector((9 - 1) downto 0);
signal d1_1_27: std_logic_vector((9 - 1) downto 0);
signal d2_1_30: std_logic_vector((9 - 1) downto 0);
signal d3_1_33: std_logic_vector((9 - 1) downto 0);
signal d4_1_36: std_logic_vector((9 - 1) downto 0);
signal d5_1_39: std_logic_vector((9 - 1) downto 0);
signal d6_1_42: std_logic_vector((9 - 1) downto 0);
signal d7_1_45: std_logic_vector((9 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((9 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, d6_1_42, d7_1_45, sel_1_20)
is
begin
case sel_1_20 is
when "000" =>
unregy_join_6_1 <= d0_1_24;
when "001" =>
unregy_join_6_1 <= d1_1_27;
when "010" =>
unregy_join_6_1 <= d2_1_30;
when "011" =>
unregy_join_6_1 <= d3_1_33;
when "100" =>
unregy_join_6_1 <= d4_1_36;
when "101" =>
unregy_join_6_1 <= d5_1_39;
when "110" =>
unregy_join_6_1 <= d6_1_42;
when others =>
unregy_join_6_1 <= d7_1_45;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_f7cb2b0c31 is
port (
a : in std_logic_vector((6 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_f7cb2b0c31;
architecture behavior of relational_f7cb2b0c31 is
signal a_1_31: unsigned((6 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
signal cast_12_17: unsigned((6 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
cast_12_17 <= u2u_cast(b_1_34, 0, 6, 0);
result_12_3_rel <= a_1_31 = cast_12_17;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_ee03197e2c is
port (
a : in std_logic_vector((4 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_ee03197e2c;
architecture behavior of relational_ee03197e2c is
signal a_1_31: unsigned((4 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
signal cast_12_17: unsigned((4 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
cast_12_17 <= u2u_cast(b_1_34, 0, 4, 0);
result_12_3_rel <= a_1_31 = cast_12_17;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_04b069dd89 is
port (
a : in std_logic_vector((3 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_04b069dd89;
architecture behavior of relational_04b069dd89 is
signal a_1_31: unsigned((3 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
signal cast_12_17: unsigned((3 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
cast_12_17 <= u2u_cast(b_1_34, 0, 3, 0);
result_12_3_rel <= a_1_31 = cast_12_17;
op <= boolean_to_vector(result_12_3_rel);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_8e3eece8f2 is
port (
sel : in std_logic_vector((4 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
d3 : in std_logic_vector((1 - 1) downto 0);
d4 : in std_logic_vector((1 - 1) downto 0);
d5 : in std_logic_vector((1 - 1) downto 0);
d6 : in std_logic_vector((1 - 1) downto 0);
d7 : in std_logic_vector((1 - 1) downto 0);
d8 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_8e3eece8f2;
architecture behavior of mux_8e3eece8f2 is
signal sel_1_20: std_logic_vector((4 - 1) downto 0);
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal d2_1_30: std_logic_vector((1 - 1) downto 0);
signal d3_1_33: std_logic_vector((1 - 1) downto 0);
signal d4_1_36: std_logic_vector((1 - 1) downto 0);
signal d5_1_39: std_logic_vector((1 - 1) downto 0);
signal d6_1_42: std_logic_vector((1 - 1) downto 0);
signal d7_1_45: std_logic_vector((1 - 1) downto 0);
signal d8_1_48: std_logic_vector((1 - 1) downto 0);
type array_type_pipe_30_22 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0);
signal pipe_30_22: array_type_pipe_30_22 := (
0 => "0");
signal pipe_30_22_front_din: std_logic_vector((1 - 1) downto 0);
signal pipe_30_22_back: std_logic_vector((1 - 1) downto 0);
signal pipe_30_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
d8_1_48 <= d8;
pipe_30_22_back <= pipe_30_22(0);
proc_pipe_30_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_30_22_push_front_pop_back_en = '1')) then
pipe_30_22(0) <= pipe_30_22_front_din;
end if;
end if;
end process proc_pipe_30_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, d6_1_42, d7_1_45, d8_1_48, sel_1_20)
is
begin
case sel_1_20 is
when "0000" =>
unregy_join_6_1 <= d0_1_24;
when "0001" =>
unregy_join_6_1 <= d1_1_27;
when "0010" =>
unregy_join_6_1 <= d2_1_30;
when "0011" =>
unregy_join_6_1 <= d3_1_33;
when "0100" =>
unregy_join_6_1 <= d4_1_36;
when "0101" =>
unregy_join_6_1 <= d5_1_39;
when "0110" =>
unregy_join_6_1 <= d6_1_42;
when "0111" =>
unregy_join_6_1 <= d7_1_45;
when others =>
unregy_join_6_1 <= d8_1_48;
end case;
end process proc_switch_6_1;
pipe_30_22_front_din <= unregy_join_6_1;
pipe_30_22_push_front_pop_back_en <= '1';
y <= pipe_30_22_back;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_938d99ac11 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_938d99ac11;
architecture behavior of logical_938d99ac11 is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bit: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
fully_2_1_bit <= d0_1_24 and d1_1_27;
y <= fully_2_1_bit;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_06590e4008 is
port (
op : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_06590e4008;
architecture behavior of constant_06590e4008 is
begin
op <= "1111";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_112ed141f4 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_112ed141f4;
architecture behavior of mux_112ed141f4 is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0);
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0;
d1_1_27 <= d1;
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_3e1f051fb7 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_3e1f051fb7;
architecture behavior of logical_3e1f051fb7 is
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal fully_2_1_bit: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0;
d1_1_27 <= d1;
fully_2_1_bit <= d0_1_24 or d1_1_27;
y <= fully_2_1_bit;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_791081a00e is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((9 - 1) downto 0);
d1 : in std_logic_vector((9 - 1) downto 0);
y : out std_logic_vector((9 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_791081a00e;
architecture behavior of mux_791081a00e is
signal sel_1_20: std_logic;
signal d0_1_24: std_logic_vector((9 - 1) downto 0);
signal d1_1_27: std_logic_vector((9 - 1) downto 0);
signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((9 - 1) downto 0);
begin
sel_1_20 <= sel(0);
d0_1_24 <= d0;
d1_1_27 <= d1;
sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned);
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert)
is
begin
case sel_internal_2_1_convert is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/Buzzer Controller"
entity buzzer_controller_entity_063692c849 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(17 downto 0);
from_register1: in std_logic_vector(17 downto 0);
from_register2: in std_logic;
register9_x0: out std_logic
);
end buzzer_controller_entity_063692c849;
architecture structural of buzzer_controller_entity_063692c849 is
signal ce_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal convert_dout_net: std_logic;
signal counter_op_net: std_logic_vector(17 downto 0);
signal from_register1_data_out_net_x0: std_logic_vector(17 downto 0);
signal from_register2_data_out_net_x0: std_logic;
signal from_register_data_out_net_x0: std_logic_vector(17 downto 0);
signal inverter_op_net: std_logic;
signal mult_p_net: std_logic_vector(17 downto 0);
signal register8_q_net: std_logic;
signal register9_q_net_x0: std_logic;
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1_sg_x0 <= ce_1;
clk_1_sg_x0 <= clk_1;
from_register_data_out_net_x0 <= from_register;
from_register1_data_out_net_x0 <= from_register1;
from_register2_data_out_net_x0 <= from_register2;
register9_x0 <= register9_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => inverter_op_net,
dout(0) => convert_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_950e4ab582797264",
op_arith => xlUnsigned,
op_width => 18
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en => "1",
rst(0) => relational_op_net,
op => counter_op_net
);
inverter: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
ip(0) => from_register2_data_out_net_x0,
op(0) => inverter_op_net
);
mult: entity work.xlmult_v9_0
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 18,
b_arith => xlUnsigned,
b_bin_pt => 18,
b_width => 18,
c_a_type => 1,
c_a_width => 18,
c_b_type => 1,
c_b_width => 18,
c_baat => 18,
c_output_width => 36,
c_type => 1,
core_name0 => "multiplier_virtex2p_10_1_817edd563258bb47",
extra_registers => 0,
multsign => 1,
overflow => 1,
p_arith => xlUnsigned,
p_bin_pt => 0,
p_width => 18,
quantization => 1
)
port map (
a => from_register_data_out_net_x0,
b => from_register1_data_out_net_x0,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
core_ce => ce_1_sg_x0,
core_clk => clk_1_sg_x0,
core_clr => '1',
en => "1",
rst => "0",
p => mult_p_net
);
register8: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => relational1_op_net,
en => "1",
rst(0) => convert_dout_net,
q(0) => register8_q_net
);
register9: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => register8_q_net,
en => "1",
rst => "0",
q(0) => register9_q_net_x0
);
relational: entity work.relational_4e76b03051
port map (
a => counter_op_net,
b => from_register_data_out_net_x0,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_1433264a0c
port map (
a => counter_op_net,
b => mult_p_net,
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/EDK Processor"
entity edk_processor_entity_94deb4def9 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic_vector(1 downto 0);
from_register1: in std_logic_vector(5 downto 0);
from_register2: in std_logic_vector(3 downto 0);
from_register3: in std_logic_vector(4 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
sg_plb_addrpref: in std_logic_vector(14 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
shared_memory1: in std_logic_vector(31 downto 0);
shared_memory2: in std_logic_vector(31 downto 0);
splb_rst: in std_logic;
to_register: in std_logic_vector(17 downto 0);
to_register1: in std_logic;
to_register10: in std_logic_vector(8 downto 0);
to_register11: in std_logic_vector(3 downto 0);
to_register12: in std_logic_vector(8 downto 0);
to_register13: in std_logic;
to_register14: in std_logic;
to_register15: in std_logic_vector(8 downto 0);
to_register16: in std_logic_vector(8 downto 0);
to_register17: in std_logic_vector(8 downto 0);
to_register18: in std_logic;
to_register19: in std_logic_vector(7 downto 0);
to_register2: in std_logic_vector(17 downto 0);
to_register20: in std_logic_vector(7 downto 0);
to_register3: in std_logic_vector(8 downto 0);
to_register4: in std_logic_vector(3 downto 0);
to_register5: in std_logic_vector(2 downto 0);
to_register6: in std_logic_vector(8 downto 0);
to_register7: in std_logic_vector(1 downto 0);
to_register8: in std_logic;
to_register9: in std_logic_vector(8 downto 0);
constant5_x0: out std_logic;
plb_decode_x0: out std_logic;
plb_decode_x1: out std_logic;
plb_decode_x2: out std_logic;
plb_decode_x3: out std_logic;
plb_decode_x4: out std_logic_vector(31 downto 0);
plb_memmap_x0: out std_logic_vector(17 downto 0);
plb_memmap_x1: out std_logic;
plb_memmap_x10: out std_logic_vector(2 downto 0);
plb_memmap_x11: out std_logic;
plb_memmap_x12: out std_logic_vector(8 downto 0);
plb_memmap_x13: out std_logic;
plb_memmap_x14: out std_logic_vector(1 downto 0);
plb_memmap_x15: out std_logic;
plb_memmap_x16: out std_logic;
plb_memmap_x17: out std_logic;
plb_memmap_x18: out std_logic_vector(8 downto 0);
plb_memmap_x19: out std_logic;
plb_memmap_x2: out std_logic;
plb_memmap_x20: out std_logic_vector(8 downto 0);
plb_memmap_x21: out std_logic;
plb_memmap_x22: out std_logic_vector(3 downto 0);
plb_memmap_x23: out std_logic;
plb_memmap_x24: out std_logic_vector(8 downto 0);
plb_memmap_x25: out std_logic;
plb_memmap_x26: out std_logic;
plb_memmap_x27: out std_logic;
plb_memmap_x28: out std_logic;
plb_memmap_x29: out std_logic;
plb_memmap_x3: out std_logic;
plb_memmap_x30: out std_logic_vector(8 downto 0);
plb_memmap_x31: out std_logic;
plb_memmap_x32: out std_logic_vector(8 downto 0);
plb_memmap_x33: out std_logic;
plb_memmap_x34: out std_logic_vector(8 downto 0);
plb_memmap_x35: out std_logic;
plb_memmap_x36: out std_logic;
plb_memmap_x37: out std_logic;
plb_memmap_x38: out std_logic_vector(7 downto 0);
plb_memmap_x39: out std_logic;
plb_memmap_x4: out std_logic_vector(17 downto 0);
plb_memmap_x40: out std_logic_vector(7 downto 0);
plb_memmap_x41: out std_logic;
plb_memmap_x42: out std_logic_vector(11 downto 0);
plb_memmap_x43: out std_logic_vector(31 downto 0);
plb_memmap_x44: out std_logic;
plb_memmap_x45: out std_logic_vector(8 downto 0);
plb_memmap_x46: out std_logic_vector(31 downto 0);
plb_memmap_x47: out std_logic;
plb_memmap_x48: out std_logic_vector(7 downto 0);
plb_memmap_x49: out std_logic_vector(31 downto 0);
plb_memmap_x5: out std_logic;
plb_memmap_x50: out std_logic;
plb_memmap_x6: out std_logic_vector(8 downto 0);
plb_memmap_x7: out std_logic;
plb_memmap_x8: out std_logic_vector(3 downto 0);
plb_memmap_x9: out std_logic
);
end edk_processor_entity_94deb4def9;
architecture structural of edk_processor_entity_94deb4def9 is
signal bankaddr: std_logic_vector(1 downto 0);
signal buttons_big_dout_x0: std_logic_vector(1 downto 0);
signal buttons_small_dout_x0: std_logic_vector(5 downto 0);
signal buzzer_dutycycle_din_x0: std_logic_vector(17 downto 0);
signal buzzer_dutycycle_dout_x0: std_logic_vector(17 downto 0);
signal buzzer_dutycycle_en_x0: std_logic;
signal buzzer_enable_din_x0: std_logic;
signal buzzer_enable_dout_x0: std_logic;
signal buzzer_enable_en_x0: std_logic;
signal buzzer_period_din_x0: std_logic_vector(17 downto 0);
signal buzzer_period_dout_x0: std_logic_vector(17 downto 0);
signal buzzer_period_en_x0: std_logic;
signal ce_1_sg_x1: std_logic;
signal clk_1_sg_x1: std_logic;
signal dip_switch_dout_x0: std_logic_vector(3 downto 0);
signal lcd_backgroundcolor_din_x0: std_logic_vector(8 downto 0);
signal lcd_backgroundcolor_dout_x0: std_logic_vector(8 downto 0);
signal lcd_backgroundcolor_en_x0: std_logic;
signal lcd_charactermap_addr_x0: std_logic_vector(11 downto 0);
signal lcd_charactermap_din_x0: std_logic_vector(31 downto 0);
signal lcd_charactermap_dout_x0: std_logic_vector(31 downto 0);
signal lcd_charactermap_we_x0: std_logic;
signal lcd_characteroffset_din_x0: std_logic_vector(3 downto 0);
signal lcd_characteroffset_dout_x0: std_logic_vector(3 downto 0);
signal lcd_characteroffset_en_x0: std_logic;
signal lcd_characters_addr_x0: std_logic_vector(8 downto 0);
signal lcd_characters_din_x0: std_logic_vector(31 downto 0);
signal lcd_characters_dout_x0: std_logic_vector(31 downto 0);
signal lcd_characters_we_x0: std_logic;
signal lcd_charactersselect_din_x0: std_logic_vector(2 downto 0);
signal lcd_charactersselect_dout_x0: std_logic_vector(2 downto 0);
signal lcd_charactersselect_en_x0: std_logic;
signal lcd_colset_din_x0: std_logic_vector(8 downto 0);
signal lcd_colset_dout_x0: std_logic_vector(8 downto 0);
signal lcd_colset_en_x0: std_logic;
signal lcd_commands_addr_x0: std_logic_vector(7 downto 0);
signal lcd_commands_din_x0: std_logic_vector(31 downto 0);
signal lcd_commands_dout_x0: std_logic_vector(31 downto 0);
signal lcd_commands_we_x0: std_logic;
signal lcd_configlocation_din_x0: std_logic_vector(1 downto 0);
signal lcd_configlocation_dout_x0: std_logic_vector(1 downto 0);
signal lcd_configlocation_en_x0: std_logic;
signal lcd_dividerselect_din_x0: std_logic;
signal lcd_dividerselect_dout_x0: std_logic;
signal lcd_dividerselect_en_x0: std_logic;
signal lcd_firstend_din_x0: std_logic_vector(8 downto 0);
signal lcd_firstend_dout_x0: std_logic_vector(8 downto 0);
signal lcd_firstend_en_x0: std_logic;
signal lcd_firststart_din_x0: std_logic_vector(8 downto 0);
signal lcd_firststart_dout_x0: std_logic_vector(8 downto 0);
signal lcd_firststart_en_x0: std_logic;
signal lcd_lineoffset_din_x0: std_logic_vector(3 downto 0);
signal lcd_lineoffset_dout_x0: std_logic_vector(3 downto 0);
signal lcd_lineoffset_en_x0: std_logic;
signal lcd_ramwrite_din_x0: std_logic_vector(8 downto 0);
signal lcd_ramwrite_dout_x0: std_logic_vector(8 downto 0);
signal lcd_ramwrite_en_x0: std_logic;
signal lcd_reset_din_x0: std_logic;
signal lcd_reset_dout_x0: std_logic;
signal lcd_reset_en_x0: std_logic;
signal lcd_resetlcd_din_x0: std_logic;
signal lcd_resetlcd_dout_x0: std_logic;
signal lcd_resetlcd_en_x0: std_logic;
signal lcd_rowset_din_x0: std_logic_vector(8 downto 0);
signal lcd_rowset_dout_x0: std_logic_vector(8 downto 0);
signal lcd_rowset_en_x0: std_logic;
signal lcd_secondend_din_x0: std_logic_vector(8 downto 0);
signal lcd_secondend_dout_x0: std_logic_vector(8 downto 0);
signal lcd_secondend_en_x0: std_logic;
signal lcd_secondstart_din_x0: std_logic_vector(8 downto 0);
signal lcd_secondstart_dout_x0: std_logic_vector(8 downto 0);
signal lcd_secondstart_en_x0: std_logic;
signal lcd_send_din_x0: std_logic;
signal lcd_send_dout_x0: std_logic;
signal lcd_send_en_x0: std_logic;
signal lcd_totalcmdtransfer_din_x0: std_logic_vector(7 downto 0);
signal lcd_totalcmdtransfer_dout_x0: std_logic_vector(7 downto 0);
signal lcd_totalcmdtransfer_en_x0: std_logic;
signal leds_din_x0: std_logic_vector(7 downto 0);
signal leds_dout_x0: std_logic_vector(7 downto 0);
signal leds_en_x0: std_logic;
signal linearaddr: std_logic_vector(12 downto 0);
signal plb_abus_net_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_net_x0: std_logic;
signal plb_rnw_net_x0: std_logic;
signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0);
signal rddata: std_logic_vector(31 downto 0);
signal rnwreg: std_logic;
signal sg_plb_addrpref_net_x0: std_logic_vector(14 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_rddbus_x0: std_logic_vector(31 downto 0);
signal sl_wait_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_net_x0: std_logic;
signal trackball_dout_x0: std_logic_vector(4 downto 0);
signal wrdbusreg: std_logic_vector(31 downto 0);
begin
ce_1_sg_x1 <= ce_1;
clk_1_sg_x1 <= clk_1;
buttons_big_dout_x0 <= from_register;
buttons_small_dout_x0 <= from_register1;
dip_switch_dout_x0 <= from_register2;
trackball_dout_x0 <= from_register3;
plb_abus_net_x0 <= plb_abus;
plb_pavalid_net_x0 <= plb_pavalid;
plb_rnw_net_x0 <= plb_rnw;
plb_wrdbus_net_x0 <= plb_wrdbus;
sg_plb_addrpref_net_x0 <= sg_plb_addrpref;
lcd_charactermap_dout_x0 <= shared_memory;
lcd_characters_dout_x0 <= shared_memory1;
lcd_commands_dout_x0 <= shared_memory2;
splb_rst_net_x0 <= splb_rst;
buzzer_dutycycle_dout_x0 <= to_register;
buzzer_enable_dout_x0 <= to_register1;
lcd_firststart_dout_x0 <= to_register10;
lcd_lineoffset_dout_x0 <= to_register11;
lcd_ramwrite_dout_x0 <= to_register12;
lcd_reset_dout_x0 <= to_register13;
lcd_resetlcd_dout_x0 <= to_register14;
lcd_rowset_dout_x0 <= to_register15;
lcd_secondend_dout_x0 <= to_register16;
lcd_secondstart_dout_x0 <= to_register17;
lcd_send_dout_x0 <= to_register18;
lcd_totalcmdtransfer_dout_x0 <= to_register19;
buzzer_period_dout_x0 <= to_register2;
leds_dout_x0 <= to_register20;
lcd_backgroundcolor_dout_x0 <= to_register3;
lcd_characteroffset_dout_x0 <= to_register4;
lcd_charactersselect_dout_x0 <= to_register5;
lcd_colset_dout_x0 <= to_register6;
lcd_configlocation_dout_x0 <= to_register7;
lcd_dividerselect_dout_x0 <= to_register8;
lcd_firstend_dout_x0 <= to_register9;
constant5_x0 <= sl_wait_x0;
plb_decode_x0 <= sl_addrack_x0;
plb_decode_x1 <= sl_rdcomp_x0;
plb_decode_x2 <= sl_wrdack_x0;
plb_decode_x3 <= sl_rddack_x0;
plb_decode_x4 <= sl_rddbus_x0;
plb_memmap_x0 <= buzzer_dutycycle_din_x0;
plb_memmap_x1 <= buzzer_dutycycle_en_x0;
plb_memmap_x10 <= lcd_charactersselect_din_x0;
plb_memmap_x11 <= lcd_charactersselect_en_x0;
plb_memmap_x12 <= lcd_colset_din_x0;
plb_memmap_x13 <= lcd_colset_en_x0;
plb_memmap_x14 <= lcd_configlocation_din_x0;
plb_memmap_x15 <= lcd_configlocation_en_x0;
plb_memmap_x16 <= lcd_dividerselect_din_x0;
plb_memmap_x17 <= lcd_dividerselect_en_x0;
plb_memmap_x18 <= lcd_firstend_din_x0;
plb_memmap_x19 <= lcd_firstend_en_x0;
plb_memmap_x2 <= buzzer_enable_din_x0;
plb_memmap_x20 <= lcd_firststart_din_x0;
plb_memmap_x21 <= lcd_firststart_en_x0;
plb_memmap_x22 <= lcd_lineoffset_din_x0;
plb_memmap_x23 <= lcd_lineoffset_en_x0;
plb_memmap_x24 <= lcd_ramwrite_din_x0;
plb_memmap_x25 <= lcd_ramwrite_en_x0;
plb_memmap_x26 <= lcd_reset_din_x0;
plb_memmap_x27 <= lcd_reset_en_x0;
plb_memmap_x28 <= lcd_resetlcd_din_x0;
plb_memmap_x29 <= lcd_resetlcd_en_x0;
plb_memmap_x3 <= buzzer_enable_en_x0;
plb_memmap_x30 <= lcd_rowset_din_x0;
plb_memmap_x31 <= lcd_rowset_en_x0;
plb_memmap_x32 <= lcd_secondend_din_x0;
plb_memmap_x33 <= lcd_secondend_en_x0;
plb_memmap_x34 <= lcd_secondstart_din_x0;
plb_memmap_x35 <= lcd_secondstart_en_x0;
plb_memmap_x36 <= lcd_send_din_x0;
plb_memmap_x37 <= lcd_send_en_x0;
plb_memmap_x38 <= lcd_totalcmdtransfer_din_x0;
plb_memmap_x39 <= lcd_totalcmdtransfer_en_x0;
plb_memmap_x4 <= buzzer_period_din_x0;
plb_memmap_x40 <= leds_din_x0;
plb_memmap_x41 <= leds_en_x0;
plb_memmap_x42 <= lcd_charactermap_addr_x0;
plb_memmap_x43 <= lcd_charactermap_din_x0;
plb_memmap_x44 <= lcd_charactermap_we_x0;
plb_memmap_x45 <= lcd_characters_addr_x0;
plb_memmap_x46 <= lcd_characters_din_x0;
plb_memmap_x47 <= lcd_characters_we_x0;
plb_memmap_x48 <= lcd_commands_addr_x0;
plb_memmap_x49 <= lcd_commands_din_x0;
plb_memmap_x5 <= buzzer_period_en_x0;
plb_memmap_x50 <= lcd_commands_we_x0;
plb_memmap_x6 <= lcd_backgroundcolor_din_x0;
plb_memmap_x7 <= lcd_backgroundcolor_en_x0;
plb_memmap_x8 <= lcd_characteroffset_din_x0;
plb_memmap_x9 <= lcd_characteroffset_en_x0;
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => sl_wait_x0
);
plb_decode: entity work.mcode_block_8231ed31e4
port map (
addrpref => sg_plb_addrpref_net_x0,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
plbabus => plb_abus_net_x0,
plbpavalid(0) => plb_pavalid_net_x0,
plbrnw(0) => plb_rnw_net_x0,
plbrst(0) => splb_rst_net_x0,
plbwrdbus => plb_wrdbus_net_x0,
rddata => rddata,
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
linearaddr => linearaddr,
rdcomp(0) => sl_rdcomp_x0,
rddack(0) => sl_rddack_x0,
rddbus => sl_rddbus_x0,
rnwreg(0) => rnwreg,
wrdack(0) => sl_wrdack_x0,
wrdbusreg => wrdbusreg
);
plb_memmap: entity work.mcode_block_66f25059c9
port map (
addrack(0) => sl_addrack_x0,
bankaddr => bankaddr,
ce => ce_1_sg_x1,
clk => clk_1_sg_x1,
clr => '0',
linearaddr => linearaddr,
rnwreg(0) => rnwreg,
sm_buttons_big => buttons_big_dout_x0,
sm_buttons_small => buttons_small_dout_x0,
sm_buzzer_dutycycle => buzzer_dutycycle_dout_x0,
sm_buzzer_enable(0) => buzzer_enable_dout_x0,
sm_buzzer_period => buzzer_period_dout_x0,
sm_dip_switch => dip_switch_dout_x0,
sm_lcd_backgroundcolor => lcd_backgroundcolor_dout_x0,
sm_lcd_charactermap => lcd_charactermap_dout_x0,
sm_lcd_characteroffset => lcd_characteroffset_dout_x0,
sm_lcd_characters => lcd_characters_dout_x0,
sm_lcd_charactersselect => lcd_charactersselect_dout_x0,
sm_lcd_colset => lcd_colset_dout_x0,
sm_lcd_commands => lcd_commands_dout_x0,
sm_lcd_configlocation => lcd_configlocation_dout_x0,
sm_lcd_dividerselect(0) => lcd_dividerselect_dout_x0,
sm_lcd_firstend => lcd_firstend_dout_x0,
sm_lcd_firststart => lcd_firststart_dout_x0,
sm_lcd_lineoffset => lcd_lineoffset_dout_x0,
sm_lcd_ramwrite => lcd_ramwrite_dout_x0,
sm_lcd_reset(0) => lcd_reset_dout_x0,
sm_lcd_resetlcd(0) => lcd_resetlcd_dout_x0,
sm_lcd_rowset => lcd_rowset_dout_x0,
sm_lcd_secondend => lcd_secondend_dout_x0,
sm_lcd_secondstart => lcd_secondstart_dout_x0,
sm_lcd_send(0) => lcd_send_dout_x0,
sm_lcd_totalcmdtransfer => lcd_totalcmdtransfer_dout_x0,
sm_leds => leds_dout_x0,
sm_trackball => trackball_dout_x0,
wrdbus => wrdbusreg,
read_bank_out => rddata,
sm_buzzer_dutycycle_din => buzzer_dutycycle_din_x0,
sm_buzzer_dutycycle_en(0) => buzzer_dutycycle_en_x0,
sm_buzzer_enable_din(0) => buzzer_enable_din_x0,
sm_buzzer_enable_en(0) => buzzer_enable_en_x0,
sm_buzzer_period_din => buzzer_period_din_x0,
sm_buzzer_period_en(0) => buzzer_period_en_x0,
sm_lcd_backgroundcolor_din => lcd_backgroundcolor_din_x0,
sm_lcd_backgroundcolor_en(0) => lcd_backgroundcolor_en_x0,
sm_lcd_charactermap_addr => lcd_charactermap_addr_x0,
sm_lcd_charactermap_din => lcd_charactermap_din_x0,
sm_lcd_charactermap_we(0) => lcd_charactermap_we_x0,
sm_lcd_characteroffset_din => lcd_characteroffset_din_x0,
sm_lcd_characteroffset_en(0) => lcd_characteroffset_en_x0,
sm_lcd_characters_addr => lcd_characters_addr_x0,
sm_lcd_characters_din => lcd_characters_din_x0,
sm_lcd_characters_we(0) => lcd_characters_we_x0,
sm_lcd_charactersselect_din => lcd_charactersselect_din_x0,
sm_lcd_charactersselect_en(0) => lcd_charactersselect_en_x0,
sm_lcd_colset_din => lcd_colset_din_x0,
sm_lcd_colset_en(0) => lcd_colset_en_x0,
sm_lcd_commands_addr => lcd_commands_addr_x0,
sm_lcd_commands_din => lcd_commands_din_x0,
sm_lcd_commands_we(0) => lcd_commands_we_x0,
sm_lcd_configlocation_din => lcd_configlocation_din_x0,
sm_lcd_configlocation_en(0) => lcd_configlocation_en_x0,
sm_lcd_dividerselect_din(0) => lcd_dividerselect_din_x0,
sm_lcd_dividerselect_en(0) => lcd_dividerselect_en_x0,
sm_lcd_firstend_din => lcd_firstend_din_x0,
sm_lcd_firstend_en(0) => lcd_firstend_en_x0,
sm_lcd_firststart_din => lcd_firststart_din_x0,
sm_lcd_firststart_en(0) => lcd_firststart_en_x0,
sm_lcd_lineoffset_din => lcd_lineoffset_din_x0,
sm_lcd_lineoffset_en(0) => lcd_lineoffset_en_x0,
sm_lcd_ramwrite_din => lcd_ramwrite_din_x0,
sm_lcd_ramwrite_en(0) => lcd_ramwrite_en_x0,
sm_lcd_reset_din(0) => lcd_reset_din_x0,
sm_lcd_reset_en(0) => lcd_reset_en_x0,
sm_lcd_resetlcd_din(0) => lcd_resetlcd_din_x0,
sm_lcd_resetlcd_en(0) => lcd_resetlcd_en_x0,
sm_lcd_rowset_din => lcd_rowset_din_x0,
sm_lcd_rowset_en(0) => lcd_rowset_en_x0,
sm_lcd_secondend_din => lcd_secondend_din_x0,
sm_lcd_secondend_en(0) => lcd_secondend_en_x0,
sm_lcd_secondstart_din => lcd_secondstart_din_x0,
sm_lcd_secondstart_en(0) => lcd_secondstart_en_x0,
sm_lcd_send_din(0) => lcd_send_din_x0,
sm_lcd_send_en(0) => lcd_send_en_x0,
sm_lcd_totalcmdtransfer_din => lcd_totalcmdtransfer_din_x0,
sm_lcd_totalcmdtransfer_en(0) => lcd_totalcmdtransfer_en_x0,
sm_leds_din => leds_din_x0,
sm_leds_en(0) => leds_en_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/Interactive I/O/8xDebounce"
entity x8xdebounce_entity_bf5cd80880 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
d: in std_logic;
q: out std_logic
);
end x8xdebounce_entity_bf5cd80880;
architecture structural of x8xdebounce_entity_bf5cd80880 is
signal ce_1_sg_x2: std_logic;
signal clk_1_sg_x2: std_logic;
signal delay1_q_net: std_logic;
signal delay2_q_net: std_logic;
signal delay3_q_net: std_logic;
signal delay4_q_net: std_logic;
signal delay5_q_net: std_logic;
signal delay6_q_net: std_logic;
signal delay_q_net: std_logic;
signal logical_y_net_x0: std_logic;
signal trackball_sel2_net_x0: std_logic;
begin
ce_1_sg_x2 <= ce_1;
clk_1_sg_x2 <= clk_1;
trackball_sel2_net_x0 <= d;
q <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => trackball_sel2_net_x0,
en => '1',
q(0) => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay_q_net,
en => '1',
q(0) => delay1_q_net
);
delay2: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay1_q_net,
en => '1',
q(0) => delay2_q_net
);
delay3: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay2_q_net,
en => '1',
q(0) => delay3_q_net
);
delay4: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay3_q_net,
en => '1',
q(0) => delay4_q_net
);
delay5: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay4_q_net,
en => '1',
q(0) => delay5_q_net
);
delay6: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x2,
clk => clk_1_sg_x2,
d(0) => delay5_q_net,
en => '1',
q(0) => delay6_q_net
);
logical: entity work.logical_4ad38e8aed
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => trackball_sel2_net_x0,
d1(0) => delay_q_net,
d2(0) => delay1_q_net,
d3(0) => delay2_q_net,
d4(0) => delay3_q_net,
d5(0) => delay4_q_net,
d6(0) => delay5_q_net,
d7(0) => delay6_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/Interactive I/O"
entity o_entity_1f30dfdbf5 is
port (
buttons_big: in std_logic_vector(1 downto 0);
buttons_small: in std_logic_vector(5 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
dip_switch: in std_logic_vector(3 downto 0);
from_register: in std_logic_vector(7 downto 0);
trackball_ox: in std_logic;
trackball_oxn: in std_logic;
trackball_oy: in std_logic;
trackball_oyn: in std_logic;
trackball_sel2: in std_logic;
concat_x0: out std_logic_vector(4 downto 0);
constant2_x0: out std_logic;
constant4_x0: out std_logic;
constant6_x0: out std_logic;
constant_x1: out std_logic;
register10_x0: out std_logic;
register11_x0: out std_logic;
register12_x0: out std_logic;
register3_x0: out std_logic_vector(1 downto 0);
register5_x0: out std_logic_vector(5 downto 0);
register7_x0: out std_logic_vector(3 downto 0);
register9_x0: out std_logic_vector(7 downto 0)
);
end o_entity_1f30dfdbf5;
architecture structural of o_entity_1f30dfdbf5 is
signal buttons_big_net_x0: std_logic_vector(1 downto 0);
signal buttons_small_net_x0: std_logic_vector(5 downto 0);
signal ce_1_sg_x7: std_logic;
signal clk_1_sg_x7: std_logic;
signal concat_y_net_x0: std_logic_vector(4 downto 0);
signal constant13_op_net: std_logic;
signal constant2_op_net_x0: std_logic;
signal constant4_op_net_x0: std_logic;
signal constant6_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic;
signal dip_switch_net_x0: std_logic_vector(3 downto 0);
signal from_register_data_out_net_x0: std_logic_vector(7 downto 0);
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal logical_y_net_x2: std_logic;
signal logical_y_net_x3: std_logic;
signal logical_y_net_x4: std_logic;
signal register10_q_net_x0: std_logic;
signal register11_q_net_x0: std_logic;
signal register12_q_net_x0: std_logic;
signal register13_q_net: std_logic;
signal register14_q_net: std_logic;
signal register15_q_net: std_logic;
signal register16_q_net: std_logic;
signal register17_q_net: std_logic;
signal register18_q_net: std_logic;
signal register19_q_net: std_logic;
signal register1_q_net: std_logic;
signal register20_q_net: std_logic;
signal register2_q_net: std_logic_vector(1 downto 0);
signal register3_q_net_x0: std_logic_vector(1 downto 0);
signal register4_q_net: std_logic_vector(5 downto 0);
signal register5_q_net_x0: std_logic_vector(5 downto 0);
signal register6_q_net: std_logic_vector(3 downto 0);
signal register7_q_net_x0: std_logic_vector(3 downto 0);
signal register8_q_net: std_logic_vector(7 downto 0);
signal register9_q_net_x0: std_logic_vector(7 downto 0);
signal register_q_net: std_logic;
signal trackball_ox_net_x1: std_logic;
signal trackball_oxn_net_x1: std_logic;
signal trackball_oy_net_x1: std_logic;
signal trackball_oyn_net_x1: std_logic;
signal trackball_sel2_net_x1: std_logic;
begin
buttons_big_net_x0 <= buttons_big;
buttons_small_net_x0 <= buttons_small;
ce_1_sg_x7 <= ce_1;
clk_1_sg_x7 <= clk_1;
dip_switch_net_x0 <= dip_switch;
from_register_data_out_net_x0 <= from_register;
trackball_ox_net_x1 <= trackball_ox;
trackball_oxn_net_x1 <= trackball_oxn;
trackball_oy_net_x1 <= trackball_oy;
trackball_oyn_net_x1 <= trackball_oyn;
trackball_sel2_net_x1 <= trackball_sel2;
concat_x0 <= concat_y_net_x0;
constant2_x0 <= constant2_op_net_x0;
constant4_x0 <= constant4_op_net_x0;
constant6_x0 <= constant6_op_net_x0;
constant_x1 <= constant_op_net_x0;
register10_x0 <= register10_q_net_x0;
register11_x0 <= register11_q_net_x0;
register12_x0 <= register12_q_net_x0;
register3_x0 <= register3_q_net_x0;
register5_x0 <= register5_q_net_x0;
register7_x0 <= register7_q_net_x0;
register9_x0 <= register9_q_net_x0;
concat: entity work.concat_2b3acb49f4
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => register20_q_net,
in1(0) => register1_q_net,
in2(0) => register14_q_net,
in3(0) => register16_q_net,
in4(0) => register18_q_net,
y => concat_y_net_x0
);
constant13: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant13_op_net
);
constant2: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant2_op_net_x0
);
constant4: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant4_op_net_x0
);
constant6: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant6_op_net_x0
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register_q_net,
en => "1",
rst => "0",
q(0) => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => constant13_op_net,
en => "1",
rst => "0",
q(0) => register10_q_net_x0
);
register11: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => constant13_op_net,
en => "1",
rst => "0",
q(0) => register11_q_net_x0
);
register12: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => constant13_op_net,
en => "1",
rst => "0",
q(0) => register12_q_net_x0
);
register13: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x2,
en => "1",
rst => "0",
q(0) => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register13_q_net,
en => "1",
rst => "0",
q(0) => register14_q_net
);
register15: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x3,
en => "1",
rst => "0",
q(0) => register15_q_net
);
register16: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register15_q_net,
en => "1",
rst => "0",
q(0) => register16_q_net
);
register17: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x4,
en => "1",
rst => "0",
q(0) => register17_q_net
);
register18: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register17_q_net,
en => "1",
rst => "0",
q(0) => register18_q_net
);
register19: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x0,
en => "1",
rst => "0",
q(0) => register19_q_net
);
register2: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => buttons_big_net_x0,
en => "1",
rst => "0",
q => register2_q_net
);
register20: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => register19_q_net,
en => "1",
rst => "0",
q(0) => register20_q_net
);
register3: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register2_q_net,
en => "1",
rst => "0",
q => register3_q_net_x0
);
register4: entity work.xlregister
generic map (
d_width => 6,
init_value => b"000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => buttons_small_net_x0,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 6,
init_value => b"000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register4_q_net,
en => "1",
rst => "0",
q => register5_q_net_x0
);
register6: entity work.xlregister
generic map (
d_width => 4,
init_value => b"0000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => dip_switch_net_x0,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 4,
init_value => b"0000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register6_q_net,
en => "1",
rst => "0",
q => register7_q_net_x0
);
register8: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => from_register_data_out_net_x0,
en => "1",
rst => "0",
q => register8_q_net
);
register9: entity work.xlregister
generic map (
d_width => 8,
init_value => b"00000000"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d => register8_q_net,
en => "1",
rst => "0",
q => register9_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x7,
clk => clk_1_sg_x7,
d(0) => logical_y_net_x1,
en => "1",
rst => "0",
q(0) => register_q_net
);
x8xdebounce1_e364c4890f: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_ox_net_x1,
q => logical_y_net_x1
);
x8xdebounce2_5537837997: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_oxn_net_x1,
q => logical_y_net_x2
);
x8xdebounce3_1e40372202: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_oy_net_x1,
q => logical_y_net_x3
);
x8xdebounce4_7911ba4284: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_oyn_net_x1,
q => logical_y_net_x4
);
x8xdebounce_bf5cd80880: entity work.x8xdebounce_entity_bf5cd80880
port map (
ce_1 => ce_1_sg_x7,
clk_1 => clk_1_sg_x7,
d => trackball_sel2_net_x1,
q => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/CommandROM/Command Memory"
entity command_memory_entity_ca978db4f0 is
port (
addr_9b: in std_logic_vector(8 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
constant1_x0: out std_logic;
constant_x1: out std_logic_vector(31 downto 0);
data_16b: out std_logic_vector(15 downto 0);
x8msb_x0: out std_logic_vector(7 downto 0)
);
end command_memory_entity_ca978db4f0;
architecture structural of command_memory_entity_ca978db4f0 is
signal concat_y_net_x0: std_logic_vector(8 downto 0);
signal constant1_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic_vector(31 downto 0);
signal lsb_y_net: std_logic;
signal mux_y_net_x0: std_logic_vector(15 downto 0);
signal shared_memory_data_out_net_x0: std_logic_vector(31 downto 0);
signal x16lsb_y_net: std_logic_vector(15 downto 0);
signal x16msb_y_net: std_logic_vector(15 downto 0);
signal x8msb_y_net_x0: std_logic_vector(7 downto 0);
begin
concat_y_net_x0 <= addr_9b;
shared_memory_data_out_net_x0 <= shared_memory;
constant1_x0 <= constant1_op_net_x0;
constant_x1 <= constant_op_net_x0;
data_16b <= mux_y_net_x0;
x8msb_x0 <= x8msb_y_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x0
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net_x0
);
lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 9,
y_width => 1
)
port map (
x => concat_y_net_x0,
y(0) => lsb_y_net
);
mux: entity work.mux_2c45f290ed
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => x16lsb_y_net,
d1 => x16msb_y_net,
sel(0) => lsb_y_net,
y => mux_y_net_x0
);
x16lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 15,
x_width => 32,
y_width => 16
)
port map (
x => shared_memory_data_out_net_x0,
y => x16lsb_y_net
);
x16msb: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 31,
x_width => 32,
y_width => 16
)
port map (
x => shared_memory_data_out_net_x0,
y => x16msb_y_net
);
x8msb: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 8,
x_width => 9,
y_width => 8
)
port map (
x => concat_y_net_x0,
y => x8msb_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/CommandROM/Neg Edge Detector"
entity neg_edge_detector_entity_b797592ea5 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
input_signal: in std_logic;
rising_edge: out std_logic
);
end neg_edge_detector_entity_b797592ea5;
architecture structural of neg_edge_detector_entity_b797592ea5 is
signal ce_1_sg_x8: std_logic;
signal clk_1_sg_x8: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal slice4_y_net_x0: std_logic;
begin
ce_1_sg_x8 <= ce_1;
clk_1_sg_x8 <= clk_1;
slice4_y_net_x0 <= input_signal;
rising_edge <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x8,
clk => clk_1_sg_x8,
d(0) => inverter_op_net,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x8,
clk => clk_1_sg_x8,
clr => '0',
ip(0) => slice4_y_net_x0,
op(0) => inverter_op_net
);
logical: entity work.logical_b1e9d7c303
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => slice4_y_net_x0,
d1(0) => delay_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/CommandROM"
entity commandrom_entity_b68e0d97b7 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register1: in std_logic_vector(8 downto 0);
from_register2: in std_logic_vector(8 downto 0);
from_register3: in std_logic_vector(8 downto 0);
from_register4: in std_logic_vector(8 downto 0);
from_register5: in std_logic_vector(8 downto 0);
from_register6: in std_logic_vector(1 downto 0);
reset: in std_logic;
sendcmds: in std_logic;
shared_memory: in std_logic_vector(31 downto 0);
totalnoofcmds: in std_logic_vector(7 downto 0);
transferdone: in std_logic;
cmdsdone: out std_logic;
command_memory: out std_logic_vector(7 downto 0);
command_memory_x0: out std_logic_vector(31 downto 0);
command_memory_x1: out std_logic;
datatosend: out std_logic_vector(8 downto 0);
starttransfer: out std_logic
);
end commandrom_entity_b68e0d97b7;
architecture structural of commandrom_entity_b68e0d97b7 is
signal accumulator1_q_net: std_logic_vector(3 downto 0);
signal accumulator_q_net: std_logic_vector(6 downto 0);
signal addsub_s_net: std_logic_vector(8 downto 0);
signal ce_1_sg_x9: std_logic;
signal clk_1_sg_x9: std_logic;
signal concat2_y_net_x0: std_logic_vector(8 downto 0);
signal concat_y_net_x0: std_logic_vector(8 downto 0);
signal constant11_op_net: std_logic_vector(8 downto 0);
signal constant1_op_net_x1: std_logic;
signal constant2_op_net: std_logic;
signal constant3_op_net: std_logic;
signal constant4_op_net: std_logic_vector(3 downto 0);
signal constant5_op_net: std_logic_vector(8 downto 0);
signal constant6_op_net: std_logic_vector(8 downto 0);
signal constant_op_net_x1: std_logic_vector(31 downto 0);
signal convert1_dout_net: std_logic;
signal convert1_dout_net_x2: std_logic;
signal convert1_dout_net_x3: std_logic;
signal convert2_dout_net: std_logic;
signal convert_dout_net: std_logic;
signal counter1_op_net: std_logic_vector(14 downto 0);
signal counter_op_net: std_logic_vector(6 downto 0);
signal delay_q_net: std_logic;
signal from_register1_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x1: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x2: std_logic_vector(7 downto 0);
signal from_register4_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register5_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register6_data_out_net_x0: std_logic_vector(1 downto 0);
signal inverter1_op_net: std_logic;
signal inverter2_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net: std_logic;
signal logical_y_net: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x2: std_logic;
signal mux1_y_net: std_logic;
signal mux2_y_net_x0: std_logic;
signal mux3_y_net: std_logic_vector(8 downto 0);
signal mux_y_net_x0: std_logic_vector(15 downto 0);
signal register_q_net_x0: std_logic;
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
signal shared_memory_data_out_net_x1: std_logic_vector(31 downto 0);
signal slice2_y_net: std_logic_vector(7 downto 0);
signal slice3_y_net: std_logic;
signal slice4_y_net_x0: std_logic;
signal slice5_y_net: std_logic_vector(8 downto 0);
signal x8msb_y_net_x1: std_logic_vector(7 downto 0);
begin
ce_1_sg_x9 <= ce_1;
clk_1_sg_x9 <= clk_1;
from_register1_data_out_net_x0 <= from_register1;
from_register2_data_out_net_x0 <= from_register2;
from_register3_data_out_net_x1 <= from_register3;
from_register4_data_out_net_x0 <= from_register4;
from_register5_data_out_net_x0 <= from_register5;
from_register6_data_out_net_x0 <= from_register6;
convert1_dout_net_x2 <= reset;
logical_y_net_x2 <= sendcmds;
shared_memory_data_out_net_x1 <= shared_memory;
from_register3_data_out_net_x2 <= totalnoofcmds;
convert1_dout_net_x3 <= transferdone;
cmdsdone <= register_q_net_x0;
command_memory <= x8msb_y_net_x1;
command_memory_x0 <= constant_op_net_x1;
command_memory_x1 <= constant1_op_net_x1;
datatosend <= concat2_y_net_x0;
starttransfer <= mux2_y_net_x0;
accumulator: entity work.accum_2cb0e56e96
port map (
b(0) => convert_dout_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en(0) => logical1_y_net,
rst(0) => logical_y_net_x2,
q => accumulator_q_net
);
accumulator1: entity work.accum_be45dd0aa2
port map (
b(0) => convert1_dout_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
rst(0) => convert1_dout_net_x2,
q => accumulator1_q_net
);
addsub: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 8,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 1,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 9,
core_name0 => "adder_subtracter_virtex2p_7_0_cf28bbebd75d9ce3",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 9,
latency => 0,
mode => 2,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 0,
s_width => 9
)
port map (
a => from_register3_data_out_net_x2,
b(0) => constant3_op_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en => "1",
s => addsub_s_net
);
command_memory_ca978db4f0: entity work.command_memory_entity_ca978db4f0
port map (
addr_9b => concat_y_net_x0,
shared_memory => shared_memory_data_out_net_x1,
constant1_x0 => constant1_op_net_x1,
constant_x1 => constant_op_net_x1,
data_16b => mux_y_net_x0,
x8msb_x0 => x8msb_y_net_x1
);
concat: entity work.concat_f62149b02a
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => from_register6_data_out_net_x0,
in1 => counter_op_net,
y => concat_y_net_x0
);
concat2: entity work.concat_1ece14600f
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => inverter1_op_net,
in1 => slice2_y_net,
y => concat2_y_net_x0
);
constant11: entity work.constant_443ed96427
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant11_op_net
);
constant2: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant2_op_net
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net
);
constant4: entity work.constant_145086465d
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant5: entity work.constant_fb9f6d3796
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant5_op_net
);
constant6: entity work.constant_09a4afb2ee
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant6_op_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => delay_q_net,
dout(0) => convert_dout_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => logical3_y_net,
dout(0) => convert1_dout_net
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 5,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
din(0) => logical_y_net_x0,
dout(0) => convert2_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_b0a257f5389d649a",
op_arith => xlUnsigned,
op_width => 7
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en(0) => logical_y_net,
rst(0) => convert1_dout_net_x2,
op => counter_op_net
);
counter1: entity work.xlcounter_limit
generic map (
cnt_15_0 => 17435,
cnt_31_16 => 0,
cnt_47_32 => 0,
cnt_63_48 => 0,
core_name0 => "binary_counter_virtex2p_7_0_32a1863440903b9d",
count_limited => 1,
op_arith => xlUnsigned,
op_width => 15
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
en(0) => logical2_y_net,
rst(0) => convert1_dout_net_x2,
op => counter1_op_net
);
delay: entity work.xldelay
generic map (
latency => 4,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => logical_y_net,
en => '1',
q(0) => delay_q_net
);
inverter1: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
ip(0) => slice3_y_net,
op(0) => inverter1_op_net
);
inverter2: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
ip(0) => relational_op_net,
op(0) => inverter2_op_net
);
logical: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => logical_y_net_x2,
d1(0) => convert1_dout_net_x3,
y(0) => logical_y_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => delay_q_net,
d1(0) => relational_op_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => inverter2_op_net,
d1(0) => convert1_dout_net_x3,
y(0) => logical2_y_net
);
logical3: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational1_op_net,
d1(0) => logical2_y_net,
y(0) => logical3_y_net
);
mux1: entity work.mux_d99e59b6d4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => constant2_op_net,
d1(0) => delay_q_net,
sel(0) => relational_op_net,
y(0) => mux1_y_net
);
mux2: entity work.mux_d99e59b6d4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => mux1_y_net,
d1(0) => delay_q_net,
sel(0) => inverter2_op_net,
y(0) => mux2_y_net_x0
);
mux3: entity work.mux_1f00a411aa
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => slice5_y_net,
d1 => constant5_op_net,
d2 => from_register1_data_out_net_x0,
d3 => from_register2_data_out_net_x0,
d4 => constant6_op_net,
d5 => from_register4_data_out_net_x0,
d6 => from_register5_data_out_net_x0,
d7 => constant11_op_net,
d8 => from_register3_data_out_net_x1,
sel => accumulator1_q_net,
y => mux3_y_net
);
neg_edge_detector_b797592ea5: entity work.neg_edge_detector_entity_b797592ea5
port map (
ce_1 => ce_1_sg_x9,
clk_1 => clk_1_sg_x9,
input_signal => slice4_y_net_x0,
rising_edge => logical_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => convert2_dout_net,
en(0) => convert2_dout_net,
rst(0) => convert1_dout_net_x2,
q(0) => register_q_net_x0
);
relational: entity work.relational_92c392c8b6
port map (
a => accumulator_q_net,
b => addsub_s_net,
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_fb96203f91
port map (
a => accumulator1_q_net,
b => constant4_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational1_op_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 9,
y_width => 8
)
port map (
x => mux3_y_net,
y => slice2_y_net
);
slice3: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 9,
y_width => 1
)
port map (
x => mux3_y_net,
y(0) => slice3_y_net
);
slice4: entity work.xlslice
generic map (
new_lsb => 14,
new_msb => 14,
x_width => 15,
y_width => 1
)
port map (
x => counter1_op_net,
y(0) => slice4_y_net_x0
);
slice5: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 8,
x_width => 16,
y_width => 9
)
port map (
x => mux_y_net_x0,
y => slice5_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Character Buffer Shared Memory"
entity character_buffer_shared_memory_entity_1eeb1f8786 is
port (
addr_11b: in std_logic_vector(10 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
constant1_x0: out std_logic;
constant_x1: out std_logic_vector(31 downto 0);
data_8b: out std_logic_vector(7 downto 0);
x9msb_x0: out std_logic_vector(8 downto 0)
);
end character_buffer_shared_memory_entity_1eeb1f8786;
architecture structural of character_buffer_shared_memory_entity_1eeb1f8786 is
signal concat1_y_net_x0: std_logic_vector(10 downto 0);
signal constant1_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic_vector(31 downto 0);
signal mux_y_net_x0: std_logic_vector(7 downto 0);
signal shared_memory_data_out_net_x0: std_logic_vector(31 downto 0);
signal x2lsb_y_net: std_logic_vector(1 downto 0);
signal x8lsb_0_y_net: std_logic_vector(7 downto 0);
signal x8lsb_16_y_net: std_logic_vector(7 downto 0);
signal x8lsb_24_y_net: std_logic_vector(7 downto 0);
signal x8lsb_8_y_net: std_logic_vector(7 downto 0);
signal x9msb_y_net_x0: std_logic_vector(8 downto 0);
begin
concat1_y_net_x0 <= addr_11b;
shared_memory_data_out_net_x0 <= shared_memory;
constant1_x0 <= constant1_op_net_x0;
constant_x1 <= constant_op_net_x0;
data_8b <= mux_y_net_x0;
x9msb_x0 <= x9msb_y_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x0
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net_x0
);
mux: entity work.mux_998e20a1ca
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => x8lsb_24_y_net,
d1 => x8lsb_16_y_net,
d2 => x8lsb_8_y_net,
d3 => x8lsb_0_y_net,
sel => x2lsb_y_net,
y => mux_y_net_x0
);
x2lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 1,
x_width => 11,
y_width => 2
)
port map (
x => concat1_y_net_x0,
y => x2lsb_y_net
);
x8lsb_0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_0_y_net
);
x8lsb_16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_16_y_net
);
x8lsb_24: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 31,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_24_y_net
);
x8lsb_8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_8_y_net
);
x9msb: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 10,
x_width => 11,
y_width => 9
)
port map (
x => concat1_y_net_x0,
y => x9msb_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Character Map Shared Memory"
entity character_map_shared_memory_entity_e504c38a5b is
port (
addr_14b: in std_logic_vector(13 downto 0);
shared_memory: in std_logic_vector(31 downto 0);
constant1_x0: out std_logic;
constant_x1: out std_logic_vector(31 downto 0);
data_8b: out std_logic_vector(7 downto 0);
x12msb_x0: out std_logic_vector(11 downto 0)
);
end character_map_shared_memory_entity_e504c38a5b;
architecture structural of character_map_shared_memory_entity_e504c38a5b is
signal concat_y_net_x0: std_logic_vector(13 downto 0);
signal constant1_op_net_x0: std_logic;
signal constant_op_net_x0: std_logic_vector(31 downto 0);
signal mux_y_net_x0: std_logic_vector(7 downto 0);
signal shared_memory_data_out_net_x0: std_logic_vector(31 downto 0);
signal x12msb_y_net_x0: std_logic_vector(11 downto 0);
signal x2lsb_y_net: std_logic_vector(1 downto 0);
signal x8lsb_0_y_net: std_logic_vector(7 downto 0);
signal x8lsb_16_y_net: std_logic_vector(7 downto 0);
signal x8lsb_24_y_net: std_logic_vector(7 downto 0);
signal x8lsb_8_y_net: std_logic_vector(7 downto 0);
begin
concat_y_net_x0 <= addr_14b;
shared_memory_data_out_net_x0 <= shared_memory;
constant1_x0 <= constant1_op_net_x0;
constant_x1 <= constant_op_net_x0;
data_8b <= mux_y_net_x0;
x12msb_x0 <= x12msb_y_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x0
);
constant_x0: entity work.constant_37567836aa
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net_x0
);
mux: entity work.mux_998e20a1ca
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => x8lsb_24_y_net,
d1 => x8lsb_16_y_net,
d2 => x8lsb_8_y_net,
d3 => x8lsb_0_y_net,
sel => x2lsb_y_net,
y => mux_y_net_x0
);
x12msb: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 13,
x_width => 14,
y_width => 12
)
port map (
x => concat_y_net_x0,
y => x12msb_y_net_x0
);
x2lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 1,
x_width => 14,
y_width => 2
)
port map (
x => concat_y_net_x0,
y => x2lsb_y_net
);
x8lsb_0: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_0_y_net
);
x8lsb_16: entity work.xlslice
generic map (
new_lsb => 16,
new_msb => 23,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_16_y_net
);
x8lsb_24: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 31,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_24_y_net
);
x8lsb_8: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 15,
x_width => 32,
y_width => 8
)
port map (
x => shared_memory_data_out_net_x0,
y => x8lsb_8_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Pos Edge Detector"
entity pos_edge_detector_entity_90ec5fccc3 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
input_signal: in std_logic;
rising_edge: out std_logic
);
end pos_edge_detector_entity_90ec5fccc3;
architecture structural of pos_edge_detector_entity_90ec5fccc3 is
signal ce_1_sg_x10: std_logic;
signal clk_1_sg_x10: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal relational_op_net_x0: std_logic;
begin
ce_1_sg_x10 <= ce_1;
clk_1_sg_x10 <= clk_1;
relational_op_net_x0 <= input_signal;
rising_edge <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x10,
clk => clk_1_sg_x10,
d(0) => inverter_op_net,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x10,
clk => clk_1_sg_x10,
clr => '0',
ip(0) => relational_op_net_x0,
op(0) => inverter_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational_op_net_x0,
d1(0) => delay_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Subsystem"
entity subsystem_entity_8d430c7bea is
port (
ce_1: in std_logic;
clk_1: in std_logic;
not0: in std_logic;
transferdone: in std_logic;
x6bitval: in std_logic;
out1: out std_logic
);
end subsystem_entity_8d430c7bea;
architecture structural of subsystem_entity_8d430c7bea is
signal ce_1_sg_x11: std_logic;
signal clk_1_sg_x11: std_logic;
signal delay_q_net: std_logic;
signal inverter2_op_net_x0: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical_y_net_x0: std_logic;
signal relational_op_net_x1: std_logic;
begin
ce_1_sg_x11 <= ce_1;
clk_1_sg_x11 <= clk_1;
inverter2_op_net_x0 <= not0;
logical_y_net_x0 <= transferdone;
relational_op_net_x1 <= x6bitval;
out1 <= logical3_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x11,
clk => clk_1_sg_x11,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay_q_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => inverter2_op_net_x0,
d1(0) => delay_q_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational_op_net_x1,
d1(0) => delay_q_net,
y(0) => logical2_y_net
);
logical3: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => logical2_y_net,
d1(0) => logical1_y_net,
y(0) => logical3_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM/Subsystem1"
entity subsystem1_entity_a91e11b915 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
x4bits: in std_logic_vector(3 downto 0);
end_x0: out std_logic_vector(8 downto 0);
start: out std_logic_vector(8 downto 0)
);
end subsystem1_entity_a91e11b915;
architecture structural of subsystem1_entity_a91e11b915 is
signal addsub1_s_net_x0: std_logic_vector(8 downto 0);
signal addsub_s_net_x0: std_logic_vector(8 downto 0);
signal ce_1_sg_x12: std_logic;
signal clk_1_sg_x12: std_logic;
signal concat6_y_net: std_logic_vector(6 downto 0);
signal constant1_op_net: std_logic_vector(7 downto 0);
signal constant2_op_net: std_logic_vector(7 downto 0);
signal constant_op_net: std_logic_vector(2 downto 0);
signal slice10_y_net_x0: std_logic_vector(3 downto 0);
begin
ce_1_sg_x12 <= ce_1;
clk_1_sg_x12 <= clk_1;
slice10_y_net_x0 <= x4bits;
end_x0 <= addsub1_s_net_x0;
start <= addsub_s_net_x0;
addsub: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 7,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 8,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 9,
core_name0 => "adder_subtracter_virtex2p_7_0_453ed16ba8e84295",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 9,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 9
)
port map (
a => concat6_y_net,
b => constant1_op_net,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
en => "1",
s => addsub_s_net_x0
);
addsub1: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 7,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 8,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 9,
core_name0 => "adder_subtracter_virtex2p_7_0_453ed16ba8e84295",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 9,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 9
)
port map (
a => concat6_y_net,
b => constant2_op_net,
ce => ce_1_sg_x12,
clk => clk_1_sg_x12,
clr => '0',
en => "1",
s => addsub1_s_net_x0
);
concat6: entity work.concat_32864ba5d6
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => slice10_y_net_x0,
in1 => constant_op_net,
y => concat6_y_net
);
constant1: entity work.constant_21d4a28b7e
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant2: entity work.constant_b940b9054a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant2_op_net
);
constant_x0: entity work.constant_822933f89b
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/DataROM"
entity datarom_entity_fd2cd392cc is
port (
ce_1: in std_logic;
clk_1: in std_logic;
cmdsdone: in std_logic;
from_register1: in std_logic_vector(8 downto 0);
from_register2: in std_logic_vector(8 downto 0);
from_register3: in std_logic_vector(8 downto 0);
from_register4: in std_logic_vector(2 downto 0);
from_register5: in std_logic_vector(3 downto 0);
from_register7: in std_logic_vector(3 downto 0);
reset: in std_logic;
shared_memory: in std_logic_vector(31 downto 0);
shared_memory_x0: in std_logic_vector(31 downto 0);
transferdone: in std_logic;
character_buffer_shared_memory: out std_logic_vector(8 downto 0);
character_buffer_shared_memory_x0: out std_logic_vector(31 downto 0);
character_buffer_shared_memory_x1: out std_logic;
character_map_shared_memory: out std_logic_vector(11 downto 0);
character_map_shared_memory_x0: out std_logic_vector(31 downto 0);
character_map_shared_memory_x1: out std_logic;
data: out std_logic_vector(8 downto 0);
starttransfer: out std_logic
);
end datarom_entity_fd2cd392cc;
architecture structural of datarom_entity_fd2cd392cc is
signal addsub1_s_net: std_logic_vector(3 downto 0);
signal addsub1_s_net_x0: std_logic_vector(8 downto 0);
signal addsub1_s_net_x1: std_logic_vector(8 downto 0);
signal addsub2_s_net: std_logic_vector(3 downto 0);
signal addsub_s_net_x0: std_logic_vector(8 downto 0);
signal addsub_s_net_x1: std_logic_vector(8 downto 0);
signal ce_1_sg_x14: std_logic;
signal clk_1_sg_x14: std_logic;
signal concat1_y_net_x0: std_logic_vector(10 downto 0);
signal concat3_y_net: std_logic_vector(1 downto 0);
signal concat4_y_net_x0: std_logic_vector(8 downto 0);
signal concat5_y_net: std_logic_vector(8 downto 0);
signal concat_y_net_x0: std_logic_vector(13 downto 0);
signal constant10_op_net: std_logic;
signal constant1_op_net_x2: std_logic;
signal constant1_op_net_x3: std_logic;
signal constant4_op_net: std_logic;
signal constant5_op_net: std_logic;
signal constant6_op_net: std_logic_vector(2 downto 0);
signal constant7_op_net: std_logic_vector(2 downto 0);
signal constant8_op_net: std_logic_vector(2 downto 0);
signal constant9_op_net: std_logic;
signal constant_op_net_x2: std_logic_vector(31 downto 0);
signal constant_op_net_x3: std_logic_vector(31 downto 0);
signal convert1_dout_net: std_logic;
signal convert1_dout_net_x4: std_logic;
signal convert1_dout_net_x5: std_logic;
signal convert_dout_net: std_logic;
signal counter1_op_net: std_logic_vector(13 downto 0);
signal counter_op_net: std_logic_vector(2 downto 0);
signal delay_q_net_x0: std_logic;
signal from_register1_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x0: std_logic_vector(8 downto 0);
signal from_register4_data_out_net_x0: std_logic_vector(2 downto 0);
signal from_register5_data_out_net_x0: std_logic_vector(3 downto 0);
signal from_register7_data_out_net_x0: std_logic_vector(3 downto 0);
signal inverter2_op_net_x0: std_logic;
signal inverter3_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal mux2_y_net: std_logic_vector(2 downto 0);
signal mux3_y_net: std_logic_vector(8 downto 0);
signal mux_y_net_x0: std_logic_vector(7 downto 0);
signal mux_y_net_x1: std_logic_vector(7 downto 0);
signal register_q_net: std_logic_vector(5 downto 0);
signal register_q_net_x1: std_logic;
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational_op_net_x1: std_logic;
signal shared_memory_data_out_net_x2: std_logic_vector(31 downto 0);
signal shared_memory_data_out_net_x3: std_logic_vector(31 downto 0);
signal slice10_y_net_x0: std_logic_vector(3 downto 0);
signal slice11_y_net_x0: std_logic_vector(3 downto 0);
signal slice4_y_net: std_logic_vector(7 downto 0);
signal slice5_y_net: std_logic_vector(5 downto 0);
signal slice6_y_net: std_logic_vector(5 downto 0);
signal slice7_y_net: std_logic_vector(3 downto 0);
signal slice8_y_net: std_logic_vector(7 downto 0);
signal slice9_y_net: std_logic;
signal x12msb_y_net_x1: std_logic_vector(11 downto 0);
signal x4lsb_y_net: std_logic_vector(3 downto 0);
signal x4msb_y_net: std_logic_vector(3 downto 0);
signal x9msb_y_net_x1: std_logic_vector(8 downto 0);
begin
ce_1_sg_x14 <= ce_1;
clk_1_sg_x14 <= clk_1;
register_q_net_x1 <= cmdsdone;
from_register1_data_out_net_x0 <= from_register1;
from_register2_data_out_net_x0 <= from_register2;
from_register3_data_out_net_x0 <= from_register3;
from_register4_data_out_net_x0 <= from_register4;
from_register5_data_out_net_x0 <= from_register5;
from_register7_data_out_net_x0 <= from_register7;
convert1_dout_net_x4 <= reset;
shared_memory_data_out_net_x2 <= shared_memory;
shared_memory_data_out_net_x3 <= shared_memory_x0;
convert1_dout_net_x5 <= transferdone;
character_buffer_shared_memory <= x9msb_y_net_x1;
character_buffer_shared_memory_x0 <= constant_op_net_x2;
character_buffer_shared_memory_x1 <= constant1_op_net_x2;
character_map_shared_memory <= x12msb_y_net_x1;
character_map_shared_memory_x0 <= constant_op_net_x3;
character_map_shared_memory_x1 <= constant1_op_net_x3;
data <= concat4_y_net_x0;
starttransfer <= delay_q_net_x0;
addsub1: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 4,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 4,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 5,
core_name0 => "adder_subtracter_virtex2p_7_0_7182743c9e7adf5e",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 5,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 4
)
port map (
a => from_register7_data_out_net_x0,
b => x4msb_y_net,
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
en => "1",
s => addsub1_s_net
);
addsub2: entity work.xladdsub
generic map (
a_arith => xlUnsigned,
a_bin_pt => 0,
a_width => 4,
b_arith => xlUnsigned,
b_bin_pt => 0,
b_width => 4,
c_has_b_out => 0,
c_has_c_out => 0,
c_has_q => 0,
c_has_q_b_out => 0,
c_has_q_c_out => 0,
c_has_s => 1,
c_latency => 0,
c_output_width => 5,
core_name0 => "adder_subtracter_virtex2p_7_0_7182743c9e7adf5e",
extra_registers => 0,
full_s_arith => 1,
full_s_width => 5,
latency => 0,
mode => 1,
overflow => 1,
quantization => 1,
s_arith => xlUnsigned,
s_bin_pt => 0,
s_width => 4
)
port map (
a => x4lsb_y_net,
b => from_register5_data_out_net_x0,
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
en => "1",
s => addsub2_s_net
);
character_buffer_shared_memory_1eeb1f8786: entity work.character_buffer_shared_memory_entity_1eeb1f8786
port map (
addr_11b => concat1_y_net_x0,
shared_memory => shared_memory_data_out_net_x2,
constant1_x0 => constant1_op_net_x2,
constant_x1 => constant_op_net_x2,
data_8b => mux_y_net_x0,
x9msb_x0 => x9msb_y_net_x1
);
character_map_shared_memory_e504c38a5b: entity work.character_map_shared_memory_entity_e504c38a5b
port map (
addr_14b => concat_y_net_x0,
shared_memory => shared_memory_data_out_net_x3,
constant1_x0 => constant1_op_net_x3,
constant_x1 => constant_op_net_x3,
data_8b => mux_y_net_x1,
x12msb_x0 => x12msb_y_net_x1
);
concat: entity work.concat_25ab81b400
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => mux_y_net_x0,
in1 => register_q_net,
y => concat_y_net_x0
);
concat1: entity work.concat_78218439f3
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => from_register4_data_out_net_x0,
in1 => addsub1_s_net,
in2 => addsub2_s_net,
y => concat1_y_net_x0
);
concat3: entity work.concat_e6f5ee726b
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => convert_dout_net,
in1(0) => convert1_dout_net,
y => concat3_y_net
);
concat4: entity work.concat_1ece14600f
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => inverter3_op_net,
in1 => slice8_y_net,
y => concat4_y_net_x0
);
concat5: entity work.concat_1ece14600f
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => constant10_op_net,
in1 => mux_y_net_x1,
y => concat5_y_net
);
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net
);
constant4: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant4_op_net
);
constant5: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant5_op_net
);
constant6: entity work.constant_822933f89b
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant6_op_net
);
constant7: entity work.constant_469094441c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant7_op_net
);
constant8: entity work.constant_a1c496ea88
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant8_op_net
);
constant9: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant9_op_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => relational_op_net_x1,
dout(0) => convert_dout_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => relational1_op_net,
dout(0) => convert1_dout_net
);
counter: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_b511f9871581ee23",
op_arith => xlUnsigned,
op_width => 3
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
din => mux2_y_net,
en(0) => logical3_y_net_x0,
load(0) => logical_y_net_x1,
rst => "0",
op => counter_op_net
);
counter1: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_a22528b4c55dc1cd",
op_arith => xlUnsigned,
op_width => 14
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
en(0) => logical1_y_net,
rst(0) => convert1_dout_net_x4,
op => counter1_op_net
);
delay: entity work.xldelay
generic map (
latency => 4,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay_q_net_x0
);
inverter2: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
ip(0) => relational2_op_net,
op(0) => inverter2_op_net_x0
);
inverter3: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
clr => '0',
ip(0) => slice9_y_net,
op(0) => inverter3_op_net
);
logical: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => convert1_dout_net_x5,
d1(0) => register_q_net_x1,
y(0) => logical_y_net_x0
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => relational2_op_net,
d1(0) => logical_y_net_x0,
y(0) => logical1_y_net
);
mux2: entity work.mux_2ec2057ae3
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => constant6_op_net,
d1 => constant6_op_net,
d2 => constant7_op_net,
d3 => constant8_op_net,
sel => concat3_y_net,
y => mux2_y_net
);
mux3: entity work.mux_7586447000
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => concat5_y_net,
d1 => from_register3_data_out_net_x0,
d2 => addsub_s_net_x0,
d3 => addsub1_s_net_x0,
d4 => from_register1_data_out_net_x0,
d5 => addsub_s_net_x1,
d6 => addsub1_s_net_x1,
d7 => from_register2_data_out_net_x0,
sel => counter_op_net,
y => mux3_y_net
);
pos_edge_detector_90ec5fccc3: entity work.pos_edge_detector_entity_90ec5fccc3
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
input_signal => relational_op_net_x1,
rising_edge => logical_y_net_x1
);
register_x0: entity work.xlregister
generic map (
d_width => 6,
init_value => b"000000"
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d => slice5_y_net,
en => "1",
rst => "0",
q => register_q_net
);
relational: entity work.relational_f7cb2b0c31
port map (
a => slice6_y_net,
b(0) => constant4_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational_op_net_x1
);
relational1: entity work.relational_ee03197e2c
port map (
a => slice7_y_net,
b(0) => constant5_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_04b069dd89
port map (
a => counter_op_net,
b(0) => constant9_op_net,
ce => '0',
clk => '0',
clr => '0',
op(0) => relational2_op_net
);
slice10: entity work.xlslice
generic map (
new_lsb => 10,
new_msb => 13,
x_width => 14,
y_width => 4
)
port map (
x => counter1_op_net,
y => slice10_y_net_x0
);
slice11: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 9,
x_width => 14,
y_width => 4
)
port map (
x => counter1_op_net,
y => slice11_y_net_x0
);
slice4: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 13,
x_width => 14,
y_width => 8
)
port map (
x => counter1_op_net,
y => slice4_y_net
);
slice5: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 5,
x_width => 14,
y_width => 6
)
port map (
x => counter1_op_net,
y => slice5_y_net
);
slice6: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 5,
x_width => 14,
y_width => 6
)
port map (
x => counter1_op_net,
y => slice6_y_net
);
slice7: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 9,
x_width => 14,
y_width => 4
)
port map (
x => counter1_op_net,
y => slice7_y_net
);
slice8: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 7,
x_width => 9,
y_width => 8
)
port map (
x => mux3_y_net,
y => slice8_y_net
);
slice9: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 9,
y_width => 1
)
port map (
x => mux3_y_net,
y(0) => slice9_y_net
);
subsystem1_a91e11b915: entity work.subsystem1_entity_a91e11b915
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
x4bits => slice10_y_net_x0,
end_x0 => addsub1_s_net_x0,
start => addsub_s_net_x0
);
subsystem2_4e1ae86655: entity work.subsystem1_entity_a91e11b915
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
x4bits => slice11_y_net_x0,
end_x0 => addsub1_s_net_x1,
start => addsub_s_net_x1
);
subsystem_8d430c7bea: entity work.subsystem_entity_8d430c7bea
port map (
ce_1 => ce_1_sg_x14,
clk_1 => clk_1_sg_x14,
not0 => inverter2_op_net_x0,
transferdone => logical_y_net_x0,
x6bitval => relational_op_net_x1,
out1 => logical3_y_net_x0
);
x4lsb: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 3,
x_width => 8,
y_width => 4
)
port map (
x => slice4_y_net,
y => x4lsb_y_net
);
x4msb: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 7,
x_width => 8,
y_width => 4
)
port map (
x => slice4_y_net,
y => x4msb_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/SPI/Data_Latch"
entity data_latch_entity_d697580f4e is
port (
bit_select: in std_logic_vector(3 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
data_to_transmit: in std_logic_vector(8 downto 0);
latchdata: in std_logic;
reset: in std_logic;
spi_data: out std_logic
);
end data_latch_entity_d697580f4e;
architecture structural of data_latch_entity_d697580f4e is
signal ce_1_sg_x16: std_logic;
signal clk_1_sg_x16: std_logic;
signal convert1_dout_net_x5: std_logic;
signal counter_op_net_x0: std_logic_vector(3 downto 0);
signal mux1_y_net_x0: std_logic;
signal mux_y_net_x1: std_logic_vector(8 downto 0);
signal mux_y_net_x2: std_logic;
signal register_q_net: std_logic_vector(8 downto 0);
signal slice1_y_net: std_logic;
signal slice2_y_net: std_logic;
signal slice3_y_net: std_logic;
signal slice4_y_net: std_logic;
signal slice5_y_net: std_logic;
signal slice6_y_net: std_logic;
signal slice7_y_net: std_logic;
signal slice8_y_net: std_logic;
signal slice_y_net: std_logic;
begin
counter_op_net_x0 <= bit_select;
ce_1_sg_x16 <= ce_1;
clk_1_sg_x16 <= clk_1;
mux_y_net_x1 <= data_to_transmit;
mux1_y_net_x0 <= latchdata;
convert1_dout_net_x5 <= reset;
spi_data <= mux_y_net_x2;
mux: entity work.mux_8e3eece8f2
port map (
ce => ce_1_sg_x16,
clk => clk_1_sg_x16,
clr => '0',
d0(0) => slice_y_net,
d1(0) => slice1_y_net,
d2(0) => slice2_y_net,
d3(0) => slice3_y_net,
d4(0) => slice4_y_net,
d5(0) => slice5_y_net,
d6(0) => slice6_y_net,
d7(0) => slice7_y_net,
d8(0) => slice8_y_net,
sel => counter_op_net_x0,
y(0) => mux_y_net_x2
);
register_x0: entity work.xlregister
generic map (
d_width => 9,
init_value => b"000000000"
)
port map (
ce => ce_1_sg_x16,
clk => clk_1_sg_x16,
d => mux_y_net_x1,
en(0) => mux1_y_net_x0,
rst(0) => convert1_dout_net_x5,
q => register_q_net
);
slice: entity work.xlslice
generic map (
new_lsb => 8,
new_msb => 8,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice_y_net
);
slice1: entity work.xlslice
generic map (
new_lsb => 7,
new_msb => 7,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice1_y_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 6,
new_msb => 6,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice2_y_net
);
slice3: entity work.xlslice
generic map (
new_lsb => 5,
new_msb => 5,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice3_y_net
);
slice4: entity work.xlslice
generic map (
new_lsb => 4,
new_msb => 4,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice4_y_net
);
slice5: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice5_y_net
);
slice6: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 2,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice6_y_net
);
slice7: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 1,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice7_y_net
);
slice8: entity work.xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 9,
y_width => 1
)
port map (
x => register_q_net,
y(0) => slice8_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/SPI/Pos Edge Detector"
entity pos_edge_detector_entity_ac86c1f1ba is
port (
ce_1: in std_logic;
clk_1: in std_logic;
input_signal: in std_logic;
rising_edge: out std_logic
);
end pos_edge_detector_entity_ac86c1f1ba;
architecture structural of pos_edge_detector_entity_ac86c1f1ba is
signal ce_1_sg_x17: std_logic;
signal clk_1_sg_x17: std_logic;
signal delay_q_net: std_logic;
signal inverter_op_net: std_logic;
signal logical_y_net_x0: std_logic;
signal mux_y_net_x0: std_logic;
begin
ce_1_sg_x17 <= ce_1;
clk_1_sg_x17 <= clk_1;
mux_y_net_x0 <= input_signal;
rising_edge <= logical_y_net_x0;
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x17,
clk => clk_1_sg_x17,
d(0) => inverter_op_net,
en => '1',
q(0) => delay_q_net
);
inverter: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x17,
clk => clk_1_sg_x17,
clr => '0',
ip(0) => mux_y_net_x0,
op(0) => inverter_op_net
);
logical: entity work.logical_938d99ac11
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => mux_y_net_x0,
d1(0) => delay_q_net,
y(0) => logical_y_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller/SPI"
entity spi_entity_fd37afb7f3 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
data_to_transfer: in std_logic_vector(8 downto 0);
dividerselect: in std_logic;
reset: in std_logic;
send: in std_logic;
cs: out std_logic;
data: out std_logic;
done: out std_logic;
scl: out std_logic
);
end spi_entity_fd37afb7f3;
architecture structural of spi_entity_fd37afb7f3 is
signal ce_1_sg_x19: std_logic;
signal clk_1_sg_x19: std_logic;
signal constant_op_net: std_logic_vector(3 downto 0);
signal convert1_dout_net_x7: std_logic;
signal convert1_dout_net_x8: std_logic;
signal convert_dout_net_x0: std_logic;
signal convert_dout_net_x1: std_logic;
signal counter1_op_net: std_logic_vector(3 downto 0);
signal counter_op_net_x0: std_logic_vector(3 downto 0);
signal delay1_q_net: std_logic;
signal delay_q_net: std_logic;
signal inverter1_op_net_x0: std_logic;
signal inverter_op_net_x0: std_logic;
signal logical_y_net: std_logic;
signal logical_y_net_x0: std_logic;
signal logical_y_net_x1: std_logic;
signal mux1_y_net: std_logic;
signal mux1_y_net_x1: std_logic;
signal mux_y_net_x3: std_logic_vector(8 downto 0);
signal mux_y_net_x4: std_logic;
signal mux_y_net_x5: std_logic;
signal register_q_net: std_logic;
signal slice1_y_net: std_logic;
signal slice2_y_net: std_logic;
signal slice_y_net: std_logic;
begin
ce_1_sg_x19 <= ce_1;
clk_1_sg_x19 <= clk_1;
mux_y_net_x3 <= data_to_transfer;
convert_dout_net_x1 <= dividerselect;
convert1_dout_net_x7 <= reset;
mux1_y_net_x1 <= send;
cs <= inverter_op_net_x0;
data <= mux_y_net_x4;
done <= convert1_dout_net_x8;
scl <= mux_y_net_x5;
constant_x0: entity work.constant_06590e4008
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => mux1_y_net,
dout(0) => convert_dout_net_x0
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => logical_y_net_x1,
dout(0) => convert1_dout_net_x8
);
counter: entity work.xlcounter_limit
generic map (
cnt_15_0 => 8,
cnt_31_16 => 0,
cnt_47_32 => 0,
cnt_63_48 => 0,
core_name0 => "binary_counter_virtex2p_7_0_23542cbcca0efa2e",
count_limited => 1,
op_arith => xlUnsigned,
op_width => 4
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
en(0) => convert_dout_net_x0,
rst(0) => convert1_dout_net_x7,
op => counter_op_net_x0
);
counter1: entity work.xlcounter_free
generic map (
core_name0 => "binary_counter_virtex2p_7_0_77cea312f82499f0",
op_arith => xlUnsigned,
op_width => 4
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
din => constant_op_net,
en(0) => register_q_net,
load(0) => convert1_dout_net_x8,
rst(0) => convert1_dout_net_x7,
op => counter1_op_net
);
data_latch_d697580f4e: entity work.data_latch_entity_d697580f4e
port map (
bit_select => counter_op_net_x0,
ce_1 => ce_1_sg_x19,
clk_1 => clk_1_sg_x19,
data_to_transmit => mux_y_net_x3,
latchdata => mux1_y_net_x1,
reset => convert1_dout_net_x7,
spi_data => mux_y_net_x4
);
delay: entity work.xldelay
generic map (
latency => 2,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 6,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
d(0) => logical_y_net_x0,
en => '1',
q(0) => delay1_q_net
);
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
ip(0) => register_q_net,
op(0) => inverter_op_net_x0
);
inverter1: entity work.inverter_e2b989a05e
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
clr => '0',
ip(0) => slice1_y_net,
op(0) => inverter1_op_net_x0
);
logical: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => convert1_dout_net_x8,
d1(0) => mux1_y_net_x1,
y(0) => logical_y_net
);
mux: entity work.mux_112ed141f4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => slice_y_net,
d1(0) => slice2_y_net,
sel(0) => convert_dout_net_x1,
y(0) => mux_y_net_x5
);
mux1: entity work.mux_112ed141f4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => delay_q_net,
d1(0) => delay1_q_net,
sel(0) => convert_dout_net_x1,
y(0) => mux1_y_net
);
pos_edge_detector2_d448638b52: entity work.pos_edge_detector_entity_ac86c1f1ba
port map (
ce_1 => ce_1_sg_x19,
clk_1 => clk_1_sg_x19,
input_signal => inverter1_op_net_x0,
rising_edge => logical_y_net_x1
);
pos_edge_detector_ac86c1f1ba: entity work.pos_edge_detector_entity_ac86c1f1ba
port map (
ce_1 => ce_1_sg_x19,
clk_1 => clk_1_sg_x19,
input_signal => mux_y_net_x5,
rising_edge => logical_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x19,
clk => clk_1_sg_x19,
d(0) => mux1_y_net_x1,
en(0) => logical_y_net,
rst(0) => convert1_dout_net_x7,
q(0) => register_q_net
);
slice: entity work.xlslice
generic map (
new_lsb => 2,
new_msb => 2,
x_width => 4,
y_width => 1
)
port map (
x => counter1_op_net,
y(0) => slice_y_net
);
slice1: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 4,
y_width => 1
)
port map (
x => counter_op_net_x0,
y(0) => slice1_y_net
);
slice2: entity work.xlslice
generic map (
new_lsb => 3,
new_msb => 3,
x_width => 4,
y_width => 1
)
port map (
x => counter1_op_net,
y(0) => slice2_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller/LCD Controller"
entity lcd_controller_entity_e3a358fc2f is
port (
ce_1: in std_logic;
clk_1: in std_logic;
from_register: in std_logic;
from_register1: in std_logic_vector(8 downto 0);
from_register1_x0: in std_logic_vector(8 downto 0);
from_register2: in std_logic_vector(8 downto 0);
from_register2_x0: in std_logic_vector(8 downto 0);
from_register3: in std_logic_vector(8 downto 0);
from_register3_x0: in std_logic_vector(8 downto 0);
from_register3_x1: in std_logic_vector(7 downto 0);
from_register4: in std_logic_vector(8 downto 0);
from_register4_x0: in std_logic_vector(2 downto 0);
from_register4_x1: in std_logic;
from_register5: in std_logic_vector(8 downto 0);
from_register5_x0: in std_logic_vector(3 downto 0);
from_register5_x1: in std_logic;
from_register6: in std_logic_vector(1 downto 0);
from_register6_x0: in std_logic;
from_register7: in std_logic_vector(3 downto 0);
reset: in std_logic;
shared_memory: in std_logic_vector(31 downto 0);
shared_memory_x0: in std_logic_vector(31 downto 0);
shared_memory_x1: in std_logic_vector(31 downto 0);
commandrom: out std_logic_vector(7 downto 0);
commandrom_x0: out std_logic_vector(31 downto 0);
commandrom_x1: out std_logic;
datarom: out std_logic_vector(8 downto 0);
datarom_x0: out std_logic_vector(31 downto 0);
datarom_x1: out std_logic;
datarom_x2: out std_logic_vector(11 downto 0);
datarom_x3: out std_logic_vector(31 downto 0);
datarom_x4: out std_logic;
delay_x0: out std_logic;
spi: out std_logic;
spi_x0: out std_logic;
spi_x1: out std_logic
);
end lcd_controller_entity_e3a358fc2f;
architecture structural of lcd_controller_entity_e3a358fc2f is
signal ce_1_sg_x20: std_logic;
signal clk_1_sg_x20: std_logic;
signal concat2_y_net_x0: std_logic_vector(8 downto 0);
signal concat4_y_net_x0: std_logic_vector(8 downto 0);
signal constant1_op_net_x4: std_logic;
signal constant1_op_net_x5: std_logic;
signal constant1_op_net_x6: std_logic;
signal constant_op_net_x4: std_logic_vector(31 downto 0);
signal constant_op_net_x5: std_logic_vector(31 downto 0);
signal constant_op_net_x6: std_logic_vector(31 downto 0);
signal convert1_dout_net_x7: std_logic;
signal convert1_dout_net_x8: std_logic;
signal convert2_dout_net_x0: std_logic;
signal convert_dout_net_x1: std_logic;
signal delay_q_net_x0: std_logic;
signal delay_q_net_x1: std_logic;
signal from_register1_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register1_data_out_net_x3: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register2_data_out_net_x3: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x3: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x4: std_logic_vector(8 downto 0);
signal from_register3_data_out_net_x5: std_logic_vector(7 downto 0);
signal from_register4_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register4_data_out_net_x3: std_logic_vector(2 downto 0);
signal from_register4_data_out_net_x4: std_logic;
signal from_register5_data_out_net_x2: std_logic_vector(8 downto 0);
signal from_register5_data_out_net_x3: std_logic_vector(3 downto 0);
signal from_register5_data_out_net_x4: std_logic;
signal from_register6_data_out_net_x1: std_logic_vector(1 downto 0);
signal from_register6_data_out_net_x2: std_logic;
signal from_register7_data_out_net_x1: std_logic_vector(3 downto 0);
signal from_register_data_out_net_x0: std_logic;
signal inverter_op_net_x1: std_logic;
signal logical1_y_net: std_logic;
signal logical_y_net_x3: std_logic;
signal mux1_y_net_x1: std_logic;
signal mux2_y_net_x0: std_logic;
signal mux_y_net_x3: std_logic_vector(8 downto 0);
signal mux_y_net_x6: std_logic;
signal mux_y_net_x7: std_logic;
signal register_q_net_x1: std_logic;
signal reset_net_x0: std_logic;
signal shared_memory_data_out_net_x4: std_logic_vector(31 downto 0);
signal shared_memory_data_out_net_x5: std_logic_vector(31 downto 0);
signal shared_memory_data_out_net_x6: std_logic_vector(31 downto 0);
signal x12msb_y_net_x2: std_logic_vector(11 downto 0);
signal x8msb_y_net_x2: std_logic_vector(7 downto 0);
signal x9msb_y_net_x2: std_logic_vector(8 downto 0);
begin
ce_1_sg_x20 <= ce_1;
clk_1_sg_x20 <= clk_1;
from_register_data_out_net_x0 <= from_register;
from_register1_data_out_net_x2 <= from_register1;
from_register1_data_out_net_x3 <= from_register1_x0;
from_register2_data_out_net_x2 <= from_register2;
from_register2_data_out_net_x3 <= from_register2_x0;
from_register3_data_out_net_x3 <= from_register3;
from_register3_data_out_net_x4 <= from_register3_x0;
from_register3_data_out_net_x5 <= from_register3_x1;
from_register4_data_out_net_x2 <= from_register4;
from_register4_data_out_net_x3 <= from_register4_x0;
from_register4_data_out_net_x4 <= from_register4_x1;
from_register5_data_out_net_x2 <= from_register5;
from_register5_data_out_net_x3 <= from_register5_x0;
from_register5_data_out_net_x4 <= from_register5_x1;
from_register6_data_out_net_x1 <= from_register6;
from_register6_data_out_net_x2 <= from_register6_x0;
from_register7_data_out_net_x1 <= from_register7;
reset_net_x0 <= reset;
shared_memory_data_out_net_x4 <= shared_memory;
shared_memory_data_out_net_x5 <= shared_memory_x0;
shared_memory_data_out_net_x6 <= shared_memory_x1;
commandrom <= x8msb_y_net_x2;
commandrom_x0 <= constant_op_net_x4;
commandrom_x1 <= constant1_op_net_x4;
datarom <= x9msb_y_net_x2;
datarom_x0 <= constant_op_net_x5;
datarom_x1 <= constant1_op_net_x5;
datarom_x2 <= x12msb_y_net_x2;
datarom_x3 <= constant_op_net_x6;
datarom_x4 <= constant1_op_net_x6;
delay_x0 <= delay_q_net_x1;
spi <= mux_y_net_x6;
spi_x0 <= inverter_op_net_x1;
spi_x1 <= mux_y_net_x7;
commandrom_b68e0d97b7: entity work.commandrom_entity_b68e0d97b7
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
from_register1 => from_register1_data_out_net_x2,
from_register2 => from_register2_data_out_net_x2,
from_register3 => from_register3_data_out_net_x3,
from_register4 => from_register4_data_out_net_x2,
from_register5 => from_register5_data_out_net_x2,
from_register6 => from_register6_data_out_net_x1,
reset => convert1_dout_net_x7,
sendcmds => logical_y_net_x3,
shared_memory => shared_memory_data_out_net_x4,
totalnoofcmds => from_register3_data_out_net_x5,
transferdone => convert1_dout_net_x8,
cmdsdone => register_q_net_x1,
command_memory => x8msb_y_net_x2,
command_memory_x0 => constant_op_net_x4,
command_memory_x1 => constant1_op_net_x4,
datatosend => concat2_y_net_x0,
starttransfer => mux2_y_net_x0
);
convert: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => from_register4_data_out_net_x4,
dout(0) => convert_dout_net_x1
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => logical1_y_net,
dout(0) => convert1_dout_net_x7
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => '0',
clk => '0',
clr => '0',
din(0) => from_register5_data_out_net_x4,
dout(0) => convert2_dout_net_x0
);
datarom_fd2cd392cc: entity work.datarom_entity_fd2cd392cc
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
cmdsdone => register_q_net_x1,
from_register1 => from_register1_data_out_net_x3,
from_register2 => from_register2_data_out_net_x3,
from_register3 => from_register3_data_out_net_x4,
from_register4 => from_register4_data_out_net_x3,
from_register5 => from_register5_data_out_net_x3,
from_register7 => from_register7_data_out_net_x1,
reset => convert1_dout_net_x7,
shared_memory => shared_memory_data_out_net_x5,
shared_memory_x0 => shared_memory_data_out_net_x6,
transferdone => convert1_dout_net_x8,
character_buffer_shared_memory => x9msb_y_net_x2,
character_buffer_shared_memory_x0 => constant_op_net_x5,
character_buffer_shared_memory_x1 => constant1_op_net_x5,
character_map_shared_memory => x12msb_y_net_x2,
character_map_shared_memory_x0 => constant_op_net_x6,
character_map_shared_memory_x1 => constant1_op_net_x6,
data => concat4_y_net_x0,
starttransfer => delay_q_net_x0
);
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
width => 1
)
port map (
ce => ce_1_sg_x20,
clk => clk_1_sg_x20,
d(0) => from_register6_data_out_net_x2,
en => '1',
q(0) => delay_q_net_x1
);
logical1: entity work.logical_3e1f051fb7
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => reset_net_x0,
d1(0) => from_register_data_out_net_x0,
y(0) => logical1_y_net
);
mux: entity work.mux_791081a00e
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => concat2_y_net_x0,
d1 => concat4_y_net_x0,
sel(0) => register_q_net_x1,
y => mux_y_net_x3
);
mux1: entity work.mux_d99e59b6d4
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => mux2_y_net_x0,
d1(0) => delay_q_net_x0,
sel(0) => register_q_net_x1,
y(0) => mux1_y_net_x1
);
pos_edge_detector_63345fcb1c: entity work.pos_edge_detector_entity_90ec5fccc3
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
input_signal => convert2_dout_net_x0,
rising_edge => logical_y_net_x3
);
spi_fd37afb7f3: entity work.spi_entity_fd37afb7f3
port map (
ce_1 => ce_1_sg_x20,
clk_1 => clk_1_sg_x20,
data_to_transfer => mux_y_net_x3,
dividerselect => convert_dout_net_x1,
reset => convert1_dout_net_x7,
send => mux1_y_net_x1,
cs => inverter_op_net_x1,
data => mux_y_net_x6,
done => convert1_dout_net_x8,
scl => mux_y_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "user_io_board_controller"
entity user_io_board_controller is
port (
buttons_big: in std_logic_vector(1 downto 0);
buttons_small: in std_logic_vector(5 downto 0);
ce_1: in std_logic;
clk_1: in std_logic;
data_out: in std_logic_vector(17 downto 0);
data_out_x0: in std_logic_vector(17 downto 0);
data_out_x1: in std_logic;
data_out_x10: in std_logic;
data_out_x11: in std_logic_vector(7 downto 0);
data_out_x12: in std_logic;
data_out_x13: in std_logic;
data_out_x14: in std_logic;
data_out_x15: in std_logic_vector(8 downto 0);
data_out_x16: in std_logic_vector(8 downto 0);
data_out_x17: in std_logic_vector(8 downto 0);
data_out_x18: in std_logic_vector(8 downto 0);
data_out_x19: in std_logic_vector(8 downto 0);
data_out_x2: in std_logic_vector(1 downto 0);
data_out_x20: in std_logic_vector(1 downto 0);
data_out_x21: in std_logic_vector(31 downto 0);
data_out_x22: in std_logic_vector(3 downto 0);
data_out_x23: in std_logic_vector(3 downto 0);
data_out_x24: in std_logic_vector(8 downto 0);
data_out_x25: in std_logic_vector(8 downto 0);
data_out_x26: in std_logic_vector(8 downto 0);
data_out_x27: in std_logic_vector(2 downto 0);
data_out_x28: in std_logic_vector(31 downto 0);
data_out_x29: in std_logic_vector(31 downto 0);
data_out_x3: in std_logic_vector(5 downto 0);
data_out_x4: in std_logic_vector(3 downto 0);
data_out_x5: in std_logic_vector(4 downto 0);
data_out_x6: in std_logic_vector(31 downto 0);
data_out_x7: in std_logic_vector(31 downto 0);
data_out_x8: in std_logic_vector(31 downto 0);
data_out_x9: in std_logic_vector(7 downto 0);
dip_switch: in std_logic_vector(3 downto 0);
dout: in std_logic_vector(17 downto 0);
dout_x0: in std_logic;
dout_x1: in std_logic_vector(17 downto 0);
dout_x10: in std_logic_vector(3 downto 0);
dout_x11: in std_logic_vector(8 downto 0);
dout_x12: in std_logic;
dout_x13: in std_logic;
dout_x14: in std_logic_vector(8 downto 0);
dout_x15: in std_logic_vector(8 downto 0);
dout_x16: in std_logic_vector(8 downto 0);
dout_x17: in std_logic;
dout_x18: in std_logic_vector(7 downto 0);
dout_x19: in std_logic_vector(7 downto 0);
dout_x2: in std_logic_vector(8 downto 0);
dout_x3: in std_logic_vector(3 downto 0);
dout_x4: in std_logic_vector(2 downto 0);
dout_x5: in std_logic_vector(8 downto 0);
dout_x6: in std_logic_vector(1 downto 0);
dout_x7: in std_logic;
dout_x8: in std_logic_vector(8 downto 0);
dout_x9: in std_logic_vector(8 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
reset: in std_logic;
sg_plb_addrpref: in std_logic_vector(14 downto 0);
splb_rst: in std_logic;
trackball_ox: in std_logic;
trackball_oxn: in std_logic;
trackball_oy: in std_logic;
trackball_oyn: in std_logic;
trackball_sel2: in std_logic;
addr: out std_logic_vector(11 downto 0);
addr_x0: out std_logic_vector(8 downto 0);
addr_x1: out std_logic_vector(7 downto 0);
addr_x2: out std_logic_vector(7 downto 0);
addr_x3: out std_logic_vector(8 downto 0);
addr_x4: out std_logic_vector(11 downto 0);
buzzer: out std_logic;
cs: out std_logic;
data_in: out std_logic_vector(17 downto 0);
data_in_x0: out std_logic;
data_in_x1: out std_logic_vector(17 downto 0);
data_in_x10: out std_logic_vector(3 downto 0);
data_in_x11: out std_logic_vector(8 downto 0);
data_in_x12: out std_logic;
data_in_x13: out std_logic;
data_in_x14: out std_logic_vector(8 downto 0);
data_in_x15: out std_logic_vector(8 downto 0);
data_in_x16: out std_logic_vector(8 downto 0);
data_in_x17: out std_logic;
data_in_x18: out std_logic_vector(7 downto 0);
data_in_x19: out std_logic_vector(7 downto 0);
data_in_x2: out std_logic_vector(8 downto 0);
data_in_x20: out std_logic_vector(31 downto 0);
data_in_x21: out std_logic_vector(31 downto 0);
data_in_x22: out std_logic_vector(31 downto 0);
data_in_x23: out std_logic_vector(4 downto 0);
data_in_x24: out std_logic_vector(1 downto 0);
data_in_x25: out std_logic_vector(5 downto 0);
data_in_x26: out std_logic_vector(3 downto 0);
data_in_x27: out std_logic_vector(31 downto 0);
data_in_x28: out std_logic_vector(31 downto 0);
data_in_x29: out std_logic_vector(31 downto 0);
data_in_x3: out std_logic_vector(3 downto 0);
data_in_x4: out std_logic_vector(2 downto 0);
data_in_x5: out std_logic_vector(8 downto 0);
data_in_x6: out std_logic_vector(1 downto 0);
data_in_x7: out std_logic;
data_in_x8: out std_logic_vector(8 downto 0);
data_in_x9: out std_logic_vector(8 downto 0);
en: out std_logic;
en_x0: out std_logic;
en_x1: out std_logic;
en_x10: out std_logic;
en_x11: out std_logic;
en_x12: out std_logic;
en_x13: out std_logic;
en_x14: out std_logic;
en_x15: out std_logic;
en_x16: out std_logic;
en_x17: out std_logic;
en_x18: out std_logic;
en_x19: out std_logic;
en_x2: out std_logic;
en_x20: out std_logic;
en_x21: out std_logic;
en_x22: out std_logic;
en_x23: out std_logic;
en_x3: out std_logic;
en_x4: out std_logic;
en_x5: out std_logic;
en_x6: out std_logic;
en_x7: out std_logic;
en_x8: out std_logic;
en_x9: out std_logic;
leds: out std_logic_vector(7 downto 0);
resetlcd: out std_logic;
scl: out std_logic;
sdi: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
trackball_sel1: out std_logic;
trackball_xscn: out std_logic;
trackball_yscn: out std_logic;
we: out std_logic;
we_x0: out std_logic;
we_x1: out std_logic;
we_x2: out std_logic;
we_x3: out std_logic;
we_x4: out std_logic
);
end user_io_board_controller;
architecture structural of user_io_board_controller is
signal addr_net: std_logic_vector(11 downto 0);
signal addr_x0_net: std_logic_vector(8 downto 0);
signal addr_x1_net: std_logic_vector(7 downto 0);
signal addr_x2_net: std_logic_vector(7 downto 0);
signal addr_x3_net: std_logic_vector(8 downto 0);
signal addr_x4_net: std_logic_vector(11 downto 0);
signal buttons_big_net: std_logic_vector(1 downto 0);
signal buttons_small_net: std_logic_vector(5 downto 0);
signal buzzer_net: std_logic;
signal ce_1_sg_x21: std_logic;
signal clk_1_sg_x21: std_logic;
signal cs_net: std_logic;
signal data_in_net: std_logic_vector(17 downto 0);
signal data_in_x0_net: std_logic;
signal data_in_x10_net: std_logic_vector(3 downto 0);
signal data_in_x11_net: std_logic_vector(8 downto 0);
signal data_in_x12_net: std_logic;
signal data_in_x13_net: std_logic;
signal data_in_x14_net: std_logic_vector(8 downto 0);
signal data_in_x15_net: std_logic_vector(8 downto 0);
signal data_in_x16_net: std_logic_vector(8 downto 0);
signal data_in_x17_net: std_logic;
signal data_in_x18_net: std_logic_vector(7 downto 0);
signal data_in_x19_net: std_logic_vector(7 downto 0);
signal data_in_x1_net: std_logic_vector(17 downto 0);
signal data_in_x20_net: std_logic_vector(31 downto 0);
signal data_in_x21_net: std_logic_vector(31 downto 0);
signal data_in_x22_net: std_logic_vector(31 downto 0);
signal data_in_x23_net: std_logic_vector(4 downto 0);
signal data_in_x24_net: std_logic_vector(1 downto 0);
signal data_in_x25_net: std_logic_vector(5 downto 0);
signal data_in_x26_net: std_logic_vector(3 downto 0);
signal data_in_x27_net: std_logic_vector(31 downto 0);
signal data_in_x28_net: std_logic_vector(31 downto 0);
signal data_in_x29_net: std_logic_vector(31 downto 0);
signal data_in_x2_net: std_logic_vector(8 downto 0);
signal data_in_x3_net: std_logic_vector(3 downto 0);
signal data_in_x4_net: std_logic_vector(2 downto 0);
signal data_in_x5_net: std_logic_vector(8 downto 0);
signal data_in_x6_net: std_logic_vector(1 downto 0);
signal data_in_x7_net: std_logic;
signal data_in_x8_net: std_logic_vector(8 downto 0);
signal data_in_x9_net: std_logic_vector(8 downto 0);
signal data_out_net: std_logic_vector(17 downto 0);
signal data_out_x0_net: std_logic_vector(17 downto 0);
signal data_out_x10_net: std_logic;
signal data_out_x11_net: std_logic_vector(7 downto 0);
signal data_out_x12_net: std_logic;
signal data_out_x13_net: std_logic;
signal data_out_x14_net: std_logic;
signal data_out_x15_net: std_logic_vector(8 downto 0);
signal data_out_x16_net: std_logic_vector(8 downto 0);
signal data_out_x17_net: std_logic_vector(8 downto 0);
signal data_out_x18_net: std_logic_vector(8 downto 0);
signal data_out_x19_net: std_logic_vector(8 downto 0);
signal data_out_x1_net: std_logic;
signal data_out_x20_net: std_logic_vector(1 downto 0);
signal data_out_x21_net: std_logic_vector(31 downto 0);
signal data_out_x22_net: std_logic_vector(3 downto 0);
signal data_out_x23_net: std_logic_vector(3 downto 0);
signal data_out_x24_net: std_logic_vector(8 downto 0);
signal data_out_x25_net: std_logic_vector(8 downto 0);
signal data_out_x26_net: std_logic_vector(8 downto 0);
signal data_out_x27_net: std_logic_vector(2 downto 0);
signal data_out_x28_net: std_logic_vector(31 downto 0);
signal data_out_x29_net: std_logic_vector(31 downto 0);
signal data_out_x2_net: std_logic_vector(1 downto 0);
signal data_out_x3_net: std_logic_vector(5 downto 0);
signal data_out_x4_net: std_logic_vector(3 downto 0);
signal data_out_x5_net: std_logic_vector(4 downto 0);
signal data_out_x6_net: std_logic_vector(31 downto 0);
signal data_out_x7_net: std_logic_vector(31 downto 0);
signal data_out_x8_net: std_logic_vector(31 downto 0);
signal data_out_x9_net: std_logic_vector(7 downto 0);
signal dip_switch_net: std_logic_vector(3 downto 0);
signal dout_net: std_logic_vector(17 downto 0);
signal dout_x0_net: std_logic;
signal dout_x10_net: std_logic_vector(3 downto 0);
signal dout_x11_net: std_logic_vector(8 downto 0);
signal dout_x12_net: std_logic;
signal dout_x13_net: std_logic;
signal dout_x14_net: std_logic_vector(8 downto 0);
signal dout_x15_net: std_logic_vector(8 downto 0);
signal dout_x16_net: std_logic_vector(8 downto 0);
signal dout_x17_net: std_logic;
signal dout_x18_net: std_logic_vector(7 downto 0);
signal dout_x19_net: std_logic_vector(7 downto 0);
signal dout_x1_net: std_logic_vector(17 downto 0);
signal dout_x2_net: std_logic_vector(8 downto 0);
signal dout_x3_net: std_logic_vector(3 downto 0);
signal dout_x4_net: std_logic_vector(2 downto 0);
signal dout_x5_net: std_logic_vector(8 downto 0);
signal dout_x6_net: std_logic_vector(1 downto 0);
signal dout_x7_net: std_logic;
signal dout_x8_net: std_logic_vector(8 downto 0);
signal dout_x9_net: std_logic_vector(8 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal en_x10_net: std_logic;
signal en_x11_net: std_logic;
signal en_x12_net: std_logic;
signal en_x13_net: std_logic;
signal en_x14_net: std_logic;
signal en_x15_net: std_logic;
signal en_x16_net: std_logic;
signal en_x17_net: std_logic;
signal en_x18_net: std_logic;
signal en_x19_net: std_logic;
signal en_x1_net: std_logic;
signal en_x20_net: std_logic;
signal en_x21_net: std_logic;
signal en_x22_net: std_logic;
signal en_x23_net: std_logic;
signal en_x2_net: std_logic;
signal en_x3_net: std_logic;
signal en_x4_net: std_logic;
signal en_x5_net: std_logic;
signal en_x6_net: std_logic;
signal en_x7_net: std_logic;
signal en_x8_net: std_logic;
signal en_x9_net: std_logic;
signal leds_net: std_logic_vector(7 downto 0);
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal reset_net: std_logic;
signal resetlcd_net: std_logic;
signal scl_net: std_logic;
signal sdi_net: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(14 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal splb_rst_net: std_logic;
signal trackball_ox_net: std_logic;
signal trackball_oxn_net: std_logic;
signal trackball_oy_net: std_logic;
signal trackball_oyn_net: std_logic;
signal trackball_sel1_net: std_logic;
signal trackball_sel2_net: std_logic;
signal trackball_xscn_net: std_logic;
signal trackball_yscn_net: std_logic;
signal we_net: std_logic;
signal we_x0_net: std_logic;
signal we_x1_net: std_logic;
signal we_x2_net: std_logic;
signal we_x3_net: std_logic;
signal we_x4_net: std_logic;
begin
buttons_big_net <= buttons_big;
buttons_small_net <= buttons_small;
ce_1_sg_x21 <= ce_1;
clk_1_sg_x21 <= clk_1;
data_out_net <= data_out;
data_out_x0_net <= data_out_x0;
data_out_x1_net <= data_out_x1;
data_out_x10_net <= data_out_x10;
data_out_x11_net <= data_out_x11;
data_out_x12_net <= data_out_x12;
data_out_x13_net <= data_out_x13;
data_out_x14_net <= data_out_x14;
data_out_x15_net <= data_out_x15;
data_out_x16_net <= data_out_x16;
data_out_x17_net <= data_out_x17;
data_out_x18_net <= data_out_x18;
data_out_x19_net <= data_out_x19;
data_out_x2_net <= data_out_x2;
data_out_x20_net <= data_out_x20;
data_out_x21_net <= data_out_x21;
data_out_x22_net <= data_out_x22;
data_out_x23_net <= data_out_x23;
data_out_x24_net <= data_out_x24;
data_out_x25_net <= data_out_x25;
data_out_x26_net <= data_out_x26;
data_out_x27_net <= data_out_x27;
data_out_x28_net <= data_out_x28;
data_out_x29_net <= data_out_x29;
data_out_x3_net <= data_out_x3;
data_out_x4_net <= data_out_x4;
data_out_x5_net <= data_out_x5;
data_out_x6_net <= data_out_x6;
data_out_x7_net <= data_out_x7;
data_out_x8_net <= data_out_x8;
data_out_x9_net <= data_out_x9;
dip_switch_net <= dip_switch;
dout_net <= dout;
dout_x0_net <= dout_x0;
dout_x1_net <= dout_x1;
dout_x10_net <= dout_x10;
dout_x11_net <= dout_x11;
dout_x12_net <= dout_x12;
dout_x13_net <= dout_x13;
dout_x14_net <= dout_x14;
dout_x15_net <= dout_x15;
dout_x16_net <= dout_x16;
dout_x17_net <= dout_x17;
dout_x18_net <= dout_x18;
dout_x19_net <= dout_x19;
dout_x2_net <= dout_x2;
dout_x3_net <= dout_x3;
dout_x4_net <= dout_x4;
dout_x5_net <= dout_x5;
dout_x6_net <= dout_x6;
dout_x7_net <= dout_x7;
dout_x8_net <= dout_x8;
dout_x9_net <= dout_x9;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
reset_net <= reset;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
trackball_ox_net <= trackball_ox;
trackball_oxn_net <= trackball_oxn;
trackball_oy_net <= trackball_oy;
trackball_oyn_net <= trackball_oyn;
trackball_sel2_net <= trackball_sel2;
addr <= addr_net;
addr_x0 <= addr_x0_net;
addr_x1 <= addr_x1_net;
addr_x2 <= addr_x2_net;
addr_x3 <= addr_x3_net;
addr_x4 <= addr_x4_net;
buzzer <= buzzer_net;
cs <= cs_net;
data_in <= data_in_net;
data_in_x0 <= data_in_x0_net;
data_in_x1 <= data_in_x1_net;
data_in_x10 <= data_in_x10_net;
data_in_x11 <= data_in_x11_net;
data_in_x12 <= data_in_x12_net;
data_in_x13 <= data_in_x13_net;
data_in_x14 <= data_in_x14_net;
data_in_x15 <= data_in_x15_net;
data_in_x16 <= data_in_x16_net;
data_in_x17 <= data_in_x17_net;
data_in_x18 <= data_in_x18_net;
data_in_x19 <= data_in_x19_net;
data_in_x2 <= data_in_x2_net;
data_in_x20 <= data_in_x20_net;
data_in_x21 <= data_in_x21_net;
data_in_x22 <= data_in_x22_net;
data_in_x23 <= data_in_x23_net;
data_in_x24 <= data_in_x24_net;
data_in_x25 <= data_in_x25_net;
data_in_x26 <= data_in_x26_net;
data_in_x27 <= data_in_x27_net;
data_in_x28 <= data_in_x28_net;
data_in_x29 <= data_in_x29_net;
data_in_x3 <= data_in_x3_net;
data_in_x4 <= data_in_x4_net;
data_in_x5 <= data_in_x5_net;
data_in_x6 <= data_in_x6_net;
data_in_x7 <= data_in_x7_net;
data_in_x8 <= data_in_x8_net;
data_in_x9 <= data_in_x9_net;
en <= en_net;
en_x0 <= en_x0_net;
en_x1 <= en_x1_net;
en_x10 <= en_x10_net;
en_x11 <= en_x11_net;
en_x12 <= en_x12_net;
en_x13 <= en_x13_net;
en_x14 <= en_x14_net;
en_x15 <= en_x15_net;
en_x16 <= en_x16_net;
en_x17 <= en_x17_net;
en_x18 <= en_x18_net;
en_x19 <= en_x19_net;
en_x2 <= en_x2_net;
en_x20 <= en_x20_net;
en_x21 <= en_x21_net;
en_x22 <= en_x22_net;
en_x23 <= en_x23_net;
en_x3 <= en_x3_net;
en_x4 <= en_x4_net;
en_x5 <= en_x5_net;
en_x6 <= en_x6_net;
en_x7 <= en_x7_net;
en_x8 <= en_x8_net;
en_x9 <= en_x9_net;
leds <= leds_net;
resetlcd <= resetlcd_net;
scl <= scl_net;
sdi <= sdi_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x1;
sl_wrdack <= sl_wrdack_x1;
trackball_sel1 <= trackball_sel1_net;
trackball_xscn <= trackball_xscn_net;
trackball_yscn <= trackball_yscn_net;
we <= we_net;
we_x0 <= we_x0_net;
we_x1 <= we_x1_net;
we_x2 <= we_x2_net;
we_x3 <= we_x3_net;
we_x4 <= we_x4_net;
buzzer_controller_063692c849: entity work.buzzer_controller_entity_063692c849
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_net,
from_register1 => data_out_x0_net,
from_register2 => data_out_x1_net,
register9_x0 => buzzer_net
);
edk_processor_94deb4def9: entity work.edk_processor_entity_94deb4def9
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_x2_net,
from_register1 => data_out_x3_net,
from_register2 => data_out_x4_net,
from_register3 => data_out_x5_net,
plb_abus => plb_abus_net,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
sg_plb_addrpref => sg_plb_addrpref_net,
shared_memory => data_out_x6_net,
shared_memory1 => data_out_x7_net,
shared_memory2 => data_out_x8_net,
splb_rst => splb_rst_net,
to_register => dout_net,
to_register1 => dout_x0_net,
to_register10 => dout_x9_net,
to_register11 => dout_x10_net,
to_register12 => dout_x11_net,
to_register13 => dout_x12_net,
to_register14 => dout_x13_net,
to_register15 => dout_x14_net,
to_register16 => dout_x15_net,
to_register17 => dout_x16_net,
to_register18 => dout_x17_net,
to_register19 => dout_x18_net,
to_register2 => dout_x1_net,
to_register20 => dout_x19_net,
to_register3 => dout_x2_net,
to_register4 => dout_x3_net,
to_register5 => dout_x4_net,
to_register6 => dout_x5_net,
to_register7 => dout_x6_net,
to_register8 => dout_x7_net,
to_register9 => dout_x8_net,
constant5_x0 => sl_wait_net,
plb_decode_x0 => sl_addrack_net,
plb_decode_x1 => sl_rdcomp_net,
plb_decode_x2 => sl_wrdack_x1,
plb_decode_x3 => sl_rddack_net,
plb_decode_x4 => sl_rddbus_net,
plb_memmap_x0 => data_in_net,
plb_memmap_x1 => en_net,
plb_memmap_x10 => data_in_x4_net,
plb_memmap_x11 => en_x4_net,
plb_memmap_x12 => data_in_x5_net,
plb_memmap_x13 => en_x5_net,
plb_memmap_x14 => data_in_x6_net,
plb_memmap_x15 => en_x6_net,
plb_memmap_x16 => data_in_x7_net,
plb_memmap_x17 => en_x7_net,
plb_memmap_x18 => data_in_x8_net,
plb_memmap_x19 => en_x8_net,
plb_memmap_x2 => data_in_x0_net,
plb_memmap_x20 => data_in_x9_net,
plb_memmap_x21 => en_x9_net,
plb_memmap_x22 => data_in_x10_net,
plb_memmap_x23 => en_x10_net,
plb_memmap_x24 => data_in_x11_net,
plb_memmap_x25 => en_x11_net,
plb_memmap_x26 => data_in_x12_net,
plb_memmap_x27 => en_x12_net,
plb_memmap_x28 => data_in_x13_net,
plb_memmap_x29 => en_x13_net,
plb_memmap_x3 => en_x0_net,
plb_memmap_x30 => data_in_x14_net,
plb_memmap_x31 => en_x14_net,
plb_memmap_x32 => data_in_x15_net,
plb_memmap_x33 => en_x15_net,
plb_memmap_x34 => data_in_x16_net,
plb_memmap_x35 => en_x16_net,
plb_memmap_x36 => data_in_x17_net,
plb_memmap_x37 => en_x17_net,
plb_memmap_x38 => data_in_x18_net,
plb_memmap_x39 => en_x18_net,
plb_memmap_x4 => data_in_x1_net,
plb_memmap_x40 => data_in_x19_net,
plb_memmap_x41 => en_x19_net,
plb_memmap_x42 => addr_net,
plb_memmap_x43 => data_in_x20_net,
plb_memmap_x44 => we_net,
plb_memmap_x45 => addr_x0_net,
plb_memmap_x46 => data_in_x21_net,
plb_memmap_x47 => we_x0_net,
plb_memmap_x48 => addr_x1_net,
plb_memmap_x49 => data_in_x22_net,
plb_memmap_x5 => en_x1_net,
plb_memmap_x50 => we_x1_net,
plb_memmap_x6 => data_in_x2_net,
plb_memmap_x7 => en_x2_net,
plb_memmap_x8 => data_in_x3_net,
plb_memmap_x9 => en_x3_net
);
lcd_controller_e3a358fc2f: entity work.lcd_controller_entity_e3a358fc2f
port map (
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
from_register => data_out_x10_net,
from_register1 => data_out_x15_net,
from_register1_x0 => data_out_x24_net,
from_register2 => data_out_x16_net,
from_register2_x0 => data_out_x25_net,
from_register3 => data_out_x17_net,
from_register3_x0 => data_out_x26_net,
from_register3_x1 => data_out_x11_net,
from_register4 => data_out_x18_net,
from_register4_x0 => data_out_x27_net,
from_register4_x1 => data_out_x12_net,
from_register5 => data_out_x19_net,
from_register5_x0 => data_out_x23_net,
from_register5_x1 => data_out_x13_net,
from_register6 => data_out_x20_net,
from_register6_x0 => data_out_x14_net,
from_register7 => data_out_x22_net,
reset => reset_net,
shared_memory => data_out_x21_net,
shared_memory_x0 => data_out_x28_net,
shared_memory_x1 => data_out_x29_net,
commandrom => addr_x2_net,
commandrom_x0 => data_in_x27_net,
commandrom_x1 => we_x2_net,
datarom => addr_x3_net,
datarom_x0 => data_in_x28_net,
datarom_x1 => we_x3_net,
datarom_x2 => addr_x4_net,
datarom_x3 => data_in_x29_net,
datarom_x4 => we_x4_net,
delay_x0 => resetlcd_net,
spi => sdi_net,
spi_x0 => cs_net,
spi_x1 => scl_net
);
o_1f30dfdbf5: entity work.o_entity_1f30dfdbf5
port map (
buttons_big => buttons_big_net,
buttons_small => buttons_small_net,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
dip_switch => dip_switch_net,
from_register => data_out_x9_net,
trackball_ox => trackball_ox_net,
trackball_oxn => trackball_oxn_net,
trackball_oy => trackball_oy_net,
trackball_oyn => trackball_oyn_net,
trackball_sel2 => trackball_sel2_net,
concat_x0 => data_in_x23_net,
constant2_x0 => en_x21_net,
constant4_x0 => en_x22_net,
constant6_x0 => en_x23_net,
constant_x1 => en_x20_net,
register10_x0 => trackball_xscn_net,
register11_x0 => trackball_yscn_net,
register12_x0 => trackball_sel1_net,
register3_x0 => data_in_x24_net,
register5_x0 => data_in_x25_net,
register7_x0 => data_in_x26_net,
register9_x0 => leds_net
);
end structural;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;
entity xlclkprobe is
port (clk : in std_logic;
clr : in std_logic;
ce : in std_logic;
fakeOutForXst : out std_logic);
end xlclkprobe;
architecture behavior of xlclkprobe is
begin
fakeOutForXst <= '0';
-- synopsys translate_off
work.clock_pkg.int_clk <= clk;
-- synopsys translate_on
end behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
end generate;
end architecture behavior;
-------------------------------------------------------------------
-- System Generator version 10.1.2 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xland2 is
port (
a : in std_logic;
b : in std_logic;
dout : out std_logic
);
end xland2;
architecture behavior of xland2 is
begin
dout <= a and b;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
clk_1: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
clk_1 <= xlclockdriver_1_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
clk => xlclockdriver_1_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity user_io_board_controller_cw is
port (
buttons_big: in std_logic_vector(1 downto 0);
buttons_small: in std_logic_vector(5 downto 0);
ce: in std_logic := '1';
clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz)
dip_switch: in std_logic_vector(3 downto 0);
plb_abus: in std_logic_vector(31 downto 0);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(31 downto 0);
reset: in std_logic;
sg_plb_addrpref: in std_logic_vector(14 downto 0);
splb_rst: in std_logic;
trackball_ox: in std_logic;
trackball_oxn: in std_logic;
trackball_oy: in std_logic;
trackball_oyn: in std_logic;
trackball_sel2: in std_logic;
buzzer: out std_logic;
cs: out std_logic;
leds: out std_logic_vector(7 downto 0);
resetlcd: out std_logic;
scl: out std_logic;
sdi: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(31 downto 0);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
trackball_sel1: out std_logic;
trackball_xscn: out std_logic;
trackball_yscn: out std_logic
);
end user_io_board_controller_cw;
architecture structural of user_io_board_controller_cw is
component dual_port_block_memory_virtex2p_6_3_25371f622c89ba44
port (
addra: in std_logic_vector(8 downto 0);
addrb: in std_logic_vector(8 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(31 downto 0);
dinb: in std_logic_vector(31 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic;
web: in std_logic;
douta: out std_logic_vector(31 downto 0);
doutb: out std_logic_vector(31 downto 0)
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is true;
attribute box_type: string;
attribute box_type of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is true;
attribute optimize_primitives of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is false;
attribute dont_touch of dual_port_block_memory_virtex2p_6_3_25371f622c89ba44: component is true;
component dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76
port (
addra: in std_logic_vector(11 downto 0);
addrb: in std_logic_vector(11 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(31 downto 0);
dinb: in std_logic_vector(31 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic;
web: in std_logic;
douta: out std_logic_vector(31 downto 0);
doutb: out std_logic_vector(31 downto 0)
);
end component;
attribute syn_black_box of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is true;
attribute box_type of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is "black_box";
attribute syn_noprune of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is true;
attribute optimize_primitives of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is false;
attribute dont_touch of dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76: component is true;
component dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8
port (
addra: in std_logic_vector(7 downto 0);
addrb: in std_logic_vector(7 downto 0);
clka: in std_logic;
clkb: in std_logic;
dina: in std_logic_vector(31 downto 0);
dinb: in std_logic_vector(31 downto 0);
ena: in std_logic;
enb: in std_logic;
wea: in std_logic;
web: in std_logic;
douta: out std_logic_vector(31 downto 0);
doutb: out std_logic_vector(31 downto 0)
);
end component;
attribute syn_black_box of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is true;
attribute box_type of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is "black_box";
attribute syn_noprune of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is true;
attribute optimize_primitives of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is false;
attribute dont_touch of dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8: component is true;
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal Buttons_Big_reg_ce: std_logic;
signal Buttons_Small_reg_ce: std_logic;
signal Buzzer_DutyCycle_reg_ce: std_logic;
signal Buzzer_Enable_reg_ce: std_logic;
signal Buzzer_Period_reg_ce: std_logic;
signal DIP_Switch_reg_ce: std_logic;
signal LCD_BackgroundColor_reg_ce: std_logic;
signal LCD_CharacterOffset_reg_ce: std_logic;
signal LCD_CharactersSelect_reg_ce: std_logic;
signal LCD_ColSet_reg_ce: std_logic;
signal LCD_ConfigLocation_reg_ce: std_logic;
signal LCD_DividerSelect_reg_ce: std_logic;
signal LCD_FirstEnd_reg_ce: std_logic;
signal LCD_FirstStart_reg_ce: std_logic;
signal LCD_LineOffset_reg_ce: std_logic;
signal LCD_RamWrite_reg_ce: std_logic;
signal LCD_ResetLCD_reg_ce: std_logic;
signal LCD_Reset_reg_ce: std_logic;
signal LCD_RowSet_reg_ce: std_logic;
signal LCD_SecondEnd_reg_ce: std_logic;
signal LCD_SecondStart_reg_ce: std_logic;
signal LCD_Send_reg_ce: std_logic;
signal LCD_TotalCmdTransfer_reg_ce: std_logic;
signal LEDs_reg_ce: std_logic;
signal Trackball_reg_ce: std_logic;
signal addr_net: std_logic_vector(11 downto 0);
signal addr_x0_net: std_logic_vector(8 downto 0);
signal addr_x1_net: std_logic_vector(7 downto 0);
signal addr_x2_net: std_logic_vector(7 downto 0);
signal addr_x3_net: std_logic_vector(8 downto 0);
signal addr_x4_net: std_logic_vector(11 downto 0);
signal buttons_big_net: std_logic_vector(1 downto 0);
signal buttons_small_net: std_logic_vector(5 downto 0);
signal buzzer_net: std_logic;
signal ce_1_sg_x21: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_1_sg_x21: signal is "REDUCE";
signal clkNet: std_logic;
signal clk_1_sg_x21: std_logic;
signal cs_net: std_logic;
signal data_in_net: std_logic_vector(17 downto 0);
signal data_in_x0_net: std_logic;
signal data_in_x10_net: std_logic_vector(3 downto 0);
signal data_in_x11_net: std_logic_vector(8 downto 0);
signal data_in_x12_net: std_logic;
signal data_in_x13_net: std_logic;
signal data_in_x14_net: std_logic_vector(8 downto 0);
signal data_in_x15_net: std_logic_vector(8 downto 0);
signal data_in_x16_net: std_logic_vector(8 downto 0);
signal data_in_x17_net: std_logic;
signal data_in_x18_net: std_logic_vector(7 downto 0);
signal data_in_x19_net: std_logic_vector(7 downto 0);
signal data_in_x1_net: std_logic_vector(17 downto 0);
signal data_in_x20_net: std_logic_vector(31 downto 0);
signal data_in_x21_net: std_logic_vector(31 downto 0);
signal data_in_x22_net: std_logic_vector(31 downto 0);
signal data_in_x23_net: std_logic_vector(4 downto 0);
signal data_in_x24_net: std_logic_vector(1 downto 0);
signal data_in_x25_net: std_logic_vector(5 downto 0);
signal data_in_x26_net: std_logic_vector(3 downto 0);
signal data_in_x27_net: std_logic_vector(31 downto 0);
signal data_in_x28_net: std_logic_vector(31 downto 0);
signal data_in_x29_net: std_logic_vector(31 downto 0);
signal data_in_x2_net: std_logic_vector(8 downto 0);
signal data_in_x3_net: std_logic_vector(3 downto 0);
signal data_in_x4_net: std_logic_vector(2 downto 0);
signal data_in_x5_net: std_logic_vector(8 downto 0);
signal data_in_x6_net: std_logic_vector(1 downto 0);
signal data_in_x7_net: std_logic;
signal data_in_x8_net: std_logic_vector(8 downto 0);
signal data_in_x9_net: std_logic_vector(8 downto 0);
signal data_out_net: std_logic_vector(17 downto 0);
signal data_out_x0_net: std_logic_vector(17 downto 0);
signal data_out_x10_net: std_logic;
signal data_out_x11_net: std_logic_vector(7 downto 0);
signal data_out_x12_net: std_logic;
signal data_out_x13_net: std_logic;
signal data_out_x14_net: std_logic;
signal data_out_x15_net: std_logic_vector(8 downto 0);
signal data_out_x16_net: std_logic_vector(8 downto 0);
signal data_out_x17_net: std_logic_vector(8 downto 0);
signal data_out_x18_net: std_logic_vector(8 downto 0);
signal data_out_x19_net: std_logic_vector(8 downto 0);
signal data_out_x1_net: std_logic;
signal data_out_x20_net: std_logic_vector(1 downto 0);
signal data_out_x21_net: std_logic_vector(31 downto 0);
signal data_out_x22_net: std_logic_vector(3 downto 0);
signal data_out_x23_net: std_logic_vector(3 downto 0);
signal data_out_x24_net: std_logic_vector(8 downto 0);
signal data_out_x25_net: std_logic_vector(8 downto 0);
signal data_out_x26_net: std_logic_vector(8 downto 0);
signal data_out_x27_net: std_logic_vector(2 downto 0);
signal data_out_x28_net: std_logic_vector(31 downto 0);
signal data_out_x29_net: std_logic_vector(31 downto 0);
signal data_out_x2_net: std_logic_vector(1 downto 0);
signal data_out_x3_net: std_logic_vector(5 downto 0);
signal data_out_x4_net: std_logic_vector(3 downto 0);
signal data_out_x5_net: std_logic_vector(4 downto 0);
signal data_out_x6_net: std_logic_vector(31 downto 0);
signal data_out_x7_net: std_logic_vector(31 downto 0);
signal data_out_x8_net: std_logic_vector(31 downto 0);
signal data_out_x9_net: std_logic_vector(7 downto 0);
signal dip_switch_net: std_logic_vector(3 downto 0);
signal en_net: std_logic;
signal en_x0_net: std_logic;
signal en_x10_net: std_logic;
signal en_x11_net: std_logic;
signal en_x12_net: std_logic;
signal en_x13_net: std_logic;
signal en_x14_net: std_logic;
signal en_x15_net: std_logic;
signal en_x16_net: std_logic;
signal en_x17_net: std_logic;
signal en_x18_net: std_logic;
signal en_x19_net: std_logic;
signal en_x1_net: std_logic;
signal en_x20_net: std_logic;
signal en_x21_net: std_logic;
signal en_x22_net: std_logic;
signal en_x23_net: std_logic;
signal en_x2_net: std_logic;
signal en_x3_net: std_logic;
signal en_x4_net: std_logic;
signal en_x5_net: std_logic;
signal en_x6_net: std_logic;
signal en_x7_net: std_logic;
signal en_x8_net: std_logic;
signal en_x9_net: std_logic;
signal leds_net: std_logic_vector(7 downto 0);
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal plb_abus_net: std_logic_vector(31 downto 0);
signal plb_pavalid_net: std_logic;
signal plb_rnw_net: std_logic;
signal plb_wrdbus_net: std_logic_vector(31 downto 0);
signal reset_net: std_logic;
signal resetlcd_net: std_logic;
signal scl_net: std_logic;
signal sdi_net: std_logic;
signal sg_plb_addrpref_net: std_logic_vector(14 downto 0);
signal sl_addrack_net: std_logic;
signal sl_rdcomp_net: std_logic;
signal sl_rddack_net: std_logic;
signal sl_rddbus_net: std_logic_vector(31 downto 0);
signal sl_wait_net: std_logic;
signal sl_wrdack_x1: std_logic;
signal sl_wrdack_x2: std_logic;
signal splb_rst_net: std_logic;
signal trackball_ox_net: std_logic;
signal trackball_oxn_net: std_logic;
signal trackball_oy_net: std_logic;
signal trackball_oyn_net: std_logic;
signal trackball_sel1_net: std_logic;
signal trackball_sel2_net: std_logic;
signal trackball_xscn_net: std_logic;
signal trackball_yscn_net: std_logic;
signal we_net: std_logic;
signal we_x0_net: std_logic;
signal we_x1_net: std_logic;
signal we_x2_net: std_logic;
signal we_x3_net: std_logic;
signal we_x4_net: std_logic;
begin
buttons_big_net <= buttons_big;
buttons_small_net <= buttons_small;
clkNet <= clk;
dip_switch_net <= dip_switch;
plb_abus_net <= plb_abus;
plb_pavalid_net <= plb_pavalid;
plb_rnw_net <= plb_rnw;
plb_wrdbus_net <= plb_wrdbus;
reset_net <= reset;
sg_plb_addrpref_net <= sg_plb_addrpref;
splb_rst_net <= splb_rst;
trackball_ox_net <= trackball_ox;
trackball_oxn_net <= trackball_oxn;
trackball_oy_net <= trackball_oy;
trackball_oyn_net <= trackball_oyn;
trackball_sel2_net <= trackball_sel2;
buzzer <= buzzer_net;
cs <= cs_net;
leds <= leds_net;
resetlcd <= resetlcd_net;
scl <= scl_net;
sdi <= sdi_net;
sl_addrack <= sl_addrack_net;
sl_rdcomp <= sl_rdcomp_net;
sl_rddack <= sl_rddack_net;
sl_rddbus <= sl_rddbus_net;
sl_wait <= sl_wait_net;
sl_wrcomp <= sl_wrdack_x2;
sl_wrdack <= sl_wrdack_x1;
trackball_sel1 <= trackball_sel1_net;
trackball_xscn <= trackball_xscn_net;
trackball_yscn <= trackball_yscn_net;
Buttons_Big_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x21_net,
dout => Buttons_Big_reg_ce
);
Buttons_Big_x0: entity work.synth_reg_w_init
generic map (
width => 2,
init_index => 2,
init_value => b"00",
latency => 1
)
port map (
ce => Buttons_Big_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x24_net,
o => data_out_x2_net
);
Buttons_Small_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x22_net,
dout => Buttons_Small_reg_ce
);
Buttons_Small_x0: entity work.synth_reg_w_init
generic map (
width => 6,
init_index => 2,
init_value => b"000000",
latency => 1
)
port map (
ce => Buttons_Small_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x25_net,
o => data_out_x3_net
);
Buzzer_DutyCycle: entity work.synth_reg_w_init
generic map (
width => 18,
init_index => 2,
init_value => b"000000000000000000",
latency => 1
)
port map (
ce => Buzzer_DutyCycle_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_net,
o => data_out_x0_net
);
Buzzer_DutyCycle_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_net,
dout => Buzzer_DutyCycle_reg_ce
);
Buzzer_Enable: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => Buzzer_Enable_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x0_net,
o(0) => data_out_x1_net
);
Buzzer_Enable_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x0_net,
dout => Buzzer_Enable_reg_ce
);
Buzzer_Period: entity work.synth_reg_w_init
generic map (
width => 18,
init_index => 2,
init_value => b"000000000000000000",
latency => 1
)
port map (
ce => Buzzer_Period_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x1_net,
o => data_out_net
);
Buzzer_Period_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x1_net,
dout => Buzzer_Period_reg_ce
);
DIP_Switch_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x23_net,
dout => DIP_Switch_reg_ce
);
DIP_Switch_x0: entity work.synth_reg_w_init
generic map (
width => 4,
init_index => 2,
init_value => b"0000",
latency => 1
)
port map (
ce => DIP_Switch_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x26_net,
o => data_out_x4_net
);
LCD_BackgroundColor: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_BackgroundColor_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x2_net,
o => data_out_x17_net
);
LCD_BackgroundColor_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x2_net,
dout => LCD_BackgroundColor_reg_ce
);
LCD_CharacterMap: dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76
port map (
addra => addr_x4_net,
addrb => addr_net,
clka => clk_1_sg_x21,
clkb => clk_1_sg_x21,
dina => data_in_x29_net,
dinb => data_in_x20_net,
ena => ce_1_sg_x21,
enb => ce_1_sg_x21,
wea => we_x4_net,
web => we_net,
douta => data_out_x29_net,
doutb => data_out_x6_net
);
LCD_CharacterOffset: entity work.synth_reg_w_init
generic map (
width => 4,
init_index => 2,
init_value => b"0000",
latency => 1
)
port map (
ce => LCD_CharacterOffset_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x3_net,
o => data_out_x23_net
);
LCD_CharacterOffset_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x3_net,
dout => LCD_CharacterOffset_reg_ce
);
LCD_Characters: dual_port_block_memory_virtex2p_6_3_25371f622c89ba44
port map (
addra => addr_x3_net,
addrb => addr_x0_net,
clka => clk_1_sg_x21,
clkb => clk_1_sg_x21,
dina => data_in_x28_net,
dinb => data_in_x21_net,
ena => ce_1_sg_x21,
enb => ce_1_sg_x21,
wea => we_x3_net,
web => we_x0_net,
douta => data_out_x28_net,
doutb => data_out_x7_net
);
LCD_CharactersSelect: entity work.synth_reg_w_init
generic map (
width => 3,
init_index => 2,
init_value => b"000",
latency => 1
)
port map (
ce => LCD_CharactersSelect_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x4_net,
o => data_out_x27_net
);
LCD_CharactersSelect_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x4_net,
dout => LCD_CharactersSelect_reg_ce
);
LCD_ColSet: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_ColSet_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x5_net,
o => data_out_x24_net
);
LCD_ColSet_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x5_net,
dout => LCD_ColSet_reg_ce
);
LCD_Commands: dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8
port map (
addra => addr_x2_net,
addrb => addr_x1_net,
clka => clk_1_sg_x21,
clkb => clk_1_sg_x21,
dina => data_in_x27_net,
dinb => data_in_x22_net,
ena => ce_1_sg_x21,
enb => ce_1_sg_x21,
wea => we_x2_net,
web => we_x1_net,
douta => data_out_x21_net,
doutb => data_out_x8_net
);
LCD_ConfigLocation: entity work.synth_reg_w_init
generic map (
width => 2,
init_index => 2,
init_value => b"00",
latency => 1
)
port map (
ce => LCD_ConfigLocation_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x6_net,
o => data_out_x20_net
);
LCD_ConfigLocation_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x6_net,
dout => LCD_ConfigLocation_reg_ce
);
LCD_DividerSelect: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_DividerSelect_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x7_net,
o(0) => data_out_x12_net
);
LCD_DividerSelect_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x7_net,
dout => LCD_DividerSelect_reg_ce
);
LCD_FirstEnd: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_FirstEnd_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x8_net,
o => data_out_x16_net
);
LCD_FirstEnd_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x8_net,
dout => LCD_FirstEnd_reg_ce
);
LCD_FirstStart: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_FirstStart_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x9_net,
o => data_out_x15_net
);
LCD_FirstStart_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x9_net,
dout => LCD_FirstStart_reg_ce
);
LCD_LineOffset: entity work.synth_reg_w_init
generic map (
width => 4,
init_index => 2,
init_value => b"0000",
latency => 1
)
port map (
ce => LCD_LineOffset_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x10_net,
o => data_out_x22_net
);
LCD_LineOffset_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x10_net,
dout => LCD_LineOffset_reg_ce
);
LCD_RamWrite: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_RamWrite_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x11_net,
o => data_out_x25_net
);
LCD_RamWrite_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x11_net,
dout => LCD_RamWrite_reg_ce
);
LCD_Reset: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_Reset_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x12_net,
o(0) => data_out_x10_net
);
LCD_ResetLCD: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_ResetLCD_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x13_net,
o(0) => data_out_x14_net
);
LCD_ResetLCD_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x13_net,
dout => LCD_ResetLCD_reg_ce
);
LCD_Reset_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x12_net,
dout => LCD_Reset_reg_ce
);
LCD_RowSet: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_RowSet_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x14_net,
o => data_out_x26_net
);
LCD_RowSet_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x14_net,
dout => LCD_RowSet_reg_ce
);
LCD_SecondEnd: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_SecondEnd_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x15_net,
o => data_out_x19_net
);
LCD_SecondEnd_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x15_net,
dout => LCD_SecondEnd_reg_ce
);
LCD_SecondStart: entity work.synth_reg_w_init
generic map (
width => 9,
init_index => 2,
init_value => b"000000000",
latency => 1
)
port map (
ce => LCD_SecondStart_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x16_net,
o => data_out_x18_net
);
LCD_SecondStart_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x16_net,
dout => LCD_SecondStart_reg_ce
);
LCD_Send: entity work.synth_reg_w_init
generic map (
width => 1,
init_index => 2,
init_value => b"0",
latency => 1
)
port map (
ce => LCD_Send_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i(0) => data_in_x17_net,
o(0) => data_out_x13_net
);
LCD_Send_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x17_net,
dout => LCD_Send_reg_ce
);
LCD_TotalCmdTransfer: entity work.synth_reg_w_init
generic map (
width => 8,
init_index => 2,
init_value => b"00000000",
latency => 1
)
port map (
ce => LCD_TotalCmdTransfer_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x18_net,
o => data_out_x11_net
);
LCD_TotalCmdTransfer_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x18_net,
dout => LCD_TotalCmdTransfer_reg_ce
);
LEDs_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x19_net,
dout => LEDs_reg_ce
);
LEDs_x0: entity work.synth_reg_w_init
generic map (
width => 8,
init_index => 2,
init_value => b"00000000",
latency => 1
)
port map (
ce => LEDs_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x19_net,
o => data_out_x9_net
);
Trackball: entity work.synth_reg_w_init
generic map (
width => 5,
init_index => 2,
init_value => b"00000",
latency => 1
)
port map (
ce => Trackball_reg_ce,
clk => clk_1_sg_x21,
clr => '0',
i => data_in_x23_net,
o => data_out_x5_net
);
Trackball_ce_and2_comp: entity work.xland2
port map (
a => ce_1_sg_x21,
b => en_x20_net,
dout => Trackball_reg_ce
);
clk_probe: entity work.xlclkprobe
port map (
ce => '1',
clk => clkNet,
clr => '0'
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => '0',
sysclk => clkNet,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
user_io_board_controller_x0: entity work.user_io_board_controller
port map (
buttons_big => buttons_big_net,
buttons_small => buttons_small_net,
ce_1 => ce_1_sg_x21,
clk_1 => clk_1_sg_x21,
data_out => data_out_net,
data_out_x0 => data_out_x0_net,
data_out_x1 => data_out_x1_net,
data_out_x10 => data_out_x10_net,
data_out_x11 => data_out_x11_net,
data_out_x12 => data_out_x12_net,
data_out_x13 => data_out_x13_net,
data_out_x14 => data_out_x14_net,
data_out_x15 => data_out_x15_net,
data_out_x16 => data_out_x16_net,
data_out_x17 => data_out_x17_net,
data_out_x18 => data_out_x18_net,
data_out_x19 => data_out_x19_net,
data_out_x2 => data_out_x2_net,
data_out_x20 => data_out_x20_net,
data_out_x21 => data_out_x21_net,
data_out_x22 => data_out_x22_net,
data_out_x23 => data_out_x23_net,
data_out_x24 => data_out_x24_net,
data_out_x25 => data_out_x25_net,
data_out_x26 => data_out_x26_net,
data_out_x27 => data_out_x27_net,
data_out_x28 => data_out_x28_net,
data_out_x29 => data_out_x29_net,
data_out_x3 => data_out_x3_net,
data_out_x4 => data_out_x4_net,
data_out_x5 => data_out_x5_net,
data_out_x6 => data_out_x6_net,
data_out_x7 => data_out_x7_net,
data_out_x8 => data_out_x8_net,
data_out_x9 => data_out_x9_net,
dip_switch => dip_switch_net,
dout => data_out_x0_net,
dout_x0 => data_out_x1_net,
dout_x1 => data_out_net,
dout_x10 => data_out_x22_net,
dout_x11 => data_out_x25_net,
dout_x12 => data_out_x10_net,
dout_x13 => data_out_x14_net,
dout_x14 => data_out_x26_net,
dout_x15 => data_out_x19_net,
dout_x16 => data_out_x18_net,
dout_x17 => data_out_x13_net,
dout_x18 => data_out_x11_net,
dout_x19 => data_out_x9_net,
dout_x2 => data_out_x17_net,
dout_x3 => data_out_x23_net,
dout_x4 => data_out_x27_net,
dout_x5 => data_out_x24_net,
dout_x6 => data_out_x20_net,
dout_x7 => data_out_x12_net,
dout_x8 => data_out_x16_net,
dout_x9 => data_out_x15_net,
plb_abus => plb_abus_net,
plb_pavalid => plb_pavalid_net,
plb_rnw => plb_rnw_net,
plb_wrdbus => plb_wrdbus_net,
reset => reset_net,
sg_plb_addrpref => sg_plb_addrpref_net,
splb_rst => splb_rst_net,
trackball_ox => trackball_ox_net,
trackball_oxn => trackball_oxn_net,
trackball_oy => trackball_oy_net,
trackball_oyn => trackball_oyn_net,
trackball_sel2 => trackball_sel2_net,
addr => addr_net,
addr_x0 => addr_x0_net,
addr_x1 => addr_x1_net,
addr_x2 => addr_x2_net,
addr_x3 => addr_x3_net,
addr_x4 => addr_x4_net,
buzzer => buzzer_net,
cs => cs_net,
data_in => data_in_net,
data_in_x0 => data_in_x0_net,
data_in_x1 => data_in_x1_net,
data_in_x10 => data_in_x10_net,
data_in_x11 => data_in_x11_net,
data_in_x12 => data_in_x12_net,
data_in_x13 => data_in_x13_net,
data_in_x14 => data_in_x14_net,
data_in_x15 => data_in_x15_net,
data_in_x16 => data_in_x16_net,
data_in_x17 => data_in_x17_net,
data_in_x18 => data_in_x18_net,
data_in_x19 => data_in_x19_net,
data_in_x2 => data_in_x2_net,
data_in_x20 => data_in_x20_net,
data_in_x21 => data_in_x21_net,
data_in_x22 => data_in_x22_net,
data_in_x23 => data_in_x23_net,
data_in_x24 => data_in_x24_net,
data_in_x25 => data_in_x25_net,
data_in_x26 => data_in_x26_net,
data_in_x27 => data_in_x27_net,
data_in_x28 => data_in_x28_net,
data_in_x29 => data_in_x29_net,
data_in_x3 => data_in_x3_net,
data_in_x4 => data_in_x4_net,
data_in_x5 => data_in_x5_net,
data_in_x6 => data_in_x6_net,
data_in_x7 => data_in_x7_net,
data_in_x8 => data_in_x8_net,
data_in_x9 => data_in_x9_net,
en => en_net,
en_x0 => en_x0_net,
en_x1 => en_x1_net,
en_x10 => en_x10_net,
en_x11 => en_x11_net,
en_x12 => en_x12_net,
en_x13 => en_x13_net,
en_x14 => en_x14_net,
en_x15 => en_x15_net,
en_x16 => en_x16_net,
en_x17 => en_x17_net,
en_x18 => en_x18_net,
en_x19 => en_x19_net,
en_x2 => en_x2_net,
en_x20 => en_x20_net,
en_x21 => en_x21_net,
en_x22 => en_x22_net,
en_x23 => en_x23_net,
en_x3 => en_x3_net,
en_x4 => en_x4_net,
en_x5 => en_x5_net,
en_x6 => en_x6_net,
en_x7 => en_x7_net,
en_x8 => en_x8_net,
en_x9 => en_x9_net,
leds => leds_net,
resetlcd => resetlcd_net,
scl => scl_net,
sdi => sdi_net,
sl_addrack => sl_addrack_net,
sl_rdcomp => sl_rdcomp_net,
sl_rddack => sl_rddack_net,
sl_rddbus => sl_rddbus_net,
sl_wait => sl_wait_net,
sl_wrcomp => sl_wrdack_x2,
sl_wrdack => sl_wrdack_x1,
trackball_sel1 => trackball_sel1_net,
trackball_xscn => trackball_xscn_net,
trackball_yscn => trackball_yscn_net,
we => we_net,
we_x0 => we_x0_net,
we_x1 => we_x1_net,
we_x2 => we_x2_net,
we_x3 => we_x3_net,
we_x4 => we_x4_net
);
end structural;
| bsd-2-clause | 22a04ef84e42bacc39da492c14399ce6 | 0.604473 | 3.047177 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo_generator_v10_0_pkg.vhd | 9 | 129,958 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 94464)
`protect data_block
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`protect end_protected
| gpl-3.0 | 28e501d86ff7bca588a3bb14be9bd375 | 0.954085 | 1.810353 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_decoder.vhd | 7 | 1,660 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
| mit | 237e2674b734530a182ffa76376ef249 | 0.705422 | 3.472803 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/Gray_Processing_GN_Gray_Processing_Gray_Processing_Module.vhd | 2 | 29,196 | -- Gray_Processing_GN_Gray_Processing_Gray_Processing_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.11:11:33
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Processing_GN_Gray_Processing_Gray_Processing_Module is
port (
data_out : out std_logic_vector(23 downto 0); -- data_out.wire
sop : in std_logic := '0'; -- sop.wire
eop : in std_logic := '0'; -- eop.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
data_in : in std_logic_vector(23 downto 0) := (others => '0') -- data_in.wire
);
end entity Gray_Processing_GN_Gray_Processing_Gray_Processing_Module;
architecture rtl of Gray_Processing_GN_Gray_Processing_Gray_Processing_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNKXX25S2S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKXX25S2S;
component alt_dspbuilder_cast_GN6OMCQQS7 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN6OMCQQS7;
component alt_dspbuilder_cast_GN7IAAYCSZ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7IAAYCSZ;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
a : in std_logic_vector(WIDTH-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
direction : in std_logic := 'X'; -- wire
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
r : out std_logic_vector(WIDTH-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic (
family : string := "Stratix";
direction : string := "AddAdd";
data3b_const : string := "00000000";
data2b_const : string := "00000000";
representation : string := "SIGNED";
dataWidth : integer := 8;
data4b_const : string := "00000000";
number_multipliers : integer := 2;
pipeline_register : string := "NoRegister";
use_dedicated_circuitry : integer := 0;
data1b_const : string := "00000000";
use_b_consts : natural := 0
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data1a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data2a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data3a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(17 downto 0); -- wire
user_aclr : in std_logic := 'X'; -- wire
ena : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiply_add_GNKLXFKAO3;
component alt_dspbuilder_multiplexer_GNCALBUTDR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNCALBUTDR;
component alt_dspbuilder_cast_GNJGR7GQ2L is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(17 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNJGR7GQ2L;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_if_statement_GN7VA7SRUP is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GN7VA7SRUP;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_constant_GNPXZ5JSVR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNPXZ5JSVR;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_cast_GNSB3OXIQS is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_cast_GNSB3OXIQS;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
signal barrel_shifteruser_aclrgnd_output_wire : std_logic; -- Barrel_Shifteruser_aclrGND:output -> Barrel_Shifter:user_aclr
signal barrel_shifterenavcc_output_wire : std_logic; -- Barrel_ShifterenaVCC:output -> Barrel_Shifter:ena
signal multiply_adduser_aclrgnd_output_wire : std_logic; -- Multiply_Adduser_aclrGND:output -> Multiply_Add:user_aclr
signal multiply_addenavcc_output_wire : std_logic; -- Multiply_AddenaVCC:output -> Multiply_Add:ena
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay2enavcc_output_wire : std_logic; -- Delay2enaVCC:output -> Delay2:ena
signal bus_concatenation_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation:output -> Bus_Concatenation1:b
signal barrel_shifter_r_wire : std_logic_vector(17 downto 0); -- Barrel_Shifter:r -> Bus_Conversion:input
signal bus_conversion_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion:output -> [Bus_Concatenation1:a, Bus_Concatenation:a, Bus_Concatenation:b]
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Bus_Conversion1:input, Bus_Conversion2:input, Bus_Conversion3:input, If_Statement1:a, Multiplexer:in0]
signal constant1_output_wire : std_logic_vector(3 downto 0); -- Constant1:output -> Barrel_Shifter:distance
signal delay2_output_wire : std_logic_vector(0 downto 0); -- Delay2:output -> [Delay:input, cast1:input]
signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0
signal sop_0_output_wire : std_logic; -- sop_0:output -> Logical_Bit_Operator:data1
signal eop_0_output_wire : std_logic; -- eop_0:output -> Logical_Bit_Operator1:data0
signal delay_output_wire : std_logic_vector(0 downto 0); -- Delay:output -> [Multiplexer:sel, cast3:input]
signal bus_concatenation1_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation1:output -> Multiplexer:in1
signal bus_conversion3_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion3:output -> Multiply_Add:data1a
signal bus_conversion2_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion2:output -> Multiply_Add:data2a
signal bus_conversion1_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion1:output -> Multiply_Add:data3a
signal multiply_add_result_wire : std_logic_vector(17 downto 0); -- Multiply_Add:result -> Barrel_Shifter:a
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> data_out_0:input
signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> cast0:input
signal cast0_output_wire : std_logic; -- cast0:output -> Delay:sclr
signal cast1_output_wire : std_logic; -- cast1:output -> Delay:ena
signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> cast2:input
signal cast2_output_wire : std_logic_vector(0 downto 0); -- cast2:output -> Delay2:input
signal cast3_output_wire : std_logic; -- cast3:output -> Logical_Bit_Operator1:data1
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> cast4:input
signal cast4_output_wire : std_logic_vector(0 downto 0); -- cast4:output -> Delay1:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Barrel_Shifter:aclr, Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Delay1:aclr, Delay2:aclr, Delay:aclr, Multiplexer:aclr, Multiply_Add:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Barrel_Shifter:clock, Bus_Concatenation1:clock, Bus_Concatenation:clock, Delay1:clock, Delay2:clock, Delay:clock, Multiplexer:clock, Multiply_Add:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
bus_conversion2 : component alt_dspbuilder_cast_GN6OMCQQS7
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GN7IAAYCSZ
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator_result_wire, -- result.wire
data0 => if_statement1_true_wire, -- data0.wire
data1 => sop_0_output_wire -- data1.wire
);
barrel_shifter : component alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map (
DISTANCE_WIDTH => 4,
NDIRECTION => 1,
SIGNED => 0,
use_dedicated_circuitry => "false",
PIPELINE => 0,
WIDTH => 18
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => multiply_add_result_wire, -- a.wire
r => barrel_shifter_r_wire, -- r.wire
distance => constant1_output_wire, -- distance.wire
ena => barrel_shifterenavcc_output_wire, -- ena.wire
user_aclr => barrel_shifteruser_aclrgnd_output_wire -- user_aclr.wire
);
barrel_shifteruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => barrel_shifteruser_aclrgnd_output_wire -- output.wire
);
barrel_shifterenavcc : component alt_dspbuilder_vcc_GN
port map (
output => barrel_shifterenavcc_output_wire -- output.wire
);
multiply_add : component alt_dspbuilder_multiply_add_GNKLXFKAO3
generic map (
family => "Cyclone V",
direction => "AddAdd",
data3b_const => "00011110",
data2b_const => "10010110",
representation => "UNSIGNED",
dataWidth => 8,
data4b_const => "01001100",
number_multipliers => 3,
pipeline_register => "NoRegister",
use_dedicated_circuitry => 1,
data1b_const => "01001100",
use_b_consts => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data1a => bus_conversion3_output_wire, -- data1a.wire
data2a => bus_conversion2_output_wire, -- data2a.wire
data3a => bus_conversion1_output_wire, -- data3a.wire
result => multiply_add_result_wire, -- result.wire
user_aclr => multiply_adduser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiply_addenavcc_output_wire -- ena.wire
);
multiply_adduser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiply_adduser_aclrgnd_output_wire -- output.wire
);
multiply_addenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiply_addenavcc_output_wire -- output.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => delay_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => data_in_0_output_wire, -- in0.wire
in1 => bus_concatenation1_output_wire -- in1.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
bus_conversion : component alt_dspbuilder_cast_GNJGR7GQ2L
generic map (
round => 0,
saturate => 0
)
port map (
input => barrel_shifter_r_wire, -- input.wire
output => bus_conversion_output_wire -- output.wire
);
constant4 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) and (a /= c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => data_in_0_output_wire, -- a.wire
b => constant3_output_wire, -- b.wire
c => constant4_output_wire -- c.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map (
widthB => 16,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion_output_wire, -- a.wire
b => bus_concatenation_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion_output_wire, -- a.wire
b => bus_conversion_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
constant3 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant3_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => delay2enavcc_output_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay2enavcc_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => cast0_output_wire, -- sclr.wire
ena => cast1_output_wire -- ena.wire
);
constant1 : component alt_dspbuilder_constant_GNPXZ5JSVR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "1000",
width => 4
)
port map (
output => constant1_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => multiplexer_result_wire, -- input.wire
output => data_out -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => eop, -- input.wire
output => eop_0_output_wire -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => eop_0_output_wire, -- data0.wire
data1 => cast3_output_wire -- data1.wire
);
cast0 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay2_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator_result_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay_output_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator1_result_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
end architecture rtl; -- of Gray_Processing_GN_Gray_Processing_Gray_Processing_Module
| mit | 9201825568fc0f6247ef0c039528bd26 | 0.556686 | 3.383474 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_multiply_add_GNKLXFKAO3.vhd | 8 | 1,702 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic ( family : string := "Cyclone V";
direction : string := "AddAdd";
data3b_const : string := "00011110";
data2b_const : string := "10010110";
representation : string := "UNSIGNED";
dataWidth : integer := 8;
data4b_const : string := "01001100";
number_multipliers : integer := 3;
pipeline_register : string := "NoRegister";
use_dedicated_circuitry : integer := 1;
data1b_const : string := "01001100";
use_b_consts : natural := 1);
port(
clock : in std_logic;
aclr : in std_logic;
data1a : in std_logic_vector(7 downto 0);
data2a : in std_logic_vector(7 downto 0);
data3a : in std_logic_vector(7 downto 0);
result : out std_logic_vector(17 downto 0);
user_aclr : in std_logic;
ena : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_multiply_add_GNKLXFKAO3 is
Begin
MultiplyAddi : alt_dspbuilder_AltMultConst generic map (
CA => "01001100",
CB => "10010110",
CC => "00011110",
CD => "01001100",
width_a => 8,
width_r => 18,
RegStruct => NoRegister,
data_signed => false
)
port map (
datain => data1a ,
datbin => data2a ,
datcin => data3a ,
datdin => "00000000" ,
dataout => result(17 downto 0),
clock => clock,
ena => ena,
aclr => aclr,
user_aclr => user_aclr
);
end architecture; | mit | 54b2bd0bf92380785cc778757697bdf6 | 0.599882 | 2.980736 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/aurora_ctrl.vhd | 4 | 850 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity aurora_ctrl is
port (
pwdn_in : in std_logic ;
user_clk : in std_logic ;
dcm_not_locked : out std_logic;
loopback : out std_logic_vector(1 downto 0);
power_down : out std_logic;
nfc_req_1 : out std_logic ;
nfc_nb : out std_logic_vector(3 downto 0)
);
end aurora_ctrl;
architecture aurora_ctrl_b1 of aurora_ctrl is
signal pwdn_reg : std_logic_vector(1 downto 0);
begin
dcm_not_locked <= '0';
loopback <= "00";
process(user_clk)
begin
if user_clk = '1' and user_clk'event then
pwdn_reg <= pwdn_reg(0)&pwdn_in;
end if;
end process;
-- power_down <= pwdn_reg(1);
power_down <= '0';
-- Native Flow Control Interface
nfc_req_1 <= '1';
nfc_nb <= "0000";
end aurora_ctrl_b1;
| bsd-2-clause | d1da4b359b089d4cc3678a5559426262 | 0.64 | 2.599388 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_bindec.vhd | 9 | 10,044 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 04b59d3be0057610a03486a70b680a4e | 0.926225 | 1.892951 | false | false | false | false |
estradjm/Class-Work | HDL/Traffic Intersection/clockCounter.vhdl | 1 | 557 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY ClockCounter IS
GENERIC (UpperBound: integer);
PORT ( Clock: IN std_logic;
Enable: OUT std_logic);
END ClockCounter;
ARCHITECTURE behavior OF ClockCounter IS
signal count : integer range 0 to(UpperBound-1);
BEGIN
PROCESS (Clock)
BEGIN
IF (rising_edge(Clock)) then
IF(count = (UpperBound-1)) then
count <= 0;
Enable <= '1';
else
count <= count+1;
Enable <= '0';
end if;
end if;
END PROCESS;
END behavior;
| apache-2.0 | 6480a5d820379be3c4558360527edaa1 | 0.642729 | 3.043716 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/rx_ll_pdu_datapath.vhd | 4 | 8,771 | -------------------------------------------------------------------------------
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:54 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: rx_ll_pdu_datapath_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- RX_LL_PDU_DATAPATH
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- Description: the RX_LL_PDU_DATAPATH module takes regular PDU data in Aurora format
-- and transforms it to LocalLink formatted data
--
-- This module supports 1 2-byte lane designs
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use WORK.AURORA.all;
entity RX_LL_PDU_DATAPATH is
port (
-- Traffic Separator Interface
PDU_DATA : in std_logic_vector(0 to 15);
PDU_DATA_V : in std_logic;
PDU_PAD : in std_logic;
PDU_SCP : in std_logic;
PDU_ECP : in std_logic;
-- LocalLink PDU Interface
RX_D : out std_logic_vector(0 to 15);
RX_REM : out std_logic;
RX_SRC_RDY_N : out std_logic;
RX_SOF_N : out std_logic;
RX_EOF_N : out std_logic;
-- Error Interface
FRAME_ERROR : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic
);
end RX_LL_PDU_DATAPATH;
architecture RTL of RX_LL_PDU_DATAPATH is
--****************************Parameter Declarations**************************
constant DLY : time := 1 ns;
--****************************External Register Declarations**************************
signal RX_D_Buffer : std_logic_vector(0 to 15);
signal RX_REM_Buffer : std_logic;
signal RX_SRC_RDY_N_Buffer : std_logic;
signal RX_SOF_N_Buffer : std_logic;
signal RX_EOF_N_Buffer : std_logic;
signal FRAME_ERROR_Buffer : std_logic;
--****************************Internal Register Declarations**************************
signal storage_r : std_logic_vector(0 to 15);
signal storage_v_r : std_logic;
signal in_frame_r : std_logic;
signal sof_in_storage_r : std_logic;
signal pad_in_storage_r : std_logic;
--*********************************Wire Declarations**********************************
signal src_rdy_n_c : std_logic;
signal storage_ce_c : std_logic;
begin
--*********************************Main Body of Code**********************************
-- VHDL Helper Logic
RX_D <= RX_D_Buffer;
RX_REM <= RX_REM_Buffer;
RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer;
RX_SOF_N <= RX_SOF_N_Buffer;
RX_EOF_N <= RX_EOF_N_Buffer;
FRAME_ERROR <= FRAME_ERROR_Buffer;
--All input goes into a storage register before it is sent on to the output
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
if(storage_ce_c = '1') then
storage_r <= PDU_DATA after DLY;
end if;
end if;
end process;
--Keep track of whether or not there is data in storage
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
if(RESET= '1') then
storage_v_r <= '0' after DLY;
elsif(storage_ce_c = '1') then
storage_v_r <= '1' after DLY;
elsif(storage_v_r = '1') then
storage_v_r <= src_rdy_n_c after DLY;
end if;
end if;
end process;
--Output data is registered
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
RX_D_Buffer <= storage_r after DLY;
end if;
end process;
--Assert the SRC_RDY_N signal when there is data in storage and incomiming data or the
-- end of a frame
src_rdy_n_c <= not (storage_v_r and (storage_ce_c or PDU_ECP));
--Register the SRC_RDY_N signal
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
if(RESET = '1') then
RX_SRC_RDY_N_Buffer <= '1' after DLY;
else
RX_SRC_RDY_N_Buffer <= src_rdy_n_c after DLY;
end if;
end if;
end process;
--Load data into storage when there is valid incoming data
storage_ce_c <= in_frame_r and PDU_DATA_V;
--Data is in a frame when it is preceded by an SOF followed by any number of non-ecp characters
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
if(RESET = '1') then
in_frame_r <= '0' after DLY;
elsif(PDU_SCP = '1') then
in_frame_r <= '1' after DLY;
elsif(PDU_ECP = '1') then
in_frame_r <= '0' after DLY;
end if;
end if;
end process;
--Hold start of frame until it can be asserted with data
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
if(PDU_SCP = '1') then
sof_in_storage_r <= '1' after DLY;
elsif(sof_in_storage_r = '1') then
sof_in_storage_r <= src_rdy_n_c after DLY;
end if;
end if;
end process;
--Register sof_in_storage for use on the LocalLink Interface
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
RX_SOF_N_Buffer <= not sof_in_storage_r after DLY;
end if;
end process;
--Register eof for use on the LocalLink Interface
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
RX_EOF_N_Buffer <= not PDU_ECP after DLY;
end if;
end process;
--Store the pad signal for any data that gets moved into storage
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
if(storage_ce_c = '1') then
pad_in_storage_r <= PDU_PAD after DLY;
end if;
end if;
end process;
--Register the pad signal for use on the LocalLink inteface
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
RX_REM_Buffer <= not pad_in_storage_r after DLY;
end if;
end process;
--Indicate a frame error when a start arrives inframe, and end arrives out
-- of frame, or an end arrives with no data in storage, indicating an empty
-- frame
process(USER_CLK)
begin
if(USER_CLK 'event and USER_CLK = '1') then
FRAME_ERROR_Buffer <= (PDU_SCP and in_frame_r) or
(PDU_ECP and not in_frame_r) or
(PDU_ECP and not storage_v_r) after DLY;
end if;
end process;
end RTL;
| bsd-2-clause | 0babdd30a16c8345447f54fea25f9389 | 0.494014 | 4.0494 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_StratixIV_OrphanedGland/sha256/rtl/sha256_qp.vhd | 4 | 13,870 | --
-- Copyright (c) 2011 OrphanedGland ([email protected])
-- Send donations to : 1PioyqqFWXbKryxysGqoq5XAu9MTRANCEP
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- SHA256 core using quasi-pipelining technique
-- Inspired by fpgaminer's sha256_transform.v
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sha256_qp is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end entity sha256_qp;
architecture sha256_qp_rtl of sha256_qp is
alias slv is std_logic_vector;
subtype msg is unsigned(511 downto 0);
subtype word is unsigned(31 downto 0);
function e0(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(1 downto 0) & x(31 downto 2)) xor (x(12 downto 0) & x(31 downto 13)) xor (x(21 downto 0) & x(31 downto 22));
end e0;
function e1(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(5 downto 0) & x(31 downto 6)) xor (x(10 downto 0) & x(31 downto 11)) xor (x(24 downto 0) & x(31 downto 25));
end e1;
function s0(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 29) := x(6 downto 4) xor x(17 downto 15);
y(28 downto 0) := (x(3 downto 0) & x(31 downto 7)) xor (x(14 downto 0) & x(31 downto 18)) xor x(31 downto 3);
return y;
end s0;
function s1(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 22) := x(16 downto 7) xor x(18 downto 9);
y(21 downto 0) := (x(6 downto 0) & x(31 downto 17)) xor (x(8 downto 0) & x(31 downto 19)) xor x(31 downto 10);
return y;
end s1;
function ch(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (not(x) and z);
end ch;
function maj(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (x and z) xor (y and z);
end maj;
type msg_array is array(0 to 63) of msg;
type word_array_64 is array(0 to 63) of word;
type word_array_65 is array(0 to 64) of word;
type word_array_66 is array(0 to 65) of word;
type hash_array is array(0 to 7) of word;
constant k : word_array_64 := ( X"428a2f98", X"71374491", X"b5c0fbcf", X"e9b5dba5", X"3956c25b", X"59f111f1", X"923f82a4", X"ab1c5ed5",
X"d807aa98", X"12835b01", X"243185be", X"550c7dc3", X"72be5d74", X"80deb1fe", X"9bdc06a7", X"c19bf174",
X"e49b69c1", X"efbe4786", X"0fc19dc6", X"240ca1cc", X"2de92c6f", X"4a7484aa", X"5cb0a9dc", X"76f988da",
X"983e5152", X"a831c66d", X"b00327c8", X"bf597fc7", X"c6e00bf3", X"d5a79147", X"06ca6351", X"14292967",
X"27b70a85", X"2e1b2138", X"4d2c6dfc", X"53380d13", X"650a7354", X"766a0abb", X"81c2c92e", X"92722c85",
X"a2bfe8a1", X"a81a664b", X"c24b8b70", X"c76c51a3", X"d192e819", X"d6990624", X"f40e3585", X"106aa070",
X"19a4c116", X"1e376c08", X"2748774c", X"34b0bcb5", X"391c0cb3", X"4ed8aa4a", X"5b9cca4f", X"682e6ff3",
X"748f82ee", X"78a5636f", X"84c87814", X"8cc70208", X"90befffa", X"a4506ceb", X"bef9a3f7", X"c67178f2" );
constant h_default : hash_array := ( X"6a09e667", X"bb67ae85", X"3c6ef372", X"a54ff53a", X"510e527f", X"9b05688c", X"1f83d9ab", X"5be0cd19" );
signal w : msg_array;
signal new_w : word_array_64;
signal a : word_array_66;
signal b : word_array_66;
signal c : word_array_66;
signal d : word_array_66;
signal e : word_array_66;
signal f : word_array_66;
signal g : word_array_66;
signal h : word_array_66;
signal hash : hash_array;
signal h_init : hash_array;
signal delta0 : word_array_64;
signal delta1 : word_array_64;
signal m1 : word_array_64;
signal m2 : word_array_64;
signal epsilon : word_array_65;
signal l : word_array_65;
signal alpha : word_array_66;
signal q_w : msg_array;
signal q_a : word_array_66;
signal q_b : word_array_66;
signal q_c : word_array_66;
signal q_d : word_array_66;
signal q_e : word_array_66;
signal q_f : word_array_66;
signal q_g : word_array_66;
signal q_h : word_array_66;
signal q_hash : hash_array;
signal q_m1 : word_array_64;
signal q_m2 : word_array_64;
signal q_l : word_array_65;
begin
output_mapping: for i in 0 to 7 generate
--digest((i+1)*32-1 downto i*32) <= slv(q_hash(7-i));
digest((i+1)*32-1 downto i*32) <= slv(q_hash(i));
end generate output_mapping;
default_h_gen: if default_h = true generate
h_init <= h_default;
end generate default_h_gen;
h_gen: if default_h = false generate
h_array_gen: for i in 0 to 7 generate
h_init(i) <= unsigned(h_in((i+1)*32-1 downto i*32));
end generate h_array_gen;
end generate h_gen;
hash_pipeline: for i in 0 to 65 generate
first_stage: if i = 0 generate
w(i) <= unsigned(msg_in);
a(i) <= h_init(0);
b(i) <= h_init(1);
c(i) <= h_init(2);
d(i) <= h_init(3);
e(i) <= h_init(4);
f(i) <= h_init(5);
g(i) <= h_init(6);
h(i) <= h_init(7);
delta0(i) <= h_init(3);
delta1(i) <= h_init(7);
m1(i) <= delta0(i) + delta1(i) + k(i) + w(i)(31 downto 0);
m2(i) <= delta1(i) + k(i) + w(i)(31 downto 0);
epsilon(i) <= e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6));
l(i) <= (others => '0');
alpha(i) <= e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
end generate first_stage;
second_stage: if i = 1 generate
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= h_init(0);
b(i) <= h_init(1);
c(i) <= h_init(2);
d(i) <= h_init(3);
e(i) <= epsilon(i);
f(i) <= h_init(4);
g(i) <= h_init(5);
h(i) <= h_init(6);
delta0(i) <= h_init(2);
delta1(i) <= h_init(6);
m1(i) <= delta0(i) + delta1(i) + k(i) + w(i)(31 downto 0);
m2(i) <= delta1(i) + k(i) + w(i)(31 downto 0);
epsilon(i) <= q_m1(i-1) + e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6));
l(i) <= q_m2(i-1) + e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6));
alpha(i) <= e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
end generate second_stage;
third_stage: if i = 2 generate
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= alpha(i);
b(i) <= h_init(0);
c(i) <= h_init(1);
d(i) <= h_init(2);
e(i) <= epsilon(i);
f(i) <= q_e(i-1);
g(i) <= h_init(4); -- q_f(i-1)
h(i) <= h_init(5); -- q_g(i-1)
delta0(i) <= h_init(1);
delta1(i) <= h_init(5);
m1(i) <= delta0(i) + delta1(i) + k(i) + w(i)(31 downto 0);
m2(i) <= delta1(i) + k(i) + w(i)(31 downto 0);
epsilon(i) <= q_m1(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), h_init(4), h_init(5));
l(i) <= q_m2(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), h_init(4), h_init(5));
alpha(i) <= q_l(i-1) + e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
end generate third_stage;
normal_stage: if i > 2 and i < 64 generate
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= alpha(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= epsilon(i);
f(i) <= q_e(i-1);
g(i) <= q_f(i-1);
h(i) <= q_g(i-1);
delta0(i) <= q_b(i-1);
delta1(i) <= q_g(i-1);
m1(i) <= delta0(i) + delta1(i) + k(i) + w(i)(31 downto 0);
m2(i) <= delta1(i) + k(i) + w(i)(31 downto 0);
epsilon(i) <= q_m1(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1));
l(i) <= q_m2(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1));
alpha(i) <= q_l(i-1) + e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
end generate normal_stage;
second_last_stage: if i = 64 generate
a(i) <= alpha(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= epsilon(i);
f(i) <= q_e(i-1);
g(i) <= q_f(i-1);
h(i) <= q_g(i-1);
epsilon(i) <= q_m1(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1));
l(i) <= q_m2(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1));
alpha(i) <= q_l(i-1) + e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
end generate second_last_stage;
last_stage: if i = 65 generate
a(i) <= alpha(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= q_e(i-1);
f(i) <= q_f(i-1);
g(i) <= q_g(i-1);
h(i) <= q_h(i-1);
alpha(i) <= q_l(i-1) + e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
end generate last_stage;
end generate hash_pipeline;
hash(0) <= q_a(65) + h_init(0);
hash(1) <= q_b(65) + h_init(1);
hash(2) <= q_c(65) + h_init(2);
hash(3) <= q_d(65) + h_init(3);
hash(4) <= q_e(65) + h_init(4);
hash(5) <= q_f(65) + h_init(5);
hash(6) <= q_g(65) + h_init(6);
hash(7) <= q_h(65) + h_init(7);
registers : process(clk, reset) is
begin
if reset = '1' then
null;
elsif rising_edge(clk) then
q_w <= w;
q_a <= a;
q_b <= b;
q_c <= c;
q_d <= d;
q_e <= e;
q_f <= f;
q_g <= g;
q_h <= h;
q_hash <= hash;
q_m1 <= m1;
q_m2 <= m2;
q_l <= l;
end if;
end process registers;
end architecture sha256_qp_rtl;
| gpl-3.0 | f96262c927ad501e104087f2f17f265c | 0.413843 | 3.011944 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_extdepth_v6.vhd | 9 | 49,967 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 8eff92cadf552f323bcc63258ed985bb | 0.948606 | 1.82122 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_multiply_add_GNPSDKCBU2.vhd | 1 | 1,730 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiply_add_GNPSDKCBU2 is
generic ( family : string := "Cyclone V";
direction : string := "AddAdd";
data3b_const : string := "00011110";
data2b_const : string := "10010110";
representation : string := "UNSIGNED";
dataWidth : integer := 8;
data4b_const : string := "01001100";
number_multipliers : integer := 3;
pipeline_register : string := "InputsMultiplierandAdder";
use_dedicated_circuitry : integer := 1;
data1b_const : string := "01001100";
use_b_consts : natural := 1);
port(
clock : in std_logic;
aclr : in std_logic;
data1a : in std_logic_vector(7 downto 0);
data2a : in std_logic_vector(7 downto 0);
data3a : in std_logic_vector(7 downto 0);
result : out std_logic_vector(17 downto 0);
user_aclr : in std_logic;
ena : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_multiply_add_GNPSDKCBU2 is
Begin
MultiplyAddi : alt_dspbuilder_AltMultConst generic map (
CA => "01001100",
CB => "10010110",
CC => "00011110",
CD => "01001100",
width_a => 8,
width_r => 18,
RegStruct => InputsMultiplierandAdder,
data_signed => false
)
port map (
datain => data1a ,
datbin => data2a ,
datcin => data3a ,
datdin => "00000000" ,
dataout => result(17 downto 0),
clock => clock,
ena => ena,
aclr => aclr,
user_aclr => user_aclr
);
end architecture; | mit | ecafd1925e03d2a93a9575db948153f4 | 0.606358 | 3.029772 | false | false | false | false |
Andy46/OV7670-VHDL | OV7670/src/mod_VGA/VGA_800x640.vhd | 1 | 3,893 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:24:58 11/12/2013
-- Design Name:
-- Module Name: VGA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGA is
Port ( clk100MHz, reset : std_logic;
colRed, colGreen, colBlue : in std_logic_vector(3 downto 0);
Hsync, Vsync : out std_logic;
vgaRed, vgaGreen, vgaBlue : out std_logic_vector(3 downto 0));
end VGA;
architecture Behavioral of VGA is
--Divisor de frecuencia
--Constantes
--Componentes
component Divisor50MHz is
Port ( clk_in, reset : in std_logic;
clk_out : out std_logic);
end component;
--Señales
signal clk50MHz : std_logic;
--Contadores vertical y horizontal
--Constantes
constant UNO : std_logic_vector(15 downto 0) := "0000000000000001";
--Componentes
component FullAdder16bits is
port ( clk, reset : std_logic;
a, b : in std_logic_vector(15 downto 0);
cin : in std_logic;
sum : out std_logic_vector(15 downto 0);
cout : out std_logic);
end component;
--Señales
signal Vcount, Vcount_next : std_logic_vector(15 downto 0);
signal Hcount, Hcount_next : std_logic_vector(15 downto 0);
begin
--Asignar colores
process(clk100MHz, reset, Vcount, Hcount, colRed, colGreen, colBlue)
begin
if (Vcount >= std_logic_vector(to_unsigned(0, 16)) and Vcount <= std_logic_vector(to_unsigned(799, 16)) and
Hcount >= std_logic_vector(to_unsigned(0, 16)) and Hcount <= std_logic_vector(to_unsigned(799, 16))) then
vgaRed <= colRed;
vgaGreen <= colGreen;
vgaBlue <= colBlue;
else
vgaRed <= (others => '0');
vgaGreen <= (others => '0');
vgaBlue <= (others => '0');
end if;
end process;
Div_VGA: Divisor50MHz port map(clk_in => clk100MHz, reset => reset, clk_out => clk50MHz);
--Process VSYNC
FA_Vsync: FullAdder16bits port map(clk => clk100MHz, reset => reset, a => Vcount, b => std_logic_vector(to_unsigned(1, 16)),
cin => '0', sum => Vcount_next);
process(clk50MHz, reset, Hcount, Vcount)
begin
if reset = '0' then
Vcount <= (others => '0');
VSync <= '0';
elsif clk50MHz'event and clk50MHz = '1' then
if Hcount = std_logic_vector(to_unsigned(1040, 16)) then --800 | 800
if Vcount = std_logic_vector(to_unsigned(665, 16)) then --525 | 448
Vcount <= (others => '0');
else
Vcount <= Vcount_next;
end if;
if Vcount >= std_logic_vector(to_unsigned(636, 16)) and Vcount < std_logic_vector(to_unsigned(642, 16)) then --490,492 | 386,388
Vsync <= '1';
else
Vsync <= '0';
end if;
end if;
end if;
end process;
--Process HSYNC
FA_Hsync: FullAdder16bits port map(clk => clk100MHz, reset => reset, a => Hcount, b => UNO,
cin => '0', sum => Hcount_next);
process(clk50MHz, reset)
begin
if reset = '0' then
Hcount <= (others => '0');
Hsync <= '0';
elsif clk50MHz'event and clk50MHz = '1' then
if Hcount = std_logic_vector(to_unsigned(1040, 16)) then --800 | 800
Hcount <= (others => '0');
else
Hcount <= Hcount_next;
end if;
if Hcount >= std_logic_vector(to_unsigned(855, 16)) and Hcount < std_logic_vector(to_unsigned(975, 16)) then --656,752 | 656,752
Hsync <= '1';
else
Hsync <= '0';
end if;
end if;
end process;
end Behavioral; | mit | 4a1edd9078c05a3a9d868e4a2dfad9b4 | 0.627537 | 3.241465 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/standard_cc_module.vhd | 4 | 10,922 |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: standard_cc_module_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- STANDARD_CC_MODULE
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engeneering Group
--
-- Description: This module drives the Aurora module's Clock Compensation
-- interface. Clock Compensation sequences are generated according
-- to the requirements in the Aurora Protocol specification.
--
-- This module supports Aurora Modules with any number of
-- 2-byte lanes and no User Flow Control.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synthesis translate_off
library UNISIM;
use UNISIM.all;
-- synthesis translate_on
entity STANDARD_CC_MODULE is
port
(
-- Clock Compensation Control Interface
WARN_CC : out std_logic;
DO_CC : out std_logic;
-- System Interface
DCM_NOT_LOCKED : in std_logic;
USER_CLK : in std_logic;
CHANNEL_UP : in std_logic
);
end STANDARD_CC_MODULE;
architecture RTL of STANDARD_CC_MODULE is
--******************************Parameter Declarations*******************************
constant DLY : time := 1 ns;
--************************** Internal Register Declarations **************************
signal prepare_count_r : std_logic_vector(0 to 9) := "0000000000";
signal cc_count_r : std_logic_vector(0 to 5) := "000000";
signal reset_r : std_logic;
signal count_13d_srl_r : std_logic_vector(0 to 11);
signal count_13d_flop_r : std_logic;
signal count_16d_srl_r : std_logic_vector(0 to 14);
signal count_16d_flop_r : std_logic;
signal count_24d_srl_r : std_logic_vector(0 to 22);
signal count_24d_flop_r : std_logic;
--*********************************Wire Declarations**********************************
signal start_cc_c : std_logic;
signal inner_count_done_r : std_logic;
signal middle_count_done_c : std_logic;
signal cc_idle_count_done_c : std_logic;
--*********************************Main Body of Code**********************************
begin
--________________________Clock Correction State Machine__________________________
-- The clock correction state machine is a counter with three sections. The first
-- section counts out the idle period before a clock correction occurs. The second
-- section counts out a period when NFC and UFC operations should not be attempted
-- because they will not be completed. The last section counts out the cycles of
-- the clock correction sequence.
-- The inner count for the CC counter counts to 13. It is implemented using
-- an SRL16 and a flop
-- The SRL counts 12 bits of the count
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
count_13d_srl_r <= (count_13d_flop_r & count_13d_srl_r(0 to 10)) after DLY;
end if;
end process;
-- The inner count is done when a 1 reaches the end of the SRL
inner_count_done_r <= count_13d_srl_r(11);
-- The flop extends the shift register to 13 bits for counting. It is held at
-- zero while channel up is low to clear the register, and is seeded with a
-- single 1 when channel up transitions from 0 to 1
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
count_13d_flop_r <= '0' after DLY;
elsif( (CHANNEL_UP and reset_r)= '1') then
count_13d_flop_r <= '1' after DLY;
else
count_13d_flop_r <= inner_count_done_r after DLY;
end if;
end if;
end process;
-- The middle count for the CC counter counts to 16. Its count increments only
-- when the inner count is done. It is implemented using an SRL16 and a flop
-- The SRL counts 15 bits of the count. It is enabled only when the inner count
-- is done
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if((inner_count_done_r or not CHANNEL_UP) = '1') then
count_16d_srl_r <= ( count_16d_flop_r & count_16d_srl_r(0 to 13) ) after DLY;
end if;
end if;
end process;
-- The middle count is done when a 1 reaches the end of the SRL and the inner
-- count finishes
middle_count_done_c <= inner_count_done_r and count_16d_srl_r(14);
-- The flop extends the shift register to 16 bits for counting. It is held at
-- zero while channel up is low to clear the register, and is seeded with a
-- single 1 when channel up transitions from 0 to 1
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
count_16d_flop_r <= '0' after DLY;
elsif((CHANNEL_UP and reset_r)='1') then
count_16d_flop_r <= '1' after DLY;
elsif(inner_count_done_r = '1') then
count_16d_flop_r <= middle_count_done_c after DLY;
end if;
end if;
end process;
-- The outer count (aka the cc idle count) is done when it reaches 24. Its count
-- increments only when the middle count is done. It is implemented with 2
-- SRL16Es.
-- The SRL counts 23 bits of the count. It is enabled only when the middle count is
-- done
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if((middle_count_done_c or not CHANNEL_UP) = '1') then
count_24d_srl_r <= (count_24d_flop_r & count_24d_srl_r(0 to 21)) after DLY;
end if;
end if;
end process;
-- The cc idle count is done when a 1 reaches the end of the SRL and the middle count finishes
cc_idle_count_done_c <= middle_count_done_c and count_24d_srl_r(22);
-- The flop extends the shift register to 24 bits for counting. It is held at
-- zero while channel up is low to clear the register, and is seeded with a single
-- 1 when channel up transitions from 0 to 1
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
count_24d_flop_r <= '0' after DLY;
elsif( (CHANNEL_UP and reset_r) = '1') then
count_24d_flop_r <= '1' after DLY;
elsif( middle_count_done_c = '1') then
count_24d_flop_r <= cc_idle_count_done_c after DLY;
end if;
end if;
end process;
-- Because UFC and CC sequences are not allowed to preempt one another, there
-- there is a warning signal to indicate an impending CC sequence. This signal
-- is used to prevent UFC messages from starting.
-- For 1 lane, we need an 10-cycle count.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
prepare_count_r <= (cc_idle_count_done_c & prepare_count_r(0 to 8)) after DLY;
end if;
end process;
-- The state machine stays in the prepare_cc state from when the cc idle
-- count finishes, to when the prepare count has finished. While in this
-- state, UFC operations cannot start, which prevents them from having to
-- be pre-empted by CC sequences.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
WARN_CC <= '0' after DLY;
elsif(cc_idle_count_done_c = '1') then
WARN_CC <= '1' after DLY;
elsif(prepare_count_r(9) = '1') then
WARN_CC <= '0' after DLY;
end if;
end if;
end process;
-- Track the state of channel up on the previous cycle. We use this signal to determine
-- when to seed the shift register counters with ones
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
reset_r <= not CHANNEL_UP after DLY;
end if;
end process;
--Do a CC after CHANNEL_UP is asserted or CC_warning is complete.
start_cc_c <= prepare_count_r(9) or (CHANNEL_UP and reset_r);
-- This SRL counter keeps track of the number of cycles spent in the CC
-- sequence. It starts counting when the prepare_cc state ends, and
-- finishes counting after 6 cycles have passed.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
cc_count_r <= ( (not CHANNEL_UP or prepare_count_r(9)) & cc_count_r(0 to 4) ) after DLY;
end if;
end process;
-- The TX_LL module stays in the do_cc state for 6 cycles. It starts
-- when the prepare_cc state ends.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
DO_CC <= '0' after DLY;
elsif(start_cc_c = '1') then
DO_CC <= '1' after DLY;
elsif(cc_count_r(5) = '1') then
DO_CC <= '0' after DLY;
end if;
end if;
end process;
end RTL;
| bsd-2-clause | 24c884b175eacc2aeedb935db4c1ffa8 | 0.558689 | 3.893761 | false | false | false | false |
inmcm/Simon_Speck_Ciphers | VHDL/SPECK_CIPHER_TB.vhd | 1 | 14,538 | -- SPECK_CIPHER_TB.vhd
-- Copyright 2016 Michael Calvin McCoy
-- [email protected]
-- see LICENSE.md
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:00:46 10/04/2015
-- Design Name:
-- Module Name: D:/Work/Code/Simon_Speck_Ciphers/VHDL/SPECK_CIPHER_TB.vhd
-- Project Name: Speck
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SPECK_CIPHER
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.SPECK_CONSTANTS.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SPECK_CIPHER_TB IS
END SPECK_CIPHER_TB;
ARCHITECTURE behavior OF SPECK_CIPHER_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SPECK_CIPHER
GENERIC(KEY_SIZE : integer range 0 to 256;
BLOCK_SIZE : integer range 0 to 128;
ROUND_LIMIT: integer range 0 to 72);
PORT(
SYS_CLK : IN std_logic;
RST : IN std_logic;
BUSY : OUT std_logic;
CONTROL : IN std_logic_vector(1 downto 0);
KEY : IN std_logic_vector(KEY_SIZE - 1 downto 0);
BLOCK_INPUT : IN std_logic_vector(BLOCK_SIZE - 1 downto 0);
BLOCK_OUTPUT : OUT std_logic_vector(BLOCK_SIZE - 1 downto 0)
);
END COMPONENT;
--Global Inputs
signal SYS_CLK : std_logic := '0';
signal RST : std_logic := '0';
signal CONTROL : std_logic_vector(1 downto 0) := (others => '0');
--UUT 1
signal KEY_1 : std_logic_vector(63 downto 0) := (others => '0');
signal BLOCK_INPUT_1 : std_logic_vector(31 downto 0) := (others => '0');
signal BUSY_1 : std_logic;
signal BLOCK_OUTPUT_1 : std_logic_vector(31 downto 0);
--UUT 2
signal KEY_2 : std_logic_vector(71 downto 0) := (others => '0');
signal BLOCK_INPUT_2 : std_logic_vector(47 downto 0) := (others => '0');
signal BUSY_2 : std_logic;
signal BLOCK_OUTPUT_2 : std_logic_vector(47 downto 0);
--UUT 3
signal KEY_3 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_3 : std_logic_vector(47 downto 0) := (others => '0');
signal BUSY_3 : std_logic;
signal BLOCK_OUTPUT_3 : std_logic_vector(47 downto 0);
--UUT 4
signal KEY_4 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_4 : std_logic_vector(63 downto 0) := (others => '0');
signal BUSY_4 : std_logic;
signal BLOCK_OUTPUT_4 : std_logic_vector(63 downto 0);
--UUT 5
signal KEY_5 : std_logic_vector(127 downto 0) := (others => '0');
signal BLOCK_INPUT_5 : std_logic_vector(63 downto 0) := (others => '0');
signal BUSY_5 : std_logic;
signal BLOCK_OUTPUT_5 : std_logic_vector(63 downto 0);
--UUT 6
signal KEY_6 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_6 : std_logic_vector(95 downto 0) := (others => '0');
signal BUSY_6 : std_logic;
signal BLOCK_OUTPUT_6 : std_logic_vector(95 downto 0);
--UUT 7
signal KEY_7 : std_logic_vector(143 downto 0) := (others => '0');
signal BLOCK_INPUT_7 : std_logic_vector(95 downto 0) := (others => '0');
signal BUSY_7 : std_logic;
signal BLOCK_OUTPUT_7 : std_logic_vector(95 downto 0);
--UUT 8
signal KEY_8 : std_logic_vector(127 downto 0) := (others => '0');
signal BLOCK_INPUT_8 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_8 : std_logic;
signal BLOCK_OUTPUT_8 : std_logic_vector(127 downto 0);
--UUT 9
signal KEY_9 : std_logic_vector(191 downto 0) := (others => '0');
signal BLOCK_INPUT_9 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_9 : std_logic;
signal BLOCK_OUTPUT_9 : std_logic_vector(127 downto 0);
--UUT 10
signal KEY_10 : std_logic_vector(255 downto 0) := (others => '0');
signal BLOCK_INPUT_10 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_10 : std_logic;
signal BLOCK_OUTPUT_10 : std_logic_vector(127 downto 0);
-- Clock period definitions
constant SYS_CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut_1: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => 64,
BLOCK_SIZE => 32,
ROUND_LIMIT => Round_Count_Lookup(64, 32))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_1,
CONTROL => CONTROL,
KEY => KEY_1,
BLOCK_INPUT => BLOCK_INPUT_1,
BLOCK_OUTPUT => BLOCK_OUTPUT_1
);
uut_2: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => 72,
BLOCK_SIZE => 48,
ROUND_LIMIT => Round_Count_Lookup(72, 48))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_2,
CONTROL => CONTROL,
KEY => KEY_2,
BLOCK_INPUT => BLOCK_INPUT_2,
BLOCK_OUTPUT => BLOCK_OUTPUT_2
);
uut_3: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 48,
ROUND_LIMIT => Round_Count_Lookup(96, 48))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_3,
CONTROL => CONTROL,
KEY => KEY_3,
BLOCK_INPUT => BLOCK_INPUT_3,
BLOCK_OUTPUT => BLOCK_OUTPUT_3
);
uut_4: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 64,
ROUND_LIMIT => Round_Count_Lookup(96, 64))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_4,
CONTROL => CONTROL,
KEY => KEY_4,
BLOCK_INPUT => BLOCK_INPUT_4,
BLOCK_OUTPUT => BLOCK_OUTPUT_4
);
uut_5: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => 128,
BLOCK_SIZE => 64,
ROUND_LIMIT => Round_Count_Lookup(128, 64))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_5,
CONTROL => CONTROL,
KEY => KEY_5,
BLOCK_INPUT => BLOCK_INPUT_5,
BLOCK_OUTPUT => BLOCK_OUTPUT_5
);
uut_6: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 96,
ROUND_LIMIT => Round_Count_Lookup(96, 96))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_6,
CONTROL => CONTROL,
KEY => KEY_6,
BLOCK_INPUT => BLOCK_INPUT_6,
BLOCK_OUTPUT => BLOCK_OUTPUT_6
);
uut_7: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => 144,
BLOCK_SIZE => 96,
ROUND_LIMIT => Round_Count_Lookup(144, 96))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_7,
CONTROL => CONTROL,
KEY => KEY_7,
BLOCK_INPUT => BLOCK_INPUT_7,
BLOCK_OUTPUT => BLOCK_OUTPUT_7
);
uut_8: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => 128,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(128, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_8,
CONTROL => CONTROL,
KEY => KEY_8,
BLOCK_INPUT => BLOCK_INPUT_8,
BLOCK_OUTPUT => BLOCK_OUTPUT_8
);
uut_9: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => 192,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(192, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_9,
CONTROL => CONTROL,
KEY => KEY_9,
BLOCK_INPUT => BLOCK_INPUT_9,
BLOCK_OUTPUT => BLOCK_OUTPUT_9
);
uut_10: SPECK_CIPHER
GENERIC MAP (KEY_SIZE => 256,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(256, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_10,
CONTROL => CONTROL,
KEY => KEY_10,
BLOCK_INPUT => BLOCK_INPUT_10,
BLOCK_OUTPUT => BLOCK_OUTPUT_10
);
-- Clock process definitions
SYS_CLK_process :process
begin
for i in 0 to 500 loop
SYS_CLK <= '0';
wait for SYS_CLK_period/2;
SYS_CLK <= '1';
wait for SYS_CLK_period/2;
end loop ;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for SYS_CLK_period*10;
KEY_1 <= X"1918111009080100";
KEY_2 <= X"1211100a0908020100";
KEY_3 <= X"1a19181211100a0908020100";
KEY_4 <= X"131211100b0a090803020100";
KEY_5 <= X"1b1a1918131211100b0a090803020100";
KEY_6 <= X"0d0c0b0a0908050403020100";
KEY_7 <= X"1514131211100d0c0b0a0908050403020100";
KEY_8 <= X"0f0e0d0c0b0a09080706050403020100";
KEY_9 <= X"17161514131211100f0e0d0c0b0a09080706050403020100";
KEY_10 <= X"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100";
CONTROL <= "01";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
BLOCK_INPUT_1 <= X"6574694c";
BLOCK_INPUT_2 <= X"20796c6c6172";
BLOCK_INPUT_3 <= X"6d2073696874";
BLOCK_INPUT_4 <= X"74614620736e6165";
BLOCK_INPUT_5 <= X"3b7265747475432d";
BLOCK_INPUT_6 <= X"65776f68202c656761737520";
BLOCK_INPUT_7 <= X"656d6974206e69202c726576";
BLOCK_INPUT_8 <= X"6c617669757165207469206564616d20";
BLOCK_INPUT_9 <= X"726148206665696843206f7420746e65";
BLOCK_INPUT_10 <= X"65736f6874206e49202e72656e6f6f70";
CONTROL <= "11";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
assert BLOCK_OUTPUT_1 /= X"a86842f2" report "UUT1 Encryption Success" severity note;
assert BLOCK_OUTPUT_1 = X"a86842f2" report "UUT1 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_2 /= X"c049a5385adc" report "UUT2 Encryption Success" severity note;
assert BLOCK_OUTPUT_2 = X"c049a5385adc" report "UUT2 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_3 /= X"735e10b6445d" report "UUT3 Encryption Success" severity note;
assert BLOCK_OUTPUT_3 = X"735e10b6445d" report "UUT3 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_4 /= X"9f7952ec4175946c" report "UUT4 Encryption Success" severity note;
assert BLOCK_OUTPUT_4 = X"9f7952ec4175946c" report "UUT4 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_5 /= X"8c6fa548454e028b" report "UUT5 Encryption Success" severity note;
assert BLOCK_OUTPUT_5 = X"8c6fa548454e028b" report "UUT5 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_6 /= X"9e4d09ab717862bdde8f79aa" report "UUT6 Encryption Success" severity note;
assert BLOCK_OUTPUT_6 = X"9e4d09ab717862bdde8f79aa" report "UUT6 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_7 /= X"2bf31072228a7ae440252ee6" report "UUT7 Encryption Success" severity note;
assert BLOCK_OUTPUT_7 = X"2bf31072228a7ae440252ee6" report "UUT7 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_8 /= X"a65d9851797832657860fedf5c570d18" report "UUT8 Encryption Success" severity note;
assert BLOCK_OUTPUT_8 = X"a65d9851797832657860fedf5c570d18" report "UUT8 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_9 /= X"1be4cf3a13135566f9bc185de03c1886" report "UUT9 Encryption Success" severity note;
assert BLOCK_OUTPUT_9 = X"1be4cf3a13135566f9bc185de03c1886" report "UUT9 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_10 /= X"4109010405c0f53e4eeeb48d9c188f43" report "UUT10 Encryption Success" severity note;
assert BLOCK_OUTPUT_10 = X"4109010405c0f53e4eeeb48d9c188f43" report "UUT10 Encryption Failed" severity failure;
BLOCK_INPUT_1 <= X"a86842f2";
BLOCK_INPUT_2 <= X"c049a5385adc";
BLOCK_INPUT_3 <= X"735e10b6445d";
BLOCK_INPUT_4 <= X"9f7952ec4175946c";
BLOCK_INPUT_5 <= X"8c6fa548454e028b";
BLOCK_INPUT_6 <= X"9e4d09ab717862bdde8f79aa";
BLOCK_INPUT_7 <= X"2bf31072228a7ae440252ee6";
BLOCK_INPUT_8 <= X"a65d9851797832657860fedf5c570d18";
BLOCK_INPUT_9 <= X"1be4cf3a13135566f9bc185de03c1886";
BLOCK_INPUT_10 <= X"4109010405c0f53e4eeeb48d9c188f43";
CONTROL <= "10";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
assert BLOCK_OUTPUT_1 /= X"6574694c" report "UUT1 Decryption Success" severity note;
assert BLOCK_OUTPUT_1 = X"6574694c" report "UUT1 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_2 /= X"20796c6c6172" report "UUT2 Decryption Success" severity note;
assert BLOCK_OUTPUT_2 = X"20796c6c6172" report "UUT2 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_3 /= X"6d2073696874" report "UUT3 Decryption Success" severity note;
assert BLOCK_OUTPUT_3 = X"6d2073696874" report "UUT3 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_4 /= X"74614620736e6165" report "UUT4 Decryption Success" severity note;
assert BLOCK_OUTPUT_4 = X"74614620736e6165" report "UUT4 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_5 /= X"3b7265747475432d" report "UUT5 Decryption Success" severity note;
assert BLOCK_OUTPUT_5 = X"3b7265747475432d" report "UUT5 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_6 /= X"65776f68202c656761737520" report "UUT6 Decryption Success" severity note;
assert BLOCK_OUTPUT_6 = X"65776f68202c656761737520" report "UUT6 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_7 /= X"656d6974206e69202c726576" report "UUT7 Decryption Success" severity note;
assert BLOCK_OUTPUT_7 = X"656d6974206e69202c726576" report "UUT7 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_8 /= X"6c617669757165207469206564616d20" report "UUT8 Decryption Success" severity note;
assert BLOCK_OUTPUT_8 = X"6c617669757165207469206564616d20" report "UUT8 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_9 /= X"726148206665696843206f7420746e65" report "UUT9 Decryption Success" severity note;
assert BLOCK_OUTPUT_9 = X"726148206665696843206f7420746e65" report "UUT9 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_10 /= X"65736f6874206e49202e72656e6f6f70" report "UUT10 Decryption Success" severity note;
assert BLOCK_OUTPUT_10 = X"65736f6874206e49202e72656e6f6f70" report "UUT10 Decryption Failed" severity failure;
-- insert stimulus here
wait;
end process;
END;
| mit | 223d39968c50c9988e3fa1b2a177c6fb | 0.642798 | 3.191658 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/ddr2ram/example_design/sim/functional/sim_tb_top.vhd | 3 | 16,489 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3200;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3200.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 13;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_SIMULATION : string := "TRUE";
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component example_top is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_HW_TESTING : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end component;
component ddr2_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
rdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal rzq3 : std_logic;
signal zio3 : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : example_top generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_HW_TESTING => C3_HW_TESTING,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
calib_done => calib_done,
error => error,
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
mcb3_dram_dqs => mcb3_dram_dqs
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr2_model_c3 port map(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_rdqs => mcb3_dram_dm_vector ,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
rdqs_n => open,
odt => mcb3_dram_odt
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
| bsd-2-clause | 4e16a25aff54d5c359c623295771b9c4 | 0.476014 | 3.707059 | false | false | false | false |
pvarin/SampleVHDL | testbench/gates_tb.vhd | 1 | 981 | library ieee;
use ieee.std_logic_1164.all;
entity gates_tb is
generic(half_period : Time := 1 ns);
end gates_tb;
architecture behavior of gates_tb is
-- declare signals
signal clk: std_logic := '0';
signal clk2: std_logic := '0';
signal and_out, or_out, not_out: std_logic;
begin
-- declare and map gate to test
or2 : entity work.OR2(basic)
port map (A => clk, B => clk2, F => or_out);
and2 : entity work.AND2(basic)
port map (A => clk, B => clk2, F => and_out);
not2 : entity work.NOT2(basic)
port map (A => clk, F => not_out);
-- define test process
-- test:
-- wire things here
-- setup the clock
clock : process begin
clk <= not clk;
wait for half_period;
assert NOW <= 200 ns report "End of Test" severity error;
end process clock;
-- setup the second clock
clock2 : process begin
clk2 <= not clk2;
wait for half_period*2;
assert NOW <= 200 ns report "End of Test" severity error;
end process clock2;
end architecture; -- behavior | bsd-3-clause | 04c103a63b17fde66479a68bffaa0cf1 | 0.66055 | 2.937126 | false | true | false | false |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/vhdl/mgt_fifo1.vhd | 2 | 29,287 | ------------------------------------------------------------------------------
-- mgt_fifo1.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY **
-- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR **
-- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND **
-- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES **
-- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: mgt_fifo1.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates IPIF and user logic.
-- Date: Tue Jul 05 10:18:46 2005 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library opb_ipif_v3_01_a;
use opb_ipif_v3_01_a.all;
library mgt_fifo1_v1_00_a;
use mgt_fifo1_v1_00_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
------------------------------------------------------------------------------
entity mgt_fifo1 is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"0000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
iTOP_REF_CLK : in std_logic;
iRXN : in std_logic;
iRXP : in std_logic;
iTXN : out std_logic;
iTXP : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity mgt_fifo1;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of mgt_fifo1 is
------------------------------------------
-- Constant: array of address range identifiers
------------------------------------------
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00, -- user logic S/W register address space
1 => IPIF_RDFIFO_REG, -- include read FIFO register service
2 => IPIF_RDFIFO_DATA, -- include read FIFO service
3 => IPIF_WRFIFO_REG, -- include write FIFO register service
4 => IPIF_WRFIFO_DATA -- include write FIFO service
);
------------------------------------------
-- Constant: array of address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
constant USER_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RDFIFO_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RDFIFO_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant RDFIFO_DATA_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200";
constant RDFIFO_DATA_HIGHADDR : std_logic_vector := C_BASEADDR or X"000002FF";
constant WRFIFO_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000300";
constant WRFIFO_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"000003FF";
constant WRFIFO_DATA_BASEADDR : std_logic_vector := C_BASEADDR or X"00000400";
constant WRFIFO_DATA_HIGHADDR : std_logic_vector := C_BASEADDR or X"000004FF";
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
ZERO_ADDR_PAD & USER_HIGHADDR, -- user logic high address
ZERO_ADDR_PAD & RDFIFO_REG_BASEADDR, -- read FIFO register base address
ZERO_ADDR_PAD & RDFIFO_REG_HIGHADDR, -- read FIFO register high address
ZERO_ADDR_PAD & RDFIFO_DATA_BASEADDR, -- read FIFO data base address
ZERO_ADDR_PAD & RDFIFO_DATA_HIGHADDR, -- read FIFO data high address
ZERO_ADDR_PAD & WRFIFO_REG_BASEADDR, -- write FIFO register base address
ZERO_ADDR_PAD & WRFIFO_REG_HIGHADDR, -- write FIFO register high address
ZERO_ADDR_PAD & WRFIFO_DATA_BASEADDR, -- write FIFO data base address
ZERO_ADDR_PAD & WRFIFO_DATA_HIGHADDR -- write FIFO data high address
);
------------------------------------------
-- Constant: array of data widths for each target address range
------------------------------------------
constant USER_DWIDTH : integer := 32;
constant USER_RDFIFO_DWIDTH : integer := 32;
constant USER_WRFIFO_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH, -- user logic data width
1 => C_OPB_DWIDTH, -- read FIFO register data width
2 => USER_RDFIFO_DWIDTH, -- read FIFO data width
3 => C_OPB_DWIDTH, -- write FIFO register data width
4 => USER_WRFIFO_DWIDTH -- write FIFO data width
);
------------------------------------------
-- Constant: array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_CE : integer := 2;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_CE), -- user logic number of CEs
1 => 2, -- read FIFO register - 2 CEs
2 => 1, -- read FIFO data - 1 CE
3 => 2, -- write FIFO register - 2 CEs
4 => 1 -- write FIFO data - 1 CE
);
------------------------------------------
-- Constant: array of unique properties for each address range
------------------------------------------
constant USER_RDFIFO_DEPTH : integer := 512;
constant USER_RDFIFO_INCLUDE_PACKET_MODE : boolean := false;
constant USER_RDFIFO_INCLUDE_VACANCY : boolean := true;
constant USER_WRFIFO_DEPTH : integer := 512;
constant USER_WRFIFO_INCLUDE_PACKET_MODE : boolean := false;
constant USER_WRFIFO_INCLUDE_VACANCY : boolean := true;
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0), -- user logic slave space dependent properties (none defined)
1 => (others => 0), -- IPIF read pfifo register dependent properties (none defined)
2 => ( -- IPIF read pfifo data dependent properties
FIFO_CAPACITY_BITS => USER_RDFIFO_DEPTH*USER_RDFIFO_DWIDTH,
WR_WIDTH_BITS => USER_RDFIFO_DWIDTH,
RD_WIDTH_BITS => USER_RDFIFO_DWIDTH,
EXCLUDE_PACKET_MODE => 1-boolean'pos(USER_RDFIFO_INCLUDE_PACKET_MODE),
EXCLUDE_VACANCY => 1-boolean'pos(USER_RDFIFO_INCLUDE_VACANCY),
others => 0),
3 => (others => 0), -- IPIF write pfifo register dependent properties (none defined)
4 => ( -- IPIF write pfifo data dependent properties
FIFO_CAPACITY_BITS => USER_WRFIFO_DEPTH*USER_WRFIFO_DWIDTH,
WR_WIDTH_BITS => USER_WRFIFO_DWIDTH,
RD_WIDTH_BITS => USER_WRFIFO_DWIDTH,
EXCLUDE_PACKET_MODE => 1-boolean'pos(USER_WRFIFO_INCLUDE_PACKET_MODE),
EXCLUDE_VACANCY => 1-boolean'pos(USER_WRFIFO_INCLUDE_VACANCY),
others => 0)
);
------------------------------------------
-- Constant: pipeline mode
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
-- Note:
-- only mode 4, 5, 7 are supported for this release
------------------------------------------
constant PIPELINE_MODEL : integer := 5;
------------------------------------------
-- Constant: user core ID code
------------------------------------------
constant DEV_BLK_ID : integer := 0;
------------------------------------------
-- Constant: enable MIR/Reset register
------------------------------------------
constant DEV_MIR_ENABLE : integer := 0;
------------------------------------------
-- Constant: array of IP interrupt mode
-- 1 = Active-high interrupt condition
-- 2 = Active-low interrupt condition
-- 3 = Active-high pulse interrupt event
-- 4 = Active-low pulse interrupt event
-- 5 = Positive-edge interrupt event
-- 6 = Negative-edge interrupt event
------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
------------------------------------------
-- Constant: enable device burst
------------------------------------------
constant DEV_BURST_ENABLE : integer := 0;
------------------------------------------
-- Constant: include address counter for burst transfers
------------------------------------------
constant INCLUDE_ADDR_CNTR : integer := 0;
------------------------------------------
-- Constant: include write buffer that decouples OPB and IPIC write transactions
------------------------------------------
constant INCLUDE_WR_BUF : integer := 0;
------------------------------------------
-- Constant: index for CS/CE
------------------------------------------
constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0');
signal iIP2RFIFO_WrReq : std_logic := '0';
signal iRFIFO2IP_AlmostFull : std_logic;
signal iRFIFO2IP_Full : std_logic;
signal iRFIFO2IP_Vacancy : std_logic_vector(0 to bits_needed_for_vac(find_ard_id(ARD_ID_ARRAY, IPIF_RDFIFO_DATA), ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA)))-1);
signal iRFIFO2IP_WrAck : std_logic;
signal iIP2WFIFO_RdReq : std_logic := '0';
signal iWFIFO2IP_AlmostEmpty : std_logic;
signal iWFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0');
signal iWFIFO2IP_Empty : std_logic;
signal iWFIFO2IP_Occupancy : std_logic_vector(0 to bits_needed_for_vac(find_ard_id(ARD_ID_ARRAY, IPIF_WRFIFO_DATA), ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA)))-1);
signal iWFIFO2IP_RdAck : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 2;
C_RDFIFO_DWIDTH : integer := 32;
C_RDFIFO_DEPTH : integer := 512;
C_WRFIFO_DWIDTH : integer := 32;
C_WRFIFO_DEPTH : integer := 512
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
TOP_REF_CLK : in std_logic;
RXP : in std_logic;
RXN : in std_logic;
TXP : out std_logic;
TXN : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2RFIFO_WrReq : out std_logic;
IP2RFIFO_Data : out std_logic_vector(0 to C_RDFIFO_DWIDTH-1);
RFIFO2IP_WrAck : in std_logic;
RFIFO2IP_AlmostFull : in std_logic;
RFIFO2IP_Full : in std_logic;
RFIFO2IP_Vacancy : in std_logic_vector(0 to log2(C_RDFIFO_DEPTH));
IP2WFIFO_RdReq : out std_logic;
WFIFO2IP_Data : in std_logic_vector(0 to C_WRFIFO_DWIDTH-1);
WFIFO2IP_RdAck : in std_logic;
WFIFO2IP_AlmostEmpty : in std_logic;
WFIFO2IP_Empty : in std_logic;
WFIFO2IP_Occupancy : in std_logic_vector(0 to log2(C_WRFIFO_DEPTH))
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_a.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sl_DBus,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_retry => Sl_retry,
Sln_toutSup => Sl_toutSup,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_AddrAck => '0',
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh,
IP2RFIFO_Data => iIP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => iIP2RFIFO_WrReq,
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => iRFIFO2IP_AlmostFull,
RFIFO2IP_Full => iRFIFO2IP_Full,
RFIFO2IP_Vacancy => iRFIFO2IP_Vacancy,
RFIFO2IP_WrAck => iRFIFO2IP_WrAck,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => iIP2WFIFO_RdReq,
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => iWFIFO2IP_AlmostEmpty,
WFIFO2IP_Data => iWFIFO2IP_Data,
WFIFO2IP_Empty => iWFIFO2IP_Empty,
WFIFO2IP_Occupancy => iWFIFO2IP_Occupancy,
WFIFO2IP_RdAck => iWFIFO2IP_RdAck,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => iBus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => iBus2IP_Reset
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE,
C_RDFIFO_DWIDTH => USER_RDFIFO_DWIDTH,
C_RDFIFO_DEPTH => USER_RDFIFO_DEPTH,
C_WRFIFO_DWIDTH => USER_WRFIFO_DWIDTH,
C_WRFIFO_DEPTH => USER_WRFIFO_DEPTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
TOP_REF_CLK => iTOP_REF_CLK,
RXP => iRXP,
RXN => iRXN,
TXP => iTXP,
TXN => iTXN,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2RFIFO_WrReq => iIP2RFIFO_WrReq,
IP2RFIFO_Data => iIP2RFIFO_Data,
RFIFO2IP_WrAck => iRFIFO2IP_WrAck,
RFIFO2IP_AlmostFull => iRFIFO2IP_AlmostFull,
RFIFO2IP_Full => iRFIFO2IP_Full,
RFIFO2IP_Vacancy => iRFIFO2IP_Vacancy,
IP2WFIFO_RdReq => iIP2WFIFO_RdReq,
WFIFO2IP_Data => iWFIFO2IP_Data,
WFIFO2IP_RdAck => iWFIFO2IP_RdAck,
WFIFO2IP_AlmostEmpty => iWFIFO2IP_AlmostEmpty,
WFIFO2IP_Empty => iWFIFO2IP_Empty,
WFIFO2IP_Occupancy => iWFIFO2IP_Occupancy
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-2-clause | 12a91349785d9de6250fd107e511fa85 | 0.462185 | 4.443484 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_BarrelShiftAltr.vhd | 8 | 7,592 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_BarrelShiftAltr is
generic (
widthin : natural :=32;
widthd : natural :=5;
pipeline : natural :=1;
ndirection : natural :=0;
use_dedicated_circuitry : natural :=0
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end alt_dspbuilder_BarrelShiftAltr;
architecture SYNTH of alt_dspbuilder_BarrelShiftAltr is
signal resdec : std_logic_vector(widthin-1 downto 0);
signal dxin : std_logic_vector(widthin-1 downto 0);
signal resmult : std_logic_vector(2*widthin downto 0);
signal sdirection : std_logic;
signal direction_dff : std_logic_vector(2 downto 0);
signal resdec_ext : std_logic_vector(widthin downto 0);
signal distance_out : std_logic_vector(widthd-1 downto 0);
signal dist_out_reg : std_logic_vector(widthd-1 downto 0);
signal max_distance : std_logic_vector(widthd-1 downto 0);
signal distance_sum : std_logic_vector(widthd-1 downto 0);
signal no_shift : std_logic;
constant distance_zero : std_logic_vector(widthd-1 downto 0):=(others=>'0');
begin
gsdir1:if ndirection=0 generate
sdirection <='0';
end generate gsdir1;
gsdir2:if ndirection=1 generate
sdirection <= '0' when distance=distance_zero else '1';
end generate gsdir2;
gsdir3:if ndirection=2 generate
sdirection <= '0' when distance=distance_zero else direction;
end generate gsdir3;
gnopipeline:if pipeline=0 generate
gc:if use_dedicated_circuitry>0 generate
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE")
PORT MAP (data => distance_out,
eq => resdec);
U1 : lpm_mult GENERIC MAP (lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP (dataa => resdec_ext,
datab => xin,
result => resmult);
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (
lpm_width => widthd,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0)
port map (
dataa => max_distance,
datab => distance,
result => distance_sum,
cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (sdirection='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gc;
gndc:if use_dedicated_circuitry=0 generate
U0 : lpm_clshift GENERIC MAP (lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ARITHMETIC",
lpm_width => widthin,
lpm_widthdist => widthd)
PORT MAP ( distance => distance,
direction => sdirection,
data => xin,
result => yout);
end generate gndc;
end generate gnopipeline;
gpipeline:if pipeline>0 generate
p:process(clock,aclr)
begin
if aclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif clock'event and clock='1' then
if sclr='1' then
dxin <= (others=>'0');
direction_dff <= (others=>'0');
dist_out_reg <= (others=>'0');
elsif ena='1' then
dxin <= xin ;
direction_dff(2)<= direction_dff(1);
direction_dff(1)<= direction_dff(0);
direction_dff(0)<= sdirection;
dist_out_reg <= distance_out;
end if;
end if;
end process p;
U0 : lpm_decode GENERIC MAP (lpm_width => widthd,
lpm_decodes => widthin,
lpm_type => "LPM_DECODE",
lpm_pipeline => 0)
PORT MAP ( data => dist_out_reg,
eq => resdec);
gndc:if use_dedicated_circuitry=0 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gndc;
gdc:if use_dedicated_circuitry=1 generate
U1 : lpm_mult GENERIC MAP ( lpm_widtha => widthin+1,
lpm_widthb => widthin,
lpm_widthp => 2*widthin+1,
lpm_widths => 1,
lpm_pipeline => 2,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=6")
PORT MAP ( dataa => resdec_ext,
datab => dxin,
clock => clock,
clken => ena,
aclr => aclr,
result => resmult);
end generate gdc;
resdec_ext(widthin-1 downto 0) <= resdec(widthin-1 downto 0);
resdec_ext(widthin) <= '0';
gleft:if ndirection=0 generate
yout(widthin-1 downto 0) <= resmult(widthin-1 downto 0);
distance_out <= distance;
end generate gleft;
grightleft:if ndirection>0 generate
max_distance <= int2ustd(widthin, widthd);
UADD: lpm_add_sub generic map (lpm_width => widthd, lpm_direction => "SUB", lpm_type => "LPM_ADD_SUB", lpm_representation => "UNSIGNED", lpm_pipeline => 0)
port map ( dataa => max_distance, datab => distance, result => distance_sum, cin=>'1');
distance_out(widthd-1 downto 0) <= distance_sum when (sdirection='1') else distance;
yout(widthin-1 downto 0) <= resmult(2*widthin-1 downto widthin) when (direction_dff(2)='1') else resmult(widthin-1 downto 0);
end generate grightleft;
end generate gpipeline;
end SYNTH;
| mit | b3eb7dcff05c29cf39d48dc2c51d59d0 | 0.623946 | 3.334212 | false | false | false | false |
Andy46/OV7670-VHDL | OV7670/src/mod_VGA/Divisor4.vhd | 1 | 1,320 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:32:05 11/08/2013
-- Design Name:
-- Module Name: Divisor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Divisor4 is
port (clk_in, reset : in std_logic;
clk_out : out std_logic);
end Divisor4;
architecture Behavioral of Divisor4 is
signal clk_aux : std_logic;
signal count : std_logic;
begin
clk_out <= clk_aux;
process(clk_in, clk_aux, reset)
begin
if clk_in'event and clk_in = '1' then
if reset = '0' then
clk_aux <= '0';
count <= '0';
else
count <= not count;
if count = '1' then
clk_aux <= not clk_aux;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 69783c911ad4ad810a1013822afb63af | 0.578788 | 3.529412 | false | false | false | false |
inmcm/Simon_Speck_Ciphers | VHDL/Speck_Constants.vhd | 3 | 2,745 | -- Speck_Constants.vhd
-- Copyright 2016 Michael Calvin McCoy
-- [email protected]
-- see LICENSE.md
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package SPECK_CONSTANTS is
function Round_Count_Lookup(key_size,block_size : integer range 0 to 256) return integer;
function Beta_Lookup(key_size,block_size : integer range 0 to 256) return integer;
function Alpha_Lookup(key_size,block_size : integer range 0 to 256) return integer;
end SPECK_CONSTANTS;
package body SPECK_CONSTANTS is
function Round_Count_Lookup(key_size,block_size : integer range 0 to 256) return integer is
variable round_count_tmp : integer range 0 to 63 := 0;
begin
-- Block Size 32 and Key Size 64 use 22 rounds
if (BLOCK_SIZE = 32 and KEY_SIZE = 64) then
round_count_tmp := 22;
-- Block Size 48 and Key Size 72 use 22 rounds
elsif (BLOCK_SIZE = 48 and KEY_SIZE = 72) then
round_count_tmp := 22;
-- Block Size 48 and Key Size 96 use 23 rounds
elsif (BLOCK_SIZE = 48 and KEY_SIZE = 96) then
round_count_tmp := 23;
-- Block Size 64 and Key Size 96 use 26 rounds
elsif (BLOCK_SIZE = 64 and KEY_SIZE = 96 ) then
round_count_tmp := 26;
-- Block Size 64 and Key Size 128 use 27 rounds
elsif (BLOCK_SIZE = 64 and KEY_SIZE = 128) then
round_count_tmp := 27;
-- Block Size 96 and Key Size 96 use 28 rounds
elsif (BLOCK_SIZE = 96 and KEY_SIZE = 96) then
round_count_tmp := 28;
-- Block Size 96 and Key Size 144 use 29 rounds
elsif (BLOCK_SIZE = 96 and KEY_SIZE = 144) then
round_count_tmp := 29;
-- Block Size 128 and Key Size 128 use 32 rounds
elsif (BLOCK_SIZE = 128 and KEY_SIZE = 128) then
round_count_tmp := 32;
-- Block Size 128 and Key Size 192 used 33 rounds
elsif (BLOCK_SIZE = 128 and KEY_SIZE = 192) then
round_count_tmp := 33;
-- Block Size 128 and Key Size 256 use 34 rounds
elsif (BLOCK_SIZE = 128 and KEY_SIZE = 256) then
round_count_tmp := 34;
end if;
return round_count_tmp;
end Round_Count_Lookup;
function Beta_Lookup(key_size,block_size : integer range 0 to 256) return integer is
variable b_tmp : integer range 0 to 3 := 0;
begin
-- Block Size 32 and Key Size 64 use beta rotate 2 bits
if (BLOCK_SIZE = 32 and KEY_SIZE = 64) then
b_tmp := 2;
-- All other key/block combinations use beta rotate 3 bits
else
b_tmp := 3;
end if;
return b_tmp;
end Beta_Lookup;
function Alpha_Lookup(key_size,block_size : integer range 0 to 256) return integer is
variable a_tmp : integer range 0 to 15 := 0;
begin
-- Block Size 32 and Key Size 64 use alpha rotate 7 bits
if (BLOCK_SIZE = 32 and KEY_SIZE = 64) then
a_tmp := 7;
-- All other key/block combinations use alpha rotate 8 bits
else
a_tmp := 8;
end if;
return a_tmp;
end Alpha_Lookup;
end SPECK_CONSTANTS; | mit | 4b884fdef95f6d94b4b3381b491a7969 | 0.693989 | 3.140732 | false | false | false | false |
estradjm/Class-Work | HDL/Traffic Intersection/ControlTraffic.vhdl | 1 | 6,454 | Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity TrafficControl is
PORT (EffClock: IN STD_LOGIC;
Clock : IN STD_LOGIC;
crosswalktraffic : IN STD_LOGIC;
lowpriortraffic : IN STD_LOGIC;
reset : IN STD_LOGIC;
HIP : OUT STD_LOGIC;
LOWP : OUT STD_LOGIC;
PED : OUT STD_LOGIC;
HiDone : OUT STD_LOGIC;
LowDone : OUT STD_LOGIC;
PedDone : OUT STD_LOGIC;
HiCount : OUT STD_LOGIC_VECTOR (3 downto 0);
LowCount : OUT STD_LOGIC_VECTOR (3 downto 0);
PedCount : OUT STD_LOGIC_VECTOR (3 downto 0));
end TrafficControl;
architecture Behavioral of TrafficControl is
type State is (HighPriority, LowPriority, Pedestrian, COUNTDOWN5Ped, COUNTDOWN5Low, L2Ped);
signal CurrentState , NextState : State;
signal countdown9 : std_logic_vector (3 downto 0);
signal countdown4 : std_logic_vector (3 downto 0);
signal countdown5 : std_logic_vector (3 downto 0);
signal resetsig : std_logic;
signal HiEnable : std_logic;
signal LowEnable : std_logic;
signal PedEnable : std_logic;
signal register5 : std_logic;
signal register9 : std_logic;
signal register4 : std_logic;
signal trip5 : std_logic;
signal trip9 : std_logic;
signal trip4 : std_logic;
signal Go2Ped : std_logic;
begin
HiCount <= countdown5;
LowCount <= countdown9;
PedCount <= countdown4;
resetsig <= reset;
Works : process (Go2Ped, reset, CurrentState, countdown4, countdown5, countdown9, NextState, crosswalktraffic, lowpriortraffic, Clock)
begin
case CurrentState is
when HighPriority =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HIenable <= '0';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '1';
trip4 <= '1';
trip9 <= '1';
Go2Ped <= '0';
if crosswalktraffic = '1' then
NextState <= COUNTDOWN5Ped;
elsif lowpriortraffic = '1' then
NextState <= COUNTDOWN5Low;
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when Pedestrian =>
NextState <= CurrentState;
HIP <= '0';
LOWP <= '0';
PED <= '1';
HiDone <= '1';
LowDone <= '1';
PedDone <= '0';
HIenable <= '0';
LowEnable <= '0';
PedEnable <= '1';
trip4 <= '0';
Go2Ped <= '0';
if countdown4 = 0 and lowpriortraffic = '1' then
NextState <= LowPriority;
trip4 <= '1';
elsif countdown4 = 0 and lowpriortraffic = '0' then
NextState <= HighPriority;
trip4 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when LowPriority =>
NextState <= CurrentState;
HIP <= '0';
LOWP <= '1';
PED <= '0';
HiDone <= '1';
LowDone <= '0';
PEDdone <= '1';
HiEnable <= '0';
LowEnable <= '1';
PedEnable <= '0';
trip9 <= '0';
if countdown9 = 0 and Go2Ped = '0' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
elsif countdown9 = 0 and Go2Ped = '1' then
NextState <= L2Ped;
trip4 <='1';
trip5 <='1';
trip9 <='1';
elsif crosswalktraffic = '1' then
Go2Ped <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when COUNTDOWN5Ped =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '0';
Go2Ped <= '0';
if countdown5 = 0 then
NextState <= pedestrian;
trip5 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when COUNTDOWN5low =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '0';
Go2Ped <= '0';
if countdown5 = 0 then
NextState <= LowPriority;
trip5 <='1';
elsif crosswalktraffic = '1' then
NextState <= COUNTDOWN5Ped;
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when L2Ped =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5<='0';
if countdown5 = 0 then
NextState <= Pedestrian;
trip5 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
end case;
end process;
CountDOWN5Down : process (EffClock, HiEnable, resetsig, countdown5, trip5)
begin
if register5 = '1' or resetsig = '1' then
countdown5 <= "0101";
elsif (RISING_EDGE (EffClock)) and HiEnable = '1' THEN
if countdown5 = 0 then
countdown5 <= "0101";
else
countdown5 <= countdown5 - 1;
end if;
end if;
end process;
count9Down : process (EffClock, LowEnable, resetsig, countdown9, trip9)
begin
if register9 = '1' or resetsig = '1' then
countdown9 <= "1001";
elsif (Rising_Edge(EffClock)) and LowEnable = '1' THEN
if countdown9 = 0 then
countdown9 <= "1001";
else
countdown9 <= countdown9 - 1;
end if;
end if;
end process;
count4Down : process (EffClock, PedEnable, resetsig, countdown4, trip4)
begin
if register4 = '1' or resetsig = '1' then
countdown4 <= "0100";
elsif (rising_edge (EffClock)) and PedEnable = '1' THEN
if countdown4 = 0 then
countdown4 <= "0100";
else
countdown4 <= countdown4 - 1;
end if;
end if;
end process;
PROCESS(Clock)
begin
IF Rising_Edge(Clock) THEN
CurrentState <= NextState;
register5 <= trip5;
register4 <= trip4;
register9 <= trip9;
END IF;
END PROCESS;
end Behavioral; | apache-2.0 | c724cc65d5436fcbf08d320ea404bd91 | 0.544469 | 3.088038 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/jpeg_encoder/design/JpegEnc.vhd | 3 | 19,969 | -------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- IMAGE RAM
iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
iram_wren : in std_logic;
iram_fifo_afull : out std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0);
outif_almost_full : in std_logic;
--debug signal
frame_size : out std_logic_vector(23 downto 0)
);
end entity JpegEnc;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
signal qdata : std_logic_vector(7 downto 0);
signal qaddr : std_logic_vector(6 downto 0);
signal qwren : std_logic;
signal jpeg_ready : std_logic;
signal jpeg_busy : std_logic;
signal outram_base_addr : std_logic_vector(9 downto 0);
signal num_enc_bytes : std_logic_vector(23 downto 0);
signal img_size_x : std_logic_vector(15 downto 0);
signal img_size_y : std_logic_vector(15 downto 0);
signal sof : std_logic;
signal jpg_iram_rden : std_logic;
signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);
signal jpg_iram_rdata : std_logic_vector(23 downto 0);
signal fdct_start : std_logic;
signal fdct_ready : std_logic;
signal zig_start : std_logic;
signal zig_ready : std_logic;
signal qua_start : std_logic;
signal qua_ready : std_logic;
signal rle_start : std_logic;
signal rle_ready : std_logic;
signal huf_start : std_logic;
signal huf_ready : std_logic;
signal bs_start : std_logic;
signal bs_ready : std_logic;
signal zz_buf_sel : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal zz_data : std_logic_vector(11 downto 0);
signal rle_buf_sel : std_logic;
signal rle_rdaddr : std_logic_vector(5 downto 0);
signal rle_data : std_logic_vector(11 downto 0);
signal qua_buf_sel : std_logic;
signal qua_rdaddr : std_logic_vector(5 downto 0);
signal qua_data : std_logic_vector(11 downto 0);
signal huf_buf_sel : std_logic;
signal huf_rdaddr : std_logic_vector(5 downto 0);
signal huf_rden : std_logic;
signal huf_runlength : std_logic_vector(3 downto 0);
signal huf_size : std_logic_vector(3 downto 0);
signal huf_amplitude : std_logic_vector(11 downto 0);
signal huf_dval : std_logic;
signal bs_buf_sel : std_logic;
signal bs_fifo_empty : std_logic;
signal bs_rd_req : std_logic;
signal bs_packed_byte : std_logic_vector(7 downto 0);
signal huf_fifo_empty : std_logic;
signal zz_rden : std_logic;
signal fdct_sm_settings : T_SM_SETTINGS;
signal zig_sm_settings : T_SM_SETTINGS;
signal qua_sm_settings : T_SM_SETTINGS;
signal rle_sm_settings : T_SM_SETTINGS;
signal huf_sm_settings : T_SM_SETTINGS;
signal bs_sm_settings : T_SM_SETTINGS;
signal image_size_reg : std_logic_vector(31 downto 0);
signal jfif_ram_byte : std_logic_vector(7 downto 0);
signal jfif_ram_wren : std_logic;
signal jfif_ram_wraddr : std_logic_vector(23 downto 0);
signal out_mux_ctrl : std_logic;
signal img_size_wr : std_logic;
signal jfif_start : std_logic;
signal jfif_ready : std_logic;
signal bs_ram_byte : std_logic_vector(7 downto 0);
signal bs_ram_wren : std_logic;
signal bs_ram_wraddr : std_logic_vector(23 downto 0);
signal jfif_eoi : std_logic;
signal fdct_fifo_rd : std_logic;
signal fdct_fifo_q : std_logic_vector(23 downto 0);
signal fdct_fifo_hf_full : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Host Interface
-------------------------------------------------------------------
U_HostIF : entity work.HostIF
port map
(
CLK => CLK,
RST => RST,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- Quantizer RAM
qdata => qdata,
qaddr => qaddr,
qwren => qwren,
-- CTRL
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- ByteStuffer
outram_base_addr => outram_base_addr,
num_enc_bytes => num_enc_bytes,
-- global
img_size_x => img_size_x,
img_size_y => img_size_y,
img_size_wr => img_size_wr,
sof => sof
);
-------------------------------------------------------------------
-- BUF_FIFO
-------------------------------------------------------------------
U_BUF_FIFO : entity work.BUF_FIFO
port map
(
CLK => CLK,
RST => RST,
-- HOST PROG
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof,
-- HOST DATA
iram_wren => iram_wren,
iram_wdata => iram_wdata,
fifo_almost_full => iram_fifo_afull,
-- FDCT
fdct_fifo_rd => fdct_fifo_rd,
fdct_fifo_q => fdct_fifo_q,
fdct_fifo_hf_full => fdct_fifo_hf_full
);
-------------------------------------------------------------------
-- Controller
-------------------------------------------------------------------
U_CtrlSM : entity work.CtrlSM
port map
(
CLK => CLK,
RST => RST,
-- output IF
outif_almost_full => outif_almost_full,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- FDCT
fdct_start => fdct_start,
fdct_ready => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- ZIGZAG
zig_start => zig_start,
zig_ready => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_start => qua_start,
qua_ready => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_start => rle_start,
rle_ready => rle_ready,
rle_sm_settings => rle_sm_settings,
-- Huffman
huf_start => huf_start,
huf_ready => huf_ready,
huf_sm_settings => huf_sm_settings,
-- ByteStuffdr
bs_start => bs_start,
bs_ready => bs_ready,
bs_sm_settings => bs_sm_settings,
-- JFIF GEN
jfif_start => jfif_start,
jfif_ready => jfif_ready,
jfif_eoi => jfif_eoi,
-- OUT MUX
out_mux_ctrl => out_mux_ctrl
);
-------------------------------------------------------------------
-- FDCT
-------------------------------------------------------------------
U_FDCT : entity work.FDCT
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => fdct_start,
ready_pb => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- BUF_FIFO
bf_fifo_rd => fdct_fifo_rd,
bf_fifo_q => fdct_fifo_q,
bf_fifo_hf_full => fdct_fifo_hf_full,
-- ZIG ZAG
zz_buf_sel => zz_buf_sel,
zz_rd_addr => zz_rd_addr,
zz_data => zz_data,
zz_rden => zz_rden,
-- HOST
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof
);
-------------------------------------------------------------------
-- ZigZag top level
-------------------------------------------------------------------
U_ZZ_TOP : entity work.ZZ_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => zig_start,
ready_pb => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_buf_sel => qua_buf_sel,
qua_rdaddr => qua_rdaddr,
qua_data => qua_data,
-- FDCT
fdct_buf_sel => zz_buf_sel,
fdct_rd_addr => zz_rd_addr,
fdct_data => zz_data,
fdct_rden => zz_rden
);
-------------------------------------------------------------------
-- Quantizer top level
-------------------------------------------------------------------
U_QUANT_TOP : entity work.QUANT_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => qua_start,
ready_pb => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_buf_sel => rle_buf_sel,
rle_rdaddr => rle_rdaddr,
rle_data => rle_data,
-- ZIGZAG
zig_buf_sel => qua_buf_sel,
zig_rd_addr => qua_rdaddr,
zig_data => qua_data,
-- HOST
qdata => qdata,
qaddr => qaddr,
qwren => qwren
);
-------------------------------------------------------------------
-- RLE TOP
-------------------------------------------------------------------
U_RLE_TOP : entity work.RLE_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => rle_start,
ready_pb => rle_ready,
rle_sm_settings => rle_sm_settings,
-- HUFFMAN
huf_buf_sel => huf_buf_sel,
huf_rden => huf_rden,
huf_runlength => huf_runlength,
huf_size => huf_size,
huf_amplitude => huf_amplitude,
huf_dval => huf_dval,
huf_fifo_empty => huf_fifo_empty,
-- Quantizer
qua_buf_sel => rle_buf_sel,
qua_rd_addr => rle_rdaddr,
qua_data => rle_data,
-- HostIF
sof => sof
);
-------------------------------------------------------------------
-- Huffman Encoder
-------------------------------------------------------------------
U_Huffman : entity work.Huffman
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => huf_start,
ready_pb => huf_ready,
huf_sm_settings => huf_sm_settings,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
-- RLE
rle_buf_sel => huf_buf_sel,
rd_en => huf_rden,
runlength => huf_runlength,
VLI_size => huf_size,
VLI => huf_amplitude,
d_val => huf_dval,
rle_fifo_empty => huf_fifo_empty,
-- Byte Stuffer
bs_buf_sel => bs_buf_sel,
bs_fifo_empty => bs_fifo_empty,
bs_rd_req => bs_rd_req,
bs_packed_byte => bs_packed_byte
);
-------------------------------------------------------------------
-- Byte Stuffer
-------------------------------------------------------------------
U_ByteStuffer : entity work.ByteStuffer
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => bs_start,
ready_pb => bs_ready,
-- HOST IF
sof => sof,
num_enc_bytes => num_enc_bytes,
outram_base_addr => outram_base_addr,
-- Huffman
huf_buf_sel => bs_buf_sel,
huf_fifo_empty => bs_fifo_empty,
huf_rd_req => bs_rd_req,
huf_packed_byte => bs_packed_byte,
-- OUT RAM
ram_byte => bs_ram_byte,
ram_wren => bs_ram_wren,
ram_wraddr => bs_ram_wraddr
);
--debug signal
frame_size <= num_enc_bytes;
-------------------------------------------------------------------
-- JFIF Generator
-------------------------------------------------------------------
U_JFIFGen : entity work.JFIFGen
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start => jfif_start,
ready => jfif_ready,
eoi => jfif_eoi,
-- ByteStuffer
num_enc_bytes => num_enc_bytes,
-- HOST IF
qwren => qwren,
qwaddr => qaddr,
qwdata => qdata,
image_size_reg => image_size_reg,
image_size_reg_wr => img_size_wr,
-- OUT RAM
ram_byte => jfif_ram_byte,
ram_wren => jfif_ram_wren,
ram_wraddr => jfif_ram_wraddr
);
image_size_reg <= img_size_x & img_size_y;
-------------------------------------------------------------------
-- OutMux
-------------------------------------------------------------------
U_OutMux : entity work.OutMux
port map
(
CLK => CLK,
RST => RST,
-- CTRL
out_mux_ctrl => out_mux_ctrl,
-- ByteStuffer
bs_ram_byte => bs_ram_byte,
bs_ram_wren => bs_ram_wren,
bs_ram_wraddr => bs_ram_wraddr,
-- ByteStuffer
jfif_ram_byte => jfif_ram_byte,
jfif_ram_wren => jfif_ram_wren,
jfif_ram_wraddr => jfif_ram_wraddr,
-- OUT RAM
ram_byte => ram_byte,
ram_wren => ram_wren,
ram_wraddr => ram_wraddr
);
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
| bsd-2-clause | 0f06f716c3686366007c61982056ae05 | 0.385948 | 4.620315 | false | false | false | false |
inmcm/Simon_Speck_Ciphers | VHDL/Simon.vhd | 1 | 10,197 | -- Simon.vhd
-- Copyright 2016 Michael Calvin McCoy
-- [email protected]
-- see LICENSE.md
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.SIMON_CONSTANTS.all;
entity SIMON_CIPHER is
Generic(KEY_SIZE : integer range 0 to 256 := 256;
BLOCK_SIZE : integer range 0 to 128 := 128;
ROUND_LIMIT: integer range 0 to 72 := 72);
Port (SYS_CLK,RST : in std_logic;
BUSY : out std_logic;
CONTROL : in std_logic_vector(1 downto 0);
KEY : in std_logic_vector (KEY_SIZE - 1 downto 0);
BLOCK_INPUT : in std_logic_vector (BLOCK_SIZE - 1 downto 0);
BLOCK_OUTPUT : out std_logic_vector (BLOCK_SIZE - 1 downto 0));
end SIMON_CIPHER;
architecture Behavioral of SIMON_CIPHER is
-------------------------------------------------------------
-- Cipher Constants
constant WORD_SIZE : integer range 0 to 64 := BLOCK_SIZE / 2;
constant K_SEGMENTS : integer range 0 to 4 := KEY_SIZE / WORD_SIZE;
constant ROUND_CONSTANT_HI : std_logic_vector(WORD_SIZE - 5 downto 0) := (OTHERS => '1');
constant ROUND_CONSTANT_LO : std_logic_vector(3 downto 0) := X"C";
-------------------------------------------------------------
signal ZJ : std_logic_vector(61 downto 0);
signal z_shift : std_logic_vector(61 downto 0);
-- Key Schedule Storage Array
type ARRAY_ROUNDxWORDSIZE is array(0 to (ROUND_LIMIT - 1)) of std_logic_vector(WORD_SIZE - 1 downto 0);
signal key_schedule: ARRAY_ROUNDxWORDSIZE;
signal round_key : std_logic_vector(WORD_SIZE - 1 downto 0);
signal round_constant : std_logic_vector(WORD_SIZE - 1 downto 0);
type ARRAY_PARTKEYxWORD is array (0 to K_SEGMENTS-1) of std_logic_vector(WORD_SIZE - 1 downto 0);
signal key_gen : ARRAY_PARTKEYxWORD;
signal cipher_direction : std_logic;
------------------------------------------------------
-- Fiestel Structure Signals
signal b_buf : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal a_buf : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal b_lft1 : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal b_lft8 : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal b_lft2 : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal b_and : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal b_xor : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal a_xor : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal key_xor : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
--------------------------------------------------------
--------------------------------------------------------
-- Key Generation Signals
signal key_temp_1 : std_logic_vector(WORD_SIZE -1 downto 0);
signal key_temp_2 : std_logic_vector(WORD_SIZE -1 downto 0);
signal rs3 : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal rs1 : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal zji : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
type state is (Reset,Idle,Key_Schedule_Generation_Run,Key_Schedule_Generation_Finish,
Cipher_Start,Cipher_Run,Cipher_Finish_1,Cipher_Finish_2,Cipher_Latch);
signal pr_state,nx_state : state;
signal round_count : integer range 0 to (ROUND_LIMIT - 1);
signal inv_round_count : integer range 0 to (ROUND_LIMIT - 1);
signal round_count_mux : integer range 0 to (ROUND_LIMIT - 1);
signal key_feedback : std_logic_vector(WORD_SIZE - 1 downto 0);
begin
----------------------------------------------------------------------
-- State Machine Processes
----------------------------------------------------------------------
State_Machine_Head : process (SYS_CLK) ----State Machine Master Control
begin
if (SYS_CLK'event and SYS_CLK='1') then
if (RST = '1') then
pr_state <= RESET;
else
pr_state <= nx_state;
end if;
end if;
end process; -- State_Machine_Head
State_Machine_Body : process (CONTROL, round_count, pr_state) ---State Machine State Definitions
begin
case pr_state is
when Reset => --Master Reset State
nx_state <= Idle;
when Idle =>
if (CONTROL = "01") then
nx_state <= Key_Schedule_Generation_Run;
elsif (CONTROL = "11" or CONTROL = "10") then
nx_state <= Cipher_Start;
else
nx_state <= Idle;
end if;
when Key_Schedule_Generation_Run =>
if (round_count = ROUND_LIMIT - 2) then
nx_state <= Key_Schedule_Generation_Finish;
else
nx_state <= Key_Schedule_Generation_Run;
end if;
when Key_Schedule_Generation_Finish =>
nx_state <= Idle;
when Cipher_Start =>
nx_state <= Cipher_Run;
when Cipher_Run =>
if (round_count = ROUND_LIMIT - 2) then
nx_state <= Cipher_Finish_1;
else
nx_state <= Cipher_Run;
end if;
when Cipher_Finish_1 =>
nx_state <= Cipher_Finish_2;
when Cipher_Finish_2 =>
nx_state <= Cipher_Latch;
when Cipher_Latch =>
nx_state <= Idle;
end case;
end process;
----------------------------------------------------------------------
-- END State Machine Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Register Processes
----------------------------------------------------------------------
Cipher_Direction_Flag : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Reset) then
cipher_direction <= '0';
elsif (pr_state = Idle) then
cipher_direction <= CONTROL(0);
end if ;
end if;
end process;
Busy_Flag_Generator : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Reset or (pr_state = Idle and CONTROL /= "00")) then
BUSY <= '1';
elsif ((pr_state = Idle and CONTROL = "00") or pr_state = Cipher_Latch or pr_state = Key_Schedule_Generation_Finish) then
BUSY <= '0';
end if;
end if;
end process ; -- Busy_Flag_Generator
Key_Schedule_Generator : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Idle) then
Init_Gen_Regs : for i in 0 to (K_SEGMENTS-1) loop
key_gen(i) <= key(((i + 1) * WORD_SIZE) - 1 downto (i * WORD_SIZE));
end loop ; -- Update_Gen_Regs
z_shift <= ZJ;
elsif (pr_state = Key_Schedule_Generation_Run or pr_state = Key_Schedule_Generation_Finish) then
key_gen(K_SEGMENTS-1) <= key_feedback;
for i in 0 to (K_SEGMENTS-2) loop
key_gen(i) <= key_gen(i+1);
end loop ;
z_shift <= z_shift(0) & z_shift(61 downto 1);
end if;
end if;
end process ; -- Key_Schedule_Generator
Fiestel_Round : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Idle) then
-- Load for Encryption
if (CONTROL = "11") then
a_buf <= BLOCK_INPUT(WORD_SIZE - 1 downto 0);
b_buf <= BLOCK_INPUT(BLOCK_SIZE - 1 downto WORD_SIZE);
-- Load for Decryption
elsif (CONTROL = "10") then
a_buf <= BLOCK_INPUT(BLOCK_SIZE - 1 downto WORD_SIZE);
b_buf <= BLOCK_INPUT(WORD_SIZE - 1 downto 0);
end if;
-- Run Cipher Engine
elsif (pr_state = Cipher_Run or pr_state = Cipher_Finish_1 or pr_state = Cipher_Finish_2) then
a_buf <= b_buf;
b_buf <= key_xor;
end if;
end if;
end process ; -- Fiestel_Round
Output_Buffer : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Cipher_Latch) then
if (cipher_direction = '1') then
BLOCK_OUTPUT <= b_buf & a_buf;
else
BLOCK_OUTPUT <= a_buf & b_buf;
end if;
end if;
end if;
end process ; -- Output_Buffer
----------------------------------------------------------------------
-- END Register Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- RAM Processes
----------------------------------------------------------------------
Key_Schedule_Array: process (SYS_CLK)
begin
if (SYS_CLK'event and SYS_CLK = '1') then
round_key <= key_schedule(round_count_mux);
if (pr_state = Key_Schedule_Generation_Run or pr_state = Key_Schedule_Generation_Finish) then
key_schedule(round_count) <= key_gen(0);
end if;
end if;
end process;
----------------------------------------------------------------------
-- End RAM Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Counter Processes
----------------------------------------------------------------------
Round_Counter : process(SYS_CLK)
begin
if (SYS_CLK'event and SYS_CLK = '1') then
if (pr_state = Reset) then
round_count <= 0;
inv_round_count <= 0;
elsif (pr_state = Idle) then
round_count <= 0;
inv_round_count <= ROUND_LIMIT - 1;
elsif (pr_state = Cipher_Start or pr_state = Cipher_Run or pr_state = Key_Schedule_Generation_Run) then
round_count <= round_count + 1;
inv_round_count <= inv_round_count - 1;
end if ;
end if ;
end process;
----------------------------------------------------------------------
-- END Counter Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Async Signals
----------------------------------------------------------------------
ZJ <= Z_Array_Lookup(KEY_SIZE,BLOCK_SIZE);
round_count_mux <= round_count when cipher_direction = '1' else inv_round_count;
-- Fiestel Round
b_lft1 <= b_buf((WORD_SIZE - 2) downto 0) & b_buf(WORD_SIZE - 1);
b_lft8 <= b_buf((WORD_SIZE - 9) downto 0) & b_buf(WORD_SIZE - 1 downto (WORD_SIZE- 8));
b_lft2 <= b_buf((WORD_SIZE - 3) downto 0) & b_buf(WORD_SIZE - 1 downto (WORD_SIZE- 2));
b_and <= b_lft1 and b_lft8;
b_xor <= b_and xor b_lft2;
a_xor <= a_buf xor b_xor;
key_xor <= round_key xor a_xor;
-- Key Schedule Generation Logic
rs3 <= key_gen(K_SEGMENTS - 1)(2 downto 0) & key_gen(K_SEGMENTS - 1)(WORD_SIZE - 1 downto 3);
Key_Feedback_1 : if (K_SEGMENTS /= 4) generate
begin
key_temp_1 <= rs3;
end generate;
Key_Feedback_2 : if (K_SEGMENTS = 4) generate
begin
key_temp_1 <= rs3 xor key_gen(1);
end generate;
rs1 <= key_temp_1(0) & key_temp_1(WORD_SIZE - 1 downto 1);
key_temp_2 <= (key_gen(0) xor key_temp_1) xor rs1;
round_constant <= ROUND_CONSTANT_HI & ROUND_CONSTANT_LO;
zji <= round_constant(WORD_SIZE - 1 downto 1) & z_shift(0);
key_feedback <= key_temp_2 xor zji;
end Behavioral;
| mit | 05a0d0d6923a074b0ba33b8b5969a61e | 0.557615 | 3.35759 | false | false | false | false |
ymei/TMSPlane | Firmware/src/gig_eth/KC705/gig_eth.vhd | 1 | 49,364 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the VHDL example design for the Tri-Mode
-- Ethernet MAC core. It is intended that this example design
-- can be quickly adapted and downloaded onto an FPGA to provide
-- a real hardware test environment.
--
-- This level:
--
-- * Instantiates the FIFO Block wrapper, containing the
-- block level wrapper and an RX and TX FIFO with an
-- AXI-S interface;
--
-- * Instantiates a simple AXI-S example design,
-- providing an address swap and a simple
-- loopback function;
--
-- * Instantiates transmitter clocking circuitry
-- -the User side of the FIFOs are clocked at gtx_clk
-- at all times
--
-- * Instantiates a state machine which drives the AXI Lite
-- interface to bring the TEMAC up in the correct state
--
-- * Serializes the Statistics vectors to prevent logic being
-- optimized out
--
-- * Ties unused inputs off to reduce the number of IO
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Tri-Mode Ethernet MAC User Gude for further information.
--
--
-- --------------------------------------------------
-- | EXAMPLE DESIGN WRAPPER |
-- | |
-- | |
-- | ------------------- ------------------- |
-- | | | | | |
-- | | Clocking | | Resets | |
-- | | | | | |
-- | ------------------- ------------------- |
-- | -------------------------------------|
-- | |FIFO BLOCK WRAPPER |
-- | | |
-- | | |
-- | | ----------------------|
-- | | | SUPPORT LEVEL |
-- | -------- | | |
-- | | | | | |
-- | | AXI |->|------------->| |
-- | | LITE | | | |
-- | | SM | | | |
-- | | |<-|<-------------| |
-- | | | | | |
-- | -------- | | |
-- | | | |
-- | -------- | ---------- | |
-- | | | | | | | |
-- | | |->|->| |->| |
-- | | PAT | | | | | |
-- | | GEN | | | | | |
-- | |(ADDR | | | AXI-S | | |
-- | | SWAP)| | | FIFO | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | |<-|<-| |<-| |
-- | | | | | | | |
-- | -------- | ---------- | |
-- | | | |
-- | | ----------------------|
-- | -------------------------------------|
-- --------------------------------------------------
--------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.com5402pkg.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example_design level wrapper.
--------------------------------------------------------------------------------
entity gig_eth is
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- clocks
gtx_clk : in std_logic; -- 125MHz
ref_clk : in std_logic; -- 200MHz
-- PHY interface
phy_resetn : out std_logic;
-- RGMII Interface
------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- TCP
MAC_ADDR : IN std_logic_vector(47 DOWNTO 0);
IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0);
IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0);
SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0);
GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0);
TCP_CONNECTION_RESET : IN std_logic;
TX_TDATA : IN std_logic_vector(7 downto 0);
TX_TVALID : IN std_logic;
TX_TREADY : OUT std_logic;
RX_TDATA : OUT std_logic_vector(7 downto 0);
RX_TVALID : OUT std_logic;
RX_TREADY : IN std_logic;
-- FIFO
TCP_USE_FIFO : IN std_logic;
TX_FIFO_WRCLK : IN std_logic;
TX_FIFO_Q : IN std_logic_vector(31 downto 0);
TX_FIFO_WREN : IN std_logic;
TX_FIFO_FULL : OUT std_logic;
RX_FIFO_RDCLK : IN std_logic;
RX_FIFO_Q : OUT std_logic_vector(31 downto 0);
RX_FIFO_RDEN : IN std_logic;
RX_FIFO_EMPTY : OUT std_logic;
--
TX_FIFO1_WRCLK : IN std_logic;
TX_FIFO1_Q : IN std_logic_vector(31 downto 0);
TX_FIFO1_WREN : IN std_logic;
TX_FIFO1_FULL : OUT std_logic;
RX_FIFO1_RDCLK : IN std_logic;
RX_FIFO1_Q : OUT std_logic_vector(31 downto 0);
RX_FIFO1_RDEN : IN std_logic;
RX_FIFO1_EMPTY : OUT std_logic
);
end gig_eth;
architecture wrapper of gig_eth is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
COMPONENT COM5402 IS
GENERIC (
CLK_FREQUENCY : integer := 125;
-- CLK frequency in MHz. Needed to compute actual delays.
TX_IDLE_TIMEOUT : integer RANGE 0 TO 50 := 50;
-- inactive input timeout, expressed in 4us units. -- 50*4us = 200us
-- Controls the transmit stream segmentation: data in the elastic buffer will be transmitted if
-- no input is received within TX_IDLE_TIMEOUT, without waiting for the transmit frame to be filled with MSS data bytes.
SIMULATION : std_logic := '0'
-- 1 during simulation with Wireshark .cap file, '0' otherwise
-- Wireshark many not be able to collect offloaded checksum computations.
-- when SIMULATION = '1': (a) IP header checksum is valid if 0000,
-- (b) TCP checksum computation is forced to a valid 00001 irrespective of the 16-bit checksum
-- captured by Wireshark.
);
PORT (
--//-- CLK, RESET
CLK : IN std_logic;
-- All signals are synchronous with CLK
-- CLK must be a global clock 125 MHz or faster to match the Gbps MAC speed.
ASYNC_RESET : IN std_logic; -- to be phased out. replace with SYNC_RESET
SYNC_RESET : IN std_logic;
--//-- CONFIGURATION
-- configuration signals are synchonous with CLK
-- Synchronous with CLK clock.
MAC_ADDR : IN std_logic_vector(47 DOWNTO 0);
IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0);
IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0);
SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0);
GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0);
-- local IP address. 4 bytes for IPv4, 16 bytes for IPv6
-- Natural order (MSB) 172.16.1.128 (LSB) as transmitted in the IP frame.
--// User-initiated connection reset for stream I
CONNECTION_RESET : IN std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
--//-- Protocol -> Transmit MAC Interface
-- 32-bit CRC is automatically appended by the MAC layer. User should not supply it.
-- Synchonous with the user-side CLK
MAC_TX_DATA : OUT std_logic_vector(7 DOWNTO 0);
-- MAC reads the data at the rising edge of CLK when MAC_TX_DATA_VALID = '1'
MAC_TX_DATA_VALID : OUT std_logic;
-- data valid
MAC_TX_SOF : out std_logic;
-- start of frame: '1' when sending the first byte.
MAC_TX_EOF : OUT std_logic;
-- '1' when sending the last byte in a packet to be transmitted.
-- Aligned with MAC_TX_DATA_VALID
MAC_TX_CTS : IN std_logic;
-- MAC-generated Clear To Send flow control signal, indicating room in the
-- MAC tx elastic buffer for a complete maximum size frame 1518B.
-- The user should check that this signal is high before deciding to send
-- sending the next frame.
-- Note: MAC_TX_CTS may go low while the frame is transfered in. Ignore it as space is guaranteed
-- at the start of frame.
--//-- Receive MAC -> Protocol
-- Valid rx packets only: packets with bad CRC or invalid address are discarded.
-- The 32-bit CRC is always removed by the MAC layer.
-- Synchonous with the user-side CLK
MAC_RX_DATA : IN std_logic_vector(7 DOWNTO 0);
-- USER reads the data at the rising edge of CLK when MAC_RX_DATA_VALID = '1'
MAC_RX_DATA_VALID : IN std_logic;
-- data valid
MAC_RX_SOF : IN std_logic;
-- '1' when sending the first byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
MAC_RX_EOF : IN std_logic;
-- '1' when sending the last byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
--//-- Application <- UDP rx
UDP_RX_DATA : OUT std_logic_vector(7 DOWNTO 0);
UDP_RX_DATA_VALID : OUT std_logic;
UDP_RX_SOF : OUT std_logic;
UDP_RX_EOF : OUT std_logic;
-- 1 CLK pulse indicating that UDP_RX_DATA is the last byte in the UDP data field.
-- ALWAYS CHECK UDP_RX_DATA_VALID at the end of packet (UDP_RX_EOF = '1') to confirm
-- that the UDP packet is valid. External buffer may have to backtrack to the the last
-- valid pointer to discard an invalid UDP packet.
-- Reason: we only knows about bad UDP packets at the end.
UDP_RX_DEST_PORT_NO : IN std_logic_vector(15 DOWNTO 0);
--//-- Application -> UDP tx
UDP_TX_DATA : IN std_logic_vector(7 DOWNTO 0);
UDP_TX_DATA_VALID : IN std_logic;
UDP_TX_SOF : IN std_logic; -- 1 CLK-wide pulse to mark the first byte in the tx UDP frame
UDP_TX_EOF : IN std_logic; -- 1 CLK-wide pulse to mark the last byte in the tx UDP frame
UDP_TX_CTS : OUT std_logic;
UDP_TX_ACK : OUT std_logic; -- 1 CLK-wide pulse indicating that the previous UDP frame is being sent
UDP_TX_NAK : OUT std_logic; -- 1 CLK-wide pulse indicating that the previous UDP frame could not be sent
UDP_TX_DEST_IP_ADDR : IN std_logic_vector(127 DOWNTO 0);
UDP_TX_DEST_PORT_NO : IN std_logic_vector(15 DOWNTO 0);
UDP_TX_SOURCE_PORT_NO : IN std_logic_vector(15 DOWNTO 0);
--//-- Application <- TCP rx
-- NTCPSTREAMS can operate independently. Only one stream active at any given time.
-- Data is pushed out. Limited flow-control here. Receipient must be able to accept data
-- at any time (in other words, it is the receipient's responsibility to have elastic
-- buffer if needed).
TCP_RX_DATA : OUT SLV8xNTCPSTREAMStype;
TCP_RX_DATA_VALID : OUT std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
TCP_RX_RTS : OUT std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
TCP_RX_CTS : IN std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
-- Optional Clear-To-Send. pull to '1' when output flow control is unused.
-- WARNING: pulling CTS down will stop the flow for ALL streams.
--//-- Application -> TCP tx
-- NTCPSTREAMS can operate independently and concurrently. No scheduling arbitration needed here.
TCP_TX_DATA : IN SLV8xNTCPSTREAMStype;
TCP_TX_DATA_VALID : IN std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
TCP_TX_CTS : OUT std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
-- Clear To Send = transmit flow control.
-- App is responsible for checking the CTS signal before sending APP_DATA
--//-- TEST POINTS, COMSCOPE TRACES
CS1 : OUT std_logic_vector(7 DOWNTO 0);
CS1_CLK : OUT std_logic;
CS2 : OUT std_logic_vector(7 DOWNTO 0);
CS2_CLK : OUT std_logic;
TP : OUT std_logic_vector(10 DOWNTO 1)
);
END COMPONENT;
-- Must have programmable full with single-threshold of 61
-- out of total write-depth 64
COMPONENT fifo8to32
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(7 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(31 DOWNTO 0);
full : OUT std_logic;
prog_full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
COMPONENT fifo32to8
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(31 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(7 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the Tri-Mode EMAC core FIFO Block wrapper
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_fifo_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- RGMII Interface
--------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- RGMII Inband Status Registers
----------------------------------
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for the AXI-Lite State machine
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_axi_lite_sm
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
phy_loopback : in std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0);
s_axi_awvalid : out std_logic;
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0);
s_axi_wvalid : out std_logic;
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0);
s_axi_arvalid : out std_logic;
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset logic
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_example_design_resets is
port (
-- clocks
s_axi_aclk : in std_logic;
gtx_clk : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
reset_error : in std_logic;
rx_reset : in std_logic;
tx_reset : in std_logic;
dcm_locked : in std_logic;
-- synchronous reset outputs
glbl_rst_intn : out std_logic;
gtx_resetn : out std_logic := '0';
s_axi_resetn : out std_logic := '0';
phy_resetn : out std_logic;
chk_resetn : out std_logic := '0'
);
end component;
------------------------------------------------------------------------------
-- internal signals used in this top level wrapper.
------------------------------------------------------------------------------
-- example design clocks
signal gtx_clk_bufg : std_logic;
signal refclk_bufg : std_logic;
signal s_axi_aclk : std_logic;
signal rx_mac_aclk : std_logic;
signal tx_mac_aclk : std_logic;
signal phy_resetn_int : std_logic;
-- resets (and reset generation)
signal reset_error : std_logic;
signal s_axi_resetn : std_logic;
signal chk_resetn : std_logic;
signal gtx_resetn : std_logic;
signal rx_reset : std_logic;
signal tx_reset : std_logic;
signal dcm_locked : std_logic;
signal glbl_rst_int : std_logic;
signal phy_reset_count : unsigned(5 downto 0) := (others => '0');
signal glbl_rst_intn : std_logic;
signal mac_speed : std_logic_vector(1 downto 0);
signal serial_response : std_logic;
signal frame_error : std_logic;
signal frame_errorn : std_logic;
signal activity_flash : std_logic;
signal activity_flashn : std_logic;
signal update_speed : std_logic := '0';
signal config_board : std_logic := '0';
-- USER side RX AXI-S interface
signal rx_fifo_clock : std_logic;
signal rx_fifo_resetn : std_logic;
signal rx_axis_fifo_tdata : std_logic_vector(7 downto 0);
signal rx_axis_fifo_tvalid : std_logic;
signal rx_axis_fifo_tlast : std_logic;
signal rx_axis_fifo_tready : std_logic;
-- USER side TX AXI-S interface
signal tx_fifo_clock : std_logic;
signal tx_fifo_resetn : std_logic;
signal tx_axis_fifo_tdata : std_logic_vector(7 downto 0);
signal tx_axis_fifo_tvalid : std_logic;
signal tx_axis_fifo_tlast : std_logic;
signal tx_axis_fifo_tready : std_logic;
-- RX Statistics serialisation signals
signal rx_statistics_s : std_logic := '0';
signal rx_statistics_valid : std_logic;
signal rx_statistics_valid_reg : std_logic;
signal rx_statistics_vector : std_logic_vector(27 downto 0);
signal rx_stats : std_logic_vector(27 downto 0);
signal rx_stats_shift : std_logic_vector(29 downto 0);
signal rx_stats_toggle : std_logic := '0';
signal rx_stats_toggle_sync : std_logic;
signal rx_stats_toggle_sync_reg : std_logic := '0';
-- TX Statistics serialisation signals
signal tx_statistics_s : std_logic := '0';
signal tx_statistics_valid : std_logic;
signal tx_statistics_valid_reg : std_logic;
signal tx_statistics_vector : std_logic_vector(31 downto 0);
signal tx_stats : std_logic_vector(31 downto 0);
signal tx_stats_shift : std_logic_vector(33 downto 0);
signal tx_stats_toggle : std_logic := '0';
signal tx_stats_toggle_sync : std_logic;
signal tx_stats_toggle_sync_reg : std_logic := '0';
-- Pause interface DESerialisation
signal pause_req_s : std_logic := '0';
signal pause_shift : std_logic_vector(18 downto 0);
signal pause_req : std_logic;
signal pause_val : std_logic_vector(15 downto 0);
-- AXI-Lite interface
signal s_axi_awaddr : std_logic_vector(11 downto 0);
signal s_axi_awvalid : std_logic;
signal s_axi_awready : std_logic;
signal s_axi_wdata : std_logic_vector(31 downto 0);
signal s_axi_wvalid : std_logic;
signal s_axi_wready : std_logic;
signal s_axi_bresp : std_logic_vector(1 downto 0);
signal s_axi_bvalid : std_logic;
signal s_axi_bready : std_logic;
signal s_axi_araddr : std_logic_vector(11 downto 0);
signal s_axi_arvalid : std_logic;
signal s_axi_arready : std_logic;
signal s_axi_rdata : std_logic_vector(31 downto 0);
signal s_axi_rresp : std_logic_vector(1 downto 0);
signal s_axi_rvalid : std_logic;
signal s_axi_rready : std_logic;
-- signal tie offs
signal tx_ifg_delay : std_logic_vector(7 downto 0) := (others => '0'); -- not used in this example
signal inband_link_status : std_logic;
signal inband_clock_speed : std_logic_vector(1 downto 0);
signal inband_duplex_status : std_logic;
signal int_frame_error : std_logic;
signal int_activity_flash : std_logic;
-- set board defaults - only updated when reprogrammed
signal enable_phy_loopback : std_logic := '0';
-- tcp
SIGNAL tcp_mac_addr : std_logic_vector(47 DOWNTO 0);
SIGNAL tcp_ipv4_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL tcp_ipv6_addr : std_logic_vector(127 DOWNTO 0);
SIGNAL tcp_subnet_mask : std_logic_vector(31 DOWNTO 0);
SIGNAL tcp_gateway_ip_addr : std_logic_vector(31 DOWNTO 0);
--
SIGNAL mac_rx_sof : std_logic;
--
SIGNAL tcp_rx_data_slv8x : SLV8xNTCPSTREAMStype;
SIGNAL tcp_tx_data_slv8x : SLV8xNTCPSTREAMStype;
SIGNAL tcp_rx_data_valid_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL tcp_tx_data_valid_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL tcp_rx_cts_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL tcp_tx_cts_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL tcp_rx_rts_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL connection_reset_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
--
SIGNAL rx_fifo_full : std_logic;
SIGNAL rx_fifo_fullm3 : std_logic;
SIGNAL tx_fifo_dout : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_fifo_rden : std_logic;
SIGNAL tx_fifo_empty : std_logic;
SIGNAL rx_fifo1_full : std_logic;
SIGNAL rx_fifo1_fullm3 : std_logic;
SIGNAL tx_fifo1_dout : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_fifo1_rden : std_logic;
SIGNAL tx_fifo1_empty : std_logic;
------------------------------------------------------------------------------
-- Begin architecture
------------------------------------------------------------------------------
begin
frame_error <= int_frame_error;
frame_errorn <= not int_frame_error;
activity_flash <= int_activity_flash;
activity_flashn <= not int_activity_flash;
mac_speed <= "11";
----------------------------------------------------------------------------
-- Clock logic to generate required clocks from the 200MHz on board
-- if 125MHz is available directly this can be removed
----------------------------------------------------------------------------
gtx_clk_bufg <= gtx_clk;
refclk_bufg <= ref_clk;
s_axi_aclk <= gtx_clk;
-- generate the user side clocks for the axi fifos
tx_fifo_clock <= gtx_clk_bufg;
rx_fifo_clock <= gtx_clk_bufg;
------------------------------------------------------------------------------
-- Generate resets required for the fifo side signals etc
------------------------------------------------------------------------------
example_resets : tri_mode_ethernet_mac_0_example_design_resets
port map (
-- clocks
s_axi_aclk => s_axi_aclk,
gtx_clk => gtx_clk_bufg,
-- asynchronous resets
glbl_rst => glbl_rst,
reset_error => reset_error,
rx_reset => rx_reset,
tx_reset => tx_reset,
dcm_locked => dcm_locked,
-- synchronous reset outputs
glbl_rst_intn => glbl_rst_intn,
gtx_resetn => gtx_resetn,
s_axi_resetn => s_axi_resetn,
phy_resetn => phy_resetn,
chk_resetn => chk_resetn
);
glbl_rst_int <= NOT glbl_rst_intn;
dcm_locked <= '1';
reset_error <= '0';
-- generate the user side resets for the axi fifos
tx_fifo_resetn <= gtx_resetn;
rx_fifo_resetn <= gtx_resetn;
----------------------------------------------------------------------------
-- Instantiate the AXI-LITE Controller
----------------------------------------------------------------------------
axi_lite_controller : tri_mode_ethernet_mac_0_axi_lite_sm
port map (
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
mac_speed => mac_speed,
update_speed => update_speed,
serial_command => pause_req_s,
serial_response => serial_response,
phy_loopback => enable_phy_loopback,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
------------------------------------------------------------------------------
-- Instantiate the TRIMAC core FIFO Block wrapper
------------------------------------------------------------------------------
trimac_fifo_block : tri_mode_ethernet_mac_0_fifo_block
port map (
gtx_clk => gtx_clk_bufg,
-- asynchronous reset
glbl_rstn => glbl_rst_intn,
rx_axi_rstn => '1',
tx_axi_rstn => '1',
-- Reference clock for IDELAYCTRL's
refclk => refclk_bufg,
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
-- Receiver => AXI-S Interface
------------------------------------------
rx_fifo_clock => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
-- Transmitter => AXI-S Interface
---------------------------------------------
tx_fifo_clock => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
-- MAC Control Interface
--------------------------
pause_req => pause_req,
pause_val => pause_val,
-- RGMII Interface
--------------------
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
-- RGMII Inband Status Registers
----------------------------------
inband_link_status => inband_link_status,
inband_clock_speed => inband_clock_speed,
inband_duplex_status => inband_duplex_status,
-- MDIO Interface
-------------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
---------------------------------------------< tcp_server
PROCESS (gtx_clk_bufg) IS
BEGIN -- Make configurations synchronous to CLK125 of the TCP module
IF rising_edge(gtx_clk_bufg) THEN
tcp_mac_addr <= MAC_ADDR;
tcp_ipv4_addr <= IPv4_ADDR;
tcp_ipv6_addr <= IPv6_ADDR;
tcp_subnet_mask <= SUBNET_MASK;
tcp_gateway_ip_addr <= GATEWAY_IP_ADDR;
END IF;
END PROCESS;
-- generate a 1-clk wide pulse SOF (start of frame)
mac_rx_sof_gen : PROCESS (gtx_clk_bufg, glbl_rst_int) IS
VARIABLE state : std_logic;
VARIABLE tvalid_prev : std_logic;
BEGIN
IF glbl_rst_int = '1' THEN
state := '0';
tvalid_prev := '0';
mac_rx_sof <= '0';
ELSIF falling_edge(gtx_clk_bufg) THEN
mac_rx_sof <= '0';
IF state = '0' THEN
IF tvalid_prev = '0' AND rx_axis_fifo_tvalid = '1' THEN
mac_rx_sof <= '1';
state := '1';
END IF;
ELSE -- state = '1'
IF rx_axis_fifo_tlast = '1' THEN
state := '0';
END IF;
END IF;
tvalid_prev := rx_axis_fifo_tvalid;
END IF;
END PROCESS;
rx_axis_fifo_tready <= '1';
connection_reset_v <= (OTHERS => TCP_CONNECTION_RESET);
tcp_server_inst : COM5402
GENERIC MAP (
CLK_FREQUENCY => 125,
-- CLK frequency in MHz. Needed to compute actual delays.
TX_IDLE_TIMEOUT => 50,
-- inactive input timeout, expressed in 4us units. -- 50*4us = 200us
-- Controls the transmit stream segmentation: data in the elastic buffer will be transmitted if
-- no input is received within TX_IDLE_TIMEOUT, without waiting for the transmit frame to be filled with MSS data bytes.
SIMULATION => '0'
-- 1 during simulation with Wireshark .cap file, '0' otherwise
-- Wireshark many not be able to collect offloaded checksum computations.
-- when SIMULATION = '1': (a) IP header checksum is valid if 0000,
-- (b) TCP checksum computation is forced to a valid 00001 irrespective of the 16-bit checksum
-- captured by Wireshark.
)
PORT MAP (
--//-- CLK, RESET
CLK => gtx_clk_bufg,
-- All signals are synchronous with CLK
-- CLK must be a global clock 125 MHz or faster to match the Gbps MAC speed.
ASYNC_RESET => glbl_rst_int, -- to be phased out. replace with SYNC_RESET
SYNC_RESET => glbl_rst_int,
--//-- CONFIGURATION
-- configuration signals are synchonous with CLK
-- Synchronous with CLK clock.
MAC_ADDR => tcp_mac_addr,
IPv4_ADDR => tcp_ipv4_addr,
IPv6_ADDR => tcp_ipv6_addr,
SUBNET_MASK => tcp_subnet_mask,
GATEWAY_IP_ADDR => tcp_gateway_ip_addr,
-- local IP address. 4 bytes for IPv4, 16 bytes for IPv6
-- Natural order (MSB) 172.16.1.128 (LSB) as transmitted in the IP frame.
--// User-initiated connection reset for stream I
CONNECTION_RESET => connection_reset_v,
--//-- Protocol -> Transmit MAC Interface
-- 32-bit CRC is automatically appended by the MAC layer. User should not supply it.
-- Synchonous with the user-side CLK
MAC_TX_DATA => tx_axis_fifo_tdata,
-- MAC reads the data at the rising edge of CLK when MAC_TX_DATA_VALID = '1'
MAC_TX_DATA_VALID => tx_axis_fifo_tvalid,
-- data valid
MAC_TX_SOF => OPEN,
-- start of frame: '1' when sending the first byte.
MAC_TX_EOF => tx_axis_fifo_tlast,
-- '1' when sending the last byte in a packet to be transmitted.
-- Aligned with MAC_TX_DATA_VALID
MAC_TX_CTS => tx_axis_fifo_tready,
-- MAC-generated Clear To Send flow control signal, indicating room in the
-- MAC tx elastic buffer for a complete maximum size frame 1518B.
-- The user should check that this signal is high before deciding to send
-- sending the next frame.
-- Note: MAC_TX_CTS may go low while the frame is transfered in. Ignore it as space is guaranteed
-- at the start of frame.
--//-- Receive MAC -> Protocol
-- Valid rx packets only: packets with bad CRC or invalid address are discarded.
-- The 32-bit CRC is always removed by the MAC layer.
-- Synchonous with the user-side CLK
MAC_RX_DATA => rx_axis_fifo_tdata,
-- USER reads the data at the rising edge of CLK when MAC_RX_DATA_VALID = '1'
MAC_RX_DATA_VALID => rx_axis_fifo_tvalid,
-- data valid
MAC_RX_SOF => mac_rx_sof,
-- '1' when sending the first byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
MAC_RX_EOF => rx_axis_fifo_tlast,
-- '1' when sending the last byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
--//-- Application <- UDP rx
UDP_RX_DATA => OPEN,
UDP_RX_DATA_VALID => OPEN,
UDP_RX_SOF => OPEN,
UDP_RX_EOF => OPEN,
-- 1 CLK pulse indicating that UDP_RX_DATA is the last byte in the UDP data field.
-- ALWAYS CHECK UDP_RX_DATA_VALID at the end of packet (UDP_RX_EOF = '1') to confirm
-- that the UDP packet is valid. External buffer may have to backtrack to the the last
-- valid pointer to discard an invalid UDP packet.
-- Reason: we only knows about bad UDP packets at the end.
UDP_RX_DEST_PORT_NO => (OTHERS => '0'),
--//-- Application -> UDP tx
UDP_TX_DATA => (OTHERS => '0'),
UDP_TX_DATA_VALID => '0',
UDP_TX_SOF => '0', -- 1 CLK-wide pulse to mark the first byte in the tx UDP frame
UDP_TX_EOF => '0', -- 1 CLK-wide pulse to mark the last byte in the tx UDP frame
UDP_TX_CTS => OPEN,
UDP_TX_ACK => OPEN, -- 1 CLK-wide pulse indicating that the previous UDP frame is being sent
UDP_TX_NAK => OPEN, -- 1 CLK-wide pulse indicating that the previous UDP frame could not be sent
UDP_TX_DEST_IP_ADDR => (OTHERS => '0'),
UDP_TX_DEST_PORT_NO => (OTHERS => '0'),
UDP_TX_SOURCE_PORT_NO => (OTHERS => '0'),
--//-- Application <- TCP rx
-- NTCPSTREAMS can operate independently. Only one stream active at any given time.
-- Data is pushed out. Limited flow-control here. Receipient must be able to accept data
-- at any time (in other words, it is the receipient's responsibility to have elastic
-- buffer if needed).
TCP_RX_DATA => tcp_rx_data_slv8x,
TCP_RX_DATA_VALID => tcp_rx_data_valid_v,
TCP_RX_RTS => tcp_rx_rts_v,
TCP_RX_CTS => tcp_rx_cts_v,
-- Optional Clear-To-Send. pull to '1' when output flow control is unused.
-- WARNING: pulling CTS down will stop the flow for ALL streams.
--//-- Application -> TCP tx
-- NTCPSTREAMS can operate independently and concurrently. No scheduling arbitration needed here.
TCP_TX_DATA => tcp_tx_data_slv8x,
TCP_TX_DATA_VALID => tcp_tx_data_valid_v,
TCP_TX_CTS => tcp_tx_cts_v,
-- Clear To Send = transmit flow control.
-- App is responsible for checking the CTS signal before sending APP_DATA
--//-- TEST POINTS, COMSCOPE TRACES
CS1 => OPEN,
CS1_CLK => OPEN,
CS2 => OPEN,
CS2_CLK => OPEN,
TP => OPEN
);
-- Must have programmable full with single-threshold of 61
-- out of total write-depth 64.
-- When RX_CTS is low, the Server continues to drive out 3 more bytes of data
-- (observed with ILA). The fifo must be able to accept them, hence the use
-- of prog_full.
rx_fifo_inst : fifo8to32
PORT MAP (
rst => glbl_rst_int,
wr_clk => gtx_clk_bufg,
rd_clk => RX_FIFO_RDCLK,
din => tcp_rx_data_slv8x(0),
wr_en => tcp_rx_data_valid_v(0),
rd_en => RX_FIFO_RDEN,
dout => RX_FIFO_Q,
full => rx_fifo_full,
prog_full => rx_fifo_fullm3, -- asserted at (full-3) writes
empty => RX_FIFO_EMPTY
);
tcp_rx_cts_v(0) <= (NOT rx_fifo_fullm3) WHEN TCP_USE_FIFO = '1' ELSE
RX_TREADY;
RX_TDATA <= tcp_rx_data_slv8x(0);
RX_TVALID <= tcp_rx_data_valid_v(0);
tx_fifo_inst : fifo32to8
PORT MAP (
rst => glbl_rst_int,
wr_clk => TX_FIFO_WRCLK,
rd_clk => gtx_clk_bufg,
din => TX_FIFO_Q,
wr_en => TX_FIFO_WREN,
rd_en => tx_fifo_rden,
dout => tx_fifo_dout,
full => TX_FIFO_FULL,
empty => tx_fifo_empty
);
tcp_tx_data_valid_v(0) <= ((NOT tx_fifo_empty) AND tcp_tx_cts_v(0)) WHEN TCP_USE_FIFO = '1' ELSE
TX_TVALID;
tx_fifo_rden <= tcp_tx_data_valid_v(0);
tcp_tx_data_slv8x(0) <= tx_fifo_dout WHEN TCP_USE_FIFO = '1' ELSE
TX_TDATA;
TX_TREADY <= tcp_tx_cts_v(0);
-- Stream 1
rx_fifo1_inst : fifo8to32
PORT MAP (
rst => glbl_rst_int,
wr_clk => gtx_clk_bufg,
rd_clk => RX_FIFO1_RDCLK,
din => tcp_rx_data_slv8x(1),
wr_en => tcp_rx_data_valid_v(1),
rd_en => RX_FIFO1_RDEN,
dout => RX_FIFO1_Q,
full => rx_fifo1_full,
prog_full => rx_fifo1_fullm3, -- asserted at (full-3) writes
empty => RX_FIFO1_EMPTY
);
tcp_rx_cts_v(1) <= NOT rx_fifo1_fullm3;
tx_fifo1_inst : fifo32to8
PORT MAP (
rst => glbl_rst_int,
wr_clk => TX_FIFO1_WRCLK,
rd_clk => gtx_clk_bufg,
din => TX_FIFO1_Q,
wr_en => TX_FIFO1_WREN,
rd_en => tx_fifo1_rden,
dout => tx_fifo1_dout,
full => TX_FIFO1_FULL,
empty => tx_fifo1_empty
);
tcp_tx_data_valid_v(1) <= ((NOT tx_fifo1_empty) AND tcp_tx_cts_v(1));
tx_fifo1_rden <= tcp_tx_data_valid_v(1);
tcp_tx_data_slv8x(1) <= tx_fifo1_dout;
end wrapper;
| bsd-3-clause | 7365bb907ca4a8218d5b36f149eb7386 | 0.485637 | 4.148584 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/chbond_count_dec.vhd | 4 | 2,930 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:51 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: chbond_count_dec_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.1 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- CHBOND_COUNT_DEC
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: This module decodes the MGT's RXCLKCORCNT. Its
-- CHANNEL_BOND_LOAD output is active when RXCLKCORCNT
-- indicates the elastic buffer has executed channel
-- bonding for the current RXDATA.
--
-- * Supports Virtex 2 Pro
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.AURORA.all;
entity CHBOND_COUNT_DEC is
port (
RX_CLK_COR_CNT : in std_logic_vector(2 downto 0);
CHANNEL_BOND_LOAD : out std_logic;
USER_CLK : in std_logic
);
end CHBOND_COUNT_DEC;
architecture RTL of CHBOND_COUNT_DEC is
-- Parameter Declarations --
constant DLY : time := 1 ns;
constant CHANNEL_BOND_LOAD_CODE : std_logic_vector(2 downto 0) := "101"; -- Code indicating channel bond load complete
-- External Register Declarations --
signal CHANNEL_BOND_LOAD_Buffer : std_logic;
begin
CHANNEL_BOND_LOAD <= CHANNEL_BOND_LOAD_Buffer;
-- Main Body of Code --
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
CHANNEL_BOND_LOAD_Buffer <= std_bool(RX_CLK_COR_CNT = CHANNEL_BOND_LOAD_CODE);
end if;
end process;
end RTL;
| bsd-2-clause | 9a916b8e3aed248bd00567bb1ec2680f | 0.593515 | 4.041379 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_write_wrapper.vhd | 9 | 65,399 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 38286d0abdae86aa754acb96c9b8984e | 0.949953 | 1.815328 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/cdcfifo/simulation/cdcfifo_dgen.vhd | 3 | 4,521 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
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--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cdcfifo_pkg.ALL;
ENTITY cdcfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF cdcfifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:cdcfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| bsd-2-clause | 4b36813956c2ea23d266fe6cfa891493 | 0.60031 | 4.253057 | false | false | false | false |
Given-Jiang/Gray_Processing | Gray_Processing_dspbuilder/hdl/Gray_Processing_GN_Gray_Processing_Gray_Processing_Module.vhd | 2 | 29,196 | -- Gray_Processing_GN_Gray_Processing_Gray_Processing_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:14:00
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Processing_GN_Gray_Processing_Gray_Processing_Module is
port (
eop : in std_logic := '0'; -- eop.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire
data_out : out std_logic_vector(23 downto 0); -- data_out.wire
sop : in std_logic := '0' -- sop.wire
);
end entity Gray_Processing_GN_Gray_Processing_Gray_Processing_Module;
architecture rtl of Gray_Processing_GN_Gray_Processing_Gray_Processing_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNKXX25S2S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKXX25S2S;
component alt_dspbuilder_cast_GN6OMCQQS7 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN6OMCQQS7;
component alt_dspbuilder_cast_GN7IAAYCSZ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7IAAYCSZ;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
a : in std_logic_vector(WIDTH-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
direction : in std_logic := 'X'; -- wire
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
r : out std_logic_vector(WIDTH-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic (
family : string := "Stratix";
direction : string := "AddAdd";
data3b_const : string := "00000000";
data2b_const : string := "00000000";
representation : string := "SIGNED";
dataWidth : integer := 8;
data4b_const : string := "00000000";
number_multipliers : integer := 2;
pipeline_register : string := "NoRegister";
use_dedicated_circuitry : integer := 0;
data1b_const : string := "00000000";
use_b_consts : natural := 0
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data1a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data2a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data3a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(17 downto 0); -- wire
user_aclr : in std_logic := 'X'; -- wire
ena : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiply_add_GNKLXFKAO3;
component alt_dspbuilder_multiplexer_GNCALBUTDR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNCALBUTDR;
component alt_dspbuilder_cast_GNJGR7GQ2L is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(17 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNJGR7GQ2L;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_if_statement_GN7VA7SRUP is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GN7VA7SRUP;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_constant_GNPXZ5JSVR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNPXZ5JSVR;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_cast_GNSB3OXIQS is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_cast_GNSB3OXIQS;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
signal barrel_shifteruser_aclrgnd_output_wire : std_logic; -- Barrel_Shifteruser_aclrGND:output -> Barrel_Shifter:user_aclr
signal barrel_shifterenavcc_output_wire : std_logic; -- Barrel_ShifterenaVCC:output -> Barrel_Shifter:ena
signal multiply_adduser_aclrgnd_output_wire : std_logic; -- Multiply_Adduser_aclrGND:output -> Multiply_Add:user_aclr
signal multiply_addenavcc_output_wire : std_logic; -- Multiply_AddenaVCC:output -> Multiply_Add:ena
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay2enavcc_output_wire : std_logic; -- Delay2enaVCC:output -> Delay2:ena
signal bus_concatenation_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation:output -> Bus_Concatenation1:b
signal barrel_shifter_r_wire : std_logic_vector(17 downto 0); -- Barrel_Shifter:r -> Bus_Conversion:input
signal bus_conversion_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion:output -> [Bus_Concatenation1:a, Bus_Concatenation:a, Bus_Concatenation:b]
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Bus_Conversion1:input, Bus_Conversion2:input, Bus_Conversion3:input, If_Statement1:a, Multiplexer:in0]
signal constant1_output_wire : std_logic_vector(3 downto 0); -- Constant1:output -> Barrel_Shifter:distance
signal delay2_output_wire : std_logic_vector(0 downto 0); -- Delay2:output -> [Delay:input, cast1:input]
signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0
signal sop_0_output_wire : std_logic; -- sop_0:output -> Logical_Bit_Operator:data1
signal eop_0_output_wire : std_logic; -- eop_0:output -> Logical_Bit_Operator1:data0
signal delay_output_wire : std_logic_vector(0 downto 0); -- Delay:output -> [Multiplexer:sel, cast3:input]
signal bus_concatenation1_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation1:output -> Multiplexer:in1
signal bus_conversion3_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion3:output -> Multiply_Add:data1a
signal bus_conversion2_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion2:output -> Multiply_Add:data2a
signal bus_conversion1_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion1:output -> Multiply_Add:data3a
signal multiply_add_result_wire : std_logic_vector(17 downto 0); -- Multiply_Add:result -> Barrel_Shifter:a
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> data_out_0:input
signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> cast0:input
signal cast0_output_wire : std_logic; -- cast0:output -> Delay:sclr
signal cast1_output_wire : std_logic; -- cast1:output -> Delay:ena
signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> cast2:input
signal cast2_output_wire : std_logic_vector(0 downto 0); -- cast2:output -> Delay2:input
signal cast3_output_wire : std_logic; -- cast3:output -> Logical_Bit_Operator1:data1
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> cast4:input
signal cast4_output_wire : std_logic_vector(0 downto 0); -- cast4:output -> Delay1:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Barrel_Shifter:aclr, Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Delay1:aclr, Delay2:aclr, Delay:aclr, Multiplexer:aclr, Multiply_Add:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Barrel_Shifter:clock, Bus_Concatenation1:clock, Bus_Concatenation:clock, Delay1:clock, Delay2:clock, Delay:clock, Multiplexer:clock, Multiply_Add:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
bus_conversion2 : component alt_dspbuilder_cast_GN6OMCQQS7
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GN7IAAYCSZ
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator_result_wire, -- result.wire
data0 => if_statement1_true_wire, -- data0.wire
data1 => sop_0_output_wire -- data1.wire
);
barrel_shifter : component alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map (
DISTANCE_WIDTH => 4,
NDIRECTION => 1,
SIGNED => 0,
use_dedicated_circuitry => "false",
PIPELINE => 0,
WIDTH => 18
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => multiply_add_result_wire, -- a.wire
r => barrel_shifter_r_wire, -- r.wire
distance => constant1_output_wire, -- distance.wire
ena => barrel_shifterenavcc_output_wire, -- ena.wire
user_aclr => barrel_shifteruser_aclrgnd_output_wire -- user_aclr.wire
);
barrel_shifteruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => barrel_shifteruser_aclrgnd_output_wire -- output.wire
);
barrel_shifterenavcc : component alt_dspbuilder_vcc_GN
port map (
output => barrel_shifterenavcc_output_wire -- output.wire
);
multiply_add : component alt_dspbuilder_multiply_add_GNKLXFKAO3
generic map (
family => "Cyclone V",
direction => "AddAdd",
data3b_const => "00011110",
data2b_const => "10010110",
representation => "UNSIGNED",
dataWidth => 8,
data4b_const => "01001100",
number_multipliers => 3,
pipeline_register => "NoRegister",
use_dedicated_circuitry => 1,
data1b_const => "01001100",
use_b_consts => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data1a => bus_conversion3_output_wire, -- data1a.wire
data2a => bus_conversion2_output_wire, -- data2a.wire
data3a => bus_conversion1_output_wire, -- data3a.wire
result => multiply_add_result_wire, -- result.wire
user_aclr => multiply_adduser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiply_addenavcc_output_wire -- ena.wire
);
multiply_adduser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiply_adduser_aclrgnd_output_wire -- output.wire
);
multiply_addenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiply_addenavcc_output_wire -- output.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => delay_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => data_in_0_output_wire, -- in0.wire
in1 => bus_concatenation1_output_wire -- in1.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
bus_conversion : component alt_dspbuilder_cast_GNJGR7GQ2L
generic map (
round => 0,
saturate => 0
)
port map (
input => barrel_shifter_r_wire, -- input.wire
output => bus_conversion_output_wire -- output.wire
);
constant4 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) and (a /= c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => data_in_0_output_wire, -- a.wire
b => constant3_output_wire, -- b.wire
c => constant4_output_wire -- c.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map (
widthB => 16,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion_output_wire, -- a.wire
b => bus_concatenation_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion_output_wire, -- a.wire
b => bus_conversion_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
constant3 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant3_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => delay2enavcc_output_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay2enavcc_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => cast0_output_wire, -- sclr.wire
ena => cast1_output_wire -- ena.wire
);
constant1 : component alt_dspbuilder_constant_GNPXZ5JSVR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "1000",
width => 4
)
port map (
output => constant1_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => multiplexer_result_wire, -- input.wire
output => data_out -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => eop, -- input.wire
output => eop_0_output_wire -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => eop_0_output_wire, -- data0.wire
data1 => cast3_output_wire -- data1.wire
);
cast0 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay2_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator_result_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay_output_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator1_result_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
end architecture rtl; -- of Gray_Processing_GN_Gray_Processing_Gray_Processing_Module
| mit | e009c617c2f56b4e909f7f9568d6cede | 0.556686 | 3.383866 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_bin_cntr.vhd | 9 | 12,982 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | 0be9654320f7747b8f4902b37145ad82 | 0.930057 | 1.863891 | false | false | false | false |
ymei/TMSPlane | Firmware/src/ten_gig_eth/TE07412C1/ten_gig_eth.vhd | 2 | 18,584 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/18/2013 11:21:31 PM
-- Design Name:
-- Module Name: ten_gig_eth - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY ten_gig_eth IS
PORT (
REFCLK_P : IN std_logic; -- 156.25MHz for transceiver
REFCLK_N : IN std_logic;
RESET : IN std_logic;
SFP_TX_P : OUT std_logic;
SFP_TX_N : OUT std_logic;
SFP_RX_P : IN std_logic;
SFP_RX_N : IN std_logic;
SFP_LOS : IN std_logic; -- loss of receiver signal
SFP_TX_DISABLE : OUT std_logic;
-- clk156.25 domain, clock generated by the core
CLK156p25 : OUT std_logic;
PCS_PMA_CORE_STATUS : OUT std_logic_vector(7 DOWNTO 0);
TX_STATISTICS_VECTOR : OUT std_logic_vector(25 DOWNTO 0);
TX_STATISTICS_VALID : OUT std_logic;
RX_STATISTICS_VECTOR : OUT std_logic_vector(29 DOWNTO 0);
RX_STATISTICS_VALID : OUT std_logic;
PAUSE_VAL : IN std_logic_vector(15 DOWNTO 0);
PAUSE_REQ : IN std_logic;
TX_IFG_DELAY : IN std_logic_vector(7 DOWNTO 0);
-- emac control interface
S_AXI_ACLK : IN std_logic;
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(10 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WDATA : IN std_logic_vector(31 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(10 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- tx_wr_clk domain
TX_AXIS_FIFO_ARESETN : IN std_logic;
TX_AXIS_FIFO_ACLK : IN std_logic;
TX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
TX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
TX_AXIS_FIFO_TVALID : IN std_logic;
TX_AXIS_FIFO_TLAST : IN std_logic;
TX_AXIS_FIFO_TREADY : OUT std_logic;
-- rx_rd_clk domain
RX_AXIS_FIFO_ARESETN : IN std_logic;
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : OUT std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : OUT std_logic;
RX_AXIS_FIFO_TLAST : OUT std_logic;
RX_AXIS_FIFO_TREADY : IN std_logic
);
END ten_gig_eth;
ARCHITECTURE Behavioral OF ten_gig_eth IS
-- PCS/PMA
COMPONENT ten_gig_eth_pcs_pma_wrapper
PORT (
refclk_p : IN std_logic;
refclk_n : IN std_logic;
coreclk_out : OUT std_logic;
reset : IN std_logic;
qpll_locked : OUT std_logic;
sim_speedup_control : IN std_logic := '0';
xgmii_txd : IN std_logic_vector(63 DOWNTO 0);
xgmii_txc : IN std_logic_vector(7 DOWNTO 0);
xgmii_rxd : OUT std_logic_vector(63 DOWNTO 0);
xgmii_rxc : OUT std_logic_vector(7 DOWNTO 0);
xgmii_rx_clk : out std_logic;
txp : OUT std_logic;
txn : OUT std_logic;
rxp : IN std_logic;
rxn : IN std_logic;
mdc : IN std_logic;
mdio_in : IN std_logic;
mdio_out : OUT std_logic;
mdio_tri : OUT std_logic;
prtad : IN std_logic_vector(4 DOWNTO 0);
core_status : OUT std_logic_vector(7 DOWNTO 0);
resetdone : OUT std_logic;
signal_detect : IN std_logic;
tx_fault : IN std_logic;
tx_disable : OUT std_logic
);
END COMPONENT;
-- EMAC
COMPONENT ten_gig_eth_mac_0
PORT (
tx_clk0 : IN std_logic;
reset : IN std_logic;
tx_axis_aresetn : IN std_logic;
tx_axis_tdata : IN std_logic_vector(63 DOWNTO 0);
tx_axis_tvalid : IN std_logic;
tx_axis_tlast : IN std_logic;
tx_axis_tuser : IN std_logic_vector(0 DOWNTO 0);
tx_ifg_delay : IN std_logic_vector(7 DOWNTO 0);
tx_axis_tkeep : IN std_logic_vector(7 DOWNTO 0);
tx_axis_tready : OUT std_logic;
tx_statistics_vector : OUT std_logic_vector(25 DOWNTO 0);
tx_statistics_valid : OUT std_logic;
rx_axis_aresetn : IN std_logic;
rx_axis_tdata : OUT std_logic_vector(63 DOWNTO 0);
rx_axis_tvalid : OUT std_logic;
rx_axis_tuser : OUT std_logic;
rx_axis_tlast : OUT std_logic;
rx_axis_tkeep : OUT std_logic_vector(7 DOWNTO 0);
rx_statistics_vector : OUT std_logic_vector(29 DOWNTO 0);
rx_statistics_valid : OUT std_logic;
pause_val : IN std_logic_vector(15 DOWNTO 0);
pause_req : IN std_logic;
s_axi_aclk : IN std_logic;
s_axi_aresetn : IN std_logic;
s_axi_awaddr : IN std_logic_vector(10 DOWNTO 0);
s_axi_awvalid : IN std_logic;
s_axi_awready : OUT std_logic;
s_axi_wdata : IN std_logic_vector(31 DOWNTO 0);
s_axi_wvalid : IN std_logic;
s_axi_wready : OUT std_logic;
s_axi_bresp : OUT std_logic_vector(1 DOWNTO 0);
s_axi_bvalid : OUT std_logic;
s_axi_bready : IN std_logic;
s_axi_araddr : IN std_logic_vector(10 DOWNTO 0);
s_axi_arvalid : IN std_logic;
s_axi_arready : OUT std_logic;
s_axi_rdata : OUT std_logic_vector(31 DOWNTO 0);
s_axi_rresp : OUT std_logic_vector(1 DOWNTO 0);
s_axi_rvalid : OUT std_logic;
s_axi_rready : IN std_logic;
xgmacint : OUT std_logic;
tx_dcm_locked : IN std_logic;
xgmii_txd : OUT std_logic_vector(63 DOWNTO 0);
xgmii_txc : OUT std_logic_vector(7 DOWNTO 0);
rx_clk0 : IN std_logic;
rx_dcm_locked : IN std_logic;
xgmii_rxd : IN std_logic_vector(63 DOWNTO 0);
xgmii_rxc : IN std_logic_vector(7 DOWNTO 0);
mdc : OUT std_logic;
mdio_in : IN std_logic;
mdio_out : OUT std_logic;
mdio_tri : OUT std_logic
);
END COMPONENT;
--ATTRIBUTE SYN_BLACK_BOX : boolean;
--ATTRIBUTE SYN_BLACK_BOX OF ten_gig_eth_mac_0 : COMPONENT IS true;
--ATTRIBUTE BLACK_BOX_PAD_PIN : string;
--ATTRIBUTE BLACK_BOX_PAD_PIN OF ten_gig_eth_mac_0 : COMPONENT IS "tx_clk0,reset,tx_axis_aresetn,tx_axis_tdata[63:0],tx_axis_tvalid,tx_axis_tlast,tx_axis_tuser[0:0],tx_ifg_delay[7:0],tx_axis_tkeep[7:0],tx_axis_tready,tx_statistics_vector[25:0],tx_statistics_valid,rx_axis_aresetn,rx_axis_tdata[63:0],rx_axis_tvalid,rx_axis_tuser,rx_axis_tlast,rx_axis_tkeep[7:0],rx_statistics_vector[29:0],rx_statistics_valid,pause_val[15:0],pause_req,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[10:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[10:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,xgmacint,tx_dcm_locked,xgmii_txd[63:0],xgmii_txc[7:0],rx_clk0,rx_dcm_locked,xgmii_rxd[63:0],xgmii_rxc[7:0],mdc,mdio_in,mdio_out,mdio_tri";
-- FIFO
COMPONENT ten_gig_eth_mac_0_xgmac_fifo
GENERIC (
TX_FIFO_SIZE : integer := 512;
RX_FIFO_SIZE : integer := 512
);
PORT (
----------------------------------------------------------------
-- client interface --
----------------------------------------------------------------
-- tx_wr_clk domain
tx_axis_fifo_aresetn : IN std_logic;
tx_axis_fifo_aclk : IN std_logic;
tx_axis_fifo_tdata : IN std_logic_vector(63 DOWNTO 0);
tx_axis_fifo_tkeep : IN std_logic_vector(7 DOWNTO 0);
tx_axis_fifo_tvalid : IN std_logic;
tx_axis_fifo_tlast : IN std_logic;
tx_axis_fifo_tready : OUT std_logic;
tx_fifo_full : OUT std_logic;
tx_fifo_status : OUT std_logic_vector(3 DOWNTO 0);
--rx_rd_clk domain
rx_axis_fifo_aresetn : IN std_logic;
rx_axis_fifo_aclk : IN std_logic;
rx_axis_fifo_tdata : OUT std_logic_vector(63 DOWNTO 0);
rx_axis_fifo_tkeep : OUT std_logic_vector(7 DOWNTO 0);
rx_axis_fifo_tvalid : OUT std_logic;
rx_axis_fifo_tlast : OUT std_logic;
rx_axis_fifo_tready : IN std_logic;
rx_fifo_status : OUT std_logic_vector(3 DOWNTO 0);
---------------------------------------------------------------------------
-- mac transmitter interface --
---------------------------------------------------------------------------
tx_axis_mac_aresetn : IN std_logic;
tx_axis_mac_aclk : IN std_logic;
tx_axis_mac_tdata : OUT std_logic_vector(63 DOWNTO 0);
tx_axis_mac_tkeep : OUT std_logic_vector(7 DOWNTO 0);
tx_axis_mac_tvalid : OUT std_logic;
tx_axis_mac_tlast : OUT std_logic;
tx_axis_mac_tready : IN std_logic;
---------------------------------------------------------------------------
-- mac receiver interface --
---------------------------------------------------------------------------
rx_axis_mac_aresetn : IN std_logic;
rx_axis_mac_aclk : IN std_logic;
rx_axis_mac_tdata : IN std_logic_vector(63 DOWNTO 0);
rx_axis_mac_tkeep : IN std_logic_vector(7 DOWNTO 0);
rx_axis_mac_tvalid : IN std_logic;
rx_axis_mac_tlast : IN std_logic;
rx_axis_mac_tuser : IN std_logic;
rx_fifo_full : OUT std_logic
);
END COMPONENT;
SIGNAL clk156p25_i : std_logic;
SIGNAL qpll_locked : std_logic;
SIGNAL xgmii_txd : std_logic_vector(63 DOWNTO 0);
SIGNAL xgmii_txc : std_logic_vector(7 DOWNTO 0);
SIGNAL xgmii_rxd : std_logic_vector(63 DOWNTO 0);
SIGNAL xgmii_rxc : std_logic_vector(7 DOWNTO 0);
SIGNAL mdc : std_logic;
SIGNAL tgemac_mdio_out : std_logic;
SIGNAL pcspma_mdio_out : std_logic;
SIGNAL signal_detect : std_logic;
SIGNAL drp_req : std_logic;
SIGNAL drp_den_o : std_logic;
SIGNAL drp_dwe_o : std_logic;
SIGNAL drp_daddr_o : std_logic_vector(15 DOWNTO 0);
SIGNAL drp_di_o : std_logic_vector(15 DOWNTO 0);
SIGNAL drp_drdy_o : std_logic;
SIGNAL drp_drpdo_o : std_logic_vector(15 DOWNTO 0);
SIGNAL tx_axis_mac_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL tx_axis_mac_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_axis_mac_tvalid : std_logic;
SIGNAL tx_axis_mac_tlast : std_logic;
SIGNAL tx_axis_mac_tready : std_logic;
SIGNAL tx_axis_mac_aresetn_i : std_logic;
SIGNAL tx_axis_fifo_aresetn_i : std_logic;
SIGNAL rx_axis_mac_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL rx_axis_mac_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_axis_mac_tvalid : std_logic;
SIGNAL rx_axis_mac_tuser : std_logic;
SIGNAL rx_axis_mac_tlast : std_logic;
SIGNAL rx_axis_mac_aresetn_i : std_logic;
SIGNAL rx_axis_fifo_aresetn_i : std_logic;
ATTRIBUTE keep : string;
ATTRIBUTE keep OF tx_axis_mac_tdata : SIGNAL IS "true";
ATTRIBUTE keep OF tx_axis_mac_tkeep : SIGNAL IS "true";
ATTRIBUTE keep OF tx_axis_mac_tvalid : SIGNAL IS "true";
ATTRIBUTE keep OF tx_axis_mac_tlast : SIGNAL IS "true";
ATTRIBUTE keep OF tx_axis_mac_tready : SIGNAL IS "true";
ATTRIBUTE keep OF rx_axis_mac_tdata : SIGNAL IS "true";
ATTRIBUTE keep OF rx_axis_mac_tkeep : SIGNAL IS "true";
ATTRIBUTE keep OF rx_axis_mac_tvalid : SIGNAL IS "true";
ATTRIBUTE keep OF rx_axis_mac_tuser : SIGNAL IS "true";
ATTRIBUTE keep OF rx_axis_mac_tlast : SIGNAL IS "true";
BEGIN
-- PCS/PMA
ten_gig_eth_pcs_pma_inst : ten_gig_eth_pcs_pma_wrapper
PORT MAP (
refclk_p => REFCLK_P,
refclk_n => REFCLK_N,
coreclk_out => clk156p25_i,
reset => RESET,
qpll_locked => qpll_locked,
xgmii_txd => xgmii_txd,
xgmii_txc => xgmii_txc,
xgmii_rxd => xgmii_rxd,
xgmii_rxc => xgmii_rxc,
xgmii_rx_clk => OPEN,
txp => SFP_TX_P,
txn => SFP_TX_N,
rxp => SFP_RX_P,
rxn => SFP_RX_N,
mdc => mdc,
mdio_in => tgemac_mdio_out,
mdio_out => pcspma_mdio_out,
mdio_tri => OPEN,
prtad => (OTHERS => '0'),
core_status => PCS_PMA_CORE_STATUS,
resetdone => OPEN,
signal_detect => signal_detect,
tx_fault => '0',
tx_disable => SFP_TX_DISABLE
);
signal_detect <= NOT SFP_LOS;
CLK156p25 <= clk156p25_i;
-- EMAC
ten_gig_eth_mac_inst : ten_gig_eth_mac_0
PORT MAP (
tx_clk0 => clk156p25_i,
reset => RESET,
tx_axis_aresetn => tx_axis_mac_aresetn_i,
tx_axis_tdata => tx_axis_mac_tdata,
tx_axis_tvalid => tx_axis_mac_tvalid,
tx_axis_tlast => tx_axis_mac_tlast,
tx_axis_tuser => (OTHERS => '0'),
tx_ifg_delay => TX_IFG_DELAY,
tx_axis_tkeep => tx_axis_mac_tkeep,
tx_axis_tready => tx_axis_mac_tready,
tx_statistics_vector => TX_STATISTICS_VECTOR,
tx_statistics_valid => TX_STATISTICS_VALID,
rx_axis_aresetn => rx_axis_mac_aresetn_i,
rx_axis_tdata => rx_axis_mac_tdata,
rx_axis_tvalid => rx_axis_mac_tvalid,
rx_axis_tuser => rx_axis_mac_tuser,
rx_axis_tlast => rx_axis_mac_tlast,
rx_axis_tkeep => rx_axis_mac_tkeep,
rx_statistics_vector => RX_STATISTICS_VECTOR,
rx_statistics_valid => RX_STATISTICS_VALID,
pause_val => PAUSE_VAL,
pause_req => PAUSE_REQ,
s_axi_aclk => S_AXI_ACLK,
s_axi_aresetn => S_AXI_ARESETN,
s_axi_awaddr => S_AXI_AWADDR,
s_axi_awvalid => S_AXI_AWVALID,
s_axi_awready => S_AXI_AWREADY,
s_axi_wdata => S_AXI_WDATA,
s_axi_wvalid => S_AXI_WVALID,
s_axi_wready => S_AXI_WREADY,
s_axi_bresp => S_AXI_BRESP,
s_axi_bvalid => S_AXI_BVALID,
s_axi_bready => S_AXI_BREADY,
s_axi_araddr => S_AXI_ARADDR,
s_axi_arvalid => S_AXI_ARVALID,
s_axi_arready => S_AXI_ARREADY,
s_axi_rdata => S_AXI_RDATA,
s_axi_rresp => S_AXI_RRESP,
s_axi_rvalid => S_AXI_RVALID,
s_axi_rready => S_AXI_RREADY,
xgmacint => OPEN,
tx_dcm_locked => qpll_locked,
xgmii_txd => xgmii_txd,
xgmii_txc => xgmii_txc,
rx_clk0 => clk156p25_i,
rx_dcm_locked => qpll_locked,
xgmii_rxd => xgmii_rxd,
xgmii_rxc => xgmii_rxc,
mdc => mdc,
mdio_in => pcspma_mdio_out,
mdio_out => tgemac_mdio_out,
mdio_tri => OPEN
);
-- FIFO
rx_axis_mac_aresetn_i <= NOT RESET;
tx_axis_mac_aresetn_i <= NOT RESET;
rx_axis_fifo_aresetn_i <= (NOT RESET) AND RX_AXIS_FIFO_ARESETN;
tx_axis_fifo_aresetn_i <= (NOT RESET) AND TX_AXIS_FIFO_ARESETN;
ten_gig_eth_mac_fifo_inst : ten_gig_eth_mac_0_xgmac_fifo
GENERIC MAP (
TX_FIFO_SIZE => 512,
RX_FIFO_SIZE => 512
)
PORT MAP (
tx_axis_fifo_aresetn => tx_axis_fifo_aresetn_i,
tx_axis_fifo_aclk => TX_AXIS_FIFO_ACLK,
tx_axis_fifo_tdata => TX_AXIS_FIFO_TDATA,
tx_axis_fifo_tkeep => TX_AXIS_FIFO_TKEEP,
tx_axis_fifo_tvalid => TX_AXIS_FIFO_TVALID,
tx_axis_fifo_tlast => TX_AXIS_FIFO_TLAST,
tx_axis_fifo_tready => TX_AXIS_FIFO_TREADY,
tx_fifo_full => OPEN,
tx_fifo_status => OPEN,
rx_axis_fifo_aresetn => rx_axis_fifo_aresetn_i,
rx_axis_fifo_aclk => RX_AXIS_FIFO_ACLK,
rx_axis_fifo_tdata => RX_AXIS_FIFO_TDATA,
rx_axis_fifo_tkeep => RX_AXIS_FIFO_TKEEP,
rx_axis_fifo_tvalid => RX_AXIS_FIFO_TVALID,
rx_axis_fifo_tlast => RX_AXIS_FIFO_TLAST,
rx_axis_fifo_tready => RX_AXIS_FIFO_TREADY,
rx_fifo_status => OPEN,
--MAC Tx Client Interface
tx_axis_mac_aresetn => tx_axis_mac_aresetn_i,
tx_axis_mac_aclk => clk156p25_i,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tkeep => tx_axis_mac_tkeep,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
--MAC Rx Client Interface
rx_axis_mac_aresetn => rx_axis_mac_aresetn_i,
rx_axis_mac_aclk => clk156p25_i,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tkeep => rx_axis_mac_tkeep,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_fifo_full => OPEN
);
END Behavioral;
| bsd-3-clause | d150f583bd6ca506ca8c9de4b8bde7e0 | 0.534869 | 3.290951 | false | false | false | false |
nxt4hll/roccc-2.0 | roccc-compiler/src/llvm-2.3/include/rocccLibrary/DoubleWordVoter.vhd | 1 | 1,664 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DoubleWordVoter is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
inputReady : in STD_LOGIC;
outputReady : out STD_LOGIC;
done : out STD_LOGIC;
stall : in STD_LOGIC;
error : out STD_LOGIC;
val0_in : in STD_LOGIC_VECTOR(31 downto 0);
val1_in : in STD_LOGIC_VECTOR(31 downto 0);
val2_in : in STD_LOGIC_VECTOR(31 downto 0);
val0_out : out STD_LOGIC_VECTOR(31 downto 0);
val1_out : out STD_LOGIC_VECTOR(31 downto 0);
val2_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end DoubleWordVoter;
architecture Behavioral of DoubleWordVoter is
begin
process(clk, rst)
begin
if( rst = '1' ) then
elsif( clk'event and clk = '1' ) then
val0_out <= (others=>'0');
error0 <= '1';
if( val0_in = val1_in ) then
val0_out <= val0_in;
error0 <= '0';
end if;
end if;
end process;
process(clk, rst)
begin
if( rst = '1' ) then
elsif( clk'event and clk = '1' ) then
val1_out <= (others=>'0');
error1 <= '1';
if( val0_in = val1_in ) then
val1_out <= val0_in;
error1 <= '0';
end if;
end if;
end process;
process(clk, rst)
begin
if( rst = '1' ) then
elsif( clk'event and clk = '1' ) then
val2_out <= (others=>'0');
error2 <= '1';
if( val0_in = val1_in ) then
val2_out <= val0_in;
error2 <= '0';
end if;
end if;
end process;
end Behavioral;
| epl-1.0 | cf4f739a70ff1b8189544182cabb7f65 | 0.603365 | 2.909091 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/aurora_16b.vhd | 4 | 36,984 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/21 23:26:37 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: aurora_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.3 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- aurora_16b
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: This is the top level module for a 1 2-byte lane Aurora
-- reference design module. This module supports the following features:
--
-- * Immediate Mode Native Flow Control
-- * Supports Virtex 2 Pro
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synthesis translate_off
library UNISIM;
use UNISIM.all;
-- synthesis translate_on
entity aurora_16b is
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- LocalLink TX Interface
TX_D : in std_logic_vector(0 to 15);
TX_REM : in std_logic;
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
TX_DST_RDY_N : out std_logic;
-- LocalLink RX Interface
RX_D : out std_logic_vector(0 to 15);
RX_REM : out std_logic;
RX_SRC_RDY_N : out std_logic;
RX_SOF_N : out std_logic;
RX_EOF_N : out std_logic;
-- Native Flow Control Interface
NFC_REQ_N : in std_logic;
NFC_NB : in std_logic_vector(0 to 3);
NFC_ACK_N : out std_logic;
-- MGT Serial I/O
RXP : in std_logic;
RXN : in std_logic;
TXP : out std_logic;
TXN : out std_logic;
-- MGT Reference Clock Interface
TOP_BREF_CLK : in std_logic;
-- Error Detection Interface
HARD_ERROR : out std_logic;
SOFT_ERROR : out std_logic;
FRAME_ERROR : out std_logic;
-- Status
CHANNEL_UP : out std_logic;
LANE_UP : out std_logic;
-- Clock Compensation Control Interface
WARN_CC : in std_logic;
DO_CC : in std_logic;
-- System Interface
DCM_NOT_LOCKED : in std_logic;
USER_CLK : in std_logic;
RESET : in std_logic;
POWER_DOWN : in std_logic;
LOOPBACK : in std_logic_vector(1 downto 0)
);
end aurora_16b;
architecture MAPPED of aurora_16b is
-- External Register Declarations --
signal TX_DST_RDY_N_Buffer : std_logic;
signal RX_D_Buffer : std_logic_vector(0 to 15);
signal RX_REM_Buffer : std_logic;
signal RX_SRC_RDY_N_Buffer : std_logic;
signal RX_SOF_N_Buffer : std_logic;
signal RX_EOF_N_Buffer : std_logic;
signal NFC_ACK_N_Buffer : std_logic;
signal TXP_Buffer : std_logic;
signal TXN_Buffer : std_logic;
signal HARD_ERROR_Buffer : std_logic;
signal SOFT_ERROR_Buffer : std_logic;
signal FRAME_ERROR_Buffer : std_logic;
signal CHANNEL_UP_Buffer : std_logic;
signal LANE_UP_Buffer : std_logic;
-- Wire Declarations --
signal rx_data_i : std_logic_vector(15 downto 0);
signal rx_not_in_table_i : std_logic_vector(1 downto 0);
signal rx_disp_err_i : std_logic_vector(1 downto 0);
signal rx_char_is_k_i : std_logic_vector(1 downto 0);
signal rx_char_is_comma_i : std_logic_vector(1 downto 0);
signal rx_buf_status_i : std_logic;
signal tx_buf_err_i : std_logic;
signal tx_k_err_i : std_logic_vector(1 downto 0);
signal rx_clk_cor_cnt_i : std_logic_vector(2 downto 0);
signal rx_realign_i : std_logic;
signal rx_polarity_i : std_logic;
signal rx_reset_i : std_logic;
signal tx_char_is_k_i : std_logic_vector(1 downto 0);
signal tx_data_i : std_logic_vector(15 downto 0);
signal tx_reset_i : std_logic;
signal ena_comma_align_i : std_logic;
signal gen_scp_i : std_logic;
signal gen_snf_i : std_logic;
signal fc_nb_i : std_logic_vector(0 to 3);
signal gen_ecp_i : std_logic;
signal gen_pad_i : std_logic;
signal tx_pe_data_i : std_logic_vector(0 to 15);
signal tx_pe_data_v_i : std_logic;
signal gen_cc_i : std_logic;
signal rx_pad_i : std_logic;
signal rx_pe_data_i : std_logic_vector(0 to 15);
signal rx_pe_data_v_i : std_logic;
signal rx_scp_i : std_logic;
signal rx_ecp_i : std_logic;
signal rx_snf_i : std_logic;
signal rx_fc_nb_i : std_logic_vector(0 to 3);
signal gen_a_i : std_logic;
signal gen_k_i : std_logic_vector(0 to 1);
signal gen_r_i : std_logic_vector(0 to 1);
signal gen_v_i : std_logic_vector(0 to 1);
signal lane_up_i : std_logic;
signal soft_error_i : std_logic;
signal hard_error_i : std_logic;
signal channel_bond_load_i : std_logic;
signal got_a_i : std_logic_vector(0 to 1);
signal got_v_i : std_logic;
signal reset_lanes_i : std_logic;
signal rx_rec_clk_i : std_logic;
signal ena_calign_rec_i : std_logic;
signal txcharisk_lane_0_i : std_logic_vector(3 downto 0);
signal txdata_lane_0_i : std_logic_vector(31 downto 0);
signal refclksel_lane_0_i : std_logic;
signal txbypass8b10b_lane_0_i : std_logic_vector(3 downto 0);
signal txchardispmode_lane_0_i : std_logic_vector(3 downto 0);
signal txchardispval_lane_0_i : std_logic_vector(3 downto 0);
signal configenable_lane_0_i : std_logic;
signal configin_lane_0_i : std_logic;
signal txforcecrcerr_lane_0_i : std_logic;
signal txinhibit_lane_0_i : std_logic;
signal txpolarity_lane_0_i : std_logic;
signal rxdata_lane_0_i : std_logic_vector(31 downto 0);
signal rxnotintable_lane_0_i : std_logic_vector(3 downto 0);
signal rxdisperr_lane_0_i : std_logic_vector(3 downto 0);
signal rxcharisk_lane_0_i : std_logic_vector(3 downto 0);
signal rxchariscomma_lane_0_i : std_logic_vector(3 downto 0);
signal rxbufstatus_lane_0_i : std_logic_vector(1 downto 0);
signal txkerr_lane_0_i : std_logic_vector(3 downto 0);
signal ch_bond_done_i : std_logic;
signal en_chan_sync_i : std_logic;
signal channel_up_i : std_logic;
signal start_rx_i : std_logic;
signal tx_wait_i : std_logic;
signal decrement_nfc_i : std_logic;
signal chbondi_not_used_i : std_logic_vector(3 downto 0);
signal chbondo_not_used_i : std_logic_vector(3 downto 0);
signal tied_to_ground_i : std_logic;
signal tied_to_vcc_i : std_logic;
signal system_reset_c : std_logic;
signal fc_nb_not_used_i : std_logic_vector(0 to 3);
-- Component Declarations --
component FD
generic (INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic
);
end component;
component AURORA_LANE
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
RX_DATA : in std_logic_vector(15 downto 0); -- 2-byte data bus from the MGT.
RX_NOT_IN_TABLE : in std_logic_vector(1 downto 0); -- Invalid 10-bit code was recieved.
RX_DISP_ERR : in std_logic_vector(1 downto 0); -- Disparity error detected on RX interface.
RX_CHAR_IS_K : in std_logic_vector(1 downto 0); -- Indicates which bytes of RX_DATA are control.
RX_CHAR_IS_COMMA : in std_logic_vector(1 downto 0); -- Comma received on given byte.
RX_BUF_STATUS : in std_logic; -- Overflow/Underflow of RX buffer detected.
TX_BUF_ERR : in std_logic; -- Overflow/Underflow of TX buffer detected.
TX_K_ERR : in std_logic_vector(1 downto 0); -- Attempt to send bad control byte detected.
RX_CLK_COR_CNT : in std_logic_vector(2 downto 0); -- Value used to determine channel bonding status.
RX_REALIGN : in std_logic; -- SERDES was realigned because of a new comma.
RX_POLARITY : out std_logic; -- Controls interpreted polarity of serial data inputs.
RX_RESET : out std_logic; -- Reset RX side of MGT logic.
TX_CHAR_IS_K : out std_logic_vector(1 downto 0); -- TX_DATA byte is a control character.
TX_DATA : out std_logic_vector(15 downto 0); -- 2-byte data bus to the MGT.
TX_RESET : out std_logic; -- Reset TX side of MGT logic.
-- Comma Detect Phase Align Interface
ENA_COMMA_ALIGN : out std_logic; -- Request comma alignment.
-- TX_LL Interface
GEN_SCP : in std_logic; -- SCP generation request from TX_LL.
GEN_ECP : in std_logic; -- ECP generation request from TX_LL.
GEN_SNF : in std_logic; -- SNF generation request from TX_LL.
GEN_PAD : in std_logic; -- PAD generation request from TX_LL.
FC_NB : in std_logic_vector(0 to 3); -- Size code for SUF and SNF messages.
TX_PE_DATA : in std_logic_vector(0 to 15); -- Data from TX_LL to send over lane.
TX_PE_DATA_V : in std_logic; -- Indicates TX_PE_DATA is Valid.
GEN_CC : in std_logic; -- CC generation request from TX_LL.
-- RX_LL Interface
RX_PAD : out std_logic; -- Indicates lane received PAD.
RX_PE_DATA : out std_logic_vector(0 to 15); -- RX data from lane to RX_LL.
RX_PE_DATA_V : out std_logic; -- RX_PE_DATA is data, not control symbol.
RX_SCP : out std_logic; -- Indicates lane received SCP.
RX_ECP : out std_logic; -- Indicates lane received ECP.
RX_SNF : out std_logic; -- Indicates lane received SNF.
RX_FC_NB : out std_logic_vector(0 to 3); -- Size code for SNF or SUF.
-- Global Logic Interface
GEN_A : in std_logic; -- 'A character' generation request from Global Logic.
GEN_K : in std_logic_vector(0 to 1); -- 'K character' generation request from Global Logic.
GEN_R : in std_logic_vector(0 to 1); -- 'R character' generation request from Global Logic.
GEN_V : in std_logic_vector(0 to 1); -- Verification data generation request.
LANE_UP : out std_logic; -- Lane is ready for bonding and verification.
SOFT_ERROR : out std_logic; -- Soft error detected.
HARD_ERROR : out std_logic; -- Hard error detected.
CHANNEL_BOND_LOAD : out std_logic; -- Channel Bonding done code received.
GOT_A : out std_logic_vector(0 to 1); -- Indicates lane recieved 'A character' bytes.
GOT_V : out std_logic; -- Verification symbols received.
-- System Interface
USER_CLK : in std_logic; -- System clock for all non-MGT Aurora Logic.
RESET : in std_logic -- Reset the lane.
);
end component;
component PHASE_ALIGN
port (
-- Aurora Lane Interface
ENA_COMMA_ALIGN : in std_logic;
-- MGT Interface
RX_REC_CLK : in std_logic;
ENA_CALIGN_REC : out std_logic
);
end component;
component GT_CUSTOM
generic (ALIGN_COMMA_MSB : boolean;
CHAN_BOND_MODE : string;
CHAN_BOND_ONE_SHOT : boolean;
CHAN_BOND_SEQ_1_1 : bit_vector;
REF_CLK_V_SEL : integer;
CLK_COR_INSERT_IDLE_FLAG : boolean;
CLK_COR_KEEP_IDLE : boolean;
CLK_COR_REPEAT_WAIT : integer;
CLK_COR_SEQ_1_1 : bit_vector;
CLK_COR_SEQ_1_2 : bit_vector;
CLK_COR_SEQ_2_USE : boolean;
CLK_COR_SEQ_LEN : integer;
CLK_CORRECT_USE : boolean;
COMMA_10B_MASK : bit_vector;
MCOMMA_10B_VALUE : bit_vector;
PCOMMA_10B_VALUE : bit_vector;
RX_CRC_USE : boolean;
RX_DATA_WIDTH : integer;
RX_LOSS_OF_SYNC_FSM : boolean;
RX_LOS_INVALID_INCR : integer;
RX_LOS_THRESHOLD : integer;
SERDES_10B : boolean;
TERMINATION_IMP : integer;
TX_CRC_USE : boolean;
TX_DATA_WIDTH : integer;
TX_DIFF_CTRL : integer;
TX_PREEMPHASIS : integer);
port (
CHBONDDONE : out std_logic;
CHBONDO : out std_logic_vector(3 downto 0);
CONFIGOUT : out std_logic;
RXBUFSTATUS : out std_logic_vector(1 downto 0);
RXCHARISCOMMA : out std_logic_vector(3 downto 0);
RXCHARISK : out std_logic_vector(3 downto 0);
RXCHECKINGCRC : out std_logic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_logic;
RXCRCERR : out std_logic;
RXDATA : out std_logic_vector(31 downto 0);
RXDISPERR : out std_logic_vector(3 downto 0);
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector(3 downto 0);
RXREALIGN : out std_logic;
RXRECCLK : out std_logic;
RXRUNDISP : out std_logic_vector(3 downto 0);
TXBUFERR : out std_logic;
TXKERR : out std_logic_vector(3 downto 0);
TXN : out std_logic;
TXP : out std_logic;
TXRUNDISP : out std_logic_vector(3 downto 0);
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector(3 downto 0);
CONFIGENABLE : in std_logic;
CONFIGIN : in std_logic;
ENCHANSYNC : in std_logic;
ENMCOMMAALIGN : in std_logic;
ENPCOMMAALIGN : in std_logic;
LOOPBACK : in std_logic_vector(1 downto 0);
POWERDOWN : in std_logic;
REFCLK : in std_logic;
REFCLK2 : in std_logic;
REFCLKSEL : in std_logic;
RXN : in std_logic;
RXP : in std_logic;
RXPOLARITY : in std_logic;
RXRESET : in std_logic;
RXUSRCLK : in std_logic;
RXUSRCLK2 : in std_logic;
TXBYPASS8B10B : in std_logic_vector(3 downto 0);
TXCHARDISPMODE : in std_logic_vector(3 downto 0);
TXCHARDISPVAL : in std_logic_vector(3 downto 0);
TXCHARISK : in std_logic_vector(3 downto 0);
TXDATA : in std_logic_vector(31 downto 0);
TXFORCECRCERR : in std_logic;
TXINHIBIT : in std_logic;
TXPOLARITY : in std_logic;
TXRESET : in std_logic;
TXUSRCLK : in std_logic;
TXUSRCLK2 : in std_logic
);
end component;
-- attribute syn_black_box of GT_CUSTOM : component is true;
component GLOBAL_LOGIC
generic (
EXTEND_WATCHDOGS : boolean := FALSE
);
port (
-- MGT Interface
CH_BOND_DONE : in std_logic;
EN_CHAN_SYNC : out std_logic;
-- Aurora Lane Interface
LANE_UP : in std_logic;
SOFT_ERROR : in std_logic;
HARD_ERROR : in std_logic;
CHANNEL_BOND_LOAD : in std_logic;
GOT_A : in std_logic_vector(0 to 1);
GOT_V : in std_logic;
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
RESET_LANES : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_UP : out std_logic;
START_RX : out std_logic;
CHANNEL_SOFT_ERROR : out std_logic;
CHANNEL_HARD_ERROR : out std_logic
);
end component;
component TX_LL
port (
-- LocalLink PDU Interface
TX_D : in std_logic_vector(0 to 15);
TX_REM : in std_logic;
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
TX_DST_RDY_N : out std_logic;
-- NFC Interface
NFC_REQ_N : in std_logic;
NFC_NB : in std_logic_vector(0 to 3);
NFC_ACK_N : out std_logic;
-- Clock Compensation Interface
WARN_CC : in std_logic;
DO_CC : in std_logic;
-- Global Logic Interface
CHANNEL_UP : in std_logic;
-- Aurora Lane Interface
GEN_SCP : out std_logic;
GEN_ECP : out std_logic;
GEN_SNF : out std_logic;
FC_NB : out std_logic_vector(0 to 3);
TX_PE_DATA_V : out std_logic;
GEN_PAD : out std_logic;
TX_PE_DATA : out std_logic_vector(0 to 15);
GEN_CC : out std_logic;
-- RX_LL Interface
TX_WAIT : in std_logic;
DECREMENT_NFC : out std_logic;
-- System Interface
USER_CLK : in std_logic
);
end component;
component RX_LL
port (
-- LocalLink PDU Interface
RX_D : out std_logic_vector(0 to 15);
RX_REM : out std_logic;
RX_SRC_RDY_N : out std_logic;
RX_SOF_N : out std_logic;
RX_EOF_N : out std_logic;
-- Global Logic Interface
START_RX : in std_logic;
-- Aurora Lane Interface
RX_PAD : in std_logic;
RX_PE_DATA : in std_logic_vector(0 to 15);
RX_PE_DATA_V : in std_logic;
RX_SCP : in std_logic;
RX_ECP : in std_logic;
RX_SNF : in std_logic;
RX_FC_NB : in std_logic_vector(0 to 3);
-- TX_LL Interface
DECREMENT_NFC : in std_logic;
TX_WAIT : out std_logic;
-- Error Interface
FRAME_ERROR : out std_logic;
-- System Interface
USER_CLK : in std_logic
);
end component;
begin
TX_DST_RDY_N <= TX_DST_RDY_N_Buffer;
RX_D <= RX_D_Buffer;
RX_REM <= RX_REM_Buffer;
RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer;
RX_SOF_N <= RX_SOF_N_Buffer;
RX_EOF_N <= RX_EOF_N_Buffer;
NFC_ACK_N <= NFC_ACK_N_Buffer;
TXP <= TXP_Buffer;
TXN <= TXN_Buffer;
HARD_ERROR <= HARD_ERROR_Buffer;
SOFT_ERROR <= SOFT_ERROR_Buffer;
FRAME_ERROR <= FRAME_ERROR_Buffer;
CHANNEL_UP <= CHANNEL_UP_Buffer;
LANE_UP <= LANE_UP_Buffer;
-- Main Body of Code --
tied_to_ground_i <= '0';
tied_to_vcc_i <= '1';
chbondi_not_used_i <= "0000";
fc_nb_not_used_i <= "0000";
CHANNEL_UP_Buffer <= channel_up_i;
system_reset_c <= RESET or DCM_NOT_LOCKED;
-- Instantiate Lane 0 --
LANE_UP_Buffer <= lane_up_i;
aurora_lane_0_i : AURORA_LANE
generic map (
EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
)
port map (
-- MGT Interface
RX_DATA => rx_data_i(15 downto 0),
RX_NOT_IN_TABLE => rx_not_in_table_i(1 downto 0),
RX_DISP_ERR => rx_disp_err_i(1 downto 0),
RX_CHAR_IS_K => rx_char_is_k_i(1 downto 0),
RX_CHAR_IS_COMMA => rx_char_is_comma_i(1 downto 0),
RX_BUF_STATUS => rx_buf_status_i,
TX_BUF_ERR => tx_buf_err_i,
TX_K_ERR => tx_k_err_i(1 downto 0),
RX_CLK_COR_CNT => rx_clk_cor_cnt_i(2 downto 0),
RX_REALIGN => rx_realign_i,
RX_POLARITY => rx_polarity_i,
RX_RESET => rx_reset_i,
TX_CHAR_IS_K => tx_char_is_k_i(1 downto 0),
TX_DATA => tx_data_i(15 downto 0),
TX_RESET => tx_reset_i,
-- Comma Detect Phase Align Interface
ENA_COMMA_ALIGN => ena_comma_align_i,
-- TX_LL Interface
GEN_SCP => gen_scp_i,
GEN_SNF => gen_snf_i,
FC_NB => fc_nb_i,
GEN_ECP => gen_ecp_i,
GEN_PAD => gen_pad_i,
TX_PE_DATA => tx_pe_data_i(0 to 15),
TX_PE_DATA_V => tx_pe_data_v_i,
GEN_CC => gen_cc_i,
-- RX_LL Interface
RX_PAD => rx_pad_i,
RX_PE_DATA => rx_pe_data_i(0 to 15),
RX_PE_DATA_V => rx_pe_data_v_i,
RX_SCP => rx_scp_i,
RX_ECP => rx_ecp_i,
RX_SNF => rx_snf_i,
RX_FC_NB => rx_fc_nb_i(0 to 3),
-- Global Logic Interface
GEN_A => gen_a_i,
GEN_K => gen_k_i(0 to 1),
GEN_R => gen_r_i(0 to 1),
GEN_V => gen_v_i(0 to 1),
LANE_UP => lane_up_i,
SOFT_ERROR => soft_error_i,
HARD_ERROR => hard_error_i,
CHANNEL_BOND_LOAD => channel_bond_load_i,
GOT_A => got_a_i(0 to 1),
GOT_V => got_v_i,
-- System Interface
USER_CLK => USER_CLK,
RESET => reset_lanes_i
);
lane_0_phase_align_i : PHASE_ALIGN
port map (
-- Aurora Lane Interface
ENA_COMMA_ALIGN => ena_comma_align_i,
-- MGT Interface
RX_REC_CLK => rx_rec_clk_i,
ENA_CALIGN_REC => ena_calign_rec_i
);
txcharisk_lane_0_i <= "00" & tx_char_is_k_i(1 downto 0);
txdata_lane_0_i <= "0000000000000000" & tx_data_i(15 downto 0);
refclksel_lane_0_i <= '0';
txbypass8b10b_lane_0_i <= "0000";
txchardispmode_lane_0_i <= "0000";
txchardispval_lane_0_i <= "0000";
configenable_lane_0_i <= '0';
configin_lane_0_i <= '0';
txforcecrcerr_lane_0_i <= '0';
txinhibit_lane_0_i <= '0';
txpolarity_lane_0_i <= '0';
rx_data_i(15 downto 0) <= rxdata_lane_0_i(15 downto 0);
rx_not_in_table_i(1 downto 0) <= rxnotintable_lane_0_i(1 downto 0);
rx_disp_err_i(1 downto 0) <= rxdisperr_lane_0_i(1 downto 0);
rx_char_is_k_i(1 downto 0) <= rxcharisk_lane_0_i(1 downto 0);
rx_char_is_comma_i(1 downto 0) <= rxchariscomma_lane_0_i(1 downto 0);
rx_buf_status_i <= rxbufstatus_lane_0_i(1);
tx_k_err_i(1 downto 0) <= txkerr_lane_0_i(1 downto 0);
lane_0_mgt_i : GT_CUSTOM
-- Lane 0 MGT attributes
generic map (
ALIGN_COMMA_MSB => TRUE,
CHAN_BOND_MODE => "OFF",
CHAN_BOND_ONE_SHOT => FALSE,
CHAN_BOND_SEQ_1_1 => "00101111100",
REF_CLK_V_SEL => 1,
CLK_COR_INSERT_IDLE_FLAG => FALSE,
CLK_COR_KEEP_IDLE => FALSE,
CLK_COR_REPEAT_WAIT => 8,
CLK_COR_SEQ_1_1 => "00111110111",
CLK_COR_SEQ_1_2 => "00111110111",
CLK_COR_SEQ_2_USE => FALSE,
CLK_COR_SEQ_LEN => 2,
CLK_CORRECT_USE => TRUE,
COMMA_10B_MASK => "1111111111",
MCOMMA_10B_VALUE => "1100000101",
PCOMMA_10B_VALUE => "0011111010",
RX_CRC_USE => FALSE,
RX_DATA_WIDTH => 2,
RX_LOSS_OF_SYNC_FSM => FALSE,
RX_LOS_INVALID_INCR => 1,
RX_LOS_THRESHOLD => 4,
SERDES_10B => FALSE,
TERMINATION_IMP => 50,
TX_CRC_USE => FALSE,
TX_DATA_WIDTH => 2,
TX_DIFF_CTRL => 600,
TX_PREEMPHASIS => 1
)
port map (
-- Aurora Lane Interface
RXPOLARITY => rx_polarity_i,
RXRESET => rx_reset_i,
TXCHARISK => txcharisk_lane_0_i,
TXDATA => txdata_lane_0_i,
TXRESET => tx_reset_i,
RXDATA => rxdata_lane_0_i,
RXNOTINTABLE => rxnotintable_lane_0_i,
RXDISPERR => rxdisperr_lane_0_i,
RXCHARISK => rxcharisk_lane_0_i,
RXCHARISCOMMA => rxchariscomma_lane_0_i,
RXBUFSTATUS => rxbufstatus_lane_0_i,
TXBUFERR => tx_buf_err_i,
TXKERR => txkerr_lane_0_i,
RXCLKCORCNT => rx_clk_cor_cnt_i(2 downto 0),
RXREALIGN => rx_realign_i,
-- Phase Align Interface
ENMCOMMAALIGN => ena_calign_rec_i,
ENPCOMMAALIGN => ena_calign_rec_i,
RXRECCLK => rx_rec_clk_i,
-- Global Logic Interface
ENCHANSYNC => tied_to_ground_i,
CHBONDDONE => ch_bond_done_i,
-- Peer Channel Bonding Interface
CHBONDI => chbondi_not_used_i,
CHBONDO => chbondo_not_used_i(3 downto 0),
-- Unused MGT Ports
CONFIGOUT => open,
RXCHECKINGCRC => open,
RXCOMMADET => open,
RXCRCERR => open,
RXLOSSOFSYNC => open,
RXRUNDISP => open,
TXRUNDISP => open,
-- Fixed MGT settings for Aurora
TXBYPASS8B10B => txbypass8b10b_lane_0_i,
TXCHARDISPMODE => txchardispmode_lane_0_i,
TXCHARDISPVAL => txchardispval_lane_0_i,
CONFIGENABLE => configenable_lane_0_i,
CONFIGIN => configin_lane_0_i,
TXFORCECRCERR => txforcecrcerr_lane_0_i,
TXINHIBIT => txinhibit_lane_0_i,
TXPOLARITY => txpolarity_lane_0_i,
-- Serial IO
RXN => RXN,
RXP => RXP,
TXN => TXN_Buffer,
TXP => TXP_Buffer,
-- Reference Clocks and User Clock
RXUSRCLK => USER_CLK,
RXUSRCLK2 => USER_CLK,
TXUSRCLK => USER_CLK,
TXUSRCLK2 => USER_CLK,
BREFCLK => TOP_BREF_CLK,
BREFCLK2 => tied_to_ground_i,
REFCLK => tied_to_ground_i,
REFCLK2 => tied_to_ground_i,
REFCLKSEL => refclksel_lane_0_i,
-- System Interface
LOOPBACK => LOOPBACK,
POWERDOWN => POWER_DOWN
);
-- Instantiate Global Logic to combine Lanes into a Channel --
global_logic_i : GLOBAL_LOGIC
generic map (
EXTEND_WATCHDOGS => EXTEND_WATCHDOGS
)
port map (
-- MGT Interface
CH_BOND_DONE => ch_bond_done_i,
EN_CHAN_SYNC => en_chan_sync_i,
-- Aurora Lane Interface
LANE_UP => lane_up_i,
SOFT_ERROR => soft_error_i,
HARD_ERROR => hard_error_i,
CHANNEL_BOND_LOAD => channel_bond_load_i,
GOT_A => got_a_i,
GOT_V => got_v_i,
GEN_A => gen_a_i,
GEN_K => gen_k_i,
GEN_R => gen_r_i,
GEN_V => gen_v_i,
RESET_LANES => reset_lanes_i,
-- System Interface
USER_CLK => USER_CLK,
RESET => system_reset_c,
POWER_DOWN => POWER_DOWN,
CHANNEL_UP => channel_up_i,
START_RX => start_rx_i,
CHANNEL_SOFT_ERROR => SOFT_ERROR_Buffer,
CHANNEL_HARD_ERROR => HARD_ERROR_Buffer
);
-- Instantiate TX_LL --
tx_ll_i : TX_LL
port map (
-- LocalLink PDU Interface
TX_D => TX_D,
TX_REM => TX_REM,
TX_SRC_RDY_N => TX_SRC_RDY_N,
TX_SOF_N => TX_SOF_N,
TX_EOF_N => TX_EOF_N,
TX_DST_RDY_N => TX_DST_RDY_N_Buffer,
-- NFC Interface
NFC_REQ_N => NFC_REQ_N,
NFC_NB => NFC_NB,
NFC_ACK_N => NFC_ACK_N_Buffer,
-- Clock Compenstaion Interface
WARN_CC => WARN_CC,
DO_CC => DO_CC,
-- Global Logic Interface
CHANNEL_UP => channel_up_i,
-- Aurora Lane Interface
GEN_SCP => gen_scp_i,
GEN_ECP => gen_ecp_i,
GEN_SNF => gen_snf_i,
FC_NB => fc_nb_i,
TX_PE_DATA_V => tx_pe_data_v_i,
GEN_PAD => gen_pad_i,
TX_PE_DATA => tx_pe_data_i,
GEN_CC => gen_cc_i,
-- RX_LL Interface
TX_WAIT => tx_wait_i,
DECREMENT_NFC => decrement_nfc_i,
-- System Interface
USER_CLK => USER_CLK
);
-- Instantiate RX_LL --
rx_ll_i : RX_LL
port map (
-- LocalLink PDU Interface
RX_D => RX_D_Buffer,
RX_REM => RX_REM_Buffer,
RX_SRC_RDY_N => RX_SRC_RDY_N_Buffer,
RX_SOF_N => RX_SOF_N_Buffer,
RX_EOF_N => RX_EOF_N_Buffer,
-- Global Logic Interface
START_RX => start_rx_i,
-- Aurora Lane Interface
RX_PAD => rx_pad_i,
RX_PE_DATA => rx_pe_data_i,
RX_PE_DATA_V => rx_pe_data_v_i,
RX_SCP => rx_scp_i,
RX_ECP => rx_ecp_i,
RX_SNF => rx_snf_i,
RX_FC_NB => rx_fc_nb_i,
-- TX_LL Interface
DECREMENT_NFC => decrement_nfc_i,
TX_WAIT => tx_wait_i,
-- Error Interface
FRAME_ERROR => FRAME_ERROR_Buffer,
-- System Interface
USER_CLK => USER_CLK
);
end MAPPED;
| bsd-2-clause | a5632aef0dc3b2e8b07bc21cbcc55d20 | 0.434404 | 4.119862 | false | false | false | false |
ymei/TMSPlane | Firmware/test_bench/shiftreg_drive_tb.vhd | 2 | 6,005 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:39:52 01/07/2015
-- Design Name: shiftreg_drive_tb
-- Module Name:
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: shiftreg_drive
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE IEEE.NUMERIC_STD.ALL;
ENTITY shiftreg_drive_tb IS
END shiftreg_drive_tb;
ARCHITECTURE behavior OF shiftreg_drive_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shiftreg_drive
GENERIC (
DATA_WIDTH : positive := 32; -- parallel data width
CLK_DIV_WIDTH : positive := 16;
DELAY_AFTER_SYNCn : natural := 0; -- number of SCLK cycles' wait after falling edge OF SYNCn
SCLK_IDLE_LEVEL : std_logic := '0'; -- High or Low for SCLK when not switching
DOUT_DRIVE_EDGE : std_logic := '1'; -- 1/0 rising/falling edge of SCLK drives new DOUT bit
DIN_CAPTURE_EDGE : std_logic := '0' -- 1/0 rising/falling edge of SCLK captures new DIN bit
);
PORT (
CLK : IN std_logic;
RESET : IN std_logic;
CLK_DIV : IN std_logic_vector(CLK_DIV_WIDTH-1 DOWNTO 0); -- SCLK freq is CLK / 2**(CLK_DIV)
DATAIN : IN std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
START : IN std_logic;
BUSY : OUT std_logic;
DATAOUT : OUT std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
SCLK : OUT std_logic;
DOUT : OUT std_logic;
SYNCn : OUT std_logic;
DIN : IN std_logic
);
END COMPONENT;
COMPONENT edge_sync
GENERIC (
EDGE : std_logic := '1' -- '1' : rising edge, '0' falling edge
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
EI : IN std_logic;
SO : OUT std_logic
);
END COMPONENT;
COMPONENT fifo16to32
PORT (
RST : IN std_logic;
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
DIN : IN std_logic_vector(15 DOWNTO 0);
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DOUT : OUT std_logic_vector(31 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL CLK : std_logic := '0';
SIGNAL CLK_DIV : std_logic_vector(15 DOWNTO 0) := x"0003";
SIGNAL RESET : std_logic := '0';
SIGNAL DATAIN : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL START : std_logic := '0';
SIGNAL DIN : std_logic;
--Outputs
SIGNAL DATAOUT : std_logic_vector(31 DOWNTO 0);
SIGNAL BUSY : std_logic;
SIGNAL SCLK : std_logic;
SIGNAL DOUT : std_logic;
SIGNAL SYNCn : std_logic;
-- internals
SIGNAL wr_start : std_logic := '0';
SIGNAL fifo_din : std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL fifo_wr_en : std_logic;
SIGNAL fifo_rd_en : std_logic;
SIGNAL fifo_full : std_logic;
SIGNAL fifo_empty : std_logic;
-- Clock period definitions
CONSTANT CLK_period : time := 10 ns;
CONSTANT SCLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : shiftreg_drive PORT MAP (
CLK => CLK,
CLK_DIV => CLK_DIV,
RESET => RESET,
DATAIN => DATAIN,
START => START,
BUSY => BUSY,
DATAOUT => DATAOUT,
SCLK => SCLK,
DOUT => DOUT,
SYNCn => SYNCn,
DIN => DIN
);
DIN <= DOUT;
fifo : fifo16to32
PORT MAP (
RST => RESET,
WR_CLK => CLK,
RD_CLK => CLK,
DIN => fifo_din,
WR_EN => fifo_wr_en,
RD_EN => fifo_rd_en,
DOUT => DATAIN,
FULL => fifo_full,
EMPTY => fifo_empty
);
START <= NOT fifo_empty;
-- rising edge of busy
rd_es : edge_sync
GENERIC MAP (
EDGE => '1' -- '1' : rising edge, '0' falling edge
)
PORT MAP (
RESET => RESET,
CLK => CLK,
EI => BUSY,
SO => fifo_rd_en
);
wr_es : edge_sync
GENERIC MAP (
EDGE => '1' -- '1' : rising edge, '0' falling edge
)
PORT MAP (
RESET => RESET,
CLK => CLK,
EI => wr_start,
SO => fifo_wr_en
);
-- Clock process definitions
CLK_process : PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_period/2;
CLK <= '1';
WAIT FOR CLK_period/2;
END PROCESS;
-- Stimulus process
stim_proc : PROCESS
BEGIN
WAIT FOR 25ns;
-- hold reset state for 80 ns.
RESET <= '1';
WAIT FOR 80 ns;
RESET <= '0';
WAIT FOR CLK_period*12;
-- insert stimulus here
WAIT FOR 10ps;
fifo_din <= x"505a";
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
fifo_din <= x"a505";
WAIT FOR CLK_period;
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
WAIT FOR 20ns;
fifo_din <= x"abcd";
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
fifo_din <= x"1234";
WAIT FOR CLK_period;
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
WAIT FOR 1100ns;
fifo_din <= x"4321";
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
fifo_din <= x"dcba";
WAIT FOR CLK_period;
wr_start <= '1';
WAIT FOR CLK_period*3;
wr_start <= '0';
WAIT;
END PROCESS;
END;
| bsd-3-clause | 1d84a3545737bcc96729f055cbc85c83 | 0.549542 | 3.445209 | false | false | false | false |
apoloval/avionica | vhdl/ic74595_tb.vhdl | 1 | 1,894 | library ieee;
use ieee.std_logic_1164.all;
entity ic74595_tb is
end ic74595_tb;
architecture behavior of ic74595_tb is
component ic74595
port (ds : in std_logic;
shcp : in std_logic;
mr : in std_logic;
stcp : in std_logic;
oe : in std_logic;
q : out std_logic_vector(7 downto 0);
q7s : out std_logic);
end component;
signal clock: std_logic := '0';
signal serial: std_logic := '0';
signal clear: std_logic := '1';
signal load: std_logic := '0';
signal oe: std_logic := '0';
signal q: std_logic_vector(0 to 7) := "00000000";
signal sout: std_logic;
for ic: ic74595 use entity work.ic74595;
begin
ic: ic74595 port map (ds => serial,
shcp => clock,
mr => clear,
stcp => load,
oe => oe,
q => q,
q7s => sout);
process
constant byte: std_logic_vector(7 downto 0) := "01001101";
begin
report "should output Z when not OE";
oe <= '1';
wait for 10 ns;
assert q = "ZZZZZZZZ" report "Q is not Z";
oe <= '0';
wait for 10 ns;
assert q /= "ZZZZZZZZ" report "Q is Z";
report "should shift some data in";
for i in byte'range loop
serial <= byte(i);
clock <= '1'; wait for 4 ns; clock <= '0'; wait for 4 ns;
end loop;
load <= '1'; wait for 4 ns; load <= '0'; wait for 4 ns;
assert q = "01001101";
report "should write rightmost bit in serial out";
assert sout = '0';
clock <= '1'; wait for 4 ns; clock <= '0'; wait for 4 ns;
assert sout = '1';
report "should clear on signal";
clear <= '0';
wait for 10 ns;
load <= '1'; wait for 4 ns; load <= '0'; wait for 4 ns;
assert q = "00000000";
report "end of test";
wait;
end process;
end behavior;
| mpl-2.0 | bc6e33695be223bb20c72dc9044a17df | 0.529039 | 3.475229 | false | false | false | false |
biximilien/ArithmeticLogicUnit | adder_n.vhd | 1 | 2,158 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Cadre : GEN1333 - Conception des circuits integrés --
-- : Projet de conception individuel 1 --
-- Par : Maxime Gauthier --
-- Date : 03 / 21 / 2015 --
-- Fichier : adder_n.vhd --
-- Description : VHDL pour une unité arithmétique logique générique (n bits) --
-- : basé sur du matériel de cours fourni par Ahmed Lakhsassi --
-- : et du code originellement écrit par Antoine Shaneen --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- librairie a inclure
library ieee;
use ieee.std_logic_1164.all;
-- déclaration de l'entité de l'additionneur générique (n bits) paramétrable
entity adder_n is
generic ( N : integer := 8);
port (
augend, addend : in std_logic_vector ( N downto 1 );
sum : out std_logic_vector ( N downto 1 );
carry_in : in std_logic;
carry_out : out std_logic
);
end adder_n;
-- architecture structurelle de l'additionneur générique (n bits).
architecture adder_n_impl of adder_n is
-- declare components
component adder
port(
augend, addend, carry_in : in std_logic;
sum, carry_out : out std_logic
);
end component;
-- declare signal
signal cs : std_logic_vector ( N downto 0 ); -- pour garder le carry
begin
cs(0) <= carry_in;
carry_out <= cs(N);
--instantiation de l'additionneur de 1 bit n fois
summator : for i in 1 to N generate
sum_n : adder
port map (
augend => augend(i),
addend => addend(i),
carry_in => cs(i-1),
sum => sum(i),
carry_out => cs(i)
);
end generate summator;
end adder_n_impl;
| mit | 59250232356445c8f2a07b82883c848d | 0.44657 | 4.294589 | false | false | false | false |
inmcm/Simon_Speck_Ciphers | VHDL/AXI_IP/Speck_Block_Cipher_Multirate_1.0/src/mux_synchronizer.vhd | 1 | 1,429 | -- Mux_Synchronizer.vhd
-- Copyright 2016 Michael Calvin McCoy
-- [email protected]
-- see LICENSE.md
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity MUX_SYNCHRONIZER is
Generic(BUS_SIZE : integer range 0 to 256 := 128);
Port ( CLK_A, CLK_B, RST : in std_logic;
DATA_BUS_A_IN : in std_logic_vector (BUS_SIZE - 1 downto 0);
DATA_BUS_B_OUT : out std_logic_vector (BUS_SIZE - 1 downto 0));
end MUX_SYNCHRONIZER;
architecture Behavioral of MUX_SYNCHRONIZER is
signal begin_sync : std_logic_vector(5 downto 0);
signal data_input_buffer : std_logic_vector(BUS_SIZE - 1 downto 0);
signal sync_chain : std_logic_vector(1 downto 0);
begin
CLK_A_PROCESS : process(CLK_A)
begin
if(CLK_A'event and CLK_A = '1') then
data_input_buffer <= DATA_BUS_A_IN;
if (RST = '1' or data_input_buffer /= DATA_BUS_A_IN) then
begin_sync <= (OTHERS => '1');
else
begin_sync <= begin_sync(4 downto 0) & '0';
end if;
end if;
end process;
CLK_B_PROCESS : process(CLK_B)
begin
if(CLK_B'event and CLK_B = '1') then
sync_chain <= sync_chain(0) & begin_sync(5);
if (sync_chain(1) = '1') then
DATA_BUS_B_OUT <= data_input_buffer;
end if;
end if;
end process;
end Behavioral; | mit | c5c7808796b6e6f0f6dbcee960730219 | 0.575227 | 3.270023 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo_generator_v10_0.vhd | 9 | 87,162 | `protect begin_protected
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| gpl-3.0 | c9dd13da7eb72011b805e17fde137f98 | 0.952456 | 1.817731 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_dc_as.vhd | 9 | 10,607 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6112)
`protect data_block
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| gpl-3.0 | 51c988247fa47c18d678b365a134accf | 0.926464 | 1.91186 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/edidram/example_design/edidram_prod.vhd | 3 | 10,241 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: edidram_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY edidram_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END edidram_prod;
ARCHITECTURE xilinx OF edidram_prod IS
COMPONENT edidram_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : edidram_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| bsd-2-clause | 202f2a9baf0dc962040c6941eb93daf6 | 0.491163 | 3.839895 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/clkGen/simulation/clkGen_tb.vhd | 3 | 6,159 | -- file: clkGen_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clkGen_tb is
end clkGen_tb;
architecture test of clkGen_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(3 downto 1);
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(3 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clkGen_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(3 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(3 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clkGen_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| bsd-2-clause | f6ea681b4fe598240cf3e4cda43efed1 | 0.639065 | 4.280056 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/rx_ll.vhd | 4 | 6,784 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/12/15 01:59:13 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: rx_ll_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.5 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- RX_LL
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: The RX_LL module receives data from the Aurora Channel,
-- converts it to LocalLink and sends it to the user interface.
-- It also handles NFC and UFC messages.
--
-- This module supports 1 2-byte lane designs.
--
-- This module supports Immediate Mode Native Flow Control.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RX_LL is
port (
-- LocalLink PDU Interface
RX_D : out std_logic_vector(0 to 15);
RX_REM : out std_logic;
RX_SRC_RDY_N : out std_logic;
RX_SOF_N : out std_logic;
RX_EOF_N : out std_logic;
-- Global Logic Interface
START_RX : in std_logic;
-- Aurora Lane Interface
RX_PAD : in std_logic;
RX_PE_DATA : in std_logic_vector(0 to 15);
RX_PE_DATA_V : in std_logic;
RX_SCP : in std_logic;
RX_ECP : in std_logic;
RX_SNF : in std_logic;
RX_FC_NB : in std_logic_vector(0 to 3);
-- TX_LL Interface
DECREMENT_NFC : in std_logic;
TX_WAIT : out std_logic;
-- Error Interface
FRAME_ERROR : out std_logic;
-- System Interface
USER_CLK : in std_logic
);
end RX_LL;
architecture MAPPED of RX_LL is
-- External Register Declarations --
signal RX_D_Buffer : std_logic_vector(0 to 15);
signal RX_REM_Buffer : std_logic;
signal RX_SRC_RDY_N_Buffer : std_logic;
signal RX_SOF_N_Buffer : std_logic;
signal RX_EOF_N_Buffer : std_logic;
signal TX_WAIT_Buffer : std_logic;
signal FRAME_ERROR_Buffer : std_logic;
-- Wire Declarations --
signal start_rx_i : std_logic;
-- Component Declarations --
component RX_LL_NFC
port (
-- Aurora Lane Interface
RX_SNF : in std_logic;
RX_FC_NB : in std_logic_vector(0 to 3);
-- TX_LL Interface
DECREMENT_NFC : in std_logic;
TX_WAIT : out std_logic;
-- Global Logic Interface
CHANNEL_UP : in std_logic;
-- USER Interface
USER_CLK : in std_logic
);
end component;
component RX_LL_PDU_DATAPATH
port (
-- Traffic Separator Interface
PDU_DATA : in std_logic_vector(0 to 15);
PDU_DATA_V : in std_logic;
PDU_PAD : in std_logic;
PDU_SCP : in std_logic;
PDU_ECP : in std_logic;
-- LocalLink PDU Interface
RX_D : out std_logic_vector(0 to 15);
RX_REM : out std_logic;
RX_SRC_RDY_N : out std_logic;
RX_SOF_N : out std_logic;
RX_EOF_N : out std_logic;
-- Error Interface
FRAME_ERROR : out std_logic;
-- System Interface
USER_CLK : in std_logic;
RESET : in std_logic
);
end component;
begin
RX_D <= RX_D_Buffer;
RX_REM <= RX_REM_Buffer;
RX_SRC_RDY_N <= RX_SRC_RDY_N_Buffer;
RX_SOF_N <= RX_SOF_N_Buffer;
RX_EOF_N <= RX_EOF_N_Buffer;
TX_WAIT <= TX_WAIT_Buffer;
FRAME_ERROR <= FRAME_ERROR_Buffer;
start_rx_i <= not START_RX;
-- Main Body of Code --
-- NFC processing --
nfc_module_i : RX_LL_NFC
port map (
-- Aurora Lane Interface
RX_SNF => RX_SNF,
RX_FC_NB => RX_FC_NB,
-- TX_LL Interface
DECREMENT_NFC => DECREMENT_NFC,
TX_WAIT => TX_WAIT_Buffer,
-- Global Logic Interface
CHANNEL_UP => START_RX,
-- USER Interface
USER_CLK => USER_CLK
);
-- Datapath for user PDUs --
rx_ll_pdu_datapath_i : RX_LL_PDU_DATAPATH
port map (
-- Traffic Separator Interface
PDU_DATA => RX_PE_DATA,
PDU_DATA_V => RX_PE_DATA_V,
PDU_PAD => RX_PAD,
PDU_SCP => RX_SCP,
PDU_ECP => RX_ECP,
-- LocalLink PDU Interface
RX_D => RX_D_Buffer,
RX_REM => RX_REM_Buffer,
RX_SRC_RDY_N => RX_SRC_RDY_N_Buffer,
RX_SOF_N => RX_SOF_N_Buffer,
RX_EOF_N => RX_EOF_N_Buffer,
-- Error Interface
FRAME_ERROR => FRAME_ERROR_Buffer,
-- System Interface
USER_CLK => USER_CLK,
RESET => start_rx_i
);
end MAPPED;
| bsd-2-clause | 49450590ed474e61bdbd4e93e8d636a1 | 0.479511 | 4.062275 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/sym_dec.vhd | 4 | 27,303 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: sym_dec_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- SYM_DEC
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description: The SYM_DEC module is a symbol decoder for the 2-byte
-- Aurora Lane. Its inputs are the raw data from the MGT.
-- It word-aligns the regular data and decodes all of the
-- Aurora control symbols. Its outputs are the word-aligned
-- data and signals indicating the arrival of specific
-- control characters.
--
-- This module supports Immediate Mode Native Flow Control.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.AURORA.all;
entity SYM_DEC is
port (
-- RX_LL Interface
RX_PAD : out std_logic; -- LSByte is PAD.
RX_PE_DATA : out std_logic_vector(0 to 15); -- Word aligned data from channel partner.
RX_PE_DATA_V : out std_logic; -- Data is valid data and not a control character.
RX_SCP : out std_logic; -- SCP symbol received.
RX_ECP : out std_logic; -- ECP symbol received.
RX_SNF : out std_logic; -- SNF symbol received.
RX_FC_NB : out std_logic_vector(0 to 3); -- Flow Control size code. Valid with RX_SNF or RX_SUF.
-- Lane Init SM Interface
DO_WORD_ALIGN : in std_logic; -- Word alignment is allowed.
RX_SP : out std_logic; -- SP sequence received with positive or negative data.
RX_SPA : out std_logic; -- SPA sequence received.
RX_NEG : out std_logic; -- Intverted data for SP or SPA received.
-- Global Logic Interface
GOT_A : out std_logic_vector(0 to 1); -- A character received on indicated byte(s).
GOT_V : out std_logic; -- V sequence received.
-- MGT Interface
RX_DATA : in std_logic_vector(15 downto 0); -- Raw RX data from MGT.
RX_CHAR_IS_K : in std_logic_vector(1 downto 0); -- Bits indicating which bytes are control characters.
RX_CHAR_IS_COMMA : in std_logic_vector(1 downto 0); -- Rx'ed a comma.
-- System Interface
USER_CLK : in std_logic; -- System clock for all non-MGT Aurora Logic.
RESET : in std_logic
);
end SYM_DEC;
architecture RTL of SYM_DEC is
-- Parameter Declarations --
constant DLY : time := 1 ns;
constant K_CHAR_0 : std_logic_vector(0 to 3) := X"B";
constant K_CHAR_1 : std_logic_vector(0 to 3) := X"C";
constant SP_DATA_0 : std_logic_vector(0 to 3) := X"4";
constant SP_DATA_1 : std_logic_vector(0 to 3) := X"A";
constant SPA_DATA_0 : std_logic_vector(0 to 3) := X"2";
constant SPA_DATA_1 : std_logic_vector(0 to 3) := X"C";
constant SP_NEG_DATA_0 : std_logic_vector(0 to 3) := X"B";
constant SP_NEG_DATA_1 : std_logic_vector(0 to 3) := X"5";
constant SPA_NEG_DATA_0 : std_logic_vector(0 to 3) := X"D";
constant SPA_NEG_DATA_1 : std_logic_vector(0 to 3) := X"3";
constant PAD_0 : std_logic_vector(0 to 3) := X"9";
constant PAD_1 : std_logic_vector(0 to 3) := X"C";
constant SCP_0 : std_logic_vector(0 to 3) := X"5";
constant SCP_1 : std_logic_vector(0 to 3) := X"C";
constant SCP_2 : std_logic_vector(0 to 3) := X"F";
constant SCP_3 : std_logic_vector(0 to 3) := X"B";
constant ECP_0 : std_logic_vector(0 to 3) := X"F";
constant ECP_1 : std_logic_vector(0 to 3) := X"D";
constant ECP_2 : std_logic_vector(0 to 3) := X"F";
constant ECP_3 : std_logic_vector(0 to 3) := X"E";
constant SNF_0 : std_logic_vector(0 to 3) := X"D";
constant SNF_1 : std_logic_vector(0 to 3) := X"C";
constant A_CHAR_0 : std_logic_vector(0 to 3) := X"7";
constant A_CHAR_1 : std_logic_vector(0 to 3) := X"C";
constant VER_DATA_0 : std_logic_vector(0 to 3) := X"E";
constant VER_DATA_1 : std_logic_vector(0 to 3) := X"8";
-- External Register Declarations --
signal RX_PAD_Buffer : std_logic;
signal RX_PE_DATA_Buffer : std_logic_vector(0 to 15);
signal RX_PE_DATA_V_Buffer : std_logic;
signal RX_SCP_Buffer : std_logic;
signal RX_ECP_Buffer : std_logic;
signal RX_SNF_Buffer : std_logic;
signal RX_FC_NB_Buffer : std_logic_vector(0 to 3);
signal RX_SP_Buffer : std_logic;
signal RX_SPA_Buffer : std_logic;
signal RX_NEG_Buffer : std_logic;
signal GOT_A_Buffer : std_logic_vector(0 to 1);
signal GOT_V_Buffer : std_logic;
-- Internal Register Declarations --
signal left_aligned_r : std_logic;
signal previous_cycle_data_r : std_logic_vector(0 to 7);
signal previous_cycle_control_r : std_logic;
signal prev_beat_sp_r : std_logic;
signal prev_beat_spa_r : std_logic;
signal word_aligned_data_r : std_logic_vector(0 to 15);
signal word_aligned_control_bits_r : std_logic_vector(0 to 1);
signal rx_pe_data_r : std_logic_vector(0 to 15);
signal rx_pe_control_r : std_logic_vector(0 to 1);
signal rx_pad_d_r : std_logic_vector(0 to 1);
signal rx_scp_d_r : std_logic_vector(0 to 3);
signal rx_ecp_d_r : std_logic_vector(0 to 3);
signal rx_snf_d_r : std_logic_vector(0 to 1);
signal prev_beat_sp_d_r : std_logic_vector(0 to 3);
signal prev_beat_spa_d_r : std_logic_vector(0 to 3);
signal rx_sp_d_r : std_logic_vector(0 to 3);
signal rx_spa_d_r : std_logic_vector(0 to 3);
signal rx_sp_neg_d_r : std_logic_vector(0 to 1);
signal rx_spa_neg_d_r : std_logic_vector(0 to 1);
signal prev_beat_v_d_r : std_logic_vector(0 to 3);
signal prev_beat_v_r : std_logic;
signal rx_v_d_r : std_logic_vector(0 to 3);
signal got_a_d_r : std_logic_vector(0 to 3);
signal first_v_received_r : std_logic := '0';
-- Wire Declarations --
signal got_v_c : std_logic;
begin
RX_PAD <= RX_PAD_Buffer;
RX_PE_DATA <= RX_PE_DATA_Buffer;
RX_PE_DATA_V <= RX_PE_DATA_V_Buffer;
RX_SCP <= RX_SCP_Buffer;
RX_ECP <= RX_ECP_Buffer;
RX_SNF <= RX_SNF_Buffer;
RX_FC_NB <= RX_FC_NB_Buffer;
RX_SP <= RX_SP_Buffer;
RX_SPA <= RX_SPA_Buffer;
RX_NEG <= RX_NEG_Buffer;
GOT_A <= GOT_A_Buffer;
GOT_V <= GOT_V_Buffer;
-- Main Body of Code --
-- Word Alignment --
-- Determine whether the lane is aligned to the left byte (MS byte) or the
-- right byte (LS byte). This information is used for word alignment. To
-- prevent the word align from changing during normal operation, we do word
-- alignment only when it is allowed by the lane_init_sm.
process (USER_CLK)
variable vec : std_logic_vector(0 to 3);
begin
if (USER_CLK 'event and USER_CLK = '1') then
if ((DO_WORD_ALIGN and not first_v_received_r) = '1') then
vec := RX_CHAR_IS_COMMA & RX_CHAR_IS_K;
case vec is
when "1010" => left_aligned_r <= '1' after DLY;
when "0101" => left_aligned_r <= '0' after DLY;
when others => left_aligned_r <= left_aligned_r after DLY;
end case;
end if;
end if;
end process;
-- Store the LS byte from the previous cycle. If the lane is aligned on
-- the LS byte, we use it as the MS byte on the current cycle.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
previous_cycle_data_r(0) <= RX_DATA(7) after DLY;
previous_cycle_data_r(1) <= RX_DATA(6) after DLY;
previous_cycle_data_r(2) <= RX_DATA(5) after DLY;
previous_cycle_data_r(3) <= RX_DATA(4) after DLY;
previous_cycle_data_r(4) <= RX_DATA(3) after DLY;
previous_cycle_data_r(5) <= RX_DATA(2) after DLY;
previous_cycle_data_r(6) <= RX_DATA(1) after DLY;
previous_cycle_data_r(7) <= RX_DATA(0) after DLY;
end if;
end process;
-- Store the control bit from the previous cycle LS byte. It becomes the
-- control bit for the MS byte on this cycle if the lane is aligned to the
-- LS byte.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
previous_cycle_control_r <= RX_CHAR_IS_K(0) after DLY;
end if;
end process;
-- Select the word-aligned MS byte. Use the current MS byte if the data is
-- left-aligned, otherwise use the LS byte from the previous cycle.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_data_r(0) <= RX_DATA(15) after DLY;
word_aligned_data_r(1) <= RX_DATA(14) after DLY;
word_aligned_data_r(2) <= RX_DATA(13) after DLY;
word_aligned_data_r(3) <= RX_DATA(12) after DLY;
word_aligned_data_r(4) <= RX_DATA(11) after DLY;
word_aligned_data_r(5) <= RX_DATA(10) after DLY;
word_aligned_data_r(6) <= RX_DATA(9) after DLY;
word_aligned_data_r(7) <= RX_DATA(8) after DLY;
else
word_aligned_data_r(0 to 7) <= previous_cycle_data_r after DLY;
end if;
end if;
end process;
-- Select the word-aligned LS byte. Use the current LSByte if the data is
-- right-aligned, otherwise use the current MS byte.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_data_r(8) <= RX_DATA(7) after DLY;
word_aligned_data_r(9) <= RX_DATA(6) after DLY;
word_aligned_data_r(10) <= RX_DATA(5) after DLY;
word_aligned_data_r(11) <= RX_DATA(4) after DLY;
word_aligned_data_r(12) <= RX_DATA(3) after DLY;
word_aligned_data_r(13) <= RX_DATA(2) after DLY;
word_aligned_data_r(14) <= RX_DATA(1) after DLY;
word_aligned_data_r(15) <= RX_DATA(0) after DLY;
else
word_aligned_data_r(8) <= RX_DATA(15) after DLY;
word_aligned_data_r(9) <= RX_DATA(14) after DLY;
word_aligned_data_r(10) <= RX_DATA(13) after DLY;
word_aligned_data_r(11) <= RX_DATA(12) after DLY;
word_aligned_data_r(12) <= RX_DATA(11) after DLY;
word_aligned_data_r(13) <= RX_DATA(10) after DLY;
word_aligned_data_r(14) <= RX_DATA(9) after DLY;
word_aligned_data_r(15) <= RX_DATA(8) after DLY;
end if;
end if;
end process;
-- Select the word-aligned MS byte control bit. Use the current MSByte's
-- control bit if the data is left-aligned, otherwise use the LS byte's
-- control bit from the previous cycle.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_control_bits_r(0) <= RX_CHAR_IS_K(1) after DLY;
else
word_aligned_control_bits_r(0) <= previous_cycle_control_r after DLY;
end if;
end if;
end process;
-- Select the word-aligned LS byte control bit. Use the current LSByte's control
-- bit if the data is left-aligned, otherwise use the current MS byte's control bit.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (left_aligned_r = '1') then
word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(0) after DLY;
else
word_aligned_control_bits_r(1) <= RX_CHAR_IS_K(1) after DLY;
end if;
end if;
end process;
-- Pipeline the word-aligned data for 1 cycle to match the Decodes.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_pe_data_r <= word_aligned_data_r after DLY;
end if;
end process;
-- Register the pipelined word-aligned data for the RX_LL interface.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_PE_DATA_Buffer <= rx_pe_data_r after DLY;
end if;
end process;
-- Decode Control Symbols --
-- All decodes are pipelined to keep the number of logic levels to a minimum.
-- Delay the control bits: they are most often used in the second stage of
-- the decoding process.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_pe_control_r <= word_aligned_control_bits_r after DLY;
end if;
end process;
-- Decode PAD
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_pad_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = PAD_0) after DLY;
rx_pad_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = PAD_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_PAD_Buffer <= std_bool((rx_pad_d_r = "11") and (rx_pe_control_r = "01")) after DLY;
end if;
end process;
-- Decode RX_PE_DATA_V
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_PE_DATA_V_Buffer <= not rx_pe_control_r(0) after DLY;
end if;
end process;
-- Decode RX_SCP
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_scp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SCP_0) after DLY;
rx_scp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SCP_1) after DLY;
rx_scp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SCP_2) after DLY;
rx_scp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SCP_3) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SCP_Buffer <= rx_pe_control_r(0) and
rx_pe_control_r(1) and
rx_scp_d_r(0) and
rx_scp_d_r(1) and
rx_scp_d_r(2) and
rx_scp_d_r(3) after DLY;
end if;
end process;
-- Decode RX_ECP
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_ecp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = ECP_0) after DLY;
rx_ecp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = ECP_1) after DLY;
rx_ecp_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = ECP_2) after DLY;
rx_ecp_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = ECP_3) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_ECP_Buffer <= rx_pe_control_r(0) and
rx_pe_control_r(1) and
rx_ecp_d_r(0) and
rx_ecp_d_r(1) and
rx_ecp_d_r(2) and
rx_ecp_d_r(3) after DLY;
end if;
end process;
-- Decode RX_SNF
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_snf_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SNF_0) after DLY;
rx_snf_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SNF_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SNF_Buffer <= rx_pe_control_r(0) and
rx_snf_d_r(0) and
rx_snf_d_r(1) after DLY;
end if;
end process;
-- Extract the Flow Control Size code and register it for the RX_LL interface.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_FC_NB_Buffer <= rx_pe_data_r(8 to 11) after DLY;
end if;
end process;
-- For an SP sequence to be valid, there must be 2 bytes of SP Data preceded
-- by a Comma and an SP Data byte in the MS byte and LS byte positions
-- respectively. This flop stores the decode of the Comma and SP Data byte
-- combination from the previous cycle. Data can be positive or negative.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_sp_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
prev_beat_sp_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
prev_beat_sp_d_r(2) <= std_bool((word_aligned_data_r(8 to 11) = SP_DATA_0) or
(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0)) after DLY;
prev_beat_sp_d_r(3) <= std_bool((word_aligned_data_r(12 to 15) = SP_DATA_1) or
(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1)) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_sp_r <= std_bool((rx_pe_control_r = "10") and
(prev_beat_sp_d_r = "1111")) after DLY;
end if;
end process;
-- This flow stores the decode of a Comma and SPA Data byte combination from the
-- previous cycle. It is used along with decodes for SPA data in the current
-- cycle to determine whether an SPA sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_spa_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
prev_beat_spa_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
prev_beat_spa_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SPA_DATA_0) after DLY;
prev_beat_spa_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SPA_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_spa_r <= std_bool((rx_pe_control_r = "10") and
(prev_beat_spa_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate the SP sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_sp_d_r(0) <= std_bool((word_aligned_data_r(0 to 3) = SP_DATA_0) or
(word_aligned_data_r(0 to 3) = SP_NEG_DATA_0)) after DLY;
rx_sp_d_r(1) <= std_bool((word_aligned_data_r(4 to 7) = SP_DATA_1) or
(word_aligned_data_r(4 to 7) = SP_NEG_DATA_1)) after DLY;
rx_sp_d_r(2) <= std_bool((word_aligned_data_r(8 to 11) = SP_DATA_0) or
(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0)) after DLY;
rx_sp_d_r(3) <= std_bool((word_aligned_data_r(12 to 15) = SP_DATA_1) or
(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1)) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SP_Buffer <= prev_beat_sp_r and
std_bool((rx_pe_control_r = "00") and
(rx_sp_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate the SPA sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_spa_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = SPA_DATA_0) after DLY;
rx_spa_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = SPA_DATA_1) after DLY;
rx_spa_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = SPA_DATA_0) after DLY;
rx_spa_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = SPA_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_SPA_Buffer <= prev_beat_spa_r and
std_bool((rx_pe_control_r = "00") and
(rx_spa_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate reversed data received. We look only at the word-aligned LS byte
-- which, during an /SP/ or /SPA/ sequence, will always contain a data byte.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_sp_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SP_NEG_DATA_0) after DLY;
rx_sp_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SP_NEG_DATA_1) after DLY;
rx_spa_neg_d_r(0) <= std_bool(word_aligned_data_r(8 to 11) = SPA_NEG_DATA_0) after DLY;
rx_spa_neg_d_r(1) <= std_bool(word_aligned_data_r(12 to 15) = SPA_NEG_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RX_NEG_Buffer <= not rx_pe_control_r(1) and
std_bool((rx_sp_neg_d_r = "11") or
(rx_spa_neg_d_r = "11")) after DLY;
end if;
end process;
-- GOT_A is decoded from the non_word-aligned input.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
got_a_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = A_CHAR_0) after DLY;
got_a_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = A_CHAR_1) after DLY;
got_a_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = A_CHAR_0) after DLY;
got_a_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = A_CHAR_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
GOT_A_Buffer(0) <= rx_pe_control_r(0) and std_bool(got_a_d_r(0 to 1) = "11") after DLY;
GOT_A_Buffer(1) <= rx_pe_control_r(1) and std_bool(got_a_d_r(2 to 3) = "11") after DLY;
end if;
end process;
-- Verification symbol decode --
-- This flow stores the decode of a Comma and SPA Data byte combination from the
-- previous cycle. It is used along with decodes for SPA data in the current
-- cycle to determine whether an SPA sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_v_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = K_CHAR_0) after DLY;
prev_beat_v_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = K_CHAR_1) after DLY;
prev_beat_v_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = VER_DATA_0) after DLY;
prev_beat_v_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = VER_DATA_1) after DLY;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_beat_v_r <= std_bool((rx_pe_control_r = "10") and
(prev_beat_v_d_r = "1111")) after DLY;
end if;
end process;
-- Indicate the SP sequence was received.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
rx_v_d_r(0) <= std_bool(word_aligned_data_r(0 to 3) = VER_DATA_0) after DLY;
rx_v_d_r(1) <= std_bool(word_aligned_data_r(4 to 7) = VER_DATA_1) after DLY;
rx_v_d_r(2) <= std_bool(word_aligned_data_r(8 to 11) = VER_DATA_0) after DLY;
rx_v_d_r(3) <= std_bool(word_aligned_data_r(12 to 15) = VER_DATA_1) after DLY;
end if;
end process;
got_v_c <= prev_beat_v_r and
std_bool((rx_pe_control_r = "00") and
(rx_v_d_r = "1111"));
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
GOT_V_Buffer <= got_v_c after DLY;
end if;
end process;
-- Remember that the first V sequence has been detected.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (RESET = '1') then
first_v_received_r <= '0' after DLY;
else
if (got_v_c = '1') then
first_v_received_r <= '1' after DLY;
end if;
end if;
end if;
end process;
end RTL;
| bsd-2-clause | 180cdba28ab3829e9ec572ed70f9a90e | 0.526682 | 3.326389 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_if_statement_GNYT6HZJI5.vhd | 9 | 1,396 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNYT6HZJI5 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a>b";
number_inputs : integer := 2;
width : natural := 8);
port(
true : out std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNYT6HZJI5 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(7 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a>b) ;
true <= result;
end architecture;
| mit | 6b57bb8384da833160f4fc731777ca6e | 0.62106 | 3.231481 | false | false | false | false |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_05_a/hdl/vhdl/radio_controller.vhd | 2 | 38,342 | -- Copyright (c) 2006 Rice University
-- All Rights Reserved
-- This code is covered by the Rice-WARP license
-- See http://warp.rice.edu/license/ for details
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library opb_ipif_v3_01_c;
use opb_ipif_v3_01_c.all;
library radio_controller_v1_05_a;
use radio_controller_v1_05_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"0000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
spi_clk : out std_logic;
data_out : out std_logic;
radio1_cs : out std_logic;
radio2_cs : out std_logic;
radio3_cs : out std_logic;
radio4_cs : out std_logic;
dac1_cs : out std_logic;
dac2_cs : out std_logic;
dac3_cs : out std_logic;
dac4_cs : out std_logic;
radio1_SHDN : out std_logic;
radio1_TxEn : out std_logic;
radio1_RxEn : out std_logic;
radio1_RxHP : out std_logic;
radio1_LD : in std_logic;
radio1_24PA : out std_logic;
radio1_5PA : out std_logic;
radio1_ANTSW : out std_logic_vector(0 to 1);
radio1_LED : out std_logic_vector(0 to 2);
radio1_ADC_RX_DCS : out std_logic;
radio1_ADC_RX_DFS : out std_logic;
radio1_ADC_RX_OTRA : in std_logic;
radio1_ADC_RX_OTRB : in std_logic;
radio1_ADC_RX_PWDNA : out std_logic;
radio1_ADC_RX_PWDNB : out std_logic;
radio1_DIPSW : in std_logic_vector(0 to 3);
radio1_RSSI_ADC_CLAMP : out std_logic;
radio1_RSSI_ADC_HIZ : out std_logic;
radio1_RSSI_ADC_OTR : in std_logic;
radio1_RSSI_ADC_SLEEP : out std_logic;
radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio1_TX_DAC_PLL_LOCK : in std_logic;
radio1_TX_DAC_RESET : out std_logic;
radio1_RxHP_external : in std_logic;
radio1_TxGain : out std_logic_vector(0 to 5);
radio1_TxStart : out std_logic;
radio2_SHDN : out std_logic;
radio2_TxEn : out std_logic;
radio2_RxEn : out std_logic;
radio2_RxHP : out std_logic;
radio2_LD : in std_logic;
radio2_24PA : out std_logic;
radio2_5PA : out std_logic;
radio2_ANTSW : out std_logic_vector(0 to 1);
radio2_LED : out std_logic_vector(0 to 2);
radio2_ADC_RX_DCS : out std_logic;
radio2_ADC_RX_DFS : out std_logic;
radio2_ADC_RX_OTRA : in std_logic;
radio2_ADC_RX_OTRB : in std_logic;
radio2_ADC_RX_PWDNA : out std_logic;
radio2_ADC_RX_PWDNB : out std_logic;
radio2_DIPSW : in std_logic_vector(0 to 3);
radio2_RSSI_ADC_CLAMP : out std_logic;
radio2_RSSI_ADC_HIZ : out std_logic;
radio2_RSSI_ADC_OTR : in std_logic;
radio2_RSSI_ADC_SLEEP : out std_logic;
radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio2_TX_DAC_PLL_LOCK : in std_logic;
radio2_TX_DAC_RESET : out std_logic;
radio2_RxHP_external : in std_logic;
radio2_TxGain : out std_logic_vector(0 to 5);
radio2_TxStart : out std_logic;
radio3_SHDN : out std_logic;
radio3_TxEn : out std_logic;
radio3_RxEn : out std_logic;
radio3_RxHP : out std_logic;
radio3_LD : in std_logic;
radio3_24PA : out std_logic;
radio3_5PA : out std_logic;
radio3_ANTSW : out std_logic_vector(0 to 1);
radio3_LED : out std_logic_vector(0 to 2);
radio3_ADC_RX_DCS : out std_logic;
radio3_ADC_RX_DFS : out std_logic;
radio3_ADC_RX_OTRA : in std_logic;
radio3_ADC_RX_OTRB : in std_logic;
radio3_ADC_RX_PWDNA : out std_logic;
radio3_ADC_RX_PWDNB : out std_logic;
radio3_DIPSW : in std_logic_vector(0 to 3);
radio3_RSSI_ADC_CLAMP : out std_logic;
radio3_RSSI_ADC_HIZ : out std_logic;
radio3_RSSI_ADC_OTR : in std_logic;
radio3_RSSI_ADC_SLEEP : out std_logic;
radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio3_TX_DAC_PLL_LOCK : in std_logic;
radio3_TX_DAC_RESET : out std_logic;
radio3_RxHP_external : in std_logic;
radio3_TxGain : out std_logic_vector(0 to 5);
radio3_TxStart : out std_logic;
radio4_SHDN : out std_logic;
radio4_TxEn : out std_logic;
radio4_RxEn : out std_logic;
radio4_RxHP : out std_logic;
radio4_LD : in std_logic;
radio4_24PA : out std_logic;
radio4_5PA : out std_logic;
radio4_ANTSW : out std_logic_vector(0 to 1);
radio4_LED : out std_logic_vector(0 to 2);
radio4_ADC_RX_DCS : out std_logic;
radio4_ADC_RX_DFS : out std_logic;
radio4_ADC_RX_OTRA : in std_logic;
radio4_ADC_RX_OTRB : in std_logic;
radio4_ADC_RX_PWDNA : out std_logic;
radio4_ADC_RX_PWDNB : out std_logic;
radio4_DIPSW : in std_logic_vector(0 to 3);
radio4_RSSI_ADC_CLAMP : out std_logic;
radio4_RSSI_ADC_HIZ : out std_logic;
radio4_RSSI_ADC_OTR : in std_logic;
radio4_RSSI_ADC_SLEEP : out std_logic;
radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio4_TX_DAC_PLL_LOCK : in std_logic;
radio4_TX_DAC_RESET : out std_logic;
radio4_RxHP_external : in std_logic;
radio4_TxGain : out std_logic_vector(0 to 5);
radio4_TxStart : out std_logic;
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Constant: array of address range identifiers
------------------------------------------
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00 -- user logic S/W register address space
);
------------------------------------------
-- Constant: array of address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
);
------------------------------------------
-- Constant: array of data widths for each target address range
------------------------------------------
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic data width
);
------------------------------------------
-- Constant: array of desired number of chip enables for each address range
------------------------------------------
-- constant USER_NUM_CE : integer := 8;
constant USER_NUM_CE : integer := 16;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
);
------------------------------------------
-- Constant: array of unique properties for each address range
------------------------------------------
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic slave space dependent properties (none defined)
);
------------------------------------------
-- Constant: pipeline mode
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
-- Note:
-- only mode 4, 5, 7 are supported for this release
------------------------------------------
constant PIPELINE_MODEL : integer := 5;
------------------------------------------
-- Constant: user core ID code
------------------------------------------
constant DEV_BLK_ID : integer := 0;
------------------------------------------
-- Constant: enable MIR/Reset register
------------------------------------------
constant DEV_MIR_ENABLE : integer := 0;
------------------------------------------
-- Constant: array of IP interrupt mode
-- 1 = Active-high interrupt condition
-- 2 = Active-low interrupt condition
-- 3 = Active-high pulse interrupt event
-- 4 = Active-low pulse interrupt event
-- 5 = Positive-edge interrupt event
-- 6 = Negative-edge interrupt event
------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
------------------------------------------
-- Constant: enable device burst
------------------------------------------
constant DEV_BURST_ENABLE : integer := 0;
------------------------------------------
-- Constant: include address counter for burst transfers
------------------------------------------
constant INCLUDE_ADDR_CNTR : integer := 0;
------------------------------------------
-- Constant: include write buffer that decouples OPB and IPIC write transactions
------------------------------------------
constant INCLUDE_WR_BUF : integer := 0;
------------------------------------------
-- Constant: index for CS/CE
------------------------------------------
constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 16
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
spi_clk : out std_logic;
data_out : out std_logic;
Radio1_cs : out std_logic;
Radio2_cs : out std_logic;
Radio3_cs : out std_logic;
Radio4_cs : out std_logic;
Dac1_cs : out std_logic;
Dac2_cs : out std_logic;
Dac3_cs : out std_logic;
Dac4_cs : out std_logic;
Radio1_SHDN : out std_logic;
Radio1_TxEn : out std_logic;
Radio1_RxEn : out std_logic;
Radio1_RxHP : out std_logic;
Radio1_LD : in std_logic;
Radio1_24PA : out std_logic;
Radio1_5PA : out std_logic;
Radio1_ANTSW : out std_logic_vector(0 to 1);
Radio1_LED : out std_logic_vector(0 to 2);
Radio1_ADC_RX_DCS : out std_logic;
Radio1_ADC_RX_DFS : out std_logic;
Radio1_ADC_RX_OTRA : in std_logic;
Radio1_ADC_RX_OTRB : in std_logic;
Radio1_ADC_RX_PWDNA : out std_logic;
Radio1_ADC_RX_PWDNB : out std_logic;
Radio1_DIPSW : in std_logic_vector(0 to 3);
Radio1_RSSI_ADC_CLAMP : out std_logic;
Radio1_RSSI_ADC_HIZ : out std_logic;
Radio1_RSSI_ADC_OTR : in std_logic;
Radio1_RSSI_ADC_SLEEP : out std_logic;
Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio1_TX_DAC_PLL_LOCK : in std_logic;
Radio1_TX_DAC_RESET : out std_logic;
Radio1_RxHP_external : in std_logic;
Radio1_TxGain : out std_logic_vector(0 to 5);
Radio1_TxStart : out std_logic;
Radio2_SHDN : out std_logic;
Radio2_TxEn : out std_logic;
Radio2_RxEn : out std_logic;
Radio2_RxHP : out std_logic;
Radio2_LD : in std_logic;
Radio2_24PA : out std_logic;
Radio2_5PA : out std_logic;
Radio2_ANTSW : out std_logic_vector(0 to 1);
Radio2_LED : out std_logic_vector(0 to 2);
Radio2_ADC_RX_DCS : out std_logic;
Radio2_ADC_RX_DFS : out std_logic;
Radio2_ADC_RX_OTRA : in std_logic;
Radio2_ADC_RX_OTRB : in std_logic;
Radio2_ADC_RX_PWDNA : out std_logic;
Radio2_ADC_RX_PWDNB : out std_logic;
Radio2_DIPSW : in std_logic_vector(0 to 3);
Radio2_RSSI_ADC_CLAMP : out std_logic;
Radio2_RSSI_ADC_HIZ : out std_logic;
Radio2_RSSI_ADC_OTR : in std_logic;
Radio2_RSSI_ADC_SLEEP : out std_logic;
Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio2_TX_DAC_PLL_LOCK : in std_logic;
Radio2_TX_DAC_RESET : out std_logic;
Radio2_RxHP_external : in std_logic;
Radio2_TxGain : out std_logic_vector(0 to 5);
Radio2_TxStart : out std_logic;
Radio3_SHDN : out std_logic;
Radio3_TxEn : out std_logic;
Radio3_RxEn : out std_logic;
Radio3_RxHP : out std_logic;
Radio3_LD : in std_logic;
Radio3_24PA : out std_logic;
Radio3_5PA : out std_logic;
Radio3_ANTSW : out std_logic_vector(0 to 1);
Radio3_LED : out std_logic_vector(0 to 2);
Radio3_ADC_RX_DCS : out std_logic;
Radio3_ADC_RX_DFS : out std_logic;
Radio3_ADC_RX_OTRA : in std_logic;
Radio3_ADC_RX_OTRB : in std_logic;
Radio3_ADC_RX_PWDNA : out std_logic;
Radio3_ADC_RX_PWDNB : out std_logic;
Radio3_DIPSW : in std_logic_vector(0 to 3);
Radio3_RSSI_ADC_CLAMP : out std_logic;
Radio3_RSSI_ADC_HIZ : out std_logic;
Radio3_RSSI_ADC_OTR : in std_logic;
Radio3_RSSI_ADC_SLEEP : out std_logic;
Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio3_TX_DAC_PLL_LOCK : in std_logic;
Radio3_TX_DAC_RESET : out std_logic;
Radio3_RxHP_external : in std_logic;
Radio3_TxGain : out std_logic_vector(0 to 5);
Radio3_TxStart : out std_logic;
Radio4_SHDN : out std_logic;
Radio4_TxEn : out std_logic;
Radio4_RxEn : out std_logic;
Radio4_RxHP : out std_logic;
Radio4_LD : in std_logic;
Radio4_24PA : out std_logic;
Radio4_5PA : out std_logic;
Radio4_ANTSW : out std_logic_vector(0 to 1);
Radio4_LED : out std_logic_vector(0 to 2);
Radio4_ADC_RX_DCS : out std_logic;
Radio4_ADC_RX_DFS : out std_logic;
Radio4_ADC_RX_OTRA : in std_logic;
Radio4_ADC_RX_OTRB : in std_logic;
Radio4_ADC_RX_PWDNA : out std_logic;
Radio4_ADC_RX_PWDNB : out std_logic;
Radio4_DIPSW : in std_logic_vector(0 to 3);
Radio4_RSSI_ADC_CLAMP : out std_logic;
Radio4_RSSI_ADC_HIZ : out std_logic;
Radio4_RSSI_ADC_OTR : in std_logic;
Radio4_RSSI_ADC_SLEEP : out std_logic;
Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio4_TX_DAC_PLL_LOCK : in std_logic;
Radio4_TX_DAC_RESET : out std_logic;
Radio4_RxHP_external : in std_logic;
Radio4_TxGain : out std_logic_vector(0 to 5);
Radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sl_DBus,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_retry => Sl_retry,
Sln_toutSup => Sl_toutSup,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_AddrAck => '0',
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => iBus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => iBus2IP_Reset
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
spi_clk => spi_clk,
data_out => data_out,
Radio1_cs => radio1_cs,
Radio2_cs => radio2_cs,
Radio3_cs => radio3_cs,
Radio4_cs => radio4_cs,
Dac1_cs => dac1_cs,
Dac2_cs => dac2_cs,
Dac3_cs => dac3_cs,
Dac4_cs => dac4_cs,
Radio1_SHDN => radio1_SHDN,
Radio1_TxEn => radio1_TxEn,
Radio1_RxEn => radio1_RxEn,
Radio1_RxHP => radio1_RxHP,
Radio1_LD => radio1_LD,
Radio1_24PA => radio1_24PA,
Radio1_5PA => radio1_5PA,
Radio1_ANTSW => radio1_ANTSW,
Radio1_LED => radio1_LED,
Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS,
Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS,
Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA,
Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB,
Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA,
Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB,
Radio1_DIPSW => radio1_DIPSW,
Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP,
Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ,
Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR,
Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP,
Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D,
Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK,
Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET,
Radio1_RxHP_external => radio1_RxHP_external,
Radio1_TxGain => radio1_TxGain,
Radio1_TxStart => radio1_TxStart,
Radio2_SHDN => radio2_SHDN,
Radio2_TxEn => radio2_TxEn,
Radio2_RxEn => radio2_RxEn,
Radio2_RxHP => radio2_RxHP,
Radio2_LD => radio2_LD,
Radio2_24PA => radio2_24PA,
Radio2_5PA => radio2_5PA,
Radio2_ANTSW => radio2_ANTSW,
Radio2_LED => radio2_LED,
Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS,
Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS,
Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA,
Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB,
Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA,
Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB,
Radio2_DIPSW => radio2_DIPSW,
Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP,
Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ,
Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR,
Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP,
Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D,
Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK,
Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET,
Radio2_RxHP_external => radio2_RxHP_external,
Radio2_TxGain => radio2_TxGain,
Radio2_TxStart => radio2_TxStart,
Radio3_SHDN => radio3_SHDN,
Radio3_TxEn => radio3_TxEn,
Radio3_RxEn => radio3_RxEn,
Radio3_RxHP => radio3_RxHP,
Radio3_LD => radio3_LD,
Radio3_24PA => radio3_24PA,
Radio3_5PA => radio3_5PA,
Radio3_ANTSW => radio3_ANTSW,
Radio3_LED => radio3_LED,
Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS,
Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS,
Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA,
Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB,
Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA,
Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB,
Radio3_DIPSW => radio3_DIPSW,
Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP,
Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ,
Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR,
Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP,
Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D,
Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK,
Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET,
Radio3_RxHP_external => radio3_RxHP_external,
Radio3_TxGain => radio3_TxGain,
Radio3_TxStart => radio3_TxStart,
Radio4_SHDN => radio4_SHDN,
Radio4_TxEn => radio4_TxEn,
Radio4_RxEn => radio4_RxEn,
Radio4_RxHP => radio4_RxHP,
Radio4_LD => radio4_LD,
Radio4_24PA => radio4_24PA,
Radio4_5PA => radio4_5PA,
Radio4_ANTSW => radio4_ANTSW,
Radio4_LED => radio4_LED,
Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS,
Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS,
Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA,
Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB,
Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA,
Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB,
Radio4_DIPSW => radio4_DIPSW,
Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP,
Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ,
Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR,
Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP,
Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D,
Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK,
Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET,
Radio4_RxHP_external => radio4_RxHP_external,
Radio4_TxGain => radio4_TxGain,
Radio4_TxStart => radio4_TxStart,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-2-clause | 8b922aacf05c24986ed21edfcca6b142 | 0.433285 | 3.945868 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/idle_and_ver_gen.vhd | 4 | 14,455 | --
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/21 23:26:37 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: idle_and_ver_gen_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.5 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- IDLE_AND_VER_GEN
--
-- Author: N. Gulstone, B.Woodard
-- Xilinx - Embedded Networking System Engineering Group
--
-- Description: the IDLE_AND_VER_GEN module generates idle sequences and
-- verification sequences for the Aurora channel. The idle sequences
-- are constantly generated by a pseudorandom generator and a counter
-- to make the sequence Aurora compliant. If the gen_ver signal is high,
-- verification symbols are added to the mix at appropriate intervals
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use WORK.AURORA.all;
-- synthesis translate_off
library UNISIM;
use UNISIM.all;
-- synthesis translate_on
entity IDLE_AND_VER_GEN is
port (
-- Channel Init SM Interface
GEN_VER : in std_logic;
DID_VER : out std_logic;
-- Aurora Lane Interface
GEN_A : out std_logic;
GEN_K : out std_logic_vector(0 to 1);
GEN_R : out std_logic_vector(0 to 1);
GEN_V : out std_logic_vector(0 to 1);
-- System Interface
RESET : in std_logic;
USER_CLK : in std_logic
);
end IDLE_AND_VER_GEN;
architecture RTL of IDLE_AND_VER_GEN is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal DID_VER_Buffer : std_logic;
signal GEN_A_Buffer : std_logic;
signal GEN_K_Buffer : std_logic_vector(0 to 1);
signal GEN_R_Buffer : std_logic_vector(0 to 1);
signal GEN_V_Buffer : std_logic_vector(0 to 1);
-- Internal Register Declarations --
signal lfsr_shift_register_r : std_logic_vector(0 to 3) := "0000";
signal downcounter_r : std_logic_vector(0 to 3) := "0001";
signal gen_ver_word_2_r : std_logic;
signal prev_cycle_gen_ver_r : std_logic;
-- Wire Declarations --
signal lfsr_last_flop_r : std_logic;
signal lfsr_taps_c : std_logic;
signal lfsr_taps_r : std_logic;
signal lfsr_r : std_logic_vector(0 to 2);
signal gen_k_r : std_logic_vector(0 to 1);
signal gen_r_r : std_logic_vector(0 to 1);
signal ver_counter_r : std_logic_vector(0 to 1);
signal gen_ver_word_1_r : std_logic;
signal gen_k_flop_c : std_logic_vector(0 to 1);
signal gen_r_flop_c : std_logic_vector(0 to 1);
signal gen_v_flop_c : std_logic_vector(0 to 1);
signal gen_a_flop_c : std_logic;
signal downcounter_done_c : std_logic;
signal gen_ver_edge_c : std_logic;
signal recycle_gen_ver_c : std_logic;
signal insert_ver_c : std_logic;
signal tied_to_gnd : std_logic;
signal tied_to_vcc : std_logic;
-- Component Declaration --
component FD
generic (INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic
);
end component;
component FDR
generic (INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic
);
end component;
component SRL16
generic (INIT : bit_vector := X"0000");
port (
Q : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
CLK : in std_ulogic;
D : in std_ulogic
);
end component;
begin
DID_VER <= DID_VER_Buffer;
GEN_A <= GEN_A_Buffer;
GEN_K <= GEN_K_Buffer;
GEN_R <= GEN_R_Buffer;
GEN_V <= GEN_V_Buffer;
tied_to_gnd <= '0';
tied_to_vcc <= '1';
-- Main Body of Code --
-- Random Pattern Generation --
-- Use an LFSR to create pseudorandom patterns. This is a 6 bit LFSR based
-- on XAPP210. Taps on bits 5 and 6 are XNORed to make the input of the
-- register. The lfsr must never be initialized to 1. The entire structure
-- should cost a maximum of 2 LUTS and 2 Flops. The output of the input
-- register and each of the tap registers is passed to the rest of the logic
-- as the LFSR output.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
lfsr_shift_register_r <= lfsr_taps_r & lfsr_shift_register_r(0 to 2) after DLY;
end if;
end process;
lfsr_last_flop_i : FDR
generic map (INIT => '0')
port map (
Q => lfsr_last_flop_r,
C => USER_CLK,
D => lfsr_shift_register_r(3),
R => RESET
);
lfsr_taps_c <= not (lfsr_shift_register_r(3) xor lfsr_last_flop_r);
lfsr_taps_i : FDR
generic map (INIT => '0')
port map (
Q => lfsr_taps_r,
C => USER_CLK,
D => lfsr_taps_c,
R => RESET
);
lfsr_r <= lfsr_taps_r & lfsr_shift_register_r(3) & lfsr_last_flop_r;
-- Use a downcounter to determine when A's should be added to the idle pattern.
-- Load the 3 least significant bits with the output of the lfsr whenever the
-- counter reaches 0.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (RESET = '1') then
downcounter_r <= "0000" after DLY;
else
if (downcounter_done_c = '1') then
downcounter_r <= "1" & lfsr_r after DLY;
else
downcounter_r <= downcounter_r - "0001" after DLY;
end if;
end if;
end if;
end process;
downcounter_done_c <= std_bool(downcounter_r = "0000");
-- The LFSR's pseudoRandom patterns are also used to generate the sequence of
-- K and R characters that make up the rest of the idle sequence. Note that
-- R characters are used whenever a K character is not used.
gen_k_r <= lfsr_r(0 to 1);
gen_r_r <= not lfsr_r(0 to 1);
-- Verification Sequence Generation --
-- Use a counter to generate the verification sequence every 64 bytes
-- (32 clocks), starting from when verification is enabled.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
prev_cycle_gen_ver_r <= GEN_VER after DLY;
end if;
end process;
-- Detect the positive edge of the GEN_VER signal.
gen_ver_edge_c <= GEN_VER and not prev_cycle_gen_ver_r;
-- If GEN_VER is still high after generating a verification sequence,
-- indicate that the gen_ver signal can be generated again.
recycle_gen_ver_c <= gen_ver_word_2_r and GEN_VER;
-- Prime the verification counter SRL16 with a 1. When this 1 reaches the end
-- of the register, it will become the gen_ver_word signal. Prime the counter
-- only if there was a positive edge on GEN_VER to start the sequence, or if
-- the sequence has just ended and another must be generated.
insert_ver_c <= gen_ver_edge_c or recycle_gen_ver_c;
-- Main Body of the verification counter. It is implemented as a shift register
-- made from 2 SRL16s. The register is 31 cycles long, and operates by
-- taking the 1 from the insert ver signal and passing it though its stages.
ver_counter_0_i : SRL16
generic map (INIT => X"0000")
port map (
Q => ver_counter_r(0),
A0 => tied_to_vcc,
A1 => tied_to_vcc,
A2 => tied_to_vcc,
A3 => tied_to_vcc,
CLK => USER_CLK,
D => insert_ver_c
);
ver_counter_1_i : SRL16
generic map (INIT => X"0000")
port map (
Q => ver_counter_r(1),
A0 => tied_to_gnd,
A1 => tied_to_vcc,
A2 => tied_to_vcc,
A3 => tied_to_vcc,
CLK => USER_CLK,
D => ver_counter_r(0)
);
-- Generate the first 2 bytes of the verification sequence when the verification
-- counter reaches '31'.
gen_ver_word_1_r <= ver_counter_r(1);
-- Generate the second 2 bytes of the verification sequence on the cycle after
-- the first verification sequence.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
gen_ver_word_2_r <= gen_ver_word_1_r after DLY;
end if;
end process;
-- Output Signals --
-- Signal that the verification sequence has been generated. Signaling off of
-- the second byte allows the counter to be primed for one count too many, but
-- is neccessary to allow GEN_V to be used as a qualifier for the output. The
-- extra gen_ver_word_1_r and gen_ver_word_2_r assertion is ok, because GEN_VER
-- will be low when they are asserted.
DID_VER_Buffer <= gen_ver_word_2_r;
-- Assert GEN_V in the MSByte of each lane when gen_ver_word_2_r is asserted.
-- Assert GEN_V in the LSByte of each lane if either gen_ver_word signal is
-- asserted. We use a seperate register for each output to provide enough slack
-- to allow the Global logic to communicate with all lanes without causing
-- timing problems.
gen_v_flop_c(0) <= GEN_VER and gen_ver_word_2_r;
gen_v_flop_0_i : FD
generic map (INIT => '0')
port map (
D => gen_v_flop_c(0),
C => USER_CLK,
Q => GEN_V_Buffer(0)
);
gen_v_flop_c(1) <= GEN_VER and (gen_ver_word_1_r or gen_ver_word_2_r);
gen_v_flop_1_i : FD
generic map (INIT => '0')
port map (
D => gen_v_flop_c(1),
C => USER_CLK,
Q => GEN_V_Buffer(1)
);
-- Assert GEN_A in the MSByte of each lane when the GEN_A downcounter reaches 0.
-- Note that the signal has a register for each lane for the same reason as the
-- GEN_V signal. GEN_A is ignored when it collides with other non-idle
-- generation requests at the Aurora Lane, but we qualify the signal with
-- the gen_ver_word_1_r signal so it does not overwrite the K used in the
-- MSByte of the first word of the Verification sequence.
gen_a_flop_c <= downcounter_done_c and not gen_ver_word_1_r;
gen_a_flop_0_i : FD
generic map (INIT => '0')
port map (
D => gen_a_flop_c,
C => USER_CLK,
Q => GEN_A_Buffer
);
-- Assert GEN_K in the MSByte when the lfsr dictates. Turn off the assertion if an
-- A symbol is being generated on the byte. Assert the signal without qualifications
-- if gen_ver_word_1_r is asserted. Assert GEN_K in the LSByte when the lfsr dictates.
-- There are no qualifications because only the GEN_R signal can collide with it, and
-- this is prevented by the way the gen_k_r signal is generated. All other GEN signals
-- will override this signal at the AURORA_LANE.
gen_k_flop_c(0) <= (gen_k_r(0) and not downcounter_done_c) or gen_ver_word_1_r;
gen_k_flop_0_i : FD
generic map (INIT => '0')
port map (
D => gen_k_flop_c(0),
C => USER_CLK,
Q => GEN_K_Buffer(0)
);
gen_k_flop_c(1) <= gen_k_r(1);
gen_k_flop_1_i : FD
generic map (INIT => '0')
port map (
D => gen_k_flop_c(1),
C => USER_CLK,
Q => GEN_K_Buffer(1)
);
-- Assert GEN_R in the MSByte when the lfsr dictates. Turn off the assertion if an
-- A symbol, or the first verification word is being generated. Assert GEN_R in the
-- LSByte when the lfsr dictates, with no qualifications (same reason as the GEN_K LSByte).
gen_r_flop_c(0) <= gen_r_r(0) and not downcounter_done_c and not gen_ver_word_1_r;
gen_r_flop_0_i : FD
generic map (INIT => '0')
port map (
D => gen_r_flop_c(0),
C => USER_CLK,
Q => GEN_R_Buffer(0)
);
gen_r_flop_c(1) <= gen_r_r(1);
gen_r_flop_1_i : FD
generic map (INIT => '0')
port map (
D => gen_r_flop_c(1),
C => USER_CLK,
Q => GEN_R_Buffer(1)
);
end RTL;
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`protect end_protected
| gpl-3.0 | 7a7d8b74038a61631f3aa052834a03a2 | 0.940898 | 1.871404 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_status_flags_ss.vhd | 9 | 17,955 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11552)
`protect data_block
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`protect end_protected
| gpl-3.0 | 164e275a36c7a25c7a503e552f4e0807 | 0.938067 | 1.84324 | false | false | false | false |
JoseHawk/Voltmeter | Voltímetro_02 (Considerando señales por separado)/Voltimetro.vhd | 1 | 4,670 | -- VOLTIMETRO
-- Librerias necesarias
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Definimos la entidad
ENTITY Voltimetro IS
PORT(
-- FPGA
reloj : IN STD_LOGIC; -- Reloj interno de la placa
unidadesDisplay : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); -- Valor de las unidades a mostrar en el display
decimalesDisplay : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); -- Valor de los decimales a mostrar en el display
puntoDisplay : OUT STD_LOGIC; -- Punto que separa la parte entera de la decimal
segundoPunto : OUT STD_LOGIC; -- Lo consideramos para apagarlo
-- Conversor A/D : Los puertos de entrada del conversor son en realidad salidas de la FPGA
-- Las salidas del conversor son entradas a la FPGA
-- FISICO IN_AD : OUT STD_LOGIC_VECTOR; -- Entradas analogicas
A : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); -- Seleccion del canal analogico a convertir
D : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- Salida digital de la senial analogica seleccionada
-- REFPOS : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- Entrada de la tension de referencia positiva
-- REFNEG : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- Entrada de la tension de referencia negativa
-- PWRDN : OUT STD_LOGIC; -- Apaga el convertidor para minimizar el consumo del sistema
MODE : OUT STD_LOGIC; -- Selecciona el MODE_0 o MODE_1
RD : OUT STD_LOGIC; -- Marca el inicio de la conversion
-- WR_RDY : OUT STD_LOGIC; -- Marca la escritura del dato o bien que la conversion ha finalizado
CS : OUT STD_LOGIC; -- Marca el inicio de la conversion
INT : IN STD_LOGIC;
INT_OUT : OUT STD_LOGIC
);
END Voltimetro;
-- Definimos la arquitectura
ARCHITECTURE arquitecturaVoltimetro OF Voltimetro IS
TYPE estado IS (estado1, estado2, estado3); -- Estados posibles
SIGNAL senialMuestreo : estado:= estado1; -- Marca las subidas y bajadas de la senial de muestreo a frecuencia 10^6
SIGNAL voltaje : STD_LOGIC_VECTOR (7 DOWNTO 0); -- Valor del voltaje digitalizado a 8 bits
SIGNAL unidades : INTEGER RANGE 0 TO 9; -- Valor de las unidades obtenido a partir del voltaje
SIGNAL decimales : INTEGER RANGE 0 TO 9; -- Valor de los decimales obtenido a partir del voltaje
-- Instanciamos el codificador de 7 segmentos para la representacion mediante display
COMPONENT codificador7Segmentos
PORT(
entrada : IN INTEGER RANGE 0 TO 9;
salida : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- Vamos a considerar la primera entrada, por tanto, seleccionamos el primer canal
A <= "000";
-- Seleccionamos MODO 0
MODE <= '0';
puntoDisplay <= '0'; -- Lo mantenemos siempre encendido
segundoPunto <= '1'; -- Apagamos el segundo punto del display
-- Obtenemos la frecuencia de muestreo mediante maquina de estados
obtencionFrecuenciaMuestreo : PROCESS (reloj)
VARIABLE pulsos : INTEGER RANGE 0 TO 50 := 0;
BEGIN
IF reloj'EVENT AND reloj = '1' THEN
CASE senialMuestreo IS
WHEN estado1 =>
RD <= '0';
CS <= '0';
IF INT = '0' THEN
senialMuestreo <= estado2;
ELSE
senialMuestreo <= estado1;
END IF;
WHEN estado2 =>
voltaje <= D;
senialMuestreo <= estado3;
WHEN estado3 =>
RD <= '1';
CS <= '1';
IF pulsos < 7 THEN
pulsos := pulsos + 1;
senialMuestreo <= estado3;
ELSE
pulsos := 0;
senialMuestreo <= estado1;
END IF;
END CASE;
END IF;
END PROCESS obtencionFrecuenciaMuestreo;
-- Con este proceso lo que haremos es obtener las unidades y la parte decimal del voltaje
obtencionValoresDisplay : PROCESS (voltaje)
VARIABLE voltajeEntero : INTEGER RANGE 0 TO 300;
BEGIN
voltajeEntero := conv_integer(voltaje); -- Pasamos el voltaje a entero
voltajeEntero := 50*(voltajeEntero)/255;
unidades <= voltajeEntero / 10; -- Obtenemos el valor de las unidades
decimales <= voltajeEntero REM 10; -- Obtenemos el valor de los decimales
END PROCESS obtencionValoresDisplay;
-- Codificamos para mostrar por el display de 7 segmentos las unidades
mostrarUnidadesDisplay : codificador7Segmentos PORT MAP(
entrada => unidades,
salida => unidadesDisplay
);
-- Codificamos para mostrar por el display de 7 segmentos los decimales
mostrarDecimalesDisplay : codificador7Segmentos PORT MAP(
entrada => decimales,
salida => decimalesDisplay
);
INT_OUT <= INT;
END arquitecturaVoltimetro; | gpl-2.0 | ba6247ac034a4519baad1a353db7c594 | 0.666167 | 3.603395 | false | false | false | false |
ymei/TMSPlane | Firmware/src/ten_gig_eth/TE07412C1/pcs_pma/ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2.vhd | 3 | 4,290 | -----------------------------------------------------------------------------
-- Title : FF Synchronizer with Reset
-- Project : 10 Gigabit Ethernet PCS/PMA Core
-- File : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2.vhd
-- Author : Xilinx Inc.
-- Description: This module provides a parameterizable multi stage
-- FF Synchronizer with appropriate synth attributes
-- to mark ASYNC_REG and prevent SRL inference
-- An active reset is included with a paramterized
-- reset value
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2 is
generic
(
C_NUM_SYNC_REGS : integer := 3;
C_RVAL : std_logic := '0'
);
port
(
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic;
data_out : out std_logic := '0'
);
end ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2;
architecture rtl of ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2 is
signal sync1_r : std_logic_vector(C_NUM_SYNC_REGS-1 downto 0) := (others => C_RVAL);
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of sync1_r : signal is "no";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sync1_r : signal is "true";
begin
-----------------------------------------------------------------------------
-- Synchronizer
-----------------------------------------------------------------------------
syncrst_proc : process(clk, rst)
begin
if(rst = '1') then
sync1_r <= (others => C_RVAL);
elsif(clk'event and clk = '1') then
sync1_r <= sync1_r(C_NUM_SYNC_REGS-2 downto 0) & data_in;
end if;
end process syncrst_proc;
outreg_proc : process(clk)
begin
if(clk'event and clk = '1') then
data_out <= sync1_r(C_NUM_SYNC_REGS-1);
end if;
end process outreg_proc;
end rtl;
| bsd-3-clause | c2c50133f47c6d74f7dae9cdc6533f09 | 0.643124 | 4.23913 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/patternClk.vhd | 3 | 5,794 | -- file: patternClk.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____65.000______0.000_______N/A______261.538________N/A
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity patternClk is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end patternClk;
architecture xilinx of patternClk is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "patternClk,clk_wiz_v3_6,{component_name=patternClk,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_ONCHIP,primtype_sel=DCM_CLKGEN,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfx : std_logic;
signal clkfx180_unused : std_logic;
signal clkfxdv_unused : std_logic;
signal clkfbout : std_logic;
-- Dynamic programming unused signals
signal progdone_unused : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(2 downto 1);
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_clkgen_inst: DCM_CLKGEN
generic map
(CLKFXDV_DIVIDE => 2,
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 13,
SPREAD_SPECTRUM => "NONE",
STARTUP_WAIT => FALSE,
CLKIN_PERIOD => 10.0,
CLKFX_MD_MAX => 0.000)
port map
-- Input clock
(CLKIN => clkin1,
-- Output clocks
CLKFX => clkfx,
CLKFX180 => clkfx180_unused,
CLKFXDV => clkfxdv_unused,
-- Ports for dynamic phase shift
PROGCLK => '0',
PROGEN => '0',
PROGDATA => '0',
PROGDONE => progdone_unused,
-- Other control and status signals
FREEZEDCM => '0',
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0');
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkfx;
end xilinx;
| bsd-2-clause | b6ccc633439a2ffe26b3f6d862009902 | 0.603038 | 4.359669 | false | false | false | false |
ymei/TMSPlane | Firmware/src/top_TMS1mmX19_KC705.vhd | 1 | 67,792 | --------------------------------------------------------------------------------
--! @file top.vhd
--! @brief Toplevel module for KC705 eval board.
--! @author Yuan Mei
--!
--! Target Devices: Kintex-7 XC7K325T-FFG900-2
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
LIBRARY work;
USE work.utility.ALL;
ENTITY top IS
GENERIC (
ENABLE_DEBUG : boolean := false;
ENABLE_GIG_ETH : boolean := true;
ENABLE_TEN_GIG_ETH : boolean := false
);
PORT (
SYS_RST : IN std_logic;
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
USER_CLK_P : IN std_logic; --! 156.250 MHz
USER_CLK_N : IN std_logic;
SGMIICLK_Q0_P : IN std_logic; --! 125 MHz, for GTP/GTH/GTX
SGMIICLK_Q0_N : IN std_logic;
SI5324CLK_P : IN std_logic; --! programmable, for GTX ref
SI5324CLK_N : IN std_logic;
--
LED8Bit : OUT std_logic_vector(7 DOWNTO 0);
DIPSw4Bit : IN std_logic_vector(3 DOWNTO 0);
BTN5Bit : IN std_logic_vector(4 DOWNTO 0);
USER_SMA_CLOCK_P : OUT std_logic;
USER_SMA_CLOCK_N : OUT std_logic;
USER_SMA_GPIO_P : IN std_logic;
USER_SMA_GPIO_N : OUT std_logic;
SI5324_RSTn : OUT std_logic;
-- UART via usb
USB_RX : OUT std_logic;
USB_TX : IN std_logic;
-- SFP
SFP_TX_P : OUT std_logic;
SFP_TX_N : OUT std_logic;
SFP_RX_P : IN std_logic;
SFP_RX_N : IN std_logic;
SFP_LOS_LS : IN std_logic;
SFP_TX_DISABLE_N : OUT std_logic;
-- SMA MGT
SMA_MGT_TX_P : OUT std_logic;
SMA_MGT_TX_N : OUT std_logic;
SMA_MGT_RX_P : IN std_logic;
SMA_MGT_RX_N : IN std_logic;
-- Gigbit eth interface (RGMII)
PHY_RESET_N : OUT std_logic;
RGMII_TXD : OUT std_logic_vector(3 DOWNTO 0);
RGMII_TX_CTL : OUT std_logic;
RGMII_TXC : OUT std_logic;
RGMII_RXD : IN std_logic_vector(3 DOWNTO 0);
RGMII_RX_CTL : IN std_logic;
RGMII_RXC : IN std_logic;
MDIO : INOUT std_logic;
MDC : OUT std_logic;
-- SDRAM
DDR3_DQ : INOUT std_logic_vector(63 DOWNTO 0);
DDR3_DQS_P : INOUT std_logic_vector(7 DOWNTO 0);
DDR3_DQS_N : INOUT std_logic_vector(7 DOWNTO 0);
-- Outputs
DDR3_ADDR : OUT std_logic_vector(13 DOWNTO 0);
DDR3_BA : OUT std_logic_vector(2 DOWNTO 0);
DDR3_RAS_N : OUT std_logic;
DDR3_CAS_N : OUT std_logic;
DDR3_WE_N : OUT std_logic;
DDR3_RESET_N : OUT std_logic;
DDR3_CK_P : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CK_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CKE : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CS_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_DM : OUT std_logic_vector(7 DOWNTO 0);
DDR3_ODT : OUT std_logic_vector(0 DOWNTO 0);
--
I2C_SCL : INOUT std_logic;
I2C_SDA : INOUT std_logic;
-- FMC HPC
FMC_HPC_HA_P :INOUT std_logic_vector(23 DOWNTO 0);
FMC_HPC_HA_N :INOUT std_logic_vector(23 DOWNTO 0);
FMC_HPC_LA_P :INOUT std_logic_vector(33 DOWNTO 0);
FMC_HPC_LA_N :INOUT std_logic_vector(33 DOWNTO 0);
-- FMC LPC
FMC_LPC_LA_P :INOUT std_logic_vector(33 DOWNTO 0);
FMC_LPC_LA_N :INOUT std_logic_vector(33 DOWNTO 0)
);
END top;
ARCHITECTURE Behavioral OF top IS
-- Components
COMPONENT global_clock_reset
PORT (
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
FORCE_RST : IN std_logic;
-- output
GLOBAL_RST : OUT std_logic;
SYS_CLK : OUT std_logic;
LOCKED : OUT std_logic;
CLK_OUT1 : OUT std_logic;
CLK_OUT2 : OUT std_logic;
CLK_OUT3 : OUT std_logic;
CLK_OUT4 : OUT std_logic
);
END COMPONENT;
---------------------------------------------< ten_gig_eth
COMPONENT ten_gig_eth
PORT (
REFCLK_P : IN std_logic; -- 156.25MHz for transceiver
REFCLK_N : IN std_logic;
RESET : IN std_logic;
SFP_TX_P : OUT std_logic;
SFP_TX_N : OUT std_logic;
SFP_RX_P : IN std_logic;
SFP_RX_N : IN std_logic;
SFP_LOS : IN std_logic; -- loss of receiver signal
SFP_TX_DISABLE : OUT std_logic;
-- clk156.25 domain, clock generated by the core
CLK156p25 : OUT std_logic;
PCS_PMA_CORE_STATUS : OUT std_logic_vector(7 DOWNTO 0);
TX_STATISTICS_VECTOR : OUT std_logic_vector(25 DOWNTO 0);
TX_STATISTICS_VALID : OUT std_logic;
RX_STATISTICS_VECTOR : OUT std_logic_vector(29 DOWNTO 0);
RX_STATISTICS_VALID : OUT std_logic;
PAUSE_VAL : IN std_logic_vector(15 DOWNTO 0);
PAUSE_REQ : IN std_logic;
TX_IFG_DELAY : IN std_logic_vector(7 DOWNTO 0);
-- emac control interface
S_AXI_ACLK : IN std_logic;
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(10 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WDATA : IN std_logic_vector(31 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(10 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- tx_wr_clk domain
TX_AXIS_FIFO_ARESETN : IN std_logic;
TX_AXIS_FIFO_ACLK : IN std_logic;
TX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
TX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
TX_AXIS_FIFO_TVALID : IN std_logic;
TX_AXIS_FIFO_TLAST : IN std_logic;
TX_AXIS_FIFO_TREADY : OUT std_logic;
-- rx_rd_clk domain
RX_AXIS_FIFO_ARESETN : IN std_logic;
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : OUT std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : OUT std_logic;
RX_AXIS_FIFO_TLAST : OUT std_logic;
RX_AXIS_FIFO_TREADY : IN std_logic
);
END COMPONENT;
COMPONENT ten_gig_eth_packet_gen
PORT (
RESET : IN std_logic;
MEM_CLK : IN std_logic;
MEM_WE : IN std_logic; -- memory write enable
MEM_ADDR : IN std_logic_vector(31 DOWNTO 0);
MEM_D : IN std_logic_vector(31 DOWNTO 0); -- memory data
--
TX_AXIS_ACLK : IN std_logic;
TX_START : IN std_logic;
TX_BYTES : IN std_logic_vector(15 DOWNTO 0); -- number of bytes to send
TX_AXIS_TDATA : OUT std_logic_vector(63 DOWNTO 0);
TX_AXIS_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
TX_AXIS_TVALID : OUT std_logic;
TX_AXIS_TLAST : OUT std_logic;
TX_AXIS_TREADY : IN std_logic
);
END COMPONENT;
COMPONENT ten_gig_eth_rx_parser
PORT (
RESET : IN std_logic;
RX_AXIS_FIFO_ARESETN : OUT std_logic;
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : IN std_logic;
RX_AXIS_FIFO_TLAST : IN std_logic;
RX_AXIS_FIFO_TREADY : OUT std_logic;
-- Constants
SRC_MAC : IN std_logic_vector(47 DOWNTO 0);
SRC_IP : IN std_logic_vector(31 DOWNTO 0);
SRC_PORT : IN std_logic_vector(15 DOWNTO 0);
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q : OUT std_logic_vector(127 DOWNTO 0);
CMD_FIFO_EMPTY : OUT std_logic;
CMD_FIFO_RDREQ : IN std_logic;
CMD_FIFO_RDCLK : IN std_logic
);
END COMPONENT;
---------------------------------------------> ten_gig_eth
---------------------------------------------< gtx / aurora
COMPONENT aurora_64b66b
PORT (
RESET : IN std_logic;
SYS_CLK : IN std_logic;
MGT_REFCLK_P : IN std_logic;
MGT_REFCLK_N : IN std_logic;
-- Data interfaces are synchronous to USER_CLK
USER_CLK : OUT std_logic;
MGT_REFCLK_BUFG_OUT : OUT std_logic;
-- TX AXI4 interface
S_AXI_TX_TDATA : IN std_logic_vector(0 TO 63);
S_AXI_TX_TVALID : IN std_logic;
S_AXI_TX_TREADY : OUT std_logic;
-- RX AXI4 interface
M_AXI_RX_TDATA : OUT std_logic_vector(0 TO 63);
M_AXI_RX_TVALID : OUT std_logic;
-- User flow control (UFC) TX
UFC_TX_REQ : IN std_logic;
S_AXI_UFC_TX_TDATA : IN std_logic_vector(0 TO 63);
UFC_TX_MS : IN std_logic_vector(0 TO 7);
S_AXI_UFC_TX_TVALID : IN std_logic;
S_AXI_UFC_TX_TREADY : OUT std_logic;
-- UFC RX
M_AXI_UFC_RX_TDATA : OUT std_logic_vector(0 TO 63);
M_AXI_UFC_RX_TKEEP : OUT std_logic_vector(0 TO 7);
M_AXI_UFC_RX_TLAST : OUT std_logic;
M_AXI_UFC_RX_TVALID : OUT std_logic;
UFC_IN_PROGRESSn : OUT std_logic;
-- GTX pins
RXP : IN std_logic;
RXN : IN std_logic;
TXP : OUT std_logic;
TXN : OUT std_logic;
-- Status
STATUS : OUT std_logic_vector(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_over_ufc
GENERIC (
FIFO_DATA_WIDTH : positive := 32;
AURORA_DATA_WIDTH : positive := 64
);
PORT (
RESET : IN std_logic;
AURORA_USER_CLK : IN std_logic;
AURORA_TX_REQ : OUT std_logic;
AURORA_TX_MS : OUT std_logic_vector(7 DOWNTO 0);
AURORA_TX_TREADY : IN std_logic;
AURORA_TX_TDATA : OUT std_logic_vector(AURORA_DATA_WIDTH-1 DOWNTO 0);
AURORA_TX_TVALID : OUT std_logic;
AURORA_RX_TDATA : IN std_logic_vector(AURORA_DATA_WIDTH-1 DOWNTO 0);
AURORA_RX_TVALID : IN std_logic;
FIFO_CLK : OUT std_logic;
TX_FIFO_Q : OUT std_logic_vector(FIFO_DATA_WIDTH-1 DOWNTO 0);
TX_FIFO_WREN : OUT std_logic;
TX_FIFO_FULL : IN std_logic;
RX_FIFO_Q : IN std_logic_vector(FIFO_DATA_WIDTH-1 DOWNTO 0);
RX_FIFO_RDEN : OUT std_logic;
RX_FIFO_EMPTY : IN std_logic;
ERR : OUT std_logic
);
END COMPONENT;
---------------------------------------------> gtx / aurora
---------------------------------------------< gig_eth
COMPONENT gig_eth
PORT (
-- asynchronous reset
GLBL_RST : IN std_logic;
-- clocks
GTX_CLK : IN std_logic; -- 125MHz
REF_CLK : IN std_logic; -- 200MHz for IODELAY
-- PHY interface
PHY_RESETN : OUT std_logic;
-- RGMII Interface
RGMII_TXD : OUT std_logic_vector(3 DOWNTO 0);
RGMII_TX_CTL : OUT std_logic;
RGMII_TXC : OUT std_logic;
RGMII_RXD : IN std_logic_vector(3 DOWNTO 0);
RGMII_RX_CTL : IN std_logic;
RGMII_RXC : IN std_logic;
-- MDIO Interface
MDIO : INOUT std_logic;
MDC : OUT std_logic;
-- TCP
MAC_ADDR : IN std_logic_vector(47 DOWNTO 0);
IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0);
IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0);
SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0);
GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0);
TCP_CONNECTION_RESET : IN std_logic;
TX_TDATA : IN std_logic_vector(7 DOWNTO 0);
TX_TVALID : IN std_logic;
TX_TREADY : OUT std_logic;
RX_TDATA : OUT std_logic_vector(7 DOWNTO 0);
RX_TVALID : OUT std_logic;
RX_TREADY : IN std_logic;
-- FIFO
TCP_USE_FIFO : IN std_logic;
TX_FIFO_WRCLK : IN std_logic;
TX_FIFO_Q : IN std_logic_vector(31 DOWNTO 0);
TX_FIFO_WREN : IN std_logic;
TX_FIFO_FULL : OUT std_logic;
RX_FIFO_RDCLK : IN std_logic;
RX_FIFO_Q : OUT std_logic_vector(31 DOWNTO 0);
RX_FIFO_RDEN : IN std_logic;
RX_FIFO_EMPTY : OUT std_logic;
--
TX_FIFO1_WRCLK : IN std_logic;
TX_FIFO1_Q : IN std_logic_vector(31 downto 0);
TX_FIFO1_WREN : IN std_logic;
TX_FIFO1_FULL : OUT std_logic;
RX_FIFO1_RDCLK : IN std_logic;
RX_FIFO1_Q : OUT std_logic_vector(31 downto 0);
RX_FIFO1_RDEN : IN std_logic;
RX_FIFO1_EMPTY : OUT std_logic
);
END COMPONENT;
---------------------------------------------> gig_eth
---------------------------------------------< UART/RS232
COMPONENT control_interface
PORT (
RESET : IN std_logic;
CLK : IN std_logic; -- system clock
-- From FPGA to PC
FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); -- interface fifo data output port
FIFO_EMPTY : OUT std_logic; -- interface fifo "emtpy" signal
FIFO_RDREQ : IN std_logic; -- interface fifo read request
FIFO_RDCLK : IN std_logic; -- interface fifo read clock
-- From PC to FPGA, FWFT
CMD_FIFO_Q : IN std_logic_vector(35 DOWNTO 0); -- interface command fifo data out port
CMD_FIFO_EMPTY : IN std_logic; -- interface command fifo "emtpy" signal
CMD_FIFO_RDREQ : OUT std_logic; -- interface command fifo read request
-- Digital I/O
CONFIG_REG : OUT std_logic_vector(511 DOWNTO 0); -- thirtytwo 16bit registers
PULSE_REG : OUT std_logic_vector(15 DOWNTO 0); -- 16bit pulse register
STATUS_REG : IN std_logic_vector(175 DOWNTO 0); -- eleven 16bit registers
-- Memory interface
MEM_WE : OUT std_logic; -- memory write enable
MEM_ADDR : OUT std_logic_vector(31 DOWNTO 0);
MEM_DIN : OUT std_logic_vector(31 DOWNTO 0); -- memory data input
MEM_DOUT : IN std_logic_vector(31 DOWNTO 0); -- memory data output
-- Data FIFO interface, FWFT
DATA_FIFO_Q : IN std_logic_vector(31 DOWNTO 0);
DATA_FIFO_EMPTY : IN std_logic;
DATA_FIFO_RDREQ : OUT std_logic;
DATA_FIFO_RDCLK : OUT std_logic
);
END COMPONENT;
COMPONENT data_sampler_fifo
GENERIC (
DIN_WIDTH : positive := 512;
DOUT_WIDTH : positive := 32
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
TRIG : IN std_logic;
DIN : IN std_logic_vector(DIN_WIDTH-1 DOWNTO 0);
DIN_VALID : IN std_logic;
DIN_CLK : IN std_logic;
DOUT : OUT std_logic_vector(DOUT_WIDTH-1 DOWNTO 0);
DOUT_EMPTY : OUT std_logic;
DOUT_RDEN : IN std_logic
);
END COMPONENT;
---------------------------------------------> UART/RS232
---------------------------------------------< SDRAM
COMPONENT sdram_ddr3
GENERIC (
INDATA_WIDTH : positive := 256;
OUTDATA_WIDTH : positive := 32;
APP_ADDR_WIDTH : positive := 28;
APP_DATA_WIDTH : positive := 512;
APP_MASK_WIDTH : positive := 64;
APP_ADDR_BURST : positive := 8
);
PORT (
CLK : IN std_logic; -- system clock, must be the same as intended in MIG
REFCLK : IN std_logic; -- 200MHz for iodelay
RESET : IN std_logic;
-- SDRAM_DDR3
-- Inouts
DDR3_DQ : INOUT std_logic_vector(63 DOWNTO 0);
DDR3_DQS_P : INOUT std_logic_vector(7 DOWNTO 0);
DDR3_DQS_N : INOUT std_logic_vector(7 DOWNTO 0);
-- Outputs
DDR3_ADDR : OUT std_logic_vector(13 DOWNTO 0);
DDR3_BA : OUT std_logic_vector(2 DOWNTO 0);
DDR3_RAS_N : OUT std_logic;
DDR3_CAS_N : OUT std_logic;
DDR3_WE_N : OUT std_logic;
DDR3_RESET_N : OUT std_logic;
DDR3_CK_P : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CK_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CKE : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CS_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_DM : OUT std_logic_vector(7 DOWNTO 0);
DDR3_ODT : OUT std_logic_vector(0 DOWNTO 0);
-- Status Outputs
INIT_CALIB_COMPLETE : OUT std_logic;
-- Internal data r/w interface
UI_CLK : OUT std_logic;
--
CTRL_RESET : IN std_logic;
WR_START : IN std_logic;
WR_ADDR_BEGIN : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_STOP : IN std_logic;
WR_WRAP_AROUND : IN std_logic;
POST_TRIGGER : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_BUSY : OUT std_logic;
WR_POINTER : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
TRIGGER_POINTER : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_WRAPPED : OUT std_logic;
RD_START : IN std_logic;
RD_ADDR_BEGIN : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
RD_ADDR_END : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
RD_BUSY : OUT std_logic;
--
DATA_FIFO_RESET : IN std_logic;
INDATA_FIFO_WRCLK : IN std_logic;
INDATA_FIFO_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0);
INDATA_FIFO_FULL : OUT std_logic;
INDATA_FIFO_WREN : IN std_logic;
--
OUTDATA_FIFO_RDCLK : IN std_logic;
OUTDATA_FIFO_Q : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0);
OUTDATA_FIFO_EMPTY : OUT std_logic;
OUTDATA_FIFO_RDEN : IN std_logic;
--
DBG_APP_ADDR : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
DBG_APP_EN : OUT std_logic;
DBG_APP_RDY : OUT std_logic;
DBG_APP_WDF_DATA : OUT std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
DBG_APP_WDF_END : OUT std_logic;
DBG_APP_WDF_WREN : OUT std_logic;
DBG_APP_WDF_RDY : OUT std_logic;
DBG_APP_RD_DATA : OUT std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
DBG_APP_RD_DATA_VALID : OUT std_logic
);
END COMPONENT;
---------------------------------------------> SDRAM
---------------------------------------------< I2C
COMPONENT i2c_write_regmap
GENERIC (
REGMAP_FNAME : string;
INPUT_CLK_FREQENCY : integer := 100_000_000;
-- BUS CLK freqency should be divided by multiples of 4 from input frequency
BUS_CLK_FREQUENCY : integer := 100_000;
START_DELAY_CYCLE : integer := 100_000_000; -- ext_rst to happen # of clk cycles after START
EXT_RST_WIDTH_CYCLE : integer := 1000; -- pulse width of ext_rst in clk cycles
EXT_RST_DELAY_CYCLE : integer := 100_000 -- 1st reg write to happen clk cycles after ext_rst
);
PORT (
CLK : IN std_logic; -- system clock 50Mhz
RESET : IN std_logic; -- active high reset
START : IN std_logic; -- rising edge triggers r/w; synchronous to CLK
EXT_RSTn : OUT std_logic; -- active low for resetting the slave
BUSY : OUT std_logic; -- indicates transaction in progress
ACK_ERROR : OUT std_logic; -- i2c has unexpected ack
SDA_in : IN std_logic; -- serial data input from i2c bus
SDA_out : OUT std_logic; -- serial data output to i2c bus
SDA_t : OUT std_logic; -- serial data direction to/from i2c bus, '1' is read-in
SCL : OUT std_logic -- serial clock output to i2c bus
);
END COMPONENT;
---------------------------------------------> I2C
---------------------------------------------< TMS
COMPONENT sdm_adc_data_aurora_recv
GENERIC (
NCH_ADC : positive := 20;
ADC_CYC : positive := 20;
NCH_SDM : positive := 19;
SDM_CYC : positive := 4
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
USER_CLK : IN std_logic;
M_AXI_RX_TDATA : IN std_logic_vector(63 DOWNTO 0);
M_AXI_RX_TVALID : IN std_logic;
DOUT : OUT std_logic_vector(511 DOWNTO 0);
DOUT_VALID : OUT std_logic;
FIFO_FULL : OUT std_logic
);
END COMPONENT;
---------------------------------------------> TMS
---------------------------------------------< debug : ILA and VIO (`Chipscope')
COMPONENT dbg_ila
PORT (
CLK : IN std_logic;
PROBE0 : IN std_logic_vector(63 DOWNTO 0);
PROBE1 : IN std_logic_vector(79 DOWNTO 0);
PROBE2 : IN std_logic_vector(79 DOWNTO 0);
PROBE3 : IN std_logic_vector(2047 DOWNTO 0)
);
END COMPONENT;
COMPONENT dbg_ila1
PORT (
CLK : IN std_logic;
PROBE0 : IN std_logic_vector(15 DOWNTO 0);
PROBE1 : IN std_logic_vector(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT dbg_vio
PORT (
CLK : IN std_logic;
PROBE_IN0 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN1 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN2 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN3 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN4 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN5 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN6 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN7 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN8 : IN std_logic_vector(35 DOWNTO 0);
PROBE_OUT0 : OUT std_logic_vector(63 DOWNTO 0)
);
END COMPONENT;
---------------------------------------------> debug : ILA and VIO (`Chipscope')
-- Signals
SIGNAL reset : std_logic;
SIGNAL sys_clk : std_logic;
SIGNAL global_clk_locked : std_logic;
SIGNAL clk_50MHz : std_logic;
SIGNAL clk_100MHz : std_logic;
SIGNAL clk_125MHz : std_logic;
SIGNAL clk_200MHz : std_logic;
SIGNAL clk_250MHz : std_logic;
SIGNAL clk_sgmii_i : std_logic;
SIGNAL clk_sgmii : std_logic;
SIGNAL clk156p25 : std_logic;
SIGNAL clk_user : std_logic;
---------------------------------------------< UART/RS232
SIGNAL uart_rx_data : std_logic_vector(7 DOWNTO 0);
SIGNAL uart_rx_rdy : std_logic;
SIGNAL control_clk : std_logic;
SIGNAL control_fifo_q : std_logic_vector(35 DOWNTO 0);
SIGNAL control_fifo_rdreq : std_logic;
SIGNAL control_fifo_empty : std_logic;
SIGNAL control_fifo_rdclk : std_logic;
SIGNAL cmd_fifo_q : std_logic_vector(35 DOWNTO 0);
SIGNAL cmd_fifo_empty : std_logic;
SIGNAL cmd_fifo_rdreq : std_logic;
-- thirtytwo 16bit registers
SIGNAL config_reg : std_logic_vector(511 DOWNTO 0);
-- 16bit pulse register
SIGNAL pulse_reg : std_logic_vector(15 DOWNTO 0);
-- eleven 16bit registers
SIGNAL status_reg : std_logic_vector(175 DOWNTO 0) := (OTHERS => '0');
SIGNAL control_mem_we : std_logic;
SIGNAL control_mem_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL control_mem_din : std_logic_vector(31 DOWNTO 0);
SIGNAL control_data_fifo_q : std_logic_vector(31 DOWNTO 0);
SIGNAL control_data_fifo_empty : std_logic;
SIGNAL control_data_fifo_rdreq : std_logic;
SIGNAL control_data_fifo_rdclk : std_logic;
SIGNAL control_data_fifo_reset : std_logic;
---------------------------------------------> UART/RS232
---------------------------------------------< gtx / aurora
SIGNAL aurora_reset : std_logic;
SIGNAL aurora_status : std_logic_vector(15 DOWNTO 0);
SIGNAL aurora_user_clk : std_logic;
SIGNAL aurora_ufc_tx_req : std_logic;
SIGNAL aurora_ufc_tx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_ufc_tx_ms : std_logic_vector(7 DOWNTO 0);
SIGNAL aurora_ufc_tx_tvalid : std_logic;
SIGNAL aurora_ufc_tx_tready : std_logic;
SIGNAL aurora_ufc_rx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_ufc_rx_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL aurora_ufc_rx_tlast : std_logic;
SIGNAL aurora_ufc_rx_tvalid : std_logic;
SIGNAL aurora_ufc_in_progress_n : std_logic;
SIGNAL aurora_tx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_tx_tvalid : std_logic;
SIGNAL aurora_tx_tready : std_logic;
SIGNAL aurora_rx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_rx_tvalid : std_logic;
---------------------------------------------> gtx / aurora
---------------------------------------------< ten_gig_eth
SIGNAL sfp_tx_disable_i : std_logic;
SIGNAL sPcs_pma_core_status : std_logic_vector(7 DOWNTO 0);
SIGNAL sEmac_status_vector : std_logic_vector(1 DOWNTO 0);
SIGNAL sTx_axis_fifo_aresetn : std_logic;
SIGNAL sTx_axis_fifo_aclk : std_logic;
SIGNAL sTx_axis_fifo_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL sTx_axis_fifo_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL sTx_axis_fifo_tvalid : std_logic;
SIGNAL sTx_axis_fifo_tlast : std_logic;
SIGNAL sTx_axis_fifo_tready : std_logic;
SIGNAL sRx_axis_fifo_aresetn : std_logic;
SIGNAL sRx_axis_fifo_aclk : std_logic;
SIGNAL sRx_axis_fifo_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL sRx_axis_fifo_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL sRx_axis_fifo_tvalid : std_logic;
SIGNAL sRx_axis_fifo_tlast : std_logic;
SIGNAL sRx_axis_fifo_tready : std_logic;
-- control interface
SIGNAL s_axi_aclk : std_logic;
SIGNAL s_axi_aresetn : std_logic;
SIGNAL s_axi_awaddr : std_logic_vector(10 DOWNTO 0);
SIGNAL s_axi_awvalid : std_logic;
SIGNAL s_axi_awready : std_logic;
SIGNAL s_axi_wdata : std_logic_vector(31 DOWNTO 0);
SIGNAL s_axi_wvalid : std_logic;
SIGNAL s_axi_wready : std_logic;
SIGNAL s_axi_bresp : std_logic_vector(1 DOWNTO 0);
SIGNAL s_axi_bvalid : std_logic;
SIGNAL s_axi_bready : std_logic;
SIGNAL s_axi_araddr : std_logic_vector(10 DOWNTO 0);
SIGNAL s_axi_arvalid : std_logic;
SIGNAL s_axi_arready : std_logic;
SIGNAL s_axi_rdata : std_logic_vector(31 DOWNTO 0);
SIGNAL s_axi_rresp : std_logic_vector(1 DOWNTO 0);
SIGNAL s_axi_rvalid : std_logic;
SIGNAL s_axi_rready : std_logic;
-- packets
SIGNAL ten_gig_eth_tx_start : std_logic;
SIGNAL tge_cmd_fifo_q : std_logic_vector(127 DOWNTO 0);
SIGNAL tge_cmd_fifo_empty : std_logic;
SIGNAL tge_cmd_fifo_rdreq : std_logic;
---------------------------------------------> ten_gig_eth
SIGNAL usr_data_output : std_logic_vector (7 DOWNTO 0);
---------------------------------------------< gig_eth
SIGNAL gig_eth_mac_addr : std_logic_vector(47 DOWNTO 0);
SIGNAL gig_eth_ipv4_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_subnet_mask : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_gateway_ip_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_tx_tdata : std_logic_vector(7 DOWNTO 0);
SIGNAL gig_eth_tx_tvalid : std_logic;
SIGNAL gig_eth_tx_tready : std_logic;
SIGNAL gig_eth_rx_tdata : std_logic_vector(7 DOWNTO 0);
SIGNAL gig_eth_rx_tvalid : std_logic;
SIGNAL gig_eth_rx_tready : std_logic;
SIGNAL gig_eth_tcp_use_fifo : std_logic;
SIGNAL gig_eth_tx_fifo_wrclk : std_logic;
SIGNAL gig_eth_tx_fifo_q : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_tx_fifo_wren : std_logic;
SIGNAL gig_eth_tx_fifo_full : std_logic;
SIGNAL gig_eth_rx_fifo_rdclk : std_logic;
SIGNAL gig_eth_rx_fifo_q : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_rx_fifo_rden : std_logic;
SIGNAL gig_eth_rx_fifo_empty : std_logic;
SIGNAL gig_eth_tx_fifo1_wrclk : std_logic;
SIGNAL gig_eth_tx_fifo1_q : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_tx_fifo1_wren : std_logic;
SIGNAL gig_eth_tx_fifo1_full : std_logic;
SIGNAL gig_eth_rx_fifo1_rdclk : std_logic;
SIGNAL gig_eth_rx_fifo1_q : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_rx_fifo1_rden : std_logic;
SIGNAL gig_eth_rx_fifo1_empty : std_logic;
---------------------------------------------> gig_eth
---------------------------------------------< SDRAM
SIGNAL sdram_app_addr : std_logic_vector(28-1 DOWNTO 0);
SIGNAL sdram_app_en : std_logic;
SIGNAL sdram_app_rdy : std_logic;
SIGNAL sdram_app_wdf_data : std_logic_vector(512-1 DOWNTO 0);
SIGNAL sdram_app_wdf_end : std_logic;
SIGNAL sdram_app_wdf_wren : std_logic;
SIGNAL sdram_app_wdf_rdy : std_logic;
SIGNAL sdram_app_rd_data : std_logic_vector(512-1 DOWNTO 0);
SIGNAL sdram_app_rd_data_valid : std_logic;
---------------------------------------------> SDRAM
---------------------------------------------< IDATA
SIGNAL TRIG_OUT_0 : std_logic;
SIGNAL idata_cmd_out : std_logic_vector(63 DOWNTO 0);
SIGNAL idata_cmd_out_val : std_logic;
SIGNAL idata_cmd_in : std_logic_vector(63 DOWNTO 0);
SIGNAL idata_cmd_in_val : std_logic;
SIGNAL idata_adc_data_clk : std_logic;
SIGNAL idata_adc_refout_clkdiv : std_logic;
SIGNAL idata_adc_data0 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data1 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data2 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data3 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data4 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data5 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data6 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data7 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data8 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data9 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data10 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data11 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_data_fifo_reset : std_logic;
SIGNAL idata_data_fifo_rdclk : std_logic;
SIGNAL idata_data_fifo_din : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_channel_avg_outdata_q : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_channel_avg_outvalid : std_logic;
SIGNAL idata_data_fifo_wren : std_logic;
SIGNAL idata_data_fifo_rden : std_logic;
SIGNAL idata_data_fifo_dout : std_logic_vector(31 DOWNTO 0);
SIGNAL idata_data_fifo_full : std_logic;
SIGNAL idata_data_fifo_empty : std_logic;
SIGNAL idata_idata_fifo_q : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_idata_fifo_wren : std_logic;
SIGNAL idata_idata_fifo_rden : std_logic;
SIGNAL idata_idata_fifo_full : std_logic;
SIGNAL idata_idata_fifo_empty : std_logic;
SIGNAL idata_trig_allow : std_logic;
SIGNAL idata_trig_in : std_logic;
SIGNAL idata_trig_synced : std_logic;
SIGNAL idata_data_wr_start : std_logic;
SIGNAL idata_data_wr_busy : std_logic;
SIGNAL idata_data_wr_wrapped : std_logic;
---------------------------------------------> IDATA
---------------------------------------------< I2C
SIGNAL i2c_sda_out : std_logic;
SIGNAL i2c_sda_in : std_logic;
SIGNAL i2c_sda_t : std_logic;
SIGNAL i2c_scl_out : std_logic;
---------------------------------------------> I2C
---------------------------------------------< TMS
SIGNAL tms_sdm_adc_dout : std_logic_vector(511 DOWNTO 0);
SIGNAL tms_sdm_adc_dout_valid : std_logic;
---------------------------------------------< TMS
---------------------------------------------< debug
SIGNAL dbg_ila_probe0 : std_logic_vector (63 DOWNTO 0);
SIGNAL dbg_ila_probe1 : std_logic_vector (79 DOWNTO 0);
SIGNAL dbg_ila_probe2 : std_logic_vector (79 DOWNTO 0);
SIGNAL dbg_ila_probe3 : std_logic_vector (2047 DOWNTO 0);
SIGNAL dbg_vio_probe_out0 : std_logic_vector (63 DOWNTO 0);
SIGNAL dbg_ila1_probe0 : std_logic_vector (15 DOWNTO 0);
SIGNAL dbg_ila1_probe1 : std_logic_vector (15 DOWNTO 0);
ATTRIBUTE mark_debug : string;
ATTRIBUTE keep : string;
ATTRIBUTE mark_debug OF USB_TX : SIGNAL IS "true";
ATTRIBUTE mark_debug OF uart_rx_data : SIGNAL IS "true";
ATTRIBUTE mark_debug OF uart_rx_rdy : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_empty : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_rdreq : SIGNAL IS "true";
ATTRIBUTE mark_debug OF config_reg : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF status_reg : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF pulse_reg : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_we : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_addr : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_din : SIGNAL IS "true";
--
ATTRIBUTE mark_debug OF sPcs_pma_core_status : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sEmac_status_vector : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_aresetn : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_aclk : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tkeep : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tlast : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tready : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_aresetn : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_aclk : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tkeep : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tlast : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tready : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF ten_gig_eth_tx_start : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_empty : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_rdreq : SIGNAL IS "true";
--
ATTRIBUTE mark_debug OF gig_eth_tx_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_tx_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_tx_tready : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_tready : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_tx_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_fifo_q : SIGNAL IS "true";
--
ATTRIBUTE mark_debug OF sdram_app_addr : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_en : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_rdy : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_data : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_end : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_wren : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_rdy : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_rd_data : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_rd_data_valid : SIGNAL IS "true";
---------------------------------------------> debug
BEGIN
---------------------------------------------< Clock
global_clock_reset_inst : global_clock_reset
PORT MAP (
SYS_CLK_P => SYS_CLK_P,
SYS_CLK_N => SYS_CLK_N,
FORCE_RST => SYS_RST,
-- output
GLOBAL_RST => reset,
SYS_CLK => sys_clk,
LOCKED => global_clk_locked,
CLK_OUT1 => clk_50MHz,
CLK_OUT2 => clk_100MHz,
CLK_OUT3 => OPEN,
CLK_OUT4 => clk_250MHz
);
user_clk_ibufds_inst : IBUFDS
GENERIC MAP (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS"
)
PORT MAP (
O => clk_user, -- Buffer output
I => USER_CLK_P, -- Diff_p buffer input (connect directly to top-level port)
IB => USER_CLK_N -- Diff_n buffer input (connect directly to top-level port)
);
-- gtx/gth reference clock can be used as general purpose clock this way
-- sgmiiclk_ibufds_inst : IBUFDS_GTE2
-- PORT MAP (
-- O => clk_sgmii_i,
-- ODIV2 => OPEN,
-- CEB => '0',
-- I => SGMIICLK_Q0_P,
-- IB => SGMIICLK_Q0_N
-- );
-- sgmiiclk_bufg_inst : BUFG
-- PORT MAP (
-- I => clk_sgmii_i,
-- O => clk_sgmii
-- );
clk_125MHz <= clk_sgmii;
---------------------------------------------> Clock
---------------------------------------------< debug : ILA and VIO (`Chipscope')
dbg_cores : IF ENABLE_DEBUG GENERATE
dbg_ila_inst : dbg_ila
PORT MAP (
CLK => sys_clk,
PROBE0 => dbg_ila_probe0,
PROBE1 => dbg_ila_probe1,
PROBE2 => dbg_ila_probe2,
PROBE3 => dbg_ila_probe3
);
dbg_vio_inst : dbg_vio
PORT MAP (
CLK => sys_clk,
PROBE_IN0 => config_reg(64*1-1 DOWNTO 64*0),
PROBE_IN1 => config_reg(64*2-1 DOWNTO 64*1),
PROBE_IN2 => config_reg(64*3-1 DOWNTO 64*2),
PROBE_IN3 => config_reg(64*4-1 DOWNTO 64*3),
PROBE_IN4 => config_reg(64*5-1 DOWNTO 64*4),
PROBE_IN5 => config_reg(64*6-1 DOWNTO 64*5),
PROBE_IN6 => config_reg(64*7-1 DOWNTO 64*6),
PROBE_IN7 => x"00000000000000" & sPcs_pma_core_status, -- config_reg(64*8-1 DOWNTO 64*7),
PROBE_IN8 => cmd_fifo_q,
PROBE_OUT0 => dbg_vio_probe_out0
);
--dbg_ila1_inst : dbg_ila1
-- PORT MAP (
-- CLK => sys_clk,
-- PROBE0 => dbg_ila1_probe0,
-- PROBE1 => dbg_ila1_probe1
-- );
END GENERATE dbg_cores;
---------------------------------------------> debug : ILA and VIO (`Chipscope')
---------------------------------------------< UART/RS232
uart_cores : IF false GENERATE
uartio_inst : uartio
GENERIC MAP (
-- tick repetition frequency is (input freq) / (2**COUNTER_WIDTH / DIVISOR)
COUNTER_WIDTH => 16,
DIVISOR => 1208*2
)
PORT MAP (
CLK => clk_50MHz,
RESET => reset,
RX_DATA => uart_rx_data,
RX_RDY => uart_rx_rdy,
TX_DATA => "0000" & DIPSw4Bit,
TX_EN => '1',
TX_RDY => dbg_ila_probe0(2),
-- serial lines
RX_PIN => USB_TX, -- notice the pin swap
TX_PIN => USB_RX
);
--dbg_ila1_probe0(7 DOWNTO 0) <= uart_rx_data;
--dbg_ila1_probe0(8) <= uart_rx_rdy;
--dbg_ila1_probe0(9) <= USB_TX;
-- dbg_ila_probe0(63 DOWNTO 32) <= cmd_fifo_q(31 DOWNTO 0);
dbg_ila_probe0(31) <= cmd_fifo_empty;
dbg_ila_probe0(30) <= cmd_fifo_rdreq;
byte2cmd_inst : byte2cmd
PORT MAP (
CLK => clk_50MHz,
RESET => reset,
-- byte in
RX_DATA => uart_rx_data,
RX_RDY => uart_rx_rdy,
-- cmd out
CMD_FIFO_Q => OPEN,-- cmd_fifo_q,
CMD_FIFO_EMPTY => OPEN,-- cmd_fifo_empty,
CMD_FIFO_RDCLK => control_clk,
CMD_FIFO_RDREQ => '0' -- cmd_fifo_rdreq
);
END GENERATE uart_cores;
control_clk <= clk_100MHz;
control_interface_inst : control_interface
PORT MAP (
RESET => reset,
CLK => control_clk,
-- From FPGA to PC
FIFO_Q => control_fifo_q,
FIFO_EMPTY => control_fifo_empty,
FIFO_RDREQ => control_fifo_rdreq,
FIFO_RDCLK => control_fifo_rdclk,
-- From PC to FPGA, FWFT
CMD_FIFO_Q => cmd_fifo_q,
CMD_FIFO_EMPTY => cmd_fifo_empty,
CMD_FIFO_RDREQ => cmd_fifo_rdreq,
-- Digital I/O
CONFIG_REG => config_reg,
PULSE_REG => pulse_reg,
STATUS_REG => status_reg,
-- Memory interface
MEM_WE => control_mem_we,
MEM_ADDR => control_mem_addr,
MEM_DIN => control_mem_din,
MEM_DOUT => (OTHERS => '0'),
-- Data FIFO interface, FWFT
DATA_FIFO_Q => control_data_fifo_q,
DATA_FIFO_EMPTY => control_data_fifo_empty,
DATA_FIFO_RDREQ => control_data_fifo_rdreq,
DATA_FIFO_RDCLK => control_data_fifo_rdclk
);
dbg_ila_probe0(18 DOWNTO 3) <= pulse_reg;
---------------------------------------------> UART/RS232
---------------------------------------------< ten_gig_eth
ten_gig_eth_cores : IF ENABLE_TEN_GIG_ETH GENERATE
ten_gig_eth_inst : ten_gig_eth
PORT MAP (
REFCLK_P => SI5324CLK_P, -- 156.25MHz for transceiver
REFCLK_N => SI5324CLK_N,
RESET => reset,
SFP_TX_P => SFP_TX_P,
SFP_TX_N => SFP_TX_N,
SFP_RX_P => SFP_RX_P,
SFP_RX_N => SFP_RX_N,
SFP_LOS => SFP_LOS_LS, -- loss of receiver signal
SFP_TX_DISABLE => sfp_tx_disable_i,
-- clk156.25 domain, clock generated by the core
CLK156p25 => clk156p25,
PCS_PMA_CORE_STATUS => sPcs_pma_core_status,
TX_STATISTICS_VECTOR => OPEN,
TX_STATISTICS_VALID => OPEN,
RX_STATISTICS_VECTOR => OPEN,
RX_STATISTICS_VALID => OPEN,
PAUSE_VAL => (OTHERS => '0'),
PAUSE_REQ => '0',
TX_IFG_DELAY => x"ff",
-- emac control interface
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- tx_wr_clk domain
TX_AXIS_FIFO_ARESETN => sTx_axis_fifo_aresetn,
Tx_AXIS_FIFO_ACLK => sTx_axis_fifo_aclk,
TX_AXIS_FIFO_TDATA => sTx_axis_fifo_tdata,
TX_AXIS_FIFO_TKEEP => sTx_axis_fifo_tkeep,
TX_AXIS_FIFO_TVALID => sTx_axis_fifo_tvalid,
TX_AXIS_FIFO_TLAST => sTx_axis_fifo_tlast,
TX_AXIS_FIFO_TREADY => sTx_axis_fifo_tready,
-- rx_rd_clk domain
RX_AXIS_FIFO_ARESETN => sRx_axis_fifo_aresetn,
RX_AXIS_FIFO_ACLK => sRx_axis_fifo_aclk,
RX_AXIS_FIFO_TDATA => sRx_axis_fifo_tdata,
RX_AXIS_FIFO_TKEEP => sRx_axis_fifo_tkeep,
RX_AXIS_FIFO_TVALID => sRx_axis_fifo_tvalid,
RX_AXIS_FIFO_TLAST => sRx_axis_fifo_tlast,
RX_AXIS_FIFO_TREADY => sRx_axis_fifo_tready
);
SFP_TX_DISABLE_N <= NOT sfp_tx_disable_i;
LED8Bit(7) <= sPcs_pma_core_status(0);
LED8Bit(6) <= NOT sfp_tx_disable_i;
LED8Bit(5) <= NOT SFP_LOS_LS;
s_axi_aclk <= clk_50MHz;
sTx_axis_fifo_aclk <= clk_200MHz;
sRx_axis_fifo_aclk <= sTx_axis_fifo_aclk;
s_axi_aresetn <= '1';
sTx_axis_fifo_aresetn <= '1';
-- sRx_axis_fifo_aresetn <= '1';
ten_gig_eth_packet_gen_inst : ten_gig_eth_packet_gen
PORT MAP (
RESET => reset,
MEM_CLK => control_clk,
MEM_WE => control_mem_we,
MEM_ADDR => control_mem_addr,
MEM_D => control_mem_din,
--
TX_AXIS_ACLK => sTx_axis_fifo_aclk,
TX_START => ten_gig_eth_tx_start,
TX_BYTES => config_reg(15 DOWNTO 0),
TX_AXIS_TDATA => OPEN, -- sTx_axis_fifo_tdata,
TX_AXIS_TKEEP => sTx_axis_fifo_tkeep,
TX_AXIS_TVALID => sTx_axis_fifo_tvalid,
TX_AXIS_TLAST => sTx_axis_fifo_tlast,
TX_AXIS_TREADY => sTx_axis_fifo_tready
);
ten_gig_eth_rx_parser_inst : ten_gig_eth_rx_parser
PORT MAP (
RESET => reset,
RX_AXIS_FIFO_ARESETN => sRx_axis_fifo_aresetn,
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK => sRx_axis_fifo_aclk,
RX_AXIS_FIFO_TDATA => sRx_axis_fifo_tdata,
RX_AXIS_FIFO_TKEEP => sRx_axis_fifo_tkeep,
RX_AXIS_FIFO_TVALID => sRx_axis_fifo_tvalid,
RX_AXIS_FIFO_TLAST => sRx_axis_fifo_tlast,
RX_AXIS_FIFO_TREADY => sRx_axis_fifo_tready,
-- Constants
SRC_MAC => x"000a3502a759",
SRC_IP => x"c0a80302",
SRC_PORT => x"ea62",
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q => tge_cmd_fifo_q,
CMD_FIFO_EMPTY => tge_cmd_fifo_empty,
CMD_FIFO_RDREQ => '1',
CMD_FIFO_RDCLK => clk_200MHz
);
ten_gig_eth_tx_start <= pulse_reg(0);
dbg_ila_probe0(0) <= clk156p25;
dbg_ila_probe0(1) <= ten_gig_eth_tx_start;
dbg_ila_probe1(79 DOWNTO 16) <= sTx_axis_fifo_tdata;
dbg_ila_probe1(15 DOWNTO 8) <= sTx_axis_fifo_tkeep;
dbg_ila_probe1(7) <= sTx_axis_fifo_tvalid;
dbg_ila_probe1(6) <= sTx_axis_fifo_tlast;
dbg_ila_probe1(5) <= sTx_axis_fifo_tready;
--dbg_ila_probe2(79 DOWNTO 16) <= sRx_axis_fifo_tdata;
--dbg_ila_probe2(79 DOWNTO 48) <= control_mem_addr;
--dbg_ila_probe2(47 DOWNTO 16) <= control_mem_din;
--dbg_ila_probe2(15 DOWNTO 8) <= sRx_axis_fifo_tkeep;
dbg_ila_probe2(7) <= sRx_axis_fifo_tvalid;
dbg_ila_probe2(6) <= sRx_axis_fifo_tlast;
dbg_ila_probe2(5) <= sRx_axis_fifo_tready;
dbg_ila_probe2(4) <= control_mem_we;
--
--dbg_ila_probe3(127 DOWNTO 0) <= tge_cmd_fifo_q;
--dbg_ila_probe3(128) <= tge_cmd_fifo_empty;
END GENERATE ten_gig_eth_cores;
---------------------------------------------> ten_gig_eth
---------------------------------------------< gtx / aurora
SFP_TX_DISABLE_N <= '1';
LED8Bit(0) <= NOT SFP_LOS_LS; -- SFP is plugged in.
LED8Bit(1) <= aurora_status(0); -- link up.
aurora_64b66b_inst : aurora_64b66b
PORT MAP (
RESET => aurora_reset,
SYS_CLK => clk_100MHz,
MGT_REFCLK_P => SGMIICLK_Q0_P,
MGT_REFCLK_N => SGMIICLK_Q0_N,
-- Data interfaces are synchronous to USER_CLK
USER_CLK => aurora_user_clk,
MGT_REFCLK_BUFG_OUT => clk_sgmii,
-- TX AXI4 interface
S_AXI_TX_TDATA => aurora_tx_tdata,
S_AXI_TX_TVALID => aurora_tx_tvalid,
S_AXI_TX_TREADY => aurora_tx_tready,
-- RX AXI4 interface
M_AXI_RX_TDATA => aurora_rx_tdata,
M_AXI_RX_TVALID => aurora_rx_tvalid,
-- User flow control (UFC) TX
UFC_TX_REQ => aurora_ufc_tx_req,
S_AXI_UFC_TX_TDATA => aurora_ufc_tx_tdata,
UFC_TX_MS => aurora_ufc_tx_ms,
S_AXI_UFC_TX_TVALID => aurora_ufc_tx_tvalid,
S_AXI_UFC_TX_TREADY => aurora_ufc_tx_tready,
-- UFC RX
M_AXI_UFC_RX_TDATA => aurora_ufc_rx_tdata,
M_AXI_UFC_RX_TKEEP => aurora_ufc_rx_tkeep,
M_AXI_UFC_RX_TLAST => aurora_ufc_rx_tlast,
M_AXI_UFC_RX_TVALID => aurora_ufc_rx_tvalid,
UFC_IN_PROGRESSn => aurora_ufc_in_progress_n,
-- GTX pins
RXP => SMA_MGT_RX_P,
RXN => SMA_MGT_RX_N,
TXP => SMA_MGT_TX_P,
TXN => SMA_MGT_TX_N,
-- Status
STATUS => aurora_status
);
aurora_reset <= reset OR pulse_reg(1);
fifo_over_ufc_inst : fifo_over_ufc
PORT MAP (
RESET => reset,
AURORA_USER_CLK => aurora_user_clk,
AURORA_TX_REQ => aurora_ufc_tx_req,
AURORA_TX_MS => aurora_ufc_tx_ms,
AURORA_TX_TREADY => aurora_ufc_tx_tready,
AURORA_TX_TDATA => aurora_ufc_tx_tdata,
AURORA_TX_TVALID => aurora_ufc_tx_tvalid,
AURORA_RX_TDATA => aurora_ufc_rx_tdata,
AURORA_RX_TVALID => aurora_ufc_rx_tvalid,
FIFO_CLK => gig_eth_tx_fifo1_wrclk,
TX_FIFO_Q => gig_eth_tx_fifo1_q,
TX_FIFO_WREN => gig_eth_tx_fifo1_wren,
TX_FIFO_FULL => gig_eth_tx_fifo1_full,
RX_FIFO_Q => gig_eth_rx_fifo1_q,
RX_FIFO_RDEN => gig_eth_rx_fifo1_rden,
RX_FIFO_EMPTY => gig_eth_rx_fifo1_empty,
ERR => LED8Bit(2)
);
gig_eth_rx_fifo1_rdclk <= gig_eth_tx_fifo1_wrclk;
sdm_adc_data_aurora_recv_inst : sdm_adc_data_aurora_recv
GENERIC MAP (
NCH_ADC => 20,
ADC_CYC => 20,
NCH_SDM => 19,
SDM_CYC => 4
)
PORT MAP (
RESET => reset,
CLK => control_clk,
USER_CLK => aurora_user_clk,
M_AXI_RX_TDATA => aurora_rx_tdata,
M_AXI_RX_TVALID => aurora_rx_tvalid,
DOUT => tms_sdm_adc_dout,
DOUT_VALID => tms_sdm_adc_dout_valid,
FIFO_FULL => OPEN
);
data_sampler_fifo_inst : data_sampler_fifo
GENERIC MAP (
DIN_WIDTH => 512,
DOUT_WIDTH => 32
)
PORT MAP (
RESET => control_data_fifo_reset,
CLK => control_clk,
TRIG => idata_trig_in,
DIN => tms_sdm_adc_dout,
DIN_VALID => tms_sdm_adc_dout_valid,
DIN_CLK => aurora_user_clk,
DOUT => control_data_fifo_q,
DOUT_EMPTY => control_data_fifo_empty,
DOUT_RDEN => control_data_fifo_rdreq
);
control_data_fifo_reset <= reset OR idata_data_fifo_reset;
-- -- debug
-- aurora_ufc_tx_req <= pulse_reg(8);
-- ufc_tx_tvalid_edge_sync_inst : edge_sync
-- GENERIC MAP (
-- EDGE => '0'
-- )
-- PORT MAP (
-- RESET => reset,
-- CLK => aurora_user_clk,
-- EI => aurora_ufc_tx_req,
-- SO => aurora_ufc_tx_tvalid
-- );
-- aurora_ufc_tx_tdata <= x"0000_0000_0000" & config_reg(30*16+15 DOWNTO 30*16);
-- aurora_ufc_tx_ms <= config_reg(29*16+7 DOWNTO 29*16); -- don't reverse bit-order here
--
dbg_ila1_inst : dbg_ila1
PORT MAP (
CLK => aurora_user_clk,
PROBE0 => dbg_ila1_probe0,
PROBE1 => dbg_ila1_probe1
);
-- dbg_ila1_probe0 <=
-- "0000" & gig_eth_rx_fifo_empty & aurora_status(2) & aurora_status(1) & aurora_status(0)
-- & aurora_reset & aurora_ufc_in_progress_n & aurora_ufc_rx_tlast & aurora_ufc_rx_tvalid
-- & aurora_ufc_tx_req & aurora_ufc_tx_tready & aurora_ufc_tx_tvalid & aurora_tx_tready;
-- dbg_ila1_probe1 <= aurora_ufc_rx_tdata(7 DOWNTO 0) & aurora_ufc_tx_tdata(7 DOWNTO 0);
PROCESS (aurora_user_clk, reset) IS
BEGIN -- PROCESS
IF reset = '1' THEN
dbg_ila1_probe0 <= (OTHERS => '0');
ELSIF rising_edge(aurora_user_clk) THEN -- rising clock edge
IF tms_sdm_adc_dout_valid = '1' THEN
dbg_ila1_probe0 <= tms_sdm_adc_dout(16*19+15 DOWNTO 16*19);
END IF;
END IF;
END PROCESS;
dbg_ila1_probe1 <= aurora_rx_tdata(63 DOWNTO 63-13) & aurora_rx_tvalid & control_data_fifo_reset;
---------------------------------------------> gtx / aurora
---------------------------------------------< gig_eth
gig_eth_cores : IF ENABLE_GIG_ETH GENERATE
gig_eth_mac_addr(gig_eth_mac_addr'length-1 DOWNTO 4) <= x"000a3502a75";
gig_eth_mac_addr(3 DOWNTO 0) <= DIPSw4Bit;
gig_eth_ipv4_addr(gig_eth_ipv4_addr'length-1 DOWNTO 4) <= x"c0a8020";
gig_eth_ipv4_addr(3 DOWNTO 0) <= DIPSw4Bit;
gig_eth_subnet_mask <= x"ffffff00";
gig_eth_gateway_ip_addr <= x"c0a80201";
gig_eth_inst : gig_eth
PORT MAP (
-- asynchronous reset
GLBL_RST => reset,
-- clocks
GTX_CLK => clk_125MHz,
REF_CLK => sys_clk, -- 200MHz for IODELAY
-- PHY interface
PHY_RESETN => PHY_RESET_N,
-- RGMII Interface
RGMII_TXD => RGMII_TXD,
RGMII_TX_CTL => RGMII_TX_CTL,
RGMII_TXC => RGMII_TXC,
RGMII_RXD => RGMII_RXD,
RGMII_RX_CTL => RGMII_RX_CTL,
RGMII_RXC => RGMII_RXC,
-- MDIO Interface
MDIO => MDIO,
MDC => MDC,
-- TCP
MAC_ADDR => gig_eth_mac_addr,
IPv4_ADDR => gig_eth_ipv4_addr,
IPv6_ADDR => (OTHERS => '0'),
SUBNET_MASK => gig_eth_subnet_mask,
GATEWAY_IP_ADDR => gig_eth_gateway_ip_addr,
TCP_CONNECTION_RESET => '0',
TX_TDATA => gig_eth_tx_tdata,
TX_TVALID => gig_eth_tx_tvalid,
TX_TREADY => gig_eth_tx_tready,
RX_TDATA => gig_eth_rx_tdata,
RX_TVALID => gig_eth_rx_tvalid,
RX_TREADY => gig_eth_rx_tready,
-- FIFO
TCP_USE_FIFO => gig_eth_tcp_use_fifo,
TX_FIFO_WRCLK => gig_eth_tx_fifo_wrclk,
TX_FIFO_Q => gig_eth_tx_fifo_q,
TX_FIFO_WREN => gig_eth_tx_fifo_wren,
TX_FIFO_FULL => gig_eth_tx_fifo_full,
RX_FIFO_RDCLK => gig_eth_rx_fifo_rdclk,
RX_FIFO_Q => gig_eth_rx_fifo_q,
RX_FIFO_RDEN => gig_eth_rx_fifo_rden,
RX_FIFO_EMPTY => gig_eth_rx_fifo_empty,
--
TX_FIFO1_WRCLK => gig_eth_tx_fifo1_wrclk,
TX_FIFO1_Q => gig_eth_tx_fifo1_q,
TX_FIFO1_WREN => gig_eth_tx_fifo1_wren,
TX_FIFO1_FULL => gig_eth_tx_fifo1_full,
RX_FIFO1_RDCLK => gig_eth_rx_fifo1_rdclk,
RX_FIFO1_Q => gig_eth_rx_fifo1_q,
RX_FIFO1_RDEN => gig_eth_rx_fifo1_rden,
RX_FIFO1_EMPTY => gig_eth_rx_fifo1_empty
);
dbg_ila_probe0(26 DOWNTO 19) <= gig_eth_rx_tdata;
dbg_ila_probe0(27) <= gig_eth_rx_tvalid;
dbg_ila_probe0(28) <= gig_eth_rx_tready;
-- loopback
--gig_eth_tx_tdata <= gig_eth_rx_tdata;
--gig_eth_tx_tvalid <= gig_eth_rx_tvalid;
--gig_eth_rx_tready <= gig_eth_tx_tready;
-- receive to cmd_fifo
gig_eth_tcp_use_fifo <= '1';
gig_eth_rx_fifo_rdclk <= control_clk;
cmd_fifo_q(31 DOWNTO 0) <= gig_eth_rx_fifo_q;
dbg_ila_probe0(63 DOWNTO 32) <= gig_eth_rx_fifo_q;
cmd_fifo_empty <= gig_eth_rx_fifo_empty;
gig_eth_rx_fifo_rden <= cmd_fifo_rdreq;
-- send control_fifo data through gig_eth_tx_fifo
gig_eth_tx_fifo_wrclk <= clk_125MHz;
-- connect FWFT fifo interface
control_fifo_rdclk <= gig_eth_tx_fifo_wrclk;
gig_eth_tx_fifo_q <= control_fifo_q(31 DOWNTO 0);
gig_eth_tx_fifo_wren <= NOT control_fifo_empty;
control_fifo_rdreq <= NOT gig_eth_tx_fifo_full;
END GENERATE gig_eth_cores;
---------------------------------------------> gig_eth
---------------------------------------------< SDRAM
sdram_ddr3_inst : sdram_ddr3
PORT MAP (
CLK => sys_clk, -- system clock, must be the same as intended in MIG
REFCLK => sys_clk, -- 200MHz for iodelay
RESET => reset,
-- SDRAM_DDR3
-- Inouts
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
-- Outputs
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT,
-- Status Outputs
INIT_CALIB_COMPLETE => LED8Bit(4),
-- Internal data r/w interface
UI_CLK => clk_200MHz,
--
CTRL_RESET => pulse_reg(6),
WR_START => idata_data_wr_start,
WR_ADDR_BEGIN => config_reg(32*4+27 DOWNTO 32*4),
WR_STOP => pulse_reg(4),
WR_WRAP_AROUND => config_reg(32*4+28),
POST_TRIGGER => config_reg(32*5+27 DOWNTO 32*5),
WR_BUSY => idata_data_wr_busy,
WR_POINTER => OPEN,
TRIGGER_POINTER => status_reg(64*2+27 DOWNTO 64*2),
WR_WRAPPED => idata_data_wr_wrapped,
RD_START => pulse_reg(5),
RD_ADDR_BEGIN => (OTHERS => '0'),
RD_ADDR_END => config_reg(32*6+27 DOWNTO 32*6),
RD_BUSY => status_reg(64*2+30),
--
DATA_FIFO_RESET => idata_data_fifo_reset,
INDATA_FIFO_WRCLK => idata_adc_data_clk,
INDATA_FIFO_Q => idata_idata_fifo_q,
INDATA_FIFO_FULL => idata_idata_fifo_full,
INDATA_FIFO_WREN => idata_idata_fifo_wren,
--
OUTDATA_FIFO_RDCLK => idata_data_fifo_rdclk,
OUTDATA_FIFO_Q => idata_data_fifo_dout,
OUTDATA_FIFO_EMPTY => idata_data_fifo_empty,
OUTDATA_FIFO_RDEN => idata_data_fifo_rden,
--
DBG_APP_ADDR => sdram_app_addr,
DBG_APP_EN => sdram_app_en,
DBG_APP_RDY => sdram_app_rdy,
DBG_APP_WDF_DATA => sdram_app_wdf_data,
DBG_APP_WDF_END => sdram_app_wdf_end,
DBG_APP_WDF_WREN => sdram_app_wdf_wren,
DBG_APP_WDF_RDY => sdram_app_wdf_rdy,
DBG_APP_RD_DATA => sdram_app_rd_data,
DBG_APP_RD_DATA_VALID => sdram_app_rd_data_valid
);
idata_adc_data_clk <= clk_125MHz;
idata_data_fifo_reset <= pulse_reg(2);
status_reg(64*2+28) <= idata_data_wr_busy;
status_reg(64*2+29) <= idata_data_wr_wrapped;
--
channel_sel_inst : channel_sel
PORT MAP (
CLK => idata_adc_data_clk, -- fifo wrclk
RESET => reset,
SEL => config_reg(32*7+7 DOWNTO 32*7),
--
DATA_FIFO_RESET => idata_data_fifo_reset,
--
INDATA_Q => idata_channel_avg_outdata_q,
DATA_FIFO_WREN => idata_data_fifo_wren,
DATA_FIFO_FULL => idata_data_fifo_full,
--
OUTDATA_FIFO_Q => idata_idata_fifo_q,
DATA_FIFO_RDEN => idata_idata_fifo_rden,
DATA_FIFO_EMPTY => idata_idata_fifo_empty
);
idata_idata_fifo_rden <= NOT idata_idata_fifo_full;
idata_idata_fifo_wren <= NOT idata_idata_fifo_empty;
idata_data_fifo_wren <= config_reg(32*6+31) AND idata_channel_avg_outvalid;
--
channel_avg_inst : channel_avg
PORT MAP (
RESET => reset,
CLK => idata_adc_data_clk,
-- high 4-bit is offset, 2**(low 4-bit) is number of points to average
CONFIG => config_reg(32*7+15 DOWNTO 32*7+8),
TRIG => idata_data_wr_start,
INDATA_Q => idata_data_fifo_din,
OUTVALID => idata_channel_avg_outvalid,
OUTDATA_Q => idata_channel_avg_outdata_q
);
--
dbg_ila_probe3(27 DOWNTO 0) <= sdram_app_addr;
dbg_ila_probe3(28) <= sdram_app_en;
dbg_ila_probe3(29) <= sdram_app_rdy;
dbg_ila_probe3(30) <= sdram_app_wdf_wren;
dbg_ila_probe3(31) <= sdram_app_wdf_rdy;
dbg_ila_probe3(32) <= sdram_app_wdf_end;
dbg_ila_probe3(1023 DOWNTO 512) <= sdram_app_wdf_data;
dbg_ila_probe3(1024+1023 DOWNTO 1024+512) <= sdram_app_rd_data;
dbg_ila_probe3(33) <= sdram_app_rd_data_valid;
dbg_ila_probe3(511 DOWNTO 336) <= status_reg;
---------------------------------------------> SDRAM
---------------------------------------------< I2C
i2c_write_regmap_inst : i2c_write_regmap
GENERIC MAP (
-- file not used, see actual code.
REGMAP_FNAME => "../../../config/Si5324_156.25MHz_regmap.txt",
INPUT_CLK_FREQENCY => 100_000_000,
BUS_CLK_FREQUENCY => 100_000
)
PORT MAP (
CLK => control_clk,
RESET => reset,
START => pulse_reg(15),
EXT_RSTn => SI5324_RSTn,
BUSY => status_reg(16*10+7),
ACK_ERROR => status_reg(16*10+6),
SDA_in => i2c_sda_in,
SDA_out => i2c_sda_out,
SDA_t => i2c_sda_t,
SCL => i2c_scl_out
);
i2c_sda_iobuf_inst : IOBUF
GENERIC MAP(
DRIVE => 12,
SLEW => "SLOW"
)
PORT MAP(
O => i2c_sda_in,
IO => I2C_SDA,
I => i2c_sda_out,
T => i2c_sda_t
);
i2c_scl_iobuf_inst : IOBUF
GENERIC MAP(
DRIVE => 12,
SLEW => "SLOW"
)
PORT MAP(
O => OPEN,
IO => I2C_SCL,
I => i2c_scl_out,
T => '0'
);
-- External clock IC
si5324_clk_div_inst : clk_div
GENERIC MAP (
WIDTH => 32,
PBITS => 8
)
PORT MAP (
RESET => reset,
CLK => clk156p25,
DIV => x"1b",
CLK_DIV => LED8Bit(3)
);
---------------------------------------------> I2C
-- clock output
refout_clk_div_inst : clk_div
PORT MAP (
RESET => reset,
CLK => idata_adc_data_clk,
DIV => config_reg(16*15+3 DOWNTO 16*15),
CLK_DIV => idata_adc_refout_clkdiv
);
clk_fwd_inst : clk_fwd -- idata_adc_refout_clkdiv
PORT MAP (R => reset, I => clk156p25, O => USER_SMA_CLOCK_P);
clk_fwd_inst1 : clk_fwd GENERIC MAP (INV => true)
PORT MAP (R => reset, I => clk156p25, O => USER_SMA_CLOCK_N);
clk_fwd_inst2 : clk_fwd GENERIC MAP (INV => true)
PORT MAP (R => reset, I => idata_adc_data_clk, O => USER_SMA_GPIO_N);
-- capture the rising edge of trigger
trig_edge_sync_inst : edge_sync
PORT MAP (
RESET => reset,
CLK => control_clk,
EI => idata_trig_in,
SO => idata_trig_synced
);
idata_trig_in <= USER_SMA_GPIO_P;
idata_trig_allow <= config_reg(32*6+30);
idata_data_wr_start <= pulse_reg(3) OR (idata_trig_synced AND idata_trig_allow
AND (NOT idata_data_wr_busy)
AND (NOT idata_data_wr_wrapped));
--led_obufs : FOR i IN 0 TO 7 GENERATE
-- led_obuf : OBUF
-- PORT MAP (
-- I => usr_data_output(i),
-- O => LED8Bit(i)
-- );
--END GENERATE led_obufs;
--LED8Bit(5 DOWNTO 1) <= (OTHERS => '0');
END Behavioral;
| bsd-3-clause | 86d1bea022f230e7aa3a4c9b478a0879 | 0.510621 | 3.46514 | false | false | false | false |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_06_a/hdl/vhdl/radio_controller.vhd | 2 | 38,342 | -- Copyright (c) 2006 Rice University
-- All Rights Reserved
-- This code is covered by the Rice-WARP license
-- See http://warp.rice.edu/license/ for details
------------------------------------------------------------------------------
-- radio_controller.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
library opb_ipif_v3_01_c;
use opb_ipif_v3_01_c.all;
library radio_controller_v1_06_a;
use radio_controller_v1_06_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
------------------------------------------------------------------------------
entity radio_controller is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"00000000";
C_HIGHADDR : std_logic_vector := X"0000FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
spi_clk : out std_logic;
data_out : out std_logic;
radio1_cs : out std_logic;
radio2_cs : out std_logic;
radio3_cs : out std_logic;
radio4_cs : out std_logic;
dac1_cs : out std_logic;
dac2_cs : out std_logic;
dac3_cs : out std_logic;
dac4_cs : out std_logic;
radio1_SHDN : out std_logic;
radio1_TxEn : out std_logic;
radio1_RxEn : out std_logic;
radio1_RxHP : out std_logic;
radio1_LD : in std_logic;
radio1_24PA : out std_logic;
radio1_5PA : out std_logic;
radio1_ANTSW : out std_logic_vector(0 to 1);
radio1_LED : out std_logic_vector(0 to 2);
radio1_ADC_RX_DCS : out std_logic;
radio1_ADC_RX_DFS : out std_logic;
radio1_ADC_RX_OTRA : in std_logic;
radio1_ADC_RX_OTRB : in std_logic;
radio1_ADC_RX_PWDNA : out std_logic;
radio1_ADC_RX_PWDNB : out std_logic;
radio1_DIPSW : in std_logic_vector(0 to 3);
radio1_RSSI_ADC_CLAMP : out std_logic;
radio1_RSSI_ADC_HIZ : out std_logic;
radio1_RSSI_ADC_OTR : in std_logic;
radio1_RSSI_ADC_SLEEP : out std_logic;
radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio1_TX_DAC_PLL_LOCK : in std_logic;
radio1_TX_DAC_RESET : out std_logic;
radio1_RxHP_external : in std_logic;
radio1_TxGain : out std_logic_vector(0 to 5);
radio1_TxStart : out std_logic;
radio2_SHDN : out std_logic;
radio2_TxEn : out std_logic;
radio2_RxEn : out std_logic;
radio2_RxHP : out std_logic;
radio2_LD : in std_logic;
radio2_24PA : out std_logic;
radio2_5PA : out std_logic;
radio2_ANTSW : out std_logic_vector(0 to 1);
radio2_LED : out std_logic_vector(0 to 2);
radio2_ADC_RX_DCS : out std_logic;
radio2_ADC_RX_DFS : out std_logic;
radio2_ADC_RX_OTRA : in std_logic;
radio2_ADC_RX_OTRB : in std_logic;
radio2_ADC_RX_PWDNA : out std_logic;
radio2_ADC_RX_PWDNB : out std_logic;
radio2_DIPSW : in std_logic_vector(0 to 3);
radio2_RSSI_ADC_CLAMP : out std_logic;
radio2_RSSI_ADC_HIZ : out std_logic;
radio2_RSSI_ADC_OTR : in std_logic;
radio2_RSSI_ADC_SLEEP : out std_logic;
radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio2_TX_DAC_PLL_LOCK : in std_logic;
radio2_TX_DAC_RESET : out std_logic;
radio2_RxHP_external : in std_logic;
radio2_TxGain : out std_logic_vector(0 to 5);
radio2_TxStart : out std_logic;
radio3_SHDN : out std_logic;
radio3_TxEn : out std_logic;
radio3_RxEn : out std_logic;
radio3_RxHP : out std_logic;
radio3_LD : in std_logic;
radio3_24PA : out std_logic;
radio3_5PA : out std_logic;
radio3_ANTSW : out std_logic_vector(0 to 1);
radio3_LED : out std_logic_vector(0 to 2);
radio3_ADC_RX_DCS : out std_logic;
radio3_ADC_RX_DFS : out std_logic;
radio3_ADC_RX_OTRA : in std_logic;
radio3_ADC_RX_OTRB : in std_logic;
radio3_ADC_RX_PWDNA : out std_logic;
radio3_ADC_RX_PWDNB : out std_logic;
radio3_DIPSW : in std_logic_vector(0 to 3);
radio3_RSSI_ADC_CLAMP : out std_logic;
radio3_RSSI_ADC_HIZ : out std_logic;
radio3_RSSI_ADC_OTR : in std_logic;
radio3_RSSI_ADC_SLEEP : out std_logic;
radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio3_TX_DAC_PLL_LOCK : in std_logic;
radio3_TX_DAC_RESET : out std_logic;
radio3_RxHP_external : in std_logic;
radio3_TxGain : out std_logic_vector(0 to 5);
radio3_TxStart : out std_logic;
radio4_SHDN : out std_logic;
radio4_TxEn : out std_logic;
radio4_RxEn : out std_logic;
radio4_RxHP : out std_logic;
radio4_LD : in std_logic;
radio4_24PA : out std_logic;
radio4_5PA : out std_logic;
radio4_ANTSW : out std_logic_vector(0 to 1);
radio4_LED : out std_logic_vector(0 to 2);
radio4_ADC_RX_DCS : out std_logic;
radio4_ADC_RX_DFS : out std_logic;
radio4_ADC_RX_OTRA : in std_logic;
radio4_ADC_RX_OTRB : in std_logic;
radio4_ADC_RX_PWDNA : out std_logic;
radio4_ADC_RX_PWDNB : out std_logic;
radio4_DIPSW : in std_logic_vector(0 to 3);
radio4_RSSI_ADC_CLAMP : out std_logic;
radio4_RSSI_ADC_HIZ : out std_logic;
radio4_RSSI_ADC_OTR : in std_logic;
radio4_RSSI_ADC_SLEEP : out std_logic;
radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
radio4_TX_DAC_PLL_LOCK : in std_logic;
radio4_TX_DAC_RESET : out std_logic;
radio4_RxHP_external : in std_logic;
radio4_TxGain : out std_logic_vector(0 to 5);
radio4_TxStart : out std_logic;
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity radio_controller;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of radio_controller is
------------------------------------------
-- Constant: array of address range identifiers
------------------------------------------
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00 -- user logic S/W register address space
);
------------------------------------------
-- Constant: array of address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');
constant USER_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_BASEADDR, -- user logic base address
ZERO_ADDR_PAD & USER_HIGHADDR -- user logic high address
);
------------------------------------------
-- Constant: array of data widths for each target address range
------------------------------------------
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic data width
);
------------------------------------------
-- Constant: array of desired number of chip enables for each address range
------------------------------------------
-- constant USER_NUM_CE : integer := 8;
constant USER_NUM_CE : integer := 16;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_CE) -- user logic number of CEs
);
------------------------------------------
-- Constant: array of unique properties for each address range
------------------------------------------
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic slave space dependent properties (none defined)
);
------------------------------------------
-- Constant: pipeline mode
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
-- Note:
-- only mode 4, 5, 7 are supported for this release
------------------------------------------
constant PIPELINE_MODEL : integer := 5;
------------------------------------------
-- Constant: user core ID code
------------------------------------------
constant DEV_BLK_ID : integer := 0;
------------------------------------------
-- Constant: enable MIR/Reset register
------------------------------------------
constant DEV_MIR_ENABLE : integer := 0;
------------------------------------------
-- Constant: array of IP interrupt mode
-- 1 = Active-high interrupt condition
-- 2 = Active-low interrupt condition
-- 3 = Active-high pulse interrupt event
-- 4 = Active-low pulse interrupt event
-- 5 = Positive-edge interrupt event
-- 6 = Negative-edge interrupt event
------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
------------------------------------------
-- Constant: enable device burst
------------------------------------------
constant DEV_BURST_ENABLE : integer := 0;
------------------------------------------
-- Constant: include address counter for burst transfers
------------------------------------------
constant INCLUDE_ADDR_CNTR : integer := 0;
------------------------------------------
-- Constant: include write buffer that decouples OPB and IPIC write transactions
------------------------------------------
constant INCLUDE_WR_BUF : integer := 0;
------------------------------------------
-- Constant: index for CS/CE
------------------------------------------
constant USER00_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_00);
constant USER00_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, USER00_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iBus2IP_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal iIP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal ZERO_IP2Bus_PostedWrInh : std_logic_vector(0 to ARD_ID_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_RDFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_WFIFO2IP_Data : std_logic_vector(0 to ARD_DWIDTH_ARRAY(get_id_index_iboe(ARD_ID_ARRAY, IPIF_WRFIFO_DATA))-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 16
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
spi_clk : out std_logic;
data_out : out std_logic;
Radio1_cs : out std_logic;
Radio2_cs : out std_logic;
Radio3_cs : out std_logic;
Radio4_cs : out std_logic;
Dac1_cs : out std_logic;
Dac2_cs : out std_logic;
Dac3_cs : out std_logic;
Dac4_cs : out std_logic;
Radio1_SHDN : out std_logic;
Radio1_TxEn : out std_logic;
Radio1_RxEn : out std_logic;
Radio1_RxHP : out std_logic;
Radio1_LD : in std_logic;
Radio1_24PA : out std_logic;
Radio1_5PA : out std_logic;
Radio1_ANTSW : out std_logic_vector(0 to 1);
Radio1_LED : out std_logic_vector(0 to 2);
Radio1_ADC_RX_DCS : out std_logic;
Radio1_ADC_RX_DFS : out std_logic;
Radio1_ADC_RX_OTRA : in std_logic;
Radio1_ADC_RX_OTRB : in std_logic;
Radio1_ADC_RX_PWDNA : out std_logic;
Radio1_ADC_RX_PWDNB : out std_logic;
Radio1_DIPSW : in std_logic_vector(0 to 3);
Radio1_RSSI_ADC_CLAMP : out std_logic;
Radio1_RSSI_ADC_HIZ : out std_logic;
Radio1_RSSI_ADC_OTR : in std_logic;
Radio1_RSSI_ADC_SLEEP : out std_logic;
Radio1_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio1_TX_DAC_PLL_LOCK : in std_logic;
Radio1_TX_DAC_RESET : out std_logic;
Radio1_RxHP_external : in std_logic;
Radio1_TxGain : out std_logic_vector(0 to 5);
Radio1_TxStart : out std_logic;
Radio2_SHDN : out std_logic;
Radio2_TxEn : out std_logic;
Radio2_RxEn : out std_logic;
Radio2_RxHP : out std_logic;
Radio2_LD : in std_logic;
Radio2_24PA : out std_logic;
Radio2_5PA : out std_logic;
Radio2_ANTSW : out std_logic_vector(0 to 1);
Radio2_LED : out std_logic_vector(0 to 2);
Radio2_ADC_RX_DCS : out std_logic;
Radio2_ADC_RX_DFS : out std_logic;
Radio2_ADC_RX_OTRA : in std_logic;
Radio2_ADC_RX_OTRB : in std_logic;
Radio2_ADC_RX_PWDNA : out std_logic;
Radio2_ADC_RX_PWDNB : out std_logic;
Radio2_DIPSW : in std_logic_vector(0 to 3);
Radio2_RSSI_ADC_CLAMP : out std_logic;
Radio2_RSSI_ADC_HIZ : out std_logic;
Radio2_RSSI_ADC_OTR : in std_logic;
Radio2_RSSI_ADC_SLEEP : out std_logic;
Radio2_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio2_TX_DAC_PLL_LOCK : in std_logic;
Radio2_TX_DAC_RESET : out std_logic;
Radio2_RxHP_external : in std_logic;
Radio2_TxGain : out std_logic_vector(0 to 5);
Radio2_TxStart : out std_logic;
Radio3_SHDN : out std_logic;
Radio3_TxEn : out std_logic;
Radio3_RxEn : out std_logic;
Radio3_RxHP : out std_logic;
Radio3_LD : in std_logic;
Radio3_24PA : out std_logic;
Radio3_5PA : out std_logic;
Radio3_ANTSW : out std_logic_vector(0 to 1);
Radio3_LED : out std_logic_vector(0 to 2);
Radio3_ADC_RX_DCS : out std_logic;
Radio3_ADC_RX_DFS : out std_logic;
Radio3_ADC_RX_OTRA : in std_logic;
Radio3_ADC_RX_OTRB : in std_logic;
Radio3_ADC_RX_PWDNA : out std_logic;
Radio3_ADC_RX_PWDNB : out std_logic;
Radio3_DIPSW : in std_logic_vector(0 to 3);
Radio3_RSSI_ADC_CLAMP : out std_logic;
Radio3_RSSI_ADC_HIZ : out std_logic;
Radio3_RSSI_ADC_OTR : in std_logic;
Radio3_RSSI_ADC_SLEEP : out std_logic;
Radio3_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio3_TX_DAC_PLL_LOCK : in std_logic;
Radio3_TX_DAC_RESET : out std_logic;
Radio3_RxHP_external : in std_logic;
Radio3_TxGain : out std_logic_vector(0 to 5);
Radio3_TxStart : out std_logic;
Radio4_SHDN : out std_logic;
Radio4_TxEn : out std_logic;
Radio4_RxEn : out std_logic;
Radio4_RxHP : out std_logic;
Radio4_LD : in std_logic;
Radio4_24PA : out std_logic;
Radio4_5PA : out std_logic;
Radio4_ANTSW : out std_logic_vector(0 to 1);
Radio4_LED : out std_logic_vector(0 to 2);
Radio4_ADC_RX_DCS : out std_logic;
Radio4_ADC_RX_DFS : out std_logic;
Radio4_ADC_RX_OTRA : in std_logic;
Radio4_ADC_RX_OTRB : in std_logic;
Radio4_ADC_RX_PWDNA : out std_logic;
Radio4_ADC_RX_PWDNB : out std_logic;
Radio4_DIPSW : in std_logic_vector(0 to 3);
Radio4_RSSI_ADC_CLAMP : out std_logic;
Radio4_RSSI_ADC_HIZ : out std_logic;
Radio4_RSSI_ADC_OTR : in std_logic;
Radio4_RSSI_ADC_SLEEP : out std_logic;
Radio4_RSSI_ADC_D : in std_logic_vector(0 to 9);
Radio4_TX_DAC_PLL_LOCK : in std_logic;
Radio4_TX_DAC_RESET : out std_logic;
Radio4_RxHP_external : in std_logic;
Radio4_TxGain : out std_logic_vector(0 to 5);
Radio4_TxStart : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v3_01_c.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sl_DBus,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_retry => Sl_retry,
Sln_toutSup => Sl_toutSup,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_AddrAck => '0',
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => ZERO_IP2Bus_PostedWrInh,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => ZERO_WFIFO2IP_Data,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
Freeze => '0',
Bus2IP_Freeze => open,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => iBus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => iBus2IP_Reset
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_DWIDTH => USER_DWIDTH,
C_NUM_CE => USER_NUM_CE
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
spi_clk => spi_clk,
data_out => data_out,
Radio1_cs => radio1_cs,
Radio2_cs => radio2_cs,
Radio3_cs => radio3_cs,
Radio4_cs => radio4_cs,
Dac1_cs => dac1_cs,
Dac2_cs => dac2_cs,
Dac3_cs => dac3_cs,
Dac4_cs => dac4_cs,
Radio1_SHDN => radio1_SHDN,
Radio1_TxEn => radio1_TxEn,
Radio1_RxEn => radio1_RxEn,
Radio1_RxHP => radio1_RxHP,
Radio1_LD => radio1_LD,
Radio1_24PA => radio1_24PA,
Radio1_5PA => radio1_5PA,
Radio1_ANTSW => radio1_ANTSW,
Radio1_LED => radio1_LED,
Radio1_ADC_RX_DCS => radio1_ADC_RX_DCS,
Radio1_ADC_RX_DFS => radio1_ADC_RX_DFS,
Radio1_ADC_RX_OTRA => radio1_ADC_RX_OTRA,
Radio1_ADC_RX_OTRB => radio1_ADC_RX_OTRB,
Radio1_ADC_RX_PWDNA => radio1_ADC_RX_PWDNA,
Radio1_ADC_RX_PWDNB => radio1_ADC_RX_PWDNB,
Radio1_DIPSW => radio1_DIPSW,
Radio1_RSSI_ADC_CLAMP => radio1_RSSI_ADC_CLAMP,
Radio1_RSSI_ADC_HIZ => radio1_RSSI_ADC_HIZ,
Radio1_RSSI_ADC_OTR => radio1_RSSI_ADC_OTR,
Radio1_RSSI_ADC_SLEEP => radio1_RSSI_ADC_SLEEP,
Radio1_RSSI_ADC_D => radio1_RSSI_ADC_D,
Radio1_TX_DAC_PLL_LOCK => radio1_TX_DAC_PLL_LOCK,
Radio1_TX_DAC_RESET => radio1_TX_DAC_RESET,
Radio1_RxHP_external => radio1_RxHP_external,
Radio1_TxGain => radio1_TxGain,
Radio1_TxStart => radio1_TxStart,
Radio2_SHDN => radio2_SHDN,
Radio2_TxEn => radio2_TxEn,
Radio2_RxEn => radio2_RxEn,
Radio2_RxHP => radio2_RxHP,
Radio2_LD => radio2_LD,
Radio2_24PA => radio2_24PA,
Radio2_5PA => radio2_5PA,
Radio2_ANTSW => radio2_ANTSW,
Radio2_LED => radio2_LED,
Radio2_ADC_RX_DCS => radio2_ADC_RX_DCS,
Radio2_ADC_RX_DFS => radio2_ADC_RX_DFS,
Radio2_ADC_RX_OTRA => radio2_ADC_RX_OTRA,
Radio2_ADC_RX_OTRB => radio2_ADC_RX_OTRB,
Radio2_ADC_RX_PWDNA => radio2_ADC_RX_PWDNA,
Radio2_ADC_RX_PWDNB => radio2_ADC_RX_PWDNB,
Radio2_DIPSW => radio2_DIPSW,
Radio2_RSSI_ADC_CLAMP => radio2_RSSI_ADC_CLAMP,
Radio2_RSSI_ADC_HIZ => radio2_RSSI_ADC_HIZ,
Radio2_RSSI_ADC_OTR => radio2_RSSI_ADC_OTR,
Radio2_RSSI_ADC_SLEEP => radio2_RSSI_ADC_SLEEP,
Radio2_RSSI_ADC_D => radio2_RSSI_ADC_D,
Radio2_TX_DAC_PLL_LOCK => radio2_TX_DAC_PLL_LOCK,
Radio2_TX_DAC_RESET => radio2_TX_DAC_RESET,
Radio2_RxHP_external => radio2_RxHP_external,
Radio2_TxGain => radio2_TxGain,
Radio2_TxStart => radio2_TxStart,
Radio3_SHDN => radio3_SHDN,
Radio3_TxEn => radio3_TxEn,
Radio3_RxEn => radio3_RxEn,
Radio3_RxHP => radio3_RxHP,
Radio3_LD => radio3_LD,
Radio3_24PA => radio3_24PA,
Radio3_5PA => radio3_5PA,
Radio3_ANTSW => radio3_ANTSW,
Radio3_LED => radio3_LED,
Radio3_ADC_RX_DCS => radio3_ADC_RX_DCS,
Radio3_ADC_RX_DFS => radio3_ADC_RX_DFS,
Radio3_ADC_RX_OTRA => radio3_ADC_RX_OTRA,
Radio3_ADC_RX_OTRB => radio3_ADC_RX_OTRB,
Radio3_ADC_RX_PWDNA => radio3_ADC_RX_PWDNA,
Radio3_ADC_RX_PWDNB => radio3_ADC_RX_PWDNB,
Radio3_DIPSW => radio3_DIPSW,
Radio3_RSSI_ADC_CLAMP => radio3_RSSI_ADC_CLAMP,
Radio3_RSSI_ADC_HIZ => radio3_RSSI_ADC_HIZ,
Radio3_RSSI_ADC_OTR => radio3_RSSI_ADC_OTR,
Radio3_RSSI_ADC_SLEEP => radio3_RSSI_ADC_SLEEP,
Radio3_RSSI_ADC_D => radio3_RSSI_ADC_D,
Radio3_TX_DAC_PLL_LOCK => radio3_TX_DAC_PLL_LOCK,
Radio3_TX_DAC_RESET => radio3_TX_DAC_RESET,
Radio3_RxHP_external => radio3_RxHP_external,
Radio3_TxGain => radio3_TxGain,
Radio3_TxStart => radio3_TxStart,
Radio4_SHDN => radio4_SHDN,
Radio4_TxEn => radio4_TxEn,
Radio4_RxEn => radio4_RxEn,
Radio4_RxHP => radio4_RxHP,
Radio4_LD => radio4_LD,
Radio4_24PA => radio4_24PA,
Radio4_5PA => radio4_5PA,
Radio4_ANTSW => radio4_ANTSW,
Radio4_LED => radio4_LED,
Radio4_ADC_RX_DCS => radio4_ADC_RX_DCS,
Radio4_ADC_RX_DFS => radio4_ADC_RX_DFS,
Radio4_ADC_RX_OTRA => radio4_ADC_RX_OTRA,
Radio4_ADC_RX_OTRB => radio4_ADC_RX_OTRB,
Radio4_ADC_RX_PWDNA => radio4_ADC_RX_PWDNA,
Radio4_ADC_RX_PWDNB => radio4_ADC_RX_PWDNB,
Radio4_DIPSW => radio4_DIPSW,
Radio4_RSSI_ADC_CLAMP => radio4_RSSI_ADC_CLAMP,
Radio4_RSSI_ADC_HIZ => radio4_RSSI_ADC_HIZ,
Radio4_RSSI_ADC_OTR => radio4_RSSI_ADC_OTR,
Radio4_RSSI_ADC_SLEEP => radio4_RSSI_ADC_SLEEP,
Radio4_RSSI_ADC_D => radio4_RSSI_ADC_D,
Radio4_TX_DAC_PLL_LOCK => radio4_TX_DAC_PLL_LOCK,
Radio4_TX_DAC_RESET => radio4_TX_DAC_RESET,
Radio4_RxHP_external => radio4_RxHP_external,
Radio4_TxGain => radio4_TxGain,
Radio4_TxStart => radio4_TxStart,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Ack => iIP2Bus_Ack,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_RdCE <= iBus2IP_RdCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE <= iBus2IP_WrCE(USER00_CE_INDEX to USER00_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
end IMP;
| bsd-2-clause | 7293cd231c6e164e0ca11de207799254 | 0.433285 | 3.945868 | false | false | false | false |
Andy46/OV7670-VHDL | OV7670/src/mod_VGA/mod_VGA.vhd | 1 | 4,153 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:32:02 05/05/2014
-- Design Name:
-- Module Name: mod_VGA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mod_VGA is
Port ( clk_100MHz, reset : in STD_LOGIC; -- FPGA's clock, FPGA's reset(Active Low)
-- VGA pins --
vga_vsync, vga_hsync : out STD_LOGIC; -- VGA Vertical synchronization, VGA Horizontal synchronization
vga_red, vga_green, vga_blue : out STD_LOGIC_VECTOR(3 downto 0) -- VGA colors (4bits)
-- vga_red, vga_green, vga_blue : out STD_LOGIC; -- VGA colors (1bit)
-- VGA pins --
);
end mod_VGA;
architecture Behavioral of mod_VGA is
--Divisor de frecuencia
component Divisor4 is
Port ( clk_in, reset : in std_logic;
clk_out : out std_logic);
end component;
signal clk_25MHz : std_logic;
--Contadores vertical y horizontal
component contador10bits is
Port ( A : in STD_LOGIC_VECTOR (9 downto 0);
A_next : out STD_LOGIC_VECTOR (9 downto 0));
end component;
--Señales
signal Vcount, Vcount_next : std_logic_vector(9 downto 0);
signal Hcount, Hcount_next : std_logic_vector(9 downto 0);
--Imagen
component mod_Image is
Port ( clk_100MHz, reset : in STD_LOGIC;
readX, readY : in STD_LOGIC_VECTOR (9 downto 0); -- Pixel read addr(row, column)
vga_red, vga_green, vga_blue : out STD_LOGIC_VECTOR (3 downto 0); -- Pixel read color
writeX, writeY : in std_logic_vector (9 downto 0); -- Pixel write addr(row, column)
pixel : in std_logic_vector(7 downto 0) -- Pixel write color
);
end component;
begin
--Divisor de frecuencia 1/4
Div_VGA: Divisor4 port map(clk_in => clk_100MHz, reset => reset, clk_out => clk_25MHz);
--Asignar colores
Im: mod_Image port map( clk_100MHz => clk_100MHz, reset => reset, readX => Hcount, readY => Vcount,
vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue,
writeX => std_logic_vector(to_unsigned(640, 10)), writeY =>std_logic_vector(to_unsigned(480,10)),
pixel => "00000011" );
--Process VSYNC
FA_Vsync: contador10bits port map(A => Vcount, A_next => Vcount_next);
process(clk_25MHz, reset, Hcount, Vcount)
begin
if clk_25MHz'event and clk_25MHz = '1' then
if reset = '0' then
Vcount <= (others => '0');
vga_vsync <= '0';
else
if Hcount = std_logic_vector(to_unsigned(800, 10)) then -- 1040 | 800 | 800
if Vcount = std_logic_vector(to_unsigned(525, 10)) then -- 665 | 525 | 448
Vcount <= (others => '0');
else
Vcount <= Vcount_next;
end if;
if Vcount >= std_logic_vector(to_unsigned(490, 10)) and Vcount < std_logic_vector(to_unsigned(492, 10)) then -- 636,642 | 490,492 | 386,388
vga_vsync <= '1';
else
vga_vsync <= '0';
end if;
end if;
end if;
end if;
end process;
--Process HSYNC
FA_Hsync: contador10bits port map(A => Hcount, A_next => Hcount_next);
process(clk_25MHz, reset)
begin
if clk_25MHz'event and clk_25MHz = '1' then
if reset = '0' then
Hcount <= (others => '0');
vga_hsync <= '0';
else
if Hcount = std_logic_vector(to_unsigned(800, 10)) then -- 1040 | 800 | 800
Hcount <= (others => '0');
else
Hcount <= Hcount_next;
end if;
if Hcount >= std_logic_vector(to_unsigned(656, 10)) and Hcount < std_logic_vector(to_unsigned(752, 10)) then -- 855, 975 | 656,752 | 656,752
vga_hsync <= '1';
else
vga_hsync <= '0';
end if;
end if;
end if;
end process;
end Behavioral; | mit | 121b303731abe059db96f6c1e8dddea5 | 0.607659 | 3.208655 | false | false | false | false |
inmcm/Simon_Speck_Ciphers | VHDL/AXI_IP/Speck_Block_Cipher_1.0/hdl/Speck_Block_Cipher_v1_0_S00_AXI.vhd | 1 | 26,309 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Speck_Block_Cipher_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
-- Cipher Block Input
SLV_REG00_OUT : out std_logic_vector(31 downto 0);
SLV_REG01_OUT : out std_logic_vector(31 downto 0);
SLV_REG02_OUT : out std_logic_vector(31 downto 0);
SLV_REG03_OUT : out std_logic_vector(31 downto 0);
-- Cipher Key Input
SLV_REG04_OUT : out std_logic_vector(31 downto 0);
SLV_REG05_OUT : out std_logic_vector(31 downto 0);
SLV_REG06_OUT : out std_logic_vector(31 downto 0);
SLV_REG07_OUT : out std_logic_vector(31 downto 0);
SLV_REG08_OUT : out std_logic_vector(31 downto 0);
SLV_REG09_OUT : out std_logic_vector(31 downto 0);
SLV_REG10_OUT : out std_logic_vector(31 downto 0);
SLV_REG11_OUT : out std_logic_vector(31 downto 0);
-- Cipher Control/Rest Register
SLV_REG12_OUT : out std_logic_vector(31 downto 0);
-- Cipher Block Output
SLV_REG13_IN : in std_logic_vector(31 downto 0);
SLV_REG14_IN : in std_logic_vector(31 downto 0);
SLV_REG15_IN : in std_logic_vector(31 downto 0);
SLV_REG16_IN : in std_logic_vector(31 downto 0);
-- Cipher Status Output
SLV_REG17_IN : in std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end Speck_Block_Cipher_v1_0_S00_AXI;
architecture arch_imp of Speck_Block_Cipher_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 14
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= slv_reg0;
when b"00001" =>
reg_data_out <= slv_reg1;
when b"00010" =>
reg_data_out <= slv_reg2;
when b"00011" =>
reg_data_out <= slv_reg3;
when b"00100" =>
reg_data_out <= slv_reg4;
when b"00101" =>
reg_data_out <= slv_reg5;
when b"00110" =>
reg_data_out <= slv_reg6;
when b"00111" =>
reg_data_out <= slv_reg7;
when b"01000" =>
reg_data_out <= slv_reg8;
when b"01001" =>
reg_data_out <= slv_reg9;
when b"01010" =>
reg_data_out <= slv_reg10;
when b"01011" =>
reg_data_out <= slv_reg11;
when b"01100" =>
reg_data_out <= slv_reg12;
when b"01101" =>
reg_data_out <= SLV_REG13_IN;
when b"01110" =>
reg_data_out <= SLV_REG14_IN;
when b"01111" =>
reg_data_out <= SLV_REG15_IN;
when b"10000" =>
reg_data_out <= SLV_REG16_IN;
when b"10001" =>
reg_data_out <= SLV_REG17_IN;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
SLV_REG00_OUT <= slv_reg0;
SLV_REG01_OUT <= slv_reg1;
SLV_REG02_OUT <= slv_reg2;
SLV_REG03_OUT <= slv_reg3;
SLV_REG04_OUT <= slv_reg4;
SLV_REG05_OUT <= slv_reg5;
SLV_REG06_OUT <= slv_reg6;
SLV_REG07_OUT <= slv_reg7;
SLV_REG08_OUT <= slv_reg8;
SLV_REG09_OUT <= slv_reg9;
SLV_REG10_OUT <= slv_reg10;
SLV_REG11_OUT <= slv_reg11;
SLV_REG12_OUT <= slv_reg12;
-- User logic ends
end arch_imp;
| mit | 5c31d7e424fbd0544a219f7b5b7bf38d | 0.567106 | 3.47497 | false | false | false | false |
timvideos/HDMI2USB-jahanzeb-firmware | ipcore_dir/cmdfifo/simulation/cmdfifo_pctrl.vhd | 3 | 20,685 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF cmdfifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
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`protect end_protected
| gpl-3.0 | be89bfd9a8a1b74c1f8f8ecbafd9e96d | 0.955798 | 1.807425 | false | false | false | false |
ymei/TMSPlane | Firmware/src/byte2cmd.vhd | 2 | 3,261 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Yuan Mei
--
-- Create Date: 23:56:58 10/26/2013
-- Design Name: Convert byte stream into command
-- Module Name: byte2cmd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY byte2cmd IS
PORT (
CLK : IN std_logic;
RESET : IN std_logic;
-- byte in
RX_DATA : IN std_logic_vector(7 DOWNTO 0);
RX_RDY : IN std_logic;
-- cmd out
CMD_FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); -- command fifo data out port
CMD_FIFO_EMPTY : OUT std_logic; -- command fifo "emtpy" SIGNAL
CMD_FIFO_RDCLK : IN std_logic;
CMD_FIFO_RDREQ : IN std_logic -- command fifo read request
);
END byte2cmd;
ARCHITECTURE Behavioral OF byte2cmd IS
COMPONENT fifo36x512
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(35 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(35 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
SIGNAL sCmdFifoWrClk : std_logic;
SIGNAL sCmdFifoD : std_logic_vector(39 DOWNTO 0);
SIGNAL sCmdFifoWrreq : std_logic;
SIGNAL sCmdFifoFull : std_logic;
SIGNAL sInByte : std_logic_vector(7 DOWNTO 0);
TYPE cmdState_t IS (S0, S1);
SIGNAL cmdState : cmdState_t;
BEGIN
-- cmd FIFO
sCmdFifoWrClk <= CLK;
cmd_fifo : fifo36x512
PORT MAP (
rst => RESET,
wr_clk => sCmdFifoWrClk,
rd_clk => CMD_FIFO_RDCLK,
din => sCmdFifoD(35 DOWNTO 0),
wr_en => sCmdFifoWrreq,
rd_en => CMD_FIFO_RDREQ,
dout => CMD_FIFO_Q,
full => sCmdFifoFull,
empty => CMD_FIFO_EMPTY
);
PROCESS (CLK, RESET) IS
VARIABLE addri : integer RANGE 0 TO 7 :=0;
BEGIN
IF RESET = '1' THEN
addri := 0;
sCmdFifoD <= (OTHERS => '0');
sCmdFifoWrreq <= '0';
sInByte <= x"ff";
cmdState <= S0;
ELSIF falling_edge(CLK) THEN
CASE cmdState IS
WHEN S0 =>
sCmdFifoWrreq <= '0';
IF RX_RDY = '1' THEN
sInByte <= RX_DATA;
addri := to_integer(unsigned(sInByte(7 DOWNTO 5)));
sCmdFifoD((addri+1)*5-1 DOWNTO addri*5) <= sInByte(4 DOWNTO 0);
IF addri = 0 THEN
cmdState <= S1;
END IF;
END IF;
WHEN S1 =>
sCmdFifoWrreq <= '1';
cmdState <= S0;
WHEN OTHERS =>
cmdState <= S0;
END CASE;
END IF;
END PROCESS;
END Behavioral;
| bsd-3-clause | dce1a1961342322d113372c6e17123b7 | 0.546765 | 3.611296 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_output_block.vhd | 9 | 17,048 | `protect begin_protected
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`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect end_protected
| gpl-3.0 | 507b89280e141effa7137b2071af1f66 | 0.937353 | 1.86012 | false | false | false | false |
Given-Jiang/Gray_Processing | tb_Gray_Processing/hdl/alt_dspbuilder_delay_GNVTJPHWYT.vhd | 9 | 1,102 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNVTJPHWYT is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "01111111";
width : positive := 8);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNVTJPHWYT is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 8,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "01111111")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; | mit | f11f4e69ebbc672d6f3497218af9694a | 0.634301 | 3.061111 | false | false | false | false |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_Xilinx_Port/uart.vhd | 4 | 3,858 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:16:44 05/29/2011
-- Design Name:
-- Module Name: uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart is
Port ( clk : in STD_LOGIC;
tx : out STD_LOGIC;
rx : in STD_LOGIC;
txdata : in STD_LOGIC_VECTOR (48 downto 0);
txwidth : in STD_LOGIC_VECTOR (5 downto 0);
txstrobe : in STD_LOGIC;
txbusy : out STD_LOGIC;
rxdata : out STD_LOGIC_VECTOR (7 downto 0);
rxstrobe : out STD_LOGIC);
end uart;
architecture Behavioral of uart is
signal txclk : std_logic := '0';
signal rxclk : std_logic := '0';
signal txclkdiv : std_logic_vector(10 downto 0);
signal rxclkdiv : std_logic_vector(10 downto 0);
signal txclksync : std_logic := '0';
signal rxclksync : std_logic := '0';
signal txdatabuf : std_logic_vector(48 downto 0) := "0000000000000000000000000000000000000000000000000";
signal txdataleft : std_logic_vector(5 downto 0) := "000000";
signal txbusy_src : std_logic := '0';
signal rxdata_src : std_logic_vector(7 downto 0);
signal rxbits : std_logic_vector(3 downto 0);
signal rxbusy : std_logic := '0';
signal rx1 : std_logic;
signal rx2 : std_logic;
begin
tx <= txdatabuf(0);
txclk <= '1' when txclkdiv = "00000000000" and txclksync = '0' else '0';
rxclk <= '1' when rxclkdiv = "00000000000" and rxclksync = '0' else '0';
txbusy_src <= '0' when txdataleft = "000000" else '1';
txbusy <= txbusy_src;
rxdata <= rxdata_src;
process(clk)
begin
if rising_edge(clk) then
rx1 <= rx;
rx2 <= rx1;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if txclksync = '1' or txclkdiv = "00000000000" then
txclkdiv <= "10000010001";
else
txclkdiv <= txclkdiv - 1;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rxclksync = '1' then
rxclkdiv <= "11000011001";
elsif rxclkdiv = "00000000000000" then
rxclkdiv <= "10000010001";
else
rxclkdiv <= rxclkdiv - 1;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if txstrobe = '1' and txbusy_src = '0' then
txdatabuf <= txdata;
txdataleft <= txwidth;
txclksync <= '1';
else
if txclk = '1' then
txdatabuf(47 downto 0) <= txdatabuf(48 downto 1);
txdatabuf(48) <= '1';
if txbusy_src = '1' then
txdataleft <= txdataleft - 1;
end if;
end if;
txclksync <= '0';
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rxbusy = '1' then
if rxclk = '1' then
if rxbits = "1000" then
rxbusy <= '0';
rxstrobe <= '1';
else
rxdata_src(6 downto 0) <= rxdata_src(7 downto 1);
rxdata_src(7) <= rx2;
rxbits <= rxbits + 1;
rxbusy <= '1';
rxstrobe <= '0';
end if;
end if;
rxclksync <= '0';
elsif rx2 = '0' then
rxbits <= "0000";
rxbusy <= '1';
rxclksync <= '1';
rxstrobe <= '0';
else
rxbusy <= '0';
rxclksync <= '0';
rxstrobe <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 2b2c402c13e6dd7a73b67af1c5f9cbc0 | 0.588388 | 3.121359 | false | false | false | false |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/fifo_64x18.vhd | 4 | 5,459 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_64x18.vhd when simulating
-- the core, fifo_64x18. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY fifo_64x18 IS
port (
din: IN std_logic_VECTOR(17 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(17 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
END fifo_64x18;
ARCHITECTURE fifo_64x18_a OF fifo_64x18 IS
-- synopsys translate_off
component wrapped_fifo_64x18
port (
din: IN std_logic_VECTOR(17 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(17 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_64x18 use entity XilinxCoreLib.fifo_generator_v2_3(behavioral)
generic map(
c_wr_response_latency => 1,
c_has_rd_data_count => 0,
c_din_width => 18,
c_has_wr_data_count => 0,
c_implementation_type => 2,
c_family => "virtex2p",
c_has_wr_rst => 0,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 18,
c_rd_depth => 64,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 1,
c_has_rst => 1,
c_data_count_width => 2,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 6,
c_has_almost_empty => 1,
c_rd_data_count_width => 2,
c_enable_rlocs => 0,
c_wr_pntr_width => 6,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 2,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 62,
c_wr_depth => 64,
c_prog_empty_thresh_negate_val => 62,
c_prog_empty_thresh_assert_val => 62,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 62,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => 512,
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 2);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_fifo_64x18
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
almost_empty => almost_empty,
almost_full => almost_full,
dout => dout,
empty => empty,
full => full);
-- synopsys translate_on
END fifo_64x18_a;
| bsd-2-clause | bb34dd9048272d28d1f57bd29fd9f7d1 | 0.566587 | 3.542505 | false | false | false | false |
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