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J-Rios/VHDL_Modules | 2.Secuencial/Register.vhd | 1 | 1,071 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-------------------------------------------------------------------------
entity REG is
Generic
(
BITS : INTEGER := 4
);
Port
(
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (BITS-1 downto 0);
Q : inout STD_LOGIC_VECTOR (BITS-1 downto 0);
Qn : inout STD_LOGIC_VECTOR (BITS-1 downto 0)
);
end REG;
-------------------------------------------------------------------------
architecture Behavioral of REG is
begin
-- One option
process(CLK, CLR)
begin
if (CLK'event and CLK = '1') then
if (CLR = '1') then
Q <= D;
Qn <= not(D);
else
Q <= (others => '0');
Qn <= (others => '1');
end if;
end if;
end process;
-- Other option
-- process
-- begin
-- wait until rising_edge(CLK);
-- if (CLR = '1') then
-- Q <= D;
-- Qn <= not(D);
-- else
-- Q <= (others => '0');
-- Qn <= (others => '1');
-- end if;
-- end process;
end Behavioral;
| gpl-3.0 | dc2e7a5b9b5a881a98f82f41633c87db | 0.416433 | 3.421725 | false | false | false | false |
J-Rios/VHDL_Modules | 2.Secuencial/Counter.vhd | 1 | 2,376 | ----------------------------------------------------------------------------------
-- ------------------- --
-- | | --
-- RST ---------| RST | --
-- | Q |--------- Q[BITS-1:0] --
-- CE ---------| CE | --
-- | | --
-- | | --
-- CLK ---------| CLK TC |--------- TC --
-- | | --
-- ------------------- --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
----------------------------------------------------------------------------------
entity COUNTER is
Generic
(
BITS : INTEGER := 4
);
Port
(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE : in STD_LOGIC;
TC : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR (BITS-1 downto 0)
);
end COUNTER;
----------------------------------------------------------------------------------
architecture Behavioral of COUNTER is
signal Qr : UNSIGNED (BITS-1 downto 0);
signal Qn : UNSIGNED (BITS-1 downto 0);
signal TCsignal : STD_LOGIC;
begin
process(RST, CLK, CE)
begin
if (CLK'event and CLK = '1') then -- Rising clock
if (CE = '1') then -- Clock enable active
if (RST = '1') then -- Reset active
Qr <= (others => '0'); -- Reset the count to zero
else
Qr <= Qn; -- Set the count
end if;
end if;
end if;
end process;
-- Next state logic
Qn <= Qr + 1; -- Increase the count
-- Output logic
Q <= std_logic_vector(Qr); -- Output vector
TC <= '1' when Qr = (2**BITS-1) else '0'; -- Tick-Count bit (End-count)
TCsignal <= TC;
CEO <= '1' when (TCsignal = '1' and CE = '1') else '0'; -- Clock Enable Out
end Behavioral;
| gpl-3.0 | 36504d9d77a180c452081889cada63d3 | 0.284933 | 5.12069 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue2/Mini-ALU/ALU.vhd | 1 | 1,598 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:53 06/12/2016
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( OP_A : in STD_LOGIC_VECTOR (3 downto 1);
OP_B : in STD_LOGIC_VECTOR (3 downto 1);
O : in STD_LOGIC_VECTOR (2 downto 1);
R : out STD_LOGIC_VECTOR (4 downto 1));
end ALU;
architecture Behavioral of ALU is
signal Zw : STD_LOGIC_VECTOR(3 downto 1);
signal Sum : STD_LOGIC_VECTOR(4 downto 1);
signal yu, yw : STD_LOGIC;
begin
operate: process(OP_A,OP_B,O)
begin
Sum <= ('0' & OP_A) + ('0' & OP_B);
Zw <= (not OP_A) + "001";
if OP_A = OP_B then yu <= '1'; else yu <= '0'; end if;
if OP_A > OP_B then yw <= '1'; else yw <= '0'; end if;
case O is
when "00" => R <= Sum;
when "01" => R <= ('0' & Zw);
when others => R <= ("00" & yu & yw);
end case;
end process operate;
end Behavioral;
| mit | f351938e8dae944d97db649457fad2af | 0.556946 | 3.267894 | false | false | false | false |
shaolinbertrand/Processador_N.I.N.A | ULA.vhd | 1 | 665 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ULA is port(
x,y : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
selection : in std_logic_vector(2 downto 0)
);
end ULA;
architecture hardware of ULA is begin
process(x,y,selection)
begin
case selection is
when "000" => s <= x or y;
when "001" => s <= x XOR y;
when "010" => s <= x - y;
when "011" => s <= x + y;
when "100" => s <= x AND y;
when "101" => s <= not y;
when "110" => s <= not x;
when others=>s <= "ZZZZ";
end case;
end process;
end hardware;
| gpl-3.0 | 6086c70ad5fe3a50fe3d718eefecccdc | 0.541353 | 2.942478 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue1/Latch/Schnappschloss.vhd | 1 | 1,174 | -- Pegelgetaktetes D-FF mit Reset
-- Automatenebene, 2-Prozess-Variante
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PDFF_R_RK is
Port ( c : in bit;
D: in bit;
R: in bit; -- Reset
y: out bit;
ny : out bit
);
end PDFF_R_RK;
--
-- Reset via RK ------------------------------------------------------------
--
architecture Automatenspek of PDFF_R_RK is
type Zustaende is (Za, Zb); -- Aufzhlungstyp
signal Z, Z_folge : Zustaende;
signal X : bit_vector (1 downto 0);
signal yInt : bit;
begin
-- Zustandsberfhrungs- und Ausgabefunktion
X <= (c,D);
Delta: process (X,Z)
begin
case Z is
when Za => yInt <= '0';
if X = "11" then Z_folge <= Zb;
else Z_folge <= Za;
end if;
when Zb => yInt <= '1';
if X = "10" then Z_folge <= Za;
else Z_folge <= Zb;
end if;
end case;
end process Delta;
-- RK (direkte Rckfhrung):
RK: process (Z_folge, R)
begin
if R = '1' then Z <= Za ;
else Z <= Z_folge;
end if;
end process RK;
y <= yInt;
-- inv. Ausgang:
ny <= not yInt;
end Automatenspek; | mit | 258f32f26280937e4af31329eb0c0266 | 0.505111 | 2.711316 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Controllori_Audio/I2C_Controller.vhd | 1 | 7,373 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo I2C_Controller.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Modulo che si occupa della comunicazione con il chip audio
-- e i registri di controllo utilizzando il protocollo I2C.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity I2C_Controller is generic (
I2C_BUS_MODE: std_logic := '0'
);
port (
clk: in std_logic;
reset: in std_logic;
clear_ack: in std_logic;
clk_400KHz: in std_logic;
start_and_stop_en: in std_logic;
change_output_bit_en: in std_logic;
send_start_bit: in std_logic;
send_stop_bit: in std_logic;
data_in: in std_logic_vector(7 downto 0);
transfer_data: in std_logic;
read_byte: in std_logic;
num_bits_to_transfer: in integer; -- std_logic_vector(2 downto 0);
i2c_sdata: inout std_logic; -- I2C Data
i2c_sclk: out std_logic; -- I2C Clock
i2c_scen: out std_logic;
enable_clk: out std_logic;
ack: out std_logic;
data_from_i2c: buffer std_logic_vector(7 downto 0);
transfer_complete: out std_logic
);
end I2C_Controller;
architecture behaviour of I2C_Controller is
-- Stati della FSM
constant I2C_STATE_0_IDLE: std_logic_vector (2 downto 0) := "000";
constant I2C_STATE_1_PRE_START: std_logic_vector (2 downto 0) := "001";
constant I2C_STATE_2_START_BIT: std_logic_vector (2 downto 0) := "010";
constant I2C_STATE_3_TRANSFER_BYTE: std_logic_vector (2 downto 0) := "011";
constant I2C_STATE_4_TRANSFER_ACK: std_logic_vector (2 downto 0) := "100";
constant I2C_STATE_5_STOP_BIT: std_logic_vector (2 downto 0) := "101";
constant I2C_STATE_6_COMPLETE: std_logic_vector (2 downto 0) := "110";
signal current_bit: integer; --std_logic_vector (2 downto 0);
signal current_byte: std_logic_vector (7 downto 0);
signal ns_i2c_transceiver: std_logic_vector (2 downto 0);
signal s_i2c_transceiver: std_logic_vector (2 downto 0);
-- Segnali buffer
signal buff1: std_logic;
signal buff2: std_logic;
begin
buff1 <= '0' when s_i2c_transceiver = I2C_STATE_0_IDLE else '1';
buff2 <= '0' when s_i2c_transceiver = I2C_STATE_6_COMPLETE else '1';
i2c_sclk <= clk_400KHz when I2C_BUS_MODE = '0' else
clk_400KHz when ((s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE)
or (s_i2c_transceiver = I2C_STATE_4_TRANSFER_ACK))
else '0';
i2c_sdata <=
'0' when (s_i2c_transceiver = I2C_STATE_2_START_BIT) else
'0' when (s_i2c_transceiver = I2C_STATE_5_STOP_BIT) else
'0' when ((s_i2c_transceiver = I2C_STATE_4_TRANSFER_ACK) and read_byte='1') else
current_byte(current_bit) when ((s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE) and read_byte='0') else
'Z';
enable_clk <= buff1 and buff2;
transfer_complete <= '1' when (s_i2c_transceiver = I2C_STATE_6_COMPLETE) else '0';
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
s_i2c_transceiver <= I2C_STATE_0_IDLE;
else
s_i2c_transceiver <= ns_i2c_transceiver;
end if;
end if;
end process;
process(all)
begin
ns_i2c_transceiver <= I2C_STATE_0_IDLE;
if s_i2c_transceiver = I2C_STATE_0_IDLE then
if ((send_start_bit = '1') and (clk_400KHz = '0')) then
ns_i2c_transceiver <= I2C_STATE_1_PRE_START;
elsif (send_start_bit = '1') then
ns_i2c_transceiver <= I2C_STATE_2_START_BIT;
elsif (send_stop_bit = '1') then
ns_i2c_transceiver <= I2C_STATE_5_STOP_BIT;
elsif (transfer_data = '1') then
ns_i2c_transceiver <= I2C_STATE_3_TRANSFER_BYTE;
else
ns_i2c_transceiver <= I2C_STATE_0_IDLE;
end if;
elsif s_i2c_transceiver = I2C_STATE_1_PRE_START then
if (start_and_stop_en = '1') then
ns_i2c_transceiver <= I2C_STATE_2_START_BIT;
else
ns_i2c_transceiver <= I2C_STATE_1_PRE_START;
end if;
elsif s_i2c_transceiver = I2C_STATE_2_START_BIT then
if (change_output_bit_en = '1') then
if ((transfer_data = '1') and (I2C_BUS_MODE = '0')) then
ns_i2c_transceiver <= I2C_STATE_3_TRANSFER_BYTE;
else
ns_i2c_transceiver <= I2C_STATE_6_COMPLETE;
end if;
else
ns_i2c_transceiver <= I2C_STATE_2_START_BIT;
end if;
elsif s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE then
if ((current_bit = 0) and (change_output_bit_en = '1')) then
if ((I2C_BUS_MODE = '0') or (num_bits_to_transfer = 6)) then
ns_i2c_transceiver <= I2C_STATE_4_TRANSFER_ACK;
else
ns_i2c_transceiver <= I2C_STATE_6_COMPLETE;
end if;
else
ns_i2c_transceiver <= I2C_STATE_3_TRANSFER_BYTE;
end if;
elsif s_i2c_transceiver = I2C_STATE_4_TRANSFER_ACK then
if (change_output_bit_en = '1') then
ns_i2c_transceiver <= I2C_STATE_6_COMPLETE;
else
ns_i2c_transceiver <= I2C_STATE_4_TRANSFER_ACK;
end if;
elsif s_i2c_transceiver = I2C_STATE_5_STOP_BIT then
if (start_and_stop_en = '1') then
ns_i2c_transceiver <= I2C_STATE_6_COMPLETE;
else
ns_i2c_transceiver <= I2C_STATE_5_STOP_BIT;
end if;
elsif s_i2c_transceiver = I2C_STATE_6_COMPLETE then
if (transfer_data = '0') then
ns_i2c_transceiver <= I2C_STATE_0_IDLE;
else
ns_i2c_transceiver <= I2C_STATE_6_COMPLETE;
end if;
else
ns_i2c_transceiver <= I2C_STATE_0_IDLE;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
i2c_scen <= '1';
elsif (change_output_bit_en='1' and (s_i2c_transceiver = I2C_STATE_2_START_BIT)) then
i2c_scen <= '0';
elsif (s_i2c_transceiver = I2C_STATE_5_STOP_BIT) then
i2c_scen <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
ack <= '0';
elsif (clear_ack = '1') then
ack <= '0';
elsif (start_and_stop_en='1' and (s_i2c_transceiver = I2C_STATE_4_TRANSFER_ACK)) then
ack <= i2c_sdata xor I2C_BUS_MODE;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
data_from_i2c <= "00000000";
elsif (start_and_stop_en='1' and (s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE)) then
data_from_i2c <= data_from_i2c(6 downto 0) & i2c_sdata;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
current_bit <= 0;
elsif ((s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE) and
(change_output_bit_en = '1')) then
current_bit <= current_bit - 1;
elsif not(s_i2c_transceiver = I2C_STATE_3_TRANSFER_BYTE) then
current_bit <= num_bits_to_transfer;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
current_byte <= "00000000";
elsif ((s_i2c_transceiver = I2C_STATE_0_IDLE) or
(s_i2c_transceiver = I2C_STATE_2_START_BIT)) then
current_byte <= data_in;
end if;
end if;
end process;
end behaviour; | mit | cf06b9e432e7b8d35db07f911eec81ef | 0.602604 | 2.6053 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Controllori_Video/VGA_Controller.vhd | 1 | 6,337 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo VGA_Controller.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Modulo trovato in rete, convertito da Verilog a VHDL
-- e successivamente adattato al progetto.
-- Implementazione del controller VGA.
-- **********************************************************
-- This module implements the VGA controller. It assumes a 25MHz clock is supplied as input.
--
-- General approach:
-- Go through each line of the screen and read the colour each pixel on that line should have from
-- the Video memory. To do that for each (x,y) pixel on the screen convert (x,y) coordinate to
-- a memory_address at which the pixel colour is stored in Video memory. Once the pixel colour is
-- read from video memory its brightness is first increased before it is forwarded to the VGA DAC.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity VGA_Controller
is generic(
-- Timing parameters.
-- Recall that the VGA specification requires a few more rows and columns are drawn
-- when refreshing the screen than are actually present on the screen. This is necessary to
-- generate the vertical and the horizontal syncronization signals. If you wish to use a
-- display mode other than 640x480 you will need to modify the parameters below as well
-- as change the frequency of the clock driving the monitor (VGA_CLK).
C_VERT_NUM_PIXELS: std_logic_vector(9 downto 0) := "0111100000"; -- 480
C_VERT_SYNC_START: std_logic_vector(9 downto 0) := "0111101101"; -- 493
C_VERT_SYNC_END: std_logic_vector(9 downto 0) := "0111101110"; -- 494
C_VERT_TOTAL_COUNT: std_logic_vector(9 downto 0) := "1000001101"; -- 525
C_HORZ_NUM_PIXELS: std_logic_vector(9 downto 0) := "1010000000"; -- 640
C_HORZ_SYNC_START: std_logic_vector(9 downto 0) := "1010010011"; -- 659
C_HORZ_SYNC_END: std_logic_vector(9 downto 0) := "1011110010"; -- 754 (C_HORZ_SYNC_START + 96 - 1);
C_HORZ_TOTAL_COUNT: std_logic_vector(9 downto 0) := "1100100000" -- 800;
);
port(
vga_clock: in std_logic;
resetn: in std_logic;
pixel_colour: in std_logic_vector(0 downto 0);
memory_address: out std_logic_vector(16 downto 0);
VGA_R: out std_logic_vector(9 downto 0);
VGA_G: out std_logic_vector(9 downto 0);
VGA_B: out std_logic_vector(9 downto 0);
VGA_HS: out std_logic register;
VGA_VS: out std_logic register;
VGA_BLANK: out std_logic register;
VGA_SYNC: out std_logic := '1' -- VGA sync e' sempre a 1.
);
end VGA_Controller;
architecture behaviour of VGA_Controller is
component VGA_CalcoloIndirizzo is port (
x : in std_logic_vector(8 downto 0);
y : in std_logic_vector(7 downto 0);
mem_address : out std_logic_vector(16 downto 0)
);
end component;
signal VGA_HS1: std_logic register;
signal VGA_VS1: std_logic register;
signal VGA_BLANK1: std_logic register;
signal xCounter: std_logic_vector(9 downto 0) register;
signal yCounter: std_logic_vector(8 downto 0) register;
signal xCounter_clear: std_logic;
signal yCounter_clear: std_logic;
signal x: std_logic_vector(8 downto 0);
signal y: std_logic_vector(7 downto 0);
signal VGA_HS1_sig: std_logic;
signal VGA_VS1_sig: std_logic;
signal VGA_BLANK1_sig: std_logic;
begin
xCounter_clear <= '1' when (xCounter = (C_HORZ_TOTAL_COUNT-1)) else '0';
yCounter_clear <= '1' when (yCounter = (C_VERT_TOTAL_COUNT-1)) else '0';
VGA_HS1_sig <= '1' when (not((xCounter >= C_HORZ_SYNC_START) and (xCounter <= C_HORZ_SYNC_END))) else '0';
VGA_VS1_sig <= '1' when (not((yCounter >= C_VERT_SYNC_START) and (yCounter <= C_VERT_SYNC_END))) else '0';
-- Current X and Y is valid pixel range
VGA_BLANK1_sig <= '1' when (((xCounter < C_HORZ_NUM_PIXELS) and (yCounter < C_VERT_NUM_PIXELS))) else '0';
-- A counter to scan through a horizontal line.
process
begin
wait until rising_edge(vga_clock);
if (resetn ='0') then
xCounter <= "0000000000";
elsif (xCounter_clear ='1') then
xCounter <= "0000000000";
else
xCounter <= xCounter + "0000000001";
end if;
end process;
-- A counter to scan vertically, indicating the row currently being drawn.
process
begin
wait until rising_edge(vga_clock);
if (resetn ='0') then
yCounter <= "000000000";
elsif (xCounter_clear ='1' and yCounter_clear ='1') then
yCounter <= "000000000";
elsif (xCounter_clear = '1') then --Increment when x counter resets
yCounter <= yCounter + "000000001";
end if;
end process;
-- Generate the vertical and horizontal synchronization pulses.
process (vga_clock)
begin
if rising_edge(vga_clock) then
-- Sync Generator (ACTIVE LOW)
VGA_HS1 <= VGA_HS1_sig;
VGA_VS1 <= VGA_VS1_sig;
-- Current X and Y is valid pixel range
VGA_BLANK1 <= VGA_BLANK1_sig;
-- Add 1 cycle delay
VGA_HS <= VGA_HS1;
VGA_VS <= VGA_VS1;
VGA_BLANK <= VGA_BLANK1;
end if;
end process;
-- Convert the xCounter/yCounter location from screen pixels (640x480) to our
-- local dots (320x240). Here we effectively divide x/y coordinate by 2,
-- depending on the resolution.
process (vga_clock, resetn, pixel_colour)
begin
x <= xCounter(9 downto 1);
y <= yCounter(8 downto 1);
end process;
-- Brighten the colour output.
-- The colour input is first processed to brighten the image a little. Setting the top
-- bits to correspond to the R,G,B colour makes the image a bit dull.
process (pixel_colour)
begin
VGA_R <= "0000000000";
VGA_G <= "0000000000";
VGA_B <= "0000000000";
for index in 0 to 9 loop
VGA_R(index) <= pixel_colour(0);
VGA_G(index) <= pixel_colour(0);
VGA_B(index) <= pixel_colour(0);
end loop;
end process;
-- Conversione da coordinate (x,y) ad indirizzo di memoria.
controller_translator : VGA_CalcoloIndirizzo
port map(
x => x,
y => y,
mem_address => memory_address);
end behaviour; | mit | 020cf6bd89e2387b72fbc70101aa2e3e | 0.63437 | 3.198889 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue3/Keyboard/RF_fetch.vhd | 1 | 1,467 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:56:33 07/06/2016
-- Design Name:
-- Module Name: RF_fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RF_fetch is
Port ( kbclk : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
rf : out STD_LOGIC);
end RF_fetch;
architecture Behavioral of RF_fetch is
signal clk_history: STD_LOGIC_VECTOR(1 downto 0);
begin
clk_history_shift: process(kbclk, clk, reset)
begin
if reset = '1' then
clk_history <= "11";
elsif clk'event and clk = '1' then
clk_history(1) <= clk_history(0);
clk_history(0) <= kbclk;
end if;
end process clk_history_shift;
find_rf: process(clk_history)
begin
if clk_history = "10" then
rf <= '1';
else
rf <= '0';
end if;
end process find_rf;
end Behavioral;
| mit | 32e7a19e824fd81d34f152176bf7f561 | 0.581459 | 3.526442 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_audio_through.vhdl | 1 | 6,733 | -----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Christian Leibold
-- Year : 2013
-- Description : This is an really awesome example. The module waits
-- until an audio sample on the left or right channel
-- has been sampled. The current sample will be taken
-- and copied into the corresponding out register of
-- the audio interface.
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register
type state_t is (S_INIT, S_WAIT_SAMPLE, S_WRITE_SAMPLE_LEFT, S_WRITE_SAMPLE_RIGHT);
signal state, state_nxt : state_t;
signal sample, sample_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
begin
-- sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
sample <= (others => '0');
state <= S_INIT;
elsif rising_edge(clock) then
sample <= sample_nxt;
state <= state_nxt;
end if;
end process;
-- combinational process contains logic only
process(state, key, audio_din, audio_irq_left, audio_irq_right, sample)
begin
-- default assignments
-- set default values for the internal bus -> zero on all signals means, nothing will happen
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
led_green <= (others => '0');
-- hold previous values of all registers
sample_nxt <= sample;
state_nxt <= state;
case state is
-- Initial start state
when S_INIT =>
led_green(0) <= '1';
-- Wait for a press on KEY0 to start the function
if key(0) = '1' then
-- next state
state_nxt <= S_WAIT_SAMPLE;
end if;
when S_WAIT_SAMPLE =>
led_green(1) <= '1';
if audio_irq_right = '1' then
audio_cs <= '1';
audio_ack_right <= '1';
audio_addr <= CV_ADDR_AUDIO_RIGHT_IN;
sample_nxt <= audio_din;
state_nxt <= S_WRITE_SAMPLE_RIGHT;
end if;
if audio_irq_left = '1' then
audio_cs <= '1';
audio_ack_left <= '1';
audio_addr <= CV_ADDR_AUDIO_LEFT_IN;
sample_nxt <= audio_din;
state_nxt <= S_WRITE_SAMPLE_LEFT;
end if;
when S_WRITE_SAMPLE_LEFT =>
led_green(4) <= '1';
audio_cs <= '1';
audio_wr <= '1';
audio_addr <= CV_ADDR_AUDIO_LEFT_OUT;
audio_dout <= sample;
state_nxt <= S_WAIT_SAMPLE;
when S_WRITE_SAMPLE_RIGHT =>
led_green(5) <= '1';
audio_cs <= '1';
audio_wr <= '1';
audio_addr <= CV_ADDR_AUDIO_RIGHT_OUT;
audio_dout <= sample;
state_nxt <= S_WAIT_SAMPLE;
end case;
end process;
-- Default assignment for the general-purpose-outs (not used in the example)
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
led_red <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 | d23323c0cdafc501f2010fbccd55a5bc | 0.574781 | 2.662317 | false | false | false | false |
Fju/LeafySan | src/vhdl/toplevel/iac_toplevel.vhdl | 1 | 24,190 | -----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Toplevel
-- Author : Jan D�rre
-- Last update : 12.01.2015
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity iac_toplevel is
generic (
SIMULATION : boolean := false
);
port (
-- global signals
clock_ext_50 : in std_ulogic;
clock_ext2_50 : in std_ulogic;
clock_ext3_50 : in std_ulogic;
reset_n : in std_ulogic; -- (key3)
-- 7_seg
hex0_n : out std_ulogic_vector(6 downto 0);
hex1_n : out std_ulogic_vector(6 downto 0);
hex2_n : out std_ulogic_vector(6 downto 0);
hex3_n : out std_ulogic_vector(6 downto 0);
hex4_n : out std_ulogic_vector(6 downto 0);
hex5_n : out std_ulogic_vector(6 downto 0);
hex6_n : out std_ulogic_vector(6 downto 0);
hex7_n : out std_ulogic_vector(6 downto 0);
-- gpio
gpio : inout std_logic_vector(15 downto 0);
-- lcd
lcd_en : out std_ulogic;
lcd_rs : out std_ulogic;
lcd_rw : out std_ulogic;
lcd_on : out std_ulogic;
lcd_blon : out std_ulogic;
lcd_dat : out std_ulogic_vector(7 downto 0);
-- led/switches/keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key_n : in std_ulogic_vector(2 downto 0);
-- adc_dac
exb_adc_switch : out std_ulogic_vector(2 downto 0);
exb_adc_en_n : out std_ulogic;
exb_dac_ldac_n : out std_ulogic;
exb_spi_clk : out std_ulogic;
exb_spi_mosi : out std_ulogic;
exb_spi_miso : in std_logic;
exb_spi_cs_adc_n : out std_ulogic;
exb_spi_cs_dac_n : out std_ulogic;
-- sram
sram_ce_n : out std_ulogic;
sram_oe_n : out std_ulogic;
sram_we_n : out std_ulogic;
sram_ub_n : out std_ulogic;
sram_lb_n : out std_ulogic;
sram_addr : out std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0);
-- uart
uart_rts : in std_ulogic;
uart_cts : out std_ulogic;
uart_rxd : in std_ulogic;
uart_txd : out std_ulogic;
-- audio
aud_xclk : out std_ulogic;
aud_bclk : in std_ulogic;
aud_adc_lrck : in std_ulogic;
aud_adc_dat : in std_ulogic;
aud_dac_lrck : in std_ulogic;
aud_dac_dat : out std_ulogic;
i2c_sdat : inout std_logic;
i2c_sclk : inout std_logic;
-- infrared
irda_rxd : in std_ulogic
);
end iac_toplevel;
architecture rtl of iac_toplevel is
-- clock
signal clk_50 : std_ulogic; -- 50 MHz
signal clk_audio_12 : std_ulogic; -- 12 MHz
signal pll_locked : std_ulogic;
-- reset
signal reset : std_ulogic;
signal reset_intern : std_ulogic;
signal reset_n_intern : std_ulogic;
-- 7-Seg Bus Signals
signal sevenseg_cs : std_ulogic;
signal sevenseg_wr : std_ulogic;
signal sevenseg_addr : std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
signal sevenseg_din : std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
signal sevenseg_dout : std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC Bus Signals
signal adc_dac_cs : std_ulogic;
signal adc_dac_wr : std_ulogic;
signal adc_dac_addr : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
signal adc_dac_din : std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
signal adc_dac_dout : std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- Audio Bus Signals
signal audio_cs : std_ulogic;
signal audio_wr : std_ulogic;
signal audio_addr : std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
signal audio_din : std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
signal audio_dout : std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
signal audio_irq_left : std_ulogic;
signal audio_irq_right : std_ulogic;
signal audio_ack_left : std_ulogic;
signal audio_ack_right : std_ulogic;
-- Infra-red Receiver
signal ir_cs : std_ulogic;
signal ir_wr : std_ulogic;
signal ir_addr : std_ulogic_vector(CW_ADDR_IR-1 downto 0);
signal ir_din : std_ulogic_vector(CW_DATA_IR-1 downto 0);
signal ir_dout : std_ulogic_vector(CW_DATA_IR-1 downto 0);
signal ir_irq_rx : std_ulogic;
signal ir_ack_rx : std_ulogic;
-- LCD Bus Signals
signal lcd_cs : std_ulogic;
signal lcd_wr : std_ulogic;
signal lcd_addr : std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
signal lcd_din : std_ulogic_vector(CW_DATA_LCD-1 downto 0);
signal lcd_dout : std_ulogic_vector(CW_DATA_LCD-1 downto 0);
signal lcd_irq_rdy : std_ulogic;
signal lcd_ack_rdy : std_ulogic;
-- SRAM Bus Signals
signal sram_cs : std_ulogic;
signal sram_wr : std_ulogic;
signal sram_adr : std_ulogic_vector(CW_ADDR_SRAM-1 downto 0); -- slightly different name, because of a conflict with the entity
signal sram_din : std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
signal sram_dout : std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART Bus Signals
signal uart_cs : std_ulogic;
signal uart_wr : std_ulogic;
signal uart_addr : std_ulogic_vector(CW_ADDR_UART-1 downto 0);
signal uart_din : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal uart_dout : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal uart_irq_rx : std_ulogic;
signal uart_irq_tx : std_ulogic;
signal uart_ack_rx : std_ulogic;
signal uart_ack_tx : std_ulogic;
-- mux data signals for the case an interface is disabled
signal sevenseg_dout_wire : std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
signal adc_dac_dout_wire : std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
signal ir_dout_wire : std_ulogic_vector(CW_DATA_IR-1 downto 0);
signal lcd_dout_wire : std_ulogic_vector(CW_DATA_LCD-1 downto 0);
signal sram_dout_wire : std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
signal uart_dout_wire : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal audio_dout_wire : std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
signal audio_irq_left_wire : std_ulogic;
signal audio_irq_right_wire : std_ulogic;
signal ir_irq_rx_wire : std_ulogic;
signal lcd_irq_rdy_wire : std_ulogic;
signal uart_irq_rx_wire : std_ulogic;
signal uart_irq_tx_wire : std_ulogic;
-- key to revert key_n
signal key : std_ulogic_vector(2 downto 0);
-- register to sync async input signals
signal key_reg : std_ulogic_vector(2 downto 0);
signal switch_reg : std_ulogic_vector(17 downto 0);
-- gpio
component gpio_switcher is
port (
gpio : inout std_logic_vector(15 downto 0);
gp_ctrl : in std_ulogic_vector(15 downto 0);
gp_in : out std_ulogic_vector(15 downto 0);
gp_out : in std_ulogic_vector(15 downto 0)
);
end component gpio_switcher;
signal gp_ctrl : std_ulogic_vector(15 downto 0);
signal gp_out : std_ulogic_vector(15 downto 0);
signal gp_in : std_ulogic_vector(15 downto 0);
-- PLL (clk_50, clk_audio_12)
component pll is
port (
areset : in std_ulogic;
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c1 : out std_ulogic;
locked : out std_ulogic
);
end component pll;
-- components
component invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end component invent_a_chip;
component seven_seg is
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- 7-Seg
hex0_n : out std_ulogic_vector(6 downto 0);
hex1_n : out std_ulogic_vector(6 downto 0);
hex2_n : out std_ulogic_vector(6 downto 0);
hex3_n : out std_ulogic_vector(6 downto 0);
hex4_n : out std_ulogic_vector(6 downto 0);
hex5_n : out std_ulogic_vector(6 downto 0);
hex6_n : out std_ulogic_vector(6 downto 0);
hex7_n : out std_ulogic_vector(6 downto 0)
);
end component seven_seg;
component adc_dac is
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- adc/dac signals
-- spi signals
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
spi_miso : in std_ulogic;
spi_cs_dac_n : out std_ulogic;
spi_cs_adc_n : out std_ulogic;
-- Switch Signals
swt_select : out std_ulogic_vector(2 downto 0);
swt_enable_n : out std_ulogic;
-- DAC Signals
dac_ldac_n : out std_ulogic
);
end component adc_dac;
component audio is
port (
-- global
clock : in std_ulogic;
clock_audio : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
-- IRQ handling
iobus_irq_left : out std_ulogic;
iobus_irq_right : out std_ulogic;
iobus_ack_left : in std_ulogic;
iobus_ack_right : in std_ulogic;
-- connections to audio codec
aud_xclk : out std_ulogic;
aud_bclk : in std_ulogic;
aud_adc_lrck : in std_ulogic;
aud_adc_dat : in std_ulogic;
aud_dac_lrck : in std_ulogic;
aud_dac_dat : out std_ulogic;
i2c_sdat : inout std_logic;
i2c_sclk : inout std_logic
);
end component audio;
component infrared is
generic (
SIMULATION : boolean := false
);
port (
-- global
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_IR-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
-- IRQ handling
iobus_irq_rx : out std_ulogic;
iobus_ack_rx : in std_ulogic;
-- connection to ir-receiver
irda_rxd : in std_ulogic
);
end component infrared;
component lcd is
generic (
SIMULATION : boolean := false
);
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus signals
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
iobus_irq_rdy : out std_ulogic;
iobus_ack_rdy : in std_ulogic;
-- display signals
disp_en : out std_ulogic;
disp_rs : out std_ulogic;
disp_rw : out std_ulogic;
disp_dat : out std_ulogic_vector(7 downto 0);
disp_pwr : out std_ulogic;
disp_blon : out std_ulogic
);
end component lcd;
component sram is
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- sram connections
sram_ce_n : out std_ulogic;
sram_oe_n : out std_ulogic;
sram_we_n : out std_ulogic;
sram_ub_n : out std_ulogic;
sram_lb_n : out std_ulogic;
sram_addr : out std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0)
);
end component sram;
component uart is
generic (
SIMULATION : boolean := false
);
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_UART-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
-- IRQ handling
iobus_irq_rx : out std_ulogic;
iobus_irq_tx : out std_ulogic;
iobus_ack_rx : in std_ulogic;
iobus_ack_tx : in std_ulogic;
-- pins to outside
rts : in std_ulogic;
cts : out std_ulogic;
rxd : in std_ulogic;
txd : out std_ulogic
);
end component uart;
begin
-- gpio
gpio_switcher_inst : gpio_switcher
port map (
gpio => gpio,
gp_ctrl => gp_ctrl,
gp_in => gp_in,
gp_out => gp_out
);
-- PLL
pll_inst : pll
port map (
areset => reset,
inclk0 => clock_ext_50,
c0 => clk_50,
c1 => clk_audio_12,
locked => pll_locked
);
-- external reset
reset <= not(reset_n);
-- high active internal reset-signal
reset_n_intern <= pll_locked;
reset_intern <= not reset_n_intern;
-- invert low-active keys
key <= not key_n;
-- register to sync async signals
process(clk_50, reset_n_intern)
begin
if reset_n_intern = '0' then
key_reg <= (others => '0');
switch_reg <= (others => '0');
elsif rising_edge(clk_50) then
key_reg <= key;
switch_reg <= switch;
end if;
end process;
-- mux to prevent undefined signals
sevenseg_dout_wire <= (others => '0') when CV_EN_SEVENSEG = 0 else sevenseg_dout;
adc_dac_dout_wire <= (others => '0') when CV_EN_ADC_DAC = 0 else adc_dac_dout;
audio_dout_wire <= (others => '0') when CV_EN_AUDIO = 0 else audio_dout;
ir_dout_wire <= (others => '0') when CV_EN_IR = 0 else ir_dout;
lcd_dout_wire <= (others => '0') when CV_EN_LCD = 0 else lcd_dout;
sram_dout_wire <= (others => '0') when CV_EN_SRAM = 0 else sram_dout;
uart_dout_wire <= (others => '0') when CV_EN_UART = 0 else uart_dout;
audio_irq_left_wire <= '0' when CV_EN_AUDIO = 0 else audio_irq_left;
audio_irq_right_wire <= '0' when CV_EN_AUDIO = 0 else audio_irq_right;
ir_irq_rx_wire <= '0' when CV_EN_IR = 0 else ir_irq_rx;
lcd_irq_rdy_wire <= '0' when CV_EN_LCD = 0 else lcd_irq_rdy;
uart_irq_rx_wire <= '0' when CV_EN_UART = 0 else uart_irq_rx;
uart_irq_tx_wire <= '0' when CV_EN_UART = 0 else uart_irq_tx;
-- invent_a_chip module
invent_a_chip_inst : invent_a_chip
port map (
-- Global Signals
clock => clk_50,
reset => reset_intern,
-- Interface Signals
-- 7-Seg
sevenseg_cs => sevenseg_cs,
sevenseg_wr => sevenseg_wr,
sevenseg_addr => sevenseg_addr,
sevenseg_din => sevenseg_dout_wire,
sevenseg_dout => sevenseg_din,
-- ADC/DAC
adc_dac_cs => adc_dac_cs,
adc_dac_wr => adc_dac_wr,
adc_dac_addr => adc_dac_addr,
adc_dac_din => adc_dac_dout_wire,
adc_dac_dout => adc_dac_din,
-- AUDIO
audio_cs => audio_cs,
audio_wr => audio_wr,
audio_addr => audio_addr,
audio_din => audio_dout_wire,
audio_dout => audio_din,
audio_irq_left => audio_irq_left_wire,
audio_irq_right => audio_irq_right_wire,
audio_ack_left => audio_ack_left,
audio_ack_right => audio_ack_right,
-- Infra-red Receiver
ir_cs => ir_cs,
ir_wr => ir_wr,
ir_addr => ir_addr,
ir_din => ir_dout_wire,
ir_dout => ir_din,
ir_irq_rx => ir_irq_rx_wire,
ir_ack_rx => ir_ack_rx,
-- LCD
lcd_cs => lcd_cs,
lcd_wr => lcd_wr,
lcd_addr => lcd_addr,
lcd_din => lcd_dout_wire,
lcd_dout => lcd_din,
lcd_irq_rdy => lcd_irq_rdy_wire,
lcd_ack_rdy => lcd_ack_rdy,
-- SRAM
sram_cs => sram_cs,
sram_wr => sram_wr,
sram_addr => sram_adr,
sram_din => sram_dout_wire,
sram_dout => sram_din,
-- UART
uart_cs => uart_cs,
uart_wr => uart_wr,
uart_addr => uart_addr,
uart_din => uart_dout_wire,
uart_dout => uart_din,
uart_irq_rx => uart_irq_rx_wire,
uart_irq_tx => uart_irq_tx_wire,
uart_ack_rx => uart_ack_rx,
uart_ack_tx => uart_ack_tx,
-- GPIO
gp_ctrl => gp_ctrl,
gp_in => gp_in,
gp_out => gp_out,
-- LED/Switches/Keys
led_green => led_green,
led_red => led_red,
switch => switch_reg,
key => key_reg
);
-- generate interface modules
seven_seg_gen : if CV_EN_SEVENSEG = 1 generate
sven_seg_inst : seven_seg
port map (
-- global signals
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => sevenseg_cs,
iobus_wr => sevenseg_wr,
iobus_addr => sevenseg_addr,
iobus_din => sevenseg_din,
iobus_dout => sevenseg_dout,
-- 7-Seg
hex0_n => hex0_n,
hex1_n => hex1_n,
hex2_n => hex2_n,
hex3_n => hex3_n,
hex4_n => hex4_n,
hex5_n => hex5_n,
hex6_n => hex6_n,
hex7_n => hex7_n
);
end generate seven_seg_gen;
adc_dac_gen : if CV_EN_ADC_DAC = 1 generate
adc_dac_inst : adc_dac
port map (
-- global signals
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => adc_dac_cs,
iobus_wr => adc_dac_wr,
iobus_addr => adc_dac_addr,
iobus_din => adc_dac_din,
iobus_dout => adc_dac_dout,
-- adc/dac signals
-- spi signals
spi_clk => exb_spi_clk,
spi_mosi => exb_spi_mosi,
spi_miso => exb_spi_miso,
spi_cs_dac_n => exb_spi_cs_dac_n,
spi_cs_adc_n => exb_spi_cs_adc_n,
-- switch signals
swt_select => exb_adc_switch,
swt_enable_n => exb_adc_en_n,
-- dac signals
dac_ldac_n => exb_dac_ldac_n
);
end generate adc_dac_gen;
audio_gen : if CV_EN_AUDIO = 1 generate
audio_inst : audio
port map (
-- global
clock => clk_50,
clock_audio => clk_audio_12,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => audio_cs,
iobus_wr => audio_wr,
iobus_addr => audio_addr,
iobus_din => audio_din,
iobus_dout => audio_dout,
-- IRQ handling
iobus_irq_left => audio_irq_left,
iobus_irq_right => audio_irq_right,
iobus_ack_left => audio_ack_left,
iobus_ack_right => audio_ack_right,
-- connections to audio codec
aud_xclk => aud_xclk,
aud_bclk => aud_bclk,
aud_adc_lrck => aud_adc_lrck,
aud_adc_dat => aud_adc_dat,
aud_dac_lrck => aud_dac_lrck,
aud_dac_dat => aud_dac_dat,
i2c_sdat => i2c_sdat,
i2c_sclk => i2c_sclk
);
end generate audio_gen;
ir_gen : if CV_EN_IR = 1 generate
ir_inst : infrared
generic map (
SIMULATION => SIMULATION
)
port map (
-- global
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => ir_cs,
iobus_wr => ir_wr,
iobus_addr => ir_addr,
iobus_din => ir_din,
iobus_dout => ir_dout,
-- IRQ handling
iobus_irq_rx => ir_irq_rx,
iobus_ack_rx => ir_ack_rx,
-- connection to ir-receiver
irda_rxd => irda_rxd
);
end generate ir_gen;
lcd_gen : if CV_EN_LCD = 1 generate
lcd_inst : lcd
generic map (
SIMULATION => SIMULATION
)
port map (
-- global signals
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => lcd_cs,
iobus_wr => lcd_wr,
iobus_addr => lcd_addr,
iobus_din => lcd_din,
iobus_dout => lcd_dout,
-- IRQ handling
iobus_irq_rdy => lcd_irq_rdy,
iobus_ack_rdy => lcd_ack_rdy,
-- display signals
disp_en => lcd_en,
disp_rs => lcd_rs,
disp_rw => lcd_rw,
disp_dat => lcd_dat,
disp_pwr => lcd_on,
disp_blon => lcd_blon
);
end generate lcd_gen;
sram_gen : if CV_EN_SRAM = 1 generate
sram_inst : sram
port map (
-- global signals
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => sram_cs,
iobus_wr => sram_wr,
iobus_addr => sram_adr,
iobus_din => sram_din,
iobus_dout => sram_dout,
-- sram connections
sram_ce_n => sram_ce_n,
sram_oe_n => sram_oe_n,
sram_we_n => sram_we_n,
sram_ub_n => sram_ub_n,
sram_lb_n => sram_lb_n,
sram_addr => sram_addr,
sram_dq => sram_dq
);
end generate sram_gen;
uart_gen : if CV_EN_UART = 1 generate
uart_inst : uart
generic map (
SIMULATION => SIMULATION
)
port map (
-- global signals
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => uart_cs,
iobus_wr => uart_wr,
iobus_addr => uart_addr,
iobus_din => uart_din,
iobus_dout => uart_dout,
-- IRQ handling
iobus_irq_rx => uart_irq_rx,
iobus_irq_tx => uart_irq_tx,
iobus_ack_rx => uart_ack_rx,
iobus_ack_tx => uart_ack_tx,
-- pins to outside
rts => uart_rts,
cts => uart_cts,
rxd => uart_rxd,
txd => uart_txd
);
end generate uart_gen;
end rtl; | apache-2.0 | 025ac71c57c443e7b398c71e0bacc467 | 0.597362 | 2.522474 | false | false | false | false |
maly/fpmi | FPGA/rmi.vhd | 1 | 6,255 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rmi is
port (
--- kit
led3, led7, led9: out std_logic;
clk: in std_logic;
--- kbd
rows: out std_logic_vector(4 downto 0);
cols: in std_logic_vector(4 downto 0);
--- LED
anode: out std_logic_vector(8 downto 0);
cathode: out std_logic_vector(7 downto 0)
);
end entity;
architecture mtest of rmi is
signal Hz1: std_logic:='0';
signal cpuClock5: std_logic;
signal segone:std_logic_vector(8 downto 0):="111111110";
signal cpuAddr: std_logic_vector(15 downto 0);
signal cpuAddrTemp: std_logic_vector(15 downto 0);
signal cpuDataOut: std_logic_vector(7 downto 0);
signal cpuDataIn: std_logic_vector(7 downto 0);
signal cpuClock: std_logic;
signal cpuClkCount: integer range 0 to 31:=0;
signal cpuReset: std_logic:='0';
signal cpuIO: std_logic;
signal cpuRd: std_logic;
signal cpuWr: std_logic;
signal cpuVMA: std_logic;
signal memRD, memWR, ioRD, ioWR: std_logic;
signal n_MREQ,n_ioRQ,n_RD,n_WR: std_logic;
signal ramDataOut: std_logic_vector(7 downto 0);
signal ramCS: std_logic;
signal romDataOut: std_logic_vector(7 downto 0);
signal romCS: std_logic;
signal pioDataOut: std_logic_vector(7 downto 0);
signal pioCS: std_logic;
signal PA1Out: std_logic_vector(7 downto 0);
signal PB1Out: std_logic_vector(7 downto 0);
signal PC1Out: std_logic_vector(7 downto 0);
signal PA1In: std_logic_vector(7 downto 0);
signal PB1In: std_logic_vector(7 downto 0);
signal PC1In: std_logic_vector(7 downto 0);
signal adlatch: std_logic_vector(15 downto 0);
signal dalatch: std_logic_vector(7 downto 0);
signal keys: std_logic_vector(24 downto 0);
signal keyrows: std_logic_vector(2 downto 0);
signal kreset, kint: std_logic;
begin
CPU: entity work.light8080 port map (
addr_out=>cpuAddrTemp,
data_in=>cpuDataIn,
data_out=>cpuDataOut,
intr=>'0',
io=>cpuIO,
rd=>cpuRd,
wr=>cpuWr,
vma=>cpuVMA,
-- clk=>Hz1, --cpuClock,
clk=>cpuClock,
reset=>cpuReset
);
--cpu1 : entity work.t80s
--generic map(mode => 0, t2write => 0, iowait => 1)
--port map(
--reset_n => not cpureset,
--clk_n => Hz1,
--wait_n => '1',
--int_n => '1',
--nmi_n => '1',
--busrq_n => '1',
--mreq_n => n_MREQ,
--iorq_n => n_IORQ,
--rd_n => n_RD,
--wr_n => n_WR,
--a => cpuAddr,
--di => cpuDataIn,
--do => cpuDataOut);
------------------
----- RAM
ram1: entity work.RAM2
port map (
rdaddress=>cpuAddr(9 downto 0),
wraddress=>cpuAddrTemp(9 downto 0),
clock=>clk,
data=>cpuDataOut,
wren=> ramCS and memWR,
q => RamDataOut
);
-- PROA: entity work.adprobe port map(cpuAddr&cpuDataIn&cpuVMA&cpuRD&CpuWR&ramCS&memRD&memWR&ioRD&ioWR);
--ram1: entity work.MEMO
--port map (
--address=>cpuAddr(9 downto 0),
--data_in=>cpuDataOut,
--WE=> memWR,
--CE=>ramCS,
--data_out => RamDataOut
--);
------------------
----- ROM
rom1: entity work.ROM
port map (
address=>cpuAddr(9 downto 0),
clock=>clk,
q => RomDataOut
);
----------------
----- 8255 if 1
io1: entity work.pia8255
port map (
reset=>cpuReset,
clken=>'1',
clk=>clk,
rd => ioRD,
wr => ioWR,
cs => pioCS,
d_i => cpuDataOut,
d_o=> pioDataOut,
pa_i=>PA1In,
pb_i=>PB1In,
pc_i=>PC1In,
pa_o=>PA1Out,
pb_o=>PB1Out,
pc_o=>PC1Out,
a=>cpuAddr(1 downto 0)
);
-------------------
-- matrix
KBDM: entity work.matrix port map (clk,rows,cols,keys);
--PROA: entity work.adprobe port map(keyrows&"00"&iord&iowr&'0'&PC1Out(3 downto 0)&"00000000000000000000");
PMIK: entity work.pmikey port map (keys, kreset,kint, PC1Out(3 downto 0),keyrows);
PC1In<='1'&keyrows&"1111";
-- PROA: entity work.adprobe port map(cpuAddr&cpuDataIn&pioCS&cpuRD&CpuWR&cpuIO&memRD&memWR&ioRD&ioWR);
----------------
----- CS logic
memRD <= cpuRd and not cpuIO and cpuVMA;
memWR <= cpuWr and not cpuIO and cpuVMA;
ioRD <= cpuRd and cpuIO;
ioWR <= cpuWr and cpuIO and cpuVMA;
--memRD <= not (n_RD or n_MREQ);
--memWR <= not (n_WR or n_MREQ);
--ioRD <= not (n_RD or n_IORQ);
--ioWR <= not (n_WR or n_IORQ);
ramCS <= '1' when (cpuAddr(15 downto 10)="000111") and (cpuIO='0') else '0';
romCS <= '1' when (cpuAddr(15 downto 10)="000000") and (cpuIO='0') else '0';
pioCS <= '1' when (cpuAddr(7 downto 2)="111110") and (cpuIO='1') else '0';
---bus bus bus
--cpuDataIn <=
-- '1'&keyrows&"1111" when pioCS='1' else
-- RamDataOut when ramCS='1' else
-- RomDataOut when (romCS='1') else;
-- cpuDataIn;
process (clk) is
begin
if rising_edge(clk) then
if cpuRD='1' then
if pioCS='1' then cpuDataIn <= pioDataOut; end if;
if ramCS='1' then cpuDataIn <= RamDataOut; end if;
if romCS='1' then cpuDataIn <= RomDataOut; end if;
end if;
end if;
end process;
--led3<= not cpuAddr(13);
--led7<= not cpuAddr(14);
--led9<= not cpuAddr(15);
--led3<= not cpuAddr(0);
--led7<= not cpuAddr(1);
--led9<= not cpuAddr(2);
--led3<= not (ramCS and memRD);
--led7<= not (romCS and memRD);
--led9<= not (pioCS and cpuIO);
led3<= keyrows(2);
led7<= keyrows(1);
led9<= keyrows(0);
cpuReset<=not kreset;
--cpuClock<=Hz1;
cpuClock<=cpuClock5;
process (clk) is
begin
if (rising_edge(clk)) then
if cpuVMA='1' then
cpuAddr<=cpuAddrTemp;
end if;
end if;
end process;
process (clk) is
variable counter:integer:=0;
begin
if (rising_edge(clk)) then
counter:= counter + 1;
if (counter<2000000) then Hz1<='1'; else Hz1<='0'; end if;
end if;
if (counter=4000000) then
counter:=0;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if cpuClkCount < 31 then -- 4 = 10MHz, 3 = 12.5MHz, 2=16.6MHz, 1=25MHz
cpuClkCount <= cpuClkCount + 1;
else
cpuClkCount <= 0;
end if;
if cpuClkCount < 15 then -- 2 when 10MHz, 2 when 12.5MHz, 2 when 16.6MHz, 1 when 25MHz
cpuClock5 <= '0';
else
cpuClock5 <= '1';
end if;
end if; --rising edge
end process;
DSPL: entity work.PMILED port map (anode, cathode,PA1Out, PC1Out(3 downto 0)); -- segment je aktivni v 0
--DSPL: entity work.PMILED port map (anode, cathode,cpuDataIn, "1110"); -- segment je aktivni v 0
--DSPL: entity work.DISP8 port map (anode, cathode,cpuDataIn,PC1Out,cpuAddr, clk); -- segment je aktivni v 0
--DSPL: entity work.DISP8 port map (anode, cathode,RamDataOut,cpuDataIn,cpuAddr, clk); -- segment je aktivni v 0
--DSPL: entity work.DISP8 port map (anode, cathode,dalatch,cpuDataIn,adlatch, clk); -- segment je aktivni v 0
end architecture; | mit | c3f70da54ebfc50ec2452d16ffe61c45 | 0.660751 | 2.716023 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Display.vhd | 1 | 3,886 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Display.vhd
-- Versione 1.03 - 21.03.2013
-- **********************************************************
-- **********************************************************
-- Gestisce il display su VGA 320x240.
-- 1 bit per pixel (monocromatico).
-- **********************************************************
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity Display is
generic (
sweep_delay : std_logic_vector(31 downto 0) := "00000000000000000010011100010000"; -- 10000
xmax : std_logic_vector(8 downto 0) := "100111111"; -- 319; // Massimo degli x
ymax : std_logic_vector(7 downto 0) := "11101111"; -- 239; // Massimo degli y
st_ploty : std_logic := '0';
st_done : std_logic := '1'
);
port (
clock : in std_logic;
reset : in std_logic;
freeze : in std_logic;
data : in std_logic_vector(15 downto 0);
x : inout std_logic_vector(8 downto 0);
y : inout std_logic_vector(7 downto 0);
color : inout std_logic;
plot : inout std_logic
);
end Display;
architecture behaviour of Display is
signal delay_counter : std_logic_vector(31 downto 0);
signal st : std_logic;
signal streg : std_logic;
signal buff_sig : std_logic_vector(8 downto 0);
begin
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------- FSM gestione VGA
---------------------------------------------------------------------------------------------
process (all)
begin
st <= streg;
case streg is
when st_ploty =>
if y = ymax then
st <= st_done;
end if;
when st_done =>
IF (freeze = '0') AND (delay_counter = sweep_delay) then
st <= st_ploty;
end if;
end case;
end process;
process (clock)
begin
if rising_edge(clock) then
if (reset = '1') then
streg <= st_done;
else
streg <= st;
end if;
end if;
end process;
buff_sig <= "000000000" when (x = xmax) else x + "000000001";
-- Contatore X
process (clock)
begin
if (rising_edge(clock)) then
if (reset = '1') then
delay_counter <= "00000000000000000000000000000000";
x <= "000000000";
elsif (streg = st_done) then
if (delay_counter = sweep_delay) then
delay_counter <= "00000000000000000000000000000000";
x <= buff_sig;
else
delay_counter <= delay_counter + "00000000000000000000000000000001";
end if;
end if;
end if;
end process;
-- Contatore Y
process (clock)
begin
if (rising_edge(clock)) then
if (reset = '1' or (streg = st_done)) then
y <= "00000000";
elsif (y < ymax) then
y <= y + "00000001";
end if;
end if;
end process;
-- Sincronizzazione
plot <= '1' when (streg = st_ploty) else '0';
-- Determino se devo visualizzare o no il pixel
-- 01111000 = 120 --> riga centrale del display
-- data(15) = segno
color <= '1' when (y= "01111000" + (data(15)
& data(14) & data(12) & data(10) & data(8) & data(6) & data(4) & data(2))) else '0';
--color <= '1' when (y= "01111000" + (data(15) & data(6 downto 0))) else '0';
end behaviour; | mit | a874558a4a335b833217427615e3c3a8 | 0.444416 | 4.112169 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/xor/myXor2.vhdl | 1 | 885 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myXor2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end myXor2;
architecture behavorial of myXor2 is
-- declare components
component myNand2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myOr2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myAnd2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
-- signals
signal a_or_b_out: std_logic;
signal a_nand_b_out: std_logic;
begin
-- initialize components and port map
myOr2_1: myOr2 port map(a => a, b => b, s => a_or_b_out);
myNand2_1: myNand2 port map(a => a, b => b, s => a_nand_b_out);
myAnd2_1: myAnd2 port map(a => a_or_b_out, b => a_nand_b_out, s => s);
end behavorial;
| mit | 8e94190e0d0359e86dbfc36cd25ecc6a | 0.620339 | 2.818471 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue2/Moebius/S_Reg.vhd | 1 | 2,083 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:59:04 06/12/2016
-- Design Name:
-- Module Name: S_Reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity S_Reg is
Port ( c_V, c_R : STD_LOGIC; -- Taktflanken
RESET : in STD_LOGIC; -- asynchrones Reset
S : in STD_LOGIC_VECTOR (2 downto 1); -- Steuersignal(e)
P : in STD_LOGIC_VECTOR (3 downto 0); -- 4 Bits fr Ladeoperation
e_l : in STD_LOGIC; -- einzuschiebendes Bit bei rechts schieben
Q : buffer STD_LOGIC_VECTOR (3 downto 0)); -- Zustand
end S_Reg;
architecture Behavioral of S_Reg is
signal D: STD_LOGIC_VECTOR(3 downto 0); -- Ausgang MUX, Eingang D-Register
signal c, Q_int, nQ_int: STD_LOGIC; -- fr Taktentprellung
begin
-- MUX: implementiert Steuerlogik
mux: process(S,P,Q,e_l)
begin
case S is
when "00" => D <= Q; -- halten
when "01" => D <= e_l & Q(3 downto 1); -- rechts schieben
when "10" => D <= Q(2 downto 0) & (not Q(3)); -- Mbius schieben, anstelle von links schieben
when others => D <= P; -- laden
end case;
end process mux;
-- D-Register: speichert Zustand, implementiert asynchrones Reset
D_Reg: process(c,RESET)
begin
if RESET = '1' then
Q <= "0000";
elsif c'event and c = '1' then
Q <= D;
end if;
end process D_Reg;
-- Entprellung des Taktsignals wie im Skript Seite 66
Q_int <= c_R nor nQ_int;
nQ_int <= c_V nor Q_int;
c <= Q_int;
end Behavioral;
| mit | 00da3aefd2b50fd4f45e90e850dcdaf8 | 0.593375 | 3.199693 | false | false | false | false |
shaolinbertrand/Processador_N.I.N.A | registrador.vhd | 1 | 446 |
entity registrador is port
( clk : in bit;
rst : in bit;
set : in bit;
d : in bit_vector(2 downto 0);
q : out bit_vector(2 downto 0));
end registrador;
architecture hardware of registrador is begin
process(clk)
begin
if(clk 'event and clk = '1') then
if(rst = '1') then q <= "000";
elsif(set = '1') then q <= "111";
else q <= d;
end if;
end if;
end process;
end hardware;
| gpl-3.0 | 7788464f4cc3b4986abe62402d4781d7 | 0.55157 | 3.231884 | false | false | false | false |
Fju/LeafySan | src/vhdl/utils/gpio_switcher.vhdl | 1 | 908 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : GPIO Switcher
-- Last update : 22.07.2014
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gpio_switcher is
port (
gpio : inout std_logic_vector(15 downto 0);
gp_ctrl : in std_ulogic_vector(15 downto 0);
gp_in : out std_ulogic_vector(15 downto 0);
gp_out : in std_ulogic_vector(15 downto 0)
);
end gpio_switcher;
architecture rtl of gpio_switcher is
begin
process (gpio, gp_ctrl, gp_out)
begin
for i in 0 to 15 loop
-- read / in
if gp_ctrl(i) = '0' then
gpio(i) <= 'Z';
gp_in(i) <= gpio(i);
-- write / out
else
gpio(i) <= gp_out(i);
gp_in(i) <= '0';
end if;
end loop;
end process;
end architecture rtl; | apache-2.0 | 2dac92d17df93c991376f59303587622 | 0.501101 | 3.016611 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sources_1/mwfc.vhd | 1 | 4,473 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity mwfc is
Generic (
precision : integer := 13;
bcdprecision : integer := 16 );
Port (
rawfrq : out unsigned(precision - 1 downto 0); -- May need an extra bit of margin
bcdfrq : out std_logic_vector(bcdprecision - 1 downto 0);
ord : out signed(7 downto 0);
overflow : out std_logic;
clk : in std_logic;
clk2 : in std_logic;
rst : in std_logic );
end mwfc;
architecture Behavioral of mwfc is
-- The following constants are taken from the accuracy calculation
-- on the associated spreadsheet
constant hfbitmargin : integer := 2; -- FIXME should be 2
constant lfbitmargin : integer := 19;
constant inputbits : integer := precision + hfbitmargin;
constant timerbits : integer := lfbitmargin;
constant nscalestages : integer := 7; -- FIXME log2 of maxscalefactor
signal tcount, isync1 : unsigned(timerbits-1 downto 0);
signal icount, isync0 : unsigned(inputbits-1 downto 0);
signal scaling : signed(nscalestages-1 downto 0);
signal ratio : unsigned(precision-1 downto 0);
signal divbusy, divoverflow, divstrobe : std_logic;
signal bcdstrobe : std_logic;
signal final : unsigned(rawfrq'range);
signal order : signed(ord'range);
constant measureinterval : integer := 2**precision;
signal bcd : std_logic_vector(bcdfrq'range);
signal convbusy, convstrobe : std_logic;
begin
-- The current values of the corrections arrays expect this
-- given precision
assert precision = 17 report "Mismatch in precision!" severity error;
ord <= order;
bcdfrq <= bcd;
rawfrq <= final;
overflow <= divoverflow;
conv : entity work.hex2bcd
generic map (
precision => final'length,
width => bcd'length,
bits => 5,
ndigits => 5 ) -- log2 of precision
port map (
hex => final,
bcd => bcd,
strobe => bcdstrobe,
rst => rst,
clk => clk );
-- Count the number of timer and input tics in the given
-- measurement interval, taking a whole number of input tics.
stage1 : entity work.counter
generic map (
Tlen => tcount'length,
ILen => icount'length,
measureinterval => measureinterval )
port map (
timer => clk,
input => clk2,
tcount => tcount,
icount => icount,
enable => '1',
strobe => divstrobe,
rst => rst);
-- Synchronize the reciprocal counter to the 'clk' clock domain
process(clk)
begin
if rising_edge(clk) then
isync1 <= (others => '0');
isync1(isync0'range) <= isync0;
isync0 <= icount;
end if;
end process;
-- Divide M by N
stage2 : entity work.fpdiv
generic map (
size => tcount'length,
precision => ratio'length,
pscale => scaling'length )
port map (
dividend => isync1,
divisor => tcount,
quotient => ratio,
scale => scaling,
busy => divbusy,
overflow => divoverflow,
strobe => divstrobe,
clk => clk,
rst => rst );
process(clk,rst)
variable divold : std_logic;
begin
if rst = '1' then
divold := '0';
elsif rising_edge(clk) then
if divold = '0' and divbusy = '1' then
convstrobe <= '1';
else
convstrobe <= '0';
end if;
divold := divbusy;
end if;
end process;
stage3 : entity work.fpbaseconv
generic map (
precision => final'length,
exp_precision => order'length,
nscalestages => nscalestages )
port map (
mantissa => final,
exponent => order,
busy => convbusy,
scaling => scaling,
ratio => ratio,
strobe => convstrobe,
clk => clk,
rst => rst );
process(clk,rst)
variable convold : std_logic;
begin
if rst = '1' then
convold := '0';
elsif rising_edge(clk) then
if convold = '0' and convbusy = '1' then
bcdstrobe <= '1';
else
bcdstrobe <= '0';
end if;
convold := convbusy;
end if;
end process;
end Behavioral;
| mit | 8028db9fa067f0da185b13380ec35f88 | 0.560921 | 3.954907 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Utils/Slow_Clock_Generator.vhd | 1 | 2,808 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Slow_Clock_Generator.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Generazione segnali di clock a bassa frequenza.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
entity Slow_Clock_Generator is
generic (
COUNTER_BITS: integer := 10;
COUNTER_INC: std_logic_vector(9 downto 0) := "0000000001"
);
port (
clk: in std_logic;
reset: in std_logic;
enable_clk: in std_logic;
new_clk: out std_logic;
ris_edge: out std_logic;
fal_edge: out std_logic;
middle_of_high_level: out std_logic;
middle_of_low_level: out std_logic
);
end Slow_Clock_Generator;
architecture behaviour of Slow_Clock_Generator is
signal clk_counter: std_logic_vector (COUNTER_BITS downto 1);
signal new_clk_sig: std_logic;
begin
new_clk <= new_clk_sig;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
clk_counter <= "0000000000";
elsif (enable_clk = '1') then
clk_counter <= clk_counter + COUNTER_INC;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
new_clk_sig <= '0';
else
new_clk_sig <= clk_counter(COUNTER_BITS);
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
ris_edge <= '0';
else
ris_edge <= (clk_counter(COUNTER_BITS) xor new_clk_sig) and (not new_clk_sig);
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
fal_edge <= '0';
else
fal_edge <= (clk_counter(COUNTER_BITS) xor new_clk_sig) and new_clk_sig;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
middle_of_high_level <= '0';
else
middle_of_high_level <= (
(clk_counter(COUNTER_BITS) and (not clk_counter((COUNTER_BITS - 1))))
and AND_REDUCE(clk_counter((COUNTER_BITS - 2) downto 1)));
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (reset = '1') then
middle_of_low_level <= '0';
else
middle_of_low_level <= (
((not clk_counter(COUNTER_BITS)) and (not clk_counter(( COUNTER_BITS - 1 ))))
and AND_REDUCE(clk_counter((COUNTER_BITS - 2) downto 1))) ;
end if;
end if;
end process;
end behaviour; | mit | 0f208cc80463d5a1d73bc1408b60cfd9 | 0.552707 | 3.003209 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sources_1/driveseg.vhd | 1 | 3,560 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package driveseg_pkg is
component driveseg
Port(
data : in STD_LOGIC_VECTOR (15 downto 0);
seg_c : out STD_LOGIC_VECTOR (7 downto 0);
seg_a : out std_logic_vector (3 downto 0);
en : in std_logic_vector(3 downto 0);
clk : in std_logic;
rst : in std_logic);
end component;
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.driveseg_pkg.all;
entity driveseg is
Port ( data : in STD_LOGIC_VECTOR (15 downto 0);
seg_c : out STD_LOGIC_VECTOR (7 downto 0);
seg_a : out std_logic_vector (3 downto 0);
en : in std_logic_vector(3 downto 0);
clk : in std_logic;
rst : in std_logic);
end driveseg;
architecture Behavioral of driveseg is
signal latch : std_logic_vector(data'range);
signal active, active_new : std_logic_vector(seg_a'range);
signal cathode, cathode_new : std_logic_vector(seg_c'range);
signal divider : unsigned(16 downto 0);
begin
seg_a <= active;
seg_c <= cathode;
process(clk,rst)
variable div,old : std_logic;
begin
if rst = '1' then
latch <= (others => '0');
active <= "1110";
cathode <= (others => '0');
divider <= (others => '0');
old := '0';
elsif rising_edge(clk) then
div := divider(16);
if old = '0' and div = '1' then
active <= active_new;
cathode <= cathode_new;
end if;
latch <= data;
divider <= divider + "1";
old := div;
end if;
end process;
process(en,active,latch,cathode)
variable digit : std_logic_vector(active'range);
variable segen : std_logic;
variable active_next : std_logic_vector(active'range);
variable cathode_next : std_logic_vector(cathode'range);
begin
active_next := active(active'high-1 downto 0) & active(active'high);
cathode_next := cathode;
-- Turn off dots
cathode_next(7) := '1';
-- Extract the current digit
case active_next is
when "1110" => digit := latch( 3 downto 0);
when "1101" => digit := latch( 7 downto 4);
when "1011" => digit := latch(11 downto 8);
when "0111" => digit := latch(15 downto 12);
when others => digit := "0000";
end case;
-- Check if the current digit is active
segen := (not active_next(3) and en(3)) or (not active_next(2) and en(2)) or (not active_next(1) and en(1)) or (not active_next(0) and en(0));
-- Drive the segment cathode based on the given digit
if segen = '1' then
case digit is
when "0000" => cathode_next(6 downto 0) := "1000000";
when "0001" => cathode_next(6 downto 0) := "1111001";
when "0010" => cathode_next(6 downto 0) := "0100100";
when "0011" => cathode_next(6 downto 0) := "0110000";
when "0100" => cathode_next(6 downto 0) := "0011001";
when "0101" => cathode_next(6 downto 0) := "0010010";
when "0110" => cathode_next(6 downto 0) := "0000010";
when "0111" => cathode_next(6 downto 0) := "1111000";
when "1000" => cathode_next(6 downto 0) := "0000000";
when "1001" => cathode_next(6 downto 0) := "0010000";
when "1010" => cathode_next(6 downto 0) := "0001000";
when "1011" => cathode_next(6 downto 0) := "0000011";
when "1100" => cathode_next(6 downto 0) := "1000110";
when "1101" => cathode_next(6 downto 0) := "0100001";
when "1110" => cathode_next(6 downto 0) := "0000110";
when "1111" => cathode_next(6 downto 0) := "0001110";
when others => cathode_next(6 downto 0) := "0111111";
end case;
else
cathode_next(6 downto 0) := "0111111";
end if;
active_new <= active_next;
cathode_new <= cathode_next;
end process;
end Behavioral;
| mit | 45ff51a2eef1c8f57813069ee40cac8a | 0.630056 | 2.959268 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | AudioVideo_Config.vhd | 1 | 14,482 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo AudioVideo_Config.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Questo modulo setta i registri di controllo Audio/Video.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
entity AudioVideo_Config is port(
clk: in std_logic;
reset: in std_logic;
ob_address: in std_logic_vector(2 downto 0);
ob_byteenable: in std_logic_vector(3 downto 0);
ob_chipselect: in std_logic;
ob_read: in std_logic;
ob_write: in std_logic;
ob_writedata: in std_logic_vector(31 downto 0);
I2C_SDAT: inout std_logic;
ob_readdata: out std_logic_vector(31 downto 0);
ob_waitrequest: out std_logic;
I2C_SCLK: out std_logic;
useMicInput: in std_logic
);
end AudioVideo_Config;
architecture behaviour of AudioVideo_Config is
-- Parametri
constant I2C_BUS_MODE: std_logic_vector(0 downto 0) := "0";
constant MIN_ROM_ADDRESS: std_logic_vector(5 downto 0) := "000000"; --6'h00;
constant MAX_ROM_ADDRESS: std_logic_vector(5 downto 0) := "001010"; --6'h0A;
--N Nome Valore Significati principali
--0 Left Line In 000011000 [4:0] = Volume canale input sinistro
--1 Right Line In 000011000 [4:0] = Volume canale input destro
--2 Left Headphone Out 001110111 [6:0] = Volume canale output sinistro
--3 Right Headphone Out 001110111 [6:0] = Volume canale output destro
--4 Analogue Audio Path Control 000010000 [2] = Mic/Linein, Altri: mute, boost, effetti (tutto a zero)
--5 Digital Audio Path Control 000000110 [0] = filtro passa alto, [2:1] = frequenza (11=48 KHz)
--6 Power Down Control 000000000 Per disabilitare vari componenti
--7 Digital Audio Interface Format 001001101 [1:0] = formato audio, [3:2] = lunghezza input dati (11=32 bit)
--8 Sampling Control 000000000 [0] = Modo (normale)
--9 Active Control 000000001 [0] = Interfaccia attiva/non attiva
constant AUD_LINE_IN_LC: std_logic_vector(8 downto 0) := "000011000"; --9'd24;
constant AUD_LINE_IN_RC: std_logic_vector(8 downto 0) := "000011000"; --9'd24;
constant AUD_LINE_OUT_LC: std_logic_vector(8 downto 0) := "001110111"; --9'd119;
constant AUD_LINE_OUT_RC: std_logic_vector(8 downto 0) := "001110111"; --9'd119;
constant AUD_ADC_PATH: std_logic_vector(8 downto 0) := "000010001"; --9'd17;
constant AUD_DAC_PATH: std_logic_vector(8 downto 0) := "000000110"; --9'd6;
constant AUD_POWER: std_logic_vector(8 downto 0) := "000000000"; --9'h000;
constant AUD_DATA_FORMAT: std_logic_vector(8 downto 0) := "001001101"; --9'd77;
constant AUD_SAMPLE_CTRL: std_logic_vector(8 downto 0) := "000000000"; --9'd0;
constant AUD_SET_ACTIVE: std_logic_vector(8 downto 0) := "000000001"; --9'h001;
-- Costanti
constant I2C_STATE_0_IDLE: std_logic_vector(1 downto 0) := "00"; -- 2'h0;
constant I2C_STATE_1_START: std_logic_vector(1 downto 0) := "01"; -- 2'h1;
constant I2C_STATE_2_TRANSFERING: std_logic_vector(1 downto 0) := "10"; -- 2'h2;
constant I2C_STATE_3_COMPLETE: std_logic_vector(1 downto 0) := "11"; -- 2'h3;
-- Segnali
signal internal_reset: std_logic;
signal valid_operation: std_logic;
signal clk_400KHz: std_logic;
signal start_and_stop_en: std_logic;
signal change_output_bit_en: std_logic;
signal enable_clk_s: std_logic;
signal address: std_logic_vector(1 downto 0);
signal byteenable: std_logic_vector(3 downto 0);
signal chipselect: std_logic;
signal read_s: std_logic;
signal write_s: std_logic;
signal writedata: std_logic_vector(31 downto 0);
signal readdata: std_logic_vector(31 downto 0);
signal waitrequest: std_logic;
signal clear_status_bits: std_logic;
signal send_start_bit: std_logic;
signal send_stop_bit: std_logic;
signal auto_init_data: std_logic_vector(7 downto 0);
signal auto_init_transfer_data: std_logic;
signal auto_init_start_bit: std_logic;
signal auto_init_stop_bit: std_logic;
signal auto_init_complete: std_logic;
signal auto_init_error: std_logic;
signal transfer_data: std_logic;
signal transfer_complete: std_logic;
signal i2c_ack: std_logic;
signal i2c_received_data: std_logic_vector(7 downto 0);
-- Internal Registers
signal data_to_transfer: std_logic_vector(7 downto 0);
signal num_bits_to_transfer: integer; --std_logic_vector(2 downto 0);
signal read_byte: std_logic;
signal transfer_is_read: std_logic;
-- State Machine Registers
signal ns_alavon_slave: std_logic_vector(1 downto 0);
signal s_alavon_slave: std_logic_vector(1 downto 0);
-- Segnali di buffer
signal buff1_sig: std_logic;
signal buff2_sig: std_logic;
signal buff3_sig: std_logic;
signal addrIs00: std_logic;
signal addrIs01: std_logic;
signal addrIs10: std_logic;
signal addrIs11: std_logic;
component Slow_Clock_Generator is
generic (
COUNTER_BITS: integer := 10;
COUNTER_INC: std_logic_vector(9 downto 0) := "0000000001"
);
port (
clk: in std_logic;
reset: in std_logic;
enable_clk: in std_logic;
new_clk: out std_logic;
ris_edge: out std_logic;
fal_edge: out std_logic;
middle_of_high_level: out std_logic;
middle_of_low_level: out std_logic
);
end component;
component AudioVideo_Init is
generic (
MIN_ROM_ADDRESS: std_logic_vector(5 downto 0);
MAX_ROM_ADDRESS: std_logic_vector(5 downto 0);
AUD_LINE_IN_LC: std_logic_vector(8 downto 0);
AUD_LINE_IN_RC: std_logic_vector(8 downto 0);
AUD_LINE_OUT_LC: std_logic_vector(8 downto 0);
AUD_LINE_OUT_RC: std_logic_vector(8 downto 0);
AUD_ADC_PATH: std_logic_vector(8 downto 0);
AUD_DAC_PATH: std_logic_vector(8 downto 0);
AUD_POWER: std_logic_vector(8 downto 0);
AUD_DATA_FORMAT: std_logic_vector(8 downto 0);
AUD_SAMPLE_CTRL: std_logic_vector(8 downto 0);
AUD_SET_ACTIVE: std_logic_vector(8 downto 0)
);
port (
clk: in std_logic;
reset: in std_logic;
clear_error: in std_logic;
ack: in std_logic;
transfer_complete: in std_logic;
data_out: out std_logic_vector(7 downto 0);
transfer_data: out std_logic;
send_start_bit: out std_logic;
send_stop_bit: out std_logic;
auto_init_complete: out std_logic;
auto_init_error: out std_logic;
useMicInput: in std_logic
);
end component;
component I2C_Controller is
generic (
I2C_BUS_MODE: std_logic_vector(0 downto 0)
);
port (
clk: in std_logic;
reset: in std_logic;
clear_ack: in std_logic;
clk_400KHz: in std_logic;
start_and_stop_en: in std_logic;
change_output_bit_en: in std_logic;
send_start_bit: in std_logic;
send_stop_bit: in std_logic;
data_in: in std_logic_vector(7 downto 0);
transfer_data: in std_logic;
read_byte: in std_logic;
num_bits_to_transfer: integer; --in std_logic_vector(2 downto 0);
i2c_sdata: inout std_logic;
i2c_sclk: out std_logic;
i2c_scen: out std_logic;
enable_clk: out std_logic;
ack: out std_logic;
data_from_i2c: buffer std_logic_vector(7 downto 0);
transfer_complete: out std_logic
);
end component;
begin
-- Segnali buffer
buff1_sig <= '1' when (s_alavon_slave /= I2C_STATE_0_IDLE) else '0';
buff2_sig <= '1' when (s_alavon_slave /= I2C_STATE_1_START) else '0';
buff3_sig <= '1' when (s_alavon_slave /= I2C_STATE_2_TRANSFERING) else '0';
addrIs00 <= '1' when address = "00" else '0';
addrIs01 <= '1' when address = "01" else '0';
addrIs10 <= '1' when address = "10" else '0';
addrIs11 <= '1' when address = "11" else '0';
ob_readdata <= readdata;
ob_waitrequest <= waitrequest;
readdata(31 downto 8) <= "000000000000000000000000";
readdata( 7 downto 4) <= i2c_received_data(7 downto 4) when addrIs11='1' else "0000";
readdata(3) <= auto_init_error when addrIs01='1' else
i2c_received_data(3) when addrIs11='1' else '0';
readdata(2) <= not auto_init_complete when addrIs01='1' else
i2c_received_data(2) when addrIs11='1' else '0';
readdata(1) <= (buff1_sig) when addrIs01='1' else
i2c_received_data(1) when addrIs11='1' else '0';
readdata(0) <= i2c_ack when addrIs01='1' else
i2c_received_data(0) when addrIs11='1' else '0';
waitrequest <= valid_operation and ((write_s and buff2_sig) or (read_s and not(transfer_complete)));
address <= ob_address(1 downto 0);
byteenable <= ob_byteenable;
chipselect <= ob_chipselect;
read_s <= ob_read;
write_s <= ob_write;
writedata <= ob_writedata;
internal_reset <= reset or (
chipselect
and byteenable(0)
and addrIs00
and write_s
and writedata(0)
);
valid_operation <= chipselect and byteenable(0)
and (
(addrIs00 and write_s and (not writedata(0)))
or (addrIs10 and write_s)
or addrIs11)
;
clear_status_bits <= chipselect and addrIs01 and write_s;
transfer_data <= auto_init_transfer_data or (not buff3_sig);
send_start_bit <= auto_init_start_bit
or (chipselect
and byteenable(0)
and addrIs00
and write_s and writedata(2)
);
send_stop_bit <= auto_init_stop_bit or
(chipselect
and byteenable(0)
and addrIs00
and write_s
and writedata(1)
);
process (clk)
begin
if (rising_edge(clk)) then
if (internal_reset = '1') then
s_alavon_slave <= I2C_STATE_0_IDLE;
else
s_alavon_slave <= ns_alavon_slave;
end if;
end if;
end process;
process (clk,
reset,
ob_address,
ob_byteenable,
ob_chipselect,
ob_read,
ob_write,
ob_writedata)
begin
ns_alavon_slave <= I2C_STATE_0_IDLE;
if (s_alavon_slave = I2C_STATE_0_IDLE) then
if ((valid_operation = '1') and (auto_init_complete = '1')) then
ns_alavon_slave <= I2C_STATE_1_START;
else
ns_alavon_slave <= I2C_STATE_0_IDLE;
end if;
elsif (s_alavon_slave = I2C_STATE_1_START) then
ns_alavon_slave <= I2C_STATE_2_TRANSFERING;
elsif (s_alavon_slave = I2C_STATE_2_TRANSFERING) then
if (transfer_complete = '1') then
ns_alavon_slave <= I2C_STATE_3_COMPLETE;
else
ns_alavon_slave <= I2C_STATE_2_TRANSFERING;
end if;
elsif (s_alavon_slave = I2C_STATE_3_COMPLETE) then
ns_alavon_slave <= I2C_STATE_0_IDLE;
else
ns_alavon_slave <= I2C_STATE_0_IDLE;
end if;
end process;
process (clk)
begin
if (rising_edge(clk)) then
if (internal_reset = '1') then
data_to_transfer <= "00000000"; --8'h00;
num_bits_to_transfer <= 3;
elsif (auto_init_complete = '0') then
data_to_transfer <= auto_init_data;
num_bits_to_transfer <= 7;
elsif (s_alavon_slave = I2C_STATE_1_START) then
num_bits_to_transfer <= 7;
if ((ob_address = "000") and writedata(2) = '1') then
data_to_transfer <= "00110100"; --8'h34;
elsif ((ob_address = "100") and writedata(2) = '1') then
data_to_transfer <= "10000000";-- or writedata(3);
else
data_to_transfer <= writedata(7 downto 0);
end if;
end if;
end if;
end process;
process (clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
read_byte <= '0';
elsif (s_alavon_slave = I2C_STATE_1_START) then
read_byte <= read_s;
end if;
end if;
end process;
process (clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
transfer_is_read <= '0';
elsif ((s_alavon_slave = I2C_STATE_1_START) and (address = "00")) then
transfer_is_read <= writedata(3);
end if;
end if;
end process;
Clock_Generator_400KHz: Slow_Clock_Generator
generic map (
COUNTER_BITS => 10,
COUNTER_INC => "0000000001"
)
port map (
clk => clk,
reset => internal_reset,
enable_clk => enable_clk_s,
new_clk => clk_400KHz,
ris_edge => OPEN,
fal_edge => OPEN,
middle_of_high_level => start_and_stop_en,
middle_of_low_level => change_output_bit_en
);
Auto_Initialize: AudioVideo_Init
generic map (
MIN_ROM_ADDRESS => MIN_ROM_ADDRESS,
MAX_ROM_ADDRESS => MAX_ROM_ADDRESS,
AUD_LINE_IN_LC => AUD_LINE_IN_LC,
AUD_LINE_IN_RC => AUD_LINE_IN_RC,
AUD_LINE_OUT_LC => AUD_LINE_OUT_LC,
AUD_LINE_OUT_RC => AUD_LINE_OUT_RC,
AUD_ADC_PATH => AUD_ADC_PATH,
AUD_DAC_PATH => AUD_DAC_PATH,
AUD_POWER => AUD_POWER,
AUD_DATA_FORMAT => AUD_DATA_FORMAT,
AUD_SAMPLE_CTRL => AUD_SAMPLE_CTRL,
AUD_SET_ACTIVE => AUD_SET_ACTIVE
)
port map (
clk => clk,
reset => internal_reset,
clear_error => clear_status_bits,
ack => i2c_ack,
transfer_complete => transfer_complete,
data_out => auto_init_data,
transfer_data => auto_init_transfer_data,
send_start_bit => auto_init_start_bit,
send_stop_bit => auto_init_stop_bit,
auto_init_complete => auto_init_complete,
auto_init_error => auto_init_error,
useMicInput => useMicInput
);
I2C_Controller_Entity: I2C_Controller
generic map(
I2C_BUS_MODE => I2C_BUS_MODE
)
port map(
clk => clk,
reset => internal_reset,
clear_ack => clear_status_bits,
clk_400KHz => clk_400KHz,
start_and_stop_en => start_and_stop_en,
change_output_bit_en => change_output_bit_en,
send_start_bit => send_start_bit,
send_stop_bit => send_stop_bit,
data_in => data_to_transfer,
transfer_data => transfer_data,
read_byte => read_byte,
num_bits_to_transfer => num_bits_to_transfer,
i2c_sdata => I2C_SDAT,
i2c_sclk => I2C_SCLK,
i2c_scen => OPEN,
enable_clk => enable_clk_s,
ack => i2c_ack,
data_from_i2c => i2c_received_data,
transfer_complete => transfer_complete
);
end behaviour; | mit | cfb868f4c955f46f1ba6bc5e477ee2ad | 0.610206 | 2.686329 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sources_1/fpbaseconv.vhd | 1 | 5,414 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity fpbaseconv is
Generic (
precision : integer := 13;
exp_precision : integer := 8;
nscalestages : integer := 7 );
Port (
mantissa : out unsigned(precision-1 downto 0);
exponent : out signed(exp_precision-1 downto 0);
busy : out std_logic;
scaling : in signed(nscalestages-1 downto 0);
ratio : in unsigned(precision-1 downto 0);
strobe : in std_logic;
clk : in std_logic;
rst : in std_logic );
end fpbaseconv;
architecture Behavioral of fpbaseconv is
type state_type is (ST_WAIT, ST_PRELOAD, ST_MULT, ST_SCALE, ST_ROUND);
signal state, state_new : state_type;
type A is array (0 to 35) of integer;
constant digits : A := (
0, 0, 0, 0,
1, 1, 1, -- 2^4 to 2^6
2, 2, 2, -- 2^7 to 2^9
3, 3, 3, 3, -- 2^10 to 2^13
4, 4, 4, -- 2^14 to 2^16
5, 5, 5, -- 2^17 to 2^19
6, 6, 6, 6, -- 2^20 to 2^23
7, 7, 7, -- 2^24 to 2^26
8, 8, 8, -- 2^27 to 2^29
9, 9, 9, 9, -- 2^30 to 2^33
10, 10 ); -- 2^34 to 2^35
type B is array(0 to 35) of unsigned(precision + 2 downto 0);
constant corrections : B := (
x"00000", x"80000", x"40000", x"20000",
x"A0000", x"50000", x"28000",
x"C8000", x"64000", x"32000",
x"FA000", x"7D000", x"3E800", x"1F400",
x"9C400", x"4E200", x"27100",
x"C3500", x"61A80", x"30D40",
x"F4240", x"7A120", x"3D090", x"1E848",
x"98968", x"4C4B4", x"2625A",
x"BEBC2", x"5F5E1", x"2FAF1",
x"EE6B3", x"77359", x"3B9AD", x"1DCD6",
x"95030", x"4A818" );
signal corr_out : unsigned(corrections(0)'range);
signal digit_out : signed(exponent'range);
signal factor, factor_new : unsigned(ratio'range);
signal shifter, shifter_new, accumulator, accumulator_new : unsigned(ratio'length + corrections(0)'length - 1 downto 0);
signal exp, exp_new : signed(exponent'range);
signal exponent_int, exponent_new : signed(exponent'range);
signal mantissa_int, mantissa_new : unsigned(mantissa'range);
signal busy_int, busy_new : std_logic;
begin
mantissa <= mantissa_int;
exponent <= exponent_int;
busy <= busy_int;
process(clk,rst)
variable S0 : integer;
begin
if rst = '1' then
state <= ST_WAIT;
busy_int <= '0';
elsif rising_edge(clk) then
S0 := -to_integer(scaling); -- Floating-point base-2 exponent
-- Multiplication factor to convert from base-2 to base-10 for
-- the given base-2 exponent
corr_out <= corrections(S0);
digit_out <= to_signed(8, exponent'length) - digits(S0); -- Get fp base-10 exponent
state <= state_new;
factor <= factor_new;
shifter <= shifter_new;
accumulator <= accumulator_new;
exp <= exp_new;
mantissa_int <= mantissa_new;
exponent_int <= exponent_new;
busy_int <= busy_new;
end if;
end process;
process(state, strobe, ratio, corr_out, digit_out, factor, shifter, accumulator, exp, exponent_int, mantissa_int, busy_int)
variable state_next : state_type;
variable factor_next : unsigned(factor'range);
variable shifter_next, accumulator_next : unsigned(shifter'range);
variable exp_next : signed(exp'range);
begin
state_next := state;
factor_next := factor;
shifter_next := shifter;
accumulator_next := accumulator;
exp_next := exp;
exponent_new <= exponent_int;
mantissa_new <= mantissa_int;
busy_new <= busy_int;
case state is
when ST_WAIT =>
if strobe = '1' then
busy_new <= '1';
state_next := ST_PRELOAD;
end if;
when ST_PRELOAD =>
factor_next := ratio;
shifter_next := (others => '0');
accumulator_next := (others => '0');
shifter_next(corr_out'range) := corr_out;
exp_next := digit_out;
state_next := ST_MULT;
when ST_MULT =>
factor_next := shift_right(factor, 1);
shifter_next := shift_left(shifter, 1);
if factor(0) = '1' then
accumulator_next := accumulator + shifter;
elsif factor = "0" then
-- 'corrections' is fixed point, shifted over precision+3 bits
-- Save one extra bit for rounding
-- Save another four bits for a multiply by 10 if needed?
-- Multiply is a slow operation
accumulator_next := shift_right(accumulator, precision + 3 - 1 - 4);
state_next := ST_SCALE;
end if;
when ST_SCALE =>
-- FIXME this depends on BCD precision!
if accumulator < shift_left(to_unsigned(10000, accumulator'length),4) then
-- Five bits, because four bits precision + 1 rounding
-- Multiply by 10 (8 + 2)
accumulator_next := shift_left(accumulator,1) + shift_left(accumulator,3);
exp_next := exp - 1;
end if;
state_next := ST_ROUND;
when ST_ROUND =>
-- Downshift by 4
-- Round based on highest truncated bit
if accumulator(4) = '1' then
mantissa_new <= accumulator(mantissa'high+5 downto 5) + "1";
else
mantissa_new <= accumulator(mantissa'high+5 downto 5);
end if;
exponent_new <= exp;
busy_new <= '0';
state_next := ST_WAIT;
when others =>
end case;
state_new <= state_next;
factor_new <= factor_next;
shifter_new <= shifter_next;
accumulator_new <= accumulator_next;
exp_new <= exp_next;
end process;
end Behavioral;
| mit | d370789384d7e3a4271d73d932efcdc6 | 0.60676 | 2.986211 | false | false | false | false |
J-Rios/VHDL_Modules | 2.Secuencial/RAM_distributed.vhd | 1 | 1,022 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity LUTRAM is
generic
(
B : NATURAL := 8; -- Address Bus width
W : NATURAL := 2 -- Data Bus width
);
port
(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
wr_en : in STD_LOGIC;
w_addr : in STD_LOGIC_VECTOR(W-1 downto 0);
r_addr : in STD_LOGIC_VECTOR(W-1 downto 0);
w_data : in STD_LOGIC_VECTOR(B-1 downto 0);
r_data : out STD_LOGIC_VECTOR(B-1 downto 0)
);
end LUTRAM;
-------------------------------------------------------------------------
architecture Behavioral of LUTRAM is
type REG_FILE_TYPE is array (2**W-1 downto 0) of STD_LOGIC_VECTOR (B-1 downto 0);
signal array_reg : REG_FILE_TYPE;
begin
process(clk)
begin
if (rising_edge(clk)) then
if (wr_en = '1') then
array_reg(to_integer(unsigned(w_addr))) <= w_data;
end if;
end if;
end process;
r_data <= array_reg(to_integer(unsigned(r_addr)));
end Behavioral;
| gpl-3.0 | ef8673d814a1a4f7e05c6363280846a3 | 0.549902 | 2.962319 | false | false | false | false |
Hyvok/KittLights | kitt_lights.vhd | 1 | 4,110 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity kitt_lights is
generic
(
-- Number of LEDs
LIGHTS_N : positive;
-- Number of clock cycles to advance an LED
ADVANCE_VAL : positive;
-- Number of bits in the PWM counter
PWM_BITS_N : positive;
-- Number of clock cycles for an LED to decay one PWM step
DECAY_VAL : positive
);
port
(
clk : in std_logic;
reset : in std_logic;
lights_out : out std_logic_vector(LIGHTS_N - 1 downto 0)
);
end entity;
architecture rtl of kitt_lights is
type decay_t is array (lights_out'range)
of unsigned(PWM_BITS_N - 1 downto 0);
signal decay : decay_t;
signal active : std_logic_vector(lights_out'range);
begin
-- Advance currently active LED
advance_p: process(clk, reset)
variable timer : unsigned(ceil_log2(ADVANCE_VAL) downto 0);
variable dir_up : boolean;
begin
if reset = '1' then
active <= (others => '0');
timer := (others => '0');
dir_up := false;
elsif rising_edge(clk) then
-- If all lights are off
if active = (active'range => '0') then
active(0) <= '1';
-- Delay done, advance to next LED
elsif timer = ADVANCE_VAL then
timer := (others => '0');
-- Change direction
if active(active'left) = '1' or active(active'right) = '1' then
dir_up := not dir_up;
end if;
-- Advance
if dir_up = true then
active <= shift_left_vec(active, 1);
else
active <= shift_right_vec(active, 1);
end if;
else
timer := timer + 1;
end if;
end if;
end process;
-- Calculate PWM values for all LEDs and decay them when LED is not active
decay_p: process(clk, reset)
variable counter : unsigned(ceil_log2(DECAY_VAL) downto 0);
begin
if reset = '1' then
decay <= (others => (others => '0'));
counter := (others => '0');
elsif rising_edge(clk) then
-- Delay done, decay PWM values
if counter = DECAY_VAL then
counter := (others => '0');
-- Calculate new PWM values
for i in 0 to decay'high loop
-- LED is currently active, apply full duty cycle
if active(i) = '1' then
decay(i) <= to_unsigned(2**PWM_BITS_N - 1, PWM_BITS_N);
-- LED is not active, decay PWM value
elsif active(i) = '0' then
-- Make sure decay does not wrap
if decay(i) >= 1 then
decay(i) <= decay(i) - to_unsigned(1, PWM_BITS_N);
else
decay(i) <= (others => '0');
end if;
end if;
end loop;
end if;
counter := counter + 1;
end if;
end process;
-- Apply PWM values
pwm_p: process(clk, reset)
variable pwm_timer : unsigned(PWM_BITS_N - 1 downto 0);
begin
if reset = '1' then
pwm_timer := (others => '0');
lights_out <= (others => '0');
elsif rising_edge(clk) then
-- Apply to all LED outputs
for i in 0 to lights_out'high loop
if pwm_timer <= decay(i) and not (decay(i) = 0) then
lights_out(i) <= '1';
else
lights_out(i) <= '0';
end if;
end loop;
pwm_timer := pwm_timer + 1;
end if;
end process;
end;
| mit | 9b14b0430255df824befebb720f01c6c | 0.454501 | 4.317227 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | PlayRecord.vhd | 1 | 7,606 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo PlayRecord.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- FSM per la gestione di Registrazione e Riproduzione Audio.
-- **********************************************************
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity PlayRecord is
generic (
st_start : std_logic_vector(2 downto 0) := "000"; -- Valori di stato della FSM
st_rc_audio_wait : std_logic_vector(2 downto 0) := "001";
st_rc_ram_nextaddr : std_logic_vector(2 downto 0) := "010";
st_rc_ram_wait : std_logic_vector(2 downto 0) := "011";
st_pl_ram_rd : std_logic_vector(2 downto 0) := "100";
st_pl_audio_wait : std_logic_vector(2 downto 0) := "101";
st_pl_ram_nextaddr : std_logic_vector(2 downto 0) := "110";
st_input_check : std_logic_vector(2 downto 0) := "111"
);
port (
CLOCK_50 : in std_logic;
CLOCK_1S : in std_logic;
reset : in std_logic;
ram_addr : out std_logic_vector(21 downto 0);
ram_data_in : out std_logic_vector(15 downto 0);
ram_read : out std_logic;
ram_write : out std_logic;
ram_data_out : in std_logic_vector(15 downto 0);
ram_valid : in std_logic;
ram_waitrq : in std_logic;
audio_out : out std_logic_vector(15 downto 0);
audio_in : in std_logic_vector(15 downto 0);
audio_out_allowed : in std_logic;
audio_in_available : in std_logic;
write_audio_out : out std_logic;
read_audio_in : out std_logic;
play : in std_logic;
rec : in std_logic;
pause : in std_logic;
speed : in std_logic_vector(1 downto 0);
ram_addr_max : in std_logic_vector(21 downto 0);
playLimitReached : inout std_logic;
secondsCounter : inout std_logic_vector(7 downto 0)
);
end PlayRecord;
architecture behaviour OF PlayRecord IS
signal st : std_logic_vector(2 downto 0);
signal streg : std_logic_vector(2 downto 0);
-- Segnali buffer
signal ram_addr_sig : std_logic_vector(21 downto 0);
signal ram_data_in_sig : std_logic_vector(15 downto 0);
signal ram_read_sig : std_logic;
signal ram_write_sig : std_logic;
signal audio_out_sig : std_logic_vector(15 downto 0);
signal write_audio_out_sig : std_logic;
signal read_audio_in_sig : std_logic;
signal secondsIncrement : std_logic_vector(7 downto 0);
begin
secondsIncrement <= "000000" & speed + "00000001"; -- Determina lo step di incremento dei secondi in Play
-- Segnali buffer
ram_addr <= ram_addr_sig;
ram_data_in <= ram_data_in_sig;
ram_read <= ram_read_sig;
ram_write <= ram_write_sig;
audio_out <= audio_out_sig;
write_audio_out <= write_audio_out_sig;
read_audio_in <= read_audio_in_sig;
playLimitReached <= '1' when ram_addr_max <= ram_addr_sig else '0';
process (all)
begin
st <= streg;
---------------------------------------------------------------------------------------------
---------------------------------------------------------------- FSM della fase di Play e Rec
---------------------------------------------------------------------------------------------
case streg is
---------------------------------------------- STATO START
when st_start =>
st <= st_input_check; -- Da start va a input_check
---------------------------------------------- STATO IDLE
when st_input_check =>
if pause = '0' then -- Stato "idle": determina la prossima operazione
if play = '1' then
if playLimitReached = '0' then
st <= st_pl_audio_wait; -- Play
end if;
elsif rec = '1' then
st <= st_rc_audio_wait; -- Rec: attesa segnale audio
else
st <= st_start; -- Ne' Play ne' Rec: non fa nulla
end if;
end if;
---------------------------------------------- GESTIONE REGSTRAZIONE
when st_rc_audio_wait =>
if (audio_in_available = '1') then
st <= st_rc_ram_nextaddr; -- Rec: passa a indirizzo di memoria successivo
end if;
when st_rc_ram_nextaddr =>
st <= st_rc_ram_wait; -- Rec: scrittura in memoria
when st_rc_ram_wait =>
if (ram_waitrq = '0') then
st <= st_input_check; -- Rec: scrittura terminata e ritorno
end if;
---------------------------------------------- GESTIONE RIPRODUZIONE
when st_pl_audio_wait =>
if (audio_out_allowed = '1') then
st <= st_pl_ram_rd; -- Play: leggi da RAM
end if;
when st_pl_ram_rd =>
if (ram_waitrq ='0' and ram_valid = '1') then
st <= st_pl_ram_nextaddr; -- Play: passa a indirizzo di memoria successivo
end if;
when st_pl_ram_nextaddr =>
st <= st_input_check; -- Play: lettura completata e ritorno
end case;
end process;
process (CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if (reset = '1') then
streg <= st_input_check;
else
streg <= st;
end if;
end if;
end process;
-- Contatore indirizzo RAM
process (CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if (reset = '1') then
ram_addr_sig <= "0000000000000000000000";
else
if (streg = st_start) then
ram_addr_sig <= "0000000000000000000000";
elsif (streg = st_rc_ram_nextaddr) then
ram_addr_sig <= ram_addr_sig + "0000000000000000000001";
elsif streg = st_pl_ram_nextaddr then -- La velocita' fa "saltare" n banchi di RAM
ram_addr_sig <= ram_addr_sig + "0000000000000000000001" + ("00000000000000000000" & speed);
end if;
end if;
end if;
end process;
-- Contatore secondi
process (CLOCK_50, CLOCK_1S)
begin
if rising_edge(CLOCK_1S) then
if (reset = '1') then
secondsCounter <= "00000000";
else
if (streg = st_start) then
secondsCounter <= "00000000";
elsif pause = '0' then
if play = '1' then
if playLimitReached = '0' then -- secondsIncrement dipende dalla velocita'
secondsCounter <= secondsCounter + secondsIncrement;
else
secondsCounter <= "00000000";
end if;
elsif rec = '1' then
secondsCounter <= secondsCounter + "00000001";
else
secondsCounter <= "00000000";
end if;
end if;
end if;
end if;
end process;
-- Controller Audio
read_audio_in_sig <= '1' when ((streg = st_rc_ram_nextaddr) or (streg = st_start and audio_in_available = '1')) else '0';
write_audio_out_sig <= '1' when (st = st_pl_ram_nextaddr) else '0';
-- Connessione con SDRAM
ram_data_in_sig <= audio_in;
audio_out_sig <= ram_data_out;
ram_write_sig <= '1' when (streg = st_rc_ram_wait) else '0';
ram_read_sig <= '1' when (streg = st_pl_ram_rd) else '0';
END behaviour; | mit | 99a0f2ada5d98dabba690bce5b210110 | 0.503944 | 3.587736 | false | false | false | false |
maly/fpmi | FPGA/8080/light8080.vhd | 1 | 57,430 | --##############################################################################
-- light8080 : Intel 8080 binary compatible core
--##############################################################################
-- v1.3 (12 FEB 2012) Fix: General solution to AND, OR, XOR clearing CY,ACY.
-- v1.2 (08 jul 2010) Fix: XOR operations were not clearing CY,ACY.
-- v1.1 (20 sep 2008) Microcode bug in INR fixed.
-- v1.0 (05 nov 2007) First release. Jose A. Ruiz.
--
-- This file and all the light8080 project files are freeware (See COPYING.TXT)
--##############################################################################
-- (See timing diagrams at bottom of file. More comprehensive explainations can
-- be found in the design notes)
--##############################################################################
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--##############################################################################
-- vma : enable a memory or io r/w access.
-- io : access in progress is io (and not memory)
-- rd : read memory or io
-- wr : write memory or io
-- data_out : data output
-- addr_out : memory and io address
-- data_in : data input
-- halt : halt status (1 when in halt state)
-- inte : interrupt status (1 when enabled)
-- intr : interrupt request
-- inta : interrupt acknowledge
-- reset : synchronous reset
-- clk : clock
--
-- (see timing diagrams at bottom of file)
--##############################################################################
entity light8080 is
Port (
addr_out : out std_logic_vector(15 downto 0);
inta : out std_logic;
inte : out std_logic;
halt : out std_logic;
intr : in std_logic;
vma : out std_logic;
io : out std_logic;
rd : out std_logic;
wr : out std_logic;
fetch : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
clk : in std_logic;
reset : in std_logic );
end light8080;
--##############################################################################
-- All memory and io accesses are synchronous (rising clock edge). Signal vma
-- works as the master memory and io synchronous enable. More specifically:
--
-- * All memory/io control signals (io,rd,wr) are valid only when vma is
-- high. They never activate when vma is inactive.
-- * Signals data_out and address are only valid when vma='1'. The high
-- address byte is 0x00 for all io accesses.
-- * Signal data_in should be valid by the end of the cycle after vma='1',
-- data is clocked in by the rising clock edge.
--
-- All signals are assumed to be synchronous to the master clock. Prevention of
-- metastability, if necessary, is up to you.
--
-- Signal reset needs to be active for just 1 clock cycle (it is sampled on a
-- positive clock edge and is subject to setup and hold times).
-- Once reset is deasserted, the first fetch at address 0x0000 will happen 4
-- cycles later.
--
-- Signal intr is sampled on all positive clock edges. If asserted when inte is
-- high, interrupts will be disabled, inta will be asserted high and a fetch
-- cycle will occur immediately after the current instruction ends execution,
-- except if intr was asserted at the last cycle of an instruction. In that case
-- it will be honored after the next instruction ends.
-- The fetched instruction will be executed normally, except that PC will not
-- be valid in any subsequent fetch cycles of the same instruction,
-- and will not be incremented (In practice, the same as the original 8080).
-- inta will remain high for the duration of the fetched instruction, including
-- fetch and execution time (in the original 8080 it was high only for the
-- opcode fetch cycle).
-- PC will not be autoincremented while inta is high, but it can be explicitly
-- modified (e.g. RST, CALL, etc.). Again, the same as the original.
-- Interrupts will be disabled upon assertion of inta, and remain disabled
-- until explicitly enabled by the program (as in the original).
-- If intr is asserted when inte is low, the interrupt will not be attended but
-- it will be registered in an int_pending flag, so it will be honored when
-- interrupts are enabled.
--
--
-- The above means that any instruction can be supplied in an inta cycle,
-- either single byte or multibyte. See the design notes.
--##############################################################################
architecture microcoded of light8080 is
-- addr_low: low byte of address
signal addr_low : std_logic_vector(7 downto 0);
-- IR: instruction register. some bits left unused.
signal IR : std_logic_vector(7 downto 0);
-- s_field: IR field, sss source reg code
signal s_field : std_logic_vector(2 downto 0);
-- d_field: IR field, ddd destination reg code
signal d_field : std_logic_vector(2 downto 0);
-- p_field: IR field, pp 16-bit reg pair code
signal p_field : std_logic_vector(1 downto 0);
-- rbh: 1 when p_field=11, used in reg bank addressing for 'special' regs
signal rbh : std_logic; -- 1 when P=11 (special case)
-- alu_op: uinst field, ALU operation code
signal alu_op : std_logic_vector(3 downto 0);
-- DI: data input to ALU block from data_in, unregistered
signal DI : std_logic_vector(7 downto 0);
-- uc_addr: microcode (ucode) address
signal uc_addr : std_logic_vector(7 downto 0);
-- next_uc_addr: computed next microcode address (uaddr++/jump/ret/fetch)
signal next_uc_addr : std_logic_vector(8 downto 0);
-- uc_jmp_addr: uinst field, absolute ucode jump address
signal uc_jmp_addr : std_logic_vector(7 downto 0);
-- uc_ret_address: ucode return address saved in previous jump
signal uc_ret_addr : std_logic_vector(7 downto 0);
-- addr_plus_1: uaddr + 1
signal addr_plus_1 : std_logic_vector(7 downto 0);
-- do_reset: reset, delayed 1 cycle -- used to reset the microcode sequencer
signal do_reset : std_logic;
-- uc_flags1: uinst field, encoded flag of group 1 (see ucode file)
signal uc_flags1 : std_logic_vector(2 downto 0);
-- uc_flags2: uinst field, encoded flag of group 2 (see ucode file)
signal uc_flags2 : std_logic_vector(2 downto 0);
-- uc_addr_sel: selection of next uc_addr, composition of 4 flags
signal uc_addr_sel : std_logic_vector(3 downto 0);
-- NOTE: see microcode file for information on flags
signal uc_jsr : std_logic; -- uinst field, decoded 'jsr' flag
signal uc_tjsr : std_logic; -- uinst field, decoded 'tjsr' flag
signal uc_decode : std_logic; -- uinst field, decoded 'decode' flag
signal uc_end : std_logic; -- uinst field, decoded 'end' flag
signal condition_reg :std_logic; -- registered tjst condition
-- condition: tjsr condition (computed ccc condition from '80 instructions)
signal condition : std_logic;
-- condition_sel: IR field, ccc condition code
signal condition_sel :std_logic_vector(2 downto 0);
signal uc_do_jmp : std_logic; -- uinst jump (jsr/tjsr) flag, pipelined
signal uc_do_ret : std_logic; -- ret flag, pipelined
signal uc_halt_flag : std_logic; -- uinst field, decoded 'halt' flag
signal uc_halt : std_logic; -- halt command
signal halt_reg : std_logic; -- halt status reg, output as 'halt' signal
signal uc_ei : std_logic; -- uinst field, decoded 'ei' flag
signal uc_di : std_logic; -- uinst field, decoded 'di' flag
signal inte_reg : std_logic; -- inte status reg, output as 'inte' signal
signal int_pending : std_logic; -- intr requested, inta not active yet
signal inta_reg : std_logic; -- inta status reg, output as 'inta'
signal clr_t1 : std_logic; -- uinst field, explicitly erase T1
signal do_clr_t1 : std_logic; -- clr_t1 pipelined
signal clr_t2 : std_logic; -- uinst field, explicitly erase T2
signal do_clr_t2 : std_logic; -- clr_t2 pipelined
signal ucode : std_logic_vector(31 downto 0); -- microcode word
signal ucode_field2 : std_logic_vector(24 downto 0); -- pipelined microcode
-- used to delay interrup enable for one entire instruction after EI
signal delayed_ei : std_logic;
-- microcode ROM : see design notes and microcode source file
type t_rom is array (0 to 511) of std_logic_vector(31 downto 0);
signal rom : t_rom := (
"00000000000000000000000000000000", -- 000
"00000000000001001000000001000100", -- 001
"00000000000001000000000001000100", -- 002
"10111101101001001000000001001101", -- 003
"10110110101001000000000001001101", -- 004
"00100000000000000000000000000000", -- 005
"00000000000000000000000000000000", -- 006
"11100100000000000000000000000000", -- 007
"00000000101010000000000000000000", -- 008
"00000100000100000000000001010111", -- 009
"00001000000000000000110000011001", -- 00a
"00000100000100000000000001010111", -- 00b
"00000000101010000000000010010111", -- 00c
"00001000000000000000110000011100", -- 00d
"00001000000000000000110000011111", -- 00e
"00000100000100000000000001010111", -- 00f
"00001000000000000000110000011111", -- 010
"00001000000000000000110000011100", -- 011
"00001000000000000000110000011111", -- 012
"00000000000110001000000001010111", -- 013
"00001000000000000000110000011111", -- 014
"00000100000110000000000001010111", -- 015
"00001000000000000000110000101110", -- 016
"00001000000000000000110000100010", -- 017
"00000100000000111000000001010111", -- 018
"00001000000000000000110000101110", -- 019
"00000000101000111000000010010111", -- 01a
"00001000000000000000110000100101", -- 01b
"00001000000000000000110000101110", -- 01c
"10111101101001100000000001001101", -- 01d
"10110110101001101000000001001101", -- 01e
"00000000100000101000000001010111", -- 01f
"00001000000000000000110000100010", -- 020
"00000100000000100000000001010111", -- 021
"00001000000000000000110000101110", -- 022
"00000000101000101000000010010111", -- 023
"10111101101001100000000001001101", -- 024
"10111010101001101000000001001101", -- 025
"00000000101000100000000010010111", -- 026
"00001000000000000000110000100101", -- 027
"00001000000000000000110000101000", -- 028
"00000100000000111000000001010111", -- 029
"00000000101000111000000010010111", -- 02a
"00001000000000000000110000101011", -- 02b
"00000000101000010000000000000000", -- 02c
"00000000000001010000000001010111", -- 02d
"00000000101000011000000000000000", -- 02e
"00000000000001011000000001010111", -- 02f
"00000000101000100000000000000000", -- 030
"00000000000000010000000001010111", -- 031
"00000000101000101000000000000000", -- 032
"00000000000000011000000001010111", -- 033
"00000000101001010000000000000000", -- 034
"00000000000000100000000001010111", -- 035
"00000000101001011000000000000000", -- 036
"00000100000000101000000001010111", -- 037
"00001000000000000000110000011111", -- 038
"00000100011000111000001101001100", -- 039
"00001000000000000000110000011111", -- 03a
"00000100011000111000001101001101", -- 03b
"00001000000000000000110000011111", -- 03c
"00000100011000111000001101001110", -- 03d
"00001000000000000000110000011111", -- 03e
"00000100011000111000001101001111", -- 03f
"00001000000000000000110000011111", -- 040
"00000100011000111100001101000100", -- 041
"00001000000000000000110000011111", -- 042
"00000100011000111100001101000101", -- 043
"00001000000000000000110000011111", -- 044
"00000100011000111100001101000110", -- 045
"00001000000000000000110000011111", -- 046
"00000100011000111000001110001110", -- 047
"00000000101010000000000000000000", -- 048
"00000100011000111000001101001100", -- 049
"00000000101010000000000000000000", -- 04a
"00000100011000111000001101001101", -- 04b
"00000000101010000000000000000000", -- 04c
"00000100011000111000001101001110", -- 04d
"00000000101010000000000000000000", -- 04e
"00000100011000111000001101001111", -- 04f
"00000000101010000000000000000000", -- 050
"00000100011000111100001101000100", -- 051
"00000000101010000000000000000000", -- 052
"00000100011000111100001101000101", -- 053
"00000000101010000000000000000000", -- 054
"00000100011000111100001101000110", -- 055
"00000000101010000000000000000000", -- 056
"00000100011000111000001110001110", -- 057
"00001000000000000000110000011001", -- 058
"00000100011000111000001101001100", -- 059
"00001000000000000000110000011001", -- 05a
"00000100011000111000001101001101", -- 05b
"00001000000000000000110000011001", -- 05c
"00000100011000111000001101001110", -- 05d
"00001000000000000000110000011001", -- 05e
"00000100011000111000001101001111", -- 05f
"00001000000000000000110000011001", -- 060
"00000100011000111100001101000100", -- 061
"00001000000000000000110000011001", -- 062
"00000100011000111100001101000101", -- 063
"00001000000000000000110000011001", -- 064
"00000100011000111100001101000110", -- 065
"00001000000000000000110000011001", -- 066
"00000100011000111000001110001110", -- 067
"10111100101100000000001001001101", -- 068
"00000100000000000000000000000000", -- 069
"00001000000000000000110000011001", -- 06a
"10111100000000000000001010001101", -- 06b
"00001000000000000000110000011100", -- 06c
"10111100011100000000001001001111", -- 06d
"00000100000000000000000000000000", -- 06e
"00001000000000000000110000011001", -- 06f
"11000000000000000000000000000000", -- 070
"10111100011001010000001010001111", -- 071
"00001000000000000000110000011100", -- 072
"10111100101110001000000001001101", -- 073
"10100100101110000000000001001101", -- 074
"10111100011110001000000001001111", -- 075
"10100100011110000000000001001111", -- 076
"00000000011110001000000000000000", -- 077
"00000000101000101000000101001100", -- 078
"00000000011110000000000000000000", -- 079
"00000100101000100000000101001101", -- 07a
"00000000101000111000000010101000", -- 07b
"00000100101000111000001101101000", -- 07c
"00000100101000111000000101000000", -- 07d
"00000100101000111000000101000001", -- 07e
"00000100101000111000000101000010", -- 07f
"00000100101000111000000101000011", -- 080
"00000100101000111000000001000111", -- 081
"00000100000000000000000100101100", -- 082
"00000100000000000000000100101101", -- 083
"00001000000000000000110000101110", -- 084
"00000000101001100000000000000000", -- 085
"00000000000001001000000001010111", -- 086
"00000000101001101000000000000000", -- 087
"00000100000001000000000001010111", -- 088
"00000100000000000000000000000000", -- 089
"00001000000000000000110000101110", -- 08a
"00010000000000000000100000000101", -- 08b
"00001000000000000000110000101110", -- 08c
"11000000101001000000000010010111", -- 08d
"00001000000000000000110000110100", -- 08e
"11000000101001001000000010010111", -- 08f
"00001000000000000000110000110100", -- 090
"00000000101001100000000000000000", -- 091
"00000000000001001000000001010111", -- 092
"00000000101001101000000000000000", -- 093
"00000100000001000000000001010111", -- 094
"00001000000000000000110000101110", -- 095
"00010000000000000000100000001101", -- 096
"00001000000000000000110000111001", -- 097
"00000000000001001000000001010111", -- 098
"00001000000000000000110000111001", -- 099
"00000100000001000000000001010111", -- 09a
"00010000000000000000100000010111", -- 09b
"11000000101001000000000010010111", -- 09c
"00001000000000000000110000110100", -- 09d
"11000000101001001000000010010111", -- 09e
"00001000000000000000110000110100", -- 09f
"11000000000001001000000001011111", -- 0a0
"00000100000001000000000001000100", -- 0a1
"00000000101000101000000000000000", -- 0a2
"00000000000001001000000001010111", -- 0a3
"00000000101000100000000000000000", -- 0a4
"00000100000001000000000001010111", -- 0a5
"11000000101110000000000010010111", -- 0a6
"00001000000000000000110000110100", -- 0a7
"11000000101110001000000010010111", -- 0a8
"00001000000000000000110000110100", -- 0a9
"00000100000000000000000000000000", -- 0aa
"11000000101000111000000010010111", -- 0ab
"00001000000000000000110000110100", -- 0ac
"11000000000000000000000010110000", -- 0ad
"00001000000000000000110000110100", -- 0ae
"00000100000000000000000000000000", -- 0af
"00001000000000000000110000111001", -- 0b0
"00000000000110001000000001010111", -- 0b1
"00001000000000000000110000111001", -- 0b2
"00000100000110000000000001010111", -- 0b3
"00001000000000000000110000111001", -- 0b4
"00000000000000110000001101010111", -- 0b5
"00001000000000000000110000111001", -- 0b6
"00000100000000111000000001010111", -- 0b7
"00001000000000000000110000111001", -- 0b8
"00000000000001100000000001010111", -- 0b9
"00001000000000000000110000111001", -- 0ba
"00000000000001101000000001010111", -- 0bb
"11000000101000100000000010010111", -- 0bc
"00001000000000000000110000110100", -- 0bd
"11000000101000101000000010010111", -- 0be
"00001000000000000000110000110100", -- 0bf
"00000000101001100000000000000000", -- 0c0
"00000000000000101000000001010111", -- 0c1
"00000000101001101000000000000000", -- 0c2
"00000100000000100000000001010111", -- 0c3
"00000000101000101000000000000000", -- 0c4
"00000000000001111000000001010111", -- 0c5
"00000000101000100000000000000000", -- 0c6
"00000100000001110000000001010111", -- 0c7
"01100100000000000000000000000000", -- 0c8
"01000100000000000000000000000000", -- 0c9
"00000000000001101000000001010111", -- 0ca
"00001000000000000000110000011111", -- 0cb
"00000000000001100000000001010111", -- 0cc
"00000000000000000000000000000000", -- 0cd
"00000001101001100000000000000000", -- 0ce
"10010110101001101000000000000000", -- 0cf
"00000100100000111000000001010111", -- 0d0
"00000000000001101000000001010111", -- 0d1
"00001000000000000000110000011111", -- 0d2
"00000000000001100000000001010111", -- 0d3
"00000000101000111000000010010111", -- 0d4
"00000001101001100000000000000000", -- 0d5
"10011010101001101000000000000000", -- 0d6
"00000100000000000000000000000000", -- 0d7
"11100100000000000000000000000000", -- 0d8
"00000001101000101000000000000000", -- 0d9
"00010110101000100000000000000000", -- 0da
"00001100100001010000000001010111", -- 0db
"00000001101000101000000000000000", -- 0dc
"00011010101000100000000000000000", -- 0dd
"00000100000000000000000000000000", -- 0de
"10111101101001001000000001001101", -- 0df
"10110110101001000000000001001101", -- 0e0
"00001100100000000000000010010111", -- 0e1
"00000001101001100000000000000000", -- 0e2
"00010110101001101000000000000000", -- 0e3
"00001100100000000000000000000000", -- 0e4
"00000001101001100000000000000000", -- 0e5
"00011010101001101000000000000000", -- 0e6
"00000100000000000000000000000000", -- 0e7
"00000001101110001000000000000000", -- 0e8
"00010110101110000000000000000000", -- 0e9
"00001100100000000000000000000000", -- 0ea
"00000001101110001000000000000000", -- 0eb
"00011010101110000000000000000000", -- 0ec
"00000100000000000000000000000000", -- 0ed
"10111101101001001000000001001101", -- 0ee
"10110110101001000000000001001101", -- 0ef
"00000000100001100000000001010111", -- 0f0
"10111101101001001000000001001101", -- 0f1
"10110110101001000000000001001101", -- 0f2
"00001100100001101000000001010111", -- 0f3
"10111100011001111000000001001111", -- 0f4
"10100000011001110000000001001111", -- 0f5
"00000001101001111000000000000000", -- 0f6
"00011010101001110000000000000000", -- 0f7
"00001100000000000000000000000000", -- 0f8
"10111101101001111000000001001101", -- 0f9
"10110110101001110000000001001101", -- 0fa
"00001100100000000000000000000000", -- 0fb
"00000100000000000000000000000000", -- 0fc
"00000100000000000000000000000000", -- 0fd
"00000100000000000000000000000000", -- 0fe
"00000100000000000000000000000000", -- 0ff
"00001000000000000000100000001001", -- 100
"00001000000000000000000000010010", -- 101
"00001000000000000000000000101010", -- 102
"00001000000000000000010000110011", -- 103
"00001000000000000000010000101000", -- 104
"00001000000000000000010000101101", -- 105
"00001000000000000000000000001110", -- 106
"00001000000000000000010000111101", -- 107
"00001000000000000000000000000000", -- 108
"00001000000000000000010000110111", -- 109
"00001000000000000000000000101000", -- 10a
"00001000000000000000010000110101", -- 10b
"00001000000000000000010000101000", -- 10c
"00001000000000000000010000101101", -- 10d
"00001000000000000000000000001110", -- 10e
"00001000000000000000010000111110", -- 10f
"00001000000000000000000000000000", -- 110
"00001000000000000000000000010010", -- 111
"00001000000000000000000000101010", -- 112
"00001000000000000000010000110011", -- 113
"00001000000000000000010000101000", -- 114
"00001000000000000000010000101101", -- 115
"00001000000000000000000000001110", -- 116
"00001000000000000000010000111111", -- 117
"00001000000000000000000000000000", -- 118
"00001000000000000000010000110111", -- 119
"00001000000000000000000000101000", -- 11a
"00001000000000000000010000110101", -- 11b
"00001000000000000000010000101000", -- 11c
"00001000000000000000010000101101", -- 11d
"00001000000000000000000000001110", -- 11e
"00001000000000000000100000000000", -- 11f
"00001000000000000000000000000000", -- 120
"00001000000000000000000000010010", -- 121
"00001000000000000000000000100010", -- 122
"00001000000000000000010000110011", -- 123
"00001000000000000000010000101000", -- 124
"00001000000000000000010000101101", -- 125
"00001000000000000000000000001110", -- 126
"00001000000000000000010000111011", -- 127
"00001000000000000000000000000000", -- 128
"00001000000000000000010000110111", -- 129
"00001000000000000000000000011100", -- 12a
"00001000000000000000010000110101", -- 12b
"00001000000000000000010000101000", -- 12c
"00001000000000000000010000101101", -- 12d
"00001000000000000000000000001110", -- 12e
"00001000000000000000100000000001", -- 12f
"00001000000000000000000000000000", -- 130
"00001000000000000000000000010010", -- 131
"00001000000000000000000000011001", -- 132
"00001000000000000000010000110011", -- 133
"00001000000000000000010000101010", -- 134
"00001000000000000000010000101111", -- 135
"00001000000000000000000000010000", -- 136
"00001000000000000000100000000011", -- 137
"00001000000000000000000000000000", -- 138
"00001000000000000000010000110111", -- 139
"00001000000000000000000000010110", -- 13a
"00001000000000000000010000110101", -- 13b
"00001000000000000000010000101000", -- 13c
"00001000000000000000010000101101", -- 13d
"00001000000000000000000000001110", -- 13e
"00001000000000000000100000000010", -- 13f
"00001000000000000000000000001000", -- 140
"00001000000000000000000000001000", -- 141
"00001000000000000000000000001000", -- 142
"00001000000000000000000000001000", -- 143
"00001000000000000000000000001000", -- 144
"00001000000000000000000000001000", -- 145
"00001000000000000000000000001010", -- 146
"00001000000000000000000000001000", -- 147
"00001000000000000000000000001000", -- 148
"00001000000000000000000000001000", -- 149
"00001000000000000000000000001000", -- 14a
"00001000000000000000000000001000", -- 14b
"00001000000000000000000000001000", -- 14c
"00001000000000000000000000001000", -- 14d
"00001000000000000000000000001010", -- 14e
"00001000000000000000000000001000", -- 14f
"00001000000000000000000000001000", -- 150
"00001000000000000000000000001000", -- 151
"00001000000000000000000000001000", -- 152
"00001000000000000000000000001000", -- 153
"00001000000000000000000000001000", -- 154
"00001000000000000000000000001000", -- 155
"00001000000000000000000000001010", -- 156
"00001000000000000000000000001000", -- 157
"00001000000000000000000000001000", -- 158
"00001000000000000000000000001000", -- 159
"00001000000000000000000000001000", -- 15a
"00001000000000000000000000001000", -- 15b
"00001000000000000000000000001000", -- 15c
"00001000000000000000000000001000", -- 15d
"00001000000000000000000000001010", -- 15e
"00001000000000000000000000001000", -- 15f
"00001000000000000000000000001000", -- 160
"00001000000000000000000000001000", -- 161
"00001000000000000000000000001000", -- 162
"00001000000000000000000000001000", -- 163
"00001000000000000000000000001000", -- 164
"00001000000000000000000000001000", -- 165
"00001000000000000000000000001010", -- 166
"00001000000000000000000000001000", -- 167
"00001000000000000000000000001000", -- 168
"00001000000000000000000000001000", -- 169
"00001000000000000000000000001000", -- 16a
"00001000000000000000000000001000", -- 16b
"00001000000000000000000000001000", -- 16c
"00001000000000000000000000001000", -- 16d
"00001000000000000000000000001010", -- 16e
"00001000000000000000000000001000", -- 16f
"00001000000000000000000000001100", -- 170
"00001000000000000000000000001100", -- 171
"00001000000000000000000000001100", -- 172
"00001000000000000000000000001100", -- 173
"00001000000000000000000000001100", -- 174
"00001000000000000000000000001100", -- 175
"00001000000000000000110000011000", -- 176
"00001000000000000000000000001100", -- 177
"00001000000000000000000000001000", -- 178
"00001000000000000000000000001000", -- 179
"00001000000000000000000000001000", -- 17a
"00001000000000000000000000001000", -- 17b
"00001000000000000000000000001000", -- 17c
"00001000000000000000000000001000", -- 17d
"00001000000000000000000000001010", -- 17e
"00001000000000000000000000001000", -- 17f
"00001000000000000000010000001000", -- 180
"00001000000000000000010000001000", -- 181
"00001000000000000000010000001000", -- 182
"00001000000000000000010000001000", -- 183
"00001000000000000000010000001000", -- 184
"00001000000000000000010000001000", -- 185
"00001000000000000000010000011000", -- 186
"00001000000000000000010000001000", -- 187
"00001000000000000000010000001010", -- 188
"00001000000000000000010000001010", -- 189
"00001000000000000000010000001010", -- 18a
"00001000000000000000010000001010", -- 18b
"00001000000000000000010000001010", -- 18c
"00001000000000000000010000001010", -- 18d
"00001000000000000000010000011010", -- 18e
"00001000000000000000010000001010", -- 18f
"00001000000000000000010000001100", -- 190
"00001000000000000000010000001100", -- 191
"00001000000000000000010000001100", -- 192
"00001000000000000000010000001100", -- 193
"00001000000000000000010000001100", -- 194
"00001000000000000000010000001100", -- 195
"00001000000000000000010000011100", -- 196
"00001000000000000000010000001100", -- 197
"00001000000000000000010000001110", -- 198
"00001000000000000000010000001110", -- 199
"00001000000000000000010000001110", -- 19a
"00001000000000000000010000001110", -- 19b
"00001000000000000000010000001110", -- 19c
"00001000000000000000010000001110", -- 19d
"00001000000000000000010000011110", -- 19e
"00001000000000000000010000001110", -- 19f
"00001000000000000000010000010000", -- 1a0
"00001000000000000000010000010000", -- 1a1
"00001000000000000000010000010000", -- 1a2
"00001000000000000000010000010000", -- 1a3
"00001000000000000000010000010000", -- 1a4
"00001000000000000000010000010000", -- 1a5
"00001000000000000000010000100000", -- 1a6
"00001000000000000000010000010000", -- 1a7
"00001000000000000000010000010010", -- 1a8
"00001000000000000000010000010010", -- 1a9
"00001000000000000000010000010010", -- 1aa
"00001000000000000000010000010010", -- 1ab
"00001000000000000000010000010010", -- 1ac
"00001000000000000000010000010010", -- 1ad
"00001000000000000000010000100010", -- 1ae
"00001000000000000000010000010010", -- 1af
"00001000000000000000010000010100", -- 1b0
"00001000000000000000010000010100", -- 1b1
"00001000000000000000010000010100", -- 1b2
"00001000000000000000010000010100", -- 1b3
"00001000000000000000010000010100", -- 1b4
"00001000000000000000010000010100", -- 1b5
"00001000000000000000010000100100", -- 1b6
"00001000000000000000010000010100", -- 1b7
"00001000000000000000010000010110", -- 1b8
"00001000000000000000010000010110", -- 1b9
"00001000000000000000010000010110", -- 1ba
"00001000000000000000010000010110", -- 1bb
"00001000000000000000010000010110", -- 1bc
"00001000000000000000010000010110", -- 1bd
"00001000000000000000010000100110", -- 1be
"00001000000000000000010000010110", -- 1bf
"00001000000000000000100000011011", -- 1c0
"00001000000000000000100000110000", -- 1c1
"00001000000000000000100000001010", -- 1c2
"00001000000000000000100000000100", -- 1c3
"00001000000000000000100000010101", -- 1c4
"00001000000000000000100000100110", -- 1c5
"00001000000000000000000000111000", -- 1c6
"00001000000000000000100000011100", -- 1c7
"00001000000000000000100000011011", -- 1c8
"00001000000000000000100000010111", -- 1c9
"00001000000000000000100000001010", -- 1ca
"00001000000000000000000000000000", -- 1cb
"00001000000000000000100000010101", -- 1cc
"00001000000000000000100000001100", -- 1cd
"00001000000000000000000000111010", -- 1ce
"00001000000000000000100000011100", -- 1cf
"00001000000000000000100000011011", -- 1d0
"00001000000000000000100000110000", -- 1d1
"00001000000000000000100000001010", -- 1d2
"00001000000000000000110000010001", -- 1d3
"00001000000000000000100000010101", -- 1d4
"00001000000000000000100000100110", -- 1d5
"00001000000000000000000000111100", -- 1d6
"00001000000000000000100000011100", -- 1d7
"00001000000000000000100000011011", -- 1d8
"00001000000000000000000000000000", -- 1d9
"00001000000000000000100000001010", -- 1da
"00001000000000000000110000001010", -- 1db
"00001000000000000000100000010101", -- 1dc
"00001000000000000000000000000000", -- 1dd
"00001000000000000000000000111110", -- 1de
"00001000000000000000100000011100", -- 1df
"00001000000000000000100000011011", -- 1e0
"00001000000000000000100000110000", -- 1e1
"00001000000000000000100000001010", -- 1e2
"00001000000000000000100000111000", -- 1e3
"00001000000000000000100000010101", -- 1e4
"00001000000000000000100000100110", -- 1e5
"00001000000000000000010000000000", -- 1e6
"00001000000000000000100000011100", -- 1e7
"00001000000000000000100000011011", -- 1e8
"00001000000000000000100000100010", -- 1e9
"00001000000000000000100000001010", -- 1ea
"00001000000000000000000000101100", -- 1eb
"00001000000000000000100000010101", -- 1ec
"00001000000000000000000000000000", -- 1ed
"00001000000000000000010000000010", -- 1ee
"00001000000000000000100000011100", -- 1ef
"00001000000000000000100000011011", -- 1f0
"00001000000000000000100000110100", -- 1f1
"00001000000000000000100000001010", -- 1f2
"00001000000000000000110000001001", -- 1f3
"00001000000000000000100000010101", -- 1f4
"00001000000000000000100000101011", -- 1f5
"00001000000000000000010000000100", -- 1f6
"00001000000000000000100000011100", -- 1f7
"00001000000000000000100000011011", -- 1f8
"00001000000000000000110000000100", -- 1f9
"00001000000000000000100000001010", -- 1fa
"00001000000000000000110000001000", -- 1fb
"00001000000000000000100000010101", -- 1fc
"00001000000000000000000000000000", -- 1fd
"00001000000000000000010000000110", -- 1fe
"00001000000000000000100000011100" -- 1ff
);
-- end of microcode ROM
signal load_al : std_logic; -- uinst field, load AL reg from rbank
signal load_addr : std_logic; -- uinst field, enable external addr reg load
signal load_t1 : std_logic; -- uinst field, load reg T1
signal load_t2 : std_logic; -- uinst field, load reg T2
signal mux_in : std_logic; -- uinst field, T1/T2 input data selection
signal load_do : std_logic; -- uinst field, pipelined, load DO reg
-- rb_addr_sel: uinst field, rbank address selection: (sss,ddd,pp,ra_field)
signal rb_addr_sel : std_logic_vector(1 downto 0);
-- ra_field: uinst field, explicit reg bank address
signal ra_field : std_logic_vector(3 downto 0);
signal rbank_data : std_logic_vector(7 downto 0); -- rbank output
signal alu_output : std_logic_vector(7 downto 0); -- ALU output
-- data_output: datapath output: ALU output vs. F reg
signal data_output : std_logic_vector(7 downto 0);
signal T1 : std_logic_vector(7 downto 0); -- T1 reg (ALU operand)
signal T2 : std_logic_vector(7 downto 0); -- T2 reg (ALU operand)
-- alu_input: data loaded into T1, T2: rbank data vs. DI
signal alu_input : std_logic_vector(7 downto 0);
signal we_rb : std_logic; -- uinst field, commands a write to the rbank
signal inhibit_pc_increment : std_logic; -- avoid PC changes (during INTA)
signal rbank_rd_addr: std_logic_vector(3 downto 0); -- rbank rd addr
signal rbank_wr_addr: std_logic_vector(3 downto 0); -- rbank wr addr
signal DO : std_logic_vector(7 downto 0); -- data output reg
-- Register bank as an array of 16 bytes.
-- This will be implemented as asynchronous LUT RAM in those devices where this
-- feature is available (Xilinx) and as multiplexed registers where it isn't
-- (Altera).
type t_reg_bank is array(0 to 15) of std_logic_vector(7 downto 0);
-- Register bank : BC, DE, HL, AF, [PC, XY, ZW, SP]
signal rbank : t_reg_bank;
signal flag_reg : std_logic_vector(7 downto 0); -- F register
-- flag_pattern: uinst field, F update pattern: which flags are updated
signal flag_pattern : std_logic_vector(1 downto 0);
signal flag_s : std_logic; -- new computed S flag
signal flag_z : std_logic; -- new computed Z flag
signal flag_p : std_logic; -- new computed P flag
signal flag_cy : std_logic; -- new computed C flag
signal flag_cy_1 : std_logic; -- C flag computed from arith/logic operation
signal flag_cy_2 : std_logic; -- C flag computed from CPC circuit
signal do_cy_op : std_logic; -- ALU explicit CY operation (CPC, etc.)
signal do_cy_op_d : std_logic; -- do_cy_op, pipelined
signal do_cpc : std_logic; -- ALU operation is CPC
signal do_cpc_d : std_logic; -- do_cpc, pipelined
signal do_daa : std_logic; -- ALU operation is DAA
signal clear_cy : std_logic; -- Instruction unconditionally clears CY
signal clear_ac : std_logic; -- Instruction unconditionally clears AC
signal set_ac : std_logic; -- Instruction unconditionally sets AC
signal flag_ac : std_logic; -- New computed half carry (AC) flag
signal flag_ac_daa : std_logic; -- AC flag computed in the special case of DAA
signal flag_ac_and : std_logic; -- AC flag computed in the special case of AN*
-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)
signal flag_aux_cy : std_logic;
signal load_psw : std_logic; -- load F register
-- aux carry computation and control signals
signal use_aux : std_logic; -- decoded from flags in 1st phase
signal use_aux_cy : std_logic; -- 2nd phase signal
signal reg_aux_cy : std_logic;
signal aux_cy_in : std_logic;
signal set_aux_cy : std_logic;
signal set_aux : std_logic;
-- ALU control signals -- together they select ALU operation
signal alu_fn : std_logic_vector(1 downto 0);
signal use_logic : std_logic; -- logic/arith mux control
signal mux_fn : std_logic_vector(1 downto 0);
signal use_psw : std_logic; -- ALU/F mux control
-- ALU arithmetic operands and result
signal arith_op1 : std_logic_vector(8 downto 0);
signal arith_op2 : std_logic_vector(8 downto 0);
signal arith_op2_sgn: std_logic_vector(8 downto 0);
signal arith_res : std_logic_vector(8 downto 0);
signal arith_res8 : std_logic_vector(7 downto 0);
-- ALU DAA intermediate signals (DAA has fully dedicated logic)
signal daa_res9 : std_logic_vector(8 downto 0);
signal daa_test1 : std_logic;
signal daa_test1a : std_logic;
signal daa_test2 : std_logic;
signal daa_test2a : std_logic;
signal arith_daa_res :std_logic_vector(7 downto 0);
signal cy_daa : std_logic;
signal acc_low_gt9 : std_logic;
signal acc_high_gt9 : std_logic;
signal acc_high_ge9 : std_logic;
signal daa_adjust : std_logic_vector(8 downto 0);
-- ALU CY flag intermediate signals
signal cy_in_sgn : std_logic;
signal cy_in : std_logic;
signal cy_in_gated : std_logic;
signal cy_adder : std_logic;
signal cy_arith : std_logic;
signal cy_shifter : std_logic;
-- ALU intermediate results
signal logic_res : std_logic_vector(7 downto 0);
signal shift_res : std_logic_vector(7 downto 0);
signal alu_mux1 : std_logic_vector(7 downto 0);
begin
DI <= data_in;
process(clk) -- IR register, load when uc_decode flag activates
begin
if clk'event and clk='1' then
if uc_decode = '1' then
IR <= DI;
end if;
end if;
end process;
s_field <= IR(2 downto 0); -- IR field extraction : sss reg code
d_field <= IR(5 downto 3); -- ddd reg code
p_field <= IR(5 downto 4); -- pp 16-bit reg pair code
--##############################################################################
-- Microcode sequencer
process(clk) -- do_reset is reset delayed 1 cycle
begin
if clk'event and clk='1' then
do_reset <= reset;
end if;
end process;
uc_flags1 <= ucode(31 downto 29);
uc_flags2 <= ucode(28 downto 26);
-- microcode address control flags are gated by do_reset (reset has priority)
uc_do_ret <= '1' when uc_flags2 = "011" and do_reset = '0' else '0';
uc_jsr <= '1' when uc_flags2 = "010" and do_reset = '0' else '0';
uc_tjsr <= '1' when uc_flags2 = "100" and do_reset = '0' else '0';
uc_decode <= '1' when uc_flags1 = "001" and do_reset = '0' else '0';
uc_end <= '1' when (uc_flags2 = "001" or (uc_tjsr='1' and condition_reg='0'))
and do_reset = '0' else '0';
-- other microinstruction flags are decoded
uc_halt_flag <= '1' when uc_flags1 = "111" else '0';
uc_halt <= '1' when uc_halt_flag='1' and inta_reg='0' else '0';
uc_ei <= '1' when uc_flags1 = "011" else '0';
uc_di <= '1' when uc_flags1 = "010" or inta_reg='1' else '0';
-- clr_t1/2 clears T1/T2 when explicitly commanded; T2 and T1 clear implicitly
-- at the end of each instruction (by uc_decode)
clr_t2 <= '1' when uc_flags2 = "001" else '0';
clr_t1 <= '1' when uc_flags1 = "110" else '0';
use_aux <= '1' when uc_flags1 = "101" else '0';
set_aux <= '1' when uc_flags2 = "111" else '0';
load_al <= ucode(24);
load_addr <= ucode(25);
do_cy_op_d <= '1' when ucode(5 downto 2)="1011" else '0'; -- decode CY ALU op
do_cpc_d <= ucode(0); -- decode CPC ALU op; valid only when do_cy_op_d='1'
-- uinst jump command, either unconditional or on a given condition
uc_do_jmp <= uc_jsr or (uc_tjsr and condition_reg);
vma <= load_addr; -- addr is valid, either for memmory or io
-- assume the only uinst that does memory access in the range 0..f is 'fetch'
fetch <= '1' when uc_addr(7 downto 4)=X"0" and load_addr='1' else '0';
-- external bus interface control signals
io <= '1' when uc_flags1="100" else '0'; -- IO access (vs. memory)
rd <= '1' when uc_flags2="101" else '0'; -- RD access
wr <= '1' when uc_flags2="110" else '0'; -- WR access
uc_jmp_addr <= ucode(11 downto 10) & ucode(5 downto 0);
uc_addr_sel <= uc_do_ret & uc_do_jmp & uc_decode & uc_end;
addr_plus_1 <= uc_addr + 1;
-- TODO simplify this!!
-- NOTE: when end='1' we jump either to the FETCH ucode ot to the HALT ucode
-- depending on the value of the halt signal.
-- We use the unregistered uc_halt instead of halt_reg because otherwise #end
-- should be on the cycle following #halt, wasting a cycle.
-- This means that the flag #halt has to be used with #end or will be ignored.
with uc_addr_sel select
next_uc_addr <= '0'&uc_ret_addr when "1000", -- ret
'0'&uc_jmp_addr when "0100", -- jsr/tjsr
'0'&addr_plus_1 when "0000", -- uaddr++
"000000"&uc_halt&"11"
when "0001", -- end: go to fetch/halt uaddr
'1'&DI when others; -- decode fetched address
-- Note how we used DI (containing instruction opcode) as a microcode address
-- read microcode rom
process (clk)
begin
if clk'event and clk='1' then
ucode <= rom(conv_integer(next_uc_addr));
end if;
end process;
-- microcode address register
process (clk)
begin
if clk'event and clk='1' then
if reset = '1' then
uc_addr <= X"00";
else
uc_addr <= next_uc_addr(7 downto 0);
end if;
end if;
end process;
-- ucode address 1-level 'return stack'
process (clk)
begin
if clk'event and clk='1' then
if reset = '1' then
uc_ret_addr <= X"00";
elsif uc_do_jmp='1' then
uc_ret_addr <= addr_plus_1;
end if;
end if;
end process;
alu_op <= ucode(3 downto 0);
-- pipeline uinst field2 for 1-cycle delayed execution.
-- note the same rbank addr field is used in cycles 1 and 2; this enforces
-- some constraints on uinst programming but simplifies the system.
process(clk)
begin
if clk'event and clk='1' then
ucode_field2 <= do_cy_op_d & do_cpc_d & clr_t2 & clr_t1 &
set_aux & use_aux & rbank_rd_addr &
ucode(14 downto 4) & alu_op;
end if;
end process;
--#### HALT logic
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' or int_pending = '1' then --inta_reg
halt_reg <= '0';
else
if uc_halt = '1' then
halt_reg <= '1';
end if;
end if;
end if;
end process;
halt <= halt_reg;
--#### INTE logic -- inte_reg = '1' means interrupts ENABLED
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
inte_reg <= '0';
delayed_ei <= '0';
else
if (uc_di='1' or uc_ei='1') and uc_end='1' then
--inte_reg <= uc_ei;
delayed_ei <= uc_ei; -- FIXME DI must not be delayed
end if;
if uc_end = '1' then -- at the last cycle of every instruction...
if uc_di='1' then -- ...disable interrupts if the instruction is DI...
inte_reg <= '0';
else
-- ...of enable interrupts after the instruction following EI
inte_reg <= delayed_ei;
end if;
end if;
end if;
end if;
end process;
inte <= inte_reg;
-- interrupts are ignored when inte='0' but they are registered and will be
-- honored when interrupts are enabled
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
int_pending <= '0';
else
-- intr will raise int_pending only if inta has not been asserted.
-- Otherwise, if intr overlapped inta, we'd enter a microcode endless
-- loop, executing the interrupt vector again and again.
if intr='1' and inte_reg='1' and int_pending='0' and inta_reg='0' then
int_pending <= '1';
else
-- int_pending is cleared when we're about to service the interrupt,
-- that is when interrupts are enabled and the current instruction ends.
if inte_reg = '1' and uc_end='1' then
int_pending <= '0';
end if;
end if;
end if;
end if;
end process;
--#### INTA logic
-- INTA goes high from END to END, that is for the entire time the instruction
-- takes to fetch and execute; in the original 8080 it was asserted only for
-- the M1 cycle.
-- All instructions can be used in an inta cycle, including XTHL which was
-- forbidden in the original 8080.
-- It's up to you figuring out which cycle is which in multibyte instructions.
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
inta_reg <= '0';
else
if int_pending = '1' and uc_end='1' then
-- enter INTA state
inta_reg <= '1';
else
-- exit INTA state
-- NOTE: don't reset inta when exiting halt state (uc_halt_flag='1').
-- If we omit this condition, when intr happens on halt state, inta
-- will only last for 1 cycle, because in halt state uc_end is
-- always asserted.
if uc_end = '1' and uc_halt_flag='0' then
inta_reg <= '0';
end if;
end if;
end if;
end if;
end process;
inta <= inta_reg;
--##############################################################################
-- Datapath
-- extract pipelined microcode fields
ra_field <= ucode(18 downto 15);
load_t1 <= ucode(23);
load_t2 <= ucode(22);
mux_in <= ucode(21);
rb_addr_sel <= ucode(20 downto 19);
load_do <= ucode_field2(7);
set_aux_cy <= ucode_field2(20);
do_clr_t1 <= ucode_field2(21);
do_clr_t2 <= ucode_field2(22);
-- T1 register
process (clk)
begin
if clk'event and clk='1' then
if reset = '1' or uc_decode = '1' or do_clr_t1='1' then
T1 <= X"00";
else
if load_t1 = '1' then
T1 <= alu_input;
end if;
end if;
end if;
end process;
-- T2 register
process (clk)
begin
if clk'event and clk='1' then
if reset = '1' or uc_decode = '1' or do_clr_t2='1' then
T2 <= X"00";
else
if load_t2 = '1' then
T2 <= alu_input;
end if;
end if;
end if;
end process;
-- T1/T2 input data mux
alu_input <= rbank_data when mux_in = '1' else DI;
-- register bank address mux logic
rbh <= '1' when p_field = "11" else '0';
with rb_addr_sel select
rbank_rd_addr <= ra_field when "00",
"0"&s_field when "01",
"0"&d_field when "10",
rbh&p_field&ra_field(0) when others;
-- RBank writes are inhibited in INTA state, but only for PC increments.
inhibit_pc_increment <= '1' when inta_reg='1' and use_aux_cy='1'
and rbank_wr_addr(3 downto 1) = "100"
else '0';
we_rb <= ucode_field2(6) and not inhibit_pc_increment;
-- Register bank logic
-- NOTE: read is asynchronous, while write is synchronous; but note also
-- that write phase for a given uinst happens the cycle after the read phase.
-- This way we give the ALU time to do its job.
rbank_wr_addr <= ucode_field2(18 downto 15);
process(clk)
begin
if clk'event and clk='1' then
if we_rb = '1' then
rbank(conv_integer(rbank_wr_addr)) <= alu_output;
end if;
end if;
end process;
rbank_data <= rbank(conv_integer(rbank_rd_addr));
-- should we read F register or ALU output?
use_psw <= '1' when ucode_field2(5 downto 4)="11" else '0';
data_output <= flag_reg when use_psw = '1' else alu_output;
process (clk)
begin
if clk'event and clk='1' then
if load_do = '1' then
DO <= data_output;
end if;
end if;
end process;
--##############################################################################
-- ALU
alu_fn <= ucode_field2(1 downto 0);
use_logic <= ucode_field2(2);
mux_fn <= ucode_field2(4 downto 3);
--#### make sure this is "00" in the microcode when no F updates should happen!
flag_pattern <= ucode_field2(9 downto 8);
use_aux_cy <= ucode_field2(19);
do_cpc <= ucode_field2(23);
do_cy_op <= ucode_field2(24);
do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0';
-- ucode_field2(14) will be set for those instructions that modify CY and AC
-- without following the standard rules -- AND, OR and XOR instructions.
-- Some instructions will unconditionally clear CY (AND, OR, XOR)
clear_cy <= ucode_field2(14);
-- Some instructions will unconditionally clear AC (OR, XOR)...
clear_ac <= '1' when ucode_field2(14) = '1' and
ucode_field2(5 downto 0) /= "000100"
else '0';
-- ...and some others unconditionally SET AC (AND)
set_ac <= '1' when ucode_field2(14) = '1' and
ucode_field2(5 downto 0) = "000100"
else '0';
aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1';
-- carry input selection: normal or aux (for 16 bit increments)?
cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in;
-- carry is not used (0) in add/sub operations
cy_in_gated <= cy_in and alu_fn(0);
--##### Adder/substractor
-- zero extend adder operands to 9 bits to ease CY output synthesis
-- use zero extension because we're only interested in cy from 7 to 8
arith_op1 <= '0' & T2;
arith_op2 <= '0' & T1;
-- The adder/substractor is done in 2 stages to help XSL synth it properly
-- Other codings result in 1 adder + a substractor + 1 mux
-- do 2nd op 2's complement if substracting...
arith_op2_sgn <= arith_op2 when alu_fn(1) = '0' else not arith_op2;
-- ...and complement cy input too
cy_in_sgn <= cy_in_gated when alu_fn(1) = '0' else not cy_in_gated;
-- once 2nd operand has been negated (or not) add operands normally
arith_res <= arith_op1 + arith_op2_sgn + cy_in_sgn;
-- take only 8 bits; 9th bit of adder is cy output
arith_res8 <= arith_res(7 downto 0);
cy_adder <= arith_res(8);
--##### DAA dedicated logic
-- Intel documentation does not cover many details of this instruction.
-- It has been experimentally determined that the following is the algorithm
-- employed in the actual original silicon:
--
-- 1.- If ACC(3..0) > 9 OR AC=1 then add 06h to ACC.
-- 2.- If (ACC(7..4) > 9 OR AC=1) OR (ACC(7..4)==9 AND (CY=1 OR ACC(3..0) > 9))
-- then add 60h to ACC.
-- Steps 1 and 2 are performed in parallel.
-- AC = 1 iif ACC(3..0) >= 10
-- CY = 1 if CY was already 1 OR
-- (ACC(7..4)>=9 AND ACC(3..0)>=10) OR
-- ACC(7..4)>=10
-- else CY is zero.
-- Note a DAA takes 2 cycles to complete; the adjutment addition is registered
-- so that it does not become the speed bottleneck. The DAA microcode will
-- execute two ALU DAA operations in a row before taking the ALU result.
-- '1' when ACC(3..0) > 9
acc_low_gt9 <= '1' when
conv_integer(arith_op2(3 downto 0)) > 9
--arith_op2(3 downto 2)="11" or arith_op2(3 downto 1)="101"
else '0';
-- '1' when ACC(7..4) > 9
acc_high_gt9 <= '1' when
conv_integer(arith_op2(7 downto 4)) > 9
--arith_op2(7 downto 6)="11" or arith_op2(7 downto 5)="101"
else '0';
-- '1' when ACC(7..4) >= 9
acc_high_ge9 <= '1' when
conv_integer(arith_op2(7 downto 4)) >= 9
else '0';
-- Condition for adding 6 to the low nibble
daa_test1 <= '1' when
acc_low_gt9='1' or -- A(3..0) > 9
flag_reg(4)='1' -- AC set
else '0';
-- condition for adding 6 to the high nibble
daa_test2 <= '1' when
(acc_high_gt9='1' or -- A(7..4) > 9
flag_reg(0)='1') or -- CY set
(daa_test2a = '1') -- condition below
else '0';
-- A(7..4)==9 && (CY or ACC(3..0)>9)
daa_test2a <= '1' when
arith_op2(7 downto 4)="1001" and (flag_reg(0)='1' or acc_low_gt9='1')
else '0';
-- daa_adjust is what we will add to ACC in order to adjust it to BCD
daa_adjust(3 downto 0) <= "0110" when daa_test1='1' else "0000";
daa_adjust(7 downto 4) <= "0110" when daa_test2='1' else "0000";
daa_adjust(8) <= '0';
-- The adder is registered so as to improve the clock rate. This takes the DAA
-- logic out of the critical speed path at the cost of an extra cycle for DAA,
-- which is a good compromise.
daa_adjutment_adder:
process(clk)
begin
if clk'event and clk='1' then
daa_res9 <= arith_op2 + daa_adjust;
end if;
end process daa_adjutment_adder;
-- AC flag raised if the low nibble was > 9, cleared otherwise.
flag_ac_daa <= acc_low_gt9;
-- CY flag raised if the condition above holds, otherwise keeps current value.
cy_daa <= '1' when
flag_reg(0)='1' or -- If CY is already 1, keep value
( (acc_high_ge9='1' and acc_low_gt9='1') or (acc_low_gt9='1') )
else '0';
-- DAA vs. adder mux
arith_daa_res <= daa_res9(7 downto 0) when do_daa='1' else arith_res8;
-- DAA vs. adder CY mux
cy_arith <= cy_daa when do_daa='1' else cy_adder;
--##### Logic operations block
logic_res <= T1 and T2 when alu_fn = "00" else
T1 xor T2 when alu_fn = "01" else
T1 or T2 when alu_fn = "10" else
not T1;
--##### Shifter
shifter:
for i in 1 to 6 generate
begin
shift_res(i) <= T1(i-1) when alu_fn(0) = '0' else T1(i+1);
end generate;
shift_res(0) <= T1(7) when alu_fn = "00" else -- rot left
cy_in when alu_fn = "10" else -- rot left through carry
T1(1); -- rot right
shift_res(7) <= T1(0) when alu_fn = "01" else -- rot right
cy_in when alu_fn = "11" else -- rot right through carry
T1(6); -- rot left
cy_shifter <= T1(7) when alu_fn(0) = '0' else -- left
T1(0); -- right
alu_mux1 <= logic_res when use_logic = '1' else shift_res;
with mux_fn select
alu_output <= alu_mux1 when "00",
arith_daa_res when "01",
not alu_mux1 when "10",
"00"&d_field&"000" when others; -- RST
--###### flag computation
flag_s <= alu_output(7);
flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor
alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));
flag_z <= '1' when alu_output=X"00" else '0';
-- AC is either the CY from bit 4 OR 0 if the instruction clears it implicitly
flag_ac <= flag_ac_and when set_ac = '1' and do_daa='0' else
'0' when clear_ac = '1' else
flag_ac_daa when do_daa = '1' else
(arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4));
-- AN* instructions deal with AC flag a bit differently
flag_ac_and <= T1(3) or T2(3);
-- CY comes from the adder or the shifter, or is 0 if the instruction
-- implicitly clears it.
flag_cy_1 <= '0' when clear_cy = '1' else
cy_arith when use_logic = '1' and clear_cy = '0' else
cy_shifter;
-- CY can also be explicitly set or complemented by STC and CMC
flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc
-- No do the actual CY update
flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;
flag_aux_cy <= cy_adder;
-- auxiliary carry reg
process(clk)
begin
if clk'event and clk='1' then
if reset='1' or uc_decode = '1' then
reg_aux_cy <= '1'; -- inits to 0 every instruction
else
reg_aux_cy <= flag_aux_cy;
end if;
end if;
end process;
-- load PSW from ALU (i.e. POP AF) or from flag signals
load_psw <= '1' when we_rb='1' and rbank_wr_addr="0110" else '0';
-- The F register has been split in two separate groupt that always update
-- together (C and all others).
-- F register, flags S,Z,AC,P
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
flag_reg(7) <= '0';
flag_reg(6) <= '0';
flag_reg(4) <= '0';
flag_reg(2) <= '0';
elsif flag_pattern(1) = '1' then
if load_psw = '1' then
flag_reg(7) <= alu_output(7);
flag_reg(6) <= alu_output(6);
flag_reg(4) <= alu_output(4);
flag_reg(2) <= alu_output(2);
else
flag_reg(7) <= flag_s;
flag_reg(6) <= flag_z;
flag_reg(4) <= flag_ac;
flag_reg(2) <= flag_p;
end if;
end if;
end if;
end procesS;
-- F register, flag C
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
flag_reg(0) <= '0';
elsif flag_pattern(0) = '1' then
if load_psw = '1' then
flag_reg(0) <= alu_output(0);
else
flag_reg(0) <= flag_cy;
end if;
end if;
end if;
end procesS;
flag_reg(5) <= '0'; -- constant flag
flag_reg(3) <= '0'; -- constant flag
flag_reg(1) <= '1'; -- constant flag
--##### Condition computation
condition_sel <= d_field(2 downto 0);
with condition_sel select
condition <=
not flag_reg(6) when "000", -- NZ
flag_reg(6) when "001", -- Z
not flag_reg(0) when "010", -- NC
flag_reg(0) when "011", -- C
not flag_reg(2) when "100", -- PO
flag_reg(2) when "101", -- PE
not flag_reg(7) when "110", -- P
flag_reg(7) when others;-- M
-- condition is registered to shorten the delay path; the extra 1-cycle
-- delay is not relevant because conditions are tested in the next instruction
-- at the earliest, and there's at least the fetch uinsts intervening.
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
condition_reg <= '0';
else
condition_reg <= condition;
end if;
end if;
end process;
-- low byte address register
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
addr_low <= X"00";
elsif load_al = '1' then
addr_low <= rbank_data;
end if;
end if;
end process;
-- note external address registers (high byte) are loaded directly from rbank
addr_out <= rbank_data & addr_low;
data_out <= DO;
end microcoded;
--------------------------------------------------------------------------------
-- Timing diagram 1: RD and WR cycles
--------------------------------------------------------------------------------
-- 1 2 3 4 5 6 7 8
-- __ __ __ __ __ __ __ __
-- clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
--
-- ==|=====|=====|=====|=====|=====|=====|=====|=====|
--
-- addr_o xxxxxxxxxxxxxx< ADR >xxxxxxxxxxx< ADR >xxxxxxxxxxx
--
-- data_i xxxxxxxxxxxxxxxxxxxx< Din >xxxxxxxxxxxxxxxxxxxxxxx
--
-- data_o xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx< Dout>xxxxxxxxxxx
-- _____ _____
-- vma_o ______________/ \___________/ \___________
-- _____
-- rd_o ______________/ \_____________________________
-- _____
-- wr_o ________________________________/ \___________
--
-- (functional diagram, actual time delays not shown)
--------------------------------------------------------------------------------
-- This diagram shows a read cycle and a write cycle back to back.
-- In clock edges (4) and (7), the address is loaded into the external
-- synchronous RAM address register.
-- In clock edge (5), read data is loaded into the CPU.
-- In clock edge (7), write data is loaded into the external synchronous RAM.
-- In actual operation, the CPU does about 1 rd/wr cycle for each 5 clock
-- cycles, which is a waste of RAM bandwidth.
--
| mit | 69b4401ea19eec07d7f873b9c65d55a7 | 0.681839 | 3.749918 | false | false | false | false |
timofonic/1541UltimateII | target/simulation/packages/vhdl_source/file_io_pkg.vhd | 4 | 9,512 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: File IO routines
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package file_io_pkg is
subtype t_byte is std_logic_vector(7 downto 0);
function nibbletohex(nibble : std_logic_vector(3 downto 0)) return character;
function hextonibble(c : character) return std_logic_vector;
function ishexchar(c : character) return boolean;
procedure vectohex(vec : std_logic_vector; str : out string);
function vectohex(vec : std_logic_vector; len : integer) return string;
procedure getcharfromfile(file myfile : text; l : inout line; stop : out boolean; hex : out character);
procedure getbytefromfile(file myfile : text; l : inout line; fileend : out boolean; dat : out t_byte);
type t_binary_file is file of integer;
type t_binary_file_handle is record
offset : integer range 0 to 4;
longvec : std_logic_vector(31 downto 0);
end record;
constant emptysp : string := " ";
procedure initrecord(rec : inout t_binary_file_handle);
procedure readbyte(file f : t_binary_file; b : out t_byte; rec : inout t_binary_file_handle);
procedure writebyte(file f : t_binary_file; b : in t_byte; rec : inout t_binary_file_handle);
procedure purge(file f : t_binary_file; rec : inout t_binary_file_handle);
procedure onoffchar(l : inout line; ena : std_logic; ch : character);
procedure onoffchar(l : inout line; ena : std_logic; ch, alt : character);
procedure hexout(l : inout line; ena : std_logic; vec : std_logic_vector; len : integer);
procedure write_s(variable li : inout line; s : string);
end;
package body file_io_pkg is
function nibbletohex(nibble : std_logic_vector(3 downto 0)) return character is
variable r : character := '?';
begin
case nibble is
when "0000" => r := '0';
when "0001" => r := '1';
when "0010" => r := '2';
when "0011" => r := '3';
when "0100" => r := '4';
when "0101" => r := '5';
when "0110" => r := '6';
when "0111" => r := '7';
when "1000" => r := '8';
when "1001" => r := '9';
when "1010" => r := 'a';
when "1011" => r := 'b';
when "1100" => r := 'c';
when "1101" => r := 'd';
when "1110" => r := 'e';
when "1111" => r := 'f';
when others => r := 'x';
end case;
return r;
end nibbletohex;
function hextonibble(c : character) return std_logic_vector is
variable z : std_logic_vector(3 downto 0);
begin
case c is
when '0' => z := "0000";
when '1' => z := "0001";
when '2' => z := "0010";
when '3' => z := "0011";
when '4' => z := "0100";
when '5' => z := "0101";
when '6' => z := "0110";
when '7' => z := "0111";
when '8' => z := "1000";
when '9' => z := "1001";
when 'a' => z := "1010";
when 'b' => z := "1011";
when 'c' => z := "1100";
when 'd' => z := "1101";
when 'e' => z := "1110";
when 'f' => z := "1111";
when 'A' => z := "1010";
when 'B' => z := "1011";
when 'C' => z := "1100";
when 'D' => z := "1101";
when 'E' => z := "1110";
when 'F' => z := "1111";
when others => z := "XXXX";
end case;
return z;
end hextonibble;
function ishexchar(c : character) return boolean is
begin
case c is
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7' => return true;
when '8'|'9'|'a'|'b'|'c'|'d'|'e'|'f' => return true;
when 'A'|'B'|'C'|'D'|'E'|'F' => return true;
when others => return false;
end case;
return false;
end ishexchar;
procedure vectohex(vec : std_logic_vector; str : out string) is
variable tempvec : std_logic_vector(str'length * 4 downto 1) := (others => '0');
variable j : integer;
variable myvec : std_logic_vector(vec'range);
variable len, mylow, myhigh : integer;
begin
myvec := vec;
len := str'length;
mylow := vec'low;
myhigh := vec'high;
if vec'length < tempvec'length then
tempvec(vec'length downto 1) := vec;
else
tempvec := vec(vec'low + tempvec'length - 1 downto vec'low);
end if;
for i in str'range loop
j := (str'right - i) * 4;
str(i) := nibbletohex(tempvec(j+4 downto j+1));
end loop;
end vectohex;
function vectohex(vec : std_logic_vector; len : integer) return string is
variable str : string(1 to len);
begin
vectohex(vec, str);
return str;
end vectohex;
procedure getcharfromfile(file myfile : text; l : inout line; stop : out boolean; hex : out character) is
variable good : boolean := false;
begin
while not(good) loop
read(l, hex, good);
if not(good) then
if endfile(myfile) then
stop := true;
hex := '1';
return;
end if;
readline(myfile, l);
end if;
end loop;
end getcharfromfile;
procedure getbytefromfile(file myfile : text; l : inout line; fileend : out boolean; dat : out t_byte) is
variable hex : character;
variable d : t_byte;
variable stop : boolean := false;
begin
d := x"00";
l1 : loop
getcharfromfile(myfile, l, stop, hex);
if stop or ishexchar(hex) then
exit l1;
end if;
end loop l1;
d(3 downto 0) := hextonibble(hex);
-- see if we can read another good hex char
getcharfromfile(myfile, l, stop, hex);
if not(stop) and ishexchar(hex) then
d(7 downto 4) := d(3 downto 0);
d(3 downto 0) := hextonibble(hex);
end if;
fileend := stop;
dat := d;
end getbytefromfile;
procedure onoffchar(l : inout line; ena : std_logic; ch : character) is
begin
if ena = '1' then
write(l, ch);
else
write(l, ' ');
end if;
end onoffchar;
procedure onoffchar(l : inout line; ena : std_logic; ch, alt : character) is
begin
if ena = '1' then
write(l, ch);
else
write(l, alt);
end if;
end onoffchar;
procedure hexout(l : inout line; ena : std_logic; vec : std_logic_vector; len : integer) is
begin
if ena = '1' then
write(l, vectohex(vec, len));
else
write(l, emptysp(1 to len));
end if;
end hexout;
procedure initrecord(rec : inout binaryfilerec) is
begin
rec.offset := 0;
rec.longvec := (others => '0');
end procedure;
procedure readbyte(file f : binary_file; b : out t_byte; rec : inout binaryfilerec) is
variable i : integer;
begin
if rec.offset = 0 then
read(f, i);
rec.longvec := std_logic_vector(to_unsigned(i, 32));
end if;
b := rec.longvec(7 downto 0);
rec.longvec := "00000000" & rec.longvec(31 downto 8); -- lsb first
if rec.offset = 3 then
rec.offset := 0;
else
rec.offset := rec.offset + 1;
end if;
end procedure;
procedure writebyte(file f : binary_file; b : in t_byte; rec : inout binaryfilerec) is
variable i : integer;
begin
rec.longvec(31 downto 24) := b;
if rec.offset = 3 then
i := to_integer(unsigned(rec.longvec));
write(f, i);
rec.offset := 0;
else
rec.offset := rec.offset + 1;
rec.longvec := "00000000" & rec.longvec(31 downto 8); -- lsb first
end if;
end procedure;
procedure purge(file f : binary_file; rec : inout binaryfilerec) is
variable i : integer;
begin
if rec.offset /= 0 then
i := to_integer(unsigned(rec.longvec));
write(f, i);
end if;
end procedure;
procedure write_s(variable li : inout line; s : string) is
begin
write(li, s);
end write_s;
end;
| gpl-3.0 | f3dcd77616405cc0149f33094098fb65 | 0.467935 | 3.904762 | false | false | false | false |
Fju/LeafySan | src/vhdl/interfaces/sram.vhdl | 1 | 1,843 | -----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : SRAM-Interface
-- Author : Jan Dürre
-- Last update : 22.07.2014
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity sram is
port(
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- sram connections
sram_ce_n : out std_ulogic;
sram_oe_n : out std_ulogic;
sram_we_n : out std_ulogic;
sram_ub_n : out std_ulogic;
sram_lb_n : out std_ulogic;
sram_addr : out std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0)
);
end sram;
architecture rtl of sram is
begin
-- constant
sram_oe_n <= '0';
sram_ub_n <= '0';
sram_lb_n <= '0';
-- chip enable only when cs = '1'
sram_ce_n <= not(iobus_cs);
-- set we only when cs = '1' and wr = '1', otherwise data might be written over
sram_we_n <= not(iobus_wr and iobus_cs);
-- always pass through address
sram_addr <= iobus_addr(sram_addr'length-1 downto 0);
-- only set data when cs and wr, else Z
sram_dq <= std_logic_vector(iobus_din(sram_dq'length-1 downto 0)) when (iobus_cs = '1' and iobus_wr = '1') else (others => 'Z');
-- pass out data when cs = '1'
iobus_dout <= std_ulogic_vector(sram_dq(iobus_dout'length-1 downto 0)) when (iobus_cs = '1' and iobus_wr = '0') else
(others => '0');
end rtl;
| apache-2.0 | 0e3c82d56a6c761f3e8b7a7d510acd4c | 0.569181 | 2.783988 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_uart_test_ping_pong.vhdl | 1 | 6,469 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Jan Dürre
-- Year : 2013
-- Description : This example waits for an uart-command, which is
-- then saved and send back to the sender.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register
type state_t is (RECEIVED_LOOP, SEND_LOOP);
signal state, state_nxt : state_t;
-- register for received data
signal received_data, received_data_nxt : std_ulogic_vector(7 downto 0);
begin
-- sequential process
process (clock, reset)
begin
-- async reset
if reset = '1' then
state <= RECEIVED_LOOP;
received_data <= (others => '0');
elsif rising_edge(clock) then
state <= state_nxt;
received_data <= received_data_nxt;
end if;
end process;
-- logic
process (state, received_data, uart_irq_rx, uart_irq_tx, uart_din)
begin
-- standard assignments
-- hold values of registers
state_nxt <= state;
received_data_nxt <= received_data;
-- set bus signals to standard values (not in use)
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
-- turn of leds
led_green <= (others => '0');
led_red <= (others => '0');
-- state machine
case state is
-- wait for and save data
when RECEIVED_LOOP =>
led_green(0) <= '1';
-- data is ready in receive-register
if uart_irq_rx = '1' then
-- select uart-interface
uart_cs <= '1';
-- address of send/receive-register
uart_addr <= CV_ADDR_UART_DATA_RX;
-- write-mode
uart_wr <= '0';
-- save data
received_data_nxt <= uart_din(7 downto 0);
-- next state
state_nxt <= SEND_LOOP;
end if;
-- send back saved data
when SEND_LOOP =>
led_green(1) <= '1';
-- check if send-register is empty
if uart_irq_tx = '1' then
-- select uart-interface
uart_cs <= '1';
-- address of send/receive-register
uart_addr <= CV_ADDR_UART_DATA_TX;
-- write-mode
uart_wr <= '1';
-- select received data
uart_dout(7 downto 0) <= received_data;
-- next state
state_nxt <= RECEIVED_LOOP;
end if;
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
end rtl; | apache-2.0 | 7b6a3541896b7d375765534cc4d715b0 | 0.557514 | 2.74184 | false | false | false | false |
Fju/LeafySan | src/vhdl/interfaces/infrared.vhdl | 1 | 13,866 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Infra-red Receiver for NEC TX Format
-- Author : Jan Dürre
-- Last update : 12.08.2014
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity infrared is
generic (
SIMULATION : boolean := false
);
port (
-- global
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_IR-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
-- IRQ handling
iobus_irq_rx : out std_ulogic;
iobus_ack_rx : in std_ulogic;
-- connection to ir-receiver
irda_rxd : in std_ulogic
);
end infrared;
architecture rtl of infrared is
constant C_IR_CUSTOM_CODE : std_ulogic_vector(15 downto 0) := x"6B86";
--------------------------------------------
-- NEC Transmission Format: Remote Output --
--------------------------------------------
-- Start Sequence -> 16 Bit Custom Code -> 8 Bit Data -> 8 Bit NOT(Data)
--
-- Timinig:
-- Start Sequence: 9 ms HIGH -> 4.5 ms LOW
-- 0-Bit: 0.6 ms HIGH -> 0.52 ms LOW
-- 1-Bit: 0.6 ms HIGH -> 1.66 ms LOW
--
-- ATTENTION: Since the receiver inverts the incoming signal (irda_rxd is inverted to the remote output signal) the timings for LOW and HIGH parts are swapped in the following!
-- factor for min / max values of time measurement
constant TOLERANCE_FACTOR : real := 0.5;
-- startbit LOW time: 9.0 ms
constant CV_STARTBIT_LOW_SYN : natural := (CV_SYS_CLOCK_RATE / 1000000) * 9000;
constant CV_STARTBIT_LOW_MIN_SYN : natural := (CV_STARTBIT_LOW_SYN - natural(real(CV_STARTBIT_LOW_SYN) * TOLERANCE_FACTOR));
constant CV_STARTBIT_LOW_MAX_SYN : natural := (CV_STARTBIT_LOW_SYN + natural(real(CV_STARTBIT_LOW_SYN) * TOLERANCE_FACTOR));
constant CV_STARTBIT_LOW_SIM : natural := 90;
constant CV_STARTBIT_LOW_MIN_SIM : natural := (CV_STARTBIT_LOW_SIM - natural(real(CV_STARTBIT_LOW_SIM) * TOLERANCE_FACTOR));
constant CV_STARTBIT_LOW_MAX_SIM : natural := (CV_STARTBIT_LOW_SIM + natural(real(CV_STARTBIT_LOW_SIM) * TOLERANCE_FACTOR));
signal CV_STARTBIT_LOW_MIN : natural;
signal CV_STARTBIT_LOW_MAX : natural;
-- startbit HIGH time: 4.5 ms
constant CV_STARTBIT_HIGH_SYN : natural := (CV_SYS_CLOCK_RATE / 1000000) * 4500;
constant CV_STARTBIT_HIGH_MIN_SYN : natural := (CV_STARTBIT_HIGH_SYN - natural(real(CV_STARTBIT_HIGH_SYN) * TOLERANCE_FACTOR));
constant CV_STARTBIT_HIGH_MAX_SYN : natural := (CV_STARTBIT_HIGH_SYN + natural(real(CV_STARTBIT_HIGH_SYN) * TOLERANCE_FACTOR));
constant CV_STARTBIT_HIGH_SIM : natural := 45;
constant CV_STARTBIT_HIGH_MIN_SIM : natural := (CV_STARTBIT_HIGH_SIM - natural(real(CV_STARTBIT_HIGH_SIM) * TOLERANCE_FACTOR));
constant CV_STARTBIT_HIGH_MAX_SIM : natural := (CV_STARTBIT_HIGH_SIM + natural(real(CV_STARTBIT_HIGH_SIM) * TOLERANCE_FACTOR));
signal CV_STARTBIT_HIGH_MIN : natural;
signal CV_STARTBIT_HIGH_MAX : natural;
-- databit LOW time: 0.6 ms
constant CV_DATA_LOW_SYN : natural := (CV_SYS_CLOCK_RATE / 1000000) * 600;
constant CV_DATA_LOW_MIN_SYN : natural := (CV_DATA_LOW_SYN - natural(real(CV_DATA_LOW_SYN) * TOLERANCE_FACTOR));
constant CV_DATA_LOW_MAX_SYN : natural := (CV_DATA_LOW_SYN + natural(real(CV_DATA_LOW_SYN) * TOLERANCE_FACTOR));
constant CV_DATA_LOW_SIM : natural := 6;
constant CV_DATA_LOW_MIN_SIM : natural := (CV_DATA_LOW_SIM - natural(real(CV_DATA_LOW_SIM) * TOLERANCE_FACTOR));
constant CV_DATA_LOW_MAX_SIM : natural := (CV_DATA_LOW_SIM + natural(real(CV_DATA_LOW_SIM) * TOLERANCE_FACTOR));
signal CV_DATA_LOW_MIN : natural;
signal CV_DATA_LOW_MAX : natural;
-- databit '0' HIGH time: 0.52 ms
constant CV_DATA0_HIGH_SYN : natural := (CV_SYS_CLOCK_RATE / 1000000) * 520;
constant CV_DATA0_HIGH_MIN_SYN : natural := (CV_DATA0_HIGH_SYN - natural(real(CV_DATA0_HIGH_SYN) * TOLERANCE_FACTOR));
constant CV_DATA0_HIGH_MAX_SYN : natural := (CV_DATA0_HIGH_SYN + natural(real(CV_DATA0_HIGH_SYN) * TOLERANCE_FACTOR));
constant CV_DATA0_HIGH_SIM : natural := 5;
constant CV_DATA0_HIGH_MIN_SIM : natural := (CV_DATA0_HIGH_SIM - natural(real(CV_DATA0_HIGH_SIM) * TOLERANCE_FACTOR));
constant CV_DATA0_HIGH_MAX_SIM : natural := (CV_DATA0_HIGH_SIM + natural(real(CV_DATA0_HIGH_SIM) * TOLERANCE_FACTOR));
signal CV_DATA0_HIGH_MIN : natural;
signal CV_DATA0_HIGH_MAX : natural;
-- databit '1' HIGH time: 1.66 ms
constant CV_DATA1_HIGH_SYN : natural := (CV_SYS_CLOCK_RATE / 1000000) * 1660;
constant CV_DATA1_HIGH_MIN_SYN : natural := (CV_DATA1_HIGH_SYN - natural(real(CV_DATA1_HIGH_SYN) * TOLERANCE_FACTOR));
constant CV_DATA1_HIGH_MAX_SYN : natural := (CV_DATA1_HIGH_SYN + natural(real(CV_DATA1_HIGH_SYN) * TOLERANCE_FACTOR));
constant CV_DATA1_HIGH_SIM : natural := 16;
constant CV_DATA1_HIGH_MIN_SIM : natural := (CV_DATA1_HIGH_SIM - natural(real(CV_DATA1_HIGH_SIM) * TOLERANCE_FACTOR));
constant CV_DATA1_HIGH_MAX_SIM : natural := (CV_DATA1_HIGH_SIM + natural(real(CV_DATA1_HIGH_SIM) * TOLERANCE_FACTOR));
signal CV_DATA1_HIGH_MIN : natural;
signal CV_DATA1_HIGH_MAX : natural;
-- fsm
type state_t IS (S_IDLE, S_START_LOW, S_START_HIGH, S_DATA_LOW, S_DATA_HIGH, S_FINISH);
signal state, state_nxt : state_t;
-- counters
signal bit_cnt, bit_cnt_nxt : unsigned(to_log2(32)-1 downto 0);
signal time_cnt, time_cnt_nxt : unsigned(19 downto 0); -- max ~20 ms
-- control register
signal control_reg, control_reg_nxt : std_ulogic_vector(0 downto 0); -- 0: filter on custom code on/off
-- register for custom code
signal custom_code, custom_code_nxt : std_ulogic_vector(15 downto 0);
-- shift reg for incoming ir data
signal ir_data, ir_data_nxt : std_ulogic_vector(31 downto 0);
-- output data register
signal data_out_reg, data_out_reg_nxt : std_ulogic_vector(31 downto 0);
-- simple ff to stabilize ir-data signal
signal irda_rxd_dly, irda_rxd_dly_nxt : std_ulogic;
-- interrupt register
signal irq_rx, irq_rx_nxt : std_ulogic;
begin
-- select correct constant
CV_STARTBIT_LOW_MIN <= CV_STARTBIT_LOW_MIN_SYN when SIMULATION = false else CV_STARTBIT_LOW_MIN_SIM;
CV_STARTBIT_LOW_MAX <= CV_STARTBIT_LOW_MAX_SYN when SIMULATION = false else CV_STARTBIT_LOW_MAX_SIM;
CV_STARTBIT_HIGH_MIN <= CV_STARTBIT_HIGH_MIN_SYN when SIMULATION = false else CV_STARTBIT_HIGH_MIN_SIM;
CV_STARTBIT_HIGH_MAX <= CV_STARTBIT_HIGH_MAX_SYN when SIMULATION = false else CV_STARTBIT_HIGH_MAX_SIM;
CV_DATA_LOW_MIN <= CV_DATA_LOW_MIN_SYN when SIMULATION = false else CV_DATA_LOW_MIN_SIM;
CV_DATA_LOW_MAX <= CV_DATA_LOW_MAX_SYN when SIMULATION = false else CV_DATA_LOW_MAX_SIM;
CV_DATA0_HIGH_MIN <= CV_DATA0_HIGH_MIN_SYN when SIMULATION = false else CV_DATA0_HIGH_MIN_SIM;
CV_DATA0_HIGH_MAX <= CV_DATA0_HIGH_MAX_SYN when SIMULATION = false else CV_DATA0_HIGH_MAX_SIM;
CV_DATA1_HIGH_MIN <= CV_DATA1_HIGH_MIN_SYN when SIMULATION = false else CV_DATA1_HIGH_MIN_SIM;
CV_DATA1_HIGH_MAX <= CV_DATA1_HIGH_MAX_SYN when SIMULATION = false else CV_DATA1_HIGH_MAX_SIM;
-- ffs
process(reset_n, clock)
begin
if reset_n = '0' then
state <= S_IDLE;
bit_cnt <= (others => '0');
time_cnt <= (others => '0');
control_reg <= "1";
custom_code <= C_IR_CUSTOM_CODE;
ir_data <= (others => '0');
data_out_reg <= (others => '0');
irda_rxd_dly <= '0';
irq_rx <= '0';
elsif rising_edge(clock) then
state <= state_nxt;
bit_cnt <= bit_cnt_nxt;
time_cnt <= time_cnt_nxt;
control_reg <= control_reg_nxt;
custom_code <= custom_code_nxt;
ir_data <= ir_data_nxt;
data_out_reg <= data_out_reg_nxt;
irda_rxd_dly <= irda_rxd_dly_nxt;
irq_rx <= irq_rx_nxt;
end if;
end process;
-- connect ir-data signal to register
irda_rxd_dly_nxt <= irda_rxd;
-- connect irq-register to iobus
iobus_irq_rx <= irq_rx;
-- receive logic
process(state, bit_cnt, time_cnt, control_reg, custom_code, ir_data, data_out_reg, irda_rxd_dly, irda_rxd, irq_rx, iobus_ack_rx, CV_STARTBIT_LOW_MIN, CV_STARTBIT_LOW_MAX, CV_STARTBIT_HIGH_MIN, CV_STARTBIT_HIGH_MAX, CV_DATA_LOW_MIN, CV_DATA_LOW_MAX, CV_DATA0_HIGH_MIN, CV_DATA0_HIGH_MAX, CV_DATA1_HIGH_MIN, CV_DATA1_HIGH_MAX)
begin
-- hold registers
state_nxt <= state;
bit_cnt_nxt <= bit_cnt;
time_cnt_nxt <= time_cnt;
ir_data_nxt <= ir_data;
data_out_reg_nxt <= data_out_reg;
-- ack handling
if iobus_ack_rx = '1' then
irq_rx_nxt <= '0';
else
irq_rx_nxt <= irq_rx;
end if;
-- fsm
case state is
when S_IDLE =>
-- start of transmission
if irda_rxd_dly = '0' then
-- reset time counter
time_cnt_nxt <= (others => '0');
-- continue: next LOW of start bit
state_nxt <= S_START_LOW;
end if;
when S_START_LOW =>
-- measure LOW time
time_cnt_nxt <= time_cnt + 1;
-- on timeout
if time_cnt = unsigned(to_signed(-1, time_cnt'length)) then
state_nxt <= S_IDLE;
-- ir-data signals goes HIGH
elsif irda_rxd_dly = '1' then
-- time measurement not within limits
if ((time_cnt < CV_STARTBIT_LOW_MIN) or (time_cnt > CV_STARTBIT_LOW_MAX)) then
state_nxt <= S_IDLE;
else
-- reset counter
time_cnt_nxt <= (others => '0');
-- continue: next HIGH of start bit
state_nxt <= S_START_HIGH;
end if;
end if;
when S_START_HIGH =>
-- measure HIGH time
time_cnt_nxt <= time_cnt + 1;
-- on timeout
if time_cnt = unsigned(to_signed(-1, time_cnt'length)) then
state_nxt <= S_IDLE;
-- ir-data signals goes LOW
elsif irda_rxd_dly = '0' then
-- time measurement not within limits
if ((time_cnt < CV_STARTBIT_HIGH_MIN) or (time_cnt > CV_STARTBIT_HIGH_MAX)) then
state_nxt <= S_IDLE;
else
-- reset counters
time_cnt_nxt <= (others => '0');
bit_cnt_nxt <= (others => '0');
-- continue: next 16 data bits
state_nxt <= S_DATA_LOW;
end if;
end if;
when S_DATA_LOW =>
-- measure LOW time
time_cnt_nxt <= time_cnt + 1;
-- on timeout
if time_cnt = unsigned(to_signed(-1, time_cnt'length)) then
state_nxt <= S_IDLE;
-- ir-data signals goes HIGH
elsif irda_rxd_dly = '1' then
-- time measurement not within limits
if ((time_cnt < CV_DATA_LOW_MIN) or (time_cnt > CV_DATA_LOW_MAX)) then
state_nxt <= S_IDLE;
else
-- reset counter
time_cnt_nxt <= (others => '0');
-- continue: next HIGH of data bit
state_nxt <= S_DATA_HIGH;
end if;
end if;
when S_DATA_HIGH =>
-- measure HIGH time
time_cnt_nxt <= time_cnt + 1;
-- on timeout
if time_cnt = unsigned(to_signed(-1, time_cnt'length)) then
state_nxt <= S_IDLE;
-- ir-data signals goes LOW
elsif irda_rxd_dly = '0' then
-- time measurement in-between limits of '0' bit
if ((time_cnt > CV_DATA0_HIGH_MIN) and (time_cnt < CV_DATA0_HIGH_MAX)) then
-- shift in '0'
ir_data_nxt <= '0' & ir_data(31 downto 1);
-- reset counter
time_cnt_nxt <= (others => '0');
-- while more data bits expected
if bit_cnt < 31 then
-- increase bit counter
bit_cnt_nxt <= bit_cnt + 1;
-- continue: next LOW of data bit
state_nxt <= S_DATA_LOW;
else
-- stop recording data
state_nxt <= S_FINISH;
end if;
-- time measurement in-between limits of '1' bit
elsif ((time_cnt > CV_DATA1_HIGH_MIN) and (time_cnt < CV_DATA1_HIGH_MAX)) then
-- shift in '1'
ir_data_nxt <= '1' & ir_data(31 downto 1);
-- reset counter
time_cnt_nxt <= (others => '0');
-- while more data bits expected
if bit_cnt < 31 then
-- increase bit counter
bit_cnt_nxt <= bit_cnt + 1;
-- continue: next LOW of data bit
state_nxt <= S_DATA_LOW;
else
-- stop recording data
state_nxt <= S_FINISH;
end if;
-- time measurement not within any limits
else
state_nxt <= S_IDLE;
end if;
end if;
when S_FINISH =>
-- check custom code (if control_reg(0) = '1')
if ((ir_data(15 downto 0) = custom_code) or (control_reg(0) = '0')) then
-- check if data is valid
if ir_data(23 downto 16) = not(ir_data(31 downto 24)) then
-- set interrupt
irq_rx_nxt <= '1';
-- save received data in register
data_out_reg_nxt <= ir_data;
end if;
end if;
-- back to idle
state_nxt <= S_IDLE;
end case;
end process;
-- iobus interface
process(iobus_cs, iobus_wr, iobus_addr, iobus_din, data_out_reg, control_reg, custom_code)
begin
-- hold registers
control_reg_nxt <= control_reg;
custom_code_nxt <= custom_code;
iobus_dout <= (others => '0');
-- chip select
if iobus_cs = '1' then
-- read
if iobus_wr = '0' then
-- read received data
if iobus_addr = CV_ADDR_IR_DATA then
iobus_dout(7 downto 0) <= data_out_reg(23 downto 16);
end if;
end if;
end if;
end process;
end architecture rtl; | apache-2.0 | 427f2971e5ef506df68c3295bac8de1f | 0.599091 | 2.853674 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Controllori_Audio/Audio_Controller.vhd | 1 | 8,869 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Audio_Controller.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Modulo che legge e scrive i dati dal WM8731.
-- Utilizza il master mode e la giustificazione a sinistra.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Audio_Controller is
generic (
AUDIO_DATA_WIDTH: integer := 32;
BIT_COUNTER_INIT: std_logic_vector(4 downto 0) := "11111"
);
port (
clear_audio_out_memory: in std_logic;
reset: in std_logic;
clear_audio_in_memory: in std_logic;
read_audio_in: in std_logic;
clk: in std_logic;
left_channel_audio_out: in std_logic_vector(AUDIO_DATA_WIDTH downto 1);
right_channel_audio_out: in std_logic_vector(AUDIO_DATA_WIDTH downto 1);
write_audio_out: in std_logic;
AUD_ADCDAT: in std_logic;
AUD_BCLK: inout std_logic;
AUD_ADCLRCK: inout std_logic;
AUD_DACLRCK: inout std_logic;
I2C_SDAT: inout std_logic;
audio_in_available: buffer std_logic; --out std_logic;
left_channel_audio_in: out std_logic_vector(AUDIO_DATA_WIDTH downto 1);
right_channel_audio_in: out std_logic_vector(AUDIO_DATA_WIDTH downto 1);
audio_out_allowed: buffer std_logic; --out std_logic;
AUD_XCK: out std_logic;
AUD_DACDAT: out std_logic;
I2C_SCLK: out std_logic;
useMicInput: in std_logic
);
end Audio_Controller;
architecture behaviour of Audio_Controller is
component Clock_Edge is port (
clk: in std_logic;
reset: in std_logic;
test_clk: in std_logic;
ris_edge: out std_logic;
fal_edge: out std_logic
);
end component;
component Audio_In_Deserializer is
generic (
AUDIO_DATA_WIDTH: integer := 32;
BIT_COUNTER_INIT: std_logic_vector (4 downto 0) := "11111"
);
port (
clk: in std_logic;
reset: in std_logic;
bit_clk_rising_edge: in std_logic;
bit_clk_falling_edge: in std_logic;
left_right_clk_rising_edge: in std_logic;
left_right_clk_falling_edge: in std_logic;
done_channel_sync: in std_logic;
serial_audio_in_data: in std_logic;
read_left_audio_data_en: in std_logic;
read_right_audio_data_en: in std_logic;
left_audio_fifo_read_space: out std_logic_vector(7 downto 0);
right_audio_fifo_read_space: out std_logic_vector(7 downto 0);
left_channel_data: out std_logic_vector(AUDIO_DATA_WIDTH downto 1);
right_channel_data: out std_logic_vector(AUDIO_DATA_WIDTH downto 1)
);
end component;
component Audio_Out_Serializer is
generic (
AUDIO_DATA_WIDTH: integer := 32
);
port (
clk: in std_logic;
reset: in std_logic;
bit_clk_rising_edge: in std_logic;
bit_clk_falling_edge: in std_logic;
left_right_clk_rising_edge: in std_logic;
left_right_clk_falling_edge: in std_logic;
left_channel_data: in std_logic_vector(AUDIO_DATA_WIDTH downto 1);
left_channel_data_en: in std_logic;
right_channel_data: in std_logic_vector(AUDIO_DATA_WIDTH downto 1);
right_channel_data_en: in std_logic;
left_channel_fifo_write_space: out std_logic_vector(7 downto 0);
right_channel_fifo_write_space: out std_logic_vector(7 downto 0);
serial_audio_out_data: out std_logic
);
end component;
component AudioVideo_Config is port(
clk: in std_logic;
reset: in std_logic;
ob_address: in std_logic_vector(2 downto 0);
ob_byteenable: in std_logic_vector(3 downto 0);
ob_chipselect: in std_logic;
ob_read: in std_logic;
ob_write: in std_logic;
ob_writedata: in std_logic_vector(31 downto 0);
I2C_SDAT: inout std_logic;
ob_readdata: out std_logic_vector(31 downto 0);
ob_waitrequest: out std_logic;
I2C_SCLK: out std_logic;
useMicInput: in std_logic
);
end component;
signal bclk_rising_edge: std_logic;
signal bclk_falling_edge: std_logic;
signal adc_lrclk_rising_edge: std_logic;
signal adc_lrclk_falling_edge: std_logic;
signal dac_lrclk_rising_edge: std_logic;
signal dac_lrclk_falling_edge: std_logic;
signal left_channel_read_available: std_logic_vector(7 downto 0);
signal right_channel_read_available:std_logic_vector(7 downto 0);
signal left_channel_write_space: std_logic_vector(7 downto 0);
signal right_channel_write_space: std_logic_vector(7 downto 0);
signal done_adc_channel_sync: std_logic;
signal done_dac_channel_sync: std_logic;
begin
AUD_BCLK <= 'Z';
AUD_ADCLRCK <= 'Z';
AUD_DACLRCK <= 'Z';
process (clk)
begin
if reset = '1' then
audio_in_available <= '0';
elsif ((left_channel_read_available(7)='1' or left_channel_read_available(6)='1')
and (right_channel_read_available(7)='1' or right_channel_read_available(6)='1')) then
audio_in_available <= '1';
else
audio_in_available <= '0';
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
audio_out_allowed <= '0';
elsif ((left_channel_write_space(7)='1' or left_channel_write_space(6)='1')
and (right_channel_write_space(7)='1' or right_channel_write_space(6)='1')) then
audio_out_allowed <= '1';
else
audio_out_allowed <= '0';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
done_adc_channel_sync <= '0';
elsif (adc_lrclk_rising_edge = '1') then
done_adc_channel_sync <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
done_dac_channel_sync <= '0';
elsif (dac_lrclk_falling_edge = '1') then
done_dac_channel_sync <= '1';
end if;
end if;
end process;
Bit_Clock_Edges: Clock_Edge port map (
clk => clk,
reset => reset,
test_clk => AUD_BCLK,
ris_edge => bclk_rising_edge,
fal_edge => bclk_falling_edge
);
ADC_Left_Right_Clock_Edges: Clock_Edge port map (
clk => clk,
reset => reset,
test_clk => AUD_ADCLRCK,
ris_edge => adc_lrclk_rising_edge,
fal_edge => adc_lrclk_falling_edge
);
DAC_Left_Right_Clock_Edges: Clock_Edge port map (
clk => clk,
reset => reset,
test_clk => AUD_DACLRCK,
ris_edge => dac_lrclk_rising_edge,
fal_edge => dac_lrclk_falling_edge
);
Audio_In_Deserializer_Entity: Audio_In_Deserializer generic map (
AUDIO_DATA_WIDTH => AUDIO_DATA_WIDTH,
BIT_COUNTER_INIT => BIT_COUNTER_INIT
) port map (
clk => clk,
reset => reset or clear_audio_in_memory,
bit_clk_rising_edge => bclk_rising_edge,
bit_clk_falling_edge => bclk_falling_edge,
left_right_clk_rising_edge => adc_lrclk_rising_edge,
left_right_clk_falling_edge => adc_lrclk_falling_edge,
done_channel_sync => done_adc_channel_sync,
serial_audio_in_data => AUD_ADCDAT,
read_left_audio_data_en => read_audio_in and audio_in_available,
read_right_audio_data_en => read_audio_in and audio_in_available,
left_audio_fifo_read_space => left_channel_read_available,
right_audio_fifo_read_space => right_channel_read_available,
left_channel_data => left_channel_audio_in,
right_channel_data => right_channel_audio_in
);
Audio_Out_Serializer_Entity: Audio_Out_Serializer generic map (
AUDIO_DATA_WIDTH => AUDIO_DATA_WIDTH
) port map (
clk => clk,
reset => reset or clear_audio_out_memory,
bit_clk_rising_edge => bclk_rising_edge,
bit_clk_falling_edge => bclk_falling_edge,
left_right_clk_rising_edge => done_dac_channel_sync and dac_lrclk_rising_edge,
left_right_clk_falling_edge => done_dac_channel_sync and dac_lrclk_falling_edge,
left_channel_data => left_channel_audio_out,
left_channel_data_en => write_audio_out and audio_out_allowed,
right_channel_data => right_channel_audio_out,
right_channel_data_en => write_audio_out and audio_out_allowed,
left_channel_fifo_write_space => left_channel_write_space,
right_channel_fifo_write_space => right_channel_write_space,
serial_audio_out_data => AUD_DACDAT
);
AudioVideo_Config_Entity: AudioVideo_Config port map (
clk => clk,
reset => reset,
ob_address => "ZZZ",
ob_byteenable => "ZZZZ",
ob_chipselect => 'Z',
ob_read => 'Z',
ob_write => 'Z',
ob_writedata => "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ",
I2C_SDAT => I2C_SDAT,
ob_readdata => OPEN,
ob_waitrequest => OPEN,
I2C_SCLK => I2C_SCLK,
useMicInput => useMicInput
);
end behaviour; | mit | f4d6a60e0ba0e58f6b3476e7be2eafa5 | 0.630511 | 2.80487 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Controllori_Audio/Audio_Bit_Counter.vhd | 1 | 1,893 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Audio_Bit_Counter.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Modulo che conta i bit per il trasferimento seriale
-- del segnale audio.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Audio_Bit_Counter is
generic(
BIT_COUNTER_INIT: std_logic_vector(4 downto 0) := "11111"
);
port(
clk: in std_logic;
reset: in std_logic;
bit_clk_rising_edge: in std_logic;
bit_clk_falling_edge: in std_logic;
left_right_clk_rising_edge: in std_logic;
left_right_clk_falling_edge: in std_logic;
counting: out std_logic
);
end Audio_Bit_Counter;
architecture behaviour of Audio_Bit_Counter is
signal reset_bit_counter: std_logic;
signal bit_counter: std_logic_vector(4 downto 0);
begin
reset_bit_counter <= left_right_clk_rising_edge or left_right_clk_falling_edge;
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
bit_counter <= "00000";
elsif (reset_bit_counter = '1') then
bit_counter <= BIT_COUNTER_INIT;
elsif ((bit_clk_falling_edge = '1') and (bit_counter > "00000")) then
bit_counter <= bit_counter - "00001";
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
counting <= '0';
elsif (reset_bit_counter = '1') then
counting <= '1';
elsif ((bit_clk_falling_edge = '1') and (bit_counter = "00000")) then
counting <= '0';
end if;
end if;
end process;
end behaviour; | mit | cccc9ac90a94292824993a3ca74f629c | 0.545166 | 3.192243 | false | false | false | false |
Fju/LeafySan | src/modelsim/uart_testbench.vhd | 1 | 10,709 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.standard.all;
use std.textio.all;
use std.env.all;
library work;
use work.iac_pkg.all;
entity uart_testbench is
end uart_testbench;
architecture sim of uart_testbench is
constant SYSTEM_CYCLE_TIME : time := 20 ns; -- 50MHz
constant SIMULATION_TIME : time := 100000 * SYSTEM_CYCLE_TIME;
constant UART_WR_BYTE_COUNT : natural := 13;
constant UART_RD_BYTE_COUNT : natural := 9;
constant UART_DATA_WIDTH : natural := 6; -- 6-bits
signal clock, reset_n, reset : std_ulogic;
-- UART registers
signal uart_sent_bytes, uart_sent_bytes_nxt : unsigned(to_log2(UART_WR_BYTE_COUNT) - 1 downto 0);
signal uart_received_bytes, uart_received_bytes_nxt : unsigned(to_log2(UART_RD_BYTE_COUNT) - 1 downto 0);
type uart_protocol_entry_t is record
cmd : std_ulogic_vector(1 downto 0);
data : std_ulogic_vector(5 downto 0);
end record;
type uart_protocol_array is array (natural range <>) of uart_protocol_entry_t;
signal uart_wr_array, uart_wr_array_nxt : uart_protocol_array(0 to UART_WR_BYTE_COUNT - 1);
signal uart_rd_array, uart_rd_array_nxt : uart_protocol_array(0 to UART_RD_BYTE_COUNT);
type uart_state_t is (S_UART_RD_WAIT_START, S_UART_RD_READ_LOOP, S_UART_WR_START, S_UART_WR_WRITE_LOOP, S_UART_WR_END);
signal uart_state, uart_state_nxt : uart_state_t;
signal uart_cs : std_ulogic;
signal uart_wr : std_ulogic;
signal uart_addr : std_ulogic_vector(CW_ADDR_UART-1 downto 0);
signal uart_din : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal uart_dout : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal uart_irq_rx : std_ulogic;
signal uart_irq_tx : std_ulogic;
signal uart_ack_rx : std_ulogic;
signal uart_ack_tx : std_ulogic;
signal uart_rts, uart_cts, uart_rxd, uart_txd : std_ulogic;
signal end_simulation : std_ulogic;
signal heating_thresh, heating_thresh_nxt : unsigned(11 downto 0);
signal lighting_thresh, lighting_thresh_nxt : unsigned(15 downto 0);
signal watering_thresh, watering_thresh_nxt : unsigned(15 downto 0);
component uart is
generic (
SIMULATION : boolean := true
);
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_UART-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
-- IRQ handling
iobus_irq_rx : out std_ulogic;
iobus_irq_tx : out std_ulogic;
iobus_ack_rx : in std_ulogic;
iobus_ack_tx : in std_ulogic;
-- pins to outside
rts : in std_ulogic;
cts : out std_ulogic;
rxd : in std_ulogic;
txd : out std_ulogic
);
end component uart;
component uart_model is
generic (
SYSTEM_CYCLE_TIME : time;
FILE_NAME_COMMAND : string;
FILE_NAME_DUMP : string;
BAUD_RATE : natural;
SIMULATION : boolean
);
port (
end_simulation : in std_ulogic;
rx : in std_ulogic;
tx : out std_ulogic
);
end component uart_model;
begin
uart_inst : uart
generic map (
SIMULATION => true
)
port map (
-- global signals
clock => clock,
reset_n => reset_n,
-- bus interface
iobus_cs => uart_cs,
iobus_wr => uart_wr,
iobus_addr => uart_addr,
iobus_din => uart_dout, -- caution!
iobus_dout => uart_din, -- caution!
-- IRQ handling
iobus_irq_rx => uart_irq_rx,
iobus_irq_tx => uart_irq_tx,
iobus_ack_rx => uart_ack_rx,
iobus_ack_tx => uart_ack_tx,
-- pins to outside
rts => uart_rts,
cts => uart_cts,
rxd => uart_rxd,
txd => uart_txd
);
uart_model_inst : uart_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FILE_NAME_COMMAND => "uart_command.txt",
FILE_NAME_DUMP => "uart_dump.txt",
BAUD_RATE => CV_UART_BAUDRATE,
SIMULATION => true
)
port map (
end_simulation => end_simulation,
rx => uart_txd,
tx => uart_rxd
);
reset <= not(reset_n);
clk : process
begin
clock <= '1';
wait for SYSTEM_CYCLE_TIME/2;
clock <= '0';
wait for SYSTEM_CYCLE_TIME/2;
end process clk;
rst : process
begin
reset_n <= '0';
wait for 2*SYSTEM_CYCLE_TIME;
reset_n <= '1';
wait;
end process rst;
end_sim : process
begin
end_simulation <= '0';
wait for SIMULATION_TIME;
end_simulation <= '1';
wait;
end process end_sim;
seq : process(clock, reset)
begin
if reset = '1' then
uart_state <= S_UART_RD_WAIT_START;
uart_wr_array <= (others => (others => (others => '0')));
uart_rd_array <= (others => (others => (others => '0')));
uart_sent_bytes <= (others => '0');
uart_received_bytes <= (others => '0');
heating_thresh <= to_unsigned(240, heating_thresh'length); -- 24,0 °C
lighting_thresh <= to_unsigned(400, lighting_thresh'length); -- 400 lx
watering_thresh <= to_unsigned(500, watering_thresh'length); -- 50,0 %
elsif rising_edge(clock) then
uart_state <= uart_state_nxt;
uart_wr_array <= uart_wr_array_nxt;
uart_rd_array <= uart_rd_array_nxt;
uart_sent_bytes <= uart_sent_bytes_nxt;
uart_received_bytes <= uart_received_bytes_nxt;
heating_thresh <= heating_thresh_nxt;
lighting_thresh <= lighting_thresh_nxt;
watering_thresh <= watering_thresh_nxt;
end if;
end process seq;
comb : process(uart_state, uart_wr_array, uart_rd_array, uart_sent_bytes, uart_received_bytes, uart_irq_tx, uart_irq_rx, uart_din, lighting_thresh, watering_thresh, heating_thresh)
constant VALUE_COUNT : natural := 5; -- amount of data segments (four segments for each sensor + one segment including all states (on/off) of peripherals)
constant SEGMENT_COUNT : natural := 3; -- 3 bytes per "segment"
variable i, j : natural := 0; -- loop variables
variable segment_cmd : std_ulogic_vector(1 downto 0);
variable segment_data : unsigned(SEGMENT_COUNT * UART_DATA_WIDTH - 1 downto 0);
variable item : uart_protocol_entry_t;
variable segment_value : std_ulogic_vector(15 downto 0);
begin
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
-- hold values
uart_state_nxt <= uart_state;
uart_sent_bytes_nxt <= uart_sent_bytes;
uart_received_bytes_nxt <= uart_received_bytes;
uart_rd_array_nxt <= uart_rd_array;
lighting_thresh_nxt <= lighting_thresh;
watering_thresh_nxt <= watering_thresh;
heating_thresh_nxt <= heating_thresh;
-- assign sensor values to protocol
for i in 0 to VALUE_COUNT - 1 loop
if i = 0 then
segment_cmd := "10";
segment_data := to_unsigned(150, segment_data'length - 2) & "00"; -- replace with lux
elsif i = 1 then
segment_cmd := "11";
segment_data := to_unsigned(300, segment_data'length - 2) & "01"; -- replace with moisture
elsif i = 2 then
segment_cmd := "10";
segment_data := to_unsigned(271, segment_data'length - 2) & "10"; -- replace with temp
elsif i = 3 then
segment_cmd := "11";
segment_data := to_unsigned(3000, segment_data'length - 2) & "11"; -- replace with co2
else
segment_cmd := "10";
segment_data := (others => '0'); -- replace with peripherals
end if;
for j in 0 to SEGMENT_COUNT - 1 loop
if i < 4 or j = 0 then
uart_wr_array_nxt(j + i * SEGMENT_COUNT) <= (
segment_cmd, -- cmd
std_ulogic_vector(resize(shift_right(segment_data, (2 - j) * UART_DATA_WIDTH), UART_DATA_WIDTH)) -- data
);
end if;
end loop;
end loop;
case uart_state is
when S_UART_RD_WAIT_START =>
if uart_irq_rx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_RX;
uart_wr <= '0';
-- save data
if uart_din(7 downto 0) = "01000000" then
uart_received_bytes_nxt <= to_unsigned(0, uart_received_bytes'length);
uart_rd_array_nxt <= (others => (others => (others => '0')));
uart_state_nxt <= S_UART_RD_READ_LOOP;
end if;
end if;
when S_UART_RD_READ_LOOP =>
if uart_irq_rx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_RX;
uart_wr <= '0';
-- increment counter
if uart_din(7 downto 0) = "00111111" then
-- received end command
if uart_received_bytes = to_unsigned(UART_RD_BYTE_COUNT, uart_received_bytes'length) then
for i in 0 to 2 loop
if uart_rd_array(i*3).cmd = "10" or uart_rd_array(i*3).cmd = "11" then
segment_value := uart_rd_array(i*3).data & uart_rd_array(i*3+1).data & uart_rd_array(i*3+2).data(5 downto 2);
if uart_rd_array(i*3+2).data(1 downto 0) = "00" then
lighting_thresh_nxt <= unsigned(segment_value);
elsif uart_rd_array(i*3+2).data(1 downto 0) = "01" then
watering_thresh_nxt <= unsigned(segment_value);
elsif uart_rd_array(i*3+2).data(1 downto 0) = "10" then
heating_thresh_nxt <= resize(unsigned(segment_value), heating_thresh'length);
end if;
end if;
end loop;
end if;
uart_state_nxt <= S_UART_WR_START;
else
uart_rd_array_nxt(to_integer(uart_received_bytes)) <= (
uart_din(7 downto 6), -- cmd
uart_din(5 downto 0) -- data
);
uart_received_bytes_nxt <= uart_received_bytes + to_unsigned(1, uart_received_bytes'length);
end if;
end if;
when S_UART_WR_START =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
-- write `start` cmd
uart_dout(7 downto 0) <= "01000000";
--
uart_state_nxt <= S_UART_WR_WRITE_LOOP;
end if;
when S_UART_WR_WRITE_LOOP =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
item := uart_wr_array(to_integer(uart_sent_bytes));
uart_dout(7 downto 0) <= item.cmd & item.data;
if uart_sent_bytes = to_unsigned(UART_WR_BYTE_COUNT - 1, uart_sent_bytes'length) then
-- last byte sent
uart_sent_bytes_nxt <= (others => '0'); -- reset counter
uart_state_nxt <= S_UART_WR_END;
else
-- increment counter
uart_sent_bytes_nxt <= uart_sent_bytes + to_unsigned(1, uart_sent_bytes'length);
end if;
end if;
when S_UART_WR_END =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
-- write `end` cmd
uart_dout(7 downto 0) <= "00111111";
uart_state_nxt <= S_UART_RD_WAIT_START;
end if;
end case;
end process comb;
end sim; | apache-2.0 | f8bfe114383fa2f8fe3de75c52e50440 | 0.618078 | 2.722858 | false | false | false | false |
Fju/LeafySan | src/vhdl/modules/moisture_sensor.vhdl | 1 | 17,874 | ----------------------------------------------------------------------
-- Project : LeafySan
-- Module : Moisture Sensor Module
-- Authors : Florian Winkler
-- Lust update : 01.09.2017
-- Description : Reads a digital soil moisture sensor through an I2C bus
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity moisture_sensor is
generic (
CYCLE_TICKS : natural := 50000000
);
port(
clock : in std_ulogic;
reset : in std_ulogic;
-- i2c bus
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
moisture : out unsigned(15 downto 0);
temperature : out unsigned(15 downto 0);
address : out unsigned(6 downto 0);
enabled : in std_ulogic
);
end moisture_sensor;
architecture rtl of moisture_sensor is
component i2c_master is
generic (
GV_SYS_CLOCK_RATE : natural := 50000000;
GV_I2C_CLOCK_RATE : natural := 400000; -- fast mode: 400000 Hz (400 kHz)
GW_SLAVE_ADDR : natural := 7;
GV_MAX_BYTES : natural := 16;
GB_USE_INOUT : boolean := false; -- seperated io signals (ctrl, out, in)
GB_TIMEOUT : boolean := false
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
-- separated in / out
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
-- separated in / out
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
-- interface
busy : out std_ulogic;
cs : in std_ulogic;
mode : in std_ulogic_vector(1 downto 0); -- 00: only read; 01: only write; 10: first read, second write; 11: first write, second read
slave_addr : in std_ulogic_vector(GW_SLAVE_ADDR - 1 downto 0);
bytes_tx : in unsigned(to_log2(GV_MAX_BYTES + 1) - 1 downto 0);
bytes_rx : in unsigned(to_log2(GV_MAX_BYTES + 1) - 1 downto 0);
tx_data : in std_ulogic_vector(7 downto 0);
tx_data_valid : in std_ulogic;
rx_data_en : in std_ulogic;
rx_data : out std_ulogic_vector(7 downto 0);
rx_data_valid : out std_ulogic;
error : out std_ulogic
);
end component i2c_master;
type moist_state_t is (S_ADDR_SCAN, S_ADDR_REGISTER_BYTE0, S_ADDR_REGISTER_BYTE1, S_ADDR_REGISTER_SEND, S_ADDR_CHECK,
S_ADDR_RESET_BYTE0, S_ADDR_RESET_SEND, S_MST_BOOT_DELAY, S_MST_IDLE, S_MST_REGISTER_BYTE0, S_MST_REGISTER_SEND_BYTE0,
S_MST_READ_DELAY, S_MST_READ_START, S_MST_READ_WAIT, S_MST_READ_BYTES, S_MST_CHECK, S_TMP_REGISTER_BYTE0,
S_TMP_REGISTER_SEND_BYTE0, S_TMP_READ_DELAY, S_TMP_READ_START, S_TMP_READ_WAIT, S_TMP_READ_BYTES, S_TMP_CHECK);
signal moist_state, moist_state_nxt : moist_state_t;
constant MOIST_SLAVE_ADDR : std_ulogic_vector(6 downto 0) := "0100000"; -- 0x20 (default address)
constant SCAN_ADDR_START : unsigned(6 downto 0) := "0001000"; -- 0x08 (lowest available i2c address)
constant SCAN_ADDR_END : unsigned(6 downto 0) := "1110111"; -- 0x77 (highest available i2c address)
-- moisture register addresses
constant MOIST_REG_RESET : std_ulogic_vector(7 downto 0) := "00000110"; -- 0x06
constant MOIST_REG_SLEEP : std_ulogic_vector(7 downto 0) := "00001000"; -- 0x08
constant MOIST_REG_MOISTURE : std_ulogic_vector(7 downto 0) := "00000000"; -- 0x00
constant MOIST_REG_SET_ADDR : std_ulogic_vector(7 downto 0) := "00000001"; -- 0x01
constant MOIST_REG_TEMP : std_ulogic_vector(7 downto 0) := "00000101"; -- 0x05
constant MOIST_VALUES_WIDTH : natural := 2; -- 2 bytes
signal moist_received_cnt, moist_received_cnt_nxt : unsigned(to_log2(MOIST_VALUES_WIDTH + 1) - 1 downto 0);
signal moist_valid, moist_valid_nxt : std_ulogic;
type moist_vals_array is array (natural range <>) of std_ulogic_vector(7 downto 0);
signal moist_vals, moist_vals_nxt : moist_vals_array(0 to MOIST_VALUES_WIDTH - 1);
signal moist_busy : std_ulogic;
constant MOIST_BOOT_DELAY_TICKS : natural := 50000000; -- 1s
constant MOIST_READ_DELAY_TICKS : natural := 1000000; -- 20ms
signal moist_boot_delay_cnt, moist_boot_delay_cnt_nxt : unsigned(to_log2(MOIST_BOOT_DELAY_TICKS) - 1 downto 0);
signal moist_read_delay_cnt, moist_read_delay_cnt_nxt : unsigned(to_log2(MOIST_READ_DELAY_TICKS) - 1 downto 0);
signal scan_addr, scan_addr_nxt : unsigned(6 downto 0);
-- signals of `i2c_master` component
signal i2c_reset_n : std_ulogic;
signal i2c_busy : std_ulogic;
signal i2c_cs : std_ulogic;
signal i2c_mode : std_ulogic_vector(1 downto 0);
signal i2c_slave_addr : std_ulogic_vector(6 downto 0);
signal i2c_bytes_tx : unsigned(4 downto 0);
signal i2c_bytes_rx : unsigned(4 downto 0);
signal i2c_tx_data : std_ulogic_vector(7 downto 0);
signal i2c_tx_data_valid : std_ulogic;
signal i2c_rx_data_en : std_ulogic;
signal i2c_rx_data : std_ulogic_vector(7 downto 0);
signal i2c_rx_data_valid : std_ulogic;
signal i2c_error : std_ulogic;
-- output registers
signal moisture_reg, moisture_reg_nxt : unsigned(15 downto 0);
signal temp_reg, temp_reg_nxt : unsigned(15 downto 0);
-- cycle registers
signal cycle_cnt, cycle_cnt_nxt : unsigned(to_log2(CYCLE_TICKS) - 1 downto 0);
signal cycle_pulse : std_ulogic;
begin
-- configure `i2c_master` signal assignments
i2c_master_inst : i2c_master
generic map (
GV_SYS_CLOCK_RATE => CV_SYS_CLOCK_RATE,
GV_I2C_CLOCK_RATE => 400000, -- fast mode 400kHz
GW_SLAVE_ADDR => 7,
GV_MAX_BYTES => 16,
GB_USE_INOUT => false,
GB_TIMEOUT => false
)
port map (
clock => clock,
reset_n => i2c_reset_n,
i2c_clk_ctrl => i2c_clk_ctrl,
i2c_clk_in => i2c_clk_in,
i2c_clk_out => i2c_clk_out,
i2c_dat_ctrl => i2c_dat_ctrl,
i2c_dat_in => i2c_dat_in,
i2c_dat_out => i2c_dat_out,
busy => i2c_busy,
cs => i2c_cs,
mode => i2c_mode,
slave_addr => i2c_slave_addr,
bytes_tx => i2c_bytes_tx,
bytes_rx => i2c_bytes_rx,
tx_data => i2c_tx_data,
tx_data_valid => i2c_tx_data_valid,
rx_data => i2c_rx_data,
rx_data_valid => i2c_rx_data_valid,
rx_data_en => i2c_rx_data_en,
error => i2c_error
);
-- sequential process
process(clock, reset)
begin
-- "manually" connect i2c_reset_n with the inverse of the reset signal
i2c_reset_n <= not(reset);
if reset = '1' then
moist_state <= S_ADDR_SCAN;
moist_received_cnt <= (others => '0');
moist_valid <= '0';
moist_vals <= (others => (others => '0'));
moist_read_delay_cnt <= (others => '0');
moist_boot_delay_cnt <= (others => '0');
moisture_reg <= (others => '0');
temp_reg <= (others => '0');
cycle_cnt <= (others => '0');
scan_addr <= (others => '0');
elsif rising_edge(clock) then
moist_state <= moist_state_nxt;
moist_received_cnt <= moist_received_cnt_nxt;
moist_valid <= moist_valid_nxt;
moist_vals <= moist_vals_nxt;
moist_read_delay_cnt <= moist_read_delay_cnt_nxt;
moist_boot_delay_cnt <= moist_boot_delay_cnt_nxt;
moisture_reg <= moisture_reg_nxt;
temp_reg <= temp_reg_nxt;
cycle_cnt <= cycle_cnt_nxt;
scan_addr <= scan_addr_nxt;
end if;
end process;
-- generate cycle pulse every second
process(enabled, moist_busy, cycle_cnt)
begin
cycle_pulse <= '0';
cycle_cnt_nxt <= cycle_cnt;
if cycle_cnt = to_unsigned(CYCLE_TICKS - 1, cycle_cnt'length) then
-- reset clock only if sensor isn't busy anymore and main entity enabled the reading process (enabled = '1')
if enabled = '1' and moist_busy = '0' then
-- set pulse to HIGH when the sensor isn't busy anymore
cycle_pulse <= '1';
cycle_cnt_nxt <= (others => '0');
end if;
else
-- increment counter
cycle_cnt_nxt <= cycle_cnt + to_unsigned(1, cycle_cnt'length);
end if;
end process;
process(cycle_pulse, i2c_error, i2c_busy, i2c_rx_data, i2c_rx_data_valid, moist_state, moist_received_cnt, moist_busy, moist_valid, moist_vals, moist_read_delay_cnt, moist_boot_delay_cnt, moisture_reg, temp_reg, scan_addr)
-- variable is used to store the read value temporally
-- it allows us to compare the value to certain constants more easily
variable temp_value : unsigned(23 downto 0) := (others => '0');
begin
-- output values
moisture <= moisture_reg;
temperature <= temp_reg;
address <= scan_addr;
-- hold value by default
moist_state_nxt <= moist_state;
moist_received_cnt_nxt <= moist_received_cnt;
moist_valid_nxt <= moist_valid;
moist_vals_nxt <= moist_vals;
moist_read_delay_cnt_nxt <= moist_read_delay_cnt;
moist_boot_delay_cnt_nxt <= moist_boot_delay_cnt;
scan_addr_nxt <= scan_addr;
moisture_reg_nxt <= moisture_reg;
temp_reg_nxt <= temp_reg;
-- default assignments of `i2c_master` component
i2c_cs <= '0';
i2c_mode <= "00";
i2c_slave_addr <= MOIST_SLAVE_ADDR;
i2c_bytes_rx <= (others => '0');
i2c_bytes_tx <= (others => '0');
i2c_rx_data_en <= '0';
i2c_tx_data_valid <= '0';
i2c_tx_data <= (others => '0');
-- always busy by default
moist_busy <= '1';
case moist_state is
when S_ADDR_SCAN =>
-- wait for cycle pulse to start the scan process
moist_busy <= i2c_busy;
if cycle_pulse = '1' then
-- start with the lowest possible i2c address
scan_addr_nxt <= SCAN_ADDR_START;
moist_state_nxt <= S_ADDR_REGISTER_BYTE0;
end if;
when S_ADDR_REGISTER_BYTE0 =>
-- write "SET_ADDRESS" register address to tx fifo
i2c_tx_data <= MOIST_REG_SET_ADDR;
i2c_tx_data_valid <= '1';
moist_state_nxt <= S_ADDR_REGISTER_BYTE1;
when S_ADDR_REGISTER_BYTE1 =>
-- write new address (0x20) to tx fifo
i2c_tx_data <= "0" & MOIST_SLAVE_ADDR; -- add "0" because slave address has a bit width of 7 elements only
i2c_tx_data_valid <= '1';
moist_state_nxt <= S_ADDR_REGISTER_SEND;
when S_ADDR_REGISTER_SEND =>
if i2c_busy = '0' then
-- start transmission
i2c_cs <= '1';
i2c_mode <= "01"; -- write only
i2c_slave_addr <= std_ulogic_vector(scan_addr); -- write to current slave address
i2c_bytes_tx <= to_unsigned(2, i2c_bytes_tx'length); -- write two bytes
moist_state_nxt <= S_ADDR_CHECK;
end if;
when S_ADDR_CHECK =>
if i2c_busy = '0' then
if i2c_error = '0' then
-- no error occured because the slave acked, thus found correct address
moist_state_nxt <= S_ADDR_RESET_BYTE0;
else
-- slave didn't acked, thus found incorrect address
if scan_addr = SCAN_ADDR_END then
-- reached end of possible i2c addresses, restart with lowest address
moist_state_nxt <= S_ADDR_SCAN;
else
-- increment address value to try the next possible
scan_addr_nxt <= scan_addr + to_unsigned(1, scan_addr'length);
moist_state_nxt <= S_ADDR_REGISTER_BYTE0;
end if;
end if;
end if;
when S_ADDR_RESET_BYTE0 =>
-- write reset command to tx fifo
i2c_tx_data <= MOIST_REG_RESET;
i2c_tx_data_valid <= '1';
moist_state_nxt <= S_ADDR_RESET_SEND;
when S_ADDR_RESET_SEND =>
-- send reset command
if i2c_busy = '0' then
i2c_cs <= '1';
i2c_mode <= "01"; -- write only
i2c_slave_addr <= std_ulogic_vector(scan_addr);
i2c_bytes_tx <= to_unsigned(1, i2c_bytes_tx'length); -- write one byte
moist_state_nxt <= S_MST_BOOT_DELAY;
end if;
when S_MST_BOOT_DELAY =>
-- wait 1s to boot up moisture sensor
if moist_boot_delay_cnt = to_unsigned(MOIST_BOOT_DELAY_TICKS - 1, moist_boot_delay_cnt'length) then
moist_boot_delay_cnt_nxt <= (others => '0');
moist_state_nxt <= S_MST_IDLE;
else
moist_boot_delay_cnt_nxt <= moist_boot_delay_cnt + to_unsigned(1, moist_boot_delay_cnt'length);
end if;
when S_MST_IDLE =>
-- wait for cycle_pulse
moist_busy <= i2c_busy;
if cycle_pulse = '1' then
moist_state_nxt <= S_MST_REGISTER_BYTE0;
end if;
when S_MST_REGISTER_BYTE0 =>
-- write register address to tx fifo
i2c_tx_data <= MOIST_REG_MOISTURE;
i2c_tx_data_valid <= '1';
moist_state_nxt <= S_MST_REGISTER_SEND_BYTE0;
when S_MST_REGISTER_SEND_BYTE0 =>
if i2c_busy = '0' then
-- start transmission
i2c_cs <= '1';
i2c_mode <= "01"; -- write only
i2c_bytes_tx <= to_unsigned(1, i2c_bytes_tx'length); -- write one byte
moist_state_nxt <= S_MST_READ_DELAY;
end if;
when S_MST_READ_DELAY =>
-- wait 20ms as recommended
if moist_read_delay_cnt = to_unsigned(MOIST_READ_DELAY_TICKS - 1, moist_read_delay_cnt'length) then
moist_read_delay_cnt_nxt <= (others => '0');
moist_state_nxt <= S_MST_READ_START;
else
moist_read_delay_cnt_nxt <= moist_read_delay_cnt + to_unsigned(1, moist_read_delay_cnt'length);
end if;
when S_MST_READ_START =>
if i2c_busy = '0' then
-- start transmission
i2c_cs <= '1';
i2c_mode <= "00"; -- read only
i2c_bytes_rx <= to_unsigned(MOIST_VALUES_WIDTH, i2c_bytes_rx'length); -- read two bytes
moist_state_nxt <= S_MST_READ_WAIT;
end if;
when S_MST_READ_WAIT =>
-- wait for i2c_master to finish communication
if i2c_busy = '0' then
moist_state_nxt <= S_MST_READ_BYTES;
moist_valid_nxt <= '1'; -- valid by default
end if;
when S_MST_READ_BYTES =>
if i2c_rx_data_valid = '1' then
-- read two bytes from rx fifo
i2c_rx_data_en <= '1';
-- increment amount of received bytes
moist_received_cnt_nxt <= moist_received_cnt + to_unsigned(1, moist_received_cnt'length);
if moist_received_cnt < to_unsigned(MOIST_VALUES_WIDTH, moist_received_cnt'length) then
-- assign byte to vals register
moist_vals_nxt(to_integer(moist_received_cnt)) <= i2c_rx_data;
end if;
if i2c_error = '1' then
-- an error occured, data isn't valid anymore
moist_valid_nxt <= '0';
end if;
else
-- rx fifo empty
moist_state_nxt <= S_MST_CHECK;
end if;
when S_MST_CHECK =>
-- clean up for next cycle, independent from `data_valid`
moist_received_cnt_nxt <= (others => '0');
if moist_valid = '1' then
-- data is valid
temp_value := resize(unsigned(std_ulogic_vector'(moist_vals(0) & moist_vals(1))), temp_value'length); -- reverse byte order
-- check if received value is in a reasonable range
if temp_value < to_unsigned(400, temp_value'length) then
-- too low, clip to 0%
moisture_reg_nxt <= (others => '0');
elsif temp_value > to_unsigned(580, temp_value'length) then
-- too damn high, clip to 99.9%
moisture_reg_nxt <= to_unsigned(999, moisture_reg'length);
else
-- in bounds, update moisture register
moisture_reg_nxt <= resize(shift_right((temp_value - 400) * 45511, 13), moisture_reg'length);
end if;
end if;
moist_state_nxt <= S_TMP_REGISTER_BYTE0;
when S_TMP_REGISTER_BYTE0 =>
-- fill tx fifo with register address of temperature register
i2c_tx_data <= MOIST_REG_TEMP;
i2c_tx_data_valid <= '1';
moist_state_nxt <= S_TMP_REGISTER_SEND_BYTE0;
when S_TMP_REGISTER_SEND_BYTE0 =>
if i2c_busy = '0' then
i2c_cs <= '1';
i2c_mode <= "01"; -- write only
i2c_bytes_tx <= to_unsigned(1, i2c_bytes_tx'length); -- write one byte
moist_state_nxt <= S_TMP_READ_DELAY;
end if;
when S_TMP_READ_DELAY =>
-- wait 20ms as recommended
if moist_read_delay_cnt = to_unsigned(MOIST_READ_DELAY_TICKS - 1, moist_read_delay_cnt'length) then
moist_read_delay_cnt_nxt <= (others => '0');
moist_state_nxt <= S_TMP_READ_START;
else
moist_read_delay_cnt_nxt <= moist_read_delay_cnt + to_unsigned(1, moist_read_delay_cnt'length);
end if;
when S_TMP_READ_START =>
if i2c_busy = '0' then
i2c_cs <= '1';
i2c_mode <= "00"; -- read only
i2c_bytes_rx <= to_unsigned(MOIST_VALUES_WIDTH, i2c_bytes_rx'length); -- read two bytes
moist_state_nxt <= S_TMP_READ_WAIT;
end if;
when S_TMP_READ_WAIT =>
-- wait for i2c_master to finish communication
if i2c_busy = '0' then
moist_state_nxt <= S_TMP_READ_BYTES;
moist_valid_nxt <= '1'; -- valid by default
end if;
when S_TMP_READ_BYTES =>
-- read bytes that are in rx fifo
if i2c_rx_data_valid = '1' then
-- get one byte
i2c_rx_data_en <= '1';
-- increment amount of received bytes
moist_received_cnt_nxt <= moist_received_cnt + to_unsigned(1, moist_received_cnt'length);
if moist_received_cnt < to_unsigned(MOIST_VALUES_WIDTH, moist_received_cnt'length) then
-- assign byte to vals register
moist_vals_nxt(to_integer(moist_received_cnt)) <= i2c_rx_data;
end if;
if i2c_error = '1' then
-- an error occured, data isn't valid anymore
moist_valid_nxt <= '0';
end if;
else
-- rx fifo empty
moist_state_nxt <= S_TMP_CHECK;
end if;
when S_TMP_CHECK =>
-- clean up for next cycle, independent from `data_valid`
moist_received_cnt_nxt <= (others => '0');
if moist_valid = '1' then
-- data is valid
temp_value := resize(unsigned(std_ulogic_vector'(moist_vals(0) & moist_vals(1))), temp_value'length);
-- check if received value is in a reasonable range
if temp_value > to_unsigned(150, temp_value'length) and temp_value < to_unsigned(350, temp_value'length) then
-- update moisture register
temp_reg_nxt <= unsigned(std_ulogic_vector'(moist_vals(0) & moist_vals(1)));
end if;
end if;
-- go back to idle state
moist_state_nxt <= S_MST_IDLE;
end case;
end process;
end rtl;
| apache-2.0 | 83d819d50abbca62f64d10f5cd95c095 | 0.623811 | 2.63434 | false | false | false | false |
Fju/LeafySan | src/vhdl/utils/fifo.vhdl | 1 | 2,960 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Generic FIFO
-- Author : Jan Dürre
-- Last update : 28.11.2014
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity fifo is
generic (
DEPTH : natural := 64;
WORDWIDTH : natural := 8;
RAMTYPE : string := "auto" -- "auto", "logic", "MLAB", "M-RAM", "M512", "M4K", "M9K", "M144K", "M10K", "M20K" (the supported memory type depends on the target device, auto & logic will always work)
);
port (
-- global
clock : in std_ulogic;
reset_n : in std_ulogic;
-- data ports
write_en : in std_ulogic;
data_in : in std_ulogic_vector(WORDWIDTH-1 downto 0);
read_en : in std_ulogic;
data_out : out std_ulogic_vector(WORDWIDTH-1 downto 0);
-- status signals
empty : out std_ulogic;
full : out std_ulogic;
fill_cnt : out unsigned(to_log2(DEPTH+1)-1 downto 0)
);
end fifo;
architecture rtl of fifo is
type ram_t is array(0 to DEPTH-1) of std_logic_vector(WORDWIDTH-1 downto 0);
signal ram : ram_t;
attribute ramstyle : string;
attribute ramstyle of ram : signal is RAMTYPE;
signal write_ptr, read_ptr : unsigned(to_log2(DEPTH)-1 downto 0);
signal fill_cnt_local : unsigned(to_log2(DEPTH+1)-1 downto 0);
begin
data_out <= std_ulogic_vector(ram(to_integer(read_ptr)));
empty <= '1' when fill_cnt_local = 0 else
'0';
full <= '1' when fill_cnt_local = DEPTH else
'0';
fill_cnt <= fill_cnt_local;
-- ram
process(clock, reset_n)
begin
if reset_n = '0' then
ram <= (others => (others => 'U'));
elsif rising_edge(clock) then
if write_en = '1' then
ram(to_integer(write_ptr)) <= std_logic_vector(data_in);
end if;
end if;
end process;
-- pointers & counters
process(clock, reset_n)
begin
if reset_n = '0' then
write_ptr <= (others => '0');
read_ptr <= (others => '0');
fill_cnt_local <= (others => '0');
elsif rising_edge(clock) then
-- write pointer
if write_en = '1' then
if write_ptr < DEPTH-1 then
write_ptr <= write_ptr + 1;
else
write_ptr <= (others => '0');
end if;
end if;
-- read pointer
if read_en = '1' then
if read_ptr < DEPTH-1 then
read_ptr <= read_ptr + 1;
else
read_ptr <= (others => '0');
end if;
end if;
-- fill count
if (write_en = '1') and (read_en = '0') then
if fill_cnt_local < DEPTH then
fill_cnt_local <= fill_cnt_local + 1;
end if;
elsif (write_en = '0') and (read_en = '1') then
if fill_cnt_local > 0 then
fill_cnt_local <= fill_cnt_local - 1;
end if;
end if;
end if;
end process;
end rtl;
| apache-2.0 | c5dc6824552d8df077798a94196c2a99 | 0.539527 | 2.821735 | false | false | false | false |
Fju/LeafySan | src/vhdl/utils/pll.vhdl | 1 | 17,238 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.1.0 Build 186 12/03/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
locked <= sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 25,
clk1_duty_cycle => 50,
clk1_multiply_by => 6,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire1,
clk => sub_wire3,
locked => sub_wire6
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "6"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| apache-2.0 | bad846a64f8776f212b51bbc75e958f0 | 0.682446 | 3.270347 | false | false | false | false |
J-Rios/VHDL_Modules | 3.Peripherals/Debounced_Input/EDGE_bb.vhd | 1 | 2,039 | -- Listado del detector de flancos
--------------------------------------------------------
-- INSTANCE TEMPLATE
--------------------------------------------------------
--Edge_inst :entity work.edge_detect
-- port map (
-- c => MCLK,
-- level => , --in
-- tick => --out
-- );
library ieee;
use ieee.std_logic_1164.all;
entity edge_detect is
generic (N: NATURAL := 3 );
port(
c : in std_logic;
level : in std_logic;
tick : out std_logic
);
end edge_detect;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- NO MODIFICAR ---------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
architecture BlackBox of edge_detect is
signal Mshreg_sync_1_0 : STD_LOGIC;
signal N0 : STD_LOGIC;
signal sync : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
sync_0 : FD
port map (
C => c,
D => sync(1),
Q => sync(0)
);
tick1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sync(1),
I1 => sync(0),
O => tick
);
XST_GND : GND
port map (
G => N0
);
Mshreg_sync_1 : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => N0,
A1 => N0,
A2 => N0,
A3 => N0,
CLK => c,
D => level,
Q => Mshreg_sync_1_0
);
sync_1 : FD
port map (
C => c,
D => Mshreg_sync_1_0,
Q => sync(1)
);
end BlackBox;
| gpl-3.0 | 4a7ea9b7cd286b844dca0e29024d1801 | 0.297695 | 4.634091 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/nand/myNand2_tb.vhdl | 1 | 944 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myNand2_tb is
end myNand2_tb;
architecture Behavioral of myNand2_tb is
component myNand2
port(a : in std_logic; b : in std_logic; s : out std_logic);
end component;
signal a, b, s : std_logic;
begin
nand_0: myNand2 port map (a => a, b => b, s => s);
process
begin
a <= '0';
b <= '0';
wait for 1 ns;
assert s = '1' report "0 nand 0 != 1" severity error;
a <= '0';
b <= '1';
wait for 1 ns;
assert s = '1' report "0 nand 1 != 1" severity error;
a <= '1';
b <= '0';
wait for 1 ns;
assert s = '1' report "1 nand 0 != 1" severity error;
a <= '1';
b <= '1';
wait for 1 ns;
assert s = '0' report "1 nand 1 != 0" severity error;
assert false report "end of test" severity note;
wait;
end process;
end Behavioral;
| mit | ebc4c902cb0d31c1b7ae521e7c59543b | 0.507415 | 3.300699 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/xor/myXor2_tb.vhdl | 1 | 1,029 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myXor2_tb is
end myXor2_tb;
architecture behavorial of myXor2_tb is
component myXor2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
signal s1: std_logic;
signal s2: std_logic;
signal o1: std_logic;
begin
myXor2_1: myXor2 port map(a => s1, b => s2, s => o1);
process
begin
s1 <= '0';
s2 <= '0';
wait for 1 ns;
assert o1 = '0' report "0 xor 0 should be 0" severity error;
s1 <= '0';
s2 <= '1';
wait for 1 ns;
assert o1 = '1' report "0 xor 1 should be 1" severity error;
s1 <= '1';
s2 <= '0';
wait for 1 ns;
assert o1 = '1' report "1 xor 0 should be 1" severity error;
s1 <= '1';
s2 <= '1';
wait for 1 ns;
assert o1 = '0' report "1 xor 1 should be 0" severity error;
assert false report "Tests complete" severity note;
wait;
end process;
end behavorial;
| mit | 87a2e7c0dd488cd0cd9a8785d53a75b4 | 0.538387 | 3.195652 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue4/Audio/segment_out.vhd | 1 | 3,658 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:45:03 07/06/2016
-- Design Name:
-- Module Name: segment_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity segment_out is port (
clk : in STD_LOGIC;
ready : in STD_LOGIC;
reset : in STD_LOGIC;
scancode : in STD_LOGIC_VECTOR(7 downto 0);
segments : out STD_LOGIC_VECTOR(14 downto 0));
end segment_out;
architecture Behavioral of segment_out is
component seg_scancode_to_segments is port (
scancode : in STD_LOGIC_VECTOR(7 downto 0);
segment_repr : out STD_LOGIC_VECTOR(6 downto 0));
end component;
signal isE0, isF0, stw_q: STD_LOGIC;
signal segment_repr : STD_LOGIC_VECTOR(6 downto 0);
signal clock_divide_counter : Integer range 0 to 100000;
signal current_digit : Integer range 0 to 7;
signal digit0 : STD_LOGIC_VECTOR (6 downto 0);
signal digit1 : STD_LOGIC_VECTOR (6 downto 0);
signal digit2 : STD_LOGIC_VECTOR (6 downto 0);
signal digit3 : STD_LOGIC_VECTOR (6 downto 0);
signal digit4 : STD_LOGIC_VECTOR (6 downto 0);
signal digit5 : STD_LOGIC_VECTOR (6 downto 0);
signal digit6 : STD_LOGIC_VECTOR (6 downto 0);
signal digit7 : STD_LOGIC_VECTOR (6 downto 0);
begin
seg_scancode_to_segments0: seg_scancode_to_segments port map (scancode, segment_repr);
ef0_detector : process(scancode)
begin
if(scancode = "11100000") then
isE0 <= '1';
else
isE0 <= '0';
end if;
if(scancode = "11110000") then
isF0 <= '1';
else
isF0 <= '0';
end if;
end process ef0_detector;
stw : process (isE0, isF0, ready, clk)
begin
if clk'event and clk = '1' and ready = '1' then
if stw_q = '0' then
if isE0 = '0' AND isF0 = '0' then
digit7 <= digit6;
digit6 <= digit5;
digit5 <= digit4;
digit4 <= digit3;
digit3 <= digit2;
digit2 <= digit1;
digit1 <= digit0;
digit0 <= segment_repr;
elsif isE0 = '0' AND isF0 = '1' then
stw_q <= '1';
end if;
else
stw_q <= '0';
end if;
end if;
end process stw;
digit_select_clock_divider : process(clk)
begin
if clk'event and clk = '1' then
if clock_divide_counter >= 99999 then
clock_divide_counter <= 0;
current_digit <= current_digit + 1; -- overflows automatically with mod 8
else
clock_divide_counter <= clock_divide_counter + 1;
end if;
end if;
end process digit_select_clock_divider;
digit_time_multiplex : process (current_digit)
begin
if current_digit = 0 then
segments <= "11111110" & digit0;
elsif current_digit = 1 then
segments <= "11111101" & digit1;
elsif current_digit = 2 then
segments <= "11111011" & digit2;
elsif current_digit = 3 then
segments <= "11110111" & digit3;
elsif current_digit = 4 then
segments <= "11101111" & digit4;
elsif current_digit = 5 then
segments <= "11011111" & digit5;
elsif current_digit = 6 then
segments <= "10111111" & digit6;
else
segments <= "01111111" & digit7;
end if;
end process digit_time_multiplex;
end Behavioral;
| mit | 6afc3e3cb48bfafcb7f31586eef61b23 | 0.630672 | 3.137221 | false | false | false | false |
Fju/LeafySan | src/vhdl/utils/i2s_slave.vhdl | 1 | 13,867 | -------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : I2S Slave
-- Author : Jan Duerre
-- Last update : 21.08.2014
-- Description : This module implements a Slave-Receiver for the
-- Inter-IC Sound Bus.
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity i2s_slave is
port (
-- general signals
clock : in std_ulogic; -- system clock
reset_n : in std_ulogic; -- global reset
-- input signals from adc
aud_bclk : in std_ulogic; -- bitstream clock
aud_adc_lrck : in std_ulogic; -- adc left/~right clock
aud_adc_dat : in std_ulogic; -- adc serial audio data
-- output signals to dac
aud_dac_lrck : in std_ulogic; -- dac left/~right clock
aud_dac_dat : out std_ulogic; -- dac serial audio data
-- audio sample inputs
ain_left_sync : out std_ulogic;
ain_left_data : out std_ulogic;
ain_right_sync : out std_ulogic;
ain_right_data : out std_ulogic;
-- audio sample outputs
aout_left_sync : in std_ulogic;
aout_left_data : in std_ulogic;
aout_right_sync : in std_ulogic;
aout_right_data : in std_ulogic
);
end i2s_slave;
architecture rtl of i2s_slave is
-- shift regs for signal detection
signal aud_bclk_sreg : std_ulogic_vector(2 downto 0);
signal aud_bclk_sreg_nxt : std_ulogic_vector(2 downto 0);
signal aud_adc_lrck_sreg : std_ulogic_vector(1 downto 0);
signal aud_adc_lrck_sreg_nxt : std_ulogic_vector(1 downto 0);
signal aud_dac_lrck_sreg : std_ulogic_vector(1 downto 0);
signal aud_dac_lrck_sreg_nxt : std_ulogic_vector(1 downto 0);
signal aud_adc_dat_reg : std_ulogic;
signal aud_adc_dat_reg_nxt : std_ulogic;
-- data registers
signal audio_data_in_lr : std_ulogic;
signal audio_data_in_lr_nxt : std_ulogic;
signal ain_lr : std_ulogic;
signal ain_lr_nxt : std_ulogic;
signal audio_data_in_left : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_in_left_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_in_right : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_in_right_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_in_sreg : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_in_sreg_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_out_lr : std_ulogic;
signal audio_data_out_lr_nxt : std_ulogic;
signal aout_lr : std_ulogic;
signal aout_lr_nxt : std_ulogic;
signal audio_data_out_left : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_out_left_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_out_right : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_out_right_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_out_sreg : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_data_out_sreg_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
-- bit counter
signal audio_data_in_cnt_left : unsigned(to_log2(CW_AUDIO_SAMPLE+2)-1 downto 0);
signal audio_data_in_cnt_left_nxt : unsigned(to_log2(CW_AUDIO_SAMPLE+2)-1 downto 0);
signal audio_data_in_cnt_right : unsigned(to_log2(CW_AUDIO_SAMPLE+2)-1 downto 0);
signal audio_data_in_cnt_right_nxt : unsigned(to_log2(CW_AUDIO_SAMPLE+2)-1 downto 0);
signal audio_data_out_cnt : unsigned(to_log2(CW_AUDIO_SAMPLE+2)-1 downto 0);
signal audio_data_out_cnt_nxt : unsigned(to_log2(CW_AUDIO_SAMPLE+2)-1 downto 0);
signal ain_cnt : unsigned(to_log2(CW_AUDIO_SAMPLE+1)-1 downto 0);
signal ain_cnt_nxt : unsigned(to_log2(CW_AUDIO_SAMPLE+1)-1 downto 0);
signal aout_cnt : unsigned(to_log2(CW_AUDIO_SAMPLE+1)-1 downto 0);
signal aout_cnt_nxt : unsigned(to_log2(CW_AUDIO_SAMPLE+1)-1 downto 0);
-- FSM adc (audio in)
type fsm_ain_t is (S_WAIT_FOR_EDGE_LR, S_WAIT_1BCLK_RISE, S_WAIT_1BCLK_FALL);
signal state_ain, state_ain_nxt : fsm_ain_t;
-- FSM dac (audio out)
type fsm_aout_t is (S_WAIT_FOR_EDGE_LR, S_WAIT_1BCLK_RISE, S_WAIT_1BCLK_FALL);
signal state_aout, state_aout_nxt : fsm_aout_t;
begin
-- FFs
process(clock, reset_n)
begin
if reset_n = '0' then
aud_bclk_sreg <= (others => '0');
aud_adc_lrck_sreg <= (others => '1');
aud_dac_lrck_sreg <= (others => '1');
aud_adc_dat_reg <= '0';
audio_data_in_lr <= '0';
audio_data_in_left <= (others => '0');
audio_data_in_right <= (others => '0');
audio_data_in_sreg <= (others => '0');
audio_data_out_lr <= '0';
audio_data_out_left <= (others => '0');
audio_data_out_right <= (others => '0');
audio_data_out_sreg <= (others => '0');
audio_data_in_cnt_left <= to_unsigned(CW_AUDIO_SAMPLE+1, audio_data_in_cnt_left'length);
audio_data_in_cnt_right <= to_unsigned(CW_AUDIO_SAMPLE+1, audio_data_in_cnt_right'length);
audio_data_out_cnt <= to_unsigned(CW_AUDIO_SAMPLE+1, audio_data_out_cnt'length);
ain_cnt <= to_unsigned(CW_AUDIO_SAMPLE, ain_cnt'length);
aout_cnt <= (others => '0');
ain_lr <= '0';
aout_lr <= '0';
state_ain <= S_WAIT_FOR_EDGE_LR;
state_aout <= S_WAIT_FOR_EDGE_LR;
elsif rising_edge(clock) then
aud_bclk_sreg <= aud_bclk_sreg_nxt;
aud_adc_lrck_sreg <= aud_adc_lrck_sreg_nxt;
aud_dac_lrck_sreg <= aud_dac_lrck_sreg_nxt;
aud_adc_dat_reg <= aud_adc_dat_reg_nxt;
audio_data_in_lr <= audio_data_in_lr_nxt;
audio_data_in_left <= audio_data_in_left_nxt;
audio_data_in_right <= audio_data_in_right_nxt;
audio_data_in_sreg <= audio_data_in_sreg_nxt;
audio_data_out_lr <= audio_data_out_lr_nxt;
audio_data_out_left <= audio_data_out_left_nxt;
audio_data_out_right <= audio_data_out_right_nxt;
audio_data_out_sreg <= audio_data_out_sreg_nxt;
audio_data_in_cnt_left <= audio_data_in_cnt_left_nxt;
audio_data_in_cnt_right <= audio_data_in_cnt_right_nxt;
audio_data_out_cnt <= audio_data_out_cnt_nxt;
ain_cnt <= ain_cnt_nxt;
aout_cnt <= aout_cnt_nxt;
ain_lr <= ain_lr_nxt;
aout_lr <= aout_lr_nxt;
state_ain <= state_ain_nxt;
state_aout <= state_aout_nxt;
end if;
end process;
-- shift regs for edge detection
aud_bclk_sreg_nxt <= aud_bclk & aud_bclk_sreg(2 downto 1);
aud_adc_lrck_sreg_nxt <= aud_adc_lrck & aud_adc_lrck_sreg(1);
aud_dac_lrck_sreg_nxt <= aud_dac_lrck & aud_dac_lrck_sreg(1);
-- connect adc data in to register, to have access to past data
aud_adc_dat_reg_nxt <= aud_adc_dat;
-- FSM Audio In
process (state_ain, audio_data_in_lr, audio_data_in_left, audio_data_in_right, audio_data_in_cnt_left, audio_data_in_cnt_right, ain_cnt, ain_lr, aud_adc_lrck, aud_adc_lrck_sreg, aud_bclk_sreg, aud_adc_dat, audio_data_in_sreg, aud_adc_dat_reg)
begin
state_ain_nxt <= state_ain;
audio_data_in_lr_nxt <= audio_data_in_lr;
audio_data_in_left_nxt <= audio_data_in_left;
audio_data_in_right_nxt <= audio_data_in_right;
audio_data_in_sreg_nxt <= audio_data_in_sreg;
audio_data_in_cnt_left_nxt <= audio_data_in_cnt_left;
audio_data_in_cnt_right_nxt <= audio_data_in_cnt_right;
ain_cnt_nxt <= ain_cnt;
ain_lr_nxt <= ain_lr;
ain_left_sync <= '0';
ain_left_data <= '0';
ain_right_sync <= '0';
ain_right_data <= '0';
-- serialization
if ain_cnt /= CW_AUDIO_SAMPLE then
-- sync signal
if ain_cnt = 0 then
-- left / right
if ain_lr = '0' then
ain_left_sync <= '1';
else
ain_right_sync <= '1';
end if;
end if;
-- serial data signal
if ain_lr = '0' then
-- left
ain_left_data <= audio_data_in_sreg(CW_AUDIO_SAMPLE-1);
else
-- right
ain_right_data <= audio_data_in_sreg(CW_AUDIO_SAMPLE-1);
end if;
-- shift data
audio_data_in_sreg_nxt <= audio_data_in_sreg(CW_AUDIO_SAMPLE-2 downto 0) & '0';
-- count
ain_cnt_nxt <= ain_cnt + 1;
end if;
-- i2s rx
-- rising edge on bclk: shift in data
if aud_bclk_sreg(2 downto 1) = "10" then
-- left
if audio_data_in_lr = '0' then
audio_data_in_left_nxt <= audio_data_in_left(CW_AUDIO_SAMPLE-2 downto 0) & aud_adc_dat_reg;
-- right
else
audio_data_in_right_nxt <= audio_data_in_right(CW_AUDIO_SAMPLE-2 downto 0) & aud_adc_dat_reg;
end if;
end if;
-- rising edge on bclk: count data
if aud_bclk_sreg(2 downto 1) = "10" then
-- left
if audio_data_in_lr = '0' then
if audio_data_in_cnt_left <= CW_AUDIO_SAMPLE then
audio_data_in_cnt_left_nxt <= audio_data_in_cnt_left + 1;
end if;
else
-- right
if audio_data_in_cnt_right <= CW_AUDIO_SAMPLE then
audio_data_in_cnt_right_nxt <= audio_data_in_cnt_right + 1;
end if;
end if;
end if;
-- finished rx : start serialization
if audio_data_in_cnt_left = CW_AUDIO_SAMPLE then
ain_cnt_nxt <= (others => '0');
ain_lr_nxt <= audio_data_in_lr;
audio_data_in_sreg_nxt <= audio_data_in_left;
audio_data_in_cnt_left_nxt <= audio_data_in_cnt_left + 1;
end if;
if audio_data_in_cnt_right = CW_AUDIO_SAMPLE then
ain_cnt_nxt <= (others => '0');
ain_lr_nxt <= audio_data_in_lr;
audio_data_in_sreg_nxt <= audio_data_in_right;
audio_data_in_cnt_right_nxt <= audio_data_in_cnt_right + 1;
end if;
-- mini-fsm to control flow
case state_ain is
when S_WAIT_FOR_EDGE_LR =>
-- on falling or rising edge on lrc
if aud_adc_lrck_sreg = "01" or aud_adc_lrck_sreg = "10" then
-- await first cycle
state_ain_nxt <= S_WAIT_1BCLK_RISE;
end if;
when S_WAIT_1BCLK_RISE =>
-- rising edge on bclk
if aud_bclk_sreg(2 downto 1) = "10" then
-- await first cycle
state_ain_nxt <= S_WAIT_1BCLK_FALL;
end if;
when S_WAIT_1BCLK_FALL =>
-- falling edge on bclk
if aud_bclk_sreg(2 downto 1) = "01" then
-- start recording data
if aud_adc_lrck = '0' then
audio_data_in_cnt_left_nxt <= (others => '0');
else
audio_data_in_cnt_right_nxt <= (others => '0');
end if;
-- save channel
audio_data_in_lr_nxt <= aud_adc_lrck;
-- wait for next edge
state_ain_nxt <= S_WAIT_FOR_EDGE_LR;
end if;
end case;
end process;
-- FSM Audio Out
process (state_aout, aout_cnt, aout_lr, aout_left_sync, aout_left_data, aout_right_sync, aout_right_data, audio_data_out_left, audio_data_out_right, audio_data_out_sreg, audio_data_out_lr, audio_data_out_cnt, aud_dac_lrck, aud_dac_lrck_sreg, aud_bclk_sreg)
begin
state_aout_nxt <= state_aout;
audio_data_out_lr_nxt <= audio_data_out_lr;
audio_data_out_left_nxt <= audio_data_out_left;
audio_data_out_right_nxt <= audio_data_out_right;
audio_data_out_sreg_nxt <= audio_data_out_sreg;
audio_data_out_cnt_nxt <= audio_data_out_cnt;
aout_cnt_nxt <= aout_cnt;
aout_lr_nxt <= aout_lr;
aud_dac_dat <= '0';
-- parallelization
if aout_left_sync = '1' then
audio_data_out_left_nxt <= audio_data_out_left(CW_AUDIO_SAMPLE-2 downto 0) & aout_left_data;
aout_lr_nxt <= '0';
elsif aout_right_sync = '1' then
audio_data_out_right_nxt <= audio_data_out_right(CW_AUDIO_SAMPLE-2 downto 0) & aout_right_data;
aout_lr_nxt <= '1';
end if;
if aout_left_sync = '1' or aout_right_sync = '1' then
aout_cnt_nxt <= (others => '0');
end if;
if aout_cnt /= CW_AUDIO_SAMPLE - 1 then
-- left / right
if aout_lr = '0' then
audio_data_out_left_nxt <= audio_data_out_left(CW_AUDIO_SAMPLE-2 downto 0) & aout_left_data;
else
audio_data_out_right_nxt <= audio_data_out_right(CW_AUDIO_SAMPLE-2 downto 0) & aout_right_data;
end if;
-- count
aout_cnt_nxt <= aout_cnt + 1;
end if;
-- i2s tx
aud_dac_dat <= audio_data_out_sreg(CW_AUDIO_SAMPLE-1);
if audio_data_out_cnt <= CW_AUDIO_SAMPLE then
-- rising edge on delayed bclk: shift
if aud_bclk_sreg(1 downto 0) = "10" then
-- left
if audio_data_out_lr = '0' then
audio_data_out_sreg_nxt <= audio_data_out_sreg(CW_AUDIO_SAMPLE-2 downto 0) & '0';
-- right
else
audio_data_out_sreg_nxt <= audio_data_out_sreg(CW_AUDIO_SAMPLE-2 downto 0) & '0';
end if;
end if;
-- rising edge on bclk: count
if aud_bclk_sreg(2 downto 1) = "10" then
-- count
audio_data_out_cnt_nxt <= audio_data_out_cnt + 1;
end if;
end if;
-- mini-fsm to control flow
case state_aout is
when S_WAIT_FOR_EDGE_LR =>
-- on rising or falling edge on lrc
if aud_dac_lrck_sreg = "10" or aud_dac_lrck_sreg = "01" then
state_aout_nxt <= S_WAIT_1BCLK_RISE;
end if;
when S_WAIT_1BCLK_RISE =>
-- rising edge on bclk
if aud_bclk_sreg(2 downto 1) = "10" then
state_aout_nxt <= S_WAIT_1BCLK_FALL;
if aud_dac_lrck = '0' then
audio_data_out_sreg_nxt <= audio_data_out_left;
else
audio_data_out_sreg_nxt <= audio_data_out_right;
end if;
end if;
when S_WAIT_1BCLK_FALL =>
-- falling edge on bclk
if aud_bclk_sreg(2 downto 1) = "01" then
audio_data_out_lr_nxt <= aud_dac_lrck;
state_aout_nxt <= S_WAIT_FOR_EDGE_LR;
audio_data_out_cnt_nxt <= (others => '0');
end if;
end case;
end process;
end architecture rtl; | apache-2.0 | 768ca627ffb06e968563f7793c9bf43d | 0.6015 | 2.656005 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Controllori_Audio/Audio_Out_Serializer.vhd | 1 | 5,801 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Audio_Out_Serializer.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Scrittura dati provenienti dalla SDRAM sul bus dell'DAC.
-- Questi dati verranno convertiti in segnale analogico
-- dal DAC del chip WM8731.
-- **********************************************************
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity Audio_Out_Serializer is
generic (
AUDIO_DATA_WIDTH: integer := 32
);
port (
clk: in std_logic;
reset: in std_logic;
bit_clk_rising_edge: in std_logic;
bit_clk_falling_edge: in std_logic;
left_right_clk_rising_edge: in std_logic;
left_right_clk_falling_edge: in std_logic;
left_channel_data: in std_logic_vector(AUDIO_DATA_WIDTH downto 1);
left_channel_data_en: in std_logic;
right_channel_data: in std_logic_vector(AUDIO_DATA_WIDTH downto 1);
right_channel_data_en: in std_logic;
left_channel_fifo_write_space: out std_logic_vector(7 downto 0);
right_channel_fifo_write_space: out std_logic_vector(7 downto 0);
serial_audio_out_data: out std_logic
);
end Audio_Out_Serializer;
architecture behaviour of Audio_Out_Serializer is
component SYNC_FIFO is
generic (
DATA_WIDTH: integer := 32;
DATA_DEPTH: integer := 128;
ADDR_WIDTH: integer := 7
);
port (
clk: in std_logic;
reset: in std_logic;
write_en: in std_logic;
write_data: in std_logic_vector(DATA_WIDTH downto 1);
read_en: in std_logic;
fifo_is_empty: out std_logic;
fifo_is_full: out std_logic;
words_used: out std_logic_vector(ADDR_WIDTH downto 1);
read_data: out std_logic_vector(DATA_WIDTH downto 1)
);
end component;
signal read_left_channel: std_logic;
signal read_right_channel: std_logic;
signal left_channel_fifo_is_empty: std_logic;
signal right_channel_fifo_is_empty: std_logic;
signal left_channel_fifo_is_full: std_logic;
signal right_channel_fifo_is_full: std_logic;
signal left_channel_fifo_used: std_logic_vector(6 downto 0);
signal right_channel_fifo_used: std_logic_vector(6 downto 0);
signal left_channel_from_fifo: std_logic_vector(AUDIO_DATA_WIDTH downto 1);
signal right_channel_from_fifo: std_logic_vector(AUDIO_DATA_WIDTH downto 1);
signal left_channel_was_read: std_logic;
signal data_out_shift_reg: std_logic_vector(AUDIO_DATA_WIDTH downto 1);
begin
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
left_channel_fifo_write_space <= "00000000";
else
left_channel_fifo_write_space <= "10000000" - (left_channel_fifo_is_full & left_channel_fifo_used);
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
right_channel_fifo_write_space <= "00000000";
else
right_channel_fifo_write_space <= "10000000" - (right_channel_fifo_is_full & right_channel_fifo_used);
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
serial_audio_out_data <= '0';
else
serial_audio_out_data <= data_out_shift_reg(AUDIO_DATA_WIDTH);
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
left_channel_was_read <= '0';
elsif (read_left_channel='1') then
left_channel_was_read <= '1';
elsif (read_right_channel='1') then
left_channel_was_read <= '0';
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
data_out_shift_reg <= "00000000000000000000000000000000"; -- {AUDIO_DATA_WIDTH{1'b0}};
elsif (read_left_channel='1') then
data_out_shift_reg <= left_channel_from_fifo;
elsif (read_right_channel='1') then
data_out_shift_reg <= right_channel_from_fifo;
elsif (left_right_clk_rising_edge='1' or left_right_clk_falling_edge='1') then
data_out_shift_reg <= "00000000000000000000000000000000"; -- {AUDIO_DATA_WIDTH{1'b0}};
elsif (bit_clk_falling_edge='1') then
data_out_shift_reg <= data_out_shift_reg((AUDIO_DATA_WIDTH - 1) downto 1) & '0';
end if;
end if;
end process;
read_left_channel <= left_right_clk_rising_edge and not(left_channel_fifo_is_empty) and not(right_channel_fifo_is_empty);
read_right_channel <= left_right_clk_falling_edge and left_channel_was_read;
Audio_Out_Left_Channel_FIFO: SYNC_FIFO generic map (
DATA_WIDTH => AUDIO_DATA_WIDTH,
DATA_DEPTH => 128,
ADDR_WIDTH => 7
)
port map (
clk => clk,
reset => reset,
write_en => left_channel_data_en and not(left_channel_fifo_is_full),
write_data => left_channel_data,
read_en => read_left_channel,
fifo_is_empty => left_channel_fifo_is_empty,
fifo_is_full => left_channel_fifo_is_full,
words_used => left_channel_fifo_used,
read_data => left_channel_from_fifo
);
Audio_Out_Right_Channel_FIFO: SYNC_FIFO generic map (
DATA_WIDTH => AUDIO_DATA_WIDTH,
DATA_DEPTH => 128,
ADDR_WIDTH => 7
)
port map (
clk => clk,
reset => reset,
write_en => right_channel_data_en and not (right_channel_fifo_is_full),
write_data => right_channel_data,
read_en => read_right_channel,
fifo_is_empty => right_channel_fifo_is_empty,
fifo_is_full => right_channel_fifo_is_full,
words_used => right_channel_fifo_used,
read_data => right_channel_from_fifo
);
end behaviour; | mit | 65640b60858f74399310e677538d45ec | 0.623858 | 2.876054 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Controllori_Audio/Audio_In_Deserializer.vhd | 1 | 5,591 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Audio_In_Deserializer.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Lettura dati dall'ADC. I dati vengono ricevuti in seriale
-- e deserializzati, cioe' raggruppati in blocchi da 32 bit.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Audio_In_Deserializer is
generic (
AUDIO_DATA_WIDTH: integer := 32;
BIT_COUNTER_INIT: std_logic_vector (4 downto 0) := "11111"
);
port (
clk: in std_logic;
reset: in std_logic;
bit_clk_rising_edge: in std_logic;
bit_clk_falling_edge: in std_logic;
left_right_clk_rising_edge: in std_logic;
left_right_clk_falling_edge: in std_logic;
done_channel_sync: in std_logic;
serial_audio_in_data: in std_logic;
read_left_audio_data_en: in std_logic;
read_right_audio_data_en: in std_logic;
left_audio_fifo_read_space: out std_logic_vector(7 downto 0);
right_audio_fifo_read_space: out std_logic_vector(7 downto 0);
left_channel_data: out std_logic_vector(AUDIO_DATA_WIDTH downto 1);
right_channel_data: out std_logic_vector(AUDIO_DATA_WIDTH downto 1)
);
end Audio_In_Deserializer;
architecture behaviour of Audio_In_Deserializer is
component Audio_Bit_Counter is
generic(
BIT_COUNTER_INIT: std_logic_vector(4 downto 0) := "11111"
);
port(
clk: in std_logic;
reset: in std_logic;
bit_clk_rising_edge: in std_logic;
bit_clk_falling_edge: in std_logic;
left_right_clk_rising_edge: in std_logic;
left_right_clk_falling_edge: in std_logic;
counting: out std_logic
);
end component;
component SYNC_FIFO is
generic (
DATA_WIDTH: integer := 32;
DATA_DEPTH: integer := 128;
ADDR_WIDTH: integer := 7
);
port (
clk: in std_logic;
reset: in std_logic;
write_en: in std_logic;
write_data: in std_logic_vector(DATA_WIDTH downto 1);
read_en: in std_logic;
fifo_is_empty: out std_logic;
fifo_is_full: out std_logic;
words_used: out std_logic_vector(ADDR_WIDTH downto 1);
read_data: out std_logic_vector(DATA_WIDTH downto 1)
);
end component;
signal valid_audio_input: std_logic;
signal left_channel_fifo_is_empty: std_logic;
signal right_channel_fifo_is_empty: std_logic;
signal left_channel_fifo_is_full: std_logic;
signal right_channel_fifo_is_full: std_logic;
signal left_channel_fifo_used: std_logic_vector(6 downto 0);
signal right_channel_fifo_used: std_logic_vector(6 downto 0);
signal data_in_shift_reg: std_logic_vector(AUDIO_DATA_WIDTH downto 1);
begin
process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
left_audio_fifo_read_space <= "00000000";
else
left_audio_fifo_read_space(7) <= left_channel_fifo_is_full;
left_audio_fifo_read_space(6 downto 0) <= left_channel_fifo_used;
end if;
end if;
end process;
process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
right_audio_fifo_read_space <= "00000000";
else
right_audio_fifo_read_space(7) <= right_channel_fifo_is_full;
right_audio_fifo_read_space(6 downto 0) <= right_channel_fifo_used;
end if;
end if;
end process;
process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
data_in_shift_reg <= "00000000000000000000000000000000";
elsif (bit_clk_rising_edge='1' and valid_audio_input='1') then
data_in_shift_reg <= data_in_shift_reg((AUDIO_DATA_WIDTH - 1) downto 1) & serial_audio_in_data;
end if;
end if;
end process;
Audio_Out_Bit_Counter: Audio_Bit_Counter generic map (
BIT_COUNTER_INIT => BIT_COUNTER_INIT
)
port map(
clk => clk,
reset => reset,
bit_clk_rising_edge => bit_clk_rising_edge,
bit_clk_falling_edge => bit_clk_falling_edge,
left_right_clk_rising_edge => left_right_clk_rising_edge,
left_right_clk_falling_edge => left_right_clk_falling_edge,
counting => valid_audio_input
);
Audio_In_Left_Channel_FIFO: SYNC_FIFO generic map(
DATA_WIDTH => AUDIO_DATA_WIDTH,
DATA_DEPTH => 128,
ADDR_WIDTH => 7
)
port map (
clk => clk,
reset => reset,
write_en => left_right_clk_falling_edge and not left_channel_fifo_is_full and done_channel_sync,
write_data => data_in_shift_reg,
read_en => read_left_audio_data_en and not left_channel_fifo_is_empty,
fifo_is_empty => left_channel_fifo_is_empty,
fifo_is_full => left_channel_fifo_is_full,
words_used => left_channel_fifo_used,
read_data => left_channel_data
);
Audio_In_Right_Channel_FIFO: SYNC_FIFO generic map(
DATA_WIDTH => AUDIO_DATA_WIDTH,
DATA_DEPTH => 128,
ADDR_WIDTH => 7
)
port map (
clk => clk,
reset => reset,
write_en => left_right_clk_rising_edge and not right_channel_fifo_is_full and done_channel_sync,
write_data => data_in_shift_reg,
read_en => read_right_audio_data_en and not right_channel_fifo_is_empty,
fifo_is_empty => right_channel_fifo_is_empty,
fifo_is_full => right_channel_fifo_is_full,
words_used => right_channel_fifo_used,
read_data => right_channel_data
);
end behaviour; | mit | 89d96b2f10734a9839e43623828f7208 | 0.6176 | 2.838071 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue4/Audio/audio_scancode_to_divisor.vhd | 1 | 1,582 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:51:13 07/09/2016
-- Design Name:
-- Module Name: audio_scancode_to_divisor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity audio_scancode_to_divisor is port (
scancode : in STD_LOGIC_VECTOR(7 downto 0);
clock_divisor : out INTEGER);
end audio_scancode_to_divisor;
architecture Behavioral of audio_scancode_to_divisor is
begin
process(scancode)
begin
case scancode is
when "00100011" => clock_divisor <= 3367000; -- 297 Hz (d')
when "00100100" => clock_divisor <= 30303000; -- 330 Hz (e')
when "00101011" => clock_divisor <= 284091000; -- 352 Hz (f')
when "00110100" => clock_divisor <= 25252; -- 396 Hz (g')
when "00011100" => clock_divisor <= 22727; -- 440 Hz (a')
when "00110011" => clock_divisor <= 2020; -- 495 Hz (h')
when others => clock_divisor <= 378788; -- 264 Hz (c');
end case;
end process;
end Behavioral;
| mit | 45f001085fa2b1a9831e85dc2204e2f4 | 0.606827 | 3.662037 | false | false | false | false |
Hyvok/KittLights | sim/kitt_lights/kitt_lights_tb.vhd | 1 | 743 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity kitt_lights_tb is
end entity;
architecture rtl of kitt_lights_tb is
-- Main clock frequency 50 MHz
constant CLK_PERIOD : time := 1 sec / 50e6;
signal clk : std_logic := '0';
signal reset : std_logic;
begin
reset <= '1', '0' after 500 ns;
clk <= not clk after CLK_PERIOD / 2;
DUT_inst: entity work.kitt_lights(rtl)
generic map
(
LIGHTS_N => 8,
ADVANCE_VAL => 100000,
PWM_BITS_N => 8,
DECAY_VAL => 2000
)
port map
(
clk => clk,
reset => reset
);
end;
| mit | cbbc2bd733e35b4bd24118b76d3c8b40 | 0.497981 | 3.555024 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue4/video/seg_scancode_to_segments.vhd | 2 | 2,046 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:08:31 07/07/2016
-- Design Name:
-- Module Name: seg_scancode_to_segments - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity seg_scancode_to_segments is port (
scancode : in STD_LOGIC_VECTOR(7 downto 0);
segment_repr : out STD_LOGIC_VECTOR(6 downto 0));
end seg_scancode_to_segments;
architecture Behavioral of seg_scancode_to_segments is
begin
process(scancode)
begin
case scancode is
when "00010110" => segment_repr <= "1001111"; --1
when "00011110" => segment_repr <= "0010010"; --2
when "00100110" => segment_repr <= "0000110"; --3
when "00100101" => segment_repr <= "1001100"; --4
when "00101110" => segment_repr <= "0100100"; --5
when "00110110" => segment_repr <= "0100000"; --6
when "00111101" => segment_repr <= "0001111"; --7
when "00111110" => segment_repr <= "0000000"; --8
when "01000110" => segment_repr <= "0000100"; --9
when "01000101" => segment_repr <= "0000001"; --0
when "00011100" => segment_repr <= "0001000"; --A
when "00110010" => segment_repr <= "1100000"; --b
when "00100001" => segment_repr <= "0110001"; --c
when "00100011" => segment_repr <= "1000010"; --d
when "00100100" => segment_repr <= "0110000"; --E
when "00101011" => segment_repr <= "0111000"; --F
when others => segment_repr <= "1000001"; --u;
end case;
end process;
end Behavioral;
| mit | 9200f21243ca338a25fc3675661348ee | 0.599218 | 3.515464 | false | false | false | false |
J-Rios/VHDL_Modules | 2.Secuencial/UniversalShiftRegister.vhd | 1 | 1,216 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity USHIFTREG is
Generic
(
BITS : INTEGER := 4
);
Port
(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CTRL : in STD_LOGIC_VECTOR (1 downto 0);
D : in STD_LOGIC_VECTOR (BITS-1 downto 0);
Q : out STD_LOGIC_VECTOR (BITS-1 downto 0)
);
end USHIFTREG;
-------------------------------------------------------------------------
architecture Behavioral of USHIFTREG is
signal r_reg : std_logic_vector (BITS-1 downto 0);
signal r_next : std_logic_vector (BITS-1 downto 0);
begin
-- State register
process(RST, CLK)
begin
if (RST = '1') then
r_reg <= (others => '0');
elsif (CLK'event and CLK = '1') then
r_reg <= r_next;
end if;
end process;
-- Next state logic
with CTRL select r_next <=
r_reg when "00", -- Do nothing
r_reg(BITS-2 downto 0) & D(0) when "01", -- Shift-Left
D(BITS-1) & r_reg(BITS-1 downto 1) when "10", -- Shift-Right
D when others; -- Load
-- Output logic
Q <= r_reg;
end Behavioral;
| gpl-3.0 | 9227f8ffaffb17c676c23f99ad59ff3e | 0.491776 | 3.435028 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue1/Hasardsimulation/mux2to1.vhd | 1 | 1,524 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:11 05/18/2016
-- Design Name:
-- Module Name: mux2to1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux2to1 is
--Port ( x1 : in STD_LOGIC;
-- x2 : in STD_LOGIC;
-- x3 : in STD_LOGIC;
-- y : out STD_LOGIC);
end mux2to1;
architecture Behavioral of mux2to1 is
signal x1, x2, x3, y : STD_LOGIC;
signal x3v, x2v, x1v : STD_LOGIC;
signal b, c,e,d : STD_LOGIC;
begin
x1 <= '1', '0' after 30ns;
x2 <= '0', '1' after 30ns;
x3 <= '1', '0' after 30ns;
x3v <= transport(x3) after 0 ns;
x2v <= transport(x2) after 3 ns;
x1v <= transport(x1) after 6 ns;
b <= transport(not x2v) after 5ns;
c <= transport(x2v and x1v)after 10 ns;
e <= transport(x3v and x1v) after 10 ns;
d <= transport(x3v and b) after 10 ns;
y <= transport(c or e or d) after 10 ns;
end Behavioral;
| mit | 638e58e38513a1c3e9710b7da1c75d2e | 0.572835 | 3.10387 | false | false | false | false |
maly/fpmi | FPGA/rom.vhd | 1 | 6,115 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: rom.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY rom IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END rom;
ARCHITECTURE SYN OF rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
ram_block_type : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../PMI.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
ram_block_type => "M4K",
widthad_a => 10,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../PMI.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../PMI.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit | ff9f9d20c0df313093d30f558aeca3c9 | 0.665413 | 3.546984 | false | false | false | false |
J-Rios/VHDL_Modules | 1.Combinational/F_Adder_BCD.vhd | 1 | 1,810 | ----------------------------------------------------------------------------------
-- ------------------- --
-- | | --
-- A[BITS-1:0] ---------| A | --
-- | Z |--------- Z[BITS-1:0] --
-- B[BITS-1:0] ---------| B | --
-- | | --
-- CI ---------| CI CO |--------- CO --
-- | | --
-- ------------------- --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
----------------------------------------------------------------------------------
entity F_Adder_BCD is
generic
(
BITS : INTEGER := 4
);
Port
(
CI : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (BITS-1 downto 0);
B : in STD_LOGIC_VECTOR (BITS-1 downto 0);
Z : out STD_LOGIC_VECTOR (BITS-1 downto 0);
CO : out STD_LOGIC
);
end F_Adder_BCD;
----------------------------------------------------------------------------------
architecture Behavioral of F_Adder_BCD is
signal A_unsig , B_unsig : UNSIGNED (BITS downto 0);
signal Sum : UNSIGNED (BITS downto 0);
begin
A_unsig <= unsigned('0' & A);
B_unsig <= unsigned('0' & B);
Sum <= A_unsig + B_unsig + ('0' & CI);
Z <= std_logic_vector(Sum(BITS-1 downto 0));
CO <= Sum(BITS);
end Behavioral;
| gpl-3.0 | 8360915845e3ee8990974e08509ea5fe | 0.252486 | 5.08427 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sources_1/otile.vhd | 1 | 24,682 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity otile is
port (
clk : in std_logic;
rst : in std_logic;
data : in std_logic_vector(15 downto 0);
addr : in std_logic_vector(9 downto 0);
wen : in std_logic;
OLED_VDD : out std_logic;
OLED_BAT : out std_logic;
OLED_RST : out std_logic;
OLED_CS : out std_logic;
OLED_SCK : out std_logic;
OLED_MOSI : out std_logic;
OLED_CD : out std_logic ) ;
end otile;
architecture Behavioral of otile is
type states is ( ST_STARTUP, ST_DISPON, ST_DISPWAIT, ST_READY, ST_WAIT, ST_BAT_OFF, ST_OFF, ST_SHUTDOWN, ST_PWR_ON, ST_BAT_ON );
signal state, state_new : states;
-- Internal replica of power signals, inverted before outputting
signal VDD_int, VDD_new : std_logic;
signal VBAT_int, VBAT_new : std_logic;
signal nRESET_int, nRESET_new : std_logic;
signal timer0, timer0_new : unsigned(23 downto 0);
-- SPI transciever signals
signal spistrobe, spistrobe_new : std_logic;
signal spibusy : std_logic;
constant spibitwidth : integer := 8;
signal spidata, spidata_new : std_logic_vector(spibitwidth-1 downto 0);
constant spidivby : integer := 100; -- 1 MHz SPI Clock
constant spidivbits : integer := 7; -- to count to 100
-- Data/!Command flag
signal spicd, spicd_new : std_logic;
constant startup_len : integer := 8;
type startup_arr is array (startup_len-1 downto 0) of std_logic_vector(spibitwidth-1 downto 0);
constant startup_cmds : startup_arr := (
x"8D", x"14", -- Enable Charge Pump
x"A6", -- Noninverted display
x"AF", -- Display On
x"A4", -- Use RAM contents
x"20", x"00", -- Use horizontal addressing mode
x"A1" ); -- Reverse direction of columns
-- Up to 16 commands, FIXME
signal cmdcounter, cmdcounter_new : unsigned(3 downto 0);
-- 8 rows of 128 columns -> 10 bit counter
signal pointer, pointer_new : unsigned(9 downto 0);
signal pixcol, pixcol_new : unsigned(2 downto 0);
signal tilecol, tilecol_new : unsigned(4 downto 0);
signal tilerow, tilerow_new : unsigned(2 downto 0);
constant tilewidth : integer := 6; -- Width of tile in pixels
constant tilecount : integer := 21; -- Tiles per row
constant tileslack : integer := 2; -- Extra pixel columns after last tile
constant tileheight : integer := 8; -- Rows per screen
signal DOA, DOB, DIB, DOA2, DOB2, DIB2 : std_logic_vector(31 downto 0);
signal DIPB : std_logic_vector(3 downto 0);
signal ADDRA, ADDRB, ADDRA2, ADDRB2 : std_logic_vector(13 downto 0);
signal WEB2 : std_logic_vector(3 downto 0);
begin
transciever : entity work.spicomm
generic map (
divby => spidivby,
divbits => spidivbits,
bitwidth => spibitwidth )
port map (
clk => clk,
rst => rst,
data => spidata,
strobe => spistrobe,
busy => spibusy,
sck => OLED_SCK,
sdi => '0', -- One-way communication
sdo => OLED_MOSI );
-- Signals drive a PFET, so are inverted
OLED_VDD <= not VDD_int;
OLED_BAT <= not VBAT_int;
OLED_RST <= nRESET_int;
OLED_CS <= not spibusy;
OLED_CD <= spicd;
comb : process(state, VDD_int, VBAT_int, nRESET_int, timer0, spibusy, spidata, spicd, pointer, cmdcounter, pixcol, tilecol, tilerow, DOA, DOA2)
-- reset delay, VDD to VBAT, 3 us
constant delay1 : unsigned := to_unsigned(300, timer0'length);
-- Startup and shutdown delay, 100 ms (FIXME should be 100 ms)
constant delay2 : unsigned := to_unsigned(10000000, timer0'length);
-- 1 us
constant delay3 : unsigned := to_unsigned(100, timer0'length);
variable state_next : states;
variable VDD_next, VBAT_next, nRESET_next : std_logic;
variable timer0_next : unsigned(timer0'range);
variable spistrobe_next : std_logic;
variable spidata_next : std_logic_vector(spidata'range);
variable spicd_next : std_logic;
variable pointer_next : unsigned(pointer'range);
variable cmdcounter_next : unsigned(cmdcounter'range);
variable pixcol_next : unsigned(pixcol'range);
variable tilecol_next : unsigned(tilecol'range);
variable tilerow_next : unsigned(tilerow'range);
variable pixdata : std_logic_vector(3 downto 0);
begin
state_next := state;
VDD_next := VDD_int;
VBAT_next := VBAT_int;
nRESET_next := nRESET_int;
if timer0 > "0" then
timer0_next := timer0 - "1";
else
timer0_next := (others => '0');
end if;
spistrobe_next := '0';
spidata_next := spidata;
spicd_next := spicd;
cmdcounter_next := cmdcounter;
pointer_next := pointer;
pixcol_next := pixcol;
tilecol_next := tilecol;
tilerow_next := tilerow;
case state is
-- While off, hold the module in reset
when ST_OFF =>
VDD_next := '0';
VBAT_next := '0';
nRESET_next := '1';
state_next := ST_STARTUP;
-- Turn on the main power, delay, and then turn on battery power
when ST_STARTUP =>
VDD_next := '1';
timer0_next := delay1;
state_next := ST_PWR_ON;
when ST_PWR_ON =>
nRESET_next := '0';
-- When the 300 us timer expires...
if timer0 = to_unsigned(0, timer0'length) then
timer0_next := delay2;
state_next := ST_BAT_ON;
end if;
when ST_BAT_ON =>
nRESET_next := '1';
VBAT_next := '1';
cmdcounter_next := to_unsigned(startup_len, cmdcounter'length);
-- When the 100 ms timer expires...
if timer0 = to_unsigned(0, timer0'length) then
state_next := ST_DISPON;
end if;
-- Send a display on command
when ST_DISPON =>
spidata_next := startup_cmds(to_integer(cmdcounter) - 1);
spistrobe_next := '1';
spicd_next := '0'; -- Sending commands
if spibusy = '1' then
cmdcounter_next := cmdcounter - "1";
state_next := ST_DISPWAIT;
end if;
when ST_DISPWAIT =>
-- spidata_next := (others => 'Z');
pointer_next := (others => '0');
pixcol_next := (others => '0');
tilecol_next := (others => '0');
tilerow_next := (others => '0');
if spibusy = '0' then
if timer0_next = "0" then
if cmdcounter = "0" then
state_next := ST_READY;
else
state_next := ST_DISPON;
end if;
end if;
else
timer0_next := delay3;
end if;
-- Display is ready for use
when ST_READY =>
if DOA2(15) = '1' then
pixdata := not DOA(3 downto 0);
else
pixdata := DOA(3 downto 0);
end if;
spidata_next := '0' & pixdata(3) & '0' & pixdata(2) & '0' & pixdata(1) & '0' & pixdata(0);
spistrobe_next := '1';
spicd_next := '1'; -- Sending data to the OLED, not a command
-- Update our position counters
if spibusy = '1' then
if tilecol = to_unsigned(tilecount, tilecol'length) then -- If we are past the final tile, in the slack
if pixcol = to_unsigned(tileslack - 1, pixcol'length) then
pixcol_next := (others => '0');
tilecol_next := (others => '0');
-- FIXME the following can be simplified under certain conditions
if tilerow = to_unsigned(tileheight - 1, tilerow'length) then
tilerow_next := (others => '0');
else
tilerow_next := tilerow + "1";
end if;
else
pixcol_next := pixcol + "1";
end if;
elsif pixcol = to_unsigned(tilewidth - 1, pixcol'length) then
pixcol_next := (others => '0');
tilecol_next := tilecol + "1";
else
pixcol_next := pixcol + "1";
end if;
-- For backwards-compatibility's sake
pointer_next := pointer + "1";
state_next := ST_WAIT;
end if;
when ST_WAIT =>
-- spidata_next := (others => 'Z');
if spibusy = '0' then
if timer0_next = "0" then
state_next := ST_READY;
end if;
else
timer0_next := delay3;
end if;
-- Turn off battery power, wait, then turn off main power
when ST_SHUTDOWN =>
-- Should be preceeded by command 0xAE, display off
VBAT_next := '0';
timer0_next := delay2;
state_next := ST_BAT_OFF;
when ST_BAT_OFF =>
if timer0 = to_unsigned(0, timer0'length) then
state_next := ST_OFF;
end if;
when others =>
end case;
state_new <= state_next;
VDD_new <= VDD_next;
VBAT_new <= VBAT_next;
nRESET_new <= nRESET_next;
timer0_new <= timer0_next;
spistrobe_new <= spistrobe_next;
spidata_new <= spidata_next;
spicd_new <= spicd_next;
cmdcounter_new <= cmdcounter_next;
pointer_new <= pointer_next;
pixcol_new <= pixcol_next;
tilecol_new <= tilecol_next;
tilerow_new <= tilerow_next;
end process;
-- A few signals require asynchronous reset
async : process(clk, rst)
begin
-- Async reset, to ensure power is off
if rst = '1' then
VDD_int <= '0';
VBAT_int <= '0';
elsif rising_edge(clk) then
VDD_int <= VDD_new;
VBAT_int <= VBAT_new;
end if;
end process;
-- Most signals only require a synchronous reset
sync : process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
state <= ST_OFF;
nRESET_int <= '1';
else
state <= state_new;
nRESET_int <= nRESET_new;
timer0 <= timer0_new;
spidata <= spidata_new;
spistrobe <= spistrobe_new;
spicd <= spicd_new;
cmdcounter <= cmdcounter_new;
pointer <= pointer_new;
pixcol <= pixcol_new;
tilecol <= tilecol_new;
tilerow <= tilerow_new;
end if;
end if;
end process;
mapram : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 4,
DATA_WIDTH_B => 0,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 1,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => TRUE,
EN_RSTRAM_B => TRUE,
-- INIT_00 to INIT_3F: Initial memory contents.
INIT_00 => X"00008700006999e000e11120004f44c000691120001953100001f10000e195e0",
INIT_01 => X"0008f80000d555e000f99960001111e0006999f000f5552000ca990000699960",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"000000000052596000338420004afa20004f4f40000000000000900000000000",
INIT_05 => X"000084200000330000888880000065000088e8800048e840000c210000012c00",
INIT_06 => X"00008700006999e000e11120004f44c000691120001953100001f10000e195e0",
INIT_07 => X"00085000008421000044444000012480000065000000660000ca990000699960",
INIT_08 => X"00f991e0000888f0001999f000c211f0002111e0006999f000f444f000e1f960",
INIT_09 => X"00e111e000f480f000f080f0001111f0001248f0000e11200001f10000f888f0",
INIT_0A => X"00e161e000c212c000e111e00000f00000699910001ac8f000d251e0000888f0",
INIT_0B => X"0011111000000000000f11000024800000011f00001195300008780000348430",
INIT_0C => X"00e555900008f80000d555e000f99960001111e0006999f000f5552000000000",
INIT_0D => X"00e111e000f008f000f0e0f00001f100001a4f00000e11200000f000007888f0",
INIT_0E => X"00e161e000c212c000e111e00021e00000255590008008f000f44480008444f0",
INIT_0F => X"0044f440000000000008611000007000001168000019531000086900001a4a10",
INIT_10 => X"00e9996000000f7000b4a1e0001911f000002e200000e12000008000001555f0",
INIT_11 => X"00e161e000c2f2c00001e080001f0f000012c210000e99e0001e00c000555e40",
INIT_12 => X"00999ff000005800008448000088a8800024842000aaaaa000d303d000195310",
INIT_13 => X"005a5a5000c2c2c00000e120000e996000000f200044c640005d555000555d50",
INIT_14 => X"00a55580000070000044f44000d222d000199f900002f2c00000f00000000000",
INIT_15 => X"0000000000e1d5e000000000000000000025a48000d5559000e55de000000000",
INIT_16 => X"00088000000f0f00002c22f000000000008440000044c4000011d11000000000",
INIT_17 => X"0021196000fffff000d39080007a62800084a520000444000004c40000021040",
INIT_18 => X"004465800099f8f000f444f000f444f000f444f000f444f000f444f000f444f0",
INIT_19 => X"0001f1000001f1000001f1000001f100001555f0001555f0001555f0001555f0",
INIT_1A => X"0024842000e111e000e111e000e111e000e111e000e111e000f248f000e19f80",
INIT_1B => X"000c22f000c222f00008780000e111e000e111e000e111e000e111e000c2a6d0",
INIT_1C => X"0004658000d5e57000f5552000f5552000f5552000f5552000f5552000f55520",
INIT_1D => X"0000f0000000f0000000f0000000f00000d555e000d555e000d555e000d555e0",
INIT_1E => X"008a8880006999600069996000699960006999600069996000f008f000e99960",
INIT_1F => X"00000000000844f00008690000e111e000e111e000e111e000e111e000c2e3c0",
INIT_20 => X"0065444000044210004555700007210000465440003444200000720000354430",
INIT_21 => X"0024300000011100007000000011110000000070000111000034443000344430",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000650000025430002106600022721000171710000707000000700000000000",
INIT_25 => X"0021000000000000000000000000000000003000001030100001240000042100",
INIT_26 => X"0065444000044210004555700007210000465440003444200000720000354430",
INIT_27 => X"0034442000012400001111100004210000003300000033000034443000344430",
INIT_28 => X"0024443000444470004444700012447000244430003444700034443000344420",
INIT_29 => X"0034443000700170007212700000007000421070004740000004740000700070",
INIT_2A => X"0070007000700070007000700044744000444430003444700034443000344470",
INIT_2B => X"0000000000124210000744000000012000044700006544400070007000610160",
INIT_2C => X"0011110000243000000111000070000000111100000000700001110000012400",
INIT_2D => X"0001110000011010001101100000740000100700000500000000200000000070",
INIT_2E => X"0010001000100010001000100011711000111100000110100011110000011110",
INIT_2F => X"0053135000422210000034400000700000443000001111100010001000100010",
INIT_30 => X"0005200000223120001001000000007000100740002531000005210000511150",
INIT_31 => X"0001010000013100001111000011111000001220000344300001227000111000",
INIT_32 => X"0044477000244430003443000000200000210120002222200012221000445640",
INIT_33 => X"0052525000121210002430000003442000444700001311100000124000421000",
INIT_34 => X"0005552000007000005313500052225000244300000272100000500000000000",
INIT_35 => X"0044444000345530000000000064444000252100003555000035553000040400",
INIT_36 => X"0000000000474730000100100004200000355000002542000011711000075700",
INIT_37 => X"0000500000777770000100700010007000012520000757000000720000000000",
INIT_38 => X"0044443000447430000353000041114000455540000555000005310000013500",
INIT_39 => X"0005150000055500000531000001350000511150001555100015311000113510",
INIT_3A => X"0021012000411140004555400005550000053100000135000054445000344700",
INIT_3B => X"0002553000122270003420300050005000144410001420100010241000532210",
INIT_3C => X"0002221000110110000353000005150000455540000555000005310000013500",
INIT_3D => X"0002020000022200000420000000240000051500000555000005310000013500",
INIT_3E => X"0002000000020200002222200002220000042000000024000045545000052000",
INIT_3F => X"0000000000012270001420100002020000022200000420000000240000031100",
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) output: Port A data
DOA => DOA, -- 32-bit output: A port data output
DOPA => open, -- 4-bit output: A port parity output
-- Port B Data: 32-bit (each) output: Port B data
DOB => DOB, -- 32-bit output: B port data output
DOPB => open, -- 4-bit output: B port parity output
-- Port A Data: 32-bit (each) input: Port A data
DIA => x"00000000", -- 32-bit input: A port data input
DIPA => x"0", -- 4-bit input: A port parity input
-- Port B Data: 32-bit (each) input: Port B data
DIB => DIB, -- 32-bit input: B port data input
DIPB => DIPB, -- 4-bit input: B port parity input
-- Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals
ADDRA => ADDRA, -- 14-bit input: A port address input
CLKA => CLK, -- 1-bit input: A port clock input
ENA => '1', -- 1-bit input: A port enable input
REGCEA => '1', -- 1-bit input: A port register clock enable input
RSTA => RST, -- 1-bit input: A port register set/reset input
WEA => "0000", -- 4-bit input: Port A byte-wide write enable input
-- Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals
ADDRB => ADDRB, -- 14-bit input: B port address input
CLKB => CLK, -- 1-bit input: B port clock input
ENB => '0', -- 1-bit input: B port enable input
REGCEB => '0', -- 1-bit input: B port register clock enable input
RSTB => RST, -- 1-bit input: B port register set/reset input
WEB => "0000" -- 4-bit input: Port B byte-wide write enable input
);
ADDRA <= tilerow(0) & DOA2(7 downto 0) & std_logic_vector(pixcol) & "00";
ADDRB <= (others => '0');
DIB <= (others => '0');
DIPB <= (others => '0');
tileram : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 18,
DATA_WIDTH_B => 18,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 1,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => TRUE,
EN_RSTRAM_B => TRUE,
-- INIT_00 to INIT_3F: Initial memory contents.
INIT_00 => X"0020002000200020002000200020002000200020002000200020002000200020",
INIT_01 => X"ffffffffffffffffffffffffffffffffffffffff002000200020002000200020",
INIT_02 => X"0020002000200020002000200020002000200020002000200020002000200020",
INIT_03 => X"ffffffffffffffffffffffffffffffffffffffff002000200020002000200020",
INIT_04 => X"0020002000200020002000200020002000200020002000200020002000200020",
INIT_05 => X"ffffffffffffffffffffffffffffffffffffffff002000200020002000200020",
INIT_06 => X"0020003000300030002e003000300030002c003000300030002c003000300031",
INIT_07 => X"ffffffffffffffffffffffffffffffffffffffff0020002000200020007a0048",
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) output: Port A data
DOA => DOA2, -- 32-bit output: A port data output
DOPA => open, -- 4-bit output: A port parity output
-- Port B Data: 32-bit (each) output: Port B data
DOB => DOB2, -- 32-bit output: B port data output
DOPB => open, -- 4-bit output: B port parity output
-- Port A Data: 32-bit (each) input: Port A data
DIA => x"00000000", -- 32-bit input: A port data input
DIPA => x"0", -- 4-bit input: A port parity input
-- Port B Data: 32-bit (each) input: Port B data
DIB => DIB2, -- 32-bit input: B port data input
DIPB => x"0", -- 4-bit input: B port parity input
-- Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals
ADDRA => ADDRA2, -- 14-bit input: A port address input
CLKA => CLK, -- 1-bit input: A port clock input
ENA => '1', -- 1-bit input: A port enable input
REGCEA => '1', -- 1-bit input: A port register clock enable input
RSTA => RST, -- 1-bit input: A port register set/reset input
WEA => "0000", -- 4-bit input: Port A byte-wide write enable input
-- Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals
ADDRB => ADDRB2, -- 14-bit input: B port address input
CLKB => CLK, -- 1-bit input: B port clock input
ENB => '1', -- 1-bit input: B port enable input
REGCEB => '0', -- 1-bit input: B port register clock enable input
RSTB => RST, -- 1-bit input: B port register set/reset input
WEB => WEB2 -- 4-bit input: Port B byte-wide write enable input
);
ADDRA2 <= "000" & std_logic_vector(tilerow(2 downto 1)) & std_logic_vector(tilecol) & "0000";
ADDRB2 <= addr & "0000";
DIB2 <= x"0000" & data(15 downto 0);
WEB2 <= wen & wen & wen & wen;
end Behavioral;
| mit | 139a2d6fea301ca698d192b10730fd50 | 0.593469 | 3.753345 | false | false | false | false |
Fju/LeafySan | src/vhdl/toplevel/iac_pkg.vhdl | 1 | 17,362 | -----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Package File Constants
-- Author : Jan Dürre
-- Last update : 21.05.2015
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package iac_pkg is
-- other constants
constant CV_SYS_CLOCK_RATE : natural := 50000000; --50 MHz
-- addresses
-- seven seg
constant CW_DATA_SEVENSEG : natural := 16;
constant CW_ADDR_SEVENSEG : natural := 5;
constant CV_ADDR_SEVENSEG_DEC : std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0) := std_ulogic_vector(to_unsigned( 1, CW_ADDR_SEVENSEG));
constant CV_ADDR_SEVENSEG_HEX4 : std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0) := std_ulogic_vector(to_unsigned( 2, CW_ADDR_SEVENSEG));
constant CV_ADDR_SEVENSEG_HEX5 : std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0) := std_ulogic_vector(to_unsigned( 4, CW_ADDR_SEVENSEG));
constant CV_ADDR_SEVENSEG_HEX6 : std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0) := std_ulogic_vector(to_unsigned( 8, CW_ADDR_SEVENSEG));
constant CV_ADDR_SEVENSEG_HEX7 : std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0) := std_ulogic_vector(to_unsigned(16, CW_ADDR_SEVENSEG));
-- adc/dac
constant CW_DATA_ADC_DAC : natural := 12;
constant CW_ADDR_ADC_DAC : natural := 4;
constant CV_ADDR_ADC0 : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned( 0, CW_ADDR_ADC_DAC));
constant CV_ADDR_ADC1 : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned( 1, CW_ADDR_ADC_DAC));
constant CV_ADDR_ADC2 : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned( 2, CW_ADDR_ADC_DAC));
constant CV_ADDR_ADC3 : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned( 3, CW_ADDR_ADC_DAC));
constant CV_ADDR_ADC4 : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned( 4, CW_ADDR_ADC_DAC));
constant CV_ADDR_ADC5 : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned( 5, CW_ADDR_ADC_DAC));
constant CV_ADDR_ADC6 : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned( 6, CW_ADDR_ADC_DAC));
constant CV_ADDR_ADC7 : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned( 7, CW_ADDR_ADC_DAC));
constant CV_ADDR_DAC0 : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned( 8, CW_ADDR_ADC_DAC));
constant CV_ADDR_DAC1 : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned( 9, CW_ADDR_ADC_DAC));
constant CV_ADDR_ADC_DAC_CTRL : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0) := std_ulogic_vector(to_unsigned(10, CW_ADDR_ADC_DAC));
-- audio
constant CW_DATA_AUDIO : natural := 16;
constant CW_ADDR_AUDIO : natural := 2;
constant CV_ADDR_AUDIO_LEFT_IN : std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0) := std_ulogic_vector(to_unsigned(0, CW_ADDR_AUDIO));
constant CV_ADDR_AUDIO_RIGHT_IN : std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0) := std_ulogic_vector(to_unsigned(1, CW_ADDR_AUDIO));
constant CV_ADDR_AUDIO_LEFT_OUT : std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0) := std_ulogic_vector(to_unsigned(0, CW_ADDR_AUDIO));
constant CV_ADDR_AUDIO_RIGHT_OUT : std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0) := std_ulogic_vector(to_unsigned(1, CW_ADDR_AUDIO));
constant CV_ADDR_AUDIO_CONFIG : std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0) := std_ulogic_vector(to_unsigned(2, CW_ADDR_AUDIO));
constant CW_AUDIO_SAMPLE : natural := 16;
-- infrared
constant CW_DATA_IR : natural := 8;
constant CW_ADDR_IR : natural := 1;
constant CV_ADDR_IR_DATA : std_ulogic_vector(CW_ADDR_IR-1 downto 0) := std_ulogic_vector(to_unsigned(0, CW_ADDR_IR));
constant C_IR_BUTTON_A : std_ulogic_vector(7 downto 0) := x"0F";
constant C_IR_BUTTON_B : std_ulogic_vector(7 downto 0) := x"13";
constant C_IR_BUTTON_C : std_ulogic_vector(7 downto 0) := x"10";
constant C_IR_BUTTON_POWER : std_ulogic_vector(7 downto 0) := x"12";
constant C_IR_BUTTON_1 : std_ulogic_vector(7 downto 0) := x"01";
constant C_IR_BUTTON_2 : std_ulogic_vector(7 downto 0) := x"02";
constant C_IR_BUTTON_3 : std_ulogic_vector(7 downto 0) := x"03";
constant C_IR_BUTTON_4 : std_ulogic_vector(7 downto 0) := x"04";
constant C_IR_BUTTON_5 : std_ulogic_vector(7 downto 0) := x"05";
constant C_IR_BUTTON_6 : std_ulogic_vector(7 downto 0) := x"06";
constant C_IR_BUTTON_7 : std_ulogic_vector(7 downto 0) := x"07";
constant C_IR_BUTTON_8 : std_ulogic_vector(7 downto 0) := x"08";
constant C_IR_BUTTON_9 : std_ulogic_vector(7 downto 0) := x"09";
constant C_IR_BUTTON_0 : std_ulogic_vector(7 downto 0) := x"00";
constant C_IR_BUTTON_CHANNEL_UP : std_ulogic_vector(7 downto 0) := x"1A";
constant C_IR_BUTTON_CHANNEL_DOWN : std_ulogic_vector(7 downto 0) := x"1E";
constant C_IR_BUTTON_VOLUME_UP : std_ulogic_vector(7 downto 0) := x"1B";
constant C_IR_BUTTON_VOLUME_DOWN : std_ulogic_vector(7 downto 0) := x"1F";
constant C_IR_BUTTON_MUTE : std_ulogic_vector(7 downto 0) := x"0C";
constant C_IR_BUTTON_MENU : std_ulogic_vector(7 downto 0) := x"11";
constant C_IR_BUTTON_RETURN : std_ulogic_vector(7 downto 0) := x"17";
constant C_IR_BUTTON_PLAY : std_ulogic_vector(7 downto 0) := x"16";
constant C_IR_BUTTON_LEFT : std_ulogic_vector(7 downto 0) := x"14";
constant C_IR_BUTTON_RIGHT : std_ulogic_vector(7 downto 0) := x"18";
-- lcd
constant CW_DATA_LCD : natural := 8;
constant CW_ADDR_LCD : natural := 1;
constant CV_ADDR_LCD_DATA : std_ulogic_vector(CW_ADDR_LCD-1 downto 0) := std_ulogic_vector(to_unsigned(0, CW_ADDR_LCD));
constant CV_ADDR_LCD_STATUS : std_ulogic_vector(CW_ADDR_LCD-1 downto 0) := std_ulogic_vector(to_unsigned(0, CW_ADDR_LCD));
constant CS_LCD_BUFFER : natural := 32;
constant C_LCD_CLEAR : std_ulogic_vector(7 downto 0) := "00000000";
constant C_LCD_CURSOR_ON : std_ulogic_vector(7 downto 0) := "00000001";
constant C_LCD_CURSOR_OFF : std_ulogic_vector(7 downto 0) := "00000010";
constant C_LCD_BLINK_ON : std_ulogic_vector(7 downto 0) := "00000011";
constant C_LCD_BLINK_OFF : std_ulogic_vector(7 downto 0) := "00000100";
constant C_LCD_CURSOR_LEFT : std_ulogic_vector(7 downto 0) := "00000101";
constant C_LCD_CURSOR_RIGHT : std_ulogic_vector(7 downto 0) := "00000110";
-- sram
constant CW_DATA_SRAM : natural := 16;
constant CW_ADDR_SRAM : natural := 20;
-- uart
constant CW_DATA_UART : natural := 8;
constant CW_ADDR_UART : natural := 1;
constant CV_ADDR_UART_DATA_RX : std_ulogic_vector(CW_ADDR_UART-1 downto 0) := std_ulogic_vector(to_unsigned(0, CW_ADDR_UART));
constant CV_ADDR_UART_DATA_TX : std_ulogic_vector(CW_ADDR_UART-1 downto 0) := std_ulogic_vector(to_unsigned(0, CW_ADDR_UART));
constant CS_UART_BUFFER : natural := 256;
constant CV_UART_BAUDRATE : natural := 115200;
constant CV_UART_DATABITS : natural := 8;
constant CV_UART_STOPBITS : natural := 1;
constant CS_UART_PARITY : string := "NONE";
-- modules enable (0/1)
constant CV_EN_SEVENSEG : natural := 1;
constant CV_EN_ADC_DAC : natural := 1;
constant CV_EN_AUDIO : natural := 1;
constant CV_EN_IR : natural := 1;
constant CV_EN_LCD : natural := 1;
constant CV_EN_SRAM : natural := 1;
constant CV_EN_UART : natural := 1;
-- functions
-- generic
-- constant integer log to base 2
function to_log2 (constant input : natural) return natural;
-- constant integer log to base 16
function to_log16 (constant input : natural) return natural;
-- bcd decode
function to_bcd (binary : std_ulogic_vector; constant no_dec_digits : natural) return std_ulogic_vector;
-- vector generation from single bit
function to_vector(single_bit : std_ulogic; constant size : natural) return std_ulogic_vector;
function to_vector(single_bit : std_logic; constant size : natural) return std_logic_vector;
-- min / max
function max(a, b: integer) return integer;
function max(a, b: unsigned) return unsigned;
function max(a, b, c: integer) return integer;
function max(a, b, c: unsigned) return unsigned;
function min(a, b: integer) return integer;
function min(a, b: unsigned) return unsigned;
function min(a, b, c: integer) return integer;
function min(a, b, c: unsigned) return unsigned;
-- lcd
-- convert character or string to ascii binary vector
function ascii(input_char : character) return std_ulogic_vector;
-- additional LUT just for numbers (0 to 9), to prevent a large complete ASCII-LUT when only numbers are required
function ascii(input_number : unsigned(3 downto 0)) return std_ulogic_vector;
function asciitext(constant input_string : string) return std_ulogic_vector;
-- generate hex-string from binary numbers (length of binary vector has to be multiple of 4)
function hex(input_vector : std_ulogic_vector) return string;
-- convert std_ulogic_vector to array of commands for LCD-display
type lcd_commands_t is array (natural range <>) of std_ulogic_vector(7 downto 0);
function lcd_cmd(input_vector : std_ulogic_vector) return lcd_commands_t;
-- convert coordinate into bit-command for lcd-display
function lcd_cursor_pos(row : natural; col : natural) return std_ulogic_vector;
-- uart
function calc_parity(data : std_ulogic_vector; parity : string) return std_ulogic;
end;
package body iac_pkg is
-- generic
-- constant integer log to base 2
function to_log2 (constant input : natural) return natural is
variable temp : natural := 2;
variable res : natural := 1;
begin
if temp < input then
while temp < input loop
temp := temp * 2;
res := res + 1;
end loop;
end if;
return res;
end function;
-- constant integer log to base 16
function to_log16 (constant input : natural) return natural is
variable temp : natural := 16;
variable res : natural := 1;
begin
if temp < input then
while temp < input loop
temp := temp * 16;
res := res + 1;
end loop;
end if;
return res;
end function;
-- bcd decode, returns n 4-bit-bcd packages (implemented with double daddle algorithm http://en.wikipedia.org/wiki/Double_dabble), fully synthezisable
function to_bcd (binary : std_ulogic_vector; constant no_dec_digits : natural) return std_ulogic_vector is
variable tmp : std_ulogic_vector(binary'length + 4*no_dec_digits -1 downto 0) := (others => '0');
begin
tmp(binary'length-1 downto 0) := binary;
-- loop for n times
for i in 0 to binary'length-1 loop
-- check if any of the 3 bcd digits is greater than 4
for j in no_dec_digits-1 downto 0 loop
if unsigned(tmp((j+1)*4 -1 + binary'length downto j*4+ binary'length)) > to_unsigned(4, 4) then
-- add 3
tmp((j+1)*4 - 1 + binary'length downto j*4+ binary'length) := std_ulogic_vector(unsigned(tmp((j+1)*4 - 1 + binary'length downto j*4+ binary'length)) + to_unsigned(3, 4));
end if;
end loop;
-- shift left
tmp := tmp(tmp'length-2 downto 0) & '0';
end loop;
return tmp(tmp'length-1 downto binary'length);
end function;
-- vector generation from single bit: returns a vector, each bit consists of single_bit
function to_vector(single_bit : std_ulogic; constant size : natural) return std_ulogic_vector is
variable tmp : std_ulogic_vector(size-1 downto 0);
begin
for i in 0 to size-1 loop
tmp(i) := single_bit;
end loop;
return tmp;
end function;
function to_vector(single_bit : std_logic; constant size : natural) return std_logic_vector is
variable tmp : std_logic_vector(size-1 downto 0);
begin
for i in 0 to size-1 loop
tmp(i) := single_bit;
end loop;
return tmp;
end function;
-- min / max
function max(a, b: integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function max(a, b: unsigned) return unsigned is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function max(a, b, c: integer) return integer is
begin
return max(max(a,b),c);
end function;
function max(a, b, c: unsigned) return unsigned is
begin
return max(max(a,b),c);
end function;
function min(a, b: integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
function min(a, b, c: integer) return integer is
begin
return min(min(a,b),c);
end function;
function min(a, b, c: unsigned) return unsigned is
begin
return min(min(a,b),c);
end function;
-- lcd
-- convert character or string to ascii binary vector
function ascii(input_char : character) return std_ulogic_vector is
begin
return std_ulogic_vector(to_unsigned(character'pos(input_char),8));
end function;
-- additional LUT just for numbers (0 to 9), to prevent a large complete ASCII-LUT when only numbers are required
function ascii(input_number : unsigned(3 downto 0)) return std_ulogic_vector is
begin
if input_number = "0000" then return "0011" & std_ulogic_vector(input_number); -- 0
elsif input_number = "0001" then return "0011" & std_ulogic_vector(input_number); -- 1
elsif input_number = "0010" then return "0011" & std_ulogic_vector(input_number); -- 2
elsif input_number = "0011" then return "0011" & std_ulogic_vector(input_number); -- 3
elsif input_number = "0100" then return "0011" & std_ulogic_vector(input_number); -- 4
elsif input_number = "0101" then return "0011" & std_ulogic_vector(input_number); -- 5
elsif input_number = "0110" then return "0011" & std_ulogic_vector(input_number); -- 6
elsif input_number = "0111" then return "0011" & std_ulogic_vector(input_number); -- 7
elsif input_number = "1000" then return "0011" & std_ulogic_vector(input_number); -- 8
elsif input_number = "1001" then return "0011" & std_ulogic_vector(input_number); -- 9
else return "01011000"; -- unexpected: return X
end if;
end function;
function asciitext(constant input_string : string) return std_ulogic_vector is
variable returntext : std_ulogic_vector((8*input_string'length)-1 downto 0);
begin
for i in 0 to input_string'length-1 loop
returntext((i+1)*8 -1 downto i*8) := std_ulogic_vector(to_unsigned(character'pos(input_string(input_string'length-i)),8));
end loop;
return returntext;
end function;
-- generate hex-string from binary numbers (length of binary vector has to be multiple of 4)
function hex(input_vector : std_ulogic_vector) return string is
variable tempchar : character;
variable four_block : std_ulogic_vector(3 downto 0);
variable returnstring : string(1 to input_vector'length/4);
begin
for i in 0 to input_vector'length/4 -1 loop
four_block := input_vector((i+1)*4 -1 downto i*4);
case four_block is
when "0000" => tempchar := '0';
when "0001" => tempchar := '1';
when "0010" => tempchar := '2';
when "0011" => tempchar := '3';
when "0100" => tempchar := '4';
when "0101" => tempchar := '5';
when "0110" => tempchar := '6';
when "0111" => tempchar := '7';
when "1000" => tempchar := '8';
when "1001" => tempchar := '9';
when "1010" => tempchar := 'A';
when "1011" => tempchar := 'B';
when "1100" => tempchar := 'C';
when "1101" => tempchar := 'D';
when "1110" => tempchar := 'E';
when "1111" => tempchar := 'F';
when others => tempchar := 'U';
end case;
returnstring(input_vector'length/4 - i) := tempchar;
end loop;
return returnstring;
end function;
-- convert std_ulogic_vector to array of commands for LCD-display
function lcd_cmd(input_vector : std_ulogic_vector) return lcd_commands_t is
variable input_vector_dirnorm : std_ulogic_vector(input_vector'length-1 downto 0);
variable return_array : lcd_commands_t(0 to (input_vector'length/8)-1);
begin
input_vector_dirnorm := input_vector;
for i in 0 to (input_vector'length/8)-1 loop
for j in 0 to 7 loop
return_array(i)(7-j) := input_vector_dirnorm(input_vector'length -1 -i*8 - j);
end loop;
end loop;
return return_array;
end function;
-- convert coordinate into bit-command for lcd-display
function lcd_cursor_pos(row : natural; col : natural) return std_ulogic_vector is
begin
if row = 0 then
return "1000" & std_ulogic_vector(to_unsigned(col, 4));
else
return "1001" & std_ulogic_vector(to_unsigned(col, 4));
end if;
end function;
-- uart
function calc_parity(data : std_ulogic_vector; parity : string) return std_ulogic is
variable v : std_ulogic;
begin
for i in 0 to data'length-1 loop
v := v xor data(i);
end loop;
if parity = "EVEN" then
return v;
else
return not v;
end if;
end function;
end iac_pkg;
| apache-2.0 | ec3fe283601ff2cb3b28870754e3ba09 | 0.655454 | 2.991385 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/demux/myDemux2.vhdl | 1 | 622 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myDemux2 is
port(a: in std_logic; sel: in std_logic; s: out std_logic; s2: out std_logic);
end myDemux2;
architecture behavioral of myDemux2 is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myNot
port(a: in std_logic; s: out std_logic);
end component;
signal selNot: std_logic;
begin
myNot_1: myNot port map(a => sel, s => selNot);
myAnd2_1: myAnd2 port map(a => a, b => selNot, s => s);
myAnd2_2: myAnd2 port map(a => a, b => sel, s => s2);
end behavioral;
| mit | bd61b0bddad81ec968c625201c7a8af1 | 0.630225 | 2.866359 | false | false | false | false |
bittner/geany | data/filetypes.vhdl | 1 | 3,020 | # For complete documentation of this file, please see Geany's main documentation
[styling]
# Edit these in the colorscheme .conf file instead
default=default
comment=comment
comment_line_bang=comment_line
number=number_1
string=string_1
operator=operator
identifier=identifier_1
stringeol=string_eol
keyword=keyword_1
stdoperator=operator
attribute=attribute
stdfunction=function
stdpackage=preprocessor
stdtype=type
userword=keyword_2
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# MIME type
mime_type=text/x-vhdl
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
| gpl-2.0 | 10ceaf1bd1aacf7684e0a9cdfa53c8a9 | 0.817219 | 4.108844 | false | false | false | false |
timofonic/1541UltimateII | fpga/6502/vhdl_source/proc_interrupt.vhd | 2 | 3,377 | library ieee;
use ieee.std_logic_1164.all;
entity proc_interrupt is
port (
clock : in std_logic;
clock_en : in std_logic;
clock_en_f : in std_logic;
ready : in std_logic;
reset : in std_logic;
irq_n : in std_logic;
nmi_n : in std_logic;
i_flag : in std_logic;
irq_done : in std_logic;
interrupt : out std_logic;
vect_sel : out std_logic_vector(2 downto 1) );
end proc_interrupt;
architecture gideon of proc_interrupt is
signal irq_c : std_logic := '1';
signal irq_cc : std_logic := '1';
signal irq_d1 : std_logic := '0';
signal irq_d2 : std_logic := '0';
signal nmi_c : std_logic := '0';
signal nmi_d1 : std_logic := '0';
signal nmi_d2 : std_logic := '0';
signal nmi_act : std_logic := '0';
signal ready_d : std_logic := '1';
signal vect_h : std_logic_vector(2 downto 1) := "10";
type state_t is (idle, do_nmi); --, do_nmi, wait_vector);
signal state : state_t;
signal resetting : std_logic := '1';
-- 21
-- NMI 1 01-
-- RESET 1 10-
-- IRQ 1 11-
function calc_vec_addr(rst, irq, nmi : std_logic) return std_logic_vector is
variable v : std_logic_vector(2 downto 1);
begin
if rst='1' then
v := "10";
elsif nmi='1' then
v := "01";
else
v := "11";
end if;
return v;
end function;
begin
vect_sel <= vect_h;
interrupt <= ((irq_d1 and not i_flag) or nmi_act);
process(clock)
begin
if rising_edge(clock) then
nmi_c <= not nmi_n;
if clock_en='1' then
-- if ready='1' then
irq_c <= irq_n;
-- end if;
end if;
if clock_en='1' then
if ready='1' then
nmi_d1 <= nmi_c;
irq_d1 <= not (irq_c);
end if;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
-- ready_d <= ready;
nmi_d2 <= nmi_d1;
if nmi_d2 = '0' and nmi_d1 = '1' then -- edge
nmi_act <= '1';
end if;
vect_h <= calc_vec_addr(resetting, irq_d1, nmi_act);
case state is
when idle =>
if nmi_act = '1' then
state <= do_nmi;
end if;
when do_nmi =>
if irq_done='1' then
nmi_act <= '0'; -- ###
state <= idle;
resetting <= '0';
end if;
when others =>
state <= idle;
end case;
end if;
if reset='1' then
state <= do_nmi;
nmi_act <= '0';
resetting <= '1';
vect_h <= "10";
end if;
end if;
end process;
end gideon;
| gpl-3.0 | c096e08adcb91ecc2f2368157a5d5c87 | 0.395617 | 3.846241 | false | false | false | false |
Fju/LeafySan | src/vhdl/interfaces/seven_seg.vhdl | 1 | 7,673 | -----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : 7-Segment Display
-- Author : Jan Dürre
-- Last update : 22.07.2014
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity seven_seg is
port(
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- 7-Seg
hex0_n : out std_ulogic_vector(6 downto 0);
hex1_n : out std_ulogic_vector(6 downto 0);
hex2_n : out std_ulogic_vector(6 downto 0);
hex3_n : out std_ulogic_vector(6 downto 0);
hex4_n : out std_ulogic_vector(6 downto 0);
hex5_n : out std_ulogic_vector(6 downto 0);
hex6_n : out std_ulogic_vector(6 downto 0);
hex7_n : out std_ulogic_vector(6 downto 0)
);
end seven_seg;
architecture rtl of seven_seg is
-- array for easier use of hex0_n to hex7_n
type seg_t is array (0 to 3) of std_ulogic_vector(6 downto 0);
signal hex_seg, dec_seg : seg_t;
-- 7-Segment Displays
-- [][] [][] | [][][][]
-- hex-display | decimal-display (-999 to 999)
-- A4A3A2A1 | A0
-- +-----+
-- | 0 |
-- | 5 1 |
-- | 6 |
-- | 4 2 |
-- | 3 |
-- +-----+
-- register for each hex-display
type hex_display_t is array (0 to 3) of std_ulogic_vector(3 downto 0);
signal hex_display, hex_display_nxt : hex_display_t;
-- register for decimal-display and sign-symbol
signal dec_display, dec_display_nxt : std_ulogic_vector(to_log2(1000)-1 downto 0); -- 0...999
signal dec_sign, dec_sign_nxt : std_ulogic;
-- register to active 7-seg-displays
signal display_active, display_active_nxt : std_ulogic_vector(4 downto 0);
begin
-- connect and invert signal seg to output
hex0_n <= not dec_seg(0);
hex1_n <= not dec_seg(1);
hex2_n <= not dec_seg(2);
hex3_n <= not dec_seg(3);
hex4_n <= not hex_seg(0);
hex5_n <= not hex_seg(1);
hex6_n <= not hex_seg(2);
hex7_n <= not hex_seg(3);
-- sequential process
process(clock, reset_n)
begin
-- async reset
if reset_n = '0' then
hex_display <= (others => (others => '0'));
dec_display <= (others => '0');
dec_sign <= '0';
display_active <= (others =>'0');
elsif rising_edge(clock) then
hex_display <= hex_display_nxt;
dec_display <= dec_display_nxt;
dec_sign <= dec_sign_nxt;
display_active <= display_active_nxt;
end if;
end process;
-- bus interface
process(hex_display, dec_display, dec_sign, iobus_cs, iobus_addr, iobus_din, iobus_wr, display_active)
begin
-- standard: hold register values
hex_display_nxt <= hex_display;
dec_display_nxt <= dec_display;
dec_sign_nxt <= dec_sign;
display_active_nxt <= display_active;
-- dout always "0..0", no readable registers available
iobus_dout <= (others => '0');
-- chip select
if iobus_cs = '1' then
-- write (no read allowed)
if iobus_wr = '1' then
-- decode LSB: choose if hex_display or dec_display is changed
if iobus_addr(0) = '1' then
-- dec
-- check MSB for positive or negative number
if iobus_din(iobus_din'length-1) = '0' then
dec_display_nxt <= iobus_din(dec_display'length-1 downto 0);
dec_sign_nxt <= '0';
else
-- save positive value
dec_display_nxt <= std_ulogic_vector(-signed(iobus_din(dec_display'length-1 downto 0)));
dec_sign_nxt <= '1';
end if;
-- activate dec-display
display_active_nxt(0) <= '1';
else
-- hex
-- check bits 1 to 4 of iobus_addr
for i in 0 to 3 loop
-- check if register should be changed
if iobus_addr(i+1) = '1' then
-- write date to array
hex_display_nxt(i) <= iobus_din(i*4 + 3 downto i*4);
-- activate display
display_active_nxt(i+1) <= '1';
end if;
end loop;
end if;
end if;
end if;
end process;
-- decode LUT for hex-displays
process(hex_display, display_active)
begin
-- for each hex-display
for i in 0 to 3 loop
-- check if display is active / has been written to
if display_active(i+1) = '1' then
case hex_display(i) is
when "0000" => hex_seg(i) <= "0111111"; -- 0
when "0001" => hex_seg(i) <= "0000110"; -- 1
when "0010" => hex_seg(i) <= "1011011"; -- 2
when "0011" => hex_seg(i) <= "1001111"; -- 3
when "0100" => hex_seg(i) <= "1100110"; -- 4
when "0101" => hex_seg(i) <= "1101101"; -- 5
when "0110" => hex_seg(i) <= "1111101"; -- 6
when "0111" => hex_seg(i) <= "0000111"; -- 7
when "1000" => hex_seg(i) <= "1111111"; -- 8
when "1001" => hex_seg(i) <= "1101111"; -- 9
when "1010" => hex_seg(i) <= "1110111"; -- A
when "1011" => hex_seg(i) <= "1111100"; -- b
when "1100" => hex_seg(i) <= "0111001"; -- C
when "1101" => hex_seg(i) <= "1011110"; -- d
when "1110" => hex_seg(i) <= "1111001"; -- E
when "1111" => hex_seg(i) <= "1110001"; -- F
when others => hex_seg(i) <= "1111001"; -- wrong value: display E
end case;
-- deactivate display
else
hex_seg(i) <= (others => '0');
end if;
end loop;
end process;
-- decode LUT for dec-display
process(dec_display, dec_sign, display_active)
variable bcd : std_ulogic_vector(11 downto 0);
begin
-- check if display is active / has been written to
if display_active(0) = '1' then
-- if value is too big
if unsigned(dec_display) > to_unsigned(999, dec_display'length) then
-- display E (for "Error")
dec_seg(0) <= "1111001";
dec_seg(1) <= "0000000";
dec_seg(2) <= "0000000";
dec_seg(3) <= "0000000";
else
-- convert binary to bcd
bcd := to_bcd(dec_display, 3);
-- for each bcd digit
for i in 0 to 2 loop
if bcd((i+1)*4 -1 downto i*4) = "0000" then dec_seg(i) <= "0111111"; -- 0
elsif bcd((i+1)*4 -1 downto i*4) = "0001" then dec_seg(i) <= "0000110"; -- 1
elsif bcd((i+1)*4 -1 downto i*4) = "0010" then dec_seg(i) <= "1011011"; -- 2
elsif bcd((i+1)*4 -1 downto i*4) = "0011" then dec_seg(i) <= "1001111"; -- 3
elsif bcd((i+1)*4 -1 downto i*4) = "0100" then dec_seg(i) <= "1100110"; -- 4
elsif bcd((i+1)*4 -1 downto i*4) = "0101" then dec_seg(i) <= "1101101"; -- 5
elsif bcd((i+1)*4 -1 downto i*4) = "0110" then dec_seg(i) <= "1111101"; -- 6
elsif bcd((i+1)*4 -1 downto i*4) = "0111" then dec_seg(i) <= "0000111"; -- 7
elsif bcd((i+1)*4 -1 downto i*4) = "1000" then dec_seg(i) <= "1111111"; -- 8
elsif bcd((i+1)*4 -1 downto i*4) = "1001" then dec_seg(i) <= "1101111"; -- 9
else dec_seg(i) <= "1111001"; -- wrong value: display E
end if;
end loop;
-- sign-symbol
if dec_sign = '1' then
dec_seg(3) <= "1000000";
else
-- turn off sign-symbol
dec_seg(3) <= (others => '0');
end if;
end if;
-- deactivate display
else
dec_seg(0) <= (others => '0');
dec_seg(1) <= (others => '0');
dec_seg(2) <= (others => '0');
dec_seg(3) <= (others => '0');
end if;
end process;
end rtl; | apache-2.0 | 02a22d0470e4d51459c6e703dcfb3d2d | 0.542161 | 2.776049 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sources_1/hex2bcd.vhd | 1 | 2,491 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity hex2bcd is
Generic ( precision : integer;
width : integer;
bits : integer;
ndigits : integer := 4 );
Port ( hex : in unsigned (precision-1 downto 0);
bcd : out STD_LOGIC_VECTOR (width-1 downto 0);
strobe : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC );
end hex2bcd;
architecture Behavioral of hex2bcd is
signal shifter, shifter_next : unsigned (precision+width-1 downto 0);
signal busy, busy_next : std_logic;
signal count : unsigned(bits-1 downto 0) := (others => '0');
signal count_next : unsigned(bits-1 downto 0);
signal bcd_int, bcd_next : unsigned(bcd'range);
constant a : integer := shifter'high; -- For convenience
begin
bcd <= std_logic_vector(bcd_int);
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
busy <= '0';
else
shifter <= shifter_next;
busy <= busy_next;
count <= count_next;
bcd_int <= bcd_next;
end if;
end if;
end process;
process(hex, strobe, shifter, busy, count, bcd_int)
variable shifter_new : unsigned (precision+width-1 downto 0);
variable busy_new : std_logic;
variable count_new : unsigned(count'range);
begin
shifter_new := shifter;
busy_new := busy;
count_new := count;
bcd_next <= bcd_int;
if busy /= '1' and strobe = '1' then
shifter_new := (others => '0');
shifter_new(hex'range) := hex;
busy_new := '1';
count_new := (others => '0');
end if;
if count = precision then
busy_new := '0';
bcd_next <= shifter(shifter'high downto shifter'high-width+1);
count_new := (others => '0');
elsif busy = '1' then
for I in 0 to ndigits-1 loop
if shifter_new(a-4*I downto a-4*I-3) > "0100" then
shifter_new(a-4*I downto a-4*I-3) := shifter_new(a-4*I downto a-4*I-3) + "0011";
end if;
end loop;
shifter_new := shift_left(shifter_new, 1);
count_new := count + "1";
end if;
shifter_next <= shifter_new;
busy_next <= busy_new;
count_next <= count_new;
end process;
end Behavioral;
| mit | e7b46f07d72c3092df9e91008a283131 | 0.523083 | 3.791476 | false | false | false | false |
timofonic/1541UltimateII | fpga/6502/vhdl_source/shifter.vhd | 2 | 2,033 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shifter is
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic := '1'; -- instruction(1)
no_data_shift : in std_logic := '0';
c_in : in std_logic;
n_in : in std_logic;
z_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
c_out : out std_logic;
n_out : out std_logic;
z_out : out std_logic;
data_out : out std_logic_vector(7 downto 0) := X"00");
end shifter;
architecture gideon of shifter is
signal data_out_i : std_logic_vector(7 downto 0) := X"00";
signal zero : std_logic := '0';
signal oper4 : std_logic_vector(3 downto 0) := X"0";
begin
-- ASL $nn ROL $nn LSR $nn ROR $nn STX $nn LDX $nn DEC $nn INC $nn
with operation & no_data_shift select data_out_i <=
data_in(6 downto 0) & '0' when "0000",
data_in(6 downto 0) & c_in when "0010",
'0' & data_in(7 downto 1) when "0100",
c_in & data_in(7 downto 1) when "0110",
data_in - 1 when "1100",
data_in + 1 when "1110",
data_in when others;
zero <= '1' when data_out_i = X"00" else '0';
oper4 <= enable & operation;
with oper4 select c_out <=
data_in(7) when "1000" | "1001",
data_in(0) when "1010" | "1011",
c_in when others;
with oper4 select z_out <=
zero when "1000" | "1001" | "1010" | "1011" | "1101" | "1110" | "1111",
z_in when others;
with oper4 select n_out <=
data_out_i(7) when "1000" | "1001" | "1010" | "1011" | "1101" | "1110" | "1111",
n_in when others;
data_out <= data_out_i when enable='1' and no_data_shift='0' else data_in;
end gideon; | gpl-3.0 | c72d0fe07bf7de3fcb3c1edd711805f5 | 0.484014 | 3.181534 | false | false | false | false |
Fju/LeafySan | src/vhdl/testbench/iac_testbench.vhdl | 1 | 15,573 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Testbench
-- Last update : 28.11.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.standard.all;
use std.textio.all;
use std.env.all;
library work;
use work.iac_pkg.all;
entity iac_testbench is
end iac_testbench;
architecture sim of iac_testbench is
constant SYSTEM_CYCLE_TIME : time := 20 ns; -- 50MHz
constant SIMULATION_TIME : time := 100000 * SYSTEM_CYCLE_TIME;
constant FULL_DEBUG : natural := 0;
constant SIMULATION_MODE : boolean := true;
signal clock, reset_n, reset : std_ulogic;
signal end_simulation : std_ulogic;
-- 7_seg
signal hex0_n : std_ulogic_vector(6 downto 0);
signal hex1_n : std_ulogic_vector(6 downto 0);
signal hex2_n : std_ulogic_vector(6 downto 0);
signal hex3_n : std_ulogic_vector(6 downto 0);
signal hex4_n : std_ulogic_vector(6 downto 0);
signal hex5_n : std_ulogic_vector(6 downto 0);
signal hex6_n : std_ulogic_vector(6 downto 0);
signal hex7_n : std_ulogic_vector(6 downto 0);
-- gpio
signal gpio : std_logic_vector(15 downto 0);
-- lcd
signal lcd_en : std_ulogic;
signal lcd_rs : std_ulogic;
signal lcd_rw : std_ulogic;
signal lcd_on : std_ulogic;
signal lcd_blon : std_ulogic;
signal lcd_dat : std_ulogic_vector(7 downto 0);
-- led/switches/keys
signal led_green : std_ulogic_vector(8 downto 0);
signal led_red : std_ulogic_vector(17 downto 0);
signal switch : std_ulogic_vector(17 downto 0);
signal key_n, key : std_ulogic_vector(2 downto 0);
-- adc_dac
signal exb_adc_switch : std_ulogic_vector(2 downto 0);
signal exb_adc_en_n : std_ulogic;
signal exb_dac_ldac_n : std_ulogic;
signal exb_spi_clk : std_ulogic;
signal exb_spi_mosi : std_ulogic;
signal exb_spi_miso : std_logic;
signal exb_spi_cs_adc_n : std_ulogic;
signal exb_spi_cs_dac_n : std_ulogic;
-- sram
signal sram_ce_n : std_ulogic;
signal sram_oe_n : std_ulogic;
signal sram_we_n : std_ulogic;
signal sram_ub_n : std_ulogic;
signal sram_lb_n : std_ulogic;
signal sram_addr : std_ulogic_vector(19 downto 0);
signal sram_dq : std_logic_vector(15 downto 0);
-- uart
signal uart_rts : std_ulogic;
signal uart_cts : std_ulogic;
signal uart_rxd : std_ulogic;
signal uart_txd : std_ulogic;
-- audio
signal aud_xclk : std_ulogic;
signal aud_bclk : std_ulogic;
signal aud_adc_lrck : std_ulogic;
signal aud_adc_dat : std_ulogic;
signal aud_dac_lrck : std_ulogic;
signal aud_dac_dat : std_ulogic;
signal i2c_sdat : std_logic;
signal i2c_sclk : std_ulogic;
-- infrared
signal irda_rxd : std_ulogic;
component iac_toplevel is
generic (
SIMULATION : boolean
);
port (
-- global signals
clock_ext_50 : in std_ulogic;
clock_ext2_50 : in std_ulogic;
clock_ext3_50 : in std_ulogic;
reset_n : in std_ulogic; -- (key3)
-- 7_seg
hex0_n : out std_ulogic_vector(6 downto 0);
hex1_n : out std_ulogic_vector(6 downto 0);
hex2_n : out std_ulogic_vector(6 downto 0);
hex3_n : out std_ulogic_vector(6 downto 0);
hex4_n : out std_ulogic_vector(6 downto 0);
hex5_n : out std_ulogic_vector(6 downto 0);
hex6_n : out std_ulogic_vector(6 downto 0);
hex7_n : out std_ulogic_vector(6 downto 0);
-- gpio
gpio : inout std_logic_vector(15 downto 0);
-- lcd
lcd_en : out std_ulogic;
lcd_rs : out std_ulogic;
lcd_rw : out std_ulogic;
lcd_on : out std_ulogic;
lcd_blon : out std_ulogic;
lcd_dat : out std_ulogic_vector(7 downto 0);
-- led/switches/keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key_n : in std_ulogic_vector(2 downto 0);
-- adc_dac
exb_adc_switch : out std_ulogic_vector(2 downto 0);
exb_adc_en_n : out std_ulogic;
exb_dac_ldac_n : out std_ulogic;
exb_spi_clk : out std_ulogic;
exb_spi_mosi : out std_ulogic;
exb_spi_miso : in std_logic;
exb_spi_cs_adc_n : out std_ulogic;
exb_spi_cs_dac_n : out std_ulogic;
-- sram
sram_ce_n : out std_ulogic;
sram_oe_n : out std_ulogic;
sram_we_n : out std_ulogic;
sram_ub_n : out std_ulogic;
sram_lb_n : out std_ulogic;
sram_addr : out std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0);
-- uart
uart_rts : in std_ulogic;
uart_cts : out std_ulogic;
uart_rxd : in std_ulogic;
uart_txd : out std_ulogic;
-- audio
aud_xclk : out std_ulogic;
aud_bclk : in std_ulogic;
aud_adc_lrck : in std_ulogic;
aud_adc_dat : in std_ulogic;
aud_dac_lrck : in std_ulogic;
aud_dac_dat : out std_ulogic;
i2c_sdat : inout std_logic;
i2c_sclk : inout std_logic;
-- infrared
irda_rxd : in std_ulogic
);
end component iac_toplevel;
component io_model is
generic(
-- file containing static bit-settings for io's
FILE_NAME_SET : string
);
port(
-- io's
gpio : inout std_logic_vector(15 downto 0);
switch : out std_ulogic_vector(17 downto 0);
key : out std_ulogic_vector(2 downto 0)
);
end component io_model;
component adc_model is
generic(
SYSTEM_CYCLE_TIME : time;
FULL_DEBUG : natural;
FILE_NAME_PRELOAD : string
);
port(
-- Global Signals
end_simulation : in std_logic;
-- SPI Signals
spi_clk : in std_ulogic;
spi_miso : out std_logic;
spi_cs_n : in std_ulogic;
-- Switch Signals
swt_select : in std_ulogic_vector(2 downto 0);
swt_enable_n : in std_ulogic
);
end component adc_model;
component dac_model is
generic(
SYSTEM_CYCLE_TIME : time;
FILE_NAME_DUMP : string
);
port(
-- Global Signals
end_simulation : in std_logic;
-- SPI Signals
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_cs_n : in std_ulogic;
-- DAC Signals
dac_ldac_n : in std_ulogic
);
end component dac_model;
component seven_seg_model is
generic (
SYSTEM_CYCLE_TIME : time
);
port (
-- Global Signals
end_simulation : in std_ulogic;
-- 7-seg connections
hex0_n : in std_ulogic_vector(6 downto 0);
hex1_n : in std_ulogic_vector(6 downto 0);
hex2_n : in std_ulogic_vector(6 downto 0);
hex3_n : in std_ulogic_vector(6 downto 0);
hex4_n : in std_ulogic_vector(6 downto 0);
hex5_n : in std_ulogic_vector(6 downto 0);
hex6_n : in std_ulogic_vector(6 downto 0);
hex7_n : in std_ulogic_vector(6 downto 0)
);
end component seven_seg_model;
component infrared_model is
generic (
SYSTEM_CYCLE_TIME : time;
-- file with bytes to be send to fpga
FILE_NAME_COMMAND : string;
-- custom code of ir-sender
CUSTOM_CODE : std_ulogic_vector(15 downto 0);
SIMULATION : boolean
);
port (
-- global signals
end_simulation : in std_ulogic;
-- ir-pin
irda_txd : out std_ulogic
);
end component infrared_model;
component lcd_model is
generic(
SYSTEM_CYCLE_TIME : time;
FULL_DEBUG : natural
);
port(
-- Global Signals
end_simulation : in std_ulogic;
-- LCD Signals
disp_en : in std_ulogic;
disp_rs : in std_ulogic;
disp_rw : in std_ulogic;
disp_dat : in std_ulogic_vector(7 downto 0)
);
end component lcd_model;
component sram_model is
generic(
SYSTEM_CYCLE_TIME : time;
FULL_DEBUG : natural;
-- file for preload of sram
FILE_NAME_PRELOAD : string;
-- file for dump at end of simulation
FILE_NAME_DUMP : string;
-- number of addressable words in sram (size of sram)
GV_SRAM_SIZE : natural
);
port(
-- global signals
end_simulation : in std_ulogic;
-- sram connections
sram_ce_n : in std_ulogic;
sram_oe_n : in std_ulogic;
sram_we_n : in std_ulogic;
sram_ub_n : in std_ulogic;
sram_lb_n : in std_ulogic;
sram_addr : in std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0)
);
end component sram_model;
component uart_model is
generic (
SYSTEM_CYCLE_TIME : time;
-- file with data to be send to fpga
FILE_NAME_COMMAND : string;
-- file for dump of data, received by pc
FILE_NAME_DUMP : string;
-- communication speed for uart-link
BAUD_RATE : natural;
SIMULATION : boolean
);
port (
-- global signals
end_simulation : in std_ulogic;
-- uart-pins (pc side)
rx : in std_ulogic;
tx : out std_ulogic
);
end component uart_model;
signal i2c_sdat_pullup_wire : std_logic;
signal i2c_sclk_pullup_wire : std_logic;
component acodec_model is
generic (
SAMPLE_WIDTH : natural;
SAMPLE_RATE : natural;
SAMPLE_FILE : string
);
port (
-- acodec signals
aud_xclk : in std_ulogic;
aud_bclk : out std_ulogic;
aud_adc_lrck : out std_ulogic;
aud_adc_dat : out std_ulogic;
aud_dac_lrck : out std_ulogic;
aud_dac_dat : in std_ulogic;
i2c_sdat : inout std_logic;
i2c_sclk : in std_logic
);
end component acodec_model;
begin
reset <= not(reset_n);
clk : process
begin
clock <= '1';
wait for SYSTEM_CYCLE_TIME/2;
clock <= '0';
wait for SYSTEM_CYCLE_TIME/2;
end process clk;
rst : process
begin
reset_n <= '0';
wait for 2*SYSTEM_CYCLE_TIME;
reset_n <= '1';
wait;
end process rst;
end_sim : process
variable tmp : line;
begin
end_simulation <= '0';
wait for SIMULATION_TIME;
end_simulation <= '1';
wait for 10*SYSTEM_CYCLE_TIME;
write(tmp, string'("Simulation finished: end time reached!"));
writeline(output, tmp);
stop;
wait;
end process end_sim;
iac_toplevel_inst : iac_toplevel
generic map (
SIMULATION => SIMULATION_MODE
)
port map (
clock_ext_50 => clock,
clock_ext2_50 => clock,
clock_ext3_50 => clock,
reset_n => reset_n,
hex0_n => hex0_n,
hex1_n => hex1_n,
hex2_n => hex2_n,
hex3_n => hex3_n,
hex4_n => hex4_n,
hex5_n => hex5_n,
hex6_n => hex6_n,
hex7_n => hex7_n,
gpio => gpio,
lcd_en => lcd_en,
lcd_rs => lcd_rs,
lcd_rw => lcd_rw,
lcd_on => lcd_on,
lcd_blon => lcd_blon,
lcd_dat => lcd_dat,
led_green => led_green,
led_red => led_red,
switch => switch,
key_n => key_n,
exb_adc_switch => exb_adc_switch,
exb_adc_en_n => exb_adc_en_n,
exb_dac_ldac_n => exb_dac_ldac_n,
exb_spi_clk => exb_spi_clk,
exb_spi_mosi => exb_spi_mosi,
exb_spi_miso => exb_spi_miso,
exb_spi_cs_adc_n => exb_spi_cs_adc_n,
exb_spi_cs_dac_n => exb_spi_cs_dac_n,
sram_ce_n => sram_ce_n,
sram_oe_n => sram_oe_n,
sram_we_n => sram_we_n,
sram_ub_n => sram_ub_n,
sram_lb_n => sram_lb_n,
sram_addr => sram_addr,
sram_dq => sram_dq,
uart_rts => uart_rts,
uart_cts => uart_cts,
uart_rxd => uart_rxd,
uart_txd => uart_txd,
aud_xclk => aud_xclk,
aud_bclk => aud_bclk,
aud_adc_lrck => aud_adc_lrck,
aud_adc_dat => aud_adc_dat,
aud_dac_lrck => aud_dac_lrck,
aud_dac_dat => aud_dac_dat,
i2c_sdat => i2c_sdat_pullup_wire,
i2c_sclk => i2c_sclk_pullup_wire,
irda_rxd => irda_rxd
);
key_n <= not(key);
io_model_inst : io_model
generic map (
FILE_NAME_SET => "io.txt")
port map (
gpio => gpio,
switch => switch,
key => key
);
seven_seg_gen : if CV_EN_SEVENSEG = 1 generate
seven_seg_model_inst : seven_seg_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME)
port map (
end_simulation => end_simulation,
hex0_n => hex0_n,
hex1_n => hex1_n,
hex2_n => hex2_n,
hex3_n => hex3_n,
hex4_n => hex4_n,
hex5_n => hex5_n,
hex6_n => hex6_n,
hex7_n => hex7_n
);
end generate seven_seg_gen;
exb_spi_miso <= 'H';
adc_dac_gen : if CV_EN_ADC_DAC = 1 generate
adc_model_inst : adc_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FULL_DEBUG => FULL_DEBUG,
FILE_NAME_PRELOAD => "adc_preload.txt")
port map (
end_simulation => end_simulation,
spi_clk => exb_spi_clk,
spi_miso => exb_spi_miso,
spi_cs_n => exb_spi_cs_adc_n,
swt_select => exb_adc_switch,
swt_enable_n => exb_adc_en_n
);
dac_model_inst : dac_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FILE_NAME_DUMP => "dac_dump.txt")
port map (
end_simulation => end_simulation,
spi_clk => exb_spi_clk,
spi_mosi => exb_spi_mosi,
spi_cs_n => exb_spi_cs_dac_n,
dac_ldac_n => exb_dac_ldac_n
);
end generate adc_dac_gen;
i2c_sdat_pullup_wire <= 'H';
i2c_sclk_pullup_wire <= 'H';
audio_gen : if CV_EN_AUDIO = 1 generate
acodec_inst : acodec_model
generic map (
SAMPLE_WIDTH => 16,
SAMPLE_RATE => 8*44100,
SAMPLE_FILE => "audio_samples.txt")
port map (
aud_xclk => aud_xclk,
aud_bclk => aud_bclk,
aud_adc_lrck => aud_adc_lrck,
aud_adc_dat => aud_adc_dat,
aud_dac_lrck => aud_dac_lrck,
aud_dac_dat => aud_dac_dat,
i2c_sdat => i2c_sdat_pullup_wire,
i2c_sclk => i2c_sclk_pullup_wire
);
end generate audio_gen;
infrared_gen : if CV_EN_IR = 1 generate
infrared_inst : infrared_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FILE_NAME_COMMAND => "ir_command.txt",
CUSTOM_CODE => x"6B86",
SIMULATION => SIMULATION_MODE
)
port map (
end_simulation => end_simulation,
irda_txd => irda_rxd
);
end generate infrared_gen;
lcd_gen : if CV_EN_LCD = 1 generate
lcd_model_inst : lcd_model
generic map(
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FULL_DEBUG => FULL_DEBUG
)
port map (
end_simulation => end_simulation,
disp_en => lcd_en,
disp_rs => lcd_rs,
disp_rw => lcd_rw,
disp_dat => lcd_dat
);
end generate lcd_gen;
sram_gen : if CV_EN_SRAM = 1 generate
sram_model_inst : sram_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FULL_DEBUG => FULL_DEBUG,
FILE_NAME_PRELOAD => "sram_preload.txt",
FILE_NAME_DUMP => "sram_dump.txt",
GV_SRAM_SIZE => 2**20
)
port map (
end_simulation => end_simulation,
sram_ce_n => sram_ce_n,
sram_oe_n => sram_oe_n,
sram_we_n => sram_we_n,
sram_ub_n => sram_ub_n,
sram_lb_n => sram_lb_n,
sram_addr => sram_addr,
sram_dq => sram_dq
);
end generate sram_gen;
uart_gen : if CV_EN_UART = 1 generate
uart_model_inst : uart_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FILE_NAME_COMMAND => "uart_command.txt",
FILE_NAME_DUMP => "uart_dump.txt",
BAUD_RATE => CV_UART_BAUDRATE,
SIMULATION => SIMULATION_MODE
)
port map (
end_simulation => end_simulation,
rx => uart_txd,
tx => uart_rxd
);
end generate uart_gen;
end sim;
| apache-2.0 | d7c5b74e93a61d7f3fc6e2408c097a60 | 0.583317 | 2.554626 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sim_1/counter_tb.vhd | 1 | 1,720 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_tb is
end counter_tb;
architecture Behavioral of counter_tb is
constant precision : integer := 13;
constant measureinterval : integer := 256; -- 8191;
constant inputbits : integer := precision + 5;
constant timerbits : integer := 18;
signal clk, clk2 : std_logic := '0';
constant clk_period : time := 10 ns;
-- constant clk2_period : time := 1.25 ns;
-- constant clk2_period : time := 2.272727 ms;
-- constant clk2_period : time := 27 ns;
-- constant clk2_period : time := 25 ns;
-- constant clk2_period : time := 24.985 ns;
-- constant clk2_period : time := 12.3107226 ns;
constant clk2_period : time := clk_period * 3.14159;
signal rst : std_logic;
signal tcount : unsigned(timerbits-1 downto 0);
signal icount : unsigned(inputbits-1 downto 0);
signal divstrobe : std_logic;
begin
-- Count the number of timer and input tics in the given
-- measurement interval, taking a whole number of input tics.
dut : entity work.counter
generic map (
Tlen => tcount'length,
Ilen => icount'length,
measureinterval => measureinterval )
port map (
timer => clk,
input => clk2,
tcount => tcount,
icount => icount,
-- overflow => open,
enable => '1',
strobe => divstrobe,
rst => rst);
clk <= not clk after clk_period/2;
clk2 <= not clk2 after clk2_period/2;
stim : process
begin
rst <= '1';
wait for 100 ns;
rst <= '0';
wait;
end process;
end Behavioral;
| mit | 694ee4a47b3f2570af28db8dc01b9073 | 0.581395 | 3.839286 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sources_1/fpdiv.vhd | 1 | 7,785 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Floating point divider
--
-- quotient * 2^scale = dividend / divisor
--
-- precision - number of bits in quotient
-- size - number of bits in dividiend and divisor
-- pscale - number of bits in scale
--
-- Scales divisor up until it is >= to dividend. Then loops,
-- scaling up dividend and subtracting divisor until precision
-- bits of quotient have been found. Detects overflows.
--
-- Output is valid on the clock edge after busy has gone low
--
-- Strobes are ignored while busy is high
entity fpdiv is
Generic ( size : integer;
precision : integer;
pscale : integer );
Port ( dividend : in UNSIGNED (size-1 downto 0);
divisor : in UNSIGNED (size-1 downto 0);
quotient : out UNSIGNED (precision-1 downto 0);
scale : out SIGNED (pscale-1 downto 0);
busy : out STD_LOGIC;
overflow : out STD_LOGIC;
strobe : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC );
end fpdiv;
architecture Behavioral of fpdiv is
type states is ( ST_WAIT, ST_PRESCALE, ST_DIV );
signal state, state_new : states;
signal dividend_int, dividend_new : unsigned (dividend'range);
signal divisor_int, divisor_new : unsigned (divisor'range);
signal quotient_int, quotient_new : unsigned (quotient'range);
signal scale_int, scale_new : signed (scale'range);
signal overflow_int, overflow_new : std_logic;
begin
-- scale <= scale_int;
-- quotient <= quotient_int;
sync : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
quotient_int <= (others => '0');
quotient <= (others => '0');
scale_int <= (others => '0');
scale <= (others => '0');
overflow_int <= '0';
overflow <= '0';
state <= ST_WAIT;
else
state <= state_new;
dividend_int <= dividend_new;
divisor_int <= divisor_new;
quotient_int <= quotient_new;
scale_int <= scale_new;
overflow_int <= overflow_new;
-- Only change outputs when entering or in WAIT
if state_new = ST_WAIT then
scale <= scale_new;
quotient <= quotient_new;
overflow <= overflow_new;
end if;
end if;
end if;
end process;
comb : process(state, strobe, dividend, dividend_int, divisor, divisor_int, quotient_int, scale_int, overflow_int)
variable dividend_next : unsigned (dividend'range);
variable divisor_next : unsigned (divisor'range);
variable quotient_next : unsigned (quotient'range);
variable scale_next : signed (scale'range);
variable overflow_next : std_logic;
variable nextd : unsigned (dividend'range);
variable nextq : unsigned (quotient'range);
begin
dividend_next := dividend_int;
divisor_next := divisor_int;
quotient_next := quotient_int;
scale_next := scale_int;
overflow_next := overflow_int;
busy <= '1';
state_new <= state;
case state is
when ST_WAIT =>
busy <= '0';
if strobe = '1' then
dividend_next := dividend;
divisor_next := divisor;
quotient_next := (others => '0');
scale_next := (others => '0');
overflow_next := '0';
state_new <= ST_PRESCALE;
end if;
-- Increases divisor until it is >= dividend
when ST_PRESCALE =>
if dividend_int = "0" then
quotient_next := (others => '0');
scale_next := (others => '0');
state_new <= ST_WAIT;
elsif dividend_int > divisor_int then
-- First check for overflow conditions
assert divisor_int(divisor_int'high) /= '1'
report "divisor overflow" severity warning;
if divisor_int(divisor_int'high) = '1' then
overflow_next := '1';
state_new <= ST_WAIT;
end if;
divisor_next := shift_left(divisor_int, 1);
-- check for scale overflow
assert scale_int(scale_int'high) /= '1'
report "Here be dragons" severity error;
scale_next := scale_int + "01";
assert scale_next(scale_int'high) /= '1'
report "scale overflow" severity warning;
if scale_next(scale_int'high) = '1' then
overflow_next := '1';
state_new <= ST_WAIT;
end if;
else
state_new <= ST_DIV;
end if;
-- Computes quotient by shifting dividend up and subtracting divisor
WHEN ST_DIV =>
-- When the quotient register is full, division is complete
if quotient_int(quotient_int'high) = '1' then
state_new <= ST_WAIT;
if dividend_int >= divisor_int then
dividend_next := dividend_int - divisor_int;
quotient_next(0) := '1';
end if;
else
assert dividend_int(dividend_int'high) /= '1'
report "Dividend overflow (next dividend will as well)" severity error;
if dividend_int(dividend_int'high) = '1' then
overflow_next := '1';
state_new <= ST_WAIT;
end if;
-- determine if subtraction must occur
if dividend_int < divisor_int then
nextd := dividend_int;
nextq := quotient_int;
else
nextd := dividend_int - divisor_int;
nextq := quotient_int + "1";
end if;
-- quotient can never overflow, due to the test above
-- nextd can never overflow, because divisor is always > (dividend / 2)
assert nextd(nextd'high) /= '1'
report "Here be dragons, next dividend should not be able to overflow" severity error;
assert nextq(nextq'high) /= '1'
report "Here be dragons, next quotient should not be able to overflow" severity error;
dividend_next := shift_left(nextd, 1);
quotient_next := shift_left(nextq, 1);
-- FIXME check for scale underflow
scale_next := scale_int - "01";
assert (scale_int(scale_int'high) /= '1' or scale_next(scale_next'high) = '1')
report "Scale underflow" severity warning;
if scale_int(scale_int'high) = '1' and scale_next(scale_next'high) = '0' then
overflow_next := '1';
state_new <= ST_WAIT;
end if;
end if;
when others =>
state_new <= ST_WAIT;
end case;
dividend_new <= dividend_next;
divisor_new <= divisor_next;
quotient_new <= quotient_next;
scale_new <= scale_next;
overflow_new <= overflow_next;
end process;
end Behavioral;
| mit | e613b9711ed8ea19bf8efbf08340865f | 0.496724 | 4.639452 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sources_1/spicomm.vhd | 1 | 4,364 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spicomm is
Generic (
divbits : integer;
divby : integer;
bitwidth : integer := 8 );
Port (
clk : in std_logic;
rst : in std_logic;
data : in std_logic_vector(bitwidth-1 downto 0);
strobe : in std_logic;
busy : out std_logic;
sck : out std_logic;
sdi : in std_logic;
sdo : out std_logic );
end spicomm;
architecture Behavioral of spicomm is
-- Clock-related signals
signal clkdiv, clkdiv_new : unsigned(divbits-1 downto 0);
signal bitcount, bitcount_new : unsigned(bitwidth-1 downto 0); -- FIXME should be log2(bitwidth)
-- Shifter-related signals
signal shifter, shifter_new : std_logic_vector(bitwidth-1 downto 0);
signal sdo_int, sdo_new : std_logic;
-- Controller-related signals
type states is (ST_WAIT, ST_SETUP, ST_SCKLO, ST_SCKHI, ST_DONE, ST_OUT);
signal state, state_new : states;
signal busy_int, busy_new : std_logic;
begin
busy <= busy_int;
sdo <= sdo_int;
comb : process(sdi, strobe, state, shifter, busy_int, sdo_int, clkdiv, bitcount, data)
variable state_next : states;
variable shifter_next : std_logic_vector(shifter'range);
variable busy_next : std_logic;
variable sdo_next : std_logic;
variable clkdiv_next : unsigned(clkdiv'range);
variable bitcount_next : unsigned(bitcount'range);
begin
state_next := state;
shifter_next := shifter;
busy_next := busy_int;
sdo_next := sdo_int;
clkdiv_next := clkdiv;
bitcount_next := bitcount;
-- data <= (others => 'Z');
sck <= '1';
case state is
when ST_WAIT =>
if strobe = '1' then
state_next := ST_SETUP;
shifter_next := data;
end if;
when ST_SETUP =>
busy_next := '1';
clkdiv_next := to_unsigned(0, clkdiv'length);
bitcount_next := to_unsigned(0, bitcount'length);
-- Shift out MSb
shifter_next := shifter(data'high-1 downto 0) & '0';
sdo_next := shifter(data'high);
state_next := ST_SCKLO;
when ST_SCKLO =>
sck <= '0';
clkdiv_next := clkdiv + "1";
if clkdiv = to_unsigned(divby/2-1, divbits) then
state_next := ST_SCKHI;
end if;
-- FIXME when is SDI shifted in? Falling edge?
when ST_SCKHI =>
sck <= '1';
clkdiv_next := clkdiv + "1";
if clkdiv = to_unsigned(divby-1, divbits) then
clkdiv_next := (others => '0');
-- Read bit in from sdi on falling edge of sck
shifter_next := shifter(data'high-1 downto 0) & sdi;
sdo_next := shifter(data'high);
bitcount_next := bitcount + "1";
if bitcount = to_unsigned(bitwidth-1, bitcount'length) then
state_next := ST_DONE;
else
state_next := ST_SCKLO;
end if;
end if;
when ST_DONE =>
busy_next := '0';
state_next := ST_OUT;
when ST_OUT =>
-- output is available on pins for one clock cycle, must be latched on the clock rising edge after busy falling edge
-- data <= shifter;
state_next := ST_WAIT;
when others =>
end case;
state_new <= state_next;
shifter_new <= shifter_next;
busy_new <= busy_next;
sdo_new <= sdo_next;
clkdiv_new <= clkdiv_next;
bitcount_new <= bitcount_next;
end process;
sync : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
state <= ST_WAIT;
else
state <= state_new;
shifter <= shifter_new;
busy_int <= busy_new;
sdo_int <= sdo_new;
clkdiv <= clkdiv_new;
bitcount <= bitcount_new;
end if;
end if;
end process;
end Behavioral;
| mit | d3835ebe36247c035526b503adb19c98 | 0.503437 | 4.007346 | false | false | false | false |
J-Rios/VHDL_Modules | 3.Peripherals/UART/UART_Rx.vhd | 1 | 2,375 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity UART_RX is
Generic
(
DBIT : integer := 8; -- # Data BITS
SB_TICK : integer := 16 -- # Stop BITS Tick (1 -> 16, 1.5 -> 24, 2 -> 32)
);
Port
(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
RX : in STD_LOGIC;
S_TICK : in STD_LOGIC;
RX_DONE_TICK : out STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (7 downto 0)
);
end UART_RX;
-------------------------------------------------------------------------
architecture Behavioral of UART_RX is
type state_type is (idle, start, data, stop);
signal state_reg, state_next: state_type;
signal s_reg, s_next: unsigned(3 downto 0);
signal n_reg, n_next: unsigned(2 downto 0);
signal b_reg, b_next: std_logic_vector(7 downto 0);
begin
-- FSMD state & data registers
process(CLK,RESET)
begin
if RESET='1' then
state_reg <= idle;
s_reg <= (others=>'0');
n_reg <= (others=>'0');
b_reg <= (others=>'0');
elsif (CLK'event and CLK='1') then
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end if;
end process;
-- Next-state logic & data path functional units/routing
process(state_reg,s_reg,n_reg,b_reg,S_TICK,RX)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
RX_DONE_TICK <='0';
case state_reg is
when idle =>
if RX='0' then
state_next <= start;
s_next <= (others=>'0');
end if;
when start =>
if (S_TICK = '1') then
if s_reg=7 then
state_next <= data;
s_next <= (others=>'0');
n_next <= (others=>'0');
else
s_next <= s_reg + 1;
end if;
end if;
when data =>
if (S_TICK = '1') then
if s_reg=15 then
s_next <= (others=>'0');
b_next <= RX & b_reg(7 downto 1);
if n_reg=(DBIT-1) then
state_next <= stop;
else
n_next <= n_reg + 1;
end if;
else
s_next <= s_reg + 1;
end if;
end if;
when stop =>
if (S_TICK = '1') then
RX_DONE_TICK <='1';
if s_reg=(SB_TICK-1) then
state_next <= idle;
else
s_next <= s_reg + 1;
end if;
end if;
end case;
end process;
DOUT <= b_reg;
end Behavioral;
| gpl-3.0 | ff002947461712596aa92ebb1d5f6826 | 0.497263 | 2.864897 | false | false | false | false |
maly/fpmi | FPGA/matrix.vhd | 1 | 911 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity matrix is
port(
--phys
clk: in std_logic;
rows: out std_logic_vector(4 downto 0);
cols: in std_logic_vector(4 downto 0);
--log
keys_n: out std_logic_vector(24 downto 0)
);
end entity;
architecture behav of matrix is
signal clkx: unsigned(4 downto 0):="11110";
begin
process (clk) is
variable div:integer:=0;
begin
if rising_edge(clk) then
div:=div+1;
if (div=10000) then
if clkx="11110" then keys_n(4 downto 0) <= cols; end if;
if clkx="11101" then keys_n(9 downto 5) <= cols; end if;
if clkx="11011" then keys_n(14 downto 10) <= cols; end if;
if clkx="10111" then keys_n(19 downto 15) <= cols; end if;
if clkx="01111" then keys_n(24 downto 20) <= cols; end if;
clkx<=clkx(3 downto 0) & clkx(4);
div:=0;
end if;
end if;
end process;
rows<=std_logic_vector(clkx);
end architecture;
| mit | 4b587af5c404d6e4a371f8bb439ee6e1 | 0.658617 | 2.820433 | false | false | false | false |
Fju/LeafySan | src/vhdl/testbench/uart_model.vhdl | 1 | 5,319 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : UART-Model for Simulation
-- Last update : 28.11.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity uart_model is
generic (
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
-- file with data to be send to fpga
FILE_NAME_COMMAND : string := "command.txt";
-- file for dump of data, received by pc
FILE_NAME_DUMP : string := "dump.txt";
-- communication speed for uart-link
BAUD_RATE : natural := 9600;
SIMULATION : boolean := true
);
port (
-- global signals
end_simulation : in std_ulogic;
-- uart-pins (pc side)
rx : in std_ulogic;
tx : out std_ulogic
);
end uart_model;
architecture sim of uart_model is
constant MAX_NO_OF_BYTES : natural := 128;
constant UART_BIT_TIME : time := 1 us * 1000000/BAUD_RATE;
file file_command : text open read_mode is FILE_NAME_COMMAND;
file file_dump : text open write_mode is FILE_NAME_DUMP;
type bytelist_t is array (0 to MAX_NO_OF_BYTES-1) of std_ulogic_vector(7 downto 0);
begin
-- send data to fpga
uart_send : process
variable commandlist : bytelist_t;
variable active_line : line;
variable neol : boolean := false;
variable data_value : integer;
variable cnt : natural := 0;
begin
-- set line to "no data"
tx <= '1';
-- preload list with undefined
commandlist := (others => (others => 'U'));
-- read preload file
while not endfile(file_command) loop
-- read line
readline(file_command, active_line);
-- loop until end of line
loop
read(active_line, data_value, neol);
exit when not neol;
-- write command to array
commandlist(cnt) := std_ulogic_vector(to_signed(data_value, 8));
-- increment counter
cnt := cnt + 1;
end loop;
end loop;
file_close(file_command);
-- send data to fpga
for i in 0 to MAX_NO_OF_BYTES-1 loop
-- check if byte is valid, else stop
if commandlist(i)(0) /= 'U' then
-- uart send procedure
-- wait some cycles before start
wait for 10*SYSTEM_CYCLE_TIME;
-- start bit
tx <= '0';
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
-- loop over data
for j in 0 to 7 loop
tx <= commandlist(i)(j);
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
end loop;
-- stop bit
tx <= '1';
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
write(active_line, string'("[UART] Sent "));
write(active_line, to_integer(unsigned(commandlist(i))));
write(active_line, string'(" ("));
write(active_line, to_bitvector(commandlist(i)));
write(active_line, string'(") to FPGA."));
writeline(output, active_line);
-- wait for some cycles before continuing
wait for 10*SYSTEM_CYCLE_TIME;
end if;
end loop;
-- wait forever
wait;
end process uart_send;
-- receive data from fpga
uart_receive : process
variable receivelist : bytelist_t;
variable cnt : integer;
variable active_line : line;
begin
-- initialize receive buffer
receivelist := (others => (others => 'U'));
cnt := 0;
-- always detect in the centre of a bit
if SIMULATION = false then wait for UART_BIT_TIME*0.5;
else wait for SYSTEM_CYCLE_TIME*16*0.5;
end if;
loop
-- stop when simulation is ended
exit when end_simulation = '1';
-- check if space in receive buffer is available, else break
exit when cnt = MAX_NO_OF_BYTES;
-- startbit detected
if rx = '0' then
--wait for first data bit
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
-- receive 8 bit
for i in 0 to 7 loop
receivelist(cnt)(i) := rx;
if SIMULATION = false then wait for UART_BIT_TIME;
else wait for SYSTEM_CYCLE_TIME*16;
end if;
end loop;
-- receive stop bit
if rx /= '1' then
-- stopbit not received!
write(active_line, string'("[UART] Expected Stop-Bit!"));
writeline(output, active_line);
else
write(active_line, string'("[UART] Received "));
write(active_line, to_integer(unsigned(receivelist(cnt))));
write(active_line, string'(" ("));
write(active_line, to_bitvector(receivelist(cnt)));
write(active_line, string'(") from FPGA."));
writeline(output, active_line);
end if;
-- inc counter
cnt := cnt + 1;
else
-- wait a cycle
wait for SYSTEM_CYCLE_TIME;
end if;
end loop;
-- loop over max number of bytes
for i in 0 to MAX_NO_OF_BYTES-1 loop
-- check if recieved byte is valid, else stop
if receivelist(i)(0) /= 'U' then
-- add value to line (will result in one value per line)
write(active_line, to_integer(unsigned(receivelist(i))));
-- write line to file
writeline(file_dump, active_line);
end if;
end loop;
file_close(file_dump);
-- wait forever
wait;
end process uart_receive;
end sim; | apache-2.0 | 48fffee616463d979c55b25ef7bc6f0b | 0.607821 | 3.257195 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue3/Keyboard/scanner.vhd | 1 | 1,563 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:14:44 07/06/2016
-- Design Name:
-- Module Name: scanner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity scanner is
Port ( clk : in STD_LOGIC;
rf : in STD_LOGIC;
kbdata : in STD_LOGIC;
reset : in STD_LOGIC;
ready : out STD_LOGIC;
scancode : out STD_LOGIC_VECTOR(7 downto 0));
end scanner;
architecture Behavioral of scanner is
signal dscan: STD_LOGIC_VECTOR(10 downto 0) := "11111111111";
begin
dscan_read: process(kbdata, clk, rf, dscan, reset)
begin
if reset = '1' then
dscan <= "11111111111";
elsif clk'event and clk = '1' then
if dscan(0) = '0' then
dscan <= "11111111111";
end if;
if rf = '1' then
dscan <= kbdata & dscan(10 downto 1);
end if;
end if;
end process dscan_read;
scancode <= dscan(8 downto 1);
ready <= not dscan(0);
end Behavioral;
| mit | a82e12e2c43b1a10acffd548c9a6ac89 | 0.577095 | 3.62645 | false | false | false | false |
Fju/LeafySan | src/modelsim/calc_lux_testbench.vhd | 1 | 2,621 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.standard.all;
use std.textio.all;
use std.env.all;
library work;
use work.iac_pkg.all;
entity calc_lux_testbench is
end calc_lux_testbench;
architecture sim of calc_lux_testbench is
constant SYSTEM_CYCLE_TIME : time := 20 ns; -- 50MHz
constant SIMULATION_TIME : time := 100000 * SYSTEM_CYCLE_TIME;
signal clock, reset_n, reset : std_ulogic;
signal calc_lux_start : std_ulogic;
signal calc_lux_busy : std_ulogic;
signal calc_lux_value : unsigned(15 downto 0);
signal calc_lux_channel0 : unsigned(15 downto 0);
signal calc_lux_channel1 : unsigned(15 downto 0);
type state_t is (S_START, S_WAIT_BUSY);
signal state, state_nxt : state_t;
signal myval, myval_nxt : unsigned(15 downto 0);
component calc_lux is
port(
clock : in std_ulogic;
reset : in std_ulogic;
channel0 : in unsigned(15 downto 0);
channel1 : in unsigned(15 downto 0);
start : in std_ulogic;
busy : out std_ulogic;
lux : out unsigned(15 downto 0)
);
end component calc_lux;
begin
calc_lux_inst : calc_lux
port map (
clock => clock,
reset => reset,
start => calc_lux_start,
busy => calc_lux_busy,
lux => calc_lux_value,
channel0 => calc_lux_channel0,
channel1 => calc_lux_channel1
);
reset <= not(reset_n);
clk : process
begin
clock <= '1';
wait for SYSTEM_CYCLE_TIME/2;
clock <= '0';
wait for SYSTEM_CYCLE_TIME/2;
end process clk;
rst : process
begin
reset_n <= '0';
wait for 2*SYSTEM_CYCLE_TIME;
reset_n <= '1';
wait;
end process rst;
seq : process(clock, reset)
begin
if reset = '1' then
state <= S_START;
myval <= to_unsigned(4000, myval'length);
elsif rising_edge(clock) then
myval <= myval_nxt;
state <= state_nxt;
end if;
end process seq;
comb : process(calc_lux_busy, myval, state)
begin
state_nxt <= state;
myval_nxt <= myval;
calc_lux_start <= '0';
calc_lux_channel0 <= (others => '0');
calc_lux_channel1 <= (others => '0');
case state is
when S_START =>
if myval = to_unsigned(7000, myval'length) then
myval_nxt <= to_unsigned(4000, myval'length);
else
myval_nxt <= myval + to_unsigned(50, myval'length);
end if;
calc_lux_start <= '1';
calc_lux_channel0 <= to_unsigned(6300, calc_lux_channel0'length);
calc_lux_channel1 <= myval;
state_nxt <= S_WAIT_BUSY;
when S_WAIT_BUSY =>
calc_lux_start <= '1';
if calc_lux_busy = '0' then
calc_lux_start <= '0';
state_nxt <= S_START;
end if;
end case;
end process comb;
end sim;
| apache-2.0 | 6aa15916680d10f39ea9f8d235b9591e | 0.639451 | 2.721703 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Utils/Add3.vhd | 1 | 1,335 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Add3.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Questo modulo serve al BinaryToBcd:
-- Se il valore binario dei BCD e' > 4, aggiunge 3 al valore.
-- **********************************************************
library ieee;
USE ieee.std_logic_1164.all;
entity Add3 is port (
signal s_i : in std_logic_vector(3 downto 0);
signal s_o : out std_logic_vector(3 downto 0)
);
end Add3;
architecture behaviour OF Add3 IS
begin
process (s_i)
begin
case s_i is
when B"0000" => s_o <= B"0000";
when B"0001" => s_o <= B"0001";
when B"0010" => s_o <= B"0010";
when B"0011" => s_o <= B"0011";
when B"0100" => s_o <= B"0100";
when B"0101" => s_o <= B"1000";
when B"0110" => s_o <= B"1001";
when B"0111" => s_o <= B"1010";
when B"1000" => s_o <= B"1011";
when B"1001" => s_o <= B"1100";
when others => s_o <= B"0000";
end case;
end process;
end behaviour; | mit | 94fd82db03f586b39fe4fc72c8d9e9b9 | 0.413483 | 3.304455 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_seven_seg_test.vhdl | 1 | 8,668 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Jan Dürre
-- Year : 2013
-- Description : This example tests every 7-seg-display by using
-- address a counter to generate every possible
-- output. For the 4 hex-displays the counter runs
-- from 0 to 15, for the dec-displays the counter
-- runs from -1000 to 1000.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- speed
constant SPEED_RATE : natural := CV_SYS_CLOCK_RATE/16;
-- state register
type state_t is (HEX_TEST, DEC_TEST, DO_NOTHING);
signal state, state_nxt : state_t;
-- counter register for every possible dec-value
signal cnt, cnt_nxt : signed(to_log2(2001)-1 downto 0); -- -1000..0..1000
-- counter for enable signal (SYS_CLOCK/16)
signal cnt_enable, cnt_enable_nxt : unsigned(to_log2(SPEED_RATE)-1 downto 0);
-- enable signal, generated by cnt_enable
signal enable : std_ulogic;
-- mask for hex displays
signal hex_mask, hex_mask_nxt : std_ulogic_vector(3 downto 0);
begin
-- sequential process
process (clock, reset)
begin
-- async reset
if reset = '1' then
state <= HEX_TEST;
cnt <= (others => '0');
cnt_enable <= (others => '0');
hex_mask <= "0001";
elsif rising_edge(clock) then
state <= state_nxt;
cnt <= cnt_nxt;
cnt_enable <= cnt_enable_nxt;
hex_mask <= hex_mask_nxt;
end if;
end process;
-- logic for enable generator
process (cnt_enable)
begin
if cnt_enable >= to_unsigned(SPEED_RATE, cnt_enable'length) then
cnt_enable_nxt <= (others => '0');
enable <= '1';
else
cnt_enable_nxt <= cnt_enable + to_unsigned(1, cnt_enable'length);
enable <= '0';
end if;
end process;
-- logic
process (state, cnt, enable, hex_mask)
begin
-- standard assignments
-- hold values of registers
state_nxt <= state;
cnt_nxt <= cnt;
hex_mask_nxt <= hex_mask;
-- set bus signals to standard values (not in use)
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
-- turn of leds
led_green <= (others => '0');
led_red <= (others => '0');
-- state machine
case state is
-- starting state
when HEX_TEST =>
-- indicate state HEX_TEST
led_green(0) <= '1';
-- for every possible hex-value
if cnt <= to_signed(15, cnt'length) then
-- wait for enable signal
if enable = '1' then
-- set chip select for seven-segment-interface
sevenseg_cs <= '1';
-- set write mode
sevenseg_wr <= '1';
-- set address, use mask to select hex-display, LSB has to be zero for hexmode
sevenseg_addr <= std_ulogic_vector(resize(unsigned(hex_mask & '0'), sevenseg_addr'length));
-- set data (4 times cnt-value)
sevenseg_dout <= std_ulogic_vector(resize(unsigned(cnt(3 downto 0) & cnt(3 downto 0) & cnt(3 downto 0) & cnt(3 downto 0)), sevenseg_dout'length));
-- inc counter
cnt_nxt <= cnt + to_signed(1, cnt'length);
end if;
else
-- last mask not reached
if hex_mask(3) = '0' then
-- shift mask
hex_mask_nxt <= std_ulogic_vector(shift_left(unsigned(hex_mask), 1));
-- reset counter
cnt_nxt <= (others => '0');
else
-- next state
state_nxt <= DEC_TEST;
-- reset counter
cnt_nxt <= to_signed(-1000, cnt'length);
end if;
end if;
-- test every value from -1000 to 1000 (-1000 and 1000 should produce error on display)
when DEC_TEST =>
-- indicate state DEC_TEST
led_green(1) <= '1';
-- wait for enable signal
if enable = '1' then
-- set chip select for seven-segment-interface
sevenseg_cs <= '1';
-- set write mode
sevenseg_wr <= '1';
-- set address
sevenseg_addr <= CV_ADDR_SEVENSEG_DEC;
-- set data
sevenseg_dout <= std_ulogic_vector(resize(cnt, sevenseg_dout'length));
-- end cnt reached
if cnt = to_signed(1000, cnt'length) then
-- end test
state_nxt <= DO_NOTHING;
else
-- inc counter
cnt_nxt <= signed(cnt) + to_signed(1, cnt'length);
end if;
end if;
-- wait forever
when DO_NOTHING =>
-- indicate state DO_NOTHING
led_green(2) <= '1';
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 | 0b6ae4e5d46579bfc40a3834a8c50fd8 | 0.560106 | 2.865455 | false | false | false | false |
J-Rios/VHDL_Modules | 1.Combinational/2sComplement.vhd | 1 | 1,027 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity a2sComplement is
Generic
(
BITS : INTEGER := 4
);
Port
(
CI : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (BITS-1 downto 0);
Z : out STD_LOGIC_VECTOR (BITS-1 downto 0);
CO : out STD_LOGIC
);
end a2sComplement;
-------------------------------------------------------------------------
architecture Behavioral of a2sComplement is
signal Sum : UNSIGNED (BITS downto 0) := (others => '0');
signal A_unsig, B_unsig : UNSIGNED (BITS downto 0);
signal a1sCompl : STD_LOGIC_VECTOR (BITS-1 downto 0);
signal B : STD_LOGIC_VECTOR (BITS-1 downto 0) := (others => '0');
begin
a1sCompl <= not(A);
B(0) <= '1';
A_unsig <= unsigned('0' & a1sCompl);
B_unsig <= unsigned('0' & B);
Sum <= A_unsig + B_unsig + ('0' & CI);
Z <= std_logic_vector(Sum(BITS-1 downto 0));
CO <= Sum(BITS);
end Behavioral;
| gpl-3.0 | 71affc23f63b2d0f634b34c6798d95d8 | 0.503408 | 3.41196 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_uart_test_trigger.vhdl | 1 | 7,306 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Jan Dürre
-- Year : 2013
-- Description : This example waits for a specific trigger word to
-- receive over UART. After the trigger-command is
-- detected some predefined datawords are send to
-- the PC.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- number of words to send after start command
constant CV_NO_DATA : natural := 5;
-- state register
type state_t is (WAIT_FOR_COMMAND, SEND_DATA);
signal state, state_nxt : state_t;
-- counter register
signal cnt, cnt_nxt : unsigned(to_log2(CV_NO_DATA)-1 downto 0);
-- start-command
constant CV_START_COMMAND : std_ulogic_vector(7 downto 0) := "00000011";
-- data to be send after command
type data_t is array (0 to CV_NO_DATA-1) of std_ulogic_vector(7 downto 0);
constant data : data_t := ("10101010", "01010101", "11110000", "00001111", "11001100");
begin
-- sequential process
process (clock, reset)
begin
-- async reset
if reset = '1' then
state <= WAIT_FOR_COMMAND;
cnt <= (others => '0');
elsif rising_edge(clock) then
state <= state_nxt;
cnt <= cnt_nxt;
end if;
end process;
-- logic
process (state, cnt, uart_irq_rx, uart_irq_tx, uart_din)
begin
-- standard assignments
-- hold values of registers
state_nxt <= state;
cnt_nxt <= cnt;
-- set bus signals to standard values (not in use)
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
-- turn of leds
led_green <= (others => '0');
led_red <= (others => '0');
-- state machine
case state is
-- wait for interrupt from UART
when WAIT_FOR_COMMAND =>
-- indicate state WAIT_FOR_COMMAND
led_green(0) <= '1';
-- data is ready in receive-register
if uart_irq_rx = '1' then
-- select uart-interface
uart_cs <= '1';
-- address of send/receive-register
uart_addr <= CV_ADDR_UART_DATA_RX;
-- read-mode
uart_wr <= '0';
-- check if received data is = start-command
if uart_din(7 downto 0) = CV_START_COMMAND then
-- next state
state_nxt <= SEND_DATA;
-- reset counter
cnt_nxt <= (others => '0');
end if;
end if;
-- send data from data-array
when SEND_DATA =>
-- indicate state SEND_DATA
led_green(1) <= '1';
-- check if send-register is empty
if uart_irq_tx = '1' then
-- select uart-interface
uart_cs <= '1';
-- address of send/receive-register
uart_addr <= CV_ADDR_UART_DATA_TX;
-- write-mode
uart_wr <= '1';
-- select data from array
uart_dout(7 downto 0) <= data(to_integer(cnt));
-- IS NOT last word
if cnt /= to_unsigned(CV_NO_DATA-1, cnt'length) then
-- inc counter
cnt_nxt <= cnt + to_unsigned(1, cnt'length);
-- IS last word
else
-- next state
state_nxt <= WAIT_FOR_COMMAND;
end if;
end if;
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
end rtl; | apache-2.0 | 27dc12ccf4e06004a80a24e5de59ca87 | 0.559206 | 2.789233 | false | false | false | false |
Fju/LeafySan | src/vhdl/testbench/seven_seg_model.vhdl | 1 | 5,176 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : 7-Segment-Display Model
-- Last update : 04.12.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.standard.all;
use std.textio.all;
entity seven_seg_model is
generic (
SYSTEM_CYCLE_TIME : time := 20 ns -- 50 MHz
);
port (
-- global signals
end_simulation : in std_ulogic;
-- 7-seg connections
hex0_n : in std_ulogic_vector(6 downto 0);
hex1_n : in std_ulogic_vector(6 downto 0);
hex2_n : in std_ulogic_vector(6 downto 0);
hex3_n : in std_ulogic_vector(6 downto 0);
hex4_n : in std_ulogic_vector(6 downto 0);
hex5_n : in std_ulogic_vector(6 downto 0);
hex6_n : in std_ulogic_vector(6 downto 0);
hex7_n : in std_ulogic_vector(6 downto 0)
);
end seven_seg_model;
architecture sim of seven_seg_model is
-- model can only be used with the iac-seven_seg-interface, only 0,1,2,3,4,5,6,7,8,9,0,A,b,C,d,E,F, ,-,X are possible values
-- convert 7-seg to character
function seg_to_char(segments : std_ulogic_vector(6 downto 0)) return character is
variable tmp : character;
begin
-- decode 7-segment (inverted!)
case segments is
when "1000000" => tmp := '0'; -- 0
when "1111001" => tmp := '1'; -- 1
when "0100100" => tmp := '2'; -- 2
when "0110000" => tmp := '3'; -- 3
when "0011001" => tmp := '4'; -- 4
when "0010010" => tmp := '5'; -- 5
when "0000010" => tmp := '6'; -- 6
when "1111000" => tmp := '7'; -- 7
when "0000000" => tmp := '8'; -- 8
when "0010000" => tmp := '9'; -- 9
when "0001000" => tmp := 'A'; -- A
when "0000011" => tmp := 'b'; -- b
when "1000110" => tmp := 'C'; -- C
when "0100001" => tmp := 'd'; -- d
when "0000110" => tmp := 'E'; -- E
when "0001110" => tmp := 'F'; -- F
when "1111111" => tmp := ' '; -- off
when "0111111" => tmp := '-'; -- - (minus)
when others => tmp := 'X'; -- unexpected value: X
end case;
return tmp;
end function seg_to_char;
begin
process
-- line for textio
variable active_line : line;
-- internal vars for display-content, initialize empty
variable seg0 : character := ' ';
variable seg1 : character := ' ';
variable seg2 : character := ' ';
variable seg3 : character := ' ';
variable seg4 : character := ' ';
variable seg5 : character := ' ';
variable seg6 : character := ' ';
variable seg7 : character := ' ';
variable display_changed : boolean := false;
begin
loop
-- stop when simulation has ended
exit when end_simulation = '1';
-- check if display should change (any display not turned off, and value differs from active display)
--if (hex0_n /= "1111111") and (seg0 /= seg_to_char(hex0_n)) and hex0_n /= "UUUUUUU" then
if (seg0 /= seg_to_char(hex0_n)) and hex0_n /= "UUUUUUU" then
seg0 := seg_to_char(hex0_n);
display_changed := true;
end if;
if (seg1 /= seg_to_char(hex1_n)) and hex1_n /= "UUUUUUU" then
seg1 := seg_to_char(hex1_n);
display_changed := true;
end if;
if (seg2 /= seg_to_char(hex2_n)) and hex2_n /= "UUUUUUU" then
seg2 := seg_to_char(hex2_n);
display_changed := true;
end if;
if (seg3 /= seg_to_char(hex3_n)) and hex3_n /= "UUUUUUU" then
seg3 := seg_to_char(hex3_n);
display_changed := true;
end if;
if (seg4 /= seg_to_char(hex4_n)) and hex4_n /= "UUUUUUU" then
seg4 := seg_to_char(hex4_n);
display_changed := true;
end if;
if (seg5 /= seg_to_char(hex5_n)) and hex5_n /= "UUUUUUU" then
seg5 := seg_to_char(hex5_n);
display_changed := true;
end if;
if (seg6 /= seg_to_char(hex6_n)) and hex6_n /= "UUUUUUU" then
seg6 := seg_to_char(hex6_n);
display_changed := true;
end if;
if (seg7 /= seg_to_char(hex7_n)) and hex7_n /= "UUUUUUU" then
seg7 := seg_to_char(hex7_n);
display_changed := true;
end if;
-- display change -> printout
if display_changed = true then
-- generate printout
write(active_line, string'("[7-SEG] ["));
write(active_line, seg7);
write(active_line, string'("]["));
write(active_line, seg6);
write(active_line, string'("] ["));
write(active_line, seg5);
write(active_line, string'("]["));
write(active_line, seg4);
write(active_line, string'("] ["));
write(active_line, seg3);
write(active_line, string'("]["));
write(active_line, seg2);
write(active_line, string'("]["));
write(active_line, seg1);
write(active_line, string'("]["));
write(active_line, seg0);
write(active_line, string'("]"));
writeline(output, active_line);
-- reset display_changed
display_changed := false;
end if;
-- wait for one cycle
wait for SYSTEM_CYCLE_TIME;
end loop;
-- wait forever
wait;
end process;
end sim;
| apache-2.0 | ffa6740ed28e78162214c57de280adfc | 0.544822 | 2.890006 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue4/video/kb_scanner.vhd | 2 | 1,525 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:14:44 07/06/2016
-- Design Name:
-- Module Name: kb_scanner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kb_scanner is port (
clk : in STD_LOGIC;
kbdata : in STD_LOGIC;
reset : in STD_LOGIC;
rf : in STD_LOGIC;
ready : out STD_LOGIC;
scancode : out STD_LOGIC_VECTOR(7 downto 0));
end kb_scanner;
architecture Behavioral of kb_scanner is
signal dscan: STD_LOGIC_VECTOR(10 downto 0) := "11111111111";
begin
dscan_read: process(kbdata, clk, rf, dscan, reset)
begin
if reset = '1' then
dscan <= "11111111111";
elsif clk'event and clk = '1' then
if dscan(0) = '0' then
dscan <= "11111111111";
end if;
if rf = '1' then
dscan <= kbdata & dscan(10 downto 1);
end if;
end if;
end process dscan_read;
scancode <= dscan(8 downto 1);
ready <= not dscan(0);
end Behavioral;
| mit | 0cba8ecf72ab4404152497d7204ff7e7 | 0.596721 | 3.300866 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/demux/myDemux2_tb.vhdl | 1 | 1,440 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myDemux2_tb is
end myDemux2_tb;
architecture behavioral of myDemux2_tb is
component myDemux2
port(a: in std_logic; sel: in std_logic; s: out std_logic; s2: out std_logic);
end component;
-- signals used for testing
signal s1: std_logic;
signal sel: std_logic;
signal o1: std_logic;
signal o2: std_logic;
begin
-- component instantiation
myDemux2_1: myDemux2 port map(a => s1, sel => sel, s => o1, s2 => o2);
process
begin
s1 <= '0';
sel <= '0';
wait for 1 ns;
assert o1 = '0' report "o1 of 0,0 was not 0" severity error;
assert o2 = '0' report "o2 of 0,0 was not 0" severity error;
s1 <= '0';
sel <= '1';
wait for 1 ns;
assert o1 = '0' report "o1 of 0,0 was not 0" severity error;
assert o2 = '0' report "o2 of 0,0 was not 0" severity error;
s1 <= '1';
sel <= '0';
wait for 1 ns;
assert o1 = '1' report "o1 of 1,0 was not 1" severity error;
assert o2 = '0' report "o2 of 1,0 was not 0" severity error;
s1 <= '1';
sel <= '1';
wait for 1 ns;
assert o1 = '0' report "o1 of 1,1 was not 0" severity error;
assert o2 = '1' report "o2 of 1,1 was not 1" severity error;
assert false report "test complete" severity note;
wait;
end process;
end behavioral;
| mit | 3d0be62ed364cf97fde1aba668204bd7 | 0.563194 | 3.185841 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_adc_dac_test.vhdl | 1 | 7,739 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Christian Leibold
-- Year : 2013
-- Description : This example reads the adc-value from channel 2
-- and displays the result on red LEDs 0 to 11.
-- Afterwards the binary value set by switches
-- 0 to 7 is send to DAC channel 1.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register
type state_t is (S_INIT, S_ADC_READ, S_DAC_SET, S_WAIT);
signal state, state_nxt : state_t;
-- register to save a value from the ADC and show it on the first twelve red LEDs
signal led_out, led_out_nxt : std_ulogic_vector(11 downto 0);
-- register for a wait counter (counts from 0 to 1000)
signal count , count_nxt : unsigned(9 downto 0);
begin
-- sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
led_out <= (others => '0');
count <= (others => '0');
state <= S_INIT;
elsif rising_edge(clock) then
led_out <= led_out_nxt;
count <= count_nxt;
state <= state_nxt;
end if;
end process;
-- combinational process contains logic only
process(state, key, count, led_out, adc_dac_din, switch)
begin
-- default assignments
-- set default values for the internal bus -> zero on all signals means, nothing will happen
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
-- hold previous values of all registers
led_out_nxt <= led_out;
count_nxt <= count;
state_nxt <= state;
case state is
-- Initial start state
when S_INIT =>
-- Wait for a press on KEY0 to start the function
if key(0) = '1' then
-- activate ADC channel 2 and DAC channel 1
adc_dac_cs <= '1';
adc_dac_wr <= '1';
adc_dac_addr <= CV_ADDR_ADC_DAC_CTRL;
adc_dac_dout(9 downto 0) <= "1000000100";
-- next state
state_nxt <= S_ADC_READ;
end if;
-- Read value from ADC and save it into the led_out-register
when S_ADC_READ =>
-- Enable the Chip-Select signal for the ADC/DAC-Module
adc_dac_cs <= '1';
-- Set read-address for the value of ADC-Channel 2
adc_dac_addr <= CV_ADDR_ADC2;
-- Set the value of the selected ADC-Channel as next value for the led_out-register
led_out_nxt <= adc_dac_din(11 downto 0);
-- next state
state_nxt <= S_DAC_SET;
-- Set a constant a value to a DAC-Channel in this state
when S_DAC_SET =>
-- Set the write to one to write a value into a register
adc_dac_wr <= '1';
-- Enable the Chip-Select signal for the ADC/DAC-Module
adc_dac_cs <= '1';
-- Set read-address for the value of DAC-Channel 1
adc_dac_addr <= CV_ADDR_DAC1;
-- Set the value which should be written into the selected register the in the selected module
adc_dac_dout(7 downto 0) <= switch(7 downto 0);
-- next state
state_nxt <= S_WAIT;
when S_WAIT =>
-- increment counter by 1 every clock cycle
count_nxt <= count + to_unsigned(1, count'length);
-- compare actual counter value with immediate 1000s
if count = to_unsigned(1000, count'length) then
-- reset the counter to zero
count_nxt <= (others => '0');
-- next state
state_nxt <= S_ADC_READ;
end if;
end case;
end process;
-- Default assignment for all unused red LEDs
led_red(17 downto 12) <= (others => '0');
-- Connect the output of the led_out-register to the first twelve red LEDs directly
-- If the value of the led_out-register, the LEDs will change immediately at the same time
led_red(11 downto 0) <= led_out;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
led_green <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 | 2a6af078628413568690c612d7faea61 | 0.594004 | 2.780812 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue4/video/segment_out.vhd | 1 | 3,737 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:45:03 07/06/2016
-- Design Name:
-- Module Name: segment_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity segment_out is port (
clk : in STD_LOGIC;
ready : in STD_LOGIC;
reset : in STD_LOGIC;
scancode : in STD_LOGIC_VECTOR(7 downto 0);
segments : out STD_LOGIC_VECTOR(14 downto 0);
anyKeyDown : out STD_LOGIC);
end segment_out;
architecture Behavioral of segment_out is
component seg_scancode_to_segments is port (
scancode : in STD_LOGIC_VECTOR(7 downto 0);
segment_repr : out STD_LOGIC_VECTOR(6 downto 0));
end component;
signal isE0, isF0, stw_q: STD_LOGIC;
signal segment_repr : STD_LOGIC_VECTOR(6 downto 0);
signal clock_divide_counter : Integer range 0 to 100000;
signal current_digit : Integer range 0 to 7;
signal digit0 : STD_LOGIC_VECTOR (6 downto 0);
signal digit1 : STD_LOGIC_VECTOR (6 downto 0);
signal digit2 : STD_LOGIC_VECTOR (6 downto 0);
signal digit3 : STD_LOGIC_VECTOR (6 downto 0);
signal digit4 : STD_LOGIC_VECTOR (6 downto 0);
signal digit5 : STD_LOGIC_VECTOR (6 downto 0);
signal digit6 : STD_LOGIC_VECTOR (6 downto 0);
signal digit7 : STD_LOGIC_VECTOR (6 downto 0);
begin
seg_scancode_to_segments0: seg_scancode_to_segments port map (scancode, segment_repr);
ef0_detector : process(scancode)
begin
if(scancode = "11100000") then
isE0 <= '1';
else
isE0 <= '0';
end if;
if(scancode = "11110000") then
isF0 <= '1';
else
isF0 <= '0';
end if;
end process ef0_detector;
stw : process (isE0, isF0, ready, clk)
begin
if clk'event and clk = '1' and ready = '1' then
if stw_q = '0' then
if isE0 = '0' AND isF0 = '0' then
digit7 <= digit6;
digit6 <= digit5;
digit5 <= digit4;
digit4 <= digit3;
digit3 <= digit2;
digit2 <= digit1;
digit1 <= digit0;
digit0 <= segment_repr;
anyKeyDown <= '1';
elsif isE0 = '0' AND isF0 = '1' then
stw_q <= '1';
anyKeyDown <= '0';
end if;
else
stw_q <= '0';
end if;
end if;
end process stw;
digit_select_clock_divider : process(clk)
begin
if clk'event and clk = '1' then
if clock_divide_counter >= 99999 then
clock_divide_counter <= 0;
current_digit <= current_digit + 1; -- overflows automatically with mod 8
else
clock_divide_counter <= clock_divide_counter + 1;
end if;
end if;
end process digit_select_clock_divider;
digit_time_multiplex : process (current_digit)
begin
if current_digit = 0 then
segments <= "11111110" & digit0;
elsif current_digit = 1 then
segments <= "11111101" & digit1;
elsif current_digit = 2 then
segments <= "11111011" & digit2;
elsif current_digit = 3 then
segments <= "11110111" & digit3;
elsif current_digit = 4 then
segments <= "11101111" & digit4;
elsif current_digit = 5 then
segments <= "11011111" & digit5;
elsif current_digit = 6 then
segments <= "10111111" & digit6;
else
segments <= "01111111" & digit7;
end if;
end process digit_time_multiplex;
end Behavioral;
| mit | 4e1d224acff18021848644359477e0c7 | 0.628847 | 3.121972 | false | false | false | false |
J-Rios/VHDL_Modules | 3.Peripherals/7Segment_4Digit_Module/Display7S_4Digits.vhd | 1 | 3,472 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity DISP7S_4 is
Generic
(
N : NATURAL := 20 -- 100MHz -> (2^N)/f = T*(2^N) = 10ns * (2^20) = 10ms | (1ms - 16ms)
);
Port
(
C : in STD_LOGIC; -- Clock source
DD : in STD_LOGIC_VECTOR (15 downto 0); -- Digit value
CAT : out STD_LOGIC_VECTOR (7 downto 0); -- Digit catode
AN : out STD_LOGIC_VECTOR (3 downto 0) -- Set digit (AN(3) Left ... AN(0) Right)
);
end DISP7S_4;
-------------------------------------------------------------------------
architecture Behavioral of DISP7S_4 is
signal Hin0, Hin1, Hin2, Hin3 : STD_LOGIC_VECTOR (3 downto 0);
signal q_reg, q_next : UNSIGNED (N-1 downto 0);
signal Count : STD_LOGIC_VECTOR (N-1 downto 0);
signal Sel : STD_LOGIC_VECTOR (1 downto 0);
signal Hex : STD_LOGIC_VECTOR (3 downto 0);
signal Sseg : STD_LOGIC_VECTOR (6 downto 0);
signal Dot : STD_LOGIC;
begin
------------------------------------------------------------------------------
Hin0 <= DD(3 downto 0);
Hin1 <= DD(7 downto 4);
Hin2 <= DD(11 downto 8);
Hin3 <= DD(15 downto 12);
------------------------------------------------------------------------------
-- Free-running Counter
process
begin
wait until rising_edge(C);
q_reg <= q_next; -- Establece la cuenta
end process;
-- Next state logic
q_next <= q_reg + 1;
-- Output logic
Count <= std_logic_vector(q_reg);
Sel <= Count(N-1 downto N-2);
------------------------------------------------------------------------------
-- 2 to 4 Decoder
AN <= "1110" when Sel = "00" else
"1101" when Sel = "01" else
"1011" when Sel = "10" else
"0111" when Sel = "11";
------------------------------------------------------------------------------
-- 4 to 1 Multiplexor
with Sel select Hex <=
Hin0 when "00", -- Boton T18
Hin1 when "01", -- Boton T17
Hin2 when "10", -- Boton U17
Hin3 when "11", -- Boton W19
Hin0 when others;
------------------------------------------------------------------------------
-- BCD to 7-SEG Converter
process(Hex)
begin
case Hex is
when "0000" => SSEG <= "1000000"; -- 0
when "0001" => SSEG <= "1111001"; -- 1
when "0010" => SSEG <= "0100100"; -- 2
when "0011" => SSEG <= "0110000"; -- 3
when "0100" => SSEG <= "0011001"; -- 4
when "0101" => SSEG <= "0010010"; -- 5
when "0110" => SSEG <= "0000010"; -- 6
when "0111" => SSEG <= "1111000"; -- 7
when "1000" => SSEG <= "0000000"; -- 8
when "1001" => SSEG <= "0010000"; -- 9
when "1010" => SSEG <= "0001000"; -- A
when "1011" => SSEG <= "0000011"; -- b
when "1100" => SSEG <= "1000110"; -- C
when "1101" => SSEG <= "0100001"; -- d
when "1110" => SSEG <= "0000110"; -- E
when "1111" => SSEG <= "0001110"; -- F
when others => SSEG <= "1111111"; -- Need for simulation
end case;
end process;
Dot <= '1';
CAT(7 downto 0) <= Dot & Sseg(6 downto 0);
------------------------------------------------------------------------------
end Behavioral;
| gpl-3.0 | d8152f11e2920d408153447ff8033f3a | 0.406394 | 4.056075 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_lcd_test_printout_text.vhdl | 1 | 6,784 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Christian Leibold
-- Year : 2013
-- Description : This example sends a predefined text to the LCD
-- display.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register
type state_t is (S_WAIT_KEY, S_PRINT_TO_LCD, S_FINISH);
signal state, state_nxt : state_t;
-- Define a constant array with the hex-codes of every single character to print them on the LC-Display
constant lcd_commands : lcd_commands_t(0 to 24) := lcd_cmd( asciitext(" Invent A Chip! ") & lcd_cursor_pos(1,4) & asciitext("IMS 2015") );
-- Define a counter to count the printed characters
signal count, count_nxt : unsigned(4 downto 0);
begin
-- Sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
count <= (others => '0');
state <= S_WAIT_KEY;
elsif rising_edge(clock) then
count <= count_nxt;
state <= state_nxt;
end if;
end process;
-- Combinational process contains logic only
process(state, lcd_irq_rdy, key, count)
begin
-- Default assignment for the green LEDs (not used in this example)
led_green <= (others => '0');
-- Default assignment for all red LEDs (not used in this example)
led_red <= (others => '0');
-- Set default values for the internal bus -> zero on all signals means, nothing will happen
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
-- Hold previous values of all registers
count_nxt <= count;
state_nxt <= state;
case state is
-- Wait until KEY0 is triggered
when S_WAIT_KEY =>
led_green(0) <= '1';
if key(0) = '1' then
state_nxt <= S_PRINT_TO_LCD;
end if;
-- Read value from ADC and save it into the led_out-register
when S_PRINT_TO_LCD =>
led_green(1) <= '1';
if lcd_irq_rdy = '1' then
-- Enable the Chip-Select signal for the LCD-Module
lcd_cs <= '1';
-- Enable the Write-Select signal
lcd_wr <= '1';
-- Take the new data from character array, the position is given by the character counter
lcd_dout(7 downto 0) <= lcd_commands(to_integer(count));
-- Set address of the LCD interface to print a character
lcd_addr <= CV_ADDR_LCD_DATA;
-- Increment the counter to count the printed characters
count_nxt <= count + to_unsigned(1, count'length);
-- The next state depends on the counter or on how many characters got already printed
if count = to_unsigned(lcd_commands'length-1, count'length) then
state_nxt <= S_FINISH;
end if;
end if;
-- Endless loop -> never leave this state
when S_FINISH =>
led_green(2) <= '1';
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 | 13096a61ca3ae992bc7fdd19b24df7d9 | 0.596256 | 2.745447 | false | false | false | false |
Fju/LeafySan | src/vhdl/interfaces/lcd.vhdl | 1 | 12,782 | -----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : LC-Display
-- Author : Christian Leibold / Jan Dürre
-- Last update : 29.04.2015
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity lcd is
generic(
SIMULATION : boolean := false
);
port(
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus signals
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
iobus_irq_rdy : out std_ulogic;
iobus_ack_rdy : in std_ulogic;
-- display signals
disp_en : out std_ulogic;
disp_rs : out std_ulogic;
disp_rw : out std_ulogic;
disp_dat : out std_ulogic_vector(7 downto 0);
disp_pwr : out std_ulogic;
disp_blon : out std_ulogic
);
end lcd;
architecture rtl of lcd is
-- buffer for incoming lcd-commands
component fifo is
generic (
DEPTH : natural;
WORDWIDTH : natural
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
write_en : in std_ulogic;
data_in : in std_ulogic_vector(WORDWIDTH-1 downto 0);
read_en : in std_ulogic;
data_out : out std_ulogic_vector(WORDWIDTH-1 downto 0);
empty : out std_ulogic;
full : out std_ulogic;
fill_cnt : out unsigned(to_log2(DEPTH+1)-1 downto 0)
);
end component fifo;
signal buf_write_en : std_ulogic;
signal buf_data_in : std_ulogic_vector(7 downto 0);
signal buf_read_en : std_ulogic;
signal buf_data_out : std_ulogic_vector(7 downto 0);
signal buf_empty : std_ulogic;
signal buf_full : std_ulogic;
type state_t IS (S_POWER_UP, S_INIT, S_READY, S_SEND, S_CURSOR_DATA, S_CURSOR_SET);
signal state, state_nxt : state_t;
signal clk_count, clk_count_nxt : unsigned(42 downto 0) := (others => '0');
signal count_inc, count_rst : std_ulogic;
signal rs, rs_nxt : std_ulogic;
signal data, data_nxt : std_ulogic_vector(7 downto 0);
-- LCD state registers
signal cursor_on, cursor_on_nxt : std_ulogic; -- Static cursor (1 = on , 0 = off)
signal blink_on, blink_on_nxt : std_ulogic; -- Cursor blinks (1 = on , 0 = off)
signal col, col_nxt : unsigned(3 downto 0);
signal row, row_nxt : unsigned(0 downto 0);
signal cursor_home : std_ulogic;
signal cursor_right : std_ulogic;
signal cursor_left : std_ulogic;
signal cursor_set : std_ulogic;
constant CYCLES_POWER_UP : natural := 50*(CV_SYS_CLOCK_RATE/1000); -- 50 ms
signal CYCLES_INIT_FUNC : natural;
signal CYCLES_INIT_FUNC_WAIT : natural;
signal CYCLES_INIT_DISP : natural;
signal CYCLES_INIT_DISP_WAIT : natural;
signal CYCLES_INIT_CLR : natural;
signal CYCLES_INIT_CLR_WAIT : natural;
signal CYCLES_INIT_ENTRY : natural;
signal CYCLES_INIT_ENTRY_WAIT : natural;
signal TIME_1us : natural;
signal TIME_50us : natural;
signal TIME_14us : natural;
signal TIME_27us : natural;
begin
CYCLES_INIT_FUNC <= 10*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else 10;
CYCLES_INIT_FUNC_WAIT <= CYCLES_INIT_FUNC + 50*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_FUNC + 50; -- + 50 us
CYCLES_INIT_DISP <= CYCLES_INIT_FUNC_WAIT + 10*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_FUNC_WAIT + 10; -- + 10 us
CYCLES_INIT_DISP_WAIT <= CYCLES_INIT_DISP + 50*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_DISP + 50; -- + 50 us
CYCLES_INIT_CLR <= CYCLES_INIT_DISP_WAIT + 10*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_DISP_WAIT + 10; -- + 10 us
CYCLES_INIT_CLR_WAIT <= CYCLES_INIT_CLR + 02*(CV_SYS_CLOCK_RATE/1000) when SIMULATION = false else CYCLES_INIT_CLR + 02; -- + 2 ms
CYCLES_INIT_ENTRY <= CYCLES_INIT_CLR_WAIT + 10*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_CLR_WAIT + 10; -- + 10 us
CYCLES_INIT_ENTRY_WAIT <= CYCLES_INIT_ENTRY + 60*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_ENTRY + 60; -- + 60 us
TIME_1us <= 01*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else 1; -- 1 us
TIME_50us <= 50*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else 50; -- 50 us
TIME_14us <= 14*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else 14; -- 14 us
TIME_27us <= 27*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else 27; -- 27 us
buf_inst : fifo
generic map (
DEPTH => CS_LCD_BUFFER,
WORDWIDTH => 8
)
port map (
clock => clock,
reset_n => reset_n,
write_en => buf_write_en,
data_in => buf_data_in,
read_en => buf_read_en,
data_out => buf_data_out,
empty => buf_empty,
full => buf_full,
fill_cnt => open
);
process(clock, reset_n)
begin
if reset_n = '0' then
clk_count <= (others => '0');
rs <= '0';
data <= (others => '0');
state <= S_POWER_UP;
-- LCD registers
cursor_on <= '0';
blink_on <= '0';
col <= (others => '0');
row <= (others => '0');
elsif rising_edge(clock) then
clk_count <= clk_count_nxt;
rs <= rs_nxt;
data <= data_nxt;
state <= state_nxt;
-- LCD registers
cursor_on <= cursor_on_nxt;
blink_on <= blink_on_nxt;
col <= col_nxt;
row <= row_nxt;
end if;
end process;
iobus_if : process(iobus_cs, iobus_wr, iobus_addr, iobus_din, buf_empty, buf_full, state)
begin
buf_write_en <= '0';
buf_data_in <= (others => '0');
iobus_irq_rdy <= not buf_full;
iobus_dout <= (others => '0');
-- chipselect
if iobus_cs = '1' then
-- write
if iobus_wr = '1' then
-- data
if iobus_addr = CV_ADDR_LCD_DATA then
-- avoid overflow
if buf_full = '0' then
buf_write_en <= '1';
buf_data_in <= iobus_din;
end if;
end if;
-- read
else
-- status
if iobus_addr = CV_ADDR_LCD_STATUS then
-- working
if buf_empty = '0' or state /= S_READY then
iobus_dout(0) <= '1';
else
iobus_dout(0) <= '0';
end if;
end if;
end if;
end if;
end process;
clk_count_nxt <= (others => '0') when count_rst = '1' else
clk_count + 1 when count_inc = '1' else
clk_count;
disp_rs <= rs;
disp_dat <= data;
disp_rw <= '0';
disp_pwr <= '1';
disp_blon <= '0';
process(state, clk_count, data, rs, cursor_on, blink_on, col, row, buf_empty, buf_data_out, CYCLES_INIT_FUNC, CYCLES_INIT_FUNC_WAIT, CYCLES_INIT_DISP, CYCLES_INIT_DISP_WAIT, CYCLES_INIT_CLR, CYCLES_INIT_CLR_WAIT, CYCLES_INIT_ENTRY, CYCLES_INIT_ENTRY_WAIT, TIME_1us, TIME_50us, TIME_14us, TIME_27us)
variable data_in : unsigned(7 downto 0) := (others => '0');
begin
state_nxt <= state;
data_nxt <= data;
rs_nxt <= rs;
cursor_on_nxt <= cursor_on;
blink_on_nxt <= blink_on;
count_rst <= '0';
count_inc <= '0';
disp_en <= '0';
buf_read_en <= '0';
cursor_home <= '0';
cursor_right <= '0';
cursor_left <= '0';
cursor_set <= '0';
case state is
-- Wait 50 ms to ensure VDD has risen and required LCD wait is met
WHEN S_POWER_UP =>
if (clk_count < CYCLES_POWER_UP) and not SIMULATION then
count_inc <= '1';
elsif (clk_count < 10) and SIMULATION then
count_inc <= '1';
else -- Power-up complete
count_rst <= '1';
rs_nxt <= '0';
data_nxt <= "00111100"; -- 2-line mode, display on
state_nxt <= S_INIT;
end if;
-- Cycle through initialization sequence
WHEN S_INIT =>
count_inc <= '1';
if clk_count < CYCLES_INIT_FUNC then -- Function set
disp_en <= '1';
elsif clk_count < CYCLES_INIT_FUNC_WAIT then -- Wait 50 us
disp_en <= '0';
data_nxt <= "00001100"; -- Display on, Cursor off, Blink off
elsif clk_count < CYCLES_INIT_DISP THEN -- Display on/off control
cursor_on_nxt <= '0'; -- Save cursor off state
blink_on_nxt <= '0'; -- Save blink off state
disp_en <= '1';
elsif clk_count < CYCLES_INIT_DISP_WAIT then -- Wait 50 us
disp_en <= '0';
data_nxt <= x"01";
elsif clk_count < CYCLES_INIT_CLR then -- Display clear
cursor_home <= '1';
disp_en <= '1';
elsif clk_count < CYCLES_INIT_CLR_WAIT then -- Wait 2 ms
disp_en <= '0';
data_nxt <= "00000110"; -- Increment mode, entire shift off
elsif clk_count < CYCLES_INIT_ENTRY then -- Entry mode set
disp_en <= '1';
elsif clk_count < CYCLES_INIT_ENTRY_WAIT then -- Wait 60 us
data_nxt <= (others => '0');
disp_en <= '0';
else -- Initialization complete
count_rst <= '1';
state_nxt <= S_READY;
END IF;
-- Wait for the enable signal (iobus_cs & iobus_wr) and then latch in the instruction
when S_READY =>
count_rst <= '1';
if buf_empty = '0' then
state_nxt <= S_SEND;
buf_read_en <= '1';
data_in := unsigned(buf_data_out(7 downto 0));
-- Code for a character
if (data_in>=16#20# and data_in<=16#7F#) or (data_in>=16#A0# and data_in<=16#FE#) then
rs_nxt <= '1';
data_nxt <= buf_data_out(7 downto 0);
cursor_right <= '1';
-- Code for a function
elsif (data_in>=16#00# and data_in<=16#06#) or (data_in>=16#80# and data_in<=16#9F#) then
rs_nxt <= '0';
if data_in = 16#00# then -- Display clear
data_nxt <= x"01";
cursor_home <= '1';
elsif data_in = 16#01# then -- Cursor on
data_nxt <= x"0" & '1' & '1' & '1' & blink_on;
cursor_on_nxt <= '1';
elsif data_in = 16#02# then -- Cursor off
data_nxt <= x"0" & '1' & '1' & '0' & blink_on;
cursor_on_nxt <= '0';
elsif data_in = 16#03# then -- Blinking on
data_nxt <= x"0" & '1' & '1' & cursor_on & '1';
blink_on_nxt <= '1';
elsif data_in = 16#04# then -- Blinking off
data_nxt <= x"0" & '1' & '1' & cursor_on & '0';
blink_on_nxt <= '0';
elsif data_in = 16#05# then -- Move cursor right
cursor_right <= '1';
state_nxt <= S_CURSOR_DATA;
elsif data_in = 16#06# then -- Move cursor left
cursor_left <= '1';
state_nxt <= S_CURSOR_DATA;
else
cursor_set <= '1';
state_nxt <= S_CURSOR_DATA;
end if;
-- Invalid codes will be ignored and the display won't get busy
else
rs_nxt <= '0';
data_nxt <= (others => '0');
state_nxt <= S_READY;
end if;
else
rs_nxt <= '0';
data_nxt <= (others => '0');
end if;
-- Send instruction to LCD
when S_SEND =>
if clk_count < TIME_50us then -- Do not exit for 50us
count_inc <= '1';
if clk_count < TIME_1us then -- Negative enable
disp_en <= '0';
elsif clk_count < TIME_14us then -- Positive enable half-cycle
disp_en <= '1';
elsif clk_count < TIME_27us then -- Negative enable half-cycle
disp_en <= '0';
end if;
else
rs_nxt <= '0';
data_nxt <= '1' & row(0) & "00" & std_ulogic_vector(col);
count_rst <= '1';
state_nxt <= S_CURSOR_SET;
end if;
when S_CURSOR_DATA =>
rs_nxt <= '0';
data_nxt <= '1' & row(0) & "00" & std_ulogic_vector(col);
count_rst <= '1';
state_nxt <= S_CURSOR_SET;
when S_CURSOR_SET =>
if clk_count < TIME_50us then -- Do not exit for 50us
count_inc <= '1';
if clk_count < TIME_1us then -- Negative enable
disp_en <= '0';
elsif clk_count < TIME_14us then -- Positive enable half-cycle
disp_en <= '1';
elsif clk_count < TIME_27us then -- Negative enable half-cycle
disp_en <= '0';
end if;
else
count_rst <= '1';
state_nxt <= S_READY;
end if;
end case;
end process;
process(col, row, cursor_home, cursor_right, cursor_left, cursor_set, buf_data_out)
begin
col_nxt <= col;
row_nxt <= row;
if cursor_home = '1' then
col_nxt <= (others => '0');
row_nxt <= (others => '0');
elsif cursor_right = '1' then
if col = 15 then
col_nxt <= (others => '0');
row_nxt <= row + 1;
else
col_nxt <= col + 1;
end if;
elsif cursor_left = '1' then
if col = 15 then
col_nxt <= (others => '0');
row_nxt <= row - 1;
else
col_nxt <= col - 1;
end if;
elsif cursor_set = '1' then
col_nxt <= unsigned(buf_data_out(3 downto 0));
row_nxt <= unsigned(buf_data_out(4 downto 4));
end if;
end process;
end rtl; | apache-2.0 | b472835fae9ce8e0fb8cc1f6ec55148a | 0.570255 | 2.705758 | false | false | false | false |
Fju/LeafySan | src/vhdl/modules/light_sensor.vhdl | 1 | 16,423 | ----------------------------------------------------------------------
-- Project : LeafySan
-- Module : Light Sensor Module
-- Authors : Florian Winkler
-- Lust update : 01.09.2017
-- Description : Reads a digital light sensor by Grove through an I2C bus
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity light_sensor is
generic (
CYCLE_TICKS : natural := 50000000 -- 1s
);
port(
clock : in std_ulogic;
reset : in std_ulogic;
-- i2c bus
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
enabled : in std_ulogic;
value : out unsigned(15 downto 0)
);
end light_sensor;
architecture rtl of light_sensor is
component calc_lux is
port(
clock : in std_ulogic;
reset : in std_ulogic;
channel0 : in unsigned(15 downto 0);
channel1 : in unsigned(15 downto 0);
start : in std_ulogic;
busy : out std_ulogic;
lux : out unsigned(15 downto 0)
);
end component calc_lux;
component i2c_master is
generic (
GV_SYS_CLOCK_RATE : natural := 50000000;
GV_I2C_CLOCK_RATE : natural := 100000;
GW_SLAVE_ADDR : natural := 7;
GV_MAX_BYTES : natural := 16;
GB_USE_INOUT : boolean := false; -- seperated io signals (ctrl, out, in)
GB_TIMEOUT : boolean := true
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
-- separated in / out
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
-- separated in / out
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
-- interface
busy : out std_ulogic;
cs : in std_ulogic;
mode : in std_ulogic_vector(1 downto 0); -- 00: only read; 01: only write; 10: first read, second write; 11: first write, second read
slave_addr : in std_ulogic_vector(GW_SLAVE_ADDR - 1 downto 0);
bytes_tx : in unsigned(to_log2(GV_MAX_BYTES + 1) - 1 downto 0);
bytes_rx : in unsigned(to_log2(GV_MAX_BYTES + 1) - 1 downto 0);
tx_data : in std_ulogic_vector(7 downto 0);
tx_data_valid : in std_ulogic;
rx_data_en : in std_ulogic;
rx_data : out std_ulogic_vector(7 downto 0);
rx_data_valid : out std_ulogic;
error : out std_ulogic
);
end component i2c_master;
type light_state_t is (S_LT_INIT_IDLE, S_LT_INIT_BYTE0, S_LT_INIT_BYTE1, S_LT_INIT_SEND, S_LT_IDLE,
S_LT_POWER_ON_BYTE0, S_LT_POWER_ON_BYTE1, S_LT_POWER_ON_SEND, S_LT_BOOT_DELAY,
S_LT_REGISTER_BYTE0, S_LT_REGISTER_SEND_BYTE0, S_LT_WAIT_READ, S_LT_READ_BYTE0, S_LT_CHECK,
S_LT_CALC_LUX, S_LT_POWER_OFF_BYTE0, S_LT_POWER_OFF_BYTE1, S_LT_POWER_OFF_SEND);
signal light_state, light_state_nxt : light_state_t;
constant LIGHT_SLAVE_ADDR : std_ulogic_vector(6 downto 0) := "0101001"; -- 0x29
-- light register addresses
constant LIGHT_REG_CONTROL : std_ulogic_vector(7 downto 0) := "10000000"; -- 0x80
constant LIGHT_REG_TIMING : std_ulogic_vector(7 downto 0) := "10000001"; -- 0x81
constant LIGHT_REG_INTERRUPT : std_ulogic_vector(7 downto 0) := "10000110"; -- 0x86
constant LIGHT_REG_CHANNEL0L : std_ulogic_vector(7 downto 0) := "10001100"; -- 0x8C
constant LIGHT_REG_CHANNEL0H : std_ulogic_vector(7 downto 0) := "10001101"; -- 0x8D
constant LIGHT_REG_CHANNEL1L : std_ulogic_vector(7 downto 0) := "10001110"; -- 0x8E
constant LIGHT_REG_CHANNEL1H : std_ulogic_vector(7 downto 0) := "10001111"; -- 0x8F
constant LIGHT_CMD_POWER_UP : std_ulogic_vector(7 downto 0) := "00000011"; -- 0x03
constant LIGHT_CMD_POWER_DOWN : std_ulogic_vector(7 downto 0) := "00000000"; -- 0x00
constant LIGHT_CMD_TIMING : std_ulogic_vector(7 downto 0) := "00010001"; -- 0x11 = high gain (16x), integration time = 101ms
-- contains channel addresses from whom we will read
type light_ch_reg_array is array (natural range <>) of std_ulogic_vector(7 downto 0);
constant LIGHT_CH_REG_LENGTH : natural := 4;
constant LIGHT_CH_REGS : light_ch_reg_array(0 to LIGHT_CH_REG_LENGTH - 1) := (
LIGHT_REG_CHANNEL0L, LIGHT_REG_CHANNEL0H, LIGHT_REG_CHANNEL1L, LIGHT_REG_CHANNEL1H
);
signal light_ch_reg_cnt, light_ch_reg_cnt_nxt : unsigned(to_log2(LIGHT_CH_REG_LENGTH + 1) - 1 downto 0);
signal light_ch_valid, light_ch_valid_nxt : std_ulogic;
type light_init_data_t is record
reg : std_ulogic_vector(7 downto 0);
cmd : std_ulogic_vector(7 downto 0);
end record;
type light_init_data_array is array (natural range<>) of light_init_data_t;
constant LIGHT_INIT_DATA_LENGTH : natural := 4;
constant LIGHT_INIT_DATA : light_init_data_array(0 to LIGHT_INIT_DATA_LENGTH - 1) := (
(LIGHT_REG_CONTROL, LIGHT_CMD_POWER_UP), -- power up
(LIGHT_REG_TIMING, LIGHT_CMD_TIMING), -- setup timing (gain + integration time)
(LIGHT_REG_INTERRUPT, (others => '0')), -- interrupt
(LIGHT_REG_CONTROL, LIGHT_CMD_POWER_DOWN) -- power down
);
signal light_init_cnt, light_init_cnt_nxt : unsigned(to_log2(LIGHT_INIT_DATA_LENGTH + 1) - 1 downto 0);
-- register to save received channel values
type light_ch_vals_array is array (natural range <>) of std_ulogic_vector(7 downto 0);
signal light_ch_vals, light_ch_vals_nxt : light_ch_vals_array(0 to LIGHT_CH_REG_LENGTH - 1);
signal light_busy : std_ulogic;
constant LIGHT_BOOT_DELAY_TICKS : natural := 5200000; -- 104 ms
signal light_boot_delay_cnt, light_boot_delay_cnt_nxt : unsigned(to_log2(LIGHT_BOOT_DELAY_TICKS) - 1 downto 0);
-- signals of `i2c_master` component
signal i2c_reset_n : std_ulogic;
signal i2c_busy : std_ulogic;
signal i2c_cs : std_ulogic;
signal i2c_mode : std_ulogic_vector(1 downto 0);
signal i2c_slave_addr : std_ulogic_vector(6 downto 0);
signal i2c_bytes_tx : unsigned(4 downto 0);
signal i2c_bytes_rx : unsigned(4 downto 0);
signal i2c_tx_data : std_ulogic_vector(7 downto 0);
signal i2c_tx_data_valid : std_ulogic;
signal i2c_rx_data_en : std_ulogic;
signal i2c_rx_data : std_ulogic_vector(7 downto 0);
signal i2c_rx_data_valid : std_ulogic;
signal i2c_error : std_ulogic;
-- signals of `calc_lux` component
signal calc_lux_start : std_ulogic;
signal calc_lux_busy : std_ulogic;
signal calc_lux_value : unsigned(15 downto 0);
signal calc_lux_channel0 : unsigned(15 downto 0);
signal calc_lux_channel1 : unsigned(15 downto 0);
signal brightness_reg, brightness_reg_nxt : unsigned(15 downto 0);
signal cycle_cnt, cycle_cnt_nxt : unsigned(to_log2(CYCLE_TICKS) - 1 downto 0);
signal cycle_pulse : std_ulogic;
begin
-- configure `calc_lux` signal assignments
calc_lux_inst : calc_lux
port map (
clock => clock,
reset => reset,
start => calc_lux_start,
busy => calc_lux_busy,
lux => calc_lux_value,
channel0 => calc_lux_channel0,
channel1 => calc_lux_channel1
);
-- configure `i2c_master` signal assignments
i2c_master_inst : i2c_master
generic map (
GV_SYS_CLOCK_RATE => CV_SYS_CLOCK_RATE,
GV_I2C_CLOCK_RATE => 100000, -- fast mode 400kHz
GW_SLAVE_ADDR => 7,
GV_MAX_BYTES => 16,
GB_USE_INOUT => false,
GB_TIMEOUT => true
)
port map (
clock => clock,
reset_n => i2c_reset_n,
i2c_clk_ctrl => i2c_clk_ctrl,
i2c_clk_in => i2c_clk_in,
i2c_clk_out => i2c_clk_out,
i2c_dat_ctrl => i2c_dat_ctrl,
i2c_dat_in => i2c_dat_in,
i2c_dat_out => i2c_dat_out,
busy => i2c_busy,
cs => i2c_cs,
mode => i2c_mode,
slave_addr => i2c_slave_addr,
bytes_tx => i2c_bytes_tx,
bytes_rx => i2c_bytes_rx,
tx_data => i2c_tx_data,
tx_data_valid => i2c_tx_data_valid,
rx_data => i2c_rx_data,
rx_data_valid => i2c_rx_data_valid,
rx_data_en => i2c_rx_data_en,
error => i2c_error
);
-- sequential process
process(clock, reset)
begin
i2c_reset_n <= not(reset);
if reset = '1' then
light_state <= S_LT_INIT_IDLE;
light_init_cnt <= (others => '0');
light_ch_reg_cnt <= (others => '0');
light_ch_valid <= '0';
light_ch_vals <= (others => (others => '0'));
light_boot_delay_cnt <= (others => '0');
brightness_reg <= (others => '0');
cycle_cnt <= (others => '0');
elsif rising_edge(clock) then
light_state <= light_state_nxt;
light_init_cnt <= light_init_cnt_nxt;
light_ch_reg_cnt <= light_ch_reg_cnt_nxt;
light_ch_valid <= light_ch_valid_nxt;
light_ch_vals <= light_ch_vals_nxt;
light_boot_delay_cnt <= light_boot_delay_cnt_nxt;
brightness_reg <= brightness_reg_nxt;
cycle_cnt <= cycle_cnt_nxt;
end if;
end process;
process(enabled, light_busy, cycle_cnt)
begin
cycle_pulse <= '0';
cycle_cnt_nxt <= cycle_cnt;
if cycle_cnt = to_unsigned(CYCLE_TICKS - 1, cycle_cnt'length) then
-- reset clock only if sensor isn't busy anymore and main entity enabled the reading process (enabled = '1')
if enabled = '1' and light_busy = '0' then
-- set pulse to HIGH when the sensor isn't busy anymore
cycle_pulse <= '1';
cycle_cnt_nxt <= (others => '0');
end if;
else
-- increment counter
cycle_cnt_nxt <= cycle_cnt + to_unsigned(1, cycle_cnt'length);
end if;
end process;
process(enabled, cycle_pulse, i2c_error, i2c_busy, i2c_rx_data, i2c_rx_data_valid, calc_lux_busy, calc_lux_value,
light_busy, light_state, light_init_cnt, light_ch_reg_cnt, light_ch_valid, light_ch_vals, light_boot_delay_cnt, brightness_reg)
variable lux_ch0 : unsigned(15 downto 0) := (others => '0');
variable lux_ch1 : unsigned(15 downto 0) := (others => '0');
begin
-- output values
value <= brightness_reg;
-- hold value by default
light_state_nxt <= light_state;
light_init_cnt_nxt <= light_init_cnt;
light_ch_reg_cnt_nxt <= light_ch_reg_cnt;
light_ch_valid_nxt <= light_ch_valid;
light_ch_vals_nxt <= light_ch_vals;
light_boot_delay_cnt_nxt <= light_boot_delay_cnt;
brightness_reg_nxt <= brightness_reg;
-- default assignments of `i2c_master` component
i2c_cs <= '0';
i2c_slave_addr <= LIGHT_SLAVE_ADDR;
i2c_mode <= "00";
i2c_bytes_rx <= (others => '0');
i2c_bytes_tx <= (others => '0');
i2c_rx_data_en <= '0';
i2c_tx_data_valid <= '0';
i2c_tx_data <= (others => '0');
-- default assignments of `calc_lux` component
calc_lux_channel0 <= (others => '0');
calc_lux_channel1 <= (others => '0');
calc_lux_start <= '0';
-- always busy by default
light_busy <= '1';
case light_state is
when S_LT_INIT_IDLE =>
-- waiting for cycle_pulse
light_busy <= i2c_busy;
if cycle_pulse = '1' then
light_state_nxt <= S_LT_INIT_BYTE0;
end if;
when S_LT_INIT_BYTE0 =>
-- write register address byte of the current init item as first byte
i2c_tx_data <= LIGHT_INIT_DATA(to_integer(light_init_cnt)).reg;
i2c_tx_data_valid <= '1';
light_state_nxt <= S_LT_INIT_BYTE1;
when S_LT_INIT_BYTE1 =>
-- write command byte of the current init item as second byte
i2c_tx_data <= LIGHT_INIT_DATA(to_integer(light_init_cnt)).cmd;
i2c_tx_data_valid <= '1';
light_state_nxt <= S_LT_INIT_SEND;
when S_LT_INIT_SEND =>
-- tx fifo filled, now send data
if i2c_busy = '0' then
i2c_cs <= '1';
-- write-only mode
i2c_mode <= "01";
-- write two bytes
i2c_bytes_tx <= to_unsigned(2, i2c_bytes_tx'length);
-- increment counter
light_init_cnt_nxt <= light_init_cnt + to_unsigned(1, light_init_cnt'length);
if light_init_cnt = to_unsigned(LIGHT_INIT_DATA_LENGTH - 1, light_init_cnt'length) then
-- leave cycle
light_state_nxt <= S_LT_IDLE;
-- reset counter
light_init_cnt_nxt <= (others => '0');
else
-- repeat writing for next init command
light_state_nxt <= S_LT_INIT_BYTE0;
end if;
end if;
when S_LT_IDLE =>
-- waiting for cycle_pulse, the light sensor will boot up completely meanwhile
light_busy <= i2c_busy;
if cycle_pulse = '1' then
light_state_nxt <= S_LT_POWER_ON_BYTE0;
light_ch_valid_nxt <= '1';
end if;
when S_LT_POWER_ON_BYTE0 =>
i2c_tx_data <= LIGHT_REG_CONTROL;
i2c_tx_data_valid <= '1';
light_state_nxt <= S_LT_POWER_ON_BYTE1;
when S_LT_POWER_ON_BYTE1 =>
i2c_tx_data <= LIGHT_CMD_POWER_UP;
i2c_tx_data_valid <= '1';
light_state_nxt <= S_LT_POWER_ON_SEND;
when S_LT_POWER_ON_SEND =>
-- send `power up` command to `control` register
if i2c_busy = '0' then
i2c_cs <= '1';
-- write-only mode
i2c_mode <= "01";
-- write two bytes
i2c_bytes_tx <= to_unsigned(2, i2c_bytes_tx'length);
light_state_nxt <= S_LT_BOOT_DELAY;
end if;
when S_LT_BOOT_DELAY =>
-- delay 104ms to wait for value integrety
if i2c_busy = '0' then
if light_boot_delay_cnt = to_unsigned(LIGHT_BOOT_DELAY_TICKS - 1, light_boot_delay_cnt'length) then
light_state_nxt <= S_LT_REGISTER_BYTE0;
light_boot_delay_cnt_nxt <= (others => '0');
else
light_boot_delay_cnt_nxt <= light_boot_delay_cnt + to_unsigned(1, light_boot_delay_cnt'length);
end if;
end if;
when S_LT_REGISTER_BYTE0 =>
-- write register address byte of current channel to tx fifo
i2c_tx_data <= LIGHT_CH_REGS(to_integer(light_ch_reg_cnt));
i2c_tx_data_valid <= '1';
light_state_nxt <= S_LT_REGISTER_SEND_BYTE0;
when S_LT_REGISTER_SEND_BYTE0 =>
if i2c_busy = '0' then
i2c_cs <= '1';
-- first write then read mode
i2c_mode <= "11";
-- write one byte from tx fifo
i2c_bytes_tx <= to_unsigned(1, i2c_bytes_tx'length);
-- expect to receive/read one byte from slave
i2c_bytes_rx <= to_unsigned(1, i2c_bytes_rx'length);
light_state_nxt <= S_LT_WAIT_READ;
end if;
when S_LT_WAIT_READ =>
-- wait for rx fifo to be filled
if i2c_busy = '0' then
light_state_nxt <= S_LT_READ_BYTE0;
end if;
when S_LT_READ_BYTE0 =>
if i2c_error = '1' then
-- an error occured, data isn't valid
light_ch_valid_nxt <= '0';
end if;
if i2c_rx_data_valid = '1' then
-- read one byte from rx fifo
i2c_rx_data_en <= '1';
light_ch_vals_nxt(to_integer(light_ch_reg_cnt)) <= i2c_rx_data;
else
-- rx fifo empty
if light_ch_reg_cnt = to_unsigned(LIGHT_CH_REG_LENGTH - 1, light_ch_reg_cnt'length) then
-- received everything
light_state_nxt <= S_LT_CHECK;
else
-- write/read next channel register
light_state_nxt <= S_LT_REGISTER_BYTE0;
light_ch_reg_cnt_nxt <= light_ch_reg_cnt + to_unsigned(1, light_ch_reg_cnt'length);
end if;
end if;
when S_LT_CHECK =>
lux_ch0 := unsigned(std_ulogic_vector'(light_ch_vals(1) & light_ch_vals(0)));
lux_ch1 := unsigned(std_ulogic_vector'(light_ch_vals(3) & light_ch_vals(2)));
-- clean up for next cycle, independent from valid data
light_ch_reg_cnt_nxt <= (others => '0');
if light_ch_valid = '1' and lux_ch0 <= 4900 and lux_ch0 >= 2 * lux_ch1 then
calc_lux_start <= '1'; -- start calculation
calc_lux_channel0 <= lux_ch0;
calc_lux_channel1 <= lux_ch1;
light_state_nxt <= S_LT_CALC_LUX;
else
-- invalid data, skip to power off
light_state_nxt <= S_LT_POWER_OFF_BYTE0;
end if;
when S_LT_CALC_LUX =>
calc_lux_start <= '1'; -- keep high for ack mechanism
if calc_lux_busy = '0' then
calc_lux_start <= '0'; -- ack
brightness_reg_nxt <= calc_lux_value;
light_state_nxt <= S_LT_POWER_OFF_BYTE0;
end if;
when S_LT_POWER_OFF_BYTE0 =>
i2c_tx_data <= LIGHT_REG_CONTROL;
i2c_tx_data_valid <= '1';
light_state_nxt <= S_LT_POWER_OFF_BYTE1;
when S_LT_POWER_OFF_BYTE1 =>
i2c_tx_data <= LIGHT_CMD_POWER_DOWN;
i2c_tx_data_valid <= '1';
light_state_nxt <= S_LT_POWER_OFF_SEND;
when S_LT_POWER_OFF_SEND =>
-- send `power off` command to `control` register
if i2c_busy = '0' then
i2c_cs <= '1';
-- write-only mode
i2c_mode <= "01";
-- write two bytes from tx fifo
i2c_bytes_tx <= to_unsigned(2, i2c_bytes_tx'length);
light_state_nxt <= S_LT_IDLE;
end if;
end case;
end process;
end rtl;
| apache-2.0 | 4d9ac604139f8016f144afc1f9ad5470 | 0.619619 | 2.582233 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_infrared_test.vhdl | 1 | 5,255 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Jan Dürre
-- Year : 2014
-- Description : This example awaits an interrupt from the
-- infra-red receiver, then displays the received
-- 8 bit on two hex displays (data is also send
-- to usb)
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
begin
process(ir_irq_rx, ir_din)
begin
-- default
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
-- on interrupt
if ir_irq_rx = '1' then
-- get rx-data
ir_cs <= '1';
ir_wr <= '0';
ir_addr <= CV_ADDR_IR_DATA;
ir_dout <= (others => '0');
-- ack interrupt
ir_ack_rx <= '1';
-- display rx-data on hex displays
sevenseg_cs <= '1';
sevenseg_wr <= '1';
sevenseg_addr <= CV_ADDR_SEVENSEG_HEX5 or CV_ADDR_SEVENSEG_HEX4;
sevenseg_dout(7 downto 0) <= ir_din(7 downto 0);
end if;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
led_green <= (others => '0');
led_red <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 | 82ecd7740e92172d60a54066856107ac | 0.545195 | 2.592501 | false | false | false | false |
jdeblese/mwfc | mwfc.srcs/sim_1/fpdiv_tb.vhd | 1 | 4,310 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fpdiv_tb is
end fpdiv_tb;
architecture Behavioral of fpdiv_tb is
constant clk_period : time := 10 ns;
signal clk : std_logic := '0';
signal rst : std_logic;
constant precision : integer := 13;
constant inputbits : integer := precision + 5;
constant timerbits : integer := 18;
constant nscalestages : integer := 6;
signal dividend : unsigned (inputbits-1 downto 0);
signal divisor : unsigned (timerbits-1 downto 0);
signal ratio : unsigned (precision-1 downto 0);
signal scale : signed (nscalestages-1 downto 0);
signal busy : std_logic;
signal overflow : std_logic;
signal strobe : std_logic := '0';
begin
clk <= not clk after clk_period/2;
stim : process
begin
rst <= '1';
wait for clk_period * 10;
rst <= '0';
wait for clk_period;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(1, dividend'length);
divisor <= to_unsigned(262143, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert overflow = '1' report "Test should have overflowed" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(0, dividend'length);
divisor <= to_unsigned(262143, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert overflow = '0' report "Test should have overflowed" severity error;
assert ratio = 0 report "Bad quotient" severity error;
assert scale = 0 report "Bad scale" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(27, dividend'length);
divisor <= to_unsigned(4, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert ratio = 6912 report "Bad quotient" severity error;
assert scale = -10 report "Bad scale" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(3277, dividend'length);
divisor <= to_unsigned(8192, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert ratio = 6554 report "Bad quotient" severity error;
assert scale = -14 report "Bad scale" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(1, dividend'length);
divisor <= to_unsigned(8193, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 36;
assert overflow = '1' report "Test should overflow" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= to_unsigned(1, dividend'length);
divisor <= to_unsigned(9, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert ratio = 7280 report "Bad quotient" severity error;
assert scale = -16 report "Bad scale" severity error;
assert busy = '0' report "Divider is still busy" severity error;
dividend <= (others => '1');
divisor <= to_unsigned(1, divisor'length);
strobe <= '1';
wait for clk_period;
strobe <= '0';
wait for clk_period * 24;
assert overflow = '1' report "Test should have overflowed" severity error;
-- FIXME formulate a divisor overflow test
wait;
end process;
dut : entity work.fpdiv
generic map (
size => divisor'length,
precision => ratio'length,
pscale => scale'length )
port map (
dividend => dividend,
divisor => divisor,
quotient => ratio,
scale => scale,
busy => busy,
overflow => overflow,
strobe => strobe,
clk => clk,
rst => rst );
end Behavioral;
| mit | 5f6dc71b4b5d26024af2f3dab0b49537 | 0.584223 | 4.184466 | false | false | false | false |
J-Rios/VHDL_Modules | 2.Secuencial/RegFile.vhd | 1 | 1,106 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity REG_FILE is
generic
(
B : NATURAL := 8; -- Address Bus width
W : NATURAL := 2 -- Data Bus width
);
port
(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
wr_en : in STD_LOGIC;
w_addr : in STD_LOGIC_VECTOR(W-1 downto 0);
r_addr : in STD_LOGIC_VECTOR(W-1 downto 0);
w_data : in STD_LOGIC_VECTOR(B-1 downto 0);
r_data : out STD_LOGIC_VECTOR(B-1 downto 0)
);
end REG_FILE;
-------------------------------------------------------------------------
architecture Behavioral of REG_FILE is
type REG_FILE_TYPE is array (2**W-1 downto 0) of STD_LOGIC_VECTOR (B-1 downto 0);
signal array_reg : REG_FILE_TYPE;
begin
process(clk,reset)
begin
if (reset = '1') then
array_reg <= (others => (others => '0'));
elsif (rising_edge(clk)) then
if (wr_en = '1') then
array_reg(to_integer(unsigned(w_addr))) <= w_data;
end if;
end if;
end process;
r_data <= array_reg(to_integer(unsigned(r_addr)));
end Behavioral;
| gpl-3.0 | 94d00728b35342880132c02ec3934de0 | 0.54792 | 2.925926 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_adc_dac_voltage_to_lcd.vhdl | 1 | 8,897 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Christian Leibold
-- Year : 2013
-- Description : The code in this file reads the measured voltage
-- from the ADC-Channel selected by the first three
-- switches and prints it on the LCD.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register
type state_t is (S_INIT, S_WAIT_TIME, S_ADC_READ, S_PRINT_CHARACTERS);
signal state, state_nxt : state_t;
-- Define a constant array with the hex-codes of every single character to print them on the LC-Display
signal lcd_cmds, lcd_cmds_nxt : lcd_commands_t(0 to 12); -- 06
-- register to save a value from the ADC and show it on the first twelve red LEDs
signal adc_value, adc_value_nxt : std_ulogic_vector(11 downto 0);
signal char_count, char_count_nxt : unsigned(to_log2(lcd_cmds'length)-1 downto 0);
signal count , count_nxt : unsigned(31 downto 0);
begin
-- sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
adc_value <= (others => '0');
char_count <= (others => '0');
lcd_cmds <= (others => (others => '0'));
count <= (others => '0');
state <= S_INIT;
elsif rising_edge(clock) then
adc_value <= adc_value_nxt;
char_count <= char_count_nxt;
lcd_cmds <= lcd_cmds_nxt;
count <= count_nxt;
state <= state_nxt;
end if;
end process;
-- combinational process contains logic only
process(state, key, adc_dac_din, lcd_din, lcd_irq_rdy, switch, char_count, lcd_cmds, adc_value, count)
variable bcd_value : unsigned(15 downto 0) := (others => '0');
variable adc_recalc : std_ulogic_vector(11 downto 0) := (others => '0');
begin
-- default assignments
-- set default values for the internal bus -> zero on all signals means, nothing will happen
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
-- hold previous values of all registers
adc_value_nxt <= adc_value;
char_count_nxt <= char_count;
lcd_cmds_nxt <= lcd_cmds;
state_nxt <= state;
count_nxt <= count;
case state is
-- Initial start state
when S_INIT =>
-- Wait for a press on KEY0 to start the function
if key(0) = '1' then
-- activate ADC channels
adc_dac_cs <= '1';
adc_dac_wr <= '1';
adc_dac_addr <= CV_ADDR_ADC_DAC_CTRL;
adc_dac_dout(9 downto 0) <= "0011111111";
-- next state
state_nxt <= S_WAIT_TIME;
end if;
when S_WAIT_TIME =>
count_nxt <= count + 1;
if count = 5000000 then
count_nxt <= (others => '0');
state_nxt <= S_ADC_READ;
end if;
-- Read value from ADC and save it into the led_out-register
when S_ADC_READ =>
-- Enable the Chip-Select signal for the ADC/DAC-Module
adc_dac_cs <= '1';
-- Set read-address for the value of the selected ADC-Channel
adc_dac_addr(2 downto 0) <= switch(2 downto 0);
-- Set the value of the selected ADC-Channel as next value for the led_out-register
adc_value_nxt <= adc_dac_din(11 downto 0);
adc_recalc := std_ulogic_vector(resize(shift_right( unsigned(adc_dac_din(11 downto 0)) * 3300 ,12), adc_recalc'length));
bcd_value := unsigned(to_bcd(adc_recalc, 4));
lcd_cmds_nxt <= lcd_cmd(lcd_cursor_pos(0, 0) & asciitext("ADC") & ascii(unsigned('0' & switch(2 downto 0))) & asciitext(": ") & ascii(bcd_value(15 downto 12)) & ascii('.') & ascii(bcd_value(11 downto 8)) & ascii(bcd_value(7 downto 4)) & ascii(bcd_value(3 downto 0)) & ascii('V'));
char_count_nxt <= (others => '0');
-- next state
state_nxt <= S_PRINT_CHARACTERS;
-- Set a constant a value to a DAC-Channel in this state
when S_PRINT_CHARACTERS =>
if lcd_irq_rdy = '1' then
-- Enable the Chip-Select signal for the LCD-Module
lcd_cs <= '1';
-- Set the write to one to write a value into a register
lcd_wr <= '1';
-- Set address of the LCD interface to print a character
lcd_addr <= CV_ADDR_LCD_DATA;
-- Set the value which should be written into the selected register the in the selected module
lcd_dout(7 downto 0) <= lcd_cmds(to_integer(char_count));
if char_count = lcd_cmds'length-1 then
-- next state
state_nxt <= S_WAIT_TIME;
else
char_count_nxt <= char_count + 1;
end if;
end if;
end case;
end process;
-- Default assignment for the 8th green LED
led_green(8) <= '0';
led_green_gen : for i in 0 to 7 generate
led_green(i) <= '1' when unsigned(adc_value) >= (i+1)*(4096/26) else '0';
end generate led_green_gen;
led_red_gen : for i in 0 to 17 generate
led_red(i) <= '1' when unsigned(adc_value) >= ((i+1)*(4096/26))+8*(4096/26) else '0';
end generate led_red_gen;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 | 0147487d0b219bde3a668db4637bad92 | 0.592559 | 2.770788 | false | false | false | false |
Fju/LeafySan | src/vhdl/modules/peripherals.vhdl | 1 | 10,557 | ----------------------------------------------------------------------
-- Project : LeafySan
-- Module : Peripherals Control Module
-- Authors : Florian Winkler
-- Last update : 03.09.2017
-- Description : Automation of peripherals, activates and deactivates heating, watering,
-- ventilation and lighting according to the sensor values
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity peripherals is
port(
clock : in std_ulogic;
reset : in std_ulogic;
temperature : in unsigned(11 downto 0);
brightness : in unsigned(15 downto 0);
moisture : in unsigned(15 downto 0);
lighting_on : out std_ulogic;
heating_on : out std_ulogic;
watering_on : out std_ulogic;
ventilation_on : out std_ulogic;
heating_thresh : in unsigned(11 downto 0);
lighting_thresh : in unsigned(15 downto 0);
watering_thresh : in unsigned(15 downto 0)
);
end peripherals;
architecture rtl of peripherals is
constant TIMER_CLOCK_COUNT : natural := 50000000; -- 1s
constant LIGHTING_CYCLE_CLOCK_COUNT : natural := 5; -- 5s
constant HEATING_DELAY_CLOCK_COUNT : natural := 5; -- 5s
constant HEATING_TIMEOUT_CLOCK_COUNT : natural := 180; -- 3min
constant WATERING_DELAY_CLOCK_COUNT : natural := 1800; -- 30min
constant WATERING_TIMEOUT_CLOCK_COUNT : natural := 180; -- 2min
constant VENTILATION_DELAY_COUNT : natural := 900; -- 15min
constant VENTILATION_TIMEOUT_COUNT : natural := 300; -- 5min
type timer_state_t is (S_TIMER_RUNNING, S_TIMER_FINISHED);
-- no need for lighting state
type heating_state_t is (S_HEATING_OFF, S_HEATING_ON, S_HEATING_DELAY);
type watering_state_t is (S_WATERING_OFF, S_WATERING_ON, S_WATERING_DELAY);
type ventilation_state_t is (S_VENTILATION_ON, S_VENTILATION_OFF);
signal timer_state, timer_state_nxt : timer_state_t;
signal heating_state, heating_state_nxt : heating_state_t;
signal watering_state, watering_state_nxt : watering_state_t;
signal ventilation_state, ventilation_state_nxt : ventilation_state_t;
signal timer_clock, timer_clock_nxt : unsigned(to_log2(TIMER_CLOCK_COUNT) - 1 downto 0);
signal timer_pulse : std_ulogic;
signal lighting_clock, lighting_clock_nxt : unsigned(to_log2(LIGHTING_CYCLE_CLOCK_COUNT) - 1 downto 0);
signal watering_clock, watering_clock_nxt : unsigned(to_log2(max(WATERING_DELAY_CLOCK_COUNT, WATERING_TIMEOUT_CLOCK_COUNT)) - 1 downto 0);
signal heating_clock, heating_clock_nxt : unsigned(to_log2(max(HEATING_DELAY_CLOCK_COUNT, HEATING_TIMEOUT_CLOCK_COUNT)) - 1 downto 0);
signal ventilation_clock, ventilation_clock_nxt : unsigned(to_log2(max(VENTILATION_DELAY_COUNT, VENTILATION_TIMEOUT_COUNT)) - 1 downto 0);
signal lighting_next, lighting_next_nxt : std_ulogic;
signal lighting_current, lighting_current_nxt : std_ulogic;
begin
-- sequential process
process(clock, reset)
begin
if reset = '1' then
timer_state <= S_TIMER_RUNNING;
heating_state <= S_HEATING_OFF;
watering_state <= S_WATERING_OFF;
ventilation_state <= S_VENTILATION_OFF;
timer_clock <= (others => '0');
lighting_clock <= (others => '0');
watering_clock <= (others => '0');
heating_clock <= (others => '0');
ventilation_clock <= (others => '0');
lighting_next <= '0';
lighting_current <= '0';
elsif rising_edge(clock) then
timer_state <= timer_state_nxt;
heating_state <= heating_state_nxt;
watering_state <= watering_state_nxt;
ventilation_state <= ventilation_state_nxt;
timer_clock <= timer_clock_nxt;
lighting_clock <= lighting_clock_nxt;
watering_clock <= watering_clock_nxt;
heating_clock <= heating_clock_nxt;
ventilation_clock <= ventilation_clock_nxt;
lighting_next <= lighting_next_nxt;
lighting_current <= lighting_current_nxt;
end if;
end process;
-- generate a timer that sets pulse to high every second
process(timer_state, timer_clock, timer_pulse)
begin
-- hold previous values
timer_state_nxt <= timer_state;
timer_clock_nxt <= timer_clock;
case timer_state is
when S_TIMER_RUNNING =>
timer_pulse <= '0';
if timer_clock = to_unsigned(TIMER_CLOCK_COUNT, timer_clock'length) then
timer_clock_nxt <= (others => '0');
timer_state_nxt <= S_TIMER_FINISHED;
else
timer_clock_nxt <= timer_clock + to_unsigned(1, timer_clock'length);
end if;
when S_TIMER_FINISHED =>
timer_pulse <= '1';
timer_state_nxt <= S_TIMER_RUNNING;
end case;
end process;
process(temperature, timer_pulse, heating_state, heating_clock, heating_thresh)
begin
-- hold previous values
heating_state_nxt <= heating_state;
heating_clock_nxt <= heating_clock;
-- `off` by default
heating_on <= '0';
case heating_state is
when S_HEATING_OFF =>
-- power on heating only if temperature is 1 degree celsius below the desired value
if temperature < heating_thresh - to_unsigned(10, temperature'length) then
heating_state_nxt <= S_HEATING_ON;
end if;
when S_HEATING_ON =>
heating_on <= '1';
-- power off heating if temperature is 1 degree above the desired value
if temperature >= heating_thresh + to_unsigned(10, temperature'length) then
heating_state_nxt <= S_HEATING_DELAY;
heating_clock_nxt <= (others => '0');
end if;
if timer_pulse = '1' then
if heating_clock = to_unsigned(HEATING_TIMEOUT_CLOCK_COUNT - 1, heating_clock'length) then
-- in case heating hasn't reach desired temperature after certain time, power off automatically
heating_state_nxt <= S_HEATING_DELAY;
heating_clock_nxt <= (others => '0');
else
heating_clock_nxt <= heating_clock + to_unsigned(1, heating_clock'length);
end if;
end if;
when S_HEATING_DELAY =>
if timer_pulse = '1' then
if heating_clock = to_unsigned(HEATING_DELAY_CLOCK_COUNT - 1, heating_clock'length) then
-- end delay
heating_state_nxt <= S_HEATING_OFF;
heating_clock_nxt <= (others => '0');
else
heating_clock_nxt <= heating_clock + to_unsigned(1, heating_clock'length);
end if;
end if;
end case;
end process;
process(timer_pulse, lighting_clock, lighting_current, lighting_next, brightness, lighting_thresh)
begin
-- hold previous values
lighting_clock_nxt <= lighting_clock;
lighting_next_nxt <= lighting_next;
lighting_current_nxt <= lighting_current;
-- `off` by default
lighting_on <= lighting_current;
if timer_pulse = '1' then
if lighting_clock = to_unsigned(LIGHTING_CYCLE_CLOCK_COUNT - 1, lighting_clock'length) then
-- reset clock and update registers
lighting_clock_nxt <= (others => '0');
lighting_current_nxt <= lighting_next;
lighting_next_nxt <= not(lighting_current);
else
-- increment clock register and update/hold next state register value
lighting_clock_nxt <= lighting_clock + to_unsigned(1, lighting_clock'length);
if lighting_current = '0' then
-- lighting is turned off currently
if brightness >= lighting_thresh then
-- next lighting state will be `off` again, because not all values were below threshold (too bright)
lighting_next_nxt <= '0';
end if;
-- otherwise the next lighting state will be `on`, see `not(lighting_current)` line 158
else
-- lighting is turned on currently
if brightness <= lighting_thresh then
-- next lighting state will be `on` again, because not all values were above threshold (too dark)
lighting_next_nxt <= '1';
end if;
-- otherwise the next lighting state will be `off`, see `not(lighting_current)` line 158
end if;
end if;
end if;
end process;
process(timer_pulse, watering_state, watering_clock, moisture, watering_thresh)
begin
-- hold previous values
watering_state_nxt <= watering_state;
watering_clock_nxt <= watering_clock;
-- `off` by default
watering_on <= '0';
case watering_state is
when S_WATERING_OFF =>
-- power on watering only if moisture value is 10 steps below threshold
if moisture < watering_thresh - to_unsigned(10, moisture'length) then
watering_state_nxt <= S_WATERING_ON;
end if;
when S_WATERING_ON =>
watering_on <= '1';
-- power off watering if moisture is above threshold
if moisture >= watering_thresh then
watering_state_nxt <= S_WATERING_DELAY;
watering_clock_nxt <= (others => '0');
end if;
if timer_pulse = '1' then
if watering_clock = to_unsigned(WATERING_TIMEOUT_CLOCK_COUNT - 1, watering_clock'length) then
-- in case watering hasn't reach desired moisture after certain time, power off automatically
-- in order to prevent permanent watering
watering_state_nxt <= S_WATERING_DELAY;
watering_clock_nxt <= (others => '0');
else
watering_clock_nxt <= watering_clock + to_unsigned(1, watering_clock'length);
end if;
end if;
when S_WATERING_DELAY =>
if timer_pulse = '1' then
if watering_clock = to_unsigned(WATERING_DELAY_CLOCK_COUNT - 1, watering_clock'length) then
-- end delay
watering_state_nxt <= S_WATERING_OFF;
watering_clock_nxt <= (others => '0');
else
watering_clock_nxt <= watering_clock + to_unsigned(1, watering_clock'length);
end if;
end if;
end case;
end process;
process(timer_pulse, ventilation_state, ventilation_clock)
begin
-- hold previous values
ventilation_state_nxt <= ventilation_state;
ventilation_clock_nxt <= ventilation_clock;
-- `off` by default
ventilation_on <= '0';
case ventilation_state is
when S_VENTILATION_OFF =>
if timer_pulse = '1' then
if ventilation_clock = to_unsigned(VENTILATION_DELAY_COUNT - 1, ventilation_clock'length) then
ventilation_clock_nxt <= (others => '0');
ventilation_state_nxt <= S_VENTILATION_ON;
else
ventilation_clock_nxt <= ventilation_clock + to_unsigned(1, ventilation_clock'length);
end if;
end if;
when S_VENTILATION_ON =>
ventilation_on <= '1';
if timer_pulse = '1' then
if ventilation_clock = to_unsigned(VENTILATION_TIMEOUT_COUNT - 1, ventilation_clock'length) then
ventilation_clock_nxt <= (others => '0');
ventilation_state_nxt <= S_VENTILATION_OFF;
else
ventilation_clock_nxt <= ventilation_clock + to_unsigned(1, ventilation_clock'length);
end if;
end if;
end case;
end process;
end rtl;
| apache-2.0 | 61e5c60c946b50c373b111e968c5326b | 0.665246 | 3.024928 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_sram_test.vhdl | 1 | 7,776 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Jan Dürre
-- Year : 2013
-- Description : This example fills the SRAM with some generated
-- data (cnt(15 downto 0)). Afterwards the data is
-- read and compared to the written data. The number
-- of errors is displayed on red LEDs.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register
type state_t is (IDLE, WRITE_TO_SRAM, READ_FROM_SRAM, DO_NOTHING, ERROR_DETECTED);
signal state, state_nxt : state_t;
-- counter register
signal cnt, cnt_nxt : unsigned(CW_ADDR_SRAM-1 downto 0);
-- error counter register
signal error_cnt, error_cnt_nxt : unsigned(CW_ADDR_SRAM-1 downto 0);
begin
-- sequential process
process (clock, reset)
begin
-- async reset
if reset = '1' then
state <= IDLE;
cnt <= (others => '0');
error_cnt <= (others => '0');
elsif rising_edge(clock) then
state <= state_nxt;
cnt <= cnt_nxt;
error_cnt <= error_cnt_nxt;
end if;
end process;
-- logic
process (state, cnt, error_cnt, sram_din)
begin
-- standard assignments
-- hold values of registers
state_nxt <= state;
cnt_nxt <= cnt;
error_cnt_nxt <= error_cnt;
-- set bus signals to standard values (not in use)
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
-- turn of green leds
led_green <= (others => '0');
-- view error count on red leds
led_red <= std_ulogic_vector(error_cnt(17 downto 0));
-- state machine
case state is
-- starting state
when IDLE =>
-- reset counters
cnt_nxt <= (others => '0');
error_cnt_nxt <= (others => '0');
-- next state
state_nxt <= WRITE_TO_SRAM;
-- fill sram with content of cnt
when WRITE_TO_SRAM =>
-- indicate state WRITE_TO_SRAM
led_green(0) <= '1';
-- while cnt < max value
if cnt /= unsigned(to_signed(-1, cnt'length)) then
-- activate chipselect
sram_cs <= '1';
-- write mode
sram_wr <= '1';
-- set address
sram_addr <= std_ulogic_vector(cnt);
-- set write-data to cnt-value
sram_dout <= std_ulogic_vector(cnt(sram_dout'length-1 downto 0));
-- inc counter
cnt_nxt <= cnt + to_unsigned(1, cnt'length);
-- cnt = max value
else
-- next state
state_nxt <= READ_FROM_SRAM;
-- reset counter
cnt_nxt <= (others => '0');
end if;
-- read all data from sram
when READ_FROM_SRAM =>
-- indicate state READ_FROM_SRAM
led_green(1) <= '1';
-- while cnt < max value
if cnt /= unsigned(to_signed(-1, cnt'length)) then
-- activate chipselect
sram_cs <= '1';
-- read mode
sram_wr <= '0';
-- set address
sram_addr <= std_ulogic_vector(cnt);
-- if returned data (iobus_din) is not equal counter
if unsigned(sram_din) /= cnt(sram_din'length-1 downto 0) then
-- inc error counter
error_cnt_nxt <= error_cnt + 1;
state_nxt <= ERROR_DETECTED;
end if;
-- inc counter
cnt_nxt <= cnt + 1;
-- cnt = max value
else
-- next state
state_nxt <= DO_NOTHING;
end if;
-- wait forever
when DO_NOTHING =>
-- indicate state DO_NOTHING
led_green(2) <= '1';
-- wait forever on error
when ERROR_DETECTED =>
-- indicate state ERROR_DETECTED
led_green(3) <= '1';
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 | 1f723cc7d76749b01f66fe73d5910afa | 0.552669 | 2.840701 | false | false | false | false |
shaolinbertrand/Processador_N.I.N.A | MULT.vhd | 1 | 1,344 | library ieee;
use ieee.std_logic_1164.all;
entity MULT is
port (a,b: in std_logic_vector(3 downto 0);
s: out std_logic_vector(3 downto 0));
end MULT;
architecture arch_MULT of MULT is
function deslocar(x: std_logic_vector(3 downto 0))
return std_logic_vector is
variable y: std_logic_vector(3 downto 0);
begin
for i in 3 downto 1 loop
y(i):=x(i-1);
end loop;
y(0):='0';
return y;
end;
function somador(a: std_logic_vector(3 downto 0);
b: std_logic_vector(3 downto 0))
return std_logic_vector is
variable vaium: std_logic;
variable soma: std_logic_vector(3 downto 0);
begin
vaium:='0';
for i in 0 to 3 loop
soma(i):=a(i) xor b(i) xor vaium;
vaium:=(a(i) and b(i)) or (b(i) and Vaium) or(vaium and a(i));
end loop;
return soma;
end;
begin
process(a,b)
variable aux1: std_logic_vector(3 downto 0);
variable aux2: std_logic_vector(3 downto 0);
variable vaium: std_logic;
begin
aux1:="0000";
aux2:=a;
vaium:= '0';
for i in 0 to 3 loop
aux1:=deslocar(aux1);
vaium:=aux2(3);
if vaium='1' then
aux1:=somador(aux1,b);
end if;
aux2:=deslocar(aux2);
end loop;
s<=aux1;
end process;
end arch_MULT;
| gpl-3.0 | dbf783697ab2db711f8a9c3f5e0b5287 | 0.568452 | 2.788382 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/or/myOr2_tb.vhdl | 1 | 1,122 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myOr2_tb is
end myOr2_tb;
architecture behavorial of myOr2_tb is
-- component declarations
component myOr2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
-- signal declations
signal s1: std_logic;
signal s2: std_logic;
signal o1: std_logic;
begin
-- component instantiation and port mapping
myOr2_a: myOr2 port map(a => s1, b => s2, s => o1);
process
begin
s1 <= '0';
s2 <= '0';
wait for 1 ns;
assert o1 = '0' report "0 or 0 should equal 0" severity error;
s1 <= '1';
s2 <= '0';
wait for 1 ns;
assert o1 = '1' report "0 or 1 should equal 1" severity error;
s1 <= '0';
s2 <= '1';
wait for 1 ns;
assert o1 = '1' report "0 or 1 should equal 1" severity error;
s1 <= '1';
s2 <= '1';
wait for 1 ns;
assert o1 = '1' report "1 or 1 should equal 1" severity error;
assert false report "Testing complete" severity note;
wait;
end process;
end behavorial;
| mit | 332c51db12003e33aa663c95a99ed311 | 0.562389 | 3.319527 | false | false | false | false |
Fju/LeafySan | src/vhdl/utils/clock_generator.vhdl | 1 | 1,127 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : simple clock generator (e.g. for spi clocks)
-- Author : Jan Dürre
-- Last update : 24.04.2014
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity clock_generator is
generic(
GV_CLOCK_DIV : natural := 50
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
enable : in std_ulogic;
clock_out : out std_ulogic
);
end clock_generator;
architecture rtl of clock_generator is
signal counter, counter_nxt : unsigned(to_log2(GV_CLOCK_DIV)-1 downto 0);
begin
process(clock, reset_n)
begin
if reset_n = '0' then
counter <= (others => '0');
elsif rising_edge(clock) then
counter <= counter_nxt;
end if;
end process;
counter_nxt <= (others => '0') when (counter = GV_CLOCK_DIV-1) or (enable = '0') else
counter + 1;
clock_out <= '1' when (counter >= GV_CLOCK_DIV/2) and (enable = '1') else
'0';
end architecture rtl; | apache-2.0 | 27043af4238fc487e52f5ed7cc6391b5 | 0.560781 | 3.079235 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/and/myAnd2.vhdl | 1 | 541 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myAnd2 is
port(a: in std_logic; b: in std_logic; s: out std_logic);
end myAnd2;
architecture behavioral of myAnd2 is
component myNand2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myNot
port(a: in std_logic; s: out std_logic);
end component;
signal nandOut: std_logic;
begin
myNand2_1: myNand2 port map(a => a, b => b, s => nandOut);
myNot_1: myNot port map(a => nandOut, s => s);
end behavioral;
| mit | bcee3c307e352d0d39669e3a051f4e71 | 0.639556 | 2.956284 | false | false | false | false |
Fju/LeafySan | src/vhdl/testbench/infrared_model.vhdl | 1 | 5,366 | -----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : UART-Model for Simulation
-- Last update : 28.11.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity infrared_model is
generic (
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
-- file with bytes to be send to fpga
FILE_NAME_COMMAND : string := "ir_command.txt";
-- custom code of ir-sender
CUSTOM_CODE : std_ulogic_vector(15 downto 0) := x"6B86";
SIMULATION : boolean := true
);
port (
-- global signals
end_simulation : in std_ulogic;
-- ir-pin
irda_txd : out std_ulogic
);
end infrared_model;
architecture sim of infrared_model is
constant MAX_NO_OF_BYTES : natural := 128;
-- startbit LOW time: 9.0 ms
constant CV_STARTBIT_LOW_REAL : time := 1 us * 9000;
constant CV_STARTBIT_LOW_SIM : time := SYSTEM_CYCLE_TIME * 90;
-- startbit HIGH time: 4.5 ms
constant CV_STARTBIT_HIGH_REAL : time := 1 us * 4500;
constant CV_STARTBIT_HIGH_SIM : time := SYSTEM_CYCLE_TIME * 45;
-- databit LOW time: 0.6 ms
constant CV_DATA_LOW_REAL : time := 1 us * 600;
constant CV_DATA_LOW_SIM : time := SYSTEM_CYCLE_TIME * 6;
-- databit '0' HIGH time: 0.52 ms
constant CV_DATA0_HIGH_REAL : time := 1 us * 520;
constant CV_DATA0_HIGH_SIM : time := SYSTEM_CYCLE_TIME * 5;
-- databit '1' HIGH time: 1.66 ms
constant CV_DATA1_HIGH_REAL : time := 1 us * 1660;
constant CV_DATA1_HIGH_SIM : time := SYSTEM_CYCLE_TIME * 16;
file file_command : text open read_mode is FILE_NAME_COMMAND;
type bytelist_t is array (0 to MAX_NO_OF_BYTES-1) of std_ulogic_vector(7 downto 0);
begin
-- send data to fpga
ir_send : process
variable commandlist : bytelist_t;
variable active_line : line;
variable neol : boolean := false;
variable data_value : integer;
variable cnt : natural := 0;
begin
-- set line to "no data"
irda_txd <= '1';
-- preload list with undefined
commandlist := (others => (others => 'U'));
-- read preload file
while not endfile(file_command) loop
-- read line
readline(file_command, active_line);
-- loop until end of line
loop
read(active_line, data_value, neol);
exit when not neol;
-- write command to array
commandlist(cnt) := std_ulogic_vector(to_signed(data_value, 8));
-- increment counter
cnt := cnt + 1;
end loop;
end loop;
file_close(file_command);
-- send data to fpga
for i in 0 to MAX_NO_OF_BYTES-1 loop
-- check if byte is valid, else stop
if commandlist(i)(0) /= 'U' then
-- wait some cycles before start
wait for 10*SYSTEM_CYCLE_TIME;
-- ir send procedure
-- start sequence
irda_txd <= '0';
if SIMULATION = false then wait for CV_STARTBIT_LOW_REAL;
else wait for CV_STARTBIT_LOW_SIM;
end if;
irda_txd <= '1';
if SIMULATION = false then wait for CV_STARTBIT_HIGH_REAL;
else wait for CV_STARTBIT_HIGH_SIM;
end if;
-- loop over custom code
for j in 0 to 15 loop
irda_txd <= '0';
if SIMULATION = false then wait for CV_DATA_LOW_REAL;
else wait for CV_DATA_LOW_SIM;
end if;
irda_txd <= '1';
if CUSTOM_CODE(j) = '1' then
if SIMULATION = false then wait for CV_DATA1_HIGH_REAL;
else wait for CV_DATA1_HIGH_SIM;
end if;
else
if SIMULATION = false then wait for CV_DATA0_HIGH_REAL;
else wait for CV_DATA0_HIGH_SIM;
end if;
end if;
end loop;
-- loop over data
for j in 0 to 7 loop
irda_txd <= '0';
if SIMULATION = false then wait for CV_DATA_LOW_REAL;
else wait for CV_DATA_LOW_SIM;
end if;
irda_txd <= '1';
if commandlist(i)(j) = '1' then
if SIMULATION = false then wait for CV_DATA1_HIGH_REAL;
else wait for CV_DATA1_HIGH_SIM;
end if;
else
if SIMULATION = false then wait for CV_DATA0_HIGH_REAL;
else wait for CV_DATA0_HIGH_SIM;
end if;
end if;
end loop;
-- loop over not(data)
for j in 0 to 7 loop
irda_txd <= '0';
if SIMULATION = false then wait for CV_DATA_LOW_REAL;
else wait for CV_DATA_LOW_SIM;
end if;
irda_txd <= '1';
if not(commandlist(i)(j)) = '1' then
if SIMULATION = false then wait for CV_DATA1_HIGH_REAL;
else wait for CV_DATA1_HIGH_SIM;
end if;
else
if SIMULATION = false then wait for CV_DATA0_HIGH_REAL;
else wait for CV_DATA0_HIGH_SIM;
end if;
end if;
end loop;
-- stop bit
irda_txd <= '0';
if SIMULATION = false then wait for CV_DATA_LOW_REAL;
else wait for CV_DATA_LOW_SIM;
end if;
-- idle
irda_txd <= '1';
write(active_line, string'("[IR] Sent "));
write(active_line, to_integer(unsigned(commandlist(i))));
write(active_line, string'(" ("));
write(active_line, to_bitvector(commandlist(i)));
write(active_line, string'(") to FPGA."));
writeline(output, active_line);
-- wait for some cycles before continuing
wait for 20*SYSTEM_CYCLE_TIME;
end if;
end loop;
-- wait forever
wait;
end process ir_send;
end sim; | apache-2.0 | 4acae79ddcc83525ce7b114dd2e83ebf | 0.592434 | 3.035068 | false | false | false | false |
acarrer/altera-de1-mp3-recorder-vhdl | Utils/SYNC_FIFO.vhd | 1 | 1,876 | -- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo SYNC_FIFO.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Gestione FIFO con uguale clock per lettura e scrittura.
-- **********************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library Altera_mf;
use altera_mf.altera_mf_components.all;
entity SYNC_FIFO is
generic (
DATA_WIDTH: integer := 32;
DATA_DEPTH: integer := 128;
ADDR_WIDTH: integer := 7
);
port (
clk: in std_logic;
reset: in std_logic;
write_en: in std_logic;
write_data: in std_logic_vector(DATA_WIDTH downto 1);
read_en: in std_logic;
fifo_is_empty: out std_logic;
fifo_is_full: out std_logic;
words_used: out std_logic_vector(ADDR_WIDTH downto 1);
read_data: out std_logic_vector(DATA_WIDTH downto 1)
);
end SYNC_FIFO;
architecture behaviour of SYNC_FIFO is
begin
Sync_FIFO_Entity : scfifo generic map (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone II",
lpm_numwords => DATA_DEPTH,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => DATA_WIDTH,
lpm_widthu => ADDR_WIDTH,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
port map (
clock => clk,
sclr => reset,
data => write_data,
wrreq => write_en,
rdreq => read_en,
empty => fifo_is_empty,
full => fifo_is_full,
usedw => words_used,
q => read_data,
-- Unused
aclr => OPEN,
almost_empty => OPEN,
almost_full => OPEN
);
end behaviour; | mit | 3f5aa62bcd380363a39eee66df60fb00 | 0.527719 | 3.025806 | false | false | false | false |
mjpatter88/fundamentals | 01-logic_gates/mux/myMux2_tb.vhdl | 1 | 1,797 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity myMux2_tb is
end myMux2_tb;
architecture behavioral of myMux2_tb is
component myMux2
port(a: in std_logic; b: in std_logic; sel: in std_logic; s: out std_logic);
end component;
-- signals used for testing
signal s1: std_logic;
signal s2: std_logic;
signal sel: std_logic;
signal o1: std_logic;
begin
-- component instantiation
myMux2_1: myMux2 port map(a => s1, b => s2, sel => sel, s => o1);
process
begin
s1 <= '0';
s2 <= '0';
sel <= '0';
wait for 1 ns;
assert o1 = '0' report "0,0,0 was not 0" severity error;
s1 <= '0';
s2 <= '1';
sel <= '0';
wait for 1 ns;
assert o1 = '0' report "0,1,0 was not 0" severity error;
s1 <= '1';
s2 <= '0';
sel <= '0';
wait for 1 ns;
assert o1 = '1' report "1,0,0 was not 1" severity error;
s1 <= '1';
s2 <= '1';
sel <= '0';
wait for 1 ns;
assert o1 = '1' report "1,1,0 was not 1" severity error;
s1 <= '0';
s2 <= '0';
sel <= '1';
wait for 1 ns;
assert o1 = '0' report "0,0,1 was not 0" severity error;
s1 <= '0';
s2 <= '1';
sel <= '1';
wait for 1 ns;
assert o1 = '1' report "0,1,1 was not 1" severity error;
s1 <= '1';
s2 <= '0';
sel <= '1';
wait for 1 ns;
assert o1 = '0' report "1,0,1 was not 0" severity error;
s1 <= '1';
s2 <= '1';
sel <= '1';
wait for 1 ns;
assert o1 = '1' report "1,1,1 was not 1" severity error;
assert false report "test complete" severity note;
wait;
end process;
end behavioral;
| mit | 507fd9dc068c66c391a4f6f893310b03 | 0.480801 | 3.163732 | false | false | false | false |
Hyvok/KittLights | kitt_lights_top.vhd | 1 | 1,484 | library ieee;
library work;
use ieee.std_logic_1164.all;
entity kitt_lights_top is
generic
(
LIGHTS_N : positive := 8;
ADVANCE_VAL : positive := 5000000;
PWM_BITS_N : positive := 8;
DECAY_VAL : positive := 52000
);
port
(
clk_in : in std_logic;
reset_in : in std_logic;
lights_out : out std_logic_vector(LIGHTS_N - 1 downto 0)
);
end entity;
architecture rtl of kitt_lights_top is
signal reset : std_logic;
signal lights : std_logic_vector(LIGHTS_N - 1 downto 0);
begin
-- Synchronize reset signal to clock and invert it
sync_reset_p: process(clk_in, reset)
begin
if rising_edge(clk_in) then
if reset_in = '0' then
reset <= '1';
else
reset <= '0';
end if;
end if;
end process;
-- Invert signal for LEDs
lights_out <= not lights;
kitt_lights_p: entity work.kitt_lights(rtl)
generic map
(
LIGHTS_N => LIGHTS_N,
ADVANCE_VAL => ADVANCE_VAL,
PWM_BITS_N => PWM_BITS_N,
DECAY_VAL => DECAY_VAL
)
port map
(
clk => clk_in,
reset => reset,
lights_out => lights
);
end;
| mit | dd09077ca986a87bd5b3901f2210e335 | 0.449461 | 3.925926 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue4/video/kb_rf_fetch.vhd | 2 | 1,447 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:56:33 07/06/2016
-- Design Name:
-- Module Name: kb_rf_fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kb_rf_fetch is port (
kbclk : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
rf : out STD_LOGIC);
end kb_rf_fetch;
architecture Behavioral of kb_rf_fetch is
signal clk_history: STD_LOGIC_VECTOR(1 downto 0);
begin
clk_history_shift: process(kbclk, clk, reset)
begin
if reset = '1' then
clk_history <= "11";
elsif clk'event and clk = '1' then
clk_history(1) <= clk_history(0);
clk_history(0) <= kbclk;
end if;
end process clk_history_shift;
find_rf: process(clk_history)
begin
if clk_history = "10" then
rf <= '1';
else
rf <= '0';
end if;
end process find_rf;
end Behavioral;
| mit | 035b90a02996fc63c5306f2a1706a696 | 0.595024 | 3.334101 | false | false | false | false |
Fju/LeafySan | src/vhdl/modules/calc_lux.vhdl | 1 | 5,165 | ----------------------------------------------------------------------
-- Project : LeafySan
-- Module : Lux Calculation Module
-- Authors : Florian Winkler
-- Lust update : 03.09.2017
-- Description : Calculates and returns lux value according to the value of the two light channels
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity calc_lux is
port(
clock : in std_ulogic;
reset : in std_ulogic;
channel0 : in unsigned(15 downto 0);
channel1 : in unsigned(15 downto 0);
start : in std_ulogic;
busy : out std_ulogic;
lux : out unsigned(15 downto 0)
);
end calc_lux;
architecture rtl of calc_lux is
type state_t is (S_IDLE, S_RATIO, S_SUBSTRACT, S_SHIFT, S_DONE);
signal state, state_nxt : state_t;
-- factor look up table
type ratio_factor_t is record
k : natural;
b : natural;
m : natural;
end record;
type ratio_factor_array is array (natural range <>) of ratio_factor_t;
constant RATIO_FACTORS_LENGTH : natural := 7;
constant RATIO_FACTORS : ratio_factor_array(0 to RATIO_FACTORS_LENGTH - 1) := (
-- k, b, m
(64, 498, 446), -- 0x0040 , 0x01f2 , 0x01be
(128, 532, 721), -- 0x0080 , 0x0214 , 0x02d1
(192, 575, 891), -- 0x00c0 , 0x023f , 0x037b
(256, 624, 1022), -- 0x0100 , 0x0270 , 0x03fe
(312, 367, 508), -- 0x0138 , 0x016f , 0x01fc
(410, 210, 251), -- 0x019a , 0x00d2 , 0x00fb
(666, 24, 18) -- 0x029a , 0x0018 , 0x0012
);
signal b, b_nxt : unsigned(10 downto 0);
signal m, m_nxt : unsigned(10 downto 0);
signal l, l_nxt : unsigned(15 downto 0);
signal ch0, ch0_nxt : unsigned(34 downto 0);
signal ch1, ch1_nxt : unsigned(34 downto 0);
signal temp, temp_nxt : signed(34 downto 0);
begin
-- sequential process
process(clock, reset)
begin
if reset = '1' then
state <= S_IDLE;
b <= (others => '0');
m <= (others => '0');
l <= (others => '0');
ch0 <= (others => '0');
ch1 <= (others => '0');
temp <= (others => '0');
elsif rising_edge(clock) then
state <= state_nxt;
b <= b_nxt;
m <= m_nxt;
l <= l_nxt;
ch0 <= ch0_nxt;
ch1 <= ch1_nxt;
temp <= temp_nxt;
end if;
end process;
process(state, start, b, m, l, temp, ch0, ch1, channel0, channel1)
variable x : unsigned(33 downto 0) := (others => '0');
begin
-- hold previous values by default
state_nxt <= state;
b_nxt <= b;
m_nxt <= m;
l_nxt <= l;
ch0_nxt <= ch0;
ch1_nxt <= ch1;
temp_nxt <= temp;
-- default assignments for output signals;
busy <= '1';
lux <= l;
case state is
when S_IDLE =>
if start = '1' then
state_nxt <= S_RATIO;
ch0_nxt <= resize(shift_right(resize(channel0, 31) * 4071, 10), ch0'length);
ch1_nxt <= resize(shift_right(resize(channel1, 31) * 4071, 10), ch1'length);
end if;
when S_RATIO =>
x := resize(ch1 & "000000000", x'length); -- shift ch1 left by 9 bits
-- find coefficients based on ratio of ch1/ch0
-- to avoid division `x/ch0 <= k` was changed to `x <= ch0 * k`
if x >= 0 and x <= RATIO_FACTORS(0).k * ch0 then
b_nxt <= to_unsigned(RATIO_FACTORS(0).b, b'length);
m_nxt <= to_unsigned(RATIO_FACTORS(0).m, m'length);
elsif x <= RATIO_FACTORS(1).k * ch0 then
b_nxt <= to_unsigned(RATIO_FACTORS(1).b, b'length);
m_nxt <= to_unsigned(RATIO_FACTORS(1).m, m'length);
elsif x <= RATIO_FACTORS(2).k * ch0 then
b_nxt <= to_unsigned(RATIO_FACTORS(2).b, b'length);
m_nxt <= to_unsigned(RATIO_FACTORS(2).m, m'length);
elsif x <= RATIO_FACTORS(3).k * ch0 then
b_nxt <= to_unsigned(RATIO_FACTORS(3).b, b'length);
m_nxt <= to_unsigned(RATIO_FACTORS(3).m, m'length);
elsif x <= RATIO_FACTORS(4).k * ch0 then
b_nxt <= to_unsigned(RATIO_FACTORS(4).b, b'length);
m_nxt <= to_unsigned(RATIO_FACTORS(4).m, m'length);
elsif x <= RATIO_FACTORS(5).k * ch0 then
b_nxt <= to_unsigned(RATIO_FACTORS(5).b, b'length);
m_nxt <= to_unsigned(RATIO_FACTORS(5).m, m'length);
elsif x <= RATIO_FACTORS(6).k * ch0 then
b_nxt <= to_unsigned(RATIO_FACTORS(6).b, b'length);
m_nxt <= to_unsigned(RATIO_FACTORS(6).m, m'length);
else
b_nxt <= to_unsigned(0, b'length);
m_nxt <= to_unsigned(0, m'length);
end if;
state_nxt <= S_SUBSTRACT;
when S_SUBSTRACT =>
-- substract both channels with their coefficients
temp_nxt <= signed(resize(ch0 * b, temp'length)) - signed(resize(ch1 * m, temp'length));
state_nxt <= S_SHIFT;
when S_SHIFT =>
-- no values below zero
if temp > to_signed(0, temp'length) then
-- shift right by 14 bits
-- add 8192 (2^13) to ceil integer value (forced round up)
l_nxt <= unsigned(resize(shift_right(temp + 8192, 14), l'length));
else
l_nxt <= (others => '0');
end if;
state_nxt <= S_DONE;
when S_DONE =>
-- finished calculation, set busy to '0'
busy <= '0';
if start = '0' then
-- received acknowledgement signal
-- go back to idle state
state_nxt <= S_IDLE;
end if;
end case;
end process;
end rtl;
| apache-2.0 | d6cde1082cc0d2189c9c16b7ca98831b | 0.585092 | 2.63386 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue4/video/project_main.vhd | 1 | 4,056 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity project_main is
Port ( video: out STD_LOGIC_VECTOR(11 downto 0);
hsync: out STD_LOGIC;
vsync: out STD_LOGIC;
segments: out STD_LOGIC_VECTOR(14 downto 0);
clk: in STD_LOGIC;
kbclk: in STD_LOGIC;
kbdata: in STD_LOGIC;
reset: in STD_LOGIC;
program_select: in STD_LOGIC;
dbg: out STD_LOGIC);
end project_main;
architecture Behavioral of project_main is
component video_timing is port(
clk: in STD_LOGIC;
x: out integer range 0 to 1440-1;
y: out integer range 0 to 900-1;
hsync: out std_logic;
vsync: out std_logic;
video_enable: out std_logic;
logic_enable: out std_logic);
end component;
component keyboard_in is port (
clk : in STD_LOGIC;
kbclk : in STD_LOGIC;
kbdata : in STD_LOGIC;
reset : in STD_LOGIC;
ready : out STD_LOGIC;
scancode : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component segment_out is port (
clk : in STD_LOGIC;
ready : in STD_LOGIC;
reset : in STD_LOGIC;
scancode : in STD_LOGIC_VECTOR(7 downto 0);
segments : out STD_LOGIC_VECTOR(14 downto 0);
anyKeyDown : out STD_LOGIC);
end component;
component twister_logic is port(
clk: in std_logic;
key_down: in std_logic;
enable: in std_logic;
color: buffer integer range 0 to 3);
end component;
component twister_output is port(
clk: in std_logic;
color: in integer range 0 to 3;
video: out std_logic_vector(11 downto 0));
end component;
component flappy_logic is port (
clk: in std_logic;
enable: in std_logic;
key_down: in std_logic;
random: in std_logic_vector(3 downto 0);
bird_y: buffer integer range 0 to 900-1 := 300;
obstacles: buffer std_logic_vector(15 downto 0);
offset: buffer integer range 0 to 358;
game_over: buffer std_logic := '1');
end component;
component flappy_output is port(
clk : in std_logic;
x : in integer range 0 to 1440-1;
y : in integer range 0 to 900-1;
bird_y : in integer range 0 to 900-1;
obstacles: in std_logic_vector(15 downto 0);
offset: in integer range 0 to 358;
game_over: in std_logic;
video : out std_logic_vector (11 downto 0));
end component;
component random_generator is port (
clk: in std_logic;
key_down: in std_logic;
random: buffer std_logic_vector(3 downto 0));
end component;
signal ready : STD_LOGIC;
signal scancode: STD_LOGIC_VECTOR(7 downto 0);
signal key_down: std_logic;
signal video_enable: std_logic;
signal logic_enable: std_logic;
signal twister_color: integer range 0 to 3;
signal twister_video: std_logic_vector(11 downto 0);
signal flappy_bird_y: integer range 0 to 900-1;
signal flappy_obstacles: std_logic_vector(15 downto 0);
signal flappy_offset: integer range 0 to 358;
signal flappy_game_over: std_logic;
signal flappy_video: std_logic_vector(11 downto 0);
signal random: std_logic_vector(3 downto 0);
signal x: integer range 0 to 1440-1;
signal y: integer range 0 to 900-1;
begin
keyboard_in0: keyboard_in port map (clk, kbclk, kbdata, reset, ready, scancode);
segment_out0: segment_out port map (clk, ready, reset, scancode, segments, key_down);
vt: video_timing port map (clk, x, y, hsync, vsync, video_enable, logic_enable);
tl: twister_logic port map (clk, key_down, logic_enable, twister_color);
tp: twister_output port map (clk, twister_color, twister_video);
fl: flappy_logic port map (clk, logic_enable, key_down, random, flappy_bird_y, flappy_obstacles, flappy_offset, flappy_game_over);
fp: flappy_output port map (clk, x, y, flappy_bird_y, flappy_obstacles, flappy_offset, flappy_game_over, flappy_video);
rg: random_generator port map (clk, key_down, random);
process(clk)
begin
if clk'event and clk = '1' then
if video_enable = '1' then
if program_select = '1' then
video <= twister_video;
else
video <= flappy_video;
end if;
else
video <= "000000000000";
end if;
end if;
end process;
dbg <= key_down;
end Behavioral;
| mit | 4e0c18c920e7af8787e5536411262341 | 0.678008 | 2.962747 | false | false | false | false |
jchromik/hpi-vhdl-2016 | pue2/Fanoe/Fanoe.vhd | 1 | 3,999 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:21:22 06/16/2016
-- Design Name:
-- Module Name: Fanoe - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Fanoe is
Port ( x : in STD_LOGIC;
Reset : in STD_LOGIC;
c_V : in STD_LOGIC;
c_R : in STD_LOGIC;
g_me : out STD_LOGIC;
y1_me : out STD_LOGIC;
y2_me : out STD_LOGIC;
g_mo : out STD_LOGIC;
y1_mo : out STD_LOGIC;
y2_mo : out STD_LOGIC);
end Fanoe;
architecture Behavioral of Fanoe is
type Zustaende_me is (S1_me, S2_me, S3_me); -- Aufzählungstyp
type Zustaende_mo is (S1_mo, S2_mo, S3_mo, S4_mo, S5_mo, S6_mo, S7_mo);
signal S_me, S_folge_me : Zustaende_me;
signal S_mo, S_folge_mo : Zustaende_mo;
signal Y_me, Y_mo : std_logic_vector (2 downto 0);
signal Q_int, nQ_int: STD_LOGIC;
signal x_sync: STD_LOGIC;
begin
DFF_x_buffer: process (Q_int, x, Reset)
begin
if Reset = '1' then
x_sync <= '0';
elsif Q_int'event and Q_int = '1' then
x_sync <= x;
else
x_sync <= x_sync;
end if;
end process DFF_x_buffer;
RSFF_clock: process (c_V, c_R)
begin
nQ_int <= c_V nor Q_int;
Q_int <= c_R nor nQ_int;
end process RSFF_clock;
-- MEALY
Delta_Lambda_me: process (x_sync,S_me)
begin
case S_me is
when S1_me =>
if x_sync = '0' then
S_folge_me <= S1_me;
Y_me <= "001" ;
else
S_folge_me <= S2_me;
Y_me <= "--0" ;
end if;
when S2_me =>
if x_sync = '0' then
S_folge_me <= S1_me;
Y_me <= "011" ;
else
S_folge_me <= S3_me;
Y_me <= "--0" ;
end if;
when S3_me =>
if x_sync = '0' then
S_folge_me <= S1_me;
Y_me <= "101" ;
else
S_folge_me <= S1_me;
Y_me <= "111" ;
end if;
end case;
end process Delta_Lambda_me;
RK_me: process (Q_int, Reset)
begin
if Reset = '1' then
S_me <= S1_me;
elsif Q_int = '1' and Q_int'event then
S_me <= S_folge_me;
end if;
end process RK_me;
y2_me <= Y_me(2);
y1_me <= Y_me(1);
g_me <= Y_me(0);
-- Moore
Delta_mo: process(x_sync, S_mo)
begin
case S_mo is
when S1_mo =>
if x_sync = '0' then S_folge_mo <= S2_mo;
else S_folge_mo <= S3_mo; end if;
when S2_mo =>
if x_sync = '0' then S_folge_mo <= S2_mo;
else S_folge_mo <= S3_mo; end if;
when S3_mo =>
if x_sync = '0' then S_folge_mo <= S4_mo;
else S_folge_mo <= S5_mo; end if;
when S4_mo =>
if x_sync = '0' then S_folge_mo <= S2_mo;
else S_folge_mo <= S3_mo; end if;
when S5_mo =>
if x_sync = '0' then S_folge_mo <= S6_mo;
else S_folge_mo <= S7_mo; end if;
when S6_mo =>
if x_sync = '0' then S_folge_mo <= S2_mo;
else S_folge_mo <= S3_mo; end if;
when S7_mo =>
if x_sync = '0' then S_folge_mo <= S2_mo;
else S_folge_mo <= S3_mo; end if;
end case;
end process Delta_mo;
RK_mo: process (Q_int, Reset)
begin
if Reset = '1' then
S_mo <= S1_mo;
elsif Q_int = '1' and Q_int'event then
S_mo <= S_folge_mo;
end if;
end process RK_mo;
My_mo: process (S_mo)
begin
case S_mo is
when S2_mo => Y_mo <= "001";
when S4_mo => Y_mo <= "011";
when S6_mo => Y_mo <= "101";
when S7_mo => Y_mo <= "111";
when others => Y_mo <= "--0";
end case;
end process My_mo;
y2_mo <= Y_mo(2);
y1_mo <= Y_mo(1);
g_mo <= Y_mo(0);
end Behavioral;
| mit | f97910297378f5856c36dee1d719aa97 | 0.534767 | 2.437805 | false | false | false | false |
Fju/LeafySan | src/vhdl/examples/invent_a_chip_audio_ir_to_gain.vhdl | 1 | 14,926 | ----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Jan Dürre
-- Year : 2013
-- Description : This example uses the ir-interface to in- or decrease
-- a volume factor to adjust the volume of audio-samples.
-- It is also possible to mute the audio. Two independent
-- FSMs are required, since the lcd is too slow for 44,1kHz
-- sampling rate.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register for audio control
type state_audio_t is (S_INIT, S_WAIT_SAMPLE, S_SAMPLE_READ, S_WRITE_SAMPLE_LEFT, S_WRITE_SAMPLE_RIGHT, S_WRITE_CONFIG);
signal state_audio, state_audio_nxt : state_audio_t;
-- state register for lcd control
type state_lcd_t is (S_WAIT_LCD, S_PRINT_CHARACTERS, S_WAIT_FOR_NEW_GAIN);
signal state_lcd, state_lcd_nxt : state_lcd_t;
-- register to save audio-sample
signal sample, sample_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
-- register to save the current volume_factor
signal vol_factor, vol_factor_nxt : unsigned(7 downto 0);
signal vol_mute, vol_mute_nxt : std_ulogic;
-- signals to communicate between fsms
signal lcd_refresh, lcd_refresh_nxt : std_ulogic;
signal lcd_refresh_ack : std_ulogic;
-- array of every single character to print out to the lcd
signal lcd_cmds, lcd_cmds_nxt : lcd_commands_t(0 to 21);
-- counter
signal char_count, char_count_nxt : unsigned(to_log2(lcd_cmds'length)-1 downto 0);
begin
-- sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
state_audio <= S_INIT;
sample <= (others => '0');
vol_factor <= to_unsigned(130, vol_factor'length);
vol_mute <= '0';
lcd_refresh <= '0';
state_lcd <= S_WAIT_LCD;
lcd_cmds <= lcd_cmd(lcd_cursor_pos(0, 0) & asciitext("Volume: XXX%") & lcd_cursor_pos(1, 0) & asciitext("Mute off"));
char_count <= (others => '0');
elsif rising_edge(clock) then
state_audio <= state_audio_nxt;
sample <= sample_nxt;
vol_factor <= vol_factor_nxt;
vol_mute <= vol_mute_nxt;
lcd_refresh <= lcd_refresh_nxt;
state_lcd <= state_lcd_nxt;
lcd_cmds <= lcd_cmds_nxt;
char_count <= char_count_nxt;
end if;
end process;
-- audio data-path (combinational process contains logic only)
process(state_audio, state_lcd, key, ir_din, ir_irq_rx, audio_din, audio_irq_left, audio_irq_right, lcd_refresh, lcd_refresh_ack, vol_factor, vol_mute, sample, switch)
begin
-- default assignment
-- leds
led_green <= (others => '0');
-- infrared interface
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
-- audio interface
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
-- communication between fsms
lcd_refresh_nxt <= lcd_refresh;
-- hold previous values of all registers
state_audio_nxt <= state_audio;
sample_nxt <= sample;
vol_factor_nxt <= vol_factor;
vol_mute_nxt <= vol_mute;
-- reset lcd_refresh if lcd-fsm acks request
if lcd_refresh_ack = '1' then
lcd_refresh_nxt <= '0';
end if;
-- audio data-path
case state_audio is
-- initial state
when S_INIT =>
led_green(0) <= '1';
-- wait for key 0 to start work
if key(0) = '1' then
-- next state
state_audio_nxt <= S_WAIT_SAMPLE;
-- write init factor to lcd
lcd_refresh_nxt <= '1';
end if;
-- wait for audio-interrupt signals to indicate new audio-sample
when S_WAIT_SAMPLE =>
led_green(1) <= '1';
-- new ir command received
if ir_irq_rx = '1' then
-- acknowledge the ir-interrupt
ir_ack_rx <= '1';
-- select the ir-interface
ir_cs <= '1';
-- set address for recevied ir data (button code)
ir_addr <= CV_ADDR_IR_DATA;
-- compare the received code with the codes for 'Button Volume Up', 'Button Volume Down' or 'Button Mute'
-- all other buttons will be ignored
-- if the recevied code equals the code for 'Button Volume Up' and the current volume is not the max. value (255)
if ir_din(7 downto 0) = C_IR_BUTTON_VOLUME_UP and vol_factor /= 255 then
-- increase the volume by the value of 5
vol_factor_nxt <= vol_factor + 5;
-- initiate rewrite of lcd display
lcd_refresh_nxt <= '1';
-- if the recevied code equals the code for 'Button Volume Down' and the current volume is not the min. value (0)
elsif ir_din(7 downto 0) = C_IR_BUTTON_VOLUME_DOWN and vol_factor /= 0 then
-- decrease the volume by the value of 5
vol_factor_nxt <= vol_factor - 5;
-- initiate rewrite of lcd display
lcd_refresh_nxt <= '1';
-- if the recevied code equals the code for 'Button Mute'
elsif ir_din(7 downto 0) = C_IR_BUTTON_MUTE then
-- toggle the one bit mute register
vol_mute_nxt <= not vol_mute;
-- initiate rewrite of lcd display
lcd_refresh_nxt <= '1';
end if;
end if;
-- new audio sample on left or right channel detected
if (audio_irq_left = '1') or (audio_irq_right = '1') then
-- start reading audio-value
state_audio_nxt <= S_SAMPLE_READ;
end if;
-- read audio value
when S_SAMPLE_READ =>
led_green(2) <= '1';
-- choose correct audio channel
if audio_irq_left = '1' then
-- chip select for audio-interface
audio_cs <= '1';
-- read mode
audio_wr <= '0';
-- acknowledge interrupt
audio_ack_left <= '1';
-- set address for left channel
audio_addr <= CV_ADDR_AUDIO_LEFT_IN;
-- save sample to register
sample_nxt <= audio_din;
-- next state
state_audio_nxt <= S_WRITE_SAMPLE_LEFT;
end if;
if audio_irq_right = '1' then
-- chip select for audio-interface
audio_cs <= '1';
-- read mode
audio_wr <= '0';
-- acknowledge interrupt
audio_ack_right <= '1';
-- set address for right channel
audio_addr <= CV_ADDR_AUDIO_RIGHT_IN;
-- save sample to register
sample_nxt <= audio_din;
-- next state
state_audio_nxt <= S_WRITE_SAMPLE_RIGHT;
end if;
-- write new sample to left channel
when S_WRITE_SAMPLE_LEFT =>
led_green(5) <= '1';
-- chip select for audio-interface
audio_cs <= '1';
-- write mode
audio_wr <= '1';
-- set address for left channel
audio_addr <= CV_ADDR_AUDIO_LEFT_OUT;
-- if the mute is not enabled, output the audio-sample multiplied with the volume factor
if vol_mute = '0' then
-- write sample * gain-factor to audio-interface
audio_dout <= std_ulogic_vector(resize(shift_right(signed(sample) * signed('0' & vol_factor), 7), audio_dout'length));
-- else output 0-sample
else
audio_dout <= (others => '0');
end if;
-- write config to acodec
state_audio_nxt <= S_WRITE_CONFIG;
-- write new sample to right channel
when S_WRITE_SAMPLE_RIGHT =>
led_green(6) <= '1';
-- chip select for audio-interface
audio_cs <= '1';
-- write mode
audio_wr <= '1';
-- set address for right channel
audio_addr <= CV_ADDR_AUDIO_RIGHT_OUT;
-- if the mute is not enabled, output the audio-sample multiplied with the volume factor
if vol_mute = '0' then
-- write sample * gain-factor to audio-interface
audio_dout <= std_ulogic_vector(resize(shift_right(signed(sample) * signed('0' & vol_factor), 7), audio_dout'length));
-- else output 0-sample
else
audio_dout <= (others => '0');
end if;
-- write config to acodec
state_audio_nxt <= S_WRITE_CONFIG;
when S_WRITE_CONFIG =>
led_green(7) <= '1';
-- chip select for audio-interface
audio_cs <= '1';
-- write mode
audio_wr <= '1';
-- set address for config register
audio_addr <= CV_ADDR_AUDIO_CONFIG;
-- set mic boost & in-select
audio_dout <= "00000000000000" & switch(1) & switch(0);
-- back to wait-state
state_audio_nxt <= S_WAIT_SAMPLE;
end case;
end process;
-- lcd control (combinational process contains logic only)
process(state_lcd, lcd_cmds, char_count, lcd_din, lcd_irq_rdy, lcd_refresh, vol_factor, vol_mute)
variable bcd_value : unsigned(11 downto 0) := (others => '0');
variable vol_recalc : std_ulogic_vector(11 downto 0) := (others => '0');
begin
-- default assignment
-- leds
led_red <= (others => '0');
-- lcd interface
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
-- communication between FSMs
lcd_refresh_ack <= '0';
--registers
state_lcd_nxt <= state_lcd;
lcd_cmds_nxt <= lcd_cmds;
char_count_nxt <= char_count;
-- second state machine to generate output on lcd-screen
case state_lcd is
-- wait for lcd-interface to be 'not busy' / finished writing old commands to lcd
when S_WAIT_LCD =>
led_red(0) <= '1';
-- chip select for lcd-interface
lcd_cs <= '1';
-- read mode
lcd_wr <= '0';
-- set address for status
lcd_addr <= CV_ADDR_LCD_STATUS;
-- start printing characters
if lcd_din(0) = '0' then
state_lcd_nxt <= S_PRINT_CHARACTERS;
end if;
-- send characters to lcd-interface
when S_PRINT_CHARACTERS =>
led_red(1) <= '1';
-- lcd ready for data
if lcd_irq_rdy = '1' then
-- chip select for lcd-interface
lcd_cs <= '1';
-- write mode
lcd_wr <= '1';
-- set address for data register of lcd
lcd_addr <= CV_ADDR_LCD_DATA;
-- select character from lcd-commands-array
lcd_dout(7 downto 0) <= lcd_cmds(to_integer(char_count));
-- decide if every character has been sent
if char_count = lcd_cmds'length-1 then
state_lcd_nxt <= S_WAIT_FOR_NEW_GAIN;
-- continue sending characters to lcd-interface
else
char_count_nxt <= char_count + 1;
end if;
end if;
when S_WAIT_FOR_NEW_GAIN =>
led_red(2) <= '1';
-- write new value, only when adc value has changed
if lcd_refresh = '1' then
-- ack refresh request
lcd_refresh_ack <= '1';
-- calculate gain-value
vol_recalc := std_ulogic_vector(resize(shift_right(vol_factor * 200,8), vol_recalc'length));
bcd_value := unsigned(to_bcd(vol_recalc, 3));
-- generate lcd-commands for the first row of the lcd
lcd_cmds_nxt(0 to 12) <= lcd_cmd(lcd_cursor_pos(0, 0) & asciitext("Volume: ") & ascii(bcd_value(11 downto 8)) & ascii(bcd_value(7 downto 4)) & ascii(bcd_value(3 downto 0)) & asciitext("%"));
-- generate lcd-commands for the secondt row of the lcd
-- dependent on the mute register a slightly different text is written to the lcd-commands
if vol_mute = '1' then
lcd_cmds_nxt(13 to 21) <= lcd_cmd(lcd_cursor_pos(1, 0) & asciitext("Mute on "));
else
lcd_cmds_nxt(13 to 21) <= lcd_cmd(lcd_cursor_pos(1, 0) & asciitext("Mute off"));
end if;
-- reset char counter
char_count_nxt <= (others => '0');
-- start writing to lcd
state_lcd_nxt <= S_WAIT_LCD;
end if;
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl; | apache-2.0 | f168329ab74cdb4cd28de13c6458133e | 0.60532 | 2.912959 | false | false | false | false |
Fju/LeafySan | src/vhdl/testbench/acodec_model.vhdl | 1 | 8,314 | -------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Simulation Model for WM8731
-- Author : Jan Duerre
-- Last update : 02.09.2014
-- Description : This module provides samples over I2S-protocol.
-- Samples are read from a file. The samples are
-- read from file as pairs of integer-numbers,
-- alternating for the left and the right channel.
-- Correct I2C communication is ack'ed but ignored.
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity acodec_model is
generic (
SAMPLE_WIDTH : natural := 16;
SAMPLE_RATE : natural := 44100;
SAMPLE_FILE : string := "audio_samples.txt"
);
port (
-- acodec signals
aud_xclk : in std_ulogic;
aud_bclk : out std_ulogic;
aud_adc_lrck : out std_ulogic;
aud_adc_dat : out std_ulogic;
aud_dac_lrck : out std_ulogic;
aud_dac_dat : in std_ulogic;
i2c_sdat : inout std_logic;
i2c_sclk : in std_logic
);
end acodec_model;
architecture rtl of acodec_model is
constant WM8731_SLAVE_ADDR : std_ulogic_vector(6 downto 0) := "0011010";
constant AUDIO_SAMPLE_TIME : time := 1 us * 1000000/SAMPLE_RATE;
signal aud_adc_dat_left : std_ulogic;
signal aud_adc_dat_right : std_ulogic;
signal aud_adc_lrck_int : std_ulogic := '1';
signal aud_dac_lrck_int : std_ulogic := '1';
-- internal data-array for preloaded samples from file
constant MAX_NUMBER_OF_SAMPLES : natural := 256;
signal number_of_samples : natural;
file sample_f : text open read_mode is SAMPLE_FILE;
type sample_data_t is array (0 to MAX_NUMBER_OF_SAMPLES-1) of std_ulogic_vector(SAMPLE_WIDTH-1 downto 0);
signal sample_data_left : sample_data_t;
signal sample_data_right : sample_data_t;
begin
-- preload samples from file
process
variable active_line : line;
variable neol : boolean := false;
variable sample_value : integer := 0;
variable cnt : natural := 0;
begin
-- preset size
number_of_samples <= 0;
-- prefill array with undefined
sample_data_left <= (others => (others => 'U'));
sample_data_right <= (others => (others => 'U'));
-- read preload file
while ((not endfile(sample_f)) and (cnt /= MAX_NUMBER_OF_SAMPLES)) loop
-- read line
readline(sample_f, active_line);
-- loop until end of line
loop
-- left:
-- read integer from line
read(active_line, sample_value, neol);
-- exit when line has ended
exit when not neol;
-- write data to array
sample_data_left(cnt) <= std_ulogic_vector(to_signed(sample_value, SAMPLE_WIDTH));
-- right:
-- read integer from line
read(active_line, sample_value, neol);
-- exit when line has ended
exit when not neol;
-- write data to array
sample_data_right(cnt) <= std_ulogic_vector(to_signed(sample_value, SAMPLE_WIDTH));
-- increment counter
cnt := cnt + 1;
-- chancel when sample array is already full
exit when cnt = MAX_NUMBER_OF_SAMPLES;
end loop;
end loop;
-- update size
number_of_samples <= cnt;
-- close file and sleep
file_close(sample_f);
wait;
end process;
aud_bclk <= aud_xclk;
aud_adc_lrck <= aud_adc_lrck_int;
aud_dac_lrck <= aud_dac_lrck_int;
aud_adc_dat <= aud_adc_dat_left or aud_adc_dat_right;
-- generate left / right channel signal
process
begin
wait until aud_xclk = '1';
wait until aud_xclk = '0';
loop
aud_adc_lrck_int <= '1';
aud_dac_lrck_int <= '1';
wait for AUDIO_SAMPLE_TIME/2;
wait until aud_xclk = '0';
aud_adc_lrck_int <= '0';
aud_dac_lrck_int <= '0';
wait for AUDIO_SAMPLE_TIME/2;
wait until aud_xclk = '0';
end loop;
end process;
-- left channel
process
variable sample_ptr : integer := 0;
begin
aud_adc_dat_left <= '0';
wait until aud_xclk = '1';
wait until aud_xclk = '0';
-- loop forever
loop
aud_adc_dat_left <= '0';
-- wait for change of channel and synchronize with audio-clock (left channel)
wait until (aud_adc_lrck_int = '0') and (aud_xclk = '0');
-- pass first aud_xclk
wait until rising_edge(aud_xclk);
wait until falling_edge(aud_xclk);
for i in SAMPLE_WIDTH-1 downto 0 loop
aud_adc_dat_left <= std_ulogic(sample_data_left(sample_ptr)(i));
wait until rising_edge(aud_xclk);
wait until falling_edge(aud_xclk);
end loop;
aud_adc_dat_left <= '0';
-- inc data pointer
if sample_ptr = number_of_samples - 1 then
sample_ptr := 0;
else
sample_ptr := sample_ptr + 1;
end if;
-- wait for change of channel (if still in left channel)
if aud_adc_lrck_int = '0' then
wait until (aud_adc_lrck_int = '1');
end if;
end loop;
end process;
-- right channel
process
variable sample_ptr : integer := 0;
begin
aud_adc_dat_right <= '0';
wait until aud_xclk = '1';
wait until aud_xclk = '0';
-- start with left channel: wait for that to finish
wait until (aud_adc_lrck_int = '0');
-- loop forever
loop
aud_adc_dat_right <= '0';
-- wait for change of channel and synchronize with audio-clock (right channel)
wait until (aud_adc_lrck_int = '1') and (aud_xclk = '0');
-- pass first aud_xclk
wait until rising_edge(aud_xclk);
wait until falling_edge(aud_xclk);
for i in SAMPLE_WIDTH-1 downto 0 loop
aud_adc_dat_right <= std_ulogic(sample_data_right(sample_ptr)(i));
wait until rising_edge(aud_xclk);
wait until falling_edge(aud_xclk);
end loop;
aud_adc_dat_right <= '0';
-- inc data pointer
if sample_ptr = number_of_samples - 1 then
sample_ptr := 0;
else
sample_ptr := sample_ptr + 1;
end if;
-- wait for change of channel (if still in right channel)
if aud_adc_lrck_int = '1' then
wait until (aud_adc_lrck_int = '0');
end if;
end loop;
end process;
-- i2c slave: registers can only be written / reading is not supported
process
variable slave_addr : std_ulogic_vector(6 downto 0) := (others => '0');
begin
i2c_sdat <= 'Z';
-- loop forever
loop
-- start condition
wait until (falling_edge(i2c_sdat) and (i2c_sclk = '1'));
-- slave addr
for i in 6 downto 0 loop
wait until rising_edge(i2c_sclk);
slave_addr(i) := i2c_sdat;
wait for 1 ns;
end loop;
-- r/w bit
wait until rising_edge(i2c_sclk);
-- correct slave address
if slave_addr = WM8731_SLAVE_ADDR then
-- write
if i2c_sdat = '0' then
-- ack
wait until falling_edge(i2c_sclk);
i2c_sdat <= '0';
-- wait one i2c-cycle
wait until rising_edge(i2c_sclk);
wait until falling_edge(i2c_sclk);
i2c_sdat <= 'Z';
-- expecting 16 bit (2 byte)
-- first byte
for i in 0 to 7 loop
wait until rising_edge(i2c_sclk);
wait for 1 ns;
end loop;
-- ack
wait until falling_edge(i2c_sclk);
i2c_sdat <= '0';
-- wait one i2c-cycle
wait until rising_edge(i2c_sclk);
wait until falling_edge(i2c_sclk);
i2c_sdat <= 'Z';
-- second byte
for i in 0 to 7 loop
wait until rising_edge(i2c_sclk);
wait for 1 ns;
end loop;
-- ack
wait until falling_edge(i2c_sclk);
i2c_sdat <= '0';
-- wait one i2c-cycle
wait until rising_edge(i2c_sclk);
wait until falling_edge(i2c_sclk);
i2c_sdat <= 'Z';
-- stop condition
wait until (rising_edge(i2c_sdat) and (i2c_sclk = '1'));
-- read
else
-- don't ack
wait until falling_edge(i2c_sclk);
i2c_sdat <= 'Z';
-- wait one i2c-cycle
wait until rising_edge(i2c_sclk);
wait until falling_edge(i2c_sclk);
i2c_sdat <= 'Z';
-- stop condition
wait until (rising_edge(i2c_sdat) and (i2c_sclk = '1'));
end if;
end if;
end loop;
end process;
end architecture rtl;
| apache-2.0 | 4c58de0b27a1fea6d02f61264ec395d3 | 0.582752 | 3.035414 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/packages/vhdl_source/tl_file_io_pkg.vhd | 1 | 9,393 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : file io package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: File IO routines
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
package tl_file_io_pkg is
type t_slv8_array is array(natural range <>) of std_logic_vector(7 downto 0);
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character);
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector);
procedure read_hex_file_to_array (file myfile : text; array_size : integer; result : inout t_slv8_array);
-- handling binary files
type t_binary_file is file of integer;
type t_binary_file_rec is record
offset : integer range 0 to 4;
long_vec : std_logic_vector(31 downto 0);
end record;
procedure init_record(rec : inout t_binary_file_rec);
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec);
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec);
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec);
end;
package body tl_file_io_pkg is
procedure get_char_from_file(file my_file : text; my_line : inout line; file_end : out boolean; hex : out character) is
variable good : boolean := false;
variable stop : boolean := false;
begin
while not(good) loop
READ(my_line, hex, good);
if not(good) then
if ENDFILE(my_file) then
stop := true;
hex := '1';
return;
end if;
READLINE(my_file, my_line);
end if;
end loop;
file_end := stop;
end get_char_from_file;
procedure get_byte_from_file(file my_file : text; my_line : inout line; file_end : out boolean; dat : out std_logic_vector) is
variable hex : character;
variable data : std_logic_vector(7 downto 0);
variable stop : boolean := false;
begin
data := X"00";
l_1 : loop
get_char_from_file(my_file, my_line, stop, hex);
if stop or is_hex_char(hex) then
exit l_1;
end if;
end loop l_1;
data(3 downto 0) := hex_to_nibble(hex);
-- see if we can read another good hex char
get_char_from_file(my_file, my_line, stop, hex);
if not(stop) and is_hex_char(hex) then
data(7 downto 4) := data(3 downto 0);
data(3 downto 0) := hex_to_nibble(hex);
end if;
file_end := stop;
dat := data;
end get_byte_from_file;
procedure read_hex_file_to_array (
file myfile : text;
array_size : integer;
result : inout t_slv8_array)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : std_logic_vector(7 downto 0);
variable sum : unsigned(7 downto 0);
variable rectype : std_logic_vector(7 downto 0);
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
variable out_array: t_slv8_array(0 to array_size-1) := (others => (others => '0'));
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
exit outer;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
out_array(to_integer(addr)) := data;
addr := addr + 1;
end loop;
when X"01" => -- end of file record
exit outer;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
exit outer;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
result := out_array;
end read_hex_file_to_array;
procedure init_record(rec : inout t_binary_file_rec) is
begin
rec.offset := 0;
rec.long_vec := (others => '0');
end procedure;
procedure read_byte(file my_file : t_binary_file; byte : out std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset = 0 then
read(my_file, i);
rec.long_vec := std_logic_vector(to_signed(i, 32));
--report "Long vec = " & hstr(rec.long_vec);
end if;
byte := rec.long_vec(7 downto 0);
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
if rec.offset = 3 then
rec.offset := 0;
else
rec.offset := rec.offset + 1;
end if;
end procedure;
procedure write_byte(file my_file : t_binary_file; byte : in std_logic_vector; rec : inout t_binary_file_rec) is
variable i : integer;
begin
rec.long_vec(31 downto 24) := byte;
if rec.offset = 3 then
i := to_integer(signed(rec.long_vec));
write(my_file, i);
rec.offset := 0;
else
rec.offset := rec.offset + 1;
rec.long_vec := "00000000" & rec.long_vec(31 downto 8); -- lsB first
end if;
end procedure;
procedure purge(file my_file : t_binary_file; rec : inout t_binary_file_rec) is
variable i : integer;
begin
if rec.offset /= 0 then
i := to_integer(unsigned(rec.long_vec));
write(my_file, i);
end if;
end procedure;
end;
| gpl-3.0 | 1631d256ceeb01c3bb93d08dc7345a9f | 0.452145 | 3.97335 | false | false | false | false |
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